; -------------------------------------------------------------------------------- ; @Title: TDA2PX On-Chip Peripherals ; @Props: Released ; @Author: KOL, STR, PIW ; @Changelog: 2018-01-25 STR ; 2022-05-11 PIW ; @Manufacturer: TI - Texas Instruments ; @Doc: XML generated (TIXML2PER 2.1.1), based on: TDA2Px.xml (Rev. 1.0) ; @Core: Cortex-A15, Cortex-M4, ARM968, C66x ; @Chip: TDA2PX, TDA2PXIPU1-CORE0, TDA2PXIPU1-CORE1, TDA2PXIPU2-CORE0, ; TDA2PXIPU2-CORE1, TDA2PXIVA1, TDA2PXIVA2, TDA2PXDSP1, TDA2PXDSP2 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: pertda2px.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif (cpuis("TDA2PX")) tree "Core Registers (Cortex-A15MPCore)" ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- width 10. tree "ID Registers" group.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..." endif rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..." rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" textline " " bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4" rgroup.long c15:0x400++0x0 line.long 0x0 "MIDR2,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x700++0x0 line.long 0x0 "MIDR3,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." endif rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..." endif rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..." bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." textline " " bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented" textline " " bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" textline " " bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented" textline " " bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented" textline " " bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented" bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented" textline " " bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented" bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented" textline " " bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented" bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented" bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" textline " " bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" textline " " bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" endif tree.end width 12. tree "System Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" textline " " bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled" bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified" bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented" bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented" textline " " bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled" bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced" bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced" bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes" textline " " bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes" bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes" bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes" textline " " bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes" bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled" bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced" textline " " bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited" bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed" bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed" textline " " bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced" bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced" bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes" textline " " bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled" bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes" bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes" textline " " bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited" bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes" bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes" bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes" bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches" textline " " bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes" textline " " bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x140F++0x00 line.long 0x0 "ACTLR2,Auxiliary Control Register 2" bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled" bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled" textline " " else hgroup.long c15:0x140F++0x00 hide.long 0x0 "ACTLR2,Auxiliary Control Register 2" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" endif group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled" bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes" textline " " bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" textline " " bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" endif group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address" textline " " rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" else hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x1609))&0x3)==0x3) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes" bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" textline " " bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x2) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" textline " " bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x1) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" textline " " bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x0) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " endif group.long c15:0x410F++0x00 line.long 0x00 "FILASTARTR,Peripheral port start address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region" bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid" group.long c15:0x420F++0x00 line.long 0x00 "FILAENDR,Peripheral port end address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") hgroup.long c15:0x1609++0x00 hide.long 0x00 "SCUCTLR,SCU Control Register" hgroup.long c15:0x410F++0x00 hide.long 0x00 "FILASTARTR,Peripheral port start address register" hgroup.long c15:0x420F++0x00 hide.long 0x00 "FILAENDR,Peripheral port end address register" endif tree.end width 12. tree "Memory Management Unit" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " endif if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes" bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High" bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes" textline " " bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1" bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7" endif textline " " group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." endif endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" else hgroup.long c15:0x0015++0x00 hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif endif group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA" hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable" bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred" textline " " bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved" textline " " bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable" bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" textline " " bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate" bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection" bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..." textline " " bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " endif if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x003A++0x00 hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x013A++0x00 hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" endif else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" textline " " bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " endif if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif textline " " if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier" hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hyp Software Thread ID Register" tree.end width 15. tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x0 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hyp Configuration Register" bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system" bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted" bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override" bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override" textline " " bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hyp Debug Control Register" bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid" textline " " bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid" textline " " bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register" bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped" textline " " bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hyp System Trap Register" bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled" bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped" textline " " bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped" bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped" bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped" textline " " bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped" bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped" bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped" textline " " bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped" bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped" bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped" textline " " bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped" bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped" bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped" textline " " bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hyp Translation Table Base Register" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hyp Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved" bitfld.long 0x00 4. " S ,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" endif group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hyp Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..." textline " " bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hyp IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits" textline " " hgroup.long c15:0x407++0x00 hide.long 0x00 "NOP,No Operation Register" in wgroup.long c15:0x17++0x00 line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x617++0x00 line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x57++0x00 line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x157++0x00 line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x457++0x00 line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x657++0x00 line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x757++0x00 line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x167++0x00 line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x267++0x00 line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write" wgroup.long c15:0x1a7++0x00 line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x2a7++0x00 line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x4a7++0x00 line.long 0x00 "CP15DSB,Data Synchronization Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x5a7++0x00 line.long 0x00 "CP15DMB,Data Memory Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x1b7++0x00 line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x1e7++0x00 line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x2e7++0x00 line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,Invalidate instruction TLB" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,Invalidate data TLB" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,Invalidate unified TLB" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" else hgroup.long c15:0x403A++0x00 hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x413A++0x00 hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" endif group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hyp Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address" tree.end width 12. tree "Cache Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..." bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..." endif group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c15:0x10EF++0x00 line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved" else hgroup.long c15:0x10EF++0x00 hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" endif tree "Level 1 memory system" width 10. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" wgroup.long c15:0x004F++0x00 line.long 0x00 "RAMINDEX,RAM Index Register" hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier" bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" textline " " group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High" bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High" bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High" textline " " bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High" bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High" hexmask.long 0x00 0.--26. 1. " TA ,Tag Address" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long 0x00 6.--30. 1. " SI ,Set index" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--15. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--16. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--17. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--18. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--19. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--20. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" else hgroup.long c15:0x314F++0x0 hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" endif if (((d.l(c15:0x324F))&0x100)==0x100) wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" else wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" endif endif tree.end tree "Level 2 memory system" width 11. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" textline " " bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid" textline " " bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle" textline " " bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191." rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes" bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes" bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced" bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced" bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled" bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes" bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes" bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes" textline " " bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes" bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled" bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes" textline " " bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes" bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes" textline " " bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled" bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes" group.long c15:0x130F++0x00 line.long 0x00 "L2PFR,L2 Prefetch Control Register" bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes" bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled" bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes" textline " " bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines" textline " " group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" hgroup.quad c15:0x110F0++0x01 hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes" rgroup.long c15:0x1609++0x00 line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register" bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1" bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location" textline " " bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA" bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid" endif tree.end tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" textline " " bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" textline " " bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes" bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes" bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes" bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes" textline " " bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed" bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled" tree.end width 12. tree "System Timer Register" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline " " bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline "" group.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" textline "" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" textline "" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" tree.end width 11. width 15. tree "Debug Registers" rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" textline " " hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") wgroup.long c14:6.++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" endif group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled" group.long c14:9.++0x0 line.long 0x00 "DBGECR,Debug Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group.long c14:32.++0x0 line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Debug Instruction Transfer Register" rgroup.long c14:33.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif endif wgroup.long c14:35.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" textline " " bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request" bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled" bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running" textline " " elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" endif rgroup.long c14:40.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..." rgroup.long c14:41.++0x0 line.long 0x00 "DBGCIDSR,DBGCIDSR" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register" bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure" bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated" hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,DBGVIDSR" endif width 15. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register" bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High" bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High" bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High" bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register" bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High" bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High" bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c14:959.++0x0 line.long 0x00 "DBGITISR,Debug Integration Input Status Register" bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High" bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High" bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " rgroup.long c14:959.++0x0 line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register" bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High" bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) rgroup.quad c14:128.++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address" bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.quad c14:256.++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" else rgroup.long c14:128.++0x0 line.long 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address" bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.long c14:256.++0x0 line.long 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" endif group.long c14:195.++0x00 line.long 0x00 "DBGOSDLR,OS Double Lock Register" bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked" else hgroup.quad c14:128.++0x1 hide.quad 0x0 "DBGDRAR,Debug ROM Address Register" hgroup.quad c14:256.++0x1 hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hgroup.long c14:195.++0x00 hide.long 0x00 "DBGOSDLR,OS Double Lock Register" endif wgroup.long c14:192.++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:193.++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..." group.long c14:196.++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High" bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset" bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High" bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High" bitfld.long 0x00 4. " HALTED ,Halted" "Low,High" textline " " bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High" bitfld.long 0x00 2. " RS ,Reset Status" "Low,High" bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High" textline " " bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High" tree "Processor ID registers" rgroup.long c14:(832.+0.)++0x00 line.long 0x00 "PIDR0,Processor ID register 0" rgroup.long c14:(832.+1.)++0x00 line.long 0x00 "PIDR1,Processor ID register 1" rgroup.long c14:(832.+2.)++0x00 line.long 0x00 "PIDR2,Processor ID register 2" rgroup.long c14:(832.+3.)++0x00 line.long 0x00 "PIDR3,Processor ID register 3" rgroup.long c14:(832.+4.)++0x00 line.long 0x00 "PIDR4,Processor ID register 4" rgroup.long c14:(832.+5.)++0x00 line.long 0x00 "PIDR5,Processor ID register 5" rgroup.long c14:(832.+6.)++0x00 line.long 0x00 "PIDR6,Processor ID register 6" rgroup.long c14:(832.+7.)++0x00 line.long 0x00 "PIDR7,Processor ID register 7" rgroup.long c14:(832.+8.)++0x00 line.long 0x00 "PIDR8,Processor ID register 8" rgroup.long c14:(832.+9.)++0x00 line.long 0x00 "PIDR9,Processor ID register 9" rgroup.long c14:(832.+10.)++0x00 line.long 0x00 "PIDR10,Processor ID register 10" rgroup.long c14:(832.+11.)++0x00 line.long 0x00 "PIDR11,Processor ID register 11" rgroup.long c14:(832.+12.)++0x00 line.long 0x00 "PIDR12,Processor ID register 12" rgroup.long c14:(832.+13.)++0x00 line.long 0x00 "PIDR13,Processor ID register 13" rgroup.long c14:(832.+14.)++0x00 line.long 0x00 "PIDR14,Processor ID register 14" rgroup.long c14:(832.+15.)++0x00 line.long 0x00 "PIDR15,Processor ID register 15" rgroup.long c14:(832.+16.)++0x00 line.long 0x00 "PIDR16,Processor ID register 16" rgroup.long c14:(832.+17.)++0x00 line.long 0x00 "PIDR17,Processor ID register 17" rgroup.long c14:(832.+18.)++0x00 line.long 0x00 "PIDR18,Processor ID register 18" rgroup.long c14:(832.+19.)++0x00 line.long 0x00 "PIDR19,Processor ID register 19" rgroup.long c14:(832.+20.)++0x00 line.long 0x00 "PIDR20,Processor ID register 20" rgroup.long c14:(832.+21.)++0x00 line.long 0x00 "PIDR21,Processor ID register 21" rgroup.long c14:(832.+22.)++0x00 line.long 0x00 "PIDR22,Processor ID register 22" rgroup.long c14:(832.+23.)++0x00 line.long 0x00 "PIDR23,Processor ID register 23" rgroup.long c14:(832.+24.)++0x00 line.long 0x00 "PIDR24,Processor ID register 24" rgroup.long c14:(832.+25.)++0x00 line.long 0x00 "PIDR25,Processor ID register 25" rgroup.long c14:(832.+26.)++0x00 line.long 0x00 "PIDR26,Processor ID register 26" rgroup.long c14:(832.+27.)++0x00 line.long 0x00 "PIDR27,Processor ID register 27" rgroup.long c14:(832.+28.)++0x00 line.long 0x00 "PIDR28,Processor ID register 28" rgroup.long c14:(832.+29.)++0x00 line.long 0x00 "PIDR29,Processor ID register 29" rgroup.long c14:(832.+30.)++0x00 line.long 0x00 "PIDR30,Processor ID register 30" rgroup.long c14:(832.+31.)++0x00 line.long 0x00 "PIDR31,Processor ID register 31" rgroup.long c14:(832.+32.)++0x00 line.long 0x00 "PIDR32,Processor ID register 32" rgroup.long c14:(832.+33.)++0x00 line.long 0x00 "PIDR33,Processor ID register 33" rgroup.long c14:(832.+34.)++0x00 line.long 0x00 "PIDR34,Processor ID register 34" rgroup.long c14:(832.+35.)++0x00 line.long 0x00 "PIDR35,Processor ID register 35" rgroup.long c14:(832.+36.)++0x00 line.long 0x00 "PIDR36,Processor ID register 36" rgroup.long c14:(832.+37.)++0x00 line.long 0x00 "PIDR37,Processor ID register 37" rgroup.long c14:(832.+38.)++0x00 line.long 0x00 "PIDR38,Processor ID register 38" rgroup.long c14:(832.+39.)++0x00 line.long 0x00 "PIDR39,Processor ID register 39" rgroup.long c14:(832.+40.)++0x00 line.long 0x00 "PIDR40,Processor ID register 40" rgroup.long c14:(832.+41.)++0x00 line.long 0x00 "PIDR41,Processor ID register 41" rgroup.long c14:(832.+42.)++0x00 line.long 0x00 "PIDR42,Processor ID register 42" rgroup.long c14:(832.+43.)++0x00 line.long 0x00 "PIDR43,Processor ID register 43" rgroup.long c14:(832.+44.)++0x00 line.long 0x00 "PIDR44,Processor ID register 44" rgroup.long c14:(832.+45.)++0x00 line.long 0x00 "PIDR45,Processor ID register 45" rgroup.long c14:(832.+46.)++0x00 line.long 0x00 "PIDR46,Processor ID register 46" rgroup.long c14:(832.+47.)++0x00 line.long 0x00 "PIDR47,Processor ID register 47" rgroup.long c14:(832.+48.)++0x00 line.long 0x00 "PIDR48,Processor ID register 48" rgroup.long c14:(832.+49.)++0x00 line.long 0x00 "PIDR49,Processor ID register 49" rgroup.long c14:(832.+50.)++0x00 line.long 0x00 "PIDR50,Processor ID register 50" rgroup.long c14:(832.+51.)++0x00 line.long 0x00 "PIDR51,Processor ID register 51" rgroup.long c14:(832.+52.)++0x00 line.long 0x00 "PIDR52,Processor ID register 52" rgroup.long c14:(832.+53.)++0x00 line.long 0x00 "PIDR53,Processor ID register 53" rgroup.long c14:(832.+54.)++0x00 line.long 0x00 "PIDR54,Processor ID register 54" rgroup.long c14:(832.+55.)++0x00 line.long 0x00 "PIDR55,Processor ID register 55" rgroup.long c14:(832.+56.)++0x00 line.long 0x00 "PIDR56,Processor ID register 56" rgroup.long c14:(832.+57.)++0x00 line.long 0x00 "PIDR57,Processor ID register 57" rgroup.long c14:(832.+58.)++0x00 line.long 0x00 "PIDR58,Processor ID register 58" rgroup.long c14:(832.+59.)++0x00 line.long 0x00 "PIDR59,Processor ID register 59" rgroup.long c14:(832.+60.)++0x00 line.long 0x00 "PIDR60,Processor ID register 60" rgroup.long c14:(832.+61.)++0x00 line.long 0x00 "PIDR61,Processor ID register 61" rgroup.long c14:(832.+62.)++0x00 line.long 0x00 "PIDR62,Processor ID register 62" rgroup.long c14:(832.+63.)++0x00 line.long 0x00 "PIDR63,Processor ID register 63" tree.end tree "Coresight Management Registers" group.long c14:960.++0x0 line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register" bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group.long c14:1000.++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set" group.long c14:1001.++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" textline " " rgroup.long c14:1006.++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" textline " " bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..." endif textline " " rgroup.long c14:1010.++0x0 line.long 0x0 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..." bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..." bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." textline " " rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Debug Device Type Register" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:1016.++0x00 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup.long c14:1017.++0x00 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup.long c14:1018.++0x00 line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup.long c14:1019.++0x00 line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup.long c14:1012.++0x00 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup.long c14:1020.++0x00 line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup.long c14:1021.++0x00 line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup.long c14:1022.++0x00 line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup.long c14:1023.++0x00 line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 10. tree "Breakpoint Registers" if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+0.)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+1.)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+2.)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+3.)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+4.)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+5.)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" group.long c14:148.++0x0 line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" group.long c14:149.++0x0 line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" tree.end width 10. tree "Watchpoint Control Registers" group.long c14:(96.+0.)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+1.)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+2.)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+3.)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif tree.end width 0xb base AD:(data.long(c15:0x400F)&0xffff8000) tree "Interrupt Controller" width 17. group.long 0x1000++0x03 "Interrupt Controller Distributor" line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global Interrupt Enable" "Disabled,Enabled" rgroup.long 0x1004++0x03 line.long 0x00 "GICD_ICTR,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "No effect,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "up to 32/0 external,up to 64/32 external,up to 96/64 external,up to 128/96 external,up to 160/128 external,up to 192/160 external,up to 224/192 external,up to 256/224 external,?..." rgroup.long 0x1008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identfication Register" hexmask.long.byte 0x00 24.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" tree "Group Registers" group.long 0x1080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" group.long 0x1084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" group.long 0x1088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" group.long 0x108C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" group.long 0x1090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" group.long 0x1094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" group.long 0x1098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" group.long 0x109C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" tree.end tree "Set-Enable Registers" group.long 0x1100++0x03 line.long 0x0 "GICD_ISER0,Interrupt Set Enable Register 0" bitfld.long 0x00 31. " SEB31 ,Set Enable Bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " SEB30 ,Set Enable Bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " SEB29 ,Set Enable Bit 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB28 ,Set Enable Bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " SEB27 ,Set Enable Bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " SEB26 ,Set Enable Bit 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB25 ,Set Enable Bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " SEB24 ,Set Enable Bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " SEB23 ,Set Enable Bit 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB22 ,Set Enable Bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " SEB21 ,Set Enable Bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " SEB20 ,Set Enable Bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB19 ,Set Enable Bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " SEB18 ,Set Enable Bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " SEB17 ,Set Enable Bit 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB16 ,Set Enable Bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " SEB15 ,Set Enable Bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " SEB14 ,Set Enable Bit 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB13 ,Set Enable Bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " SEB12 ,Set Enable Bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " SEB11 ,Set Enable Bit 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB10 ,Set Enable Bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " SEB9 ,Set Enable Bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " SEB8 ,Set Enable Bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB7 ,Set Enable Bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " SEB6 ,Set Enable Bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " SEB5 ,Set Enable Bit 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB4 ,Set Enable Bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " SEB3 ,Set Enable Bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " SEB2 ,Set Enable Bit 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB1 ,Set Enable Bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " SEB0 ,Set Enable Bit 0" "Disabled,Enabled" group.long 0x1104++0x03 line.long 0x0 "GICD_ISER1,Interrupt Set Enable Register 1" bitfld.long 0x00 31. " SEB63 ,Set Enable Bit 63" "Disabled,Enabled" bitfld.long 0x00 30. " SEB62 ,Set Enable Bit 62" "Disabled,Enabled" bitfld.long 0x00 29. " SEB61 ,Set Enable Bit 61" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB60 ,Set Enable Bit 60" "Disabled,Enabled" bitfld.long 0x00 27. " SEB59 ,Set Enable Bit 59" "Disabled,Enabled" bitfld.long 0x00 26. " SEB58 ,Set Enable Bit 58" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB57 ,Set Enable Bit 57" "Disabled,Enabled" bitfld.long 0x00 24. " SEB56 ,Set Enable Bit 56" "Disabled,Enabled" bitfld.long 0x00 23. " SEB55 ,Set Enable Bit 55" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB54 ,Set Enable Bit 54" "Disabled,Enabled" bitfld.long 0x00 21. " SEB53 ,Set Enable Bit 53" "Disabled,Enabled" bitfld.long 0x00 20. " SEB52 ,Set Enable Bit 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB51 ,Set Enable Bit 51" "Disabled,Enabled" bitfld.long 0x00 18. " SEB50 ,Set Enable Bit 50" "Disabled,Enabled" bitfld.long 0x00 17. " SEB49 ,Set Enable Bit 49" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB48 ,Set Enable Bit 48" "Disabled,Enabled" bitfld.long 0x00 15. " SEB47 ,Set Enable Bit 47" "Disabled,Enabled" bitfld.long 0x00 14. " SEB46 ,Set Enable Bit 46" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB45 ,Set Enable Bit 45" "Disabled,Enabled" bitfld.long 0x00 12. " SEB44 ,Set Enable Bit 44" "Disabled,Enabled" bitfld.long 0x00 11. " SEB43 ,Set Enable Bit 43" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB42 ,Set Enable Bit 42" "Disabled,Enabled" bitfld.long 0x00 9. " SEB41 ,Set Enable Bit 41" "Disabled,Enabled" bitfld.long 0x00 8. " SEB40 ,Set Enable Bit 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB39 ,Set Enable Bit 39" "Disabled,Enabled" bitfld.long 0x00 6. " SEB38 ,Set Enable Bit 38" "Disabled,Enabled" bitfld.long 0x00 5. " SEB37 ,Set Enable Bit 37" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB36 ,Set Enable Bit 36" "Disabled,Enabled" bitfld.long 0x00 3. " SEB35 ,Set Enable Bit 35" "Disabled,Enabled" bitfld.long 0x00 2. " SEB34 ,Set Enable Bit 34" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB33 ,Set Enable Bit 33" "Disabled,Enabled" bitfld.long 0x00 0. " SEB32 ,Set Enable Bit 32" "Disabled,Enabled" group.long 0x1108++0x03 line.long 0x0 "GICD_ISER2,Interrupt Set Enable Register 2" bitfld.long 0x00 31. " SEB95 ,Set Enable Bit 95" "Disabled,Enabled" bitfld.long 0x00 30. " SEB94 ,Set Enable Bit 94" "Disabled,Enabled" bitfld.long 0x00 29. " SEB93 ,Set Enable Bit 93" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB92 ,Set Enable Bit 92" "Disabled,Enabled" bitfld.long 0x00 27. " SEB91 ,Set Enable Bit 91" "Disabled,Enabled" bitfld.long 0x00 26. " SEB90 ,Set Enable Bit 90" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB89 ,Set Enable Bit 89" "Disabled,Enabled" bitfld.long 0x00 24. " SEB88 ,Set Enable Bit 88" "Disabled,Enabled" bitfld.long 0x00 23. " SEB87 ,Set Enable Bit 87" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB86 ,Set Enable Bit 86" "Disabled,Enabled" bitfld.long 0x00 21. " SEB85 ,Set Enable Bit 85" "Disabled,Enabled" bitfld.long 0x00 20. " SEB84 ,Set Enable Bit 84" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB83 ,Set Enable Bit 83" "Disabled,Enabled" bitfld.long 0x00 18. " SEB82 ,Set Enable Bit 82" "Disabled,Enabled" bitfld.long 0x00 17. " SEB81 ,Set Enable Bit 81" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB80 ,Set Enable Bit 80" "Disabled,Enabled" bitfld.long 0x00 15. " SEB79 ,Set Enable Bit 79" "Disabled,Enabled" bitfld.long 0x00 14. " SEB78 ,Set Enable Bit 78" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB77 ,Set Enable Bit 77" "Disabled,Enabled" bitfld.long 0x00 12. " SEB76 ,Set Enable Bit 76" "Disabled,Enabled" bitfld.long 0x00 11. " SEB75 ,Set Enable Bit 75" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB74 ,Set Enable Bit 74" "Disabled,Enabled" bitfld.long 0x00 9. " SEB73 ,Set Enable Bit 73" "Disabled,Enabled" bitfld.long 0x00 8. " SEB72 ,Set Enable Bit 72" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB71 ,Set Enable Bit 71" "Disabled,Enabled" bitfld.long 0x00 6. " SEB70 ,Set Enable Bit 70" "Disabled,Enabled" bitfld.long 0x00 5. " SEB69 ,Set Enable Bit 69" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB68 ,Set Enable Bit 68" "Disabled,Enabled" bitfld.long 0x00 3. " SEB67 ,Set Enable Bit 67" "Disabled,Enabled" bitfld.long 0x00 2. " SEB66 ,Set Enable Bit 66" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB65 ,Set Enable Bit 65" "Disabled,Enabled" bitfld.long 0x00 0. " SEB64 ,Set Enable Bit 64" "Disabled,Enabled" group.long 0x110C++0x03 line.long 0x0 "GICD_ISER3,Interrupt Set Enable Register 3" bitfld.long 0x00 31. " SEB127 ,Set Enable Bit 127" "Disabled,Enabled" bitfld.long 0x00 30. " SEB126 ,Set Enable Bit 126" "Disabled,Enabled" bitfld.long 0x00 29. " SEB125 ,Set Enable Bit 125" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB124 ,Set Enable Bit 124" "Disabled,Enabled" bitfld.long 0x00 27. " SEB123 ,Set Enable Bit 123" "Disabled,Enabled" bitfld.long 0x00 26. " SEB122 ,Set Enable Bit 122" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB121 ,Set Enable Bit 121" "Disabled,Enabled" bitfld.long 0x00 24. " SEB120 ,Set Enable Bit 120" "Disabled,Enabled" bitfld.long 0x00 23. " SEB119 ,Set Enable Bit 119" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB118 ,Set Enable Bit 118" "Disabled,Enabled" bitfld.long 0x00 21. " SEB117 ,Set Enable Bit 117" "Disabled,Enabled" bitfld.long 0x00 20. " SEB116 ,Set Enable Bit 116" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB115 ,Set Enable Bit 115" "Disabled,Enabled" bitfld.long 0x00 18. " SEB114 ,Set Enable Bit 114" "Disabled,Enabled" bitfld.long 0x00 17. " SEB113 ,Set Enable Bit 113" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB112 ,Set Enable Bit 112" "Disabled,Enabled" bitfld.long 0x00 15. " SEB111 ,Set Enable Bit 111" "Disabled,Enabled" bitfld.long 0x00 14. " SEB110 ,Set Enable Bit 110" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB109 ,Set Enable Bit 109" "Disabled,Enabled" bitfld.long 0x00 12. " SEB108 ,Set Enable Bit 108" "Disabled,Enabled" bitfld.long 0x00 11. " SEB107 ,Set Enable Bit 107" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB106 ,Set Enable Bit 106" "Disabled,Enabled" bitfld.long 0x00 9. " SEB105 ,Set Enable Bit 105" "Disabled,Enabled" bitfld.long 0x00 8. " SEB104 ,Set Enable Bit 104" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB103 ,Set Enable Bit 103" "Disabled,Enabled" bitfld.long 0x00 6. " SEB102 ,Set Enable Bit 102" "Disabled,Enabled" bitfld.long 0x00 5. " SEB101 ,Set Enable Bit 101" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB100 ,Set Enable Bit 100" "Disabled,Enabled" bitfld.long 0x00 3. " SEB99 ,Set Enable Bit 99" "Disabled,Enabled" bitfld.long 0x00 2. " SEB98 ,Set Enable Bit 98" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB97 ,Set Enable Bit 97" "Disabled,Enabled" bitfld.long 0x00 0. " SEB96 ,Set Enable Bit 96" "Disabled,Enabled" group.long 0x1110++0x03 line.long 0x0 "GICD_ISER4,Interrupt Set Enable Register 4" bitfld.long 0x00 31. " SEB159 ,Set Enable Bit 159" "Disabled,Enabled" bitfld.long 0x00 30. " SEB158 ,Set Enable Bit 158" "Disabled,Enabled" bitfld.long 0x00 29. " SEB157 ,Set Enable Bit 157" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB156 ,Set Enable Bit 156" "Disabled,Enabled" bitfld.long 0x00 27. " SEB155 ,Set Enable Bit 155" "Disabled,Enabled" bitfld.long 0x00 26. " SEB154 ,Set Enable Bit 154" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB153 ,Set Enable Bit 153" "Disabled,Enabled" bitfld.long 0x00 24. " SEB152 ,Set Enable Bit 152" "Disabled,Enabled" bitfld.long 0x00 23. " SEB151 ,Set Enable Bit 151" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB150 ,Set Enable Bit 150" "Disabled,Enabled" bitfld.long 0x00 21. " SEB149 ,Set Enable Bit 149" "Disabled,Enabled" bitfld.long 0x00 20. " SEB148 ,Set Enable Bit 148" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB147 ,Set Enable Bit 147" "Disabled,Enabled" bitfld.long 0x00 18. " SEB146 ,Set Enable Bit 146" "Disabled,Enabled" bitfld.long 0x00 17. " SEB145 ,Set Enable Bit 145" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB144 ,Set Enable Bit 144" "Disabled,Enabled" bitfld.long 0x00 15. " SEB143 ,Set Enable Bit 143" "Disabled,Enabled" bitfld.long 0x00 14. " SEB142 ,Set Enable Bit 142" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB141 ,Set Enable Bit 141" "Disabled,Enabled" bitfld.long 0x00 12. " SEB140 ,Set Enable Bit 140" "Disabled,Enabled" bitfld.long 0x00 11. " SEB139 ,Set Enable Bit 139" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB138 ,Set Enable Bit 138" "Disabled,Enabled" bitfld.long 0x00 9. " SEB137 ,Set Enable Bit 137" "Disabled,Enabled" bitfld.long 0x00 8. " SEB136 ,Set Enable Bit 136" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB135 ,Set Enable Bit 135" "Disabled,Enabled" bitfld.long 0x00 6. " SEB134 ,Set Enable Bit 134" "Disabled,Enabled" bitfld.long 0x00 5. " SEB133 ,Set Enable Bit 133" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB132 ,Set Enable Bit 132" "Disabled,Enabled" bitfld.long 0x00 3. " SEB131 ,Set Enable Bit 131" "Disabled,Enabled" bitfld.long 0x00 2. " SEB130 ,Set Enable Bit 130" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB129 ,Set Enable Bit 129" "Disabled,Enabled" bitfld.long 0x00 0. " SEB128 ,Set Enable Bit 128" "Disabled,Enabled" group.long 0x1114++0x03 line.long 0x0 "GICD_ISER5,Interrupt Set Enable Register 5" bitfld.long 0x00 31. " SEB191 ,Set Enable Bit 191" "Disabled,Enabled" bitfld.long 0x00 30. " SEB190 ,Set Enable Bit 190" "Disabled,Enabled" bitfld.long 0x00 29. " SEB189 ,Set Enable Bit 189" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB188 ,Set Enable Bit 188" "Disabled,Enabled" bitfld.long 0x00 27. " SEB187 ,Set Enable Bit 187" "Disabled,Enabled" bitfld.long 0x00 26. " SEB186 ,Set Enable Bit 186" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB185 ,Set Enable Bit 185" "Disabled,Enabled" bitfld.long 0x00 24. " SEB184 ,Set Enable Bit 184" "Disabled,Enabled" bitfld.long 0x00 23. " SEB183 ,Set Enable Bit 183" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB182 ,Set Enable Bit 182" "Disabled,Enabled" bitfld.long 0x00 21. " SEB181 ,Set Enable Bit 181" "Disabled,Enabled" bitfld.long 0x00 20. " SEB180 ,Set Enable Bit 180" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB179 ,Set Enable Bit 179" "Disabled,Enabled" bitfld.long 0x00 18. " SEB178 ,Set Enable Bit 178" "Disabled,Enabled" bitfld.long 0x00 17. " SEB177 ,Set Enable Bit 177" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB176 ,Set Enable Bit 176" "Disabled,Enabled" bitfld.long 0x00 15. " SEB175 ,Set Enable Bit 175" "Disabled,Enabled" bitfld.long 0x00 14. " SEB174 ,Set Enable Bit 174" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB173 ,Set Enable Bit 173" "Disabled,Enabled" bitfld.long 0x00 12. " SEB172 ,Set Enable Bit 172" "Disabled,Enabled" bitfld.long 0x00 11. " SEB171 ,Set Enable Bit 171" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB170 ,Set Enable Bit 170" "Disabled,Enabled" bitfld.long 0x00 9. " SEB169 ,Set Enable Bit 169" "Disabled,Enabled" bitfld.long 0x00 8. " SEB168 ,Set Enable Bit 168" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB167 ,Set Enable Bit 167" "Disabled,Enabled" bitfld.long 0x00 6. " SEB166 ,Set Enable Bit 166" "Disabled,Enabled" bitfld.long 0x00 5. " SEB165 ,Set Enable Bit 165" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB164 ,Set Enable Bit 164" "Disabled,Enabled" bitfld.long 0x00 3. " SEB163 ,Set Enable Bit 163" "Disabled,Enabled" bitfld.long 0x00 2. " SEB162 ,Set Enable Bit 162" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB161 ,Set Enable Bit 161" "Disabled,Enabled" bitfld.long 0x00 0. " SEB160 ,Set Enable Bit 160" "Disabled,Enabled" group.long 0x1118++0x03 line.long 0x0 "GICD_ISER6,Interrupt Set Enable Register 6" bitfld.long 0x00 31. " SEB223 ,Set Enable Bit 223" "Disabled,Enabled" bitfld.long 0x00 30. " SEB222 ,Set Enable Bit 222" "Disabled,Enabled" bitfld.long 0x00 29. " SEB221 ,Set Enable Bit 221" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB220 ,Set Enable Bit 220" "Disabled,Enabled" bitfld.long 0x00 27. " SEB219 ,Set Enable Bit 219" "Disabled,Enabled" bitfld.long 0x00 26. " SEB218 ,Set Enable Bit 218" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB217 ,Set Enable Bit 217" "Disabled,Enabled" bitfld.long 0x00 24. " SEB216 ,Set Enable Bit 216" "Disabled,Enabled" bitfld.long 0x00 23. " SEB215 ,Set Enable Bit 215" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB214 ,Set Enable Bit 214" "Disabled,Enabled" bitfld.long 0x00 21. " SEB213 ,Set Enable Bit 213" "Disabled,Enabled" bitfld.long 0x00 20. " SEB212 ,Set Enable Bit 212" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB211 ,Set Enable Bit 211" "Disabled,Enabled" bitfld.long 0x00 18. " SEB210 ,Set Enable Bit 210" "Disabled,Enabled" bitfld.long 0x00 17. " SEB209 ,Set Enable Bit 209" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB208 ,Set Enable Bit 208" "Disabled,Enabled" bitfld.long 0x00 15. " SEB207 ,Set Enable Bit 207" "Disabled,Enabled" bitfld.long 0x00 14. " SEB206 ,Set Enable Bit 206" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB205 ,Set Enable Bit 205" "Disabled,Enabled" bitfld.long 0x00 12. " SEB204 ,Set Enable Bit 204" "Disabled,Enabled" bitfld.long 0x00 11. " SEB203 ,Set Enable Bit 203" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB202 ,Set Enable Bit 202" "Disabled,Enabled" bitfld.long 0x00 9. " SEB201 ,Set Enable Bit 201" "Disabled,Enabled" bitfld.long 0x00 8. " SEB200 ,Set Enable Bit 200" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB199 ,Set Enable Bit 199" "Disabled,Enabled" bitfld.long 0x00 6. " SEB198 ,Set Enable Bit 198" "Disabled,Enabled" bitfld.long 0x00 5. " SEB197 ,Set Enable Bit 197" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB196 ,Set Enable Bit 196" "Disabled,Enabled" bitfld.long 0x00 3. " SEB195 ,Set Enable Bit 195" "Disabled,Enabled" bitfld.long 0x00 2. " SEB194 ,Set Enable Bit 194" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB193 ,Set Enable Bit 193" "Disabled,Enabled" bitfld.long 0x00 0. " SEB192 ,Set Enable Bit 192" "Disabled,Enabled" group.long 0x111C++0x03 line.long 0x0 "GICD_ISER7,Interrupt Set Enable Register 7" bitfld.long 0x00 31. " SEB255 ,Set Enable Bit 255" "Disabled,Enabled" bitfld.long 0x00 30. " SEB254 ,Set Enable Bit 254" "Disabled,Enabled" bitfld.long 0x00 29. " SEB253 ,Set Enable Bit 253" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB252 ,Set Enable Bit 252" "Disabled,Enabled" bitfld.long 0x00 27. " SEB251 ,Set Enable Bit 251" "Disabled,Enabled" bitfld.long 0x00 26. " SEB250 ,Set Enable Bit 250" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB249 ,Set Enable Bit 249" "Disabled,Enabled" bitfld.long 0x00 24. " SEB248 ,Set Enable Bit 248" "Disabled,Enabled" bitfld.long 0x00 23. " SEB247 ,Set Enable Bit 247" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB246 ,Set Enable Bit 246" "Disabled,Enabled" bitfld.long 0x00 21. " SEB245 ,Set Enable Bit 245" "Disabled,Enabled" bitfld.long 0x00 20. " SEB244 ,Set Enable Bit 244" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB243 ,Set Enable Bit 243" "Disabled,Enabled" bitfld.long 0x00 18. " SEB242 ,Set Enable Bit 242" "Disabled,Enabled" bitfld.long 0x00 17. " SEB241 ,Set Enable Bit 241" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB240 ,Set Enable Bit 240" "Disabled,Enabled" bitfld.long 0x00 15. " SEB239 ,Set Enable Bit 239" "Disabled,Enabled" bitfld.long 0x00 14. " SEB238 ,Set Enable Bit 238" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB237 ,Set Enable Bit 237" "Disabled,Enabled" bitfld.long 0x00 12. " SEB236 ,Set Enable Bit 236" "Disabled,Enabled" bitfld.long 0x00 11. " SEB235 ,Set Enable Bit 235" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB234 ,Set Enable Bit 234" "Disabled,Enabled" bitfld.long 0x00 9. " SEB233 ,Set Enable Bit 233" "Disabled,Enabled" bitfld.long 0x00 8. " SEB232 ,Set Enable Bit 232" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB231 ,Set Enable Bit 231" "Disabled,Enabled" bitfld.long 0x00 6. " SEB230 ,Set Enable Bit 230" "Disabled,Enabled" bitfld.long 0x00 5. " SEB229 ,Set Enable Bit 229" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB228 ,Set Enable Bit 228" "Disabled,Enabled" bitfld.long 0x00 3. " SEB227 ,Set Enable Bit 227" "Disabled,Enabled" bitfld.long 0x00 2. " SEB226 ,Set Enable Bit 226" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB225 ,Set Enable Bit 225" "Disabled,Enabled" bitfld.long 0x00 0. " SEB224 ,Set Enable Bit 224" "Disabled,Enabled" tree.end tree "Clear-Enable Registers" group.long 0x1180++0x03 line.long 0x0 "GICD_ICER0,Interrupt Clear Enable Register 0" eventfld.long 0x00 31. " CEB31 ,Clear Enable Bit 31" "Disabled,Enabled" eventfld.long 0x00 30. " CEB30 ,Clear Enable Bit 30" "Disabled,Enabled" eventfld.long 0x00 29. " CEB29 ,Clear Enable Bit 29" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB28 ,Clear Enable Bit 28" "Disabled,Enabled" eventfld.long 0x00 27. " CEB27 ,Clear Enable Bit 27" "Disabled,Enabled" eventfld.long 0x00 26. " CEB26 ,Clear Enable Bit 26" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB25 ,Clear Enable Bit 25" "Disabled,Enabled" eventfld.long 0x00 24. " CEB24 ,Clear Enable Bit 24" "Disabled,Enabled" eventfld.long 0x00 23. " CEB23 ,Clear Enable Bit 23" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB22 ,Clear Enable Bit 22" "Disabled,Enabled" eventfld.long 0x00 21. " CEB21 ,Clear Enable Bit 21" "Disabled,Enabled" eventfld.long 0x00 20. " CEB20 ,Clear Enable Bit 20" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB19 ,Clear Enable Bit 19" "Disabled,Enabled" eventfld.long 0x00 18. " CEB18 ,Clear Enable Bit 18" "Disabled,Enabled" eventfld.long 0x00 17. " CEB17 ,Clear Enable Bit 17" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB16 ,Clear Enable Bit 16" "Disabled,Enabled" eventfld.long 0x00 15. " CEB15 ,Clear Enable Bit 15" "Disabled,Enabled" eventfld.long 0x00 14. " CEB14 ,Clear Enable Bit 14" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB13 ,Clear Enable Bit 13" "Disabled,Enabled" eventfld.long 0x00 12. " CEB12 ,Clear Enable Bit 12" "Disabled,Enabled" eventfld.long 0x00 11. " CEB11 ,Clear Enable Bit 11" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB10 ,Clear Enable Bit 10" "Disabled,Enabled" eventfld.long 0x00 9. " CEB9 ,Clear Enable Bit 9" "Disabled,Enabled" eventfld.long 0x00 8. " CEB8 ,Clear Enable Bit 8" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB7 ,Clear Enable Bit 7" "Disabled,Enabled" eventfld.long 0x00 6. " CEB6 ,Clear Enable Bit 6" "Disabled,Enabled" eventfld.long 0x00 5. " CEB5 ,Clear Enable Bit 5" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB4 ,Clear Enable Bit 4" "Disabled,Enabled" eventfld.long 0x00 3. " CEB3 ,Clear Enable Bit 3" "Disabled,Enabled" eventfld.long 0x00 2. " CEB2 ,Clear Enable Bit 2" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB1 ,Clear Enable Bit 1" "Disabled,Enabled" eventfld.long 0x00 0. " CEB0 ,Clear Enable Bit 0" "Disabled,Enabled" group.long 0x1184++0x03 line.long 0x0 "GICD_ICER1,Interrupt Clear Enable Register 1" eventfld.long 0x00 31. " CEB63 ,Clear Enable Bit 63" "Disabled,Enabled" eventfld.long 0x00 30. " CEB62 ,Clear Enable Bit 62" "Disabled,Enabled" eventfld.long 0x00 29. " CEB61 ,Clear Enable Bit 61" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB60 ,Clear Enable Bit 60" "Disabled,Enabled" eventfld.long 0x00 27. " CEB59 ,Clear Enable Bit 59" "Disabled,Enabled" eventfld.long 0x00 26. " CEB58 ,Clear Enable Bit 58" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB57 ,Clear Enable Bit 57" "Disabled,Enabled" eventfld.long 0x00 24. " CEB56 ,Clear Enable Bit 56" "Disabled,Enabled" eventfld.long 0x00 23. " CEB55 ,Clear Enable Bit 55" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB54 ,Clear Enable Bit 54" "Disabled,Enabled" eventfld.long 0x00 21. " CEB53 ,Clear Enable Bit 53" "Disabled,Enabled" eventfld.long 0x00 20. " CEB52 ,Clear Enable Bit 52" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB51 ,Clear Enable Bit 51" "Disabled,Enabled" eventfld.long 0x00 18. " CEB50 ,Clear Enable Bit 50" "Disabled,Enabled" eventfld.long 0x00 17. " CEB49 ,Clear Enable Bit 49" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB48 ,Clear Enable Bit 48" "Disabled,Enabled" eventfld.long 0x00 15. " CEB47 ,Clear Enable Bit 47" "Disabled,Enabled" eventfld.long 0x00 14. " CEB46 ,Clear Enable Bit 46" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB45 ,Clear Enable Bit 45" "Disabled,Enabled" eventfld.long 0x00 12. " CEB44 ,Clear Enable Bit 44" "Disabled,Enabled" eventfld.long 0x00 11. " CEB43 ,Clear Enable Bit 43" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB42 ,Clear Enable Bit 42" "Disabled,Enabled" eventfld.long 0x00 9. " CEB41 ,Clear Enable Bit 41" "Disabled,Enabled" eventfld.long 0x00 8. " CEB40 ,Clear Enable Bit 40" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB39 ,Clear Enable Bit 39" "Disabled,Enabled" eventfld.long 0x00 6. " CEB38 ,Clear Enable Bit 38" "Disabled,Enabled" eventfld.long 0x00 5. " CEB37 ,Clear Enable Bit 37" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB36 ,Clear Enable Bit 36" "Disabled,Enabled" eventfld.long 0x00 3. " CEB35 ,Clear Enable Bit 35" "Disabled,Enabled" eventfld.long 0x00 2. " CEB34 ,Clear Enable Bit 34" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB33 ,Clear Enable Bit 33" "Disabled,Enabled" eventfld.long 0x00 0. " CEB32 ,Clear Enable Bit 32" "Disabled,Enabled" group.long 0x1188++0x03 line.long 0x0 "GICD_ICER2,Interrupt Clear Enable Register 2" eventfld.long 0x00 31. " CEB95 ,Clear Enable Bit 95" "Disabled,Enabled" eventfld.long 0x00 30. " CEB94 ,Clear Enable Bit 94" "Disabled,Enabled" eventfld.long 0x00 29. " CEB93 ,Clear Enable Bit 93" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB92 ,Clear Enable Bit 92" "Disabled,Enabled" eventfld.long 0x00 27. " CEB91 ,Clear Enable Bit 91" "Disabled,Enabled" eventfld.long 0x00 26. " CEB90 ,Clear Enable Bit 90" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB89 ,Clear Enable Bit 89" "Disabled,Enabled" eventfld.long 0x00 24. " CEB88 ,Clear Enable Bit 88" "Disabled,Enabled" eventfld.long 0x00 23. " CEB87 ,Clear Enable Bit 87" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB86 ,Clear Enable Bit 86" "Disabled,Enabled" eventfld.long 0x00 21. " CEB85 ,Clear Enable Bit 85" "Disabled,Enabled" eventfld.long 0x00 20. " CEB84 ,Clear Enable Bit 84" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB83 ,Clear Enable Bit 83" "Disabled,Enabled" eventfld.long 0x00 18. " CEB82 ,Clear Enable Bit 82" "Disabled,Enabled" eventfld.long 0x00 17. " CEB81 ,Clear Enable Bit 81" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB80 ,Clear Enable Bit 80" "Disabled,Enabled" eventfld.long 0x00 15. " CEB79 ,Clear Enable Bit 79" "Disabled,Enabled" eventfld.long 0x00 14. " CEB78 ,Clear Enable Bit 78" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB77 ,Clear Enable Bit 77" "Disabled,Enabled" eventfld.long 0x00 12. " CEB76 ,Clear Enable Bit 76" "Disabled,Enabled" eventfld.long 0x00 11. " CEB75 ,Clear Enable Bit 75" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB74 ,Clear Enable Bit 74" "Disabled,Enabled" eventfld.long 0x00 9. " CEB73 ,Clear Enable Bit 73" "Disabled,Enabled" eventfld.long 0x00 8. " CEB72 ,Clear Enable Bit 72" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB71 ,Clear Enable Bit 71" "Disabled,Enabled" eventfld.long 0x00 6. " CEB70 ,Clear Enable Bit 70" "Disabled,Enabled" eventfld.long 0x00 5. " CEB69 ,Clear Enable Bit 69" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB68 ,Clear Enable Bit 68" "Disabled,Enabled" eventfld.long 0x00 3. " CEB67 ,Clear Enable Bit 67" "Disabled,Enabled" eventfld.long 0x00 2. " CEB66 ,Clear Enable Bit 66" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB65 ,Clear Enable Bit 65" "Disabled,Enabled" eventfld.long 0x00 0. " CEB64 ,Clear Enable Bit 64" "Disabled,Enabled" group.long 0x118C++0x03 line.long 0x0 "GICD_ICER3,Interrupt Clear Enable Register 3" eventfld.long 0x00 31. " CEB127 ,Clear Enable Bit 127" "Disabled,Enabled" eventfld.long 0x00 30. " CEB126 ,Clear Enable Bit 126" "Disabled,Enabled" eventfld.long 0x00 29. " CEB125 ,Clear Enable Bit 125" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB124 ,Clear Enable Bit 124" "Disabled,Enabled" eventfld.long 0x00 27. " CEB123 ,Clear Enable Bit 123" "Disabled,Enabled" eventfld.long 0x00 26. " CEB122 ,Clear Enable Bit 122" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB121 ,Clear Enable Bit 121" "Disabled,Enabled" eventfld.long 0x00 24. " CEB120 ,Clear Enable Bit 120" "Disabled,Enabled" eventfld.long 0x00 23. " CEB119 ,Clear Enable Bit 119" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB118 ,Clear Enable Bit 118" "Disabled,Enabled" eventfld.long 0x00 21. " CEB117 ,Clear Enable Bit 117" "Disabled,Enabled" eventfld.long 0x00 20. " CEB116 ,Clear Enable Bit 116" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB115 ,Clear Enable Bit 115" "Disabled,Enabled" eventfld.long 0x00 18. " CEB114 ,Clear Enable Bit 114" "Disabled,Enabled" eventfld.long 0x00 17. " CEB113 ,Clear Enable Bit 113" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB112 ,Clear Enable Bit 112" "Disabled,Enabled" eventfld.long 0x00 15. " CEB111 ,Clear Enable Bit 111" "Disabled,Enabled" eventfld.long 0x00 14. " CEB110 ,Clear Enable Bit 110" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB109 ,Clear Enable Bit 109" "Disabled,Enabled" eventfld.long 0x00 12. " CEB108 ,Clear Enable Bit 108" "Disabled,Enabled" eventfld.long 0x00 11. " CEB107 ,Clear Enable Bit 107" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB106 ,Clear Enable Bit 106" "Disabled,Enabled" eventfld.long 0x00 9. " CEB105 ,Clear Enable Bit 105" "Disabled,Enabled" eventfld.long 0x00 8. " CEB104 ,Clear Enable Bit 104" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB103 ,Clear Enable Bit 103" "Disabled,Enabled" eventfld.long 0x00 6. " CEB102 ,Clear Enable Bit 102" "Disabled,Enabled" eventfld.long 0x00 5. " CEB101 ,Clear Enable Bit 101" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB100 ,Clear Enable Bit 100" "Disabled,Enabled" eventfld.long 0x00 3. " CEB99 ,Clear Enable Bit 99" "Disabled,Enabled" eventfld.long 0x00 2. " CEB98 ,Clear Enable Bit 98" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB97 ,Clear Enable Bit 97" "Disabled,Enabled" eventfld.long 0x00 0. " CEB96 ,Clear Enable Bit 96" "Disabled,Enabled" group.long 0x1190++0x03 line.long 0x0 "GICD_ICER4,Interrupt Clear Enable Register 4" eventfld.long 0x00 31. " CEB159 ,Clear Enable Bit 159" "Disabled,Enabled" eventfld.long 0x00 30. " CEB158 ,Clear Enable Bit 158" "Disabled,Enabled" eventfld.long 0x00 29. " CEB157 ,Clear Enable Bit 157" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB156 ,Clear Enable Bit 156" "Disabled,Enabled" eventfld.long 0x00 27. " CEB155 ,Clear Enable Bit 155" "Disabled,Enabled" eventfld.long 0x00 26. " CEB154 ,Clear Enable Bit 154" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB153 ,Clear Enable Bit 153" "Disabled,Enabled" eventfld.long 0x00 24. " CEB152 ,Clear Enable Bit 152" "Disabled,Enabled" eventfld.long 0x00 23. " CEB151 ,Clear Enable Bit 151" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB150 ,Clear Enable Bit 150" "Disabled,Enabled" eventfld.long 0x00 21. " CEB149 ,Clear Enable Bit 149" "Disabled,Enabled" eventfld.long 0x00 20. " CEB148 ,Clear Enable Bit 148" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB147 ,Clear Enable Bit 147" "Disabled,Enabled" eventfld.long 0x00 18. " CEB146 ,Clear Enable Bit 146" "Disabled,Enabled" eventfld.long 0x00 17. " CEB145 ,Clear Enable Bit 145" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB144 ,Clear Enable Bit 144" "Disabled,Enabled" eventfld.long 0x00 15. " CEB143 ,Clear Enable Bit 143" "Disabled,Enabled" eventfld.long 0x00 14. " CEB142 ,Clear Enable Bit 142" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB141 ,Clear Enable Bit 141" "Disabled,Enabled" eventfld.long 0x00 12. " CEB140 ,Clear Enable Bit 140" "Disabled,Enabled" eventfld.long 0x00 11. " CEB139 ,Clear Enable Bit 139" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB138 ,Clear Enable Bit 138" "Disabled,Enabled" eventfld.long 0x00 9. " CEB137 ,Clear Enable Bit 137" "Disabled,Enabled" eventfld.long 0x00 8. " CEB136 ,Clear Enable Bit 136" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB135 ,Clear Enable Bit 135" "Disabled,Enabled" eventfld.long 0x00 6. " CEB134 ,Clear Enable Bit 134" "Disabled,Enabled" eventfld.long 0x00 5. " CEB133 ,Clear Enable Bit 133" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB132 ,Clear Enable Bit 132" "Disabled,Enabled" eventfld.long 0x00 3. " CEB131 ,Clear Enable Bit 131" "Disabled,Enabled" eventfld.long 0x00 2. " CEB130 ,Clear Enable Bit 130" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB129 ,Clear Enable Bit 129" "Disabled,Enabled" eventfld.long 0x00 0. " CEB128 ,Clear Enable Bit 128" "Disabled,Enabled" group.long 0x1194++0x03 line.long 0x0 "GICD_ICER5,Interrupt Clear Enable Register 5" eventfld.long 0x00 31. " CEB191 ,Clear Enable Bit 191" "Disabled,Enabled" eventfld.long 0x00 30. " CEB190 ,Clear Enable Bit 190" "Disabled,Enabled" eventfld.long 0x00 29. " CEB189 ,Clear Enable Bit 189" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB188 ,Clear Enable Bit 188" "Disabled,Enabled" eventfld.long 0x00 27. " CEB187 ,Clear Enable Bit 187" "Disabled,Enabled" eventfld.long 0x00 26. " CEB186 ,Clear Enable Bit 186" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB185 ,Clear Enable Bit 185" "Disabled,Enabled" eventfld.long 0x00 24. " CEB184 ,Clear Enable Bit 184" "Disabled,Enabled" eventfld.long 0x00 23. " CEB183 ,Clear Enable Bit 183" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB182 ,Clear Enable Bit 182" "Disabled,Enabled" eventfld.long 0x00 21. " CEB181 ,Clear Enable Bit 181" "Disabled,Enabled" eventfld.long 0x00 20. " CEB180 ,Clear Enable Bit 180" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB179 ,Clear Enable Bit 179" "Disabled,Enabled" eventfld.long 0x00 18. " CEB178 ,Clear Enable Bit 178" "Disabled,Enabled" eventfld.long 0x00 17. " CEB177 ,Clear Enable Bit 177" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB176 ,Clear Enable Bit 176" "Disabled,Enabled" eventfld.long 0x00 15. " CEB175 ,Clear Enable Bit 175" "Disabled,Enabled" eventfld.long 0x00 14. " CEB174 ,Clear Enable Bit 174" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB173 ,Clear Enable Bit 173" "Disabled,Enabled" eventfld.long 0x00 12. " CEB172 ,Clear Enable Bit 172" "Disabled,Enabled" eventfld.long 0x00 11. " CEB171 ,Clear Enable Bit 171" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB170 ,Clear Enable Bit 170" "Disabled,Enabled" eventfld.long 0x00 9. " CEB169 ,Clear Enable Bit 169" "Disabled,Enabled" eventfld.long 0x00 8. " CEB168 ,Clear Enable Bit 168" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB167 ,Clear Enable Bit 167" "Disabled,Enabled" eventfld.long 0x00 6. " CEB166 ,Clear Enable Bit 166" "Disabled,Enabled" eventfld.long 0x00 5. " CEB165 ,Clear Enable Bit 165" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB164 ,Clear Enable Bit 164" "Disabled,Enabled" eventfld.long 0x00 3. " CEB163 ,Clear Enable Bit 163" "Disabled,Enabled" eventfld.long 0x00 2. " CEB162 ,Clear Enable Bit 162" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB161 ,Clear Enable Bit 161" "Disabled,Enabled" eventfld.long 0x00 0. " CEB160 ,Clear Enable Bit 160" "Disabled,Enabled" group.long 0x1198++0x03 line.long 0x0 "GICD_ICER6,Interrupt Clear Enable Register 6" eventfld.long 0x00 31. " CEB223 ,Clear Enable Bit 223" "Disabled,Enabled" eventfld.long 0x00 30. " CEB222 ,Clear Enable Bit 222" "Disabled,Enabled" eventfld.long 0x00 29. " CEB221 ,Clear Enable Bit 221" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB220 ,Clear Enable Bit 220" "Disabled,Enabled" eventfld.long 0x00 27. " CEB219 ,Clear Enable Bit 219" "Disabled,Enabled" eventfld.long 0x00 26. " CEB218 ,Clear Enable Bit 218" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB217 ,Clear Enable Bit 217" "Disabled,Enabled" eventfld.long 0x00 24. " CEB216 ,Clear Enable Bit 216" "Disabled,Enabled" eventfld.long 0x00 23. " CEB215 ,Clear Enable Bit 215" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB214 ,Clear Enable Bit 214" "Disabled,Enabled" eventfld.long 0x00 21. " CEB213 ,Clear Enable Bit 213" "Disabled,Enabled" eventfld.long 0x00 20. " CEB212 ,Clear Enable Bit 212" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB211 ,Clear Enable Bit 211" "Disabled,Enabled" eventfld.long 0x00 18. " CEB210 ,Clear Enable Bit 210" "Disabled,Enabled" eventfld.long 0x00 17. " CEB209 ,Clear Enable Bit 209" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB208 ,Clear Enable Bit 208" "Disabled,Enabled" eventfld.long 0x00 15. " CEB207 ,Clear Enable Bit 207" "Disabled,Enabled" eventfld.long 0x00 14. " CEB206 ,Clear Enable Bit 206" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB205 ,Clear Enable Bit 205" "Disabled,Enabled" eventfld.long 0x00 12. " CEB204 ,Clear Enable Bit 204" "Disabled,Enabled" eventfld.long 0x00 11. " CEB203 ,Clear Enable Bit 203" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB202 ,Clear Enable Bit 202" "Disabled,Enabled" eventfld.long 0x00 9. " CEB201 ,Clear Enable Bit 201" "Disabled,Enabled" eventfld.long 0x00 8. " CEB200 ,Clear Enable Bit 200" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB199 ,Clear Enable Bit 199" "Disabled,Enabled" eventfld.long 0x00 6. " CEB198 ,Clear Enable Bit 198" "Disabled,Enabled" eventfld.long 0x00 5. " CEB197 ,Clear Enable Bit 197" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB196 ,Clear Enable Bit 196" "Disabled,Enabled" eventfld.long 0x00 3. " CEB195 ,Clear Enable Bit 195" "Disabled,Enabled" eventfld.long 0x00 2. " CEB194 ,Clear Enable Bit 194" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB193 ,Clear Enable Bit 193" "Disabled,Enabled" eventfld.long 0x00 0. " CEB192 ,Clear Enable Bit 192" "Disabled,Enabled" group.long 0x119C++0x03 line.long 0x0 "GICD_ICER7,Interrupt Clear Enable Register 7" eventfld.long 0x00 31. " CEB255 ,Clear Enable Bit 255" "Disabled,Enabled" eventfld.long 0x00 30. " CEB254 ,Clear Enable Bit 254" "Disabled,Enabled" eventfld.long 0x00 29. " CEB253 ,Clear Enable Bit 253" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB252 ,Clear Enable Bit 252" "Disabled,Enabled" eventfld.long 0x00 27. " CEB251 ,Clear Enable Bit 251" "Disabled,Enabled" eventfld.long 0x00 26. " CEB250 ,Clear Enable Bit 250" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB249 ,Clear Enable Bit 249" "Disabled,Enabled" eventfld.long 0x00 24. " CEB248 ,Clear Enable Bit 248" "Disabled,Enabled" eventfld.long 0x00 23. " CEB247 ,Clear Enable Bit 247" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB246 ,Clear Enable Bit 246" "Disabled,Enabled" eventfld.long 0x00 21. " CEB245 ,Clear Enable Bit 245" "Disabled,Enabled" eventfld.long 0x00 20. " CEB244 ,Clear Enable Bit 244" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB243 ,Clear Enable Bit 243" "Disabled,Enabled" eventfld.long 0x00 18. " CEB242 ,Clear Enable Bit 242" "Disabled,Enabled" eventfld.long 0x00 17. " CEB241 ,Clear Enable Bit 241" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB240 ,Clear Enable Bit 240" "Disabled,Enabled" eventfld.long 0x00 15. " CEB239 ,Clear Enable Bit 239" "Disabled,Enabled" eventfld.long 0x00 14. " CEB238 ,Clear Enable Bit 238" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB237 ,Clear Enable Bit 237" "Disabled,Enabled" eventfld.long 0x00 12. " CEB236 ,Clear Enable Bit 236" "Disabled,Enabled" eventfld.long 0x00 11. " CEB235 ,Clear Enable Bit 235" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB234 ,Clear Enable Bit 234" "Disabled,Enabled" eventfld.long 0x00 9. " CEB233 ,Clear Enable Bit 233" "Disabled,Enabled" eventfld.long 0x00 8. " CEB232 ,Clear Enable Bit 232" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB231 ,Clear Enable Bit 231" "Disabled,Enabled" eventfld.long 0x00 6. " CEB230 ,Clear Enable Bit 230" "Disabled,Enabled" eventfld.long 0x00 5. " CEB229 ,Clear Enable Bit 229" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB228 ,Clear Enable Bit 228" "Disabled,Enabled" eventfld.long 0x00 3. " CEB227 ,Clear Enable Bit 227" "Disabled,Enabled" eventfld.long 0x00 2. " CEB226 ,Clear Enable Bit 226" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB225 ,Clear Enable Bit 225" "Disabled,Enabled" eventfld.long 0x00 0. " CEB224 ,Clear Enable Bit 224" "Disabled,Enabled" tree.end tree "Set-Pending Registers" group.long 0x1200++0x03 line.long 0x0 "GICD_ISPR0,Interrupt Set Pending Register 0" bitfld.long 0x00 31. " SPB31 ,Set Pending Bit 31" "Not pending,Pending" bitfld.long 0x00 30. " SPB30 ,Set Pending Bit 30" "Not pending,Pending" bitfld.long 0x00 29. " SPB29 ,Set Pending Bit 29" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB28 ,Set Pending Bit 28" "Not pending,Pending" bitfld.long 0x00 27. " SPB27 ,Set Pending Bit 27" "Not pending,Pending" bitfld.long 0x00 26. " SPB26 ,Set Pending Bit 26" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB25 ,Set Pending Bit 25" "Not pending,Pending" bitfld.long 0x00 24. " SPB24 ,Set Pending Bit 24" "Not pending,Pending" bitfld.long 0x00 23. " SPB23 ,Set Pending Bit 23" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB22 ,Set Pending Bit 22" "Not pending,Pending" bitfld.long 0x00 21. " SPB21 ,Set Pending Bit 21" "Not pending,Pending" bitfld.long 0x00 20. " SPB20 ,Set Pending Bit 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB19 ,Set Pending Bit 19" "Not pending,Pending" bitfld.long 0x00 18. " SPB18 ,Set Pending Bit 18" "Not pending,Pending" bitfld.long 0x00 17. " SPB17 ,Set Pending Bit 17" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB16 ,Set Pending Bit 16" "Not pending,Pending" bitfld.long 0x00 15. " SPB15 ,Set Pending Bit 15" "Not pending,Pending" bitfld.long 0x00 14. " SPB14 ,Set Pending Bit 14" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB13 ,Set Pending Bit 13" "Not pending,Pending" bitfld.long 0x00 12. " SPB12 ,Set Pending Bit 12" "Not pending,Pending" bitfld.long 0x00 11. " SPB11 ,Set Pending Bit 11" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB10 ,Set Pending Bit 10" "Not pending,Pending" bitfld.long 0x00 9. " SPB9 ,Set Pending Bit 9" "Not pending,Pending" bitfld.long 0x00 8. " SPB8 ,Set Pending Bit 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB7 ,Set Pending Bit 7" "Not pending,Pending" bitfld.long 0x00 6. " SPB6 ,Set Pending Bit 6" "Not pending,Pending" bitfld.long 0x00 5. " SPB5 ,Set Pending Bit 5" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB4 ,Set Pending Bit 4" "Not pending,Pending" bitfld.long 0x00 3. " SPB3 ,Set Pending Bit 3" "Not pending,Pending" bitfld.long 0x00 2. " SPB2 ,Set Pending Bit 2" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB1 ,Set Pending Bit 1" "Not pending,Pending" bitfld.long 0x00 0. " SPB0 ,Set Pending Bit 0" "Not pending,Pending" group.long 0x1204++0x03 line.long 0x0 "GICD_ISPR1,Interrupt Set Pending Register 1" bitfld.long 0x00 31. " SPB63 ,Set Pending Bit 63" "Not pending,Pending" bitfld.long 0x00 30. " SPB62 ,Set Pending Bit 62" "Not pending,Pending" bitfld.long 0x00 29. " SPB61 ,Set Pending Bit 61" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB60 ,Set Pending Bit 60" "Not pending,Pending" bitfld.long 0x00 27. " SPB59 ,Set Pending Bit 59" "Not pending,Pending" bitfld.long 0x00 26. " SPB58 ,Set Pending Bit 58" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB57 ,Set Pending Bit 57" "Not pending,Pending" bitfld.long 0x00 24. " SPB56 ,Set Pending Bit 56" "Not pending,Pending" bitfld.long 0x00 23. " SPB55 ,Set Pending Bit 55" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB54 ,Set Pending Bit 54" "Not pending,Pending" bitfld.long 0x00 21. " SPB53 ,Set Pending Bit 53" "Not pending,Pending" bitfld.long 0x00 20. " SPB52 ,Set Pending Bit 52" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB51 ,Set Pending Bit 51" "Not pending,Pending" bitfld.long 0x00 18. " SPB50 ,Set Pending Bit 50" "Not pending,Pending" bitfld.long 0x00 17. " SPB49 ,Set Pending Bit 49" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB48 ,Set Pending Bit 48" "Not pending,Pending" bitfld.long 0x00 15. " SPB47 ,Set Pending Bit 47" "Not pending,Pending" bitfld.long 0x00 14. " SPB46 ,Set Pending Bit 46" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB45 ,Set Pending Bit 45" "Not pending,Pending" bitfld.long 0x00 12. " SPB44 ,Set Pending Bit 44" "Not pending,Pending" bitfld.long 0x00 11. " SPB43 ,Set Pending Bit 43" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB42 ,Set Pending Bit 42" "Not pending,Pending" bitfld.long 0x00 9. " SPB41 ,Set Pending Bit 41" "Not pending,Pending" bitfld.long 0x00 8. " SPB40 ,Set Pending Bit 40" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB39 ,Set Pending Bit 39" "Not pending,Pending" bitfld.long 0x00 6. " SPB38 ,Set Pending Bit 38" "Not pending,Pending" bitfld.long 0x00 5. " SPB37 ,Set Pending Bit 37" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB36 ,Set Pending Bit 36" "Not pending,Pending" bitfld.long 0x00 3. " SPB35 ,Set Pending Bit 35" "Not pending,Pending" bitfld.long 0x00 2. " SPB34 ,Set Pending Bit 34" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB33 ,Set Pending Bit 33" "Not pending,Pending" bitfld.long 0x00 0. " SPB32 ,Set Pending Bit 32" "Not pending,Pending" group.long 0x1208++0x03 line.long 0x0 "GICD_ISPR2,Interrupt Set Pending Register 2" bitfld.long 0x00 31. " SPB95 ,Set Pending Bit 95" "Not pending,Pending" bitfld.long 0x00 30. " SPB94 ,Set Pending Bit 94" "Not pending,Pending" bitfld.long 0x00 29. " SPB93 ,Set Pending Bit 93" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB92 ,Set Pending Bit 92" "Not pending,Pending" bitfld.long 0x00 27. " SPB91 ,Set Pending Bit 91" "Not pending,Pending" bitfld.long 0x00 26. " SPB90 ,Set Pending Bit 90" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB89 ,Set Pending Bit 89" "Not pending,Pending" bitfld.long 0x00 24. " SPB88 ,Set Pending Bit 88" "Not pending,Pending" bitfld.long 0x00 23. " SPB87 ,Set Pending Bit 87" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB86 ,Set Pending Bit 86" "Not pending,Pending" bitfld.long 0x00 21. " SPB85 ,Set Pending Bit 85" "Not pending,Pending" bitfld.long 0x00 20. " SPB84 ,Set Pending Bit 84" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB83 ,Set Pending Bit 83" "Not pending,Pending" bitfld.long 0x00 18. " SPB82 ,Set Pending Bit 82" "Not pending,Pending" bitfld.long 0x00 17. " SPB81 ,Set Pending Bit 81" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB80 ,Set Pending Bit 80" "Not pending,Pending" bitfld.long 0x00 15. " SPB79 ,Set Pending Bit 79" "Not pending,Pending" bitfld.long 0x00 14. " SPB78 ,Set Pending Bit 78" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB77 ,Set Pending Bit 77" "Not pending,Pending" bitfld.long 0x00 12. " SPB76 ,Set Pending Bit 76" "Not pending,Pending" bitfld.long 0x00 11. " SPB75 ,Set Pending Bit 75" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB74 ,Set Pending Bit 74" "Not pending,Pending" bitfld.long 0x00 9. " SPB73 ,Set Pending Bit 73" "Not pending,Pending" bitfld.long 0x00 8. " SPB72 ,Set Pending Bit 72" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB71 ,Set Pending Bit 71" "Not pending,Pending" bitfld.long 0x00 6. " SPB70 ,Set Pending Bit 70" "Not pending,Pending" bitfld.long 0x00 5. " SPB69 ,Set Pending Bit 69" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB68 ,Set Pending Bit 68" "Not pending,Pending" bitfld.long 0x00 3. " SPB67 ,Set Pending Bit 67" "Not pending,Pending" bitfld.long 0x00 2. " SPB66 ,Set Pending Bit 66" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB65 ,Set Pending Bit 65" "Not pending,Pending" bitfld.long 0x00 0. " SPB64 ,Set Pending Bit 64" "Not pending,Pending" group.long 0x120C++0x03 line.long 0x0 "GICD_ISPR3,Interrupt Set Pending Register 3" bitfld.long 0x00 31. " SPB127 ,Set Pending Bit 127" "Not pending,Pending" bitfld.long 0x00 30. " SPB126 ,Set Pending Bit 126" "Not pending,Pending" bitfld.long 0x00 29. " SPB125 ,Set Pending Bit 125" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB124 ,Set Pending Bit 124" "Not pending,Pending" bitfld.long 0x00 27. " SPB123 ,Set Pending Bit 123" "Not pending,Pending" bitfld.long 0x00 26. " SPB122 ,Set Pending Bit 122" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB121 ,Set Pending Bit 121" "Not pending,Pending" bitfld.long 0x00 24. " SPB120 ,Set Pending Bit 120" "Not pending,Pending" bitfld.long 0x00 23. " SPB119 ,Set Pending Bit 119" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB118 ,Set Pending Bit 118" "Not pending,Pending" bitfld.long 0x00 21. " SPB117 ,Set Pending Bit 117" "Not pending,Pending" bitfld.long 0x00 20. " SPB116 ,Set Pending Bit 116" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB115 ,Set Pending Bit 115" "Not pending,Pending" bitfld.long 0x00 18. " SPB114 ,Set Pending Bit 114" "Not pending,Pending" bitfld.long 0x00 17. " SPB113 ,Set Pending Bit 113" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB112 ,Set Pending Bit 112" "Not pending,Pending" bitfld.long 0x00 15. " SPB111 ,Set Pending Bit 111" "Not pending,Pending" bitfld.long 0x00 14. " SPB110 ,Set Pending Bit 110" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB109 ,Set Pending Bit 109" "Not pending,Pending" bitfld.long 0x00 12. " SPB108 ,Set Pending Bit 108" "Not pending,Pending" bitfld.long 0x00 11. " SPB107 ,Set Pending Bit 107" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB106 ,Set Pending Bit 106" "Not pending,Pending" bitfld.long 0x00 9. " SPB105 ,Set Pending Bit 105" "Not pending,Pending" bitfld.long 0x00 8. " SPB104 ,Set Pending Bit 104" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB103 ,Set Pending Bit 103" "Not pending,Pending" bitfld.long 0x00 6. " SPB102 ,Set Pending Bit 102" "Not pending,Pending" bitfld.long 0x00 5. " SPB101 ,Set Pending Bit 101" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB100 ,Set Pending Bit 100" "Not pending,Pending" bitfld.long 0x00 3. " SPB99 ,Set Pending Bit 99" "Not pending,Pending" bitfld.long 0x00 2. " SPB98 ,Set Pending Bit 98" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB97 ,Set Pending Bit 97" "Not pending,Pending" bitfld.long 0x00 0. " SPB96 ,Set Pending Bit 96" "Not pending,Pending" group.long 0x1210++0x03 line.long 0x0 "GICD_ISPR4,Interrupt Set Pending Register 4" bitfld.long 0x00 31. " SPB159 ,Set Pending Bit 159" "Not pending,Pending" bitfld.long 0x00 30. " SPB158 ,Set Pending Bit 158" "Not pending,Pending" bitfld.long 0x00 29. " SPB157 ,Set Pending Bit 157" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB156 ,Set Pending Bit 156" "Not pending,Pending" bitfld.long 0x00 27. " SPB155 ,Set Pending Bit 155" "Not pending,Pending" bitfld.long 0x00 26. " SPB154 ,Set Pending Bit 154" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB153 ,Set Pending Bit 153" "Not pending,Pending" bitfld.long 0x00 24. " SPB152 ,Set Pending Bit 152" "Not pending,Pending" bitfld.long 0x00 23. " SPB151 ,Set Pending Bit 151" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB150 ,Set Pending Bit 150" "Not pending,Pending" bitfld.long 0x00 21. " SPB149 ,Set Pending Bit 149" "Not pending,Pending" bitfld.long 0x00 20. " SPB148 ,Set Pending Bit 148" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB147 ,Set Pending Bit 147" "Not pending,Pending" bitfld.long 0x00 18. " SPB146 ,Set Pending Bit 146" "Not pending,Pending" bitfld.long 0x00 17. " SPB145 ,Set Pending Bit 145" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB144 ,Set Pending Bit 144" "Not pending,Pending" bitfld.long 0x00 15. " SPB143 ,Set Pending Bit 143" "Not pending,Pending" bitfld.long 0x00 14. " SPB142 ,Set Pending Bit 142" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB141 ,Set Pending Bit 141" "Not pending,Pending" bitfld.long 0x00 12. " SPB140 ,Set Pending Bit 140" "Not pending,Pending" bitfld.long 0x00 11. " SPB139 ,Set Pending Bit 139" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB138 ,Set Pending Bit 138" "Not pending,Pending" bitfld.long 0x00 9. " SPB137 ,Set Pending Bit 137" "Not pending,Pending" bitfld.long 0x00 8. " SPB136 ,Set Pending Bit 136" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB135 ,Set Pending Bit 135" "Not pending,Pending" bitfld.long 0x00 6. " SPB134 ,Set Pending Bit 134" "Not pending,Pending" bitfld.long 0x00 5. " SPB133 ,Set Pending Bit 133" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB132 ,Set Pending Bit 132" "Not pending,Pending" bitfld.long 0x00 3. " SPB131 ,Set Pending Bit 131" "Not pending,Pending" bitfld.long 0x00 2. " SPB130 ,Set Pending Bit 130" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB129 ,Set Pending Bit 129" "Not pending,Pending" bitfld.long 0x00 0. " SPB128 ,Set Pending Bit 128" "Not pending,Pending" group.long 0x1214++0x03 line.long 0x0 "GICD_ISPR5,Interrupt Set Pending Register 5" bitfld.long 0x00 31. " SPB191 ,Set Pending Bit 191" "Not pending,Pending" bitfld.long 0x00 30. " SPB190 ,Set Pending Bit 190" "Not pending,Pending" bitfld.long 0x00 29. " SPB189 ,Set Pending Bit 189" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB188 ,Set Pending Bit 188" "Not pending,Pending" bitfld.long 0x00 27. " SPB187 ,Set Pending Bit 187" "Not pending,Pending" bitfld.long 0x00 26. " SPB186 ,Set Pending Bit 186" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB185 ,Set Pending Bit 185" "Not pending,Pending" bitfld.long 0x00 24. " SPB184 ,Set Pending Bit 184" "Not pending,Pending" bitfld.long 0x00 23. " SPB183 ,Set Pending Bit 183" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB182 ,Set Pending Bit 182" "Not pending,Pending" bitfld.long 0x00 21. " SPB181 ,Set Pending Bit 181" "Not pending,Pending" bitfld.long 0x00 20. " SPB180 ,Set Pending Bit 180" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB179 ,Set Pending Bit 179" "Not pending,Pending" bitfld.long 0x00 18. " SPB178 ,Set Pending Bit 178" "Not pending,Pending" bitfld.long 0x00 17. " SPB177 ,Set Pending Bit 177" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB176 ,Set Pending Bit 176" "Not pending,Pending" bitfld.long 0x00 15. " SPB175 ,Set Pending Bit 175" "Not pending,Pending" bitfld.long 0x00 14. " SPB174 ,Set Pending Bit 174" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB173 ,Set Pending Bit 173" "Not pending,Pending" bitfld.long 0x00 12. " SPB172 ,Set Pending Bit 172" "Not pending,Pending" bitfld.long 0x00 11. " SPB171 ,Set Pending Bit 171" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB170 ,Set Pending Bit 170" "Not pending,Pending" bitfld.long 0x00 9. " SPB169 ,Set Pending Bit 169" "Not pending,Pending" bitfld.long 0x00 8. " SPB168 ,Set Pending Bit 168" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB167 ,Set Pending Bit 167" "Not pending,Pending" bitfld.long 0x00 6. " SPB166 ,Set Pending Bit 166" "Not pending,Pending" bitfld.long 0x00 5. " SPB165 ,Set Pending Bit 165" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB164 ,Set Pending Bit 164" "Not pending,Pending" bitfld.long 0x00 3. " SPB163 ,Set Pending Bit 163" "Not pending,Pending" bitfld.long 0x00 2. " SPB162 ,Set Pending Bit 162" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB161 ,Set Pending Bit 161" "Not pending,Pending" bitfld.long 0x00 0. " SPB160 ,Set Pending Bit 160" "Not pending,Pending" group.long 0x1218++0x03 line.long 0x0 "GICD_ISPR6,Interrupt Set Pending Register 6" bitfld.long 0x00 31. " SPB223 ,Set Pending Bit 223" "Not pending,Pending" bitfld.long 0x00 30. " SPB222 ,Set Pending Bit 222" "Not pending,Pending" bitfld.long 0x00 29. " SPB221 ,Set Pending Bit 221" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB220 ,Set Pending Bit 220" "Not pending,Pending" bitfld.long 0x00 27. " SPB219 ,Set Pending Bit 219" "Not pending,Pending" bitfld.long 0x00 26. " SPB218 ,Set Pending Bit 218" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB217 ,Set Pending Bit 217" "Not pending,Pending" bitfld.long 0x00 24. " SPB216 ,Set Pending Bit 216" "Not pending,Pending" bitfld.long 0x00 23. " SPB215 ,Set Pending Bit 215" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB214 ,Set Pending Bit 214" "Not pending,Pending" bitfld.long 0x00 21. " SPB213 ,Set Pending Bit 213" "Not pending,Pending" bitfld.long 0x00 20. " SPB212 ,Set Pending Bit 212" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB211 ,Set Pending Bit 211" "Not pending,Pending" bitfld.long 0x00 18. " SPB210 ,Set Pending Bit 210" "Not pending,Pending" bitfld.long 0x00 17. " SPB209 ,Set Pending Bit 209" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB208 ,Set Pending Bit 208" "Not pending,Pending" bitfld.long 0x00 15. " SPB207 ,Set Pending Bit 207" "Not pending,Pending" bitfld.long 0x00 14. " SPB206 ,Set Pending Bit 206" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB205 ,Set Pending Bit 205" "Not pending,Pending" bitfld.long 0x00 12. " SPB204 ,Set Pending Bit 204" "Not pending,Pending" bitfld.long 0x00 11. " SPB203 ,Set Pending Bit 203" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB202 ,Set Pending Bit 202" "Not pending,Pending" bitfld.long 0x00 9. " SPB201 ,Set Pending Bit 201" "Not pending,Pending" bitfld.long 0x00 8. " SPB200 ,Set Pending Bit 200" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB199 ,Set Pending Bit 199" "Not pending,Pending" bitfld.long 0x00 6. " SPB198 ,Set Pending Bit 198" "Not pending,Pending" bitfld.long 0x00 5. " SPB197 ,Set Pending Bit 197" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB196 ,Set Pending Bit 196" "Not pending,Pending" bitfld.long 0x00 3. " SPB195 ,Set Pending Bit 195" "Not pending,Pending" bitfld.long 0x00 2. " SPB194 ,Set Pending Bit 194" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB193 ,Set Pending Bit 193" "Not pending,Pending" bitfld.long 0x00 0. " SPB192 ,Set Pending Bit 192" "Not pending,Pending" group.long 0x121C++0x03 line.long 0x0 "GICD_ISPR7,Interrupt Set Pending Register 7" bitfld.long 0x00 31. " SPB255 ,Set Pending Bit 255" "Not pending,Pending" bitfld.long 0x00 30. " SPB254 ,Set Pending Bit 254" "Not pending,Pending" bitfld.long 0x00 29. " SPB253 ,Set Pending Bit 253" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB252 ,Set Pending Bit 252" "Not pending,Pending" bitfld.long 0x00 27. " SPB251 ,Set Pending Bit 251" "Not pending,Pending" bitfld.long 0x00 26. " SPB250 ,Set Pending Bit 250" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB249 ,Set Pending Bit 249" "Not pending,Pending" bitfld.long 0x00 24. " SPB248 ,Set Pending Bit 248" "Not pending,Pending" bitfld.long 0x00 23. " SPB247 ,Set Pending Bit 247" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB246 ,Set Pending Bit 246" "Not pending,Pending" bitfld.long 0x00 21. " SPB245 ,Set Pending Bit 245" "Not pending,Pending" bitfld.long 0x00 20. " SPB244 ,Set Pending Bit 244" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB243 ,Set Pending Bit 243" "Not pending,Pending" bitfld.long 0x00 18. " SPB242 ,Set Pending Bit 242" "Not pending,Pending" bitfld.long 0x00 17. " SPB241 ,Set Pending Bit 241" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB240 ,Set Pending Bit 240" "Not pending,Pending" bitfld.long 0x00 15. " SPB239 ,Set Pending Bit 239" "Not pending,Pending" bitfld.long 0x00 14. " SPB238 ,Set Pending Bit 238" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB237 ,Set Pending Bit 237" "Not pending,Pending" bitfld.long 0x00 12. " SPB236 ,Set Pending Bit 236" "Not pending,Pending" bitfld.long 0x00 11. " SPB235 ,Set Pending Bit 235" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB234 ,Set Pending Bit 234" "Not pending,Pending" bitfld.long 0x00 9. " SPB233 ,Set Pending Bit 233" "Not pending,Pending" bitfld.long 0x00 8. " SPB232 ,Set Pending Bit 232" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB231 ,Set Pending Bit 231" "Not pending,Pending" bitfld.long 0x00 6. " SPB230 ,Set Pending Bit 230" "Not pending,Pending" bitfld.long 0x00 5. " SPB229 ,Set Pending Bit 229" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB228 ,Set Pending Bit 228" "Not pending,Pending" bitfld.long 0x00 3. " SPB227 ,Set Pending Bit 227" "Not pending,Pending" bitfld.long 0x00 2. " SPB226 ,Set Pending Bit 226" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB225 ,Set Pending Bit 225" "Not pending,Pending" bitfld.long 0x00 0. " SPB224 ,Set Pending Bit 224" "Not pending,Pending" textline " " tree.end tree "Clear-Pending Registers" group.long 0x1280++0x03 line.long 0x0 "GICD_ICPR0,Interrupt Clear Pending Register 0" eventfld.long 0x00 31. " CPB31 ,Clear Pending Bit 31" "Not pending,Pending" eventfld.long 0x00 30. " CPB30 ,Clear Pending Bit 30" "Not pending,Pending" eventfld.long 0x00 29. " CPB29 ,Clear Pending Bit 29" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB28 ,Clear Pending Bit 28" "Not pending,Pending" eventfld.long 0x00 27. " CPB27 ,Clear Pending Bit 27" "Not pending,Pending" eventfld.long 0x00 26. " CPB26 ,Clear Pending Bit 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB25 ,Clear Pending Bit 25" "Not pending,Pending" eventfld.long 0x00 24. " CPB24 ,Clear Pending Bit 24" "Not pending,Pending" eventfld.long 0x00 23. " CPB23 ,Clear Pending Bit 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB22 ,Clear Pending Bit 22" "Not pending,Pending" eventfld.long 0x00 21. " CPB21 ,Clear Pending Bit 21" "Not pending,Pending" eventfld.long 0x00 20. " CPB20 ,Clear Pending Bit 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB19 ,Clear Pending Bit 19" "Not pending,Pending" eventfld.long 0x00 18. " CPB18 ,Clear Pending Bit 18" "Not pending,Pending" eventfld.long 0x00 17. " CPB17 ,Clear Pending Bit 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB16 ,Clear Pending Bit 16" "Not pending,Pending" eventfld.long 0x00 15. " CPB15 ,Clear Pending Bit 15" "Not pending,Pending" eventfld.long 0x00 14. " CPB14 ,Clear Pending Bit 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB13 ,Clear Pending Bit 13" "Not pending,Pending" eventfld.long 0x00 12. " CPB12 ,Clear Pending Bit 12" "Not pending,Pending" eventfld.long 0x00 11. " CPB11 ,Clear Pending Bit 11" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB10 ,Clear Pending Bit 10" "Not pending,Pending" eventfld.long 0x00 9. " CPB9 ,Clear Pending Bit 9" "Not pending,Pending" eventfld.long 0x00 8. " CPB8 ,Clear Pending Bit 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB7 ,Clear Pending Bit 7" "Not pending,Pending" eventfld.long 0x00 6. " CPB6 ,Clear Pending Bit 6" "Not pending,Pending" eventfld.long 0x00 5. " CPB5 ,Clear Pending Bit 5" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB4 ,Clear Pending Bit 4" "Not pending,Pending" eventfld.long 0x00 3. " CPB3 ,Clear Pending Bit 3" "Not pending,Pending" eventfld.long 0x00 2. " CPB2 ,Clear Pending Bit 2" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB1 ,Clear Pending Bit 1" "Not pending,Pending" eventfld.long 0x00 0. " CPB0 ,Clear Pending Bit 0" "Not pending,Pending" group.long 0x1284++0x03 line.long 0x0 "GICD_ICPR1,Interrupt Clear Pending Register 1" eventfld.long 0x00 31. " CPB63 ,Clear Pending Bit 63" "Not pending,Pending" eventfld.long 0x00 30. " CPB62 ,Clear Pending Bit 62" "Not pending,Pending" eventfld.long 0x00 29. " CPB61 ,Clear Pending Bit 61" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB60 ,Clear Pending Bit 60" "Not pending,Pending" eventfld.long 0x00 27. " CPB59 ,Clear Pending Bit 59" "Not pending,Pending" eventfld.long 0x00 26. " CPB58 ,Clear Pending Bit 58" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB57 ,Clear Pending Bit 57" "Not pending,Pending" eventfld.long 0x00 24. " CPB56 ,Clear Pending Bit 56" "Not pending,Pending" eventfld.long 0x00 23. " CPB55 ,Clear Pending Bit 55" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB54 ,Clear Pending Bit 54" "Not pending,Pending" eventfld.long 0x00 21. " CPB53 ,Clear Pending Bit 53" "Not pending,Pending" eventfld.long 0x00 20. " CPB52 ,Clear Pending Bit 52" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB51 ,Clear Pending Bit 51" "Not pending,Pending" eventfld.long 0x00 18. " CPB50 ,Clear Pending Bit 50" "Not pending,Pending" eventfld.long 0x00 17. " CPB49 ,Clear Pending Bit 49" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB48 ,Clear Pending Bit 48" "Not pending,Pending" eventfld.long 0x00 15. " CPB47 ,Clear Pending Bit 47" "Not pending,Pending" eventfld.long 0x00 14. " CPB46 ,Clear Pending Bit 46" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB45 ,Clear Pending Bit 45" "Not pending,Pending" eventfld.long 0x00 12. " CPB44 ,Clear Pending Bit 44" "Not pending,Pending" eventfld.long 0x00 11. " CPB43 ,Clear Pending Bit 43" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB42 ,Clear Pending Bit 42" "Not pending,Pending" eventfld.long 0x00 9. " CPB41 ,Clear Pending Bit 41" "Not pending,Pending" eventfld.long 0x00 8. " CPB40 ,Clear Pending Bit 40" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB39 ,Clear Pending Bit 39" "Not pending,Pending" eventfld.long 0x00 6. " CPB38 ,Clear Pending Bit 38" "Not pending,Pending" eventfld.long 0x00 5. " CPB37 ,Clear Pending Bit 37" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB36 ,Clear Pending Bit 36" "Not pending,Pending" eventfld.long 0x00 3. " CPB35 ,Clear Pending Bit 35" "Not pending,Pending" eventfld.long 0x00 2. " CPB34 ,Clear Pending Bit 34" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB33 ,Clear Pending Bit 33" "Not pending,Pending" eventfld.long 0x00 0. " CPB32 ,Clear Pending Bit 32" "Not pending,Pending" group.long 0x1288++0x03 line.long 0x0 "GICD_ICPR2,Interrupt Clear Pending Register 2" eventfld.long 0x00 31. " CPB95 ,Clear Pending Bit 95" "Not pending,Pending" eventfld.long 0x00 30. " CPB94 ,Clear Pending Bit 94" "Not pending,Pending" eventfld.long 0x00 29. " CPB93 ,Clear Pending Bit 93" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB92 ,Clear Pending Bit 92" "Not pending,Pending" eventfld.long 0x00 27. " CPB91 ,Clear Pending Bit 91" "Not pending,Pending" eventfld.long 0x00 26. " CPB90 ,Clear Pending Bit 90" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB89 ,Clear Pending Bit 89" "Not pending,Pending" eventfld.long 0x00 24. " CPB88 ,Clear Pending Bit 88" "Not pending,Pending" eventfld.long 0x00 23. " CPB87 ,Clear Pending Bit 87" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB86 ,Clear Pending Bit 86" "Not pending,Pending" eventfld.long 0x00 21. " CPB85 ,Clear Pending Bit 85" "Not pending,Pending" eventfld.long 0x00 20. " CPB84 ,Clear Pending Bit 84" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB83 ,Clear Pending Bit 83" "Not pending,Pending" eventfld.long 0x00 18. " CPB82 ,Clear Pending Bit 82" "Not pending,Pending" eventfld.long 0x00 17. " CPB81 ,Clear Pending Bit 81" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB80 ,Clear Pending Bit 80" "Not pending,Pending" eventfld.long 0x00 15. " CPB79 ,Clear Pending Bit 79" "Not pending,Pending" eventfld.long 0x00 14. " CPB78 ,Clear Pending Bit 78" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB77 ,Clear Pending Bit 77" "Not pending,Pending" eventfld.long 0x00 12. " CPB76 ,Clear Pending Bit 76" "Not pending,Pending" eventfld.long 0x00 11. " CPB75 ,Clear Pending Bit 75" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB74 ,Clear Pending Bit 74" "Not pending,Pending" eventfld.long 0x00 9. " CPB73 ,Clear Pending Bit 73" "Not pending,Pending" eventfld.long 0x00 8. " CPB72 ,Clear Pending Bit 72" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB71 ,Clear Pending Bit 71" "Not pending,Pending" eventfld.long 0x00 6. " CPB70 ,Clear Pending Bit 70" "Not pending,Pending" eventfld.long 0x00 5. " CPB69 ,Clear Pending Bit 69" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB68 ,Clear Pending Bit 68" "Not pending,Pending" eventfld.long 0x00 3. " CPB67 ,Clear Pending Bit 67" "Not pending,Pending" eventfld.long 0x00 2. " CPB66 ,Clear Pending Bit 66" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB65 ,Clear Pending Bit 65" "Not pending,Pending" eventfld.long 0x00 0. " CPB64 ,Clear Pending Bit 64" "Not pending,Pending" group.long 0x128C++0x03 line.long 0x0 "GICD_ICPR3,Interrupt Clear Pending Register 3" eventfld.long 0x00 31. " CPB127 ,Clear Pending Bit 127" "Not pending,Pending" eventfld.long 0x00 30. " CPB126 ,Clear Pending Bit 126" "Not pending,Pending" eventfld.long 0x00 29. " CPB125 ,Clear Pending Bit 125" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB124 ,Clear Pending Bit 124" "Not pending,Pending" eventfld.long 0x00 27. " CPB123 ,Clear Pending Bit 123" "Not pending,Pending" eventfld.long 0x00 26. " CPB122 ,Clear Pending Bit 122" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB121 ,Clear Pending Bit 121" "Not pending,Pending" eventfld.long 0x00 24. " CPB120 ,Clear Pending Bit 120" "Not pending,Pending" eventfld.long 0x00 23. " CPB119 ,Clear Pending Bit 119" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB118 ,Clear Pending Bit 118" "Not pending,Pending" eventfld.long 0x00 21. " CPB117 ,Clear Pending Bit 117" "Not pending,Pending" eventfld.long 0x00 20. " CPB116 ,Clear Pending Bit 116" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB115 ,Clear Pending Bit 115" "Not pending,Pending" eventfld.long 0x00 18. " CPB114 ,Clear Pending Bit 114" "Not pending,Pending" eventfld.long 0x00 17. " CPB113 ,Clear Pending Bit 113" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB112 ,Clear Pending Bit 112" "Not pending,Pending" eventfld.long 0x00 15. " CPB111 ,Clear Pending Bit 111" "Not pending,Pending" eventfld.long 0x00 14. " CPB110 ,Clear Pending Bit 110" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB109 ,Clear Pending Bit 109" "Not pending,Pending" eventfld.long 0x00 12. " CPB108 ,Clear Pending Bit 108" "Not pending,Pending" eventfld.long 0x00 11. " CPB107 ,Clear Pending Bit 107" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB106 ,Clear Pending Bit 106" "Not pending,Pending" eventfld.long 0x00 9. " CPB105 ,Clear Pending Bit 105" "Not pending,Pending" eventfld.long 0x00 8. " CPB104 ,Clear Pending Bit 104" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB103 ,Clear Pending Bit 103" "Not pending,Pending" eventfld.long 0x00 6. " CPB102 ,Clear Pending Bit 102" "Not pending,Pending" eventfld.long 0x00 5. " CPB101 ,Clear Pending Bit 101" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB100 ,Clear Pending Bit 100" "Not pending,Pending" eventfld.long 0x00 3. " CPB99 ,Clear Pending Bit 99" "Not pending,Pending" eventfld.long 0x00 2. " CPB98 ,Clear Pending Bit 98" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB97 ,Clear Pending Bit 97" "Not pending,Pending" eventfld.long 0x00 0. " CPB96 ,Clear Pending Bit 96" "Not pending,Pending" group.long 0x1290++0x03 line.long 0x0 "GICD_ICPR4,Interrupt Clear Pending Register 4" eventfld.long 0x00 31. " CPB159 ,Clear Pending Bit 159" "Not pending,Pending" eventfld.long 0x00 30. " CPB158 ,Clear Pending Bit 158" "Not pending,Pending" eventfld.long 0x00 29. " CPB157 ,Clear Pending Bit 157" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB156 ,Clear Pending Bit 156" "Not pending,Pending" eventfld.long 0x00 27. " CPB155 ,Clear Pending Bit 155" "Not pending,Pending" eventfld.long 0x00 26. " CPB154 ,Clear Pending Bit 154" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB153 ,Clear Pending Bit 153" "Not pending,Pending" eventfld.long 0x00 24. " CPB152 ,Clear Pending Bit 152" "Not pending,Pending" eventfld.long 0x00 23. " CPB151 ,Clear Pending Bit 151" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB150 ,Clear Pending Bit 150" "Not pending,Pending" eventfld.long 0x00 21. " CPB149 ,Clear Pending Bit 149" "Not pending,Pending" eventfld.long 0x00 20. " CPB148 ,Clear Pending Bit 148" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB147 ,Clear Pending Bit 147" "Not pending,Pending" eventfld.long 0x00 18. " CPB146 ,Clear Pending Bit 146" "Not pending,Pending" eventfld.long 0x00 17. " CPB145 ,Clear Pending Bit 145" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB144 ,Clear Pending Bit 144" "Not pending,Pending" eventfld.long 0x00 15. " CPB143 ,Clear Pending Bit 143" "Not pending,Pending" eventfld.long 0x00 14. " CPB142 ,Clear Pending Bit 142" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB141 ,Clear Pending Bit 141" "Not pending,Pending" eventfld.long 0x00 12. " CPB140 ,Clear Pending Bit 140" "Not pending,Pending" eventfld.long 0x00 11. " CPB139 ,Clear Pending Bit 139" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB138 ,Clear Pending Bit 138" "Not pending,Pending" eventfld.long 0x00 9. " CPB137 ,Clear Pending Bit 137" "Not pending,Pending" eventfld.long 0x00 8. " CPB136 ,Clear Pending Bit 136" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB135 ,Clear Pending Bit 135" "Not pending,Pending" eventfld.long 0x00 6. " CPB134 ,Clear Pending Bit 134" "Not pending,Pending" eventfld.long 0x00 5. " CPB133 ,Clear Pending Bit 133" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB132 ,Clear Pending Bit 132" "Not pending,Pending" eventfld.long 0x00 3. " CPB131 ,Clear Pending Bit 131" "Not pending,Pending" eventfld.long 0x00 2. " CPB130 ,Clear Pending Bit 130" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB129 ,Clear Pending Bit 129" "Not pending,Pending" eventfld.long 0x00 0. " CPB128 ,Clear Pending Bit 128" "Not pending,Pending" group.long 0x1294++0x03 line.long 0x0 "GICD_ICPR5,Interrupt Clear Pending Register 5" eventfld.long 0x00 31. " CPB191 ,Clear Pending Bit 191" "Not pending,Pending" eventfld.long 0x00 30. " CPB190 ,Clear Pending Bit 190" "Not pending,Pending" eventfld.long 0x00 29. " CPB189 ,Clear Pending Bit 189" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB188 ,Clear Pending Bit 188" "Not pending,Pending" eventfld.long 0x00 27. " CPB187 ,Clear Pending Bit 187" "Not pending,Pending" eventfld.long 0x00 26. " CPB186 ,Clear Pending Bit 186" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB185 ,Clear Pending Bit 185" "Not pending,Pending" eventfld.long 0x00 24. " CPB184 ,Clear Pending Bit 184" "Not pending,Pending" eventfld.long 0x00 23. " CPB183 ,Clear Pending Bit 183" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB182 ,Clear Pending Bit 182" "Not pending,Pending" eventfld.long 0x00 21. " CPB181 ,Clear Pending Bit 181" "Not pending,Pending" eventfld.long 0x00 20. " CPB180 ,Clear Pending Bit 180" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB179 ,Clear Pending Bit 179" "Not pending,Pending" eventfld.long 0x00 18. " CPB178 ,Clear Pending Bit 178" "Not pending,Pending" eventfld.long 0x00 17. " CPB177 ,Clear Pending Bit 177" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB176 ,Clear Pending Bit 176" "Not pending,Pending" eventfld.long 0x00 15. " CPB175 ,Clear Pending Bit 175" "Not pending,Pending" eventfld.long 0x00 14. " CPB174 ,Clear Pending Bit 174" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB173 ,Clear Pending Bit 173" "Not pending,Pending" eventfld.long 0x00 12. " CPB172 ,Clear Pending Bit 172" "Not pending,Pending" eventfld.long 0x00 11. " CPB171 ,Clear Pending Bit 171" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB170 ,Clear Pending Bit 170" "Not pending,Pending" eventfld.long 0x00 9. " CPB169 ,Clear Pending Bit 169" "Not pending,Pending" eventfld.long 0x00 8. " CPB168 ,Clear Pending Bit 168" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB167 ,Clear Pending Bit 167" "Not pending,Pending" eventfld.long 0x00 6. " CPB166 ,Clear Pending Bit 166" "Not pending,Pending" eventfld.long 0x00 5. " CPB165 ,Clear Pending Bit 165" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB164 ,Clear Pending Bit 164" "Not pending,Pending" eventfld.long 0x00 3. " CPB163 ,Clear Pending Bit 163" "Not pending,Pending" eventfld.long 0x00 2. " CPB162 ,Clear Pending Bit 162" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB161 ,Clear Pending Bit 161" "Not pending,Pending" eventfld.long 0x00 0. " CPB160 ,Clear Pending Bit 160" "Not pending,Pending" group.long 0x1298++0x03 line.long 0x0 "GICD_ICPR6,Interrupt Clear Pending Register 6" eventfld.long 0x00 31. " CPB223 ,Clear Pending Bit 223" "Not pending,Pending" eventfld.long 0x00 30. " CPB222 ,Clear Pending Bit 222" "Not pending,Pending" eventfld.long 0x00 29. " CPB221 ,Clear Pending Bit 221" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB220 ,Clear Pending Bit 220" "Not pending,Pending" eventfld.long 0x00 27. " CPB219 ,Clear Pending Bit 219" "Not pending,Pending" eventfld.long 0x00 26. " CPB218 ,Clear Pending Bit 218" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB217 ,Clear Pending Bit 217" "Not pending,Pending" eventfld.long 0x00 24. " CPB216 ,Clear Pending Bit 216" "Not pending,Pending" eventfld.long 0x00 23. " CPB215 ,Clear Pending Bit 215" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB214 ,Clear Pending Bit 214" "Not pending,Pending" eventfld.long 0x00 21. " CPB213 ,Clear Pending Bit 213" "Not pending,Pending" eventfld.long 0x00 20. " CPB212 ,Clear Pending Bit 212" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB211 ,Clear Pending Bit 211" "Not pending,Pending" eventfld.long 0x00 18. " CPB210 ,Clear Pending Bit 210" "Not pending,Pending" eventfld.long 0x00 17. " CPB209 ,Clear Pending Bit 209" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB208 ,Clear Pending Bit 208" "Not pending,Pending" eventfld.long 0x00 15. " CPB207 ,Clear Pending Bit 207" "Not pending,Pending" eventfld.long 0x00 14. " CPB206 ,Clear Pending Bit 206" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB205 ,Clear Pending Bit 205" "Not pending,Pending" eventfld.long 0x00 12. " CPB204 ,Clear Pending Bit 204" "Not pending,Pending" eventfld.long 0x00 11. " CPB203 ,Clear Pending Bit 203" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB202 ,Clear Pending Bit 202" "Not pending,Pending" eventfld.long 0x00 9. " CPB201 ,Clear Pending Bit 201" "Not pending,Pending" eventfld.long 0x00 8. " CPB200 ,Clear Pending Bit 200" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB199 ,Clear Pending Bit 199" "Not pending,Pending" eventfld.long 0x00 6. " CPB198 ,Clear Pending Bit 198" "Not pending,Pending" eventfld.long 0x00 5. " CPB197 ,Clear Pending Bit 197" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB196 ,Clear Pending Bit 196" "Not pending,Pending" eventfld.long 0x00 3. " CPB195 ,Clear Pending Bit 195" "Not pending,Pending" eventfld.long 0x00 2. " CPB194 ,Clear Pending Bit 194" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB193 ,Clear Pending Bit 193" "Not pending,Pending" eventfld.long 0x00 0. " CPB192 ,Clear Pending Bit 192" "Not pending,Pending" group.long 0x129C++0x03 line.long 0x0 "GICD_ICPR7,Interrupt Clear Pending Register 7" eventfld.long 0x00 31. " CPB255 ,Clear Pending Bit 255" "Not pending,Pending" eventfld.long 0x00 30. " CPB254 ,Clear Pending Bit 254" "Not pending,Pending" eventfld.long 0x00 29. " CPB253 ,Clear Pending Bit 253" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB252 ,Clear Pending Bit 252" "Not pending,Pending" eventfld.long 0x00 27. " CPB251 ,Clear Pending Bit 251" "Not pending,Pending" eventfld.long 0x00 26. " CPB250 ,Clear Pending Bit 250" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB249 ,Clear Pending Bit 249" "Not pending,Pending" eventfld.long 0x00 24. " CPB248 ,Clear Pending Bit 248" "Not pending,Pending" eventfld.long 0x00 23. " CPB247 ,Clear Pending Bit 247" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB246 ,Clear Pending Bit 246" "Not pending,Pending" eventfld.long 0x00 21. " CPB245 ,Clear Pending Bit 245" "Not pending,Pending" eventfld.long 0x00 20. " CPB244 ,Clear Pending Bit 244" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB243 ,Clear Pending Bit 243" "Not pending,Pending" eventfld.long 0x00 18. " CPB242 ,Clear Pending Bit 242" "Not pending,Pending" eventfld.long 0x00 17. " CPB241 ,Clear Pending Bit 241" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB240 ,Clear Pending Bit 240" "Not pending,Pending" eventfld.long 0x00 15. " CPB239 ,Clear Pending Bit 239" "Not pending,Pending" eventfld.long 0x00 14. " CPB238 ,Clear Pending Bit 238" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB237 ,Clear Pending Bit 237" "Not pending,Pending" eventfld.long 0x00 12. " CPB236 ,Clear Pending Bit 236" "Not pending,Pending" eventfld.long 0x00 11. " CPB235 ,Clear Pending Bit 235" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB234 ,Clear Pending Bit 234" "Not pending,Pending" eventfld.long 0x00 9. " CPB233 ,Clear Pending Bit 233" "Not pending,Pending" eventfld.long 0x00 8. " CPB232 ,Clear Pending Bit 232" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB231 ,Clear Pending Bit 231" "Not pending,Pending" eventfld.long 0x00 6. " CPB230 ,Clear Pending Bit 230" "Not pending,Pending" eventfld.long 0x00 5. " CPB229 ,Clear Pending Bit 229" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB228 ,Clear Pending Bit 228" "Not pending,Pending" eventfld.long 0x00 3. " CPB227 ,Clear Pending Bit 227" "Not pending,Pending" eventfld.long 0x00 2. " CPB226 ,Clear Pending Bit 226" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB225 ,Clear Pending Bit 225" "Not pending,Pending" eventfld.long 0x00 0. " CPB224 ,Clear Pending Bit 224" "Not pending,Pending" textline " " tree.end tree "Set/Clear Active Registers" group.long 0x1300++0x03 line.long 0x0 "GICD_ISACTIVER0,Interrupt Set Active Register 0" group.long 0x1304++0x03 line.long 0x0 "GICD_ISACTIVER1,Interrupt Set Active Register 1" group.long 0x1308++0x03 line.long 0x0 "GICD_ISACTIVER2,Interrupt Set Active Register 2" group.long 0x130C++0x03 line.long 0x0 "GICD_ISACTIVER3,Interrupt Set Active Register 3" group.long 0x1310++0x03 line.long 0x0 "GICD_ISACTIVER4,Interrupt Set Active Register 4" group.long 0x1314++0x03 line.long 0x0 "GICD_ISACTIVER5,Interrupt Set Active Register 5" group.long 0x1318++0x03 line.long 0x0 "GICD_ISACTIVER6,Interrupt Set Active Register 6" group.long 0x131C++0x03 line.long 0x0 "GICD_ISACTIVER7,Interrupt Set Active Register 7" textline " " group.long 0x1380++0x03 line.long 0x0 "GICD_ICACTIVER0,Interrupt Clear Active Register 0" group.long 0x1384++0x03 line.long 0x0 "GICD_ICACTIVER1,Interrupt Clear Active Register 1" group.long 0x1388++0x03 line.long 0x0 "GICD_ICACTIVER2,Interrupt Clear Active Register 2" group.long 0x138C++0x03 line.long 0x0 "GICD_ICACTIVER3,Interrupt Clear Active Register 3" group.long 0x1390++0x03 line.long 0x0 "GICD_ICACTIVER4,Interrupt Clear Active Register 4" group.long 0x1394++0x03 line.long 0x0 "GICD_ICACTIVER5,Interrupt Clear Active Register 5" group.long 0x1398++0x03 line.long 0x0 "GICD_ICACTIVER6,Interrupt Clear Active Register 6" group.long 0x139C++0x03 line.long 0x0 "GICD_ICACTIVER7,Interrupt Clear Active Register 7" textline " " tree.end tree "Priority Registers" group.long 0x1400++0x03 line.long 0x0 "GICD_IPR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1404++0x03 line.long 0x0 "GICD_IPR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1408++0x03 line.long 0x0 "GICD_IPR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x140C++0x03 line.long 0x0 "GICD_IPR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1410++0x03 line.long 0x0 "GICD_IPR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1414++0x03 line.long 0x0 "GICD_IPR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1418++0x03 line.long 0x0 "GICD_IPR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x141C++0x03 line.long 0x0 "GICD_IPR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1420++0x03 line.long 0x0 "GICD_IPR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1424++0x03 line.long 0x0 "GICD_IPR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1428++0x03 line.long 0x0 "GICD_IPR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x142C++0x03 line.long 0x0 "GICD_IPR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1430++0x03 line.long 0x0 "GICD_IPR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1434++0x03 line.long 0x0 "GICD_IPR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1438++0x03 line.long 0x0 "GICD_IPR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x143C++0x03 line.long 0x0 "GICD_IPR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1440++0x03 line.long 0x0 "GICD_IPR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1444++0x03 line.long 0x0 "GICD_IPR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1448++0x03 line.long 0x0 "GICD_IPR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x144C++0x03 line.long 0x0 "GICD_IPR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1450++0x03 line.long 0x0 "GICD_IPR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1454++0x03 line.long 0x0 "GICD_IPR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1458++0x03 line.long 0x0 "GICD_IPR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x145C++0x03 line.long 0x0 "GICD_IPR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1460++0x03 line.long 0x0 "GICD_IPR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1464++0x03 line.long 0x0 "GICD_IPR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1468++0x03 line.long 0x0 "GICD_IPR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x146C++0x03 line.long 0x0 "GICD_IPR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1470++0x03 line.long 0x0 "GICD_IPR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1474++0x03 line.long 0x0 "GICD_IPR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1478++0x03 line.long 0x0 "GICD_IPR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x147C++0x03 line.long 0x0 "GICD_IPR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1480++0x03 line.long 0x0 "GICD_IPR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1484++0x03 line.long 0x0 "GICD_IPR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1488++0x03 line.long 0x0 "GICD_IPR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x148C++0x03 line.long 0x0 "GICD_IPR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1490++0x03 line.long 0x0 "GICD_IPR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1494++0x03 line.long 0x0 "GICD_IPR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1498++0x03 line.long 0x0 "GICD_IPR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x149C++0x03 line.long 0x0 "GICD_IPR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A0++0x03 line.long 0x0 "GICD_IPR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A4++0x03 line.long 0x0 "GICD_IPR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A8++0x03 line.long 0x0 "GICD_IPR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14AC++0x03 line.long 0x0 "GICD_IPR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B0++0x03 line.long 0x0 "GICD_IPR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B4++0x03 line.long 0x0 "GICD_IPR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B8++0x03 line.long 0x0 "GICD_IPR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14BC++0x03 line.long 0x0 "GICD_IPR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C0++0x03 line.long 0x0 "GICD_IPR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C4++0x03 line.long 0x0 "GICD_IPR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C8++0x03 line.long 0x0 "GICD_IPR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14CC++0x03 line.long 0x0 "GICD_IPR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D0++0x03 line.long 0x0 "GICD_IPR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D4++0x03 line.long 0x0 "GICD_IPR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D8++0x03 line.long 0x0 "GICD_IPR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14DC++0x03 line.long 0x0 "GICD_IPR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E0++0x03 line.long 0x0 "GICD_IPR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E4++0x03 line.long 0x0 "GICD_IPR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E8++0x03 line.long 0x0 "GICD_IPR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14EC++0x03 line.long 0x0 "GICD_IPR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F0++0x03 line.long 0x0 "GICD_IPR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F4++0x03 line.long 0x0 "GICD_IPR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F8++0x03 line.long 0x0 "GICD_IPR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14FC++0x03 line.long 0x0 "GICD_IPR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" textline " " tree.end tree "Processor Targets Registers" rgroup.long 0x1800++0x03 line.long 0x0 "GICD_IPTR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1804++0x03 line.long 0x0 "GICD_IPTR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1808++0x03 line.long 0x0 "GICD_IPTR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x180C++0x03 line.long 0x0 "GICD_IPTR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1810++0x03 line.long 0x0 "GICD_IPTR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1814++0x03 line.long 0x0 "GICD_IPTR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1818++0x03 line.long 0x0 "GICD_IPTR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x181C++0x03 line.long 0x0 "GICD_IPTR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1820++0x03 line.long 0x0 "GICD_IPTR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1824++0x03 line.long 0x0 "GICD_IPTR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1828++0x03 line.long 0x0 "GICD_IPTR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x182C++0x03 line.long 0x0 "GICD_IPTR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1830++0x03 line.long 0x0 "GICD_IPTR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1834++0x03 line.long 0x0 "GICD_IPTR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1838++0x03 line.long 0x0 "GICD_IPTR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x183C++0x03 line.long 0x0 "GICD_IPTR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1840++0x03 line.long 0x0 "GICD_IPTR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1844++0x03 line.long 0x0 "GICD_IPTR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1848++0x03 line.long 0x0 "GICD_IPTR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x184C++0x03 line.long 0x0 "GICD_IPTR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1850++0x03 line.long 0x0 "GICD_IPTR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1854++0x03 line.long 0x0 "GICD_IPTR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1858++0x03 line.long 0x0 "GICD_IPTR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x185C++0x03 line.long 0x0 "GICD_IPTR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1860++0x03 line.long 0x0 "GICD_IPTR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1864++0x03 line.long 0x0 "GICD_IPTR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1868++0x03 line.long 0x0 "GICD_IPTR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x186C++0x03 line.long 0x0 "GICD_IPTR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1870++0x03 line.long 0x0 "GICD_IPTR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1874++0x03 line.long 0x0 "GICD_IPTR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1878++0x03 line.long 0x0 "GICD_IPTR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x187C++0x03 line.long 0x0 "GICD_IPTR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1880++0x03 line.long 0x0 "GICD_IPTR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1884++0x03 line.long 0x0 "GICD_IPTR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1888++0x03 line.long 0x0 "GICD_IPTR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x188C++0x03 line.long 0x0 "GICD_IPTR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1890++0x03 line.long 0x0 "GICD_IPTR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1894++0x03 line.long 0x0 "GICD_IPTR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1898++0x03 line.long 0x0 "GICD_IPTR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x189C++0x03 line.long 0x0 "GICD_IPTR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A0++0x03 line.long 0x0 "GICD_IPTR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A4++0x03 line.long 0x0 "GICD_IPTR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A8++0x03 line.long 0x0 "GICD_IPTR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18AC++0x03 line.long 0x0 "GICD_IPTR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B0++0x03 line.long 0x0 "GICD_IPTR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B4++0x03 line.long 0x0 "GICD_IPTR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B8++0x03 line.long 0x0 "GICD_IPTR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18BC++0x03 line.long 0x0 "GICD_IPTR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C0++0x03 line.long 0x0 "GICD_IPTR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C4++0x03 line.long 0x0 "GICD_IPTR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C8++0x03 line.long 0x0 "GICD_IPTR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18CC++0x03 line.long 0x0 "GICD_IPTR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D0++0x03 line.long 0x0 "GICD_IPTR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D4++0x03 line.long 0x0 "GICD_IPTR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D8++0x03 line.long 0x0 "GICD_IPTR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18DC++0x03 line.long 0x0 "GICD_IPTR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E0++0x03 line.long 0x0 "GICD_IPTR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E4++0x03 line.long 0x0 "GICD_IPTR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E8++0x03 line.long 0x0 "GICD_IPTR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18EC++0x03 line.long 0x0 "GICD_IPTR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F0++0x03 line.long 0x0 "GICD_IPTR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F4++0x03 line.long 0x0 "GICD_IPTR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F8++0x03 line.long 0x0 "GICD_IPTR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18FC++0x03 line.long 0x0 "GICD_IPTR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" textline " " tree.end tree "Configuration Registers" rgroup.long 0x1C00++0x03 line.long 0x00 "GICD_ICFR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" rgroup.long 0x1C04++0x03 line.long 0x00 "GICD_ICFR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C08++0x03 line.long 0x00 "GICD_ICFR2,Interrupt Configuration Register 0x1C08" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C0C++0x03 line.long 0x00 "GICD_ICFR3,Interrupt Configuration Register 0x1C0C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C10++0x03 line.long 0x00 "GICD_ICFR4,Interrupt Configuration Register 0x1C10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C14++0x03 line.long 0x00 "GICD_ICFR5,Interrupt Configuration Register 0x1C14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C18++0x03 line.long 0x00 "GICD_ICFR6,Interrupt Configuration Register 0x1C18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C1C++0x03 line.long 0x00 "GICD_ICFR7,Interrupt Configuration Register 0x1C1C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C20++0x03 line.long 0x00 "GICD_ICFR8,Interrupt Configuration Register 0x1C20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C24++0x03 line.long 0x00 "GICD_ICFR9,Interrupt Configuration Register 0x1C24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C28++0x03 line.long 0x00 "GICD_ICFR10,Interrupt Configuration Register 0x1C28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C2C++0x03 line.long 0x00 "GICD_ICFR11,Interrupt Configuration Register 0x1C2C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C30++0x03 line.long 0x00 "GICD_ICFR12,Interrupt Configuration Register 0x1C30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C34++0x03 line.long 0x00 "GICD_ICFR13,Interrupt Configuration Register 0x1C34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C38++0x03 line.long 0x00 "GICD_ICFR14,Interrupt Configuration Register 0x1C38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C3C++0x03 line.long 0x00 "GICD_ICFR15,Interrupt Configuration Register 0x1C3C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " tree.end width 17. tree "Private/Shared Peripheral Interrupt Status Registers" rgroup.long 0x1D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" rgroup.long 0x1D04++0x03 line.long 0x00 "GICD_SPISR0,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[31] ,IRQS[31] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[30] ,IRQS[30] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[29] ,IRQS[29] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[28] ,IRQS[28] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[27] ,IRQS[27] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[26] ,IRQS[26] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[25] ,IRQS[25] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[24] ,IRQS[24] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[23] ,IRQS[23] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[22] ,IRQS[22] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[21] ,IRQS[21] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[20] ,IRQS[20] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[19] ,IRQS[19] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[18] ,IRQS[18] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[17] ,IRQS[17] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[16] ,IRQS[16] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[15] ,IRQS[15] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[14] ,IRQS[14] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[13] ,IRQS[13] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[12] ,IRQS[12] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[11] ,IRQS[11] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[10] ,IRQS[10] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[9] ,IRQS[9] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[8] ,IRQS[8] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[7] ,IRQS[7] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[6] ,IRQS[6] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[5] ,IRQS[5] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[4] ,IRQS[4] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[3] ,IRQS[3] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[2] ,IRQS[2] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[1] ,IRQS[1] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[0] ,IRQS[0] status" "No interrupt,Interrupt" rgroup.long 0x1D08++0x03 line.long 0x00 "GICD_SPISR1,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[63] ,IRQS[63] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[62] ,IRQS[62] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[61] ,IRQS[61] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[60] ,IRQS[60] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[59] ,IRQS[59] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[58] ,IRQS[58] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[57] ,IRQS[57] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[56] ,IRQS[56] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[55] ,IRQS[55] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[54] ,IRQS[54] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[53] ,IRQS[53] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[52] ,IRQS[52] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[51] ,IRQS[51] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[50] ,IRQS[50] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[49] ,IRQS[49] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[48] ,IRQS[48] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[47] ,IRQS[47] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[46] ,IRQS[46] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[45] ,IRQS[45] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[44] ,IRQS[44] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[43] ,IRQS[43] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[42] ,IRQS[42] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[41] ,IRQS[41] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[40] ,IRQS[40] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[39] ,IRQS[39] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[38] ,IRQS[38] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[37] ,IRQS[37] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[36] ,IRQS[36] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[35] ,IRQS[35] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[34] ,IRQS[34] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[33] ,IRQS[33] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[32] ,IRQS[32] status" "No interrupt,Interrupt" rgroup.long 0x1D0C++0x03 line.long 0x00 "GICD_SPISR2,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[95] ,IRQS[95] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[94] ,IRQS[94] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[93] ,IRQS[93] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[92] ,IRQS[92] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[91] ,IRQS[91] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[90] ,IRQS[90] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[89] ,IRQS[89] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[88] ,IRQS[88] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[87] ,IRQS[87] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[86] ,IRQS[86] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[85] ,IRQS[85] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[84] ,IRQS[84] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[83] ,IRQS[83] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[82] ,IRQS[82] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[81] ,IRQS[81] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[80] ,IRQS[80] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[79] ,IRQS[79] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[78] ,IRQS[78] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[77] ,IRQS[77] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[76] ,IRQS[76] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[75] ,IRQS[75] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[74] ,IRQS[74] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[73] ,IRQS[73] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[72] ,IRQS[72] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[71] ,IRQS[71] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[70] ,IRQS[70] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[69] ,IRQS[69] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[68] ,IRQS[68] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[67] ,IRQS[67] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[66] ,IRQS[66] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[65] ,IRQS[65] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[64] ,IRQS[64] status" "No interrupt,Interrupt" rgroup.long 0x1D10++0x03 line.long 0x00 "GICD_SPISR3,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[127] ,IRQS[127] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[126] ,IRQS[126] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[125] ,IRQS[125] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[124] ,IRQS[124] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[123] ,IRQS[123] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[122] ,IRQS[122] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[121] ,IRQS[121] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[120] ,IRQS[120] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[119] ,IRQS[119] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[118] ,IRQS[118] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[117] ,IRQS[117] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[116] ,IRQS[116] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[115] ,IRQS[115] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[114] ,IRQS[114] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[113] ,IRQS[113] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[112] ,IRQS[112] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[111] ,IRQS[111] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[110] ,IRQS[110] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[109] ,IRQS[109] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[108] ,IRQS[108] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[107] ,IRQS[107] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[106] ,IRQS[106] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[105] ,IRQS[105] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[104] ,IRQS[104] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[103] ,IRQS[103] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[102] ,IRQS[102] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[101] ,IRQS[101] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[100] ,IRQS[100] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[99] ,IRQS[99] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[98] ,IRQS[98] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[97] ,IRQS[97] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[96] ,IRQS[96] status" "No interrupt,Interrupt" rgroup.long 0x1D14++0x03 line.long 0x00 "GICD_SPISR4,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[159] ,IRQS[159] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[158] ,IRQS[158] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[157] ,IRQS[157] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[156] ,IRQS[156] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[155] ,IRQS[155] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[154] ,IRQS[154] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[153] ,IRQS[153] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[152] ,IRQS[152] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[151] ,IRQS[151] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[150] ,IRQS[150] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[149] ,IRQS[149] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[148] ,IRQS[148] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[147] ,IRQS[147] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[146] ,IRQS[146] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[145] ,IRQS[145] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[144] ,IRQS[144] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[143] ,IRQS[143] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[142] ,IRQS[142] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[141] ,IRQS[141] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[140] ,IRQS[140] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[139] ,IRQS[139] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[138] ,IRQS[138] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[137] ,IRQS[137] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[136] ,IRQS[136] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[135] ,IRQS[135] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[134] ,IRQS[134] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[133] ,IRQS[133] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[132] ,IRQS[132] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[131] ,IRQS[131] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[130] ,IRQS[130] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[129] ,IRQS[129] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[128] ,IRQS[128] status" "No interrupt,Interrupt" rgroup.long 0x1D18++0x03 line.long 0x00 "GICD_SPISR5,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[191] ,IRQS[191] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[190] ,IRQS[190] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[189] ,IRQS[189] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[188] ,IRQS[188] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[187] ,IRQS[187] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[186] ,IRQS[186] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[185] ,IRQS[185] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[184] ,IRQS[184] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[183] ,IRQS[183] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[182] ,IRQS[182] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[181] ,IRQS[181] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[180] ,IRQS[180] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[179] ,IRQS[179] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[178] ,IRQS[178] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[177] ,IRQS[177] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[176] ,IRQS[176] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[175] ,IRQS[175] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[174] ,IRQS[174] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[173] ,IRQS[173] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[172] ,IRQS[172] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[171] ,IRQS[171] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[170] ,IRQS[170] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[169] ,IRQS[169] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[168] ,IRQS[168] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[167] ,IRQS[167] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[166] ,IRQS[166] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[165] ,IRQS[165] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[164] ,IRQS[164] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[163] ,IRQS[163] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[162] ,IRQS[162] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[161] ,IRQS[161] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[160] ,IRQS[160] status" "No interrupt,Interrupt" rgroup.long 0x1D1C++0x03 line.long 0x00 "GICD_SPISR6,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[223] ,IRQS[223] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[222] ,IRQS[222] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[221] ,IRQS[221] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[220] ,IRQS[220] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[219] ,IRQS[219] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[218] ,IRQS[218] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[217] ,IRQS[217] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[216] ,IRQS[216] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[215] ,IRQS[215] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[214] ,IRQS[214] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[213] ,IRQS[213] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[212] ,IRQS[212] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[211] ,IRQS[211] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[210] ,IRQS[210] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[209] ,IRQS[209] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[208] ,IRQS[208] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[207] ,IRQS[207] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[206] ,IRQS[206] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[205] ,IRQS[205] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[204] ,IRQS[204] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[203] ,IRQS[203] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[202] ,IRQS[202] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[201] ,IRQS[201] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[200] ,IRQS[200] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[199] ,IRQS[199] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[198] ,IRQS[198] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[197] ,IRQS[197] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[196] ,IRQS[196] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[195] ,IRQS[195] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[194] ,IRQS[194] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[193] ,IRQS[193] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[192] ,IRQS[192] status" "No interrupt,Interrupt" tree.end textline " " width 17. wgroup.long 0x1F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "Send to specified,Send to all,Send to interrupt,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" bitfld.long 0x00 15. " SATT ,SATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F10++0x03 line.long 0x00 "GICD_CPENDSGIR0,SGI Clear Pending Registers" group.long 0x1F14++0x03 line.long 0x00 "GICD_CPENDSGIR1,SGI Clear Pending Registers" group.long 0x1F18++0x03 line.long 0x00 "GICD_CPENDSGIR2,SGI Clear Pending Registers" group.long 0x1F1C++0x03 line.long 0x00 "GICD_CPENDSGIR3,SGI Clear Pending Registers" textline " " group.long 0x1F20++0x03 line.long 0x00 "GICD_SPENDSGIR0,SGI Set Pending Registers" group.long 0x1F24++0x03 line.long 0x00 "GICD_SPENDSGIR1,SGI Set Pending Registers" group.long 0x1F28++0x03 line.long 0x00 "GICD_SPENDSGIR2,SGI Set Pending Registers" group.long 0x1F2C++0x03 line.long 0x00 "GICD_SPENDSGIR3,SGI Set Pending Registers" textline " " rgroup.long 0x1FE0++0x03 "Peripheral/Component ID Registers" line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.long 0x1FE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1FE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.long 0x00 0.--2. " DEVID ,DevID field" "0,1,2,3,4,5,6,7" rgroup.long 0x1FEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1FD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x1FD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0x1FD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0x1FDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.long 0x1FF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " width 17. group.long 0x2000++0x03 "Interrupt Controller Physical CPU Interface" line.long 0x00 "GICC_ICR,CPU Interface Control Register" bitfld.long 0x00 4. " SBPR ,Secure/Non-secure Binary Point Register for preemption control" "SBPR for Secure/Non-SBPR for Non-Secure,SBPR for Both" textline " " bitfld.long 0x00 3. " FIQEN ,Indicates using of FIQ or IRQ signal for interrupts" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Interrupt acknowledge control" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 1. " ENABLENS ,Global Enable for signalling of Non-secure interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLES ,Global Enable for signalling of Secure interrupts" "Disabled,Enabled" group.long 0x2004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x2008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x200C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x2010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,ACKINTID value from the corresponding ICCIAR access" rgroup.long 0x2014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x2018++0x03 line.long 0x00 "GICC_HPIR,Highest Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt" group.long 0x201C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" group.long 0x20D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" group.long 0x20E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" rgroup.long 0x20FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x3000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" width 17. group.long 0x4000++0x03 "Interrupt Controller Virtual CPU Interface (Hypervisor view)" line.long 0x00 "GICH_HCR,Hypervisor Control Register" rgroup.long 0x4004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x40F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" group.long 0x4100++0x03 line.long 0x00 "GICH_LR0,List Register 0" group.long 0x4104++0x03 line.long 0x00 "GICH_LR1,List Register 1" group.long 0x4108++0x03 line.long 0x00 "GICH_LR2,List Register 2" group.long 0x410C++0x03 line.long 0x00 "GICH_LR3,List Register 3" group.long 0x6000++0x03 "Interrupt Controller Virtual CPU Interface (Virtual Machine View)" line.long 0x00 "GICV_CTLR,VM Control Register" group.long 0x6004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" group.long 0x6008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" hgroup.long 0x600C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x6010++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" rgroup.long 0x6014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" rgroup.long 0x6018++0x03 line.long 0x00 "GICV_HPIR,VM Highest Pending Interrupt Register" group.long 0x601C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" group.long 0x60D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" group.long 0x60E0++0x03 line.long 0x00 "GICV_NSAPR0,VM Non-Secure Active Priority Register" rgroup.long 0x60FC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x7000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" tree.end tree.end elif (cpuis("TDA2PXIPU*")) tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif (cpuis("TDA2PXIVA*")) tree "Core Registers (ARM968)" width 9. tree "ID Registers" rgroup.long c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Major Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Minor Specification Revision" rgroup.long c15:0x200--0x200 line.long 0x0 "TCMCFG ,Tightly Coupled Memory Size Configuraton" bitfld.long 0x0 18.--22. " DTCM , Data TCM Size" "0,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserve,?..." bitfld.long 0x0 14. " DTCM , Data TCM Exists" "Yes,No" textline " " bitfld.long 0x0 6.--10. " ITCM , Instruction TCM Size" "0,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,512kB,1MB,2MB,4MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserve,?..." bitfld.long 0x0 2. " ITCM , Instruction TCM Exists" "Yes,No" tree.end width 9. tree "System Configuration and Control" group.long c15:0x1--0x1 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " LT ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction SRAM Enable" "Disable,Enable" textline " " bitfld.long 0x0 7. " B ,Endianism" "Little,Big" bitfld.long 0x0 3. " W ,Write Buffer" "Disable,Enable" bitfld.long 0x0 2. " D ,Data SRAM Enable" "Disable,Enable" textline " " bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable" group.long c15:0x101f--0x101f line.long 0x0 "CCR,Configuration Control Register" bitfld.long 0x0 18. " I ,ITCM Order Bit" "Not stalled,Stalled" bitfld.long 0x0 17. " D ,DTCM Order Bit" "Not stalled,Stalled" bitfld.long 0x0 16. " B ,AHB Instruction Prefetch Buffer Disable Bit" "No,Yes" textline " " bitfld.long 0x0 2. " FM ,Stalling Core when FIQ and ETM FIFOFULL" "Not stalled,Stalled" bitfld.long 0x0 1. " IM ,Stalling Core when IRQ and ETM FIFOFULL" "Not stalled,Stalled" group.long c15:0x010d--0x010d line.long 0x0 "CONTEXT,Trace Process ID Register" tree.end width 9. tree "ICEbreaker" group.long ice:0x0--0x0 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "No,Yes" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "Disabled,Enabled" bitfld.long 0x0 0x3 " STEP ,Single Step" "Disabled,Enabled" textline " " bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "No,Yes" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "No,Yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "No,Yes" rgroup.long ice:0x1--0x1 line.long 0x0 "DBGSTAT,Debug Status Register" bitfld.long 0x0 0x4 " ITBIT ,ITBIT" "0,Thumb" bitfld.long 0x0 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x0 0x2 " IFEN ,Interrupts Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "No,Yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "No,Yes" group.long ice:0x2--0x2 line.long 0x0 "VECTOR,Vector Catch Register" bitfld.long 0x0 0x7 " FIQ ,FIQ" "Disabled,Enabled" bitfld.long 0x0 0x6 " IRQ ,IRQ" "Disabled,Enabled" bitfld.long 0x0 0x4 " D_ABO ,D_ABORT" "Disabled,Enabled" textline " " bitfld.long 0x0 0x3 " P_ABO ,P_ABORT" "Disabled,Enabled" bitfld.long 0x0 0x2 " SWI ,SWI" "Disabled,Enabled" bitfld.long 0x0 0x1 " UND ,UNDEF" "Disabled,Enabled" textline " " bitfld.long 0x0 0x0 " RES ,RESET" "Disabled,Enabled" rgroup.long ice:0x4--0x4 line.long 0x0 "COMCTRL,Debug Communication Control Register" bitfld.long 0x0 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x0 0x1 " W ,Write Register Free" "Idle,Pending" bitfld.long 0x0 0x0 " R ,Read Register Free" "Idle,Pending" group.long ice:0x5--0x5 line.long 0x0 "COMDATA,Debug Communication Data Register" group.long ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "Disabled,Enabled" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0,1" bitfld.long 0x10 0x5 " DBGEXT ,Depentend from EXTERN Signal" "0,1" bitfld.long 0x10 0x4 " DnTRANS ,CPU Mode" "User,No User" bitfld.long 0x10 0x1--0x2 " DMAS ,Access Size" "Byte,Word,Long,?..." bitfld.long 0x10 0x0 " DnRW ,Read/Write" "R,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "Enabled,Disabled" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "Enabled,Disabled" bitfld.long 0x14 0x5 " DBGEXT ,Depentend from EXTERN Signal" "Enabled,Disabled" bitfld.long 0x14 0x4 " DnTRANS ,CPU Mode" "Enabled,Disabled" bitfld.long 0x14 0x1--0x2 " DMAS ,Access Size" "Enabled,Reserved,Reserved,Disabled" bitfld.long 0x14 0x0 " DnRW ,Read/Write" "Enabled,Disabled" group.long ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "Disabled,Enabled" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0,1" bitfld.long 0x10 0x5 " DBGEXT ,Depentend from EXTERN Signal" "0,1" bitfld.long 0x10 0x4 " DnTRANS ,CPU Mode" "User,No User" bitfld.long 0x10 0x1--0x2 " DMAS ,Access Size" "Byte,Word,Long,?..." bitfld.long 0x10 0x0 " DnRW ,Read/Write" "R,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "Enabled,Disabled" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "Enabled,Disabled" bitfld.long 0x14 0x5 " DBGEXT ,Depentend from EXTERN Signal" "Enabled,Disabled" bitfld.long 0x14 0x4 " DnTRANS ,CPU Mode" "Enabled,Disabled" bitfld.long 0x14 0x1--0x2 " DMAS ,Access Size" "Enabled,Reserved,Reserved,Disabled" bitfld.long 0x14 0x0 " DnRW ,Read/Write" "Enabled,Disabled" tree.end width 0xb tree.end elif cpuis("TDA2PXDSP?") AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (c66x)" config 16. 8. width 0x0b tree.open "Cache" tree "L1P Cache" base d:0x01840000 width 9. group.long 0x20++0x7 "L1P Cache Control Registers" line.long 0x00 "L1PCFG,L1P Configuration Register" bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1PCC,L1P Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1P freeze mode" "Disabled,Enabled" wgroup.long 0x4020++0x3 line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation" group.long 0x4024++0x3 line.long 0x00 "L1PIWC,L1P Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1PIWC ,Word count for block invalidation" group.long 0x5028++0x3 line.long 0x00 "L1PINV,L1P Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1P cache" "Normal,Invalidate" //width 13. //wgroup.long 0xD00++0x13 "Memory Protection Lock Registers" // line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0" // hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" // line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1" // hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" // line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2" // hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" // line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3" // hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" // line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register" // bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset" // bitfld.long 0x10 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" // bitfld.long 0x10 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" //rgroup.long 0xD14++0x3 // line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register" // bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" base d:0x0184a000 width 12. tree "Memory Page Protection Attribute Registers" group.long 0x640++0x3f line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" tree.end width 11. rgroup.long 0x400++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Local" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" textline " " bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x408++0x3 line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear" bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear" AUTOINDENT.ON right tree rgroup.long 0x6404++0x3 "Error Detection Registers" line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x6408++0x3 line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0x640C++0x3 line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Contains the upper 27 bit of error location" bitfld.long 0x0 0. "RAM,Location where error was detected" "L1P cache,L1P RAM" AUTOINDENT.OFF width 0xb tree.end tree "L1D Cache" base d:0x01840000 width 10. group.long 0x40++0x7 "L1D Cache Control Registers" line.long 0x00 "L1DCFG,L1D Cache Configuration" bitfld.long 0x00 0.--2. " L1DMODE ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1DCC,L1D Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1D freeze mode" "Disabled,Enabled" wgroup.long 0x4030++0x3 line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address" hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address" group.long 0x4034++0x3 line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWIWC ,L1D Writeback-Invalidated Word Count" wgroup.long 0x4040++0x3 line.long 0x00 "L1DWBAR,L1D Writeback Base Address" hexmask.long 0x00 0.--31. 1. " L1DWBAR ,L1D Writeback Base Address" group.long 0x4044++0x3 line.long 0x00 "L1DWWC,L1D Writeback Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWWC ,L1D Writeback Word Count" wgroup.long 0x4048++0x3 line.long 0x00 "L1DIBAR,L1D Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L1DIBAR ,L1D Invalidate Base Address" group.long 0x404c++0x3 line.long 0x00 "L1DIWC,L1D Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DIWC ,L1D Invalidate Word Count" group.long 0x5048++0x3 line.long 0x00 "L1DINV,L1D Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1D cache" "Normal,Invalidate" group.long 0x5040++0x3 line.long 0x00 "L1DWB,L1P Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L1D cache" "Normal,Write back" group.long 0x5044++0x3 line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register" bitfld.long 0x00 0. " C ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate" width 11. base d:0x0184a000 tree "Memory Protection Attribute Registers" group.long 0xe40++0x3f line.long 0x0 "MPPA16,Memory Protection Attribute Register" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" line.long 0x4 "MPPA17,Memory Protection Attribute Register" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" line.long 0x8 "MPPA18,Memory Protection Attribute Register" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" line.long 0xC "MPPA19,Memory Protection Attribute Register" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" line.long 0x10 "MPPA20,Memory Protection Attribute Register" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" line.long 0x14 "MPPA21,Memory Protection Attribute Register" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" line.long 0x18 "MPPA22,Memory Protection Attribute Register" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" line.long 0x1C "MPPA23,Memory Protection Attribute Register" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" line.long 0x20 "MPPA24,Memory Protection Attribute Register" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" line.long 0x24 "MPPA25,Memory Protection Attribute Register" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" line.long 0x28 "MPPA26,Memory Protection Attribute Register" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" line.long 0x2C "MPPA27,Memory Protection Attribute Register" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" line.long 0x30 "MPPA28,Memory Protection Attribute Register" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" line.long 0x34 "MPPA29,Memory Protection Attribute Register" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" line.long 0x38 "MPPA30,Memory Protection Attribute Register" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" line.long 0x3C "MPPA31,Memory Protection Attribute Register" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" tree.end base d:0x0184a000 width 10. rgroup.long 0xc00++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0xc08++0x3 line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared" width 13. wgroup.long 0xd00++0xf "Memory Protection Lock Registers" line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2" line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3" wgroup.long 0xd10++0x3 line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0xd14++0x3 line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" width 0xb tree.end tree "L2 Cache" base d:0x01840000 width 9. group.long 0x00++0x3 "L2 Cache Control Registers" line.long 0x00 "L2CFG,L2 Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " NUM_MM ,Number of megamodules minus one" hexmask.long.byte 0x00 16.--19. 1. " MMID ,Contains the Megamodule ID number" bitfld.long 0x00 9. " IP ,L1P global invalidate bit" "Normal,Invalidate" textline " " bitfld.long 0x00 8. " ID ,L1D global invalidate bit" "Normal,Invalidate" bitfld.long 0x00 3. " L2CC ,Freeze mode" "Normal,Frozen" bitfld.long 0x00 0.--2. " L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum" wgroup.long 0x4000++0x3 line.long 0x00 "L2WBAR,L2 Writeback Base Address Register" hexmask.long 0x00 0.--31. 1. " L2WBAR ,L2 Writeback Base Address" group.long 0x4004++0x3 line.long 0x00 "L2WWC,L2 Writeback Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WWC ,L2 Writeback Word Count" wgroup.long 0x4010++0x3 line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address" group.long 0x4014++0x3 line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WIWC ,L2 Writeback Invalidate Word Count" wgroup.long 0x4018++0x3 line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L2IBAR ,L2 Invalidate Base Address" group.long 0x401c++0x3 line.long 0x00 "L2IWC,L2 Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2IWC ,L2 Invalidate Word Count" group.long 0x5000++0xb line.long 0x00 "L2WB,L2 Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L2 cache" "Normal,Writeback" line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register" bitfld.long 0x04 0. " C ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback" line.long 0x08 "L2INV,L2 Invalidate Register" bitfld.long 0x08 0. " I ,Controls the global invalidation of L2 cache" "Normal,Invalidate" tree "Memory Attribute Registers" width 8. base d:0x01848000 rgroup.long 0x00++0x2f line.long 0x0 "MAR0,Memory Attribute Register 0" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR1,Memory Attribute Register 1" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR2,Memory Attribute Register 2" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR3,Memory Attribute Register 3" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR4,Memory Attribute Register 4" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR5,Memory Attribute Register 5" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR6,Memory Attribute Register 6" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR7,Memory Attribute Register 7" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR8,Memory Attribute Register 8" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR9,Memory Attribute Register 9" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR10,Memory Attribute Register 10" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR11,Memory Attribute Register 11" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" group.long 0x30++0x3cf line.long 0x0 "MAR12,Memory Attribute Register 12" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR13,Memory Attribute Register 13" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR14,Memory Attribute Register 14" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR15,Memory Attribute Register 15" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR16,Memory Attribute Register 16" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR17,Memory Attribute Register 17" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR18,Memory Attribute Register 18" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR19,Memory Attribute Register 19" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR20,Memory Attribute Register 20" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR21,Memory Attribute Register 21" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR22,Memory Attribute Register 22" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR23,Memory Attribute Register 23" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30 "MAR24,Memory Attribute Register 24" bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34 "MAR25,Memory Attribute Register 25" bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38 "MAR26,Memory Attribute Register 26" bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C "MAR27,Memory Attribute Register 27" bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x40 "MAR28,Memory Attribute Register 28" bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x40 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x44 "MAR29,Memory Attribute Register 29" bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x44 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x48 "MAR30,Memory Attribute Register 30" bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x48 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4C "MAR31,Memory Attribute Register 31" bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x50 "MAR32,Memory Attribute Register 32" bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x50 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x54 "MAR33,Memory Attribute Register 33" bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x54 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x58 "MAR34,Memory Attribute Register 34" bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x58 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x5C "MAR35,Memory Attribute Register 35" bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x5C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x60 "MAR36,Memory Attribute Register 36" bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x60 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x64 "MAR37,Memory Attribute Register 37" bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x64 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x68 "MAR38,Memory Attribute Register 38" bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x68 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x6C "MAR39,Memory Attribute Register 39" bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x6C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x70 "MAR40,Memory Attribute Register 40" bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x70 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x74 "MAR41,Memory Attribute Register 41" bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x74 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x78 "MAR42,Memory Attribute Register 42" bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x78 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x7C "MAR43,Memory Attribute Register 43" bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x7C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x80 "MAR44,Memory Attribute Register 44" bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x80 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x84 "MAR45,Memory Attribute Register 45" bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x84 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x88 "MAR46,Memory Attribute Register 46" bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x88 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8C "MAR47,Memory Attribute Register 47" bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x90 "MAR48,Memory Attribute Register 48" bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x90 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x94 "MAR49,Memory Attribute Register 49" bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x94 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x98 "MAR50,Memory Attribute Register 50" bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x98 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x9C "MAR51,Memory Attribute Register 51" bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x9C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA0 "MAR52,Memory Attribute Register 52" bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA4 "MAR53,Memory Attribute Register 53" bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA8 "MAR54,Memory Attribute Register 54" bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xAC "MAR55,Memory Attribute Register 55" bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xAC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB0 "MAR56,Memory Attribute Register 56" bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB4 "MAR57,Memory Attribute Register 57" bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB8 "MAR58,Memory Attribute Register 58" bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xBC "MAR59,Memory Attribute Register 59" bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xBC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC0 "MAR60,Memory Attribute Register 60" bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC4 "MAR61,Memory Attribute Register 61" bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC8 "MAR62,Memory Attribute Register 62" bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xCC "MAR63,Memory Attribute Register 63" bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xCC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD0 "MAR64,Memory Attribute Register 64" bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD4 "MAR65,Memory Attribute Register 65" bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD8 "MAR66,Memory Attribute Register 66" bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xDC "MAR67,Memory Attribute Register 67" bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xDC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE0 "MAR68,Memory Attribute Register 68" bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE4 "MAR69,Memory Attribute Register 69" bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE8 "MAR70,Memory Attribute Register 70" bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xEC "MAR71,Memory Attribute Register 71" bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xEC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF0 "MAR72,Memory Attribute Register 72" bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF4 "MAR73,Memory Attribute Register 73" bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF8 "MAR74,Memory Attribute Register 74" bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xFC "MAR75,Memory Attribute Register 75" bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xFC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x100 "MAR76,Memory Attribute Register 76" bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x100 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x104 "MAR77,Memory Attribute Register 77" bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x104 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x108 "MAR78,Memory Attribute Register 78" bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x108 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10C "MAR79,Memory Attribute Register 79" bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x110 "MAR80,Memory Attribute Register 80" bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x110 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x114 "MAR81,Memory Attribute Register 81" bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x114 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x118 "MAR82,Memory Attribute Register 82" bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x118 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x11C "MAR83,Memory Attribute Register 83" bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x11C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x120 "MAR84,Memory Attribute Register 84" bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x120 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x124 "MAR85,Memory Attribute Register 85" bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x124 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x128 "MAR86,Memory Attribute Register 86" bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x128 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x12C "MAR87,Memory Attribute Register 87" bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x12C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x130 "MAR88,Memory Attribute Register 88" bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x130 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x134 "MAR89,Memory Attribute Register 89" bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x134 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x138 "MAR90,Memory Attribute Register 90" bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x138 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x13C "MAR91,Memory Attribute Register 91" bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x13C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x140 "MAR92,Memory Attribute Register 92" bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x140 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x144 "MAR93,Memory Attribute Register 93" bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x144 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x148 "MAR94,Memory Attribute Register 94" bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x148 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14C "MAR95,Memory Attribute Register 95" bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x150 "MAR96,Memory Attribute Register 96" bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x150 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x154 "MAR97,Memory Attribute Register 97" bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x154 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x158 "MAR98,Memory Attribute Register 98" bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x158 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x15C "MAR99,Memory Attribute Register 99" bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x15C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x160 "MAR100,Memory Attribute Register 100" bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x160 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x164 "MAR101,Memory Attribute Register 101" bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x164 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x168 "MAR102,Memory Attribute Register 102" bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x168 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x16C "MAR103,Memory Attribute Register 103" bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x16C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x170 "MAR104,Memory Attribute Register 104" bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x170 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x174 "MAR105,Memory Attribute Register 105" bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x174 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x178 "MAR106,Memory Attribute Register 106" bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x178 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x17C "MAR107,Memory Attribute Register 107" bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x17C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x180 "MAR108,Memory Attribute Register 108" bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x180 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x184 "MAR109,Memory Attribute Register 109" bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x184 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x188 "MAR110,Memory Attribute Register 110" bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x188 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18C "MAR111,Memory Attribute Register 111" bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x190 "MAR112,Memory Attribute Register 112" bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x190 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x194 "MAR113,Memory Attribute Register 113" bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x194 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x198 "MAR114,Memory Attribute Register 114" bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x198 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x19C "MAR115,Memory Attribute Register 115" bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x19C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A0 "MAR116,Memory Attribute Register 116" bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A4 "MAR117,Memory Attribute Register 117" bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A8 "MAR118,Memory Attribute Register 118" bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1AC "MAR119,Memory Attribute Register 119" bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B0 "MAR120,Memory Attribute Register 120" bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B4 "MAR121,Memory Attribute Register 121" bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B8 "MAR122,Memory Attribute Register 122" bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1BC "MAR123,Memory Attribute Register 123" bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C0 "MAR124,Memory Attribute Register 124" bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C4 "MAR125,Memory Attribute Register 125" bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C8 "MAR126,Memory Attribute Register 126" bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1CC "MAR127,Memory Attribute Register 127" bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D0 "MAR128,Memory Attribute Register 128" bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D4 "MAR129,Memory Attribute Register 129" bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D8 "MAR130,Memory Attribute Register 130" bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1DC "MAR131,Memory Attribute Register 131" bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E0 "MAR132,Memory Attribute Register 132" bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E4 "MAR133,Memory Attribute Register 133" bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E8 "MAR134,Memory Attribute Register 134" bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1EC "MAR135,Memory Attribute Register 135" bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F0 "MAR136,Memory Attribute Register 136" bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F4 "MAR137,Memory Attribute Register 137" bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F8 "MAR138,Memory Attribute Register 138" bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1FC "MAR139,Memory Attribute Register 139" bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x200 "MAR140,Memory Attribute Register 140" bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x200 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x204 "MAR141,Memory Attribute Register 141" bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x204 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x208 "MAR142,Memory Attribute Register 142" bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x208 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20C "MAR143,Memory Attribute Register 143" bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x210 "MAR144,Memory Attribute Register 144" bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x210 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x214 "MAR145,Memory Attribute Register 145" bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x214 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x218 "MAR146,Memory Attribute Register 146" bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x218 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x21C "MAR147,Memory Attribute Register 147" bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x21C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x220 "MAR148,Memory Attribute Register 148" bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x220 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x224 "MAR149,Memory Attribute Register 149" bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x224 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x228 "MAR150,Memory Attribute Register 150" bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x228 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x22C "MAR151,Memory Attribute Register 151" bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x22C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x230 "MAR152,Memory Attribute Register 152" bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x230 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x234 "MAR153,Memory Attribute Register 153" bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x234 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x238 "MAR154,Memory Attribute Register 154" bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x238 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x23C "MAR155,Memory Attribute Register 155" bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x23C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x240 "MAR156,Memory Attribute Register 156" bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x240 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x244 "MAR157,Memory Attribute Register 157" bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x244 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x248 "MAR158,Memory Attribute Register 158" bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x248 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24C "MAR159,Memory Attribute Register 159" bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x250 "MAR160,Memory Attribute Register 160" bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x250 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x254 "MAR161,Memory Attribute Register 161" bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x254 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x258 "MAR162,Memory Attribute Register 162" bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x258 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x25C "MAR163,Memory Attribute Register 163" bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x25C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x260 "MAR164,Memory Attribute Register 164" bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x260 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x264 "MAR165,Memory Attribute Register 165" bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x264 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x268 "MAR166,Memory Attribute Register 166" bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x268 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x26C "MAR167,Memory Attribute Register 167" bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x26C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x270 "MAR168,Memory Attribute Register 168" bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x270 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x274 "MAR169,Memory Attribute Register 169" bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x274 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x278 "MAR170,Memory Attribute Register 170" bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x278 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x27C "MAR171,Memory Attribute Register 171" bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x27C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x280 "MAR172,Memory Attribute Register 172" bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x280 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x284 "MAR173,Memory Attribute Register 173" bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x284 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x288 "MAR174,Memory Attribute Register 174" bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x288 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28C "MAR175,Memory Attribute Register 175" bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x290 "MAR176,Memory Attribute Register 176" bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x290 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x294 "MAR177,Memory Attribute Register 177" bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x294 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x298 "MAR178,Memory Attribute Register 178" bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x298 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x29C "MAR179,Memory Attribute Register 179" bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x29C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A0 "MAR180,Memory Attribute Register 180" bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A4 "MAR181,Memory Attribute Register 181" bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A8 "MAR182,Memory Attribute Register 182" bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2AC "MAR183,Memory Attribute Register 183" bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B0 "MAR184,Memory Attribute Register 184" bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B4 "MAR185,Memory Attribute Register 185" bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B8 "MAR186,Memory Attribute Register 186" bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2BC "MAR187,Memory Attribute Register 187" bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C0 "MAR188,Memory Attribute Register 188" bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C4 "MAR189,Memory Attribute Register 189" bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C8 "MAR190,Memory Attribute Register 190" bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2CC "MAR191,Memory Attribute Register 191" bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D0 "MAR192,Memory Attribute Register 192" bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D4 "MAR193,Memory Attribute Register 193" bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D8 "MAR194,Memory Attribute Register 194" bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2DC "MAR195,Memory Attribute Register 195" bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E0 "MAR196,Memory Attribute Register 196" bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E4 "MAR197,Memory Attribute Register 197" bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E8 "MAR198,Memory Attribute Register 198" bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2EC "MAR199,Memory Attribute Register 199" bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F0 "MAR200,Memory Attribute Register 200" bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F4 "MAR201,Memory Attribute Register 201" bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F8 "MAR202,Memory Attribute Register 202" bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2FC "MAR203,Memory Attribute Register 203" bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x300 "MAR204,Memory Attribute Register 204" bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x300 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x304 "MAR205,Memory Attribute Register 205" bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x304 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x308 "MAR206,Memory Attribute Register 206" bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x308 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30C "MAR207,Memory Attribute Register 207" bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x310 "MAR208,Memory Attribute Register 208" bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x310 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x314 "MAR209,Memory Attribute Register 209" bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x314 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x318 "MAR210,Memory Attribute Register 210" bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x318 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x31C "MAR211,Memory Attribute Register 211" bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x31C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x320 "MAR212,Memory Attribute Register 212" bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x320 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x324 "MAR213,Memory Attribute Register 213" bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x324 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x328 "MAR214,Memory Attribute Register 214" bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x328 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x32C "MAR215,Memory Attribute Register 215" bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x32C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x330 "MAR216,Memory Attribute Register 216" bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x330 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x334 "MAR217,Memory Attribute Register 217" bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x334 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x338 "MAR218,Memory Attribute Register 218" bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x338 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x33C "MAR219,Memory Attribute Register 219" bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x33C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x340 "MAR220,Memory Attribute Register 220" bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x340 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x344 "MAR221,Memory Attribute Register 221" bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x344 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x348 "MAR222,Memory Attribute Register 222" bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x348 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34C "MAR223,Memory Attribute Register 223" bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x350 "MAR224,Memory Attribute Register 224" bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x350 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x354 "MAR225,Memory Attribute Register 225" bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x354 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x358 "MAR226,Memory Attribute Register 226" bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x358 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x35C "MAR227,Memory Attribute Register 227" bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x35C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x360 "MAR228,Memory Attribute Register 228" bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x360 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x364 "MAR229,Memory Attribute Register 229" bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x364 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x368 "MAR230,Memory Attribute Register 230" bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x368 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x36C "MAR231,Memory Attribute Register 231" bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x36C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x370 "MAR232,Memory Attribute Register 232" bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x370 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x374 "MAR233,Memory Attribute Register 233" bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x374 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x378 "MAR234,Memory Attribute Register 234" bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x378 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x37C "MAR235,Memory Attribute Register 235" bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x37C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x380 "MAR236,Memory Attribute Register 236" bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x380 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x384 "MAR237,Memory Attribute Register 237" bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x384 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x388 "MAR238,Memory Attribute Register 238" bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x388 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38C "MAR239,Memory Attribute Register 239" bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x390 "MAR240,Memory Attribute Register 240" bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x390 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x394 "MAR241,Memory Attribute Register 241" bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x394 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x398 "MAR242,Memory Attribute Register 242" bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x398 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x39C "MAR243,Memory Attribute Register 243" bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x39C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A0 "MAR244,Memory Attribute Register 244" bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A4 "MAR245,Memory Attribute Register 245" bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A8 "MAR246,Memory Attribute Register 246" bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3AC "MAR247,Memory Attribute Register 247" bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B0 "MAR248,Memory Attribute Register 248" bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B4 "MAR249,Memory Attribute Register 249" bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B8 "MAR250,Memory Attribute Register 250" bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3BC "MAR251,Memory Attribute Register 251" bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C0 "MAR252,Memory Attribute Register 252" bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C4 "MAR253,Memory Attribute Register 253" bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C8 "MAR254,Memory Attribute Register 254" bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3CC "MAR255,Memory Attribute Register 255" bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" tree.end width 10. base d:0x0184a000 tree "Memory Protection Page Attribute Registers" group.long 0x200++0x7f line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16" bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x40 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x40 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x40 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x40 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x40 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x40 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x40 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x40 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x40 2. " UR ,User read access type" "Normal,User" bitfld.long 0x40 1. " UW ,User write access type" "Normal,User" bitfld.long 0x40 0. " UX ,User execute access type" "Normal,User" line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17" bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x44 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x44 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x44 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x44 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x44 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x44 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x44 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x44 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x44 2. " UR ,User read access type" "Normal,User" bitfld.long 0x44 1. " UW ,User write access type" "Normal,User" bitfld.long 0x44 0. " UX ,User execute access type" "Normal,User" line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18" bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x48 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x48 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x48 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x48 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x48 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x48 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x48 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x48 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x48 2. " UR ,User read access type" "Normal,User" bitfld.long 0x48 1. " UW ,User write access type" "Normal,User" bitfld.long 0x48 0. " UX ,User execute access type" "Normal,User" line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19" bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4C 0. " UX ,User execute access type" "Normal,User" line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20" bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x50 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x50 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x50 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x50 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x50 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x50 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x50 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x50 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x50 2. " UR ,User read access type" "Normal,User" bitfld.long 0x50 1. " UW ,User write access type" "Normal,User" bitfld.long 0x50 0. " UX ,User execute access type" "Normal,User" line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21" bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x54 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x54 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x54 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x54 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x54 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x54 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x54 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x54 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x54 2. " UR ,User read access type" "Normal,User" bitfld.long 0x54 1. " UW ,User write access type" "Normal,User" bitfld.long 0x54 0. " UX ,User execute access type" "Normal,User" line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22" bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x58 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x58 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x58 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x58 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x58 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x58 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x58 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x58 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x58 2. " UR ,User read access type" "Normal,User" bitfld.long 0x58 1. " UW ,User write access type" "Normal,User" bitfld.long 0x58 0. " UX ,User execute access type" "Normal,User" line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23" bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x5C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x5C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x5C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x5C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x5C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x5C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x5C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x5C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x5C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x5C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x5C 0. " UX ,User execute access type" "Normal,User" line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24" bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x60 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x60 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x60 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x60 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x60 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x60 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x60 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x60 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x60 2. " UR ,User read access type" "Normal,User" bitfld.long 0x60 1. " UW ,User write access type" "Normal,User" bitfld.long 0x60 0. " UX ,User execute access type" "Normal,User" line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25" bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x64 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x64 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x64 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x64 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x64 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x64 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x64 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x64 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x64 2. " UR ,User read access type" "Normal,User" bitfld.long 0x64 1. " UW ,User write access type" "Normal,User" bitfld.long 0x64 0. " UX ,User execute access type" "Normal,User" line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26" bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x68 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x68 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x68 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x68 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x68 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x68 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x68 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x68 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x68 2. " UR ,User read access type" "Normal,User" bitfld.long 0x68 1. " UW ,User write access type" "Normal,User" bitfld.long 0x68 0. " UX ,User execute access type" "Normal,User" line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27" bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x6C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x6C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x6C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x6C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x6C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x6C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x6C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x6C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x6C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x6C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x6C 0. " UX ,User execute access type" "Normal,User" line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28" bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x70 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x70 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x70 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x70 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x70 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x70 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x70 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x70 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x70 2. " UR ,User read access type" "Normal,User" bitfld.long 0x70 1. " UW ,User write access type" "Normal,User" bitfld.long 0x70 0. " UX ,User execute access type" "Normal,User" line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29" bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x74 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x74 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x74 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x74 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x74 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x74 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x74 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x74 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x74 2. " UR ,User read access type" "Normal,User" bitfld.long 0x74 1. " UW ,User write access type" "Normal,User" bitfld.long 0x74 0. " UX ,User execute access type" "Normal,User" line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30" bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x78 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x78 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x78 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x78 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x78 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x78 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x78 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x78 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x78 2. " UR ,User read access type" "Normal,User" bitfld.long 0x78 1. " UW ,User write access type" "Normal,User" bitfld.long 0x78 0. " UX ,User execute access type" "Normal,User" line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31" bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x7C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x7C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x7C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x7C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x7C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x7C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x7C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x7C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x7C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x7C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x7C 0. " UX ,User execute access type" "Normal,User" tree.end width 9. rgroup.long 0x000++0x7 "Memory Protection Fault Registers" line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x008++0x3 line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear" width 12. wgroup.long 0x100++0xf "Memory Protection Lock Registers" line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2" hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3" hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" wgroup.long 0x110++0x3 line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0x114++0x3 line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" AUTOINDENT.ON right tree base d:0x01846000 rgroup.long 0x4++0x3 "Error Detection Registers" line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register" decmask.long.byte 0x0 16.--23. "BITPOS,Single Bit error position" bitfld.long 0x0 8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value" newline bitfld.long 0x0 7. "VERR,Error occurred on L2 victims" "False,True" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" newline bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x8++0x3 line.long 0x0 "L2EDCMD, L2 Error Detection Command Register" bitfld.long 0x0 7. "VCLR,Clears the victim parity error status" "No effect,Clear" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 4. "DCLR,Clears the data fetch parity error status" "No effect,Clear" newline bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0xC++0x3 line.long 0x0 "L2EDADDR,L2 Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)" bitfld.long 0x0 8.--9. "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3" bitfld.long 0x0 0. "RAM,Location where error was detected" "L2,RAM" rgroup.long 0x18++0x3 line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" rgroup.long 0x1C++0x3 line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" group.long 0x30++0x3 line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register" bitfld.long 0x0 0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" bitfld.long 0x0 0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" AUTOINDENT.OFF width 0xb tree.end tree.end tree "IDMA (Internal Direct Memory Access Controller)" width 14. base d:0x01820000 rgroup.long 0x00++0x3 "Channel 0" line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x04++0xf line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register" bitfld.long 0x00 31. " M31 ,Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " M30 ,Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " M29 ,Mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " M28 ,Mask bit 28" "Not masked,Masked" bitfld.long 0x00 27. " M27 ,Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " M26 ,Mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " M25 ,Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " M24 ,Mask bit 24" "Not masked,Masked" bitfld.long 0x00 23. " M23 ,Mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " M22 ,Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " M21 ,Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " M20 ,Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " M19 ,Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " M18 ,Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " M17 ,Mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " M16 ,Mask bit 16" "Not masked,Masked" bitfld.long 0x00 15. " M15 ,Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " M14 ,Mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " M13 ,Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " M12 ,Mask bit 12" "Not masked,Masked" bitfld.long 0x00 11. " M11 ,Mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " M10 ,Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " M9 ,Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " M8 ,Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " M7 ,Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " M6 ,Mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " M5 ,Mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " M4 ,Mask bit 4" "Not masked,Masked" bitfld.long 0x00 3. " M3 ,Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " M2 ,Mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " M1 ,Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " M0 ,Mask bit 0" "Not masked,Masked" line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register" hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address" line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register" hexmask.long 0x08 5.--31. 0x20 " DESTADDR ,Destination address" line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register" bitfld.long 0x0c 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x0c 0.--3. " COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.long 0x100++0x3 "Channel 1" line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x108++0xb line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register" hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address" line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register" hexmask.long 0x04 2.--31. 0x4 " DESTADDR ,Destination address" line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register" bitfld.long 0x08 29.--31. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x08 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " FILL ,Block fill" "0,1" textline " " hexmask.long.word 0x08 0.--15. 1. " COUNT ,Byte count" width 0xb tree.end tree "XMC (Extended Memory Controller)" width 14. AUTOINDENT.ON right tree base d:0x08000000 group.long 0x00++0x7F "XMC MPAX Segment Registers" line.long 0x0 "XMPAXL0,MPAX segment 0 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x0 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x0 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x0 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x0 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x0 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x0 0. "UX,User mode may execute from segment" "False,True" line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x0 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x8 "XMPAXL1,MPAX segment 1 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x8 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x8 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x8 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x8 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x8 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x8 0. "UX,User mode may execute from segment" "False,True" line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x8 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x10 "XMPAXL2,MPAX segment 2 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x10 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x10 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x10 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x10 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x10 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x10 0. "UX,User mode may execute from segment" "False,True" line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x10 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x18 "XMPAXL3,MPAX segment 3 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x18 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x18 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x18 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x18 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x18 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x18 0. "UX,User mode may execute from segment" "False,True" line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x18 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x20 "XMPAXL4,MPAX segment 4 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x20 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x20 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x20 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x20 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x20 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x20 0. "UX,User mode may execute from segment" "False,True" line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x20 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x28 "XMPAXL5,MPAX segment 5 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x28 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x28 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x28 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x28 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x28 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x28 0. "UX,User mode may execute from segment" "False,True" line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x28 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x30 "XMPAXL6,MPAX segment 6 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x30 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x30 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x30 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x30 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x30 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x30 0. "UX,User mode may execute from segment" "False,True" line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x30 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x38 "XMPAXL7,MPAX segment 7 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x38 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x38 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x38 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x38 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x38 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x38 0. "UX,User mode may execute from segment" "False,True" line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x38 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x40 "XMPAXL8,MPAX segment 8 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x40 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x40 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x40 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x40 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x40 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x40 0. "UX,User mode may execute from segment" "False,True" line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x40 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x48 "XMPAXL9,MPAX segment 9 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x48 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x48 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x48 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x48 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x48 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x48 0. "UX,User mode may execute from segment" "False,True" line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x48 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x50 "XMPAXL10,MPAX segment 10 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x50 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x50 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x50 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x50 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x50 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x50 0. "UX,User mode may execute from segment" "False,True" line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x50 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x58 "XMPAXL11,MPAX segment 11 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x58 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x58 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x58 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x58 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x58 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x58 0. "UX,User mode may execute from segment" "False,True" line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x58 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x60 "XMPAXL12,MPAX segment 12 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x60 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x60 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x60 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x60 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x60 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x60 0. "UX,User mode may execute from segment" "False,True" line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x60 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x68 "XMPAXL13,MPAX segment 13 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x68 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x68 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x68 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x68 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x68 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x68 0. "UX,User mode may execute from segment" "False,True" line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x68 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x70 "XMPAXL14,MPAX segment 14 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x70 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x70 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x70 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x70 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x70 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x70 0. "UX,User mode may execute from segment" "False,True" line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x70 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x78 "XMPAXL15,MPAX segment 15 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x78 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x78 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x78 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x78 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x78 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x78 0. "UX,User mode may execute from segment" "False,True" line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x78 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" textline "" rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers" line.long 0. "XMPFAR,Memory Protection Fault Address Register" hexmask.long 0x0 0.--31. "Fault Address,Fault Address" rgroup.long 0x204++0x3 line.long 0. "XMPFSR,Memory Protection Fault Status Register" bitfld.long 0. 8. "LOCAL,Access was a LOCAL access" "False,True" bitfld.long 0. 5. "SR,When set, indicates a supervisor read request" "False,True" bitfld.long 0. 4. "SW,When set, indicates a supervisor write request" "False,True" bitfld.long 0. 3. "SX,When set, indicates a supervisor program fetch request" "False,True" bitfld.long 0. 2. "UR,When set, indicates a user read request" "False,True" bitfld.long 0. 1. "UW,When set, indicates a user write request" "False,True" bitfld.long 0. 0. "UX,When set, indicates a user program fetch request" "False,True" group.long 0x208++0x3 line.long 0. "XMPFCR,Memory Protection Fault Clear Register" bitfld.long 0. 0. "MPFCLR,Clear fault" "No effect,Clear" group.long 0x280++0x3 "Prefetch Priority Register" line.long 0. "MDMAARBX,MDMA Arbitration Priority Register" bitfld.long 0. 16.--18. "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)" rgroup.long 0x300++0x3 "Prefetch Buffer Registers" line.long 0. "XPFCMD,Prefetch Command Register" bitfld.long 0. 4. "ACRST,Analysis Counter Reset" "No effect,Reset" hexmask.long.byte 0. 2.--3. "ACEN,Analysis Counter Enable" bitfld.long 0. 1. "ACENL,Analysis Counter ENable (ACEN) Load" "False,True" bitfld.long 0. 0. "INV,Invalidate prefetch buffer contents" "No effect,Invalidate" rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers" line.long 0. "XPFACS,Prefetch Analysis Counter Status" rgroup.long 0x310++0xF line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0" line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1" line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2" line.long 0xC "XPFAC3,Prefetch Analysis Counter 3" rgroup.long 0x400++0x1F line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0" line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1" line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2" line.long 0xC "XPFADDR3,Prefetch Address for Slot 3" line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4" line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5" line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6" line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7" AUTOINDENT.OFF width 0xb tree.end tree "Bandwith Management" width 13. base d:0x01841000 group.long 0x40++0xf "L1D" line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. group.long 0x00++0xf "L2" line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. base d:0x01820000 group.long 0x200++0xf "EMC" line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register" bitfld.long 0x0c 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" width 0xb tree.end tree "Interrupt Controller" width 11. base d:0x01800000 group.long 0x00++0xf line.long 0x00 "EVTFLAG0,Event Flag Register 0" setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr ,State of event EVT14" "Not occurred,Occurred" setclrfld.long 0x00 13. 0x20 13. 0x40 13. " EF13_set/clr ,State of event EVT13" "Not occurred,Occurred" textline " " setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr ,State of event EVT12" "Not occurred,Occurred" setclrfld.long 0x00 11. 0x20 11. 0x40 11. " EF11_set/clr ,State of event EVT11" "Not occurred,Occurred" textline " " setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr ,State of event EVT9" "Not occurred,Occurred" setclrfld.long 0x00 8. 0x20 8. 0x40 8. " EF8_set/clr ,State of event EVT8" "Not occurred,Occurred" textline " " setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr ,State of event EVT7" "Not occurred,Occurred" setclrfld.long 0x00 6. 0x20 6. 0x40 6. " EF6_set/clr ,State of event EVT6" "Not occurred,Occurred" textline " " setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr ,State of event EVT5" "Not occurred,Occurred" setclrfld.long 0x00 4. 0x20 4. 0x40 4. " EF4_set/clr ,State of event EVT4" "Not occurred,Occurred" textline " " setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr ,State of event EVT3" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x20 2. 0x40 2. " EF2_set/clr ,State of event EVT2" "Not occurred,Occurred" textline " " setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr ,State of event EVT1" "Not occurred,Occurred" setclrfld.long 0x00 0. 0x20 0. 0x40 0. " EF0_set/clr ,State of event EVT0" "Not occurred,Occurred" line.long 0x04 "EVTFLAG1,Event Flag Register 1" setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr ,State of event EVT60" "Not occurred,Occurred" setclrfld.long 0x04 27. 0x24 27. 0x44 27. " EF59_set/clr ,State of event EVT59" "Not occurred,Occurred" textline " " setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr ,State of event EVT56" "Not occurred,Occurred" setclrfld.long 0x04 23. 0x24 23. 0x44 23. " EF55_set/clr ,State of event EVT55" "Not occurred,Occurred" textline " " setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr ,State of event EVT54" "Not occurred,Occurred" setclrfld.long 0x04 21. 0x24 21. 0x44 21. " EF53_set/clr ,State of event EVT53" "Not occurred,Occurred" textline " " setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr ,State of event EVT51" "Not occurred,Occurred" setclrfld.long 0x04 18. 0x24 18. 0x44 18. " EF50_set/clr ,State of event EVT50" "Not occurred,Occurred" textline " " setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr ,State of event EVT49" "Not occurred,Occurred" setclrfld.long 0x04 16. 0x24 16. 0x44 16. " EF48_set/clr ,State of event EVT48" "Not occurred,Occurred" textline " " setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr ,State of event EVT47" "Not occurred,Occurred" setclrfld.long 0x04 11. 0x24 11. 0x44 11. " EF43_set/clr ,State of event EVT43" "Not occurred,Occurred" textline " " setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr ,State of event EVT41" "Not occurred,Occurred" setclrfld.long 0x04 8. 0x24 8. 0x44 8. " EF40_set/clr ,State of event EVT40" "Not occurred,Occurred" textline " " setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr ,State of event EVT39" "Not occurred,Occurred" setclrfld.long 0x04 6. 0x24 6. 0x44 6. " EF38_set/clr ,State of event EVT38" "Not occurred,Occurred" textline " " setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr ,State of event EVT37" "Not occurred,Occurred" setclrfld.long 0x04 4. 0x24 4. 0x44 4. " EF36_set/clr ,State of event EVT36" "Not occurred,Occurred" textline " " setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr ,State of event EVT35" "Not occurred,Occurred" setclrfld.long 0x04 2. 0x24 2. 0x44 2. " EF34_set/clr ,State of event EVT34" "Not occurred,Occurred" line.long 0x08 "EVTFLAG2,Event Flag Register 2" setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr ,State of event EVT85" "Not occurred,Occurred" setclrfld.long 0x08 20. 0x28 20. 0x48 20. " EF84_set/clr ,State of event EVT84" "Not occurred,Occurred" textline " " setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr ,State of event EVT83" "Not occurred,Occurred" setclrfld.long 0x08 18. 0x28 18. 0x48 18. " EF82_set/clr ,State of event EVT82" "Not occurred,Occurred" textline " " setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr ,State of event EVT81" "Not occurred,Occurred" setclrfld.long 0x08 16. 0x28 16. 0x48 16. " EF80_set/clr ,State of event EVT80" "Not occurred,Occurred" textline " " setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr ,State of event EVT78" "Not occurred,Occurred" setclrfld.long 0x08 13. 0x28 13. 0x48 13. " EF77_set/clr ,State of event EVT77" "Not occurred,Occurred" textline " " setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr ,State of event EVT76" "Not occurred,Occurred" setclrfld.long 0x08 11. 0x28 11. 0x48 11. " EF75_set/clr ,State of event EVT75" "Not occurred,Occurred" textline " " setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr ,State of event EVT74" "Not occurred,Occurred" setclrfld.long 0x08 9. 0x28 9. 0x48 9. " EF73_set/clr ,State of event EVT73" "Not occurred,Occurred" textline " " setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr ,State of event EVT72" "Not occurred,Occurred" setclrfld.long 0x08 7. 0x28 7. 0x48 7. " EF71_set/clr ,State of event EVT71" "Not occurred,Occurred" textline " " setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr ,State of event EVT70" "Not occurred,Occurred" setclrfld.long 0x08 5. 0x28 5. 0x48 5. " EF69_set/clr ,State of event EVT69" "Not occurred,Occurred" textline " " setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr ,State of event EVT68" "Not occurred,Occurred" setclrfld.long 0x08 3. 0x28 3. 0x48 3. " EF67_set/clr ,State of event EVT67" "Not occurred,Occurred" textline " " setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr ,State of event EVT66" "Not occurred,Occurred" setclrfld.long 0x08 1. 0x28 1. 0x48 1. " EF65_set/clr ,State of event EVT65" "Not occurred,Occurred" textline " " setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr ,State of event EVT64" "Not occurred,Occurred" line.long 0x0c "EVTFLAG3,Event Flag Register 3" setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred" setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. " EF126_set/clr ,State of event EVT126" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred" setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. " EF124_set/clr ,State of event EVT124" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred" setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. " EF122_set/clr ,State of event EVT122" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred" setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. " EF120_set/clr ,State of event EVT120" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred" setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. " EF118_set/clr ,State of event EVT118" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred" setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. " EF116_set/clr ,State of event EVT116" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred" setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. " EF97_set/clr ,State of event EVT97" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr ,State of event EVT96" "Not occurred,Occurred" width 11. group.long 0x80++0xf line.long 0x00 "EVTMASK0,Event Mask Register 0" bitfld.long 0x00 14. " EM14 ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 13. " EM13 ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 12. " EM12 ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " EM11 ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 9. " EM9 ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 8. " EM8 ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " EM7 ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 6. " EM6 ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 5. " EM5 ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " EM4 ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 3. " EM3 ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 2. " EM2 ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " EM1 ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 0. " EM0 ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled" line.long 0x04 "EVTMASK1,Event Mask Register 1" bitfld.long 0x04 28. " EM60 ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 27. " EM59 ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 24. " EM56 ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " EM55 ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 22. " EM54 ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 21. " EM53 ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " EM51 ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 18. " EM50 ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 17. " EM49 ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " EM48 ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 15. " EM47 ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 11. " EM43 ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " EM41 ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 8. " EM40 ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 7. " EM39 ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " EM38 ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 5. " EM37 ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 4. " EM36 ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " EM35 ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 2. " EM34 ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled" line.long 0x08 "EVTMASK2,Event Mask Register 2" bitfld.long 0x08 21. " EM85 ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 20. " EM84 ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 19. " EM83 ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " EM82 ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 17. " EM81 ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 16. " EM80 ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " EM78 ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 13. " EM77 ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 12. " EM76 ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " EM75 ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 10. " EM74 ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 9. " EM73 ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " EM72 ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 7. " EM71 ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 6. " EM70 ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " EM69 ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 4. " EM68 ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 3. " EM67 ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " EM66 ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 1. " EM65 ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 0. " EM64 ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled" line.long 0x0c "EVTMASK3,Event Mask Register 3" bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 30. " EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 29. " EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 27. " EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 26. " EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 24. " EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 23. " EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 21. " EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 20. " EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 1. " EM97 ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 0. " EM96 ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled" group.long 0xc0++0xf line.long 0x00 "EXPMASK0,Exception Mask Register 0" bitfld.long 0x00 14. " XM14 ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 13. " XM13 ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 12. " XM12 ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " XM11 ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 9. " XM9 ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 8. " XM8 ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " XM7 ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 6. " XM6 ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 5. " XM5 ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " XM4 ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 3. " XM3 ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 2. " XM2 ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " XM1 ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 0. " XM0 ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x04 "EXPMASK1,Exception Mask Register 1" bitfld.long 0x04 28. " XM60 ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 27. " XM59 ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 24. " XM56 ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " XM55 ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 22. " XM54 ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 21. " XM53 ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " XM51 ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 18. " XM50 ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 17. " XM49 ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " XM48 ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 15. " XM47 ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 11. " XM43 ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " XM41 ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 8. " XM40 ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 7. " XM39 ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " XM38 ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 5. " XM37 ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 4. " XM36 ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " XM35 ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 2. " XM34 ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x08 "EXPMASK2,Exception Mask Register 2" bitfld.long 0x08 21. " XM85 ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 20. " XM84 ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 19. " XM83 ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " XM82 ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 17. " XM81 ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 16. " XM80 ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " XM78 ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 13. " XM77 ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 12. " XM76 ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " XM75 ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 10. " XM74 ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 9. " XM73 ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " XM72 ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 7. " XM71 ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 6. " XM70 ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " XM69 ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 4. " XM68 ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 3. " XM67 ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " XM66 ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 1. " XM65 ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 0. " XM64 ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x0c "EXPMASK3,Exception Mask Register 3" bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 30. " XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 29. " XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 27. " XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 26. " XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 24. " XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 23. " XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 21. " XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 20. " XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 1. " XM97 ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 0. " XM96 ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled" width 11. rgroup.long 0xa0++0xf line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0" hexmask.long 0x00 0.--31. 1. " MEF[31:0] ,Displays content of EF when EM=0" line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1" hexmask.long 0x04 0.--31. 1. " MEF[63:32] ,Displays content of EF when EM=0" line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2" hexmask.long 0x08 0.--31. 1. " MEF[95:64] ,Displays content of EF when EM=0" line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3" hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0" rgroup.long 0xe0++0xf line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0" line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1" line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2" line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3" width 11. group.long 0x104++0xb line.long 0x00 "INTMUX1,Interrupt Mux Register 1" hexmask.long.byte 0x00 24.--30. 1. " INTSEL7 ,Number of the event that maps to CPUINT7" hexmask.long.byte 0x00 16.--22. 1. " INTSEL6 ,Number of the event that maps to CPUINT6" hexmask.long.byte 0x00 8.--14. 1. " INTSEL5 ,Number of the event that maps to CPUINT5" hexmask.long.byte 0x00 0.--6. 1. " INTSEL4 ,Number of the event that maps to CPUINT4" line.long 0x04 "INTMUX2,Interrupt Mux Register 2" hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11" hexmask.long.byte 0x04 16.--22. 1. " INTSEL10 ,Number of the event that maps to CPUINT10" hexmask.long.byte 0x04 8.--14. 1. " INTSEL9 ,Number of the event that maps to CPUINT9" hexmask.long.byte 0x04 0.--6. 1. " INTSEL8 ,Number of the event that maps to CPUINT8" line.long 0x08 "INTMUX3,Interrupt Mux Register 3" hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15" hexmask.long.byte 0x08 16.--22. 1. " INTSEL14 ,Number of the event that maps to CPUINT14" hexmask.long.byte 0x08 8.--14. 1. " INTSEL13 ,Number of the event that maps to CPUINT13" hexmask.long.byte 0x08 0.--6. 1. " INTSEL12 ,Number of the event that maps to CPUINT12" rgroup.long 0x180++0x3 line.long 0x00 "INTXSTAT,Interrupt Exception Status Register" hexmask.long.byte 0x00 24.--31. 1. " SYSINT ,System Event number" hexmask.long.byte 0x00 16.--23. 1. " CPUINT ,CPU interrupt number" bitfld.long 0x00 0. " DROP ,Dropped event flag" "No event dropped,Event dropped" width 11. wgroup.long 0x184++0x3 line.long 0x00 "INTXCLR,Interrupt Exception Clear Register" bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared" rgroup.long 0x188++0x3 line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register" bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 14. " IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 13. " IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 11. " IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 10. " IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 9. " IDM9 ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 8. " IDM8 ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 7. " IDM7 ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 6. " IDM6 ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 5. " IDM5 ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 4. " IDM4 ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored" width 11. group.long 0x140++0x07 line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers" hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select" hexmask.long.byte 0x00 16.--23. 1. " AEGSEL2 ,Advanced Event Generator Select" hexmask.long.byte 0x00 8.--15. 1. " AEGSEL1 ,Advanced Event Generator Select" hexmask.long.byte 0x00 0.--7. 1. " AEGSEL0 ,Advanced Event Generator Select" line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers" hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select" hexmask.long.byte 0x04 16.--23. 1. " AEGSEL6 ,Advanced Event Generator Select" hexmask.long.byte 0x04 8.--15. 1. " AEGSEL5 ,Advanced Event Generator Select" hexmask.long.byte 0x04 0.--7. 1. " AEGSEL4 ,Advanced Event Generator Select" width 0xb tree.end tree "Power-Down Controller" width 8. base d:0x01810000 group.long 0x00++0x3 line.long 0x00 "PDCCMD,Power-Down Controller Command Register" bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode" width 0xb tree.end tree.end AUTOINDENT.POP endif AUTOINDENT.ON center tree tree "_32_kHz_Synchronized_Timer_COUNTER_32K_" base ad:0x4AE04000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,This register contains the sync counter IP revision code" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,This register is used for idle modes only" hexmask.long 0x00 5.--31. 1. "Reserved,Reads return 0" bitfld.long 0x00 3.--4. "IDLEMODE,Power management REQ/ACK control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 1.--2. "Reserved,Reads return 0" "0,1,2,3" bitfld.long 0x00 0. "SYNCMODE,Synchronization scheme - 0x0 Gray synchronization scheme" "0,1" rgroup.long 0x30++0x03 line.long 0x00 "CR,This register contains the 32-kHz sync counter value" width 0x0B tree.end tree "BB2D" base ad:0x59000000 group.long 0x00++0x37 line.long 0x00 "AQHICLOCKCONTROL,Clock control register" bitfld.long 0x00 24.--27. "MULTI_PIPE_USE_SINGLE_AXI,Force all the transactions to go to one AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "MULTI_PIPE_REG_SELECT,Determines which HI/MC to use while reading registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "ISOLATE_GPU,Isolate GPU bit" "0,1" newline rbitfld.long 0x00 18. "IDLE_VG,VG pipe is idle" "0,1" newline rbitfld.long 0x00 17. "IDLE2_D,2D pipe is idle" "0,1" newline rbitfld.long 0x00 16. "IDLE3_D,3D pipe is idle" "0,1" newline bitfld.long 0x00 12. "SOFT_RESET,Soft resets the subsystem" "0,1" newline bitfld.long 0x00 11. "DISABLE_DEBUG_REGISTERS,Disable debug registers" "0,1" newline bitfld.long 0x00 10. "DISABLE_RAM_CLOCK_GATING,Disables clock gating for RAMs" "0,1" newline bitfld.long 0x00 9. "FSCALE_CMD_LOAD," "0,1" newline hexmask.long.byte 0x00 2.--8. 1. "FSCALE_VAL," newline bitfld.long 0x00 1. "CLK2D_DIS,Disable 2D clock" "0,1" newline bitfld.long 0x00 0. "CLK3D_DIS,Disable 3D clock" "0,1" line.long 0x04 "AQHIIDLE,Idle status register" bitfld.long 0x04 31. "AXI_LP,AXI is in low power mode" "0,1" newline bitfld.long 0x04 11. "IDLE_TS,TS is idle" "0,1" newline bitfld.long 0x04 10. "IDLE_FP,FP is idle" "0,1" newline bitfld.long 0x04 9. "IDLE_IM,IM is idle" "0,1" newline bitfld.long 0x04 8. "IDLE_VG,VG is idle" "0,1" newline bitfld.long 0x04 7. "IDLE_TX,TX is idle" "0,1" newline bitfld.long 0x04 6. "IDLE_RA,RA is idle" "0,1" newline bitfld.long 0x04 5. "IDLE_SE,SE is idle" "0,1" newline bitfld.long 0x04 4. "IDLE_PA,PA is idle" "0,1" newline bitfld.long 0x04 3. "IDLE_SH,SH is idle" "0,1" newline bitfld.long 0x04 2. "IDLE_PE,PE is idle" "0,1" newline bitfld.long 0x04 1. "IDLE_DE,DE is idle" "0,1" newline bitfld.long 0x04 0. "IDLE_FE,FE is idle" "0,1" line.long 0x08 "AQAXICONFIG,AXI config" bitfld.long 0x08 12.--15. "ARCACHE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. "AWCACHE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 4.--7. "ARID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "AWID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "AQAXISTATUS,AXI status" bitfld.long 0x0C 9. "DET_RD_ERR," "0,1" newline bitfld.long 0x0C 8. "DET_WR_ERR," "0,1" newline bitfld.long 0x0C 4.--7. "RD_ERR_ID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "WR_ERR_ID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "AQINTRACKNOWLEDGE,Interrupt acknowledge register" line.long 0x14 "AQINTRENBL,Interrupt enable register" line.long 0x18 "AQIDENT,Identification register" abitfld.long 0x18 24.--31. "FAMILY,Family value" "0x01=GC500,0x02=GC520,0x03=GC530,0x04=GC400,0x05=GC450,0x08=GC600,0x09=GC700,0x0A=GC350,0x0B=GC380,0x0C=GC800,0x10=GC1000,0x14=GC2000" newline hexmask.long.byte 0x18 16.--23. 1. "PRODUCT,Product value" newline bitfld.long 0x18 12.--15. "REVISION,Revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 8.--11. "TECHNOLOGY,Technology value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 0.--7. 1. "CUSTOMER,Customer value" line.long 0x1C "GCFEATURES,Shows which features are enabled in current subsystem implementation" bitfld.long 0x1C 31. "FE20_BIT_INDEX,Supports 20 bit index" "0,1" newline bitfld.long 0x1C 30. "RS_YUV_TARGET,Supports resolveing into YUV target" "0,1" newline bitfld.long 0x1C 29. "BYTE_WRITE_3D,3D PE has byte write capability" "0,1" newline bitfld.long 0x1C 28. "FE20,FE 2.0 is present" "0,1" newline bitfld.long 0x1C 27. "VGTS,VG tesselator is present" "0,1" newline bitfld.long 0x1C 26. "PIPE_VG,VG pipe is present" "0,1" newline bitfld.long 0x1C 25. "MEM32_BIT_SUPPORT,32 bit memory address support" "0,1" newline bitfld.long 0x1C 24. "YUY2_RENDER_TARGET,YUY2 support in PE and YUY2 to RGB conversion in resolve" "0,1" newline bitfld.long 0x1C 23. "HALF_TX_CACHE,TX cache is half" "0,1" newline bitfld.long 0x1C 22. "HALF_PE_CACHE,PE cache is half" "0,1" newline bitfld.long 0x1C 21. "YUY2_AVERAGING,YUY2 averaging support in resolve" "0,1" newline bitfld.long 0x1C 20. "NO_SCALER,No 2D scaler" "0,1" newline bitfld.long 0x1C 19. "BYTE_WRITE_2D,Supports byte write in 2D" "0,1" newline bitfld.long 0x1C 18. "BUFFER_INTERLEAVING,Supports interleaving depth and color buffers" "0,1" newline bitfld.long 0x1C 17. "NO422_TEXTURE,No 422 texture input format" "0,1" newline bitfld.long 0x1C 16. "NO_EZ,No early-Z" "0,1" newline bitfld.long 0x1C 15. "MIN_AREA,Configured to have minimum area" "0,1" newline bitfld.long 0x1C 14. "MODULE_CG,Second level clock gating is available" "0,1" newline bitfld.long 0x1C 13. "YUV420_TILER,YUV 4:2:0 tiler is available" "0,1" newline bitfld.long 0x1C 12. "HIGH_DYNAMIC_RANGE,Shows if there is HDR support" "0,1" newline bitfld.long 0x1C 11. "FAST_SCALER,Shows if there is HD scaler" "0,1" newline bitfld.long 0x1C 10. "ETC1_TEXTURE_COMPRESSION,ETC1 texture compression" "0,1" newline bitfld.long 0x1C 9. "PIPE_2D,Shows if there is 2D engine" "0,1" newline bitfld.long 0x1C 8. "DC,Shows if there is a display controller" "0,1" newline bitfld.long 0x1C 7. "MSAA,MSAA support" "0,1" newline bitfld.long 0x1C 6. "YUV420_FILTER,YUV 4:2:0 support in filter blit" "0,1" newline bitfld.long 0x1C 5. "ZCOMPRESSION,Depth and color compression" "0,1" newline bitfld.long 0x1C 4. "DEBUG_MODE,Debug registers" "0,1" newline bitfld.long 0x1C 3. "DXT_TEXTURE_COMPRESSION,DXT texture compression" "0,1" newline bitfld.long 0x1C 2. "PIPE_3D,3D pipe" "0,1" newline bitfld.long 0x1C 1. "SPECIAL_ANTI_ALIASING,Full-screen anti-aliasing" "0,1" newline bitfld.long 0x1C 0. "FAST_CLEAR,Fast clear" "0,1" line.long 0x20 "GCCHIPID,Shows the ID for the subsystem in BCD" line.long 0x24 "GCCHIPREV,Shows the revision for the subsystem in BCD" line.long 0x28 "GCCHIPDATE,Shows the release date for the subsystem" line.long 0x2C "GCCHIPTIME,Shows the release time for the subsystem" line.long 0x30 "GCCHIPCUSTOMER,Shows the customer and group for the subsystem" hexmask.long.word 0x30 16.--31. 1. "COMPANY,Company" newline hexmask.long.word 0x30 0.--15. 1. "GROUP,Group" line.long 0x34 "GCMINORFEATURES0,Shows which minor features are enabled in the subsystem" bitfld.long 0x34 31. "ENHANCE_VR,Enhance VR and add a mode to walk 16 pixels in 16-bit mode in vertical pass to improve cache hit rate when rotating 90/270" "0,1" newline bitfld.long 0x34 30. "CORRECT_STENCIL,Correct stencil behavior in depth only" "0,1" newline bitfld.long 0x34 29. "A8_TARGET_SUPPORT,2D engine supports A8 target" "0,1" newline bitfld.long 0x34 28. "NEW_TEXTURE,New texture unit is available" "0,1" newline bitfld.long 0x34 27. "HIERARCHICAL_Z,Hierarchiccal Z is supported" "0,1" newline bitfld.long 0x34 26. "BYPASS_IN_MSAA,Shader supports bypass mode when MSAA is enabled" "0,1" newline bitfld.long 0x34 25. "VAA,VAA is available or not" "0,1" newline bitfld.long 0x34 24. "BUG_FIXES0," "0,1" newline bitfld.long 0x34 23. "SHADER_MSAA_SIDEBAND,Put the MSAA data into sideband fifo" "0,1" newline bitfld.long 0x34 22. "MC_20,New style MC with separate paths for color and depth" "0,1" newline bitfld.long 0x34 21. "DEFAULT_REG0,Unavailable registers will return 0" "0,1" newline bitfld.long 0x34 20. "EXTRA_SHADER_INSTRUCTIONS1,Sqrt sin cos instructions are available" "0,1" newline bitfld.long 0x34 19. "SHADER_GETS_W,W is sent to SH from RA" "0,1" newline bitfld.long 0x34 18. "VG_21,Minor updates to VG pipe (Event generation from VG TS PE)" "0,1" newline bitfld.long 0x34 17. "VG_FILTER,VG filter is available" "0,1" newline bitfld.long 0x34 16. "EXTRA_SHADER_INSTRUCTIONS0,Floor ceil and sign instructions are available" "0,1" newline bitfld.long 0x34 15. "COMPRESSION_FIFO_FIXED,If this bit is not set the FIFO counter should be set to 50" "0,1" newline bitfld.long 0x34 14. "TS_EXTENDED_COMMANDS,New commands added to the tessellator" "0,1" newline bitfld.long 0x34 13. "VG_20,Major updates to VG pipe (TS buffer tiling. State masking.)" "0,1" newline bitfld.long 0x34 12. "SUPER_TILED_32X32,32 x 32 super tile is available" "0,1" newline bitfld.long 0x34 11. "SEPARATE_TILE_STATUS_WHEN_INTERLEAVED,Use 2 separate tile status buffers in interleaved mode" "0,1" newline bitfld.long 0x34 10. "TILE_STATUS_2BITS,2 bits are used instead of 4 bits for tile status" "0,1" newline bitfld.long 0x34 9. "RENDER_8K,Supports 8K render target" "0,1" newline bitfld.long 0x34 8. "CORRECT_AUTO_DISABLE,Reserved" "0,1" newline bitfld.long 0x34 7. "PE20_2D,2D PE 2.0 is present" "0,1" newline bitfld.long 0x34 6. "FAST_CLEAR_FLUSH,Proper flush is done in fast clear cache" "0,1" newline bitfld.long 0x34 5. "SPECIAL_MSAA_LOD,Special LOD calculation when MSAA is on" "0,1" newline bitfld.long 0x34 4. "CORRECT_TEXTURE_CONVERTER,Driver hack is not needed" "0,1" newline bitfld.long 0x34 3. "TEXTURE8_K,Supports 8K x 8K textures" "0,1" newline bitfld.long 0x34 2. "ENDIANNESS_CONFIG,Configurable endianness support" "0,1" newline bitfld.long 0x34 1. "DUAL_RETURN_BUS,Dual Return Bus from HI to clients" "0,1" newline bitfld.long 0x34 0. "FLIP_Y,Y flipping capability is added to resolve" "0,1" group.long 0x3C++0x2B line.long 0x00 "GCRESETMEMCOUNTERS,Writing 1 will reset the counters and stop counting" bitfld.long 0x00 0. "RESET," "0,1" line.long 0x04 "GCTOTALREADS,Total reads in terms of 64 bits" line.long 0x08 "GCTOTALWRITES,Total writes in terms of 64 bits" line.long 0x0C "GCCHIPSPECS,Specs for the subsystem" bitfld.long 0x0C 28.--31. "VERTEX_OUTPUT_BUFFER_SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 25.--27. "NUM_PIXEL_PIPES," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--24. "NUM_SHADER_CORES," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 12.--16. "VERTEX_CACHE_SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 8.--11. "THREAD_COUNT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 4.--7. "TEMP_REGISTERS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "STREAMS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "GCTOTALWRITEBURSTS,Total write data count in terms of 64 bits" line.long 0x14 "GCTOTALWRITEREQS,Total write request count" line.long 0x18 "GCTOTALWRITELASTS,Total WLAST count" line.long 0x1C "GCTOTALREADBURSTS,Total read data count in terms of 64 bits" line.long 0x20 "GCTOTALREADREQS,Total read request count" line.long 0x24 "GCTOTALREADLASTS,Total RLAST count" line.long 0x28 "GCGPOUT0,General purpose output register" bitfld.long 0x28 0. "GCHOLD," "0,1" group.long 0x70++0x17 line.long 0x00 "GCAXICONTROL,Special handling on AXI Bus" bitfld.long 0x00 0. "WR_FULL_BURST_MODE," "0,1" line.long 0x04 "GCMINORFEATURES1,Shows which features are enabled in the subsystem" bitfld.long 0x04 31. "FC_FLUSH_STALL," "0,1" newline bitfld.long 0x04 30. "BUG_FIXES6," "0,1" newline bitfld.long 0x04 29. "WIDE_LINE," "0,1" newline bitfld.long 0x04 28. "MMU," "0,1" newline bitfld.long 0x04 27. "OK_TO_GATE_AXI_CLOCK," "0,1" newline bitfld.long 0x04 26. "RESOLVE_OFFSET," "0,1" newline bitfld.long 0x04 25. "NEGATIVE_LOG_FIX," "0,1" newline bitfld.long 0x04 24. "CORRECT_OVERFLOW_VG," "0,1" newline bitfld.long 0x04 23. "HALTI0," "0,1" newline bitfld.long 0x04 22. "LINEAR_TEXTURE_SUPPORT," "0,1" newline bitfld.long 0x04 21. "NON_POWER_OF_TWO," "0,1" newline bitfld.long 0x04 20. "TEXTURE_HORIZONTAL_ALIGNMENT_SELECT," "0,1" newline bitfld.long 0x04 19. "NEW_FLOATING_POINT_ARITHMETIC," "0,1" newline bitfld.long 0x04 18. "NEW_2D," "0,1" newline bitfld.long 0x04 17. "BUG_FIXES5," "0,1" newline bitfld.long 0x04 16. "DITHER_AND_FILTER_PLUS_ALPHA_2D,Dither and filter+alpha available" "0,1" newline bitfld.long 0x04 15. "CORRECT_MIN_MAX_DEPTH,EEZ and HZ are correct" "0,1" newline bitfld.long 0x04 14. "EXTENDED_PIXEL_FORMAT," "0,1" newline bitfld.long 0x04 13. "TWO_STENCIL_REFERENCE," "0,1" newline bitfld.long 0x04 12. "PIXEL_DITHER," "0,1" newline bitfld.long 0x04 11. "HALF_FLOAT_PIPE," "0,1" newline bitfld.long 0x04 10. "L2_WINDOWING," "0,1" newline bitfld.long 0x04 9. "BUG_FIXES4," "0,1" newline bitfld.long 0x04 8. "AUTO_RESTART_TS," "0,1" newline bitfld.long 0x04 7. "CORRECT_AUTO_DISABLE," "0,1" newline bitfld.long 0x04 6. "BUG_FIXES3," "0,1" newline bitfld.long 0x04 5. "TEXTURE_STRIDE,Texture has stride and memory addressing" "0,1" newline bitfld.long 0x04 4. "BUG_FIXES2," "0,1" newline bitfld.long 0x04 3. "BUG_FIXES1," "0,1" newline bitfld.long 0x04 2. "VG_DOUBLE_BUFFER,Double buffering support for VG (second TS-->VG semaphore is present)" "0,1" newline bitfld.long 0x04 1. "V2_COMPRESSION,V2 compression" "0,1" newline bitfld.long 0x04 0. "RSUV_SWIZZLE,Resolve UV swizzle" "0,1" line.long 0x08 "GCTOTALCYCLES,Total cycles" line.long 0x0C "GCTOTALIDLECYCLES,Total cycles where the GPU is idle" line.long 0x10 "GCCHIPSPECS2,Specs for the subsystem" hexmask.long.word 0x10 16.--31. 1. "NUMBER_OF_CONSTANTS," newline hexmask.long.byte 0x10 8.--15. 1. "INSTRUCTION_COUNT," newline hexmask.long.byte 0x10 0.--7. 1. "BUFFER_SIZE," line.long 0x14 "GCMINORFEATURES2,Shows which features are enabled in the subsystem" bitfld.long 0x14 28. "NO_INDEX_PATTERN," "0,1" newline bitfld.long 0x14 26. "NOT_USED," "0,1" newline bitfld.long 0x14 25. "MIXED_STREAMS," "0,1" newline bitfld.long 0x14 24. "INTERLEAVER," "0,1" newline bitfld.long 0x14 23. "FLUSH_FIXED_2D," "0,1" newline bitfld.long 0x14 22. "YUV_CONVERSION," "0,1" newline bitfld.long 0x14 21. "MULTI_SOURCE_BLT," "0,1" newline bitfld.long 0x14 20. "YUV_STANDARD," "0,1" newline bitfld.long 0x14 19. "TILE_FILLER," "0,1" newline bitfld.long 0x14 18. "THREAD_WALKER_IN_PS," "0,1" newline bitfld.long 0x14 17. "ONE_PASS_2D_FILTER," "0,1" newline bitfld.long 0x14 16. "FULL_DIRECT_FB," "0,1" newline bitfld.long 0x14 15. "TX_FILTER," "0,1" newline bitfld.long 0x14 14. "DYNAMIC_FREQUENCY_SCALING," "0,1" newline bitfld.long 0x14 13. "TX_YUV_ASSEMBLER," "0,1" newline bitfld.long 0x14 12. "RGB888," "0,1" newline bitfld.long 0x14 11. "HALTI1," "0,1" newline bitfld.long 0x14 10. "S1S8," "0,1" newline bitfld.long 0x14 9. "END_EVENT," "0,1" newline bitfld.long 0x14 8. "PE_SWIZZLE," "0,1" newline bitfld.long 0x14 7. "CORRECT_AUTO_DISABLE_COUNT_WIDTH," "0,1" newline bitfld.long 0x14 6. "COMPOSITION," "0,1" newline bitfld.long 0x14 5. "RECT_PRIMITIVE," "0,1" newline bitfld.long 0x14 4. "LINEAR_PE," "0,1" newline bitfld.long 0x14 3. "SUPER_TILED_TEXTURE," "0,1" newline bitfld.long 0x14 2. "SEAMLESS_CUBE_MAP," "0,1" newline bitfld.long 0x14 1. "LOGIC_OP," "0,1" newline bitfld.long 0x14 0. "LINE_LOOP," "0,1" group.long 0x100++0x0B line.long 0x00 "GCMODULEPOWERCONTROLS,Control register for module level power controls" hexmask.long.word 0x00 16.--31. 1. "TURN_OFF_COUNTER,Counter value for clock gating the module if the module is idle for this amount of clock cycles" newline bitfld.long 0x00 4.--7. "TURN_ON_COUNTER,Number of clock cycles to wait after turning on the clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. "DISABLE_STARVE_MODULE_CLOCK_GATING,Disables module level clock gating for starve/idle condition" "0,1" newline bitfld.long 0x00 1. "DISABLE_STALL_MODULE_CLOCK_GATING,Disables module level clock gating for stall condition" "0,1" newline bitfld.long 0x00 0. "ENABLE_MODULE_CLOCK_GATING,Enables module level clock gating" "0,1" line.long 0x04 "GCMODULEPOWERMODULECONTROL,Module level control registers" bitfld.long 0x04 7. "DISABLE_MODULE_CLOCK_GATING_TX,Disables module level clock gating for starve/idle condition" "0,1" newline bitfld.long 0x04 6. "DISABLE_MODULE_CLOCK_GATING_RA,Disables module level clock gating for stall condition" "0,1" newline bitfld.long 0x04 5. "DISABLE_MODULE_CLOCK_GATING_SE,Enables module level clock gating" "0,1" newline bitfld.long 0x04 4. "DISABLE_MODULE_CLOCK_GATING_PA,Counter value for clock gating the module if the module is idle for this amount of clock cycles" "0,1" newline bitfld.long 0x04 3. "DISABLE_MODULE_CLOCK_GATING_SH,Number of clock cycles to wait after turning on the clock" "0,1" newline bitfld.long 0x04 2. "DISABLE_MODULE_CLOCK_GATING_PE,Disables module level clock gating for starve/idle condition" "0,1" newline bitfld.long 0x04 1. "DISABLE_MODULE_CLOCK_GATING_DE,Disables module level clock gating for stall condition" "0,1" newline bitfld.long 0x04 0. "DISABLE_MODULE_CLOCK_GATING_FE,Enables module level clock gating" "0,1" line.long 0x08 "GCMODULEPOWERMODULESTATUS,Module level control status" bitfld.long 0x08 7. "MODULE_CLOCK_GATED_TX,Module level clock gating is ON for TX" "0,1" newline bitfld.long 0x08 6. "MODULE_CLOCK_GATED_RA,Module level clock gating is ON for RA" "0,1" newline bitfld.long 0x08 5. "MODULE_CLOCK_GATED_SE,Module level clock gating is ON for SE" "0,1" newline bitfld.long 0x08 4. "MODULE_CLOCK_GATED_PA,Module level clock gating is ON for PA" "0,1" newline bitfld.long 0x08 3. "MODULE_CLOCK_GATED_SH,Module level clock gating is ON for SH" "0,1" newline bitfld.long 0x08 2. "MODULE_CLOCK_GATED_PE,Module level clock gating is ON for PE" "0,1" newline bitfld.long 0x08 1. "MODULE_CLOCK_GATED_DE,Module level clock gating is ON for DE" "0,1" newline bitfld.long 0x08 0. "MODULE_CLOCK_GATED_FE,Module level clock gating is ON for FE" "0,1" rgroup.long 0x188++0x07 line.long 0x00 "GCREGMMUSTATUS,Status register that holds which MMU generated an exception" bitfld.long 0x00 12.--13. "EXCEPTION3,MMU 3 caused an exception and theGCREGMMUEXCEPTION3 register holds the offending address" "?,SLAVE_NOT_PRESENT,PAGE_NOT_PRESENT,WRITE_VIOLATION" newline bitfld.long 0x00 8.--9. "EXCEPTION2,MMU 2 caused an exception and theGCREGMMUEXCEPTION2 register holds the offending address" "?,SLAVE_NOT_PRESENT,PAGE_NOT_PRESENT,WRITE_VIOLATION" newline bitfld.long 0x00 4.--5. "EXCEPTION1,MMU 1 caused an exception and theGCREGMMUEXCEPTION1 register holds the offending address" "?,SLAVE_NOT_PRESENT,PAGE_NOT_PRESENT,WRITE_VIOLATION" newline bitfld.long 0x00 0.--1. "EXCEPTION0,MMU 0 caused an exception and theGCREGMMUEXCEPTION0 holds the offending address" "?,SLAVE_NOT_PRESENT,PAGE_NOT_PRESENT,WRITE_VIOLATION" line.long 0x04 "GCREGMMUCONTROL,Control register that enables the MMU (one time shot)" bitfld.long 0x04 0. "ENABLE,Enable the MMU" "0,1" group.long 0x414++0x03 line.long 0x00 "AQMEMORYDEBUG," bitfld.long 0x00 30. "DONT_STALL_WRITES_TO_SAME_ADDRESS," "0,1" newline bitfld.long 0x00 24.--29. "ZCOMP_LIMIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. "DISABLE_WRITE_DATA_SPEEDUP," "0,1" newline bitfld.long 0x00 22. "DISABLE_STALL_READS," "0,1" newline bitfld.long 0x00 19. "LIMIT_CONTROL,Limit control" "REQUESTS,DATA" newline bitfld.long 0x00 17. "INTERLEAVE_BUFFER_LOW_LATENCY_MODE," "0,1" newline bitfld.long 0x00 14. "DISABLE_MINI_MMU_CACHE," "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_OUTSTANDING_READS,Limits the total number of outstanding read requests" group.long 0x42C++0x03 line.long 0x00 "AQREGISTERTIMINGCONTROL," bitfld.long 0x00 22. "LIGHT_SLEEP,Light sleep" "0,1" newline bitfld.long 0x00 21. "DEEP_SLEEP,Deep sleep" "0,1" newline bitfld.long 0x00 20. "POWER_DOWN,Powerdown memory" "0,1" newline bitfld.long 0x00 18.--19. "FAST_WTC,WTC for fast RAMs" "0,1,2,3" newline bitfld.long 0x00 16.--17. "FAST_RTC,RTC for fast RAMs" "0,1,2,3" newline hexmask.long.byte 0x00 8.--15. 1. "FOR_RF2P," newline hexmask.long.byte 0x00 0.--7. 1. "FOR_RF1P," group.long 0x434++0x63 line.long 0x00 "GCDISPLAYPRIORITY,Controls the priority of the display controller requests" hexmask.long.byte 0x00 8.--15. 1. "HIGH,'Duty cycle'" newline hexmask.long.byte 0x00 0.--7. 1. "PERIOD,Period" line.long 0x04 "GCDBGCYCLECOUNTER,Increments every cycle" line.long 0x08 "GCOUTSTANDINGREADS0,Number of outstanding reads per client in multiples of 8 bytes" hexmask.long.byte 0x08 24.--31. 1. "MMU,Number of outstanding MMU reads in multiples of 8 bytes" newline hexmask.long.byte 0x08 16.--23. 1. "FE,Number of outstanding FE reads in multiples of 8 bytes" newline hexmask.long.byte 0x08 8.--15. 1. "PEZ,Number of outstanding PEZ reads in multiples of 8 bytes" newline hexmask.long.byte 0x08 0.--7. 1. "PEC,Number of outstanding PEC reads in multiples of 8 bytes" line.long 0x0C "GCOUTSTANDINGREADS1,Number of outstanding reads per client in multiples of 8 bytes" hexmask.long.byte 0x0C 24.--31. 1. "TOTAL,This field keeps the value of total read requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field" newline hexmask.long.byte 0x0C 16.--23. 1. "FC,Number of outstanding FC reads in multiples of 8 bytes" newline hexmask.long.byte 0x0C 8.--15. 1. "TX,Number of outstanding TX reads in multiples of 8 bytes" newline hexmask.long.byte 0x0C 0.--7. 1. "RA,Number of outstanding RA reads in multiples of 8 bytes" line.long 0x10 "GCOUTSTANDINGWRITES,Number of outstanding writes per client" hexmask.long.byte 0x10 24.--31. 1. "TOTAL,This field keeps the value of total write requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field" newline hexmask.long.byte 0x10 16.--23. 1. "FC,Number of outstanding FC writes in multiples of 8 bytes" newline hexmask.long.byte 0x10 8.--15. 1. "PEZ,Number of outstanding PEZ writes in multiples of 8 bytes" newline hexmask.long.byte 0x10 0.--7. 1. "PEC,Number of outstanding PEC writes in multiples of 8 bytes" line.long 0x14 "GCDEBUGSIGNALSRA,32 bit debug signal from RA" line.long 0x18 "GCDEBUGSIGNALSTX,32 bit debug signal from TX" line.long 0x1C "GCDEBUGSIGNALSFE,32 bit debug signal from FE" line.long 0x20 "GCDEBUGSIGNALSPE,32 bit debug signal from PE" line.long 0x24 "GCDEBUGSIGNALSDE,32 bit debug signal from DE" line.long 0x28 "GCDEBUGSIGNALSSH,32 bit debug signal from SH" line.long 0x2C "GCDEBUGSIGNALSPA,32 bit debug signal from PA" line.long 0x30 "GCDEBUGSIGNALSSE,32 bit debug signal from SE" line.long 0x34 "GCDEBUGSIGNALSMC,32 bit debug signal from MC" line.long 0x38 "GCDEBUGSIGNALSHI,32 bit debug signal from HI" line.long 0x3C "GCDEBUGCONTROL0," bitfld.long 0x3C 24.--27. "SH,Selects which set of 32 bit data to get from SH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 16.--19. "PE,Selects which set of 32 bit data to get from PE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 8.--11. "DE,Selects which set of 32 bit data to get from DE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 0.--3. "FE,Selects which set of 32 bit data to get from FE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "GCDEBUGCONTROL1," bitfld.long 0x40 24.--27. "TX,Selects which set of 32 bit data to get from TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 16.--19. "RA,Selects which set of 32 bit data to get from RA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 8.--11. "SE,Selects which set of 32 bit data to get from SE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 0.--3. "PA,Selects which set of 32 bit data to get from PA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "GCDEBUGCONTROL2," bitfld.long 0x44 8.--11. "HI,Selects which set of 32 bit data to get from HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x44 0.--3. "MC,Selects which set of 32 bit data to get from MC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "GCDEBUGCONTROL3," bitfld.long 0x48 8.--11. "PROBE1,Selects which module's output will be put in the MSB 32 bits of 64 bit debug signal" "FE,DE,PE,SH,PA,SE,RA,TX,MC,?..." newline bitfld.long 0x48 0.--3. "PROBE0,Selects which module's output will be put in the LSB 32 bits of 64 bit debug signal" "FE,DE,PE,SH,PA,SE,RA,TX,MC,?..." line.long 0x4C "GCBUSCONTROL,Shows which features are enabled in the subsystem" bitfld.long 0x4C 8. "FCC,Select the return bus for FCC" "0,1" newline bitfld.long 0x4C 7. "TX,Select the return bus for TX" "0,1" newline bitfld.long 0x4C 6. "FC,Select the return bus for FC-Depth" "0,1" newline bitfld.long 0x4C 5. "MMU,Select the return bus for MMU" "0,1" newline bitfld.long 0x4C 3. "FE,Select the return bus for FE" "0,1" newline bitfld.long 0x4C 1. "PEZ,Select the return bus for PEZ" "0,1" newline bitfld.long 0x4C 0. "PEC,Select the return bus for PEC" "0,1" line.long 0x50 "GCREGENDIANNESS0," line.long 0x54 "GCREGENDIANNESS1," line.long 0x58 "GCREGENDIANNESS2," line.long 0x5C "GCREGDRAWPRIMITIVESTARTTIMESTAMP," line.long 0x60 "GCREGDRAWPRIMITIVEENDTIMESTAMP," group.long 0x558++0x03 line.long 0x00 "GCREGCONTROL0,Composition trigger" bitfld.long 0x00 26.--31. "MISC1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 16.--25. 1. "OUTSTANDING_READS_PER_CHANNEL," newline hexmask.long.word 0x00 4.--15. 1. "MISC0," newline bitfld.long 0x00 3. "ENABLE_UNALIGNED_WRITE_MERGE," "0,1" newline bitfld.long 0x00 2. "ENABLE_WRITE_MERGE," "0,1" newline bitfld.long 0x00 1. "ENABLE_UNALIGNED_MERGE," "0,1" newline bitfld.long 0x00 0. "ENABLE_READ_MERGE," "0,1" group.long 0x654++0x0B line.long 0x00 "AQCMDBUFFERADDR,Base address for the command buffer" bitfld.long 0x00 31. "TYPE," "0,1" newline hexmask.long 0x00 0.--30. 1. "ADDRESS,ADDRESS" line.long 0x04 "AQCMDBUFFERCTRL,Command buffer control" bitfld.long 0x04 20.--21. "ENDIAN_CONTROL,Endian control" "NO_SWAP,SWAP_WORD,SWAP_DWORD,?..." newline bitfld.long 0x04 16. "ENABLE,Command buffer" "DISABLE,ENABLE" newline hexmask.long.word 0x04 0.--15. 1. "PREFETCH,Number of 64-bit words to fetch from the command buffer" line.long 0x08 "AQFESTATUS,FE status" bitfld.long 0x08 0. "COMMAND_DATA,Status of the command parser" "Idle,Busy" rgroup.long 0x664++0x03 line.long 0x00 "AQFEDEBUGCURCMDADR,This is the command decoder address" hexmask.long 0x00 3.--31. 1. "CUR_CMD_ADR," repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x190)++0x03 line.long 0x00 "GCREGMMUEXCEPTION$1,Holds the original address that generated an exception" repeat.end width 0x0B tree.end tree "CAMSS_Overview" base ad:0x4845B000 group.long 0x130++0x07 line.long 0x00 "CAL_BYS_CTRL1,BYS port control register" bitfld.long 0x00 31. "BYSINEN,Enable/disable the BYS input port Note: the BYS output port is disabled by setting PCLK=0 - DIS" "BYSINEN_0,BYSINEN_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,BYSout port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_BYS_CTRL2,BYS port control register" bitfld.long 0x04 11. "FREERUNNING,Controls PCLK generation when the BYSout state machine is in the IDLE state - NO" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 10. "DUPLICATEDDATA,Control if data sent to the BYS output port should also be send to the DPCM encoder - NO" "DUPLICATEDDATA_0,DUPLICATEDDATA_1" bitfld.long 0x04 5.--9. "CPORTOUT,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "CPORTIN,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x07 line.long 0x00 "CAL_CTRL,Global control register" hexmask.long.byte 0x00 24.--31. 1. "MFLAGH,Refer to section CAL Write DMA Real Time Traffic" bitfld.long 0x00 22. "RD_DMA_STALL,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0" "RD_DMA_STALL_0,RD_DMA_STALL_1" bitfld.long 0x00 21. "PWRSCPCLK,Controls autogating of the PWRSCP clock - AUTO" "PWRSCPCLK_0,PWRSCPCLK_1" newline hexmask.long.byte 0x00 13.--20. 1. "MFLAGL,Refer to section CAL Write DMA Real Time Traffic" bitfld.long 0x00 7.--12. "LL_FORCE_STATE,Forces the state of the CSI-3 low level protocol state machine" "the next OCPI transaction for this CPORT will..,the next OCPI transaction for this CPORT will..,?..." bitfld.long 0x00 5.--6. "BURSTSIZE,Maximum allowed burst size for the write DMA" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 1.--4. "TAGCNT,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "POSTED_WRITES,- NONPOSTED" "POSTED_WRITES_0,POSTED_WRITES_1" line.long 0x04 "CAL_CTRL1,CAL global control register" bitfld.long 0x04 4.--5. "INTERLEAVE23,Controls stream interleaving Context #2 and #3 - DISABLED" "INTERLEAVE23_0,INTERLEAVE23_1,INTERLEAVE23_2,INTERLEAVE23_3" bitfld.long 0x04 2.--3. "INTERLEAVE01,Controls stream interleaving Context #0 and #1 - DISABLED" "INTERLEAVE01_0,INTERLEAVE01_1,INTERLEAVE01_2,INTERLEAVE01_3" bitfld.long 0x04 0.--1. "PPI_GROUPING,Controls PPI grouping - DISABLED" "PPI_GROUPING_0,PPI_GROUPING_1,PPI_GROUPING_2,PPI_GROUPING_3" rgroup.long 0x04++0x03 line.long 0x00 "CAL_HL_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x00 30.--31. "NPPI_CONTEXTS1,Number of contexts for PPI interface #0 - RESERVED" "NPPI_CONTEXTS1_0_r,NPPI_CONTEXTS1_1_r,NPPI_CONTEXTS1_2_r,NPPI_CONTEXTS1_3_r" bitfld.long 0x00 28.--29. "NPPI_CONTEXTS0,Number of contexts for PPI interface #0 - RESERVED" "NPPI_CONTEXTS0_0_r,NPPI_CONTEXTS0_1_r,NPPI_CONTEXTS0_2_r,NPPI_CONTEXTS0_3_r" bitfld.long 0x00 23.--27. "NCPORT,Number of supported CPORTs (including CPORT #0) minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--22. "VFIFO,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--18. "WCTX,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--12. "PCTX,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "RFIFO,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "WFIFO,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" rgroup.long 0x00++0x03 line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration - FORCE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset - NOACTION" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x108++0x03 line.long 0x00 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event" hexmask.long.word 0x00 16.--29. 1. "LINE," bitfld.long 0x00 0.--4. "CPORT,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x03 line.long 0x00 "CAL_RD_DMA_CTRL,Read DMA control register" hexmask.long.tbyte 0x00 15.--31. 1. "PCLK,Controls the data rate at which data is read from the read DMA FIFO and sent to the internal processing pipeline" bitfld.long 0x00 11.--14. "OCP_TAG_CNT,Maximum allowed number of outstanding OCP read requests minus 1 (i.e. 0xF meand up to 16 outstanding requests)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--10. 1. "BW_LIMITER,Defines a minimum cycle count between to consecutive read requests issued by the RD DMA" newline bitfld.long 0x00 1. "INIT,Enable reading of DPCM decoder initialization data from SDRAM - DIS" "INIT_0,INIT_1" bitfld.long 0x00 0. "GO,Start data read from memory" "GO_0_r,GO_1_r" group.long 0x16C++0x03 line.long 0x00 "CAL_RD_DMA_CTRL2,Read DMA control register" hexmask.long.word 0x00 16.--29. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 6. "BYSOUT_LE_WAIT,Controls the behavior of the RD DMA when the line end is reached" "BYSOUT_LE_WAIT_0,BYSOUT_LE_WAIT_1" bitfld.long 0x00 4.--5. "RD_PATTERN,Data read pattern - LINEAR" "RD_PATTERN_0,RD_PATTERN_1,RD_PATTERN_2,RD_PATTERN_3" newline bitfld.long 0x00 3. "ICM_CSTART,Enables monitoring of the ICM_CSTART signal - DIS" "ICM_CSTART_0,ICM_CSTART_1" bitfld.long 0x00 0.--2. "CIRC_MODE,Circular mode control - ONE" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3,CIRC_MODE_4,CIRC_MODE_5,?,?" group.long 0x154++0x03 line.long 0x00 "CAL_RD_DMA_INIT_ADDR,Read address" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" group.long 0x168++0x03 line.long 0x00 "CAL_RD_DMA_INIT_OFST,Byte offset between two consecutive line starts" hexmask.long 0x00 3.--31. 1. "OFST,Offset in words of 8 bytes" group.long 0x144++0x0F line.long 0x00 "CAL_RD_DMA_PIX_ADDR,Byte address of the top left corner of the buffer to read in system memory" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" line.long 0x04 "CAL_RD_DMA_PIX_OFST,Byte offset between two consecutive line starts Shall be 16 byte aligned for YUV420" hexmask.long 0x04 4.--31. 1. "OFST,Offset in words of 16 bytes" line.long 0x08 "CAL_RD_DMA_XSIZE,Number of bytes to read per line" hexmask.long.word 0x08 19.--31. 1. "XSIZE,Words of 64-bits to read per line" line.long 0x0C "CAL_RD_DMA_YSIZE,Number of lines to" hexmask.long.word 0x0C 16.--29. 1. "YSIZE," group.long 0x120++0x07 line.long 0x00 "CAL_VPORT_CTRL1,Video port control register" bitfld.long 0x00 31. "WIDTH,Video port width - ONE" "WIDTH_0,WIDTH_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,Video port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_VPORT_CTRL2,Video port control register" hexmask.long.word 0x04 18.--31. 1. "RDY_THR,Data shall be send to the video port after frame start only when (RDY_THR+1)*4 pixels are ready and the 4 PCLK cycles (require before each frame start) have been sent" bitfld.long 0x04 17. "FSM_RESET,Forces a reset of the video port FSM - NOEFFECT" "FSM_RESET_0_w,FSM_RESET_1_w" bitfld.long 0x04 16. "FS_RESETS,Controls the behavior of the timing generator when a data tagged as PIX_DAT_FS is received" "FS_RESETS_0,FS_RESETS_1" newline bitfld.long 0x04 15. "FREERUNNING,Controls PCLK generation during IDLE" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 0.--4. "CPORT,Cport ID Valid range=0..(CAL_HL_HWINFO.NCPORT-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "Channel_0" group.long 0x304++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_0,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x310++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x308++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x330++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_0,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_0,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_0,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_0,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_0,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_0,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_0,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_0,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x300++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_0,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x30C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_0,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x350++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_0,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_0,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_0,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_0,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_0,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_0,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_0,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_0,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x314++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_0,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x328++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x2C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x28++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x20++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC0++0x03 line.long 0x00 "CAL_PIX_PROC_i_0,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x204++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_0,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x200++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_0,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x208++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_0,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_0,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "Channel_1" group.long 0x384++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_1,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x390++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x388++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x3B0++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_1,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_1,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_1,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_1,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_1,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_1,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_1,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_1,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x380++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_1,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x38C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_1,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x3D0++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_1,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_1,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_1,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_1,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_1,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_1,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_1,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_1,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x394++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_1,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3A8++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x38++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x30++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC4++0x03 line.long 0x00 "CAL_PIX_PROC_i_1,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x214++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_1,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x210++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_1,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x218++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_1,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_1,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_2" group.long 0x4C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x48++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x40++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC8++0x03 line.long 0x00 "CAL_PIX_PROC_i_2,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x224++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_2,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x220++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_2,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x228++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_2,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_2,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_3" group.long 0x5C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x58++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x50++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_3,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_3,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xCC++0x03 line.long 0x00 "CAL_PIX_PROC_i_3,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x234++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_3,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x230++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_3,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x238++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_3,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_3,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_4" group.long 0x6C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x68++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x60++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x244++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_4,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x240++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_4,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x248++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_4,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_4,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_5" group.long 0x7C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x78++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x70++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x254++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_5,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x250++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_5,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x258++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_5,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_5,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_6" group.long 0x8C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_6,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x88++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_6,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x80++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_6,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x264++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_6,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x260++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_6,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x268++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_6,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_6,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_7" group.long 0x9C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_7,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x98++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_7,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x90++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_7,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_7,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x274++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_7,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x270++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_7,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x278++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_7,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_7,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_8" group.long 0xAC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_8,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_8,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_8,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_8,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end tree "IRQ_Line_9" group.long 0xBC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_9,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_9,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_9,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_9,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check section CAMSS Interrupt Events for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check section CAMSS Interrupt Events for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check section CAMSS Interrupt Events for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check section CAMSS Interrupt Events for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check section CAMSS Interrupt Events for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check section CAMSS Interrupt Events for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check section CAMSS Interrupt Events for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check section CAMSS Interrupt Events for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check section CAMSS Interrupt Events for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check section CAMSS Interrupt Events for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check section CAMSS Interrupt Events for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check section CAMSS Interrupt Events for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check section CAMSS Interrupt Events for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check section CAMSS Interrupt Events for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check section CAMSS Interrupt Events for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check section CAMSS Interrupt Events for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check section CAMSS Interrupt Events for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check section CAMSS Interrupt Events for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check section CAMSS Interrupt Events for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check section CAMSS Interrupt Events for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check section CAMSS Interrupt Events for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check section CAMSS Interrupt Events for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check section CAMSS Interrupt Events for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check section CAMSS Interrupt Events for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check section CAMSS Interrupt Events for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check section CAMSS Interrupt Events for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check section CAMSS Interrupt Events for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check section CAMSS Interrupt Events for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check section CAMSS Interrupt Events for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check section CAMSS Interrupt Events for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check section CAMSS Interrupt Events for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check section CAMSS Interrupt Events for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end width 0x0B tree.end tree "Control_Module" tree "CTRL_MODULE_CORE" base ad:0x4A002000 rgroup.long 0x134++0x03 line.long 0x00 "CTRL_CORE_STATUS,Control Module Status Register" bitfld.long 0x00 6.--8. "DEVICE_TYPE,Device type captured at reset time" "0,1,2,3,4,5,6,7" group.long 0x148++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_1,Firewall Error Status functional Register 1" bitfld.long 0x00 31. "EVE4_FW_ERROR,EVE4 firewall" "No error firewall,Error from firewall" newline bitfld.long 0x00 30. "EVE3_FW_ERROR,ISS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 29. "EVE2_FW_ERROR,EVE2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 28. "EVE1_FW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 23. "BB2D_FW_ERROR,BB2D firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 22. "L4_WAKEUP_FW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 18. "DEBUGSS_FW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_FW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_FW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 14. "DSS_FW_ERROR,DSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 13. "GPU_FW_ERROR,GPU firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 6. "IVAHD_SL2_FW_ERROR,IVAHD SL2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 5. "IPU1_FW_ERROR,IPU1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "IVAHD_FW_ERROR,IVAHD firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 3. "EMIF_FW_ERROR,EMIF firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_FW_ERROR,GPMC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_FW_ERROR,L3RAM1 firewall" "No error from firewall,Error from firewall" group.long 0x150++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_1,Firewall Error Status Debug Register 1" bitfld.long 0x00 31. "EVE4_DBGFW_ERROR,EVE4 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 30. "EVE3_DBGFW_ERROR,ISS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 29. "EVE2_DBGFW_ERROR,EVE2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 28. "EVE1_DBGFW_ERROR,EVE1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 23. "BB2D_DBGFW_ERROR,BB2D firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 22. "L4_WAKEUP_DBGFW_ERROR,L4 wakeup firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 18. "DEBUGSS_DBGFW_ERROR,DebugSS firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "L4_CONFIG_DBGFW_ERROR,L4 config firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "L4_PERIPH1_DBGFW_ERROR,L4 periph1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 14. "DSS_DBGFW_ERROR,DSS debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 13. "GPU_DBGFW_ERROR,GPU debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 6. "IVAHD_SL2_DBGFW_ERROR,IVAHD SL2 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 5. "IPU1_DBGFW_ERROR,IPU1 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "IVAHD_DBGFW_ERROR,IVAHD debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 3. "EMIF_DBGFW_ERROR,EMIF debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "GPMC_DBGFW_ERROR,GPMC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "L3RAM1_DBGFW_ERROR,L3RAM1 debug firewall" "No error from firewall,Error from firewall" group.long 0x15C++0x03 line.long 0x00 "CTRL_CORE_MPU_FORCEWRNP,FORCE WRITE NON POSTED" bitfld.long 0x00 0. "MPU_FORCEWRNP,Force mpu write non posted transactions" "disable force wrnp,force wrnp" rgroup.long 0x194++0x5B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5,Standard Fuse OPP VDD_GPU [191:160]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0,Standard Fuse OPP VDD_MPU [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1,Standard Fuse OPP VDD_MPU [63:32]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2,Standard Fuse OPP VDD_MPU [95:64]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3,Standard Fuse OPP VDD_MPU [127:96]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4,Standard Fuse OPP VDD_MPU [159:128]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5,Standard Fuse OPP VDD_MPU [191:160]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6,Standard Fuse OPP VDD_MPU [223:192]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7,Standard Fuse OPP VDD_MPU [255:224]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x3C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x40 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x44 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x48 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x4C "CTRL_CORE_STD_FUSE_OPP_BGAP_GPU,Trim values for GPU associated temperature sensor and bandgap" hexmask.long.byte 0x4C 24.--31. 1. "STD_FUSE_OPP_BGAP_GPU_0,Trim values for GPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x4C 16.--23. 1. "STD_FUSE_OPP_BGAP_GPU_1,Trim values for GPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x4C 8.--15. 1. "STD_FUSE_OPP_BGAP_GPU_2,Trim values for GPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x4C 0.--7. 1. "STD_FUSE_OPP_BGAP_GPU_3,Trim values for GPU associated temperature sensor and bandgap" line.long 0x50 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU,Trim values for MPU associated temperature sensor and bandgap" hexmask.long.byte 0x50 24.--31. 1. "STD_FUSE_OPP_BGAP_MPU_0,Trim values for MPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x50 16.--23. 1. "STD_FUSE_OPP_BGAP_MPU_1,Trim values for MPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x50 8.--15. 1. "STD_FUSE_OPP_BGAP_MPU_2,Trim values for MPU associated temperature sensor and bandgap" newline hexmask.long.byte 0x50 0.--7. 1. "STD_FUSE_OPP_BGAP_MPU_3,Trim values for MPU associated temperature sensor and bandgap" line.long 0x54 "CTRL_CORE_STD_FUSE_OPP_BGAP_CORE,Trim values for CORE associated temperature sensor and bandgap" hexmask.long.byte 0x54 24.--31. 1. "STD_FUSE_OPP_BGAP_CORE_0,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x54 16.--23. 1. "STD_FUSE_OPP_BGAP_CORE_1,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x54 8.--15. 1. "STD_FUSE_OPP_BGAP_CORE_2,Trim values for CORE associated temperature sensor and bandgap" newline hexmask.long.byte 0x54 0.--7. 1. "STD_FUSE_OPP_BGAP_CORE_3,Trim values for CORE associated temperature sensor and bandgap" line.long 0x58 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23,Standard Fuse OPP BGAP" hexmask.long.word 0x58 16.--31. 1. "STD_FUSE_OPP_BGAP_MPU3," newline hexmask.long.word 0x58 0.--15. 1. "STD_FUSE_OPP_BGAP_MPU2," rgroup.long 0x220++0x57 line.long 0x00 "CTRL_CORE_STD_FUSE_MPK_0,Standard Fuse keys" line.long 0x04 "CTRL_CORE_STD_FUSE_MPK_1,Standard Fuse keys" line.long 0x08 "CTRL_CORE_STD_FUSE_MPK_2,Standard Fuse keys" line.long 0x0C "CTRL_CORE_STD_FUSE_MPK_3,Standard Fuse keys" line.long 0x10 "CTRL_CORE_STD_FUSE_MPK_4,Standard Fuse keys" line.long 0x14 "CTRL_CORE_STD_FUSE_MPK_5,Standard Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_MPK_6,Standard Fuse keys" line.long 0x1C "CTRL_CORE_STD_FUSE_MPK_7,Standard Fuse keys" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5,Standard Fuse OPP VDD_GPU [191:160]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0,Standard Fuse OPP VDD_MPU [31:0]" line.long 0x3C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1,Standard Fuse OPP VDD_MPU [63:32]" line.long 0x40 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2,Standard Fuse OPP VDD_MPU [95:64]" line.long 0x44 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3,Standard Fuse OPP VDD_MPU [127:96]" line.long 0x48 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4,Standard Fuse OPP VDD_MPU [159:128]" line.long 0x4C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5,Standard Fuse OPP VDD_MPU [191:160]" line.long 0x50 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6,Standard Fuse OPP VDD_MPU [223:192]" line.long 0x54 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7,Standard Fuse OPP VDD_MPU [255:224]" rgroup.long 0x2BC++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_SWRV_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_SWRV_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_SWRV_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_SWRV_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_SWRV_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_SWRV_6,Customer Fuse keys" group.long 0x300++0x03 line.long 0x00 "CTRL_CORE_DEV_CONF,This register is used to power down the USB2_PHY1" bitfld.long 0x00 0. "USBPHY_PD,Power down the entire USB2_PHY1 (data common module and UTMI)" "Normal operation,Power down the USB2_PHY1" rgroup.long 0x32C++0x0B line.long 0x00 "CTRL_CORE_TEMP_SENSOR_MPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x00 11. "BGAP_TMPSOFF_MPU,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x00 10. "BGAP_EOCZ_MPU,ADC End of Conversion" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "BGAP_DTEMP_MPU,Temperature data from the ADC" line.long 0x04 "CTRL_CORE_TEMP_SENSOR_GPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x04 11. "BGAP_TMPSOFF_GPU,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x04 10. "BGAP_EOCZ_GPU,ADC End of Conversion" "0,1" newline hexmask.long.word 0x04 0.--9. 1. "BGAP_DTEMP_GPU,Temperature data from the ADC" line.long 0x08 "CTRL_CORE_TEMP_SENSOR_CORE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x08 11. "BGAP_TMPSOFF_CORE,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x08 10. "BGAP_EOCZ_CORE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x08 0.--9. 1. "BGAP_DTEMP_CORE,Temperature data from the ADC" group.long 0x358++0x0B line.long 0x00 "CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR,Cortex M4 register" hexmask.long.tbyte 0x00 0.--19. 1. "CORTEX_M4_MMUADDRTRANSLTR,Used to save the mmu address boot" line.long 0x04 "CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR," hexmask.long.tbyte 0x04 0.--19. 1. "CORTEX_M4_MMUADDRLOGICTR," line.long 0x08 "CTRL_CORE_HWOBS_CONTROL,HW observability control" bitfld.long 0x08 14.--18. "HWOBS_CLKDIV_SEL_2,Clock divider selection on po_hwobs(2)" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 9.--13. "HWOBS_CLKDIV_SEL_1,Clock divider selection on po_hwobs(1)" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 3.--7. "HWOBS_CLKDIV_SEL,Clock divider selection on po_hwobs(0)" "?,output is not divided,output is divided by 2,?,output is divided by 4,?,?,?,output is divided by 8,?,?,?,?,?,?,?,output is divided by 16,?..." newline bitfld.long 0x08 2. "HWOBS_ALL_ZERO_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 0" newline bitfld.long 0x08 1. "HWOBS_ALL_ONE_MODE,Used to gate observable signals" "hw observability ports are not gated,hw observability ports are all set to 1" newline bitfld.long 0x08 0. "HWOBS_MACRO_ENABLE,Used to gate observable signals coming from macros using" "hw observability ports from macros are gated and..,hw observability ports from macros are not gated" group.long 0x370++0x07 line.long 0x00 "CTRL_CORE_PHY_POWER_USB,phy_power_usb" hexmask.long.word 0x00 22.--31. 1. "USB_PWRCTL_CLK_FREQ,Frequency of SYSCLK1 in MHz (rounded)" newline hexmask.long.byte 0x00 14.--21. 1. "USB_PWRCTL_CLK_CMD,Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules" line.long 0x04 "CTRL_CORE_PHY_POWER_SATA,phy_power_sata" hexmask.long.word 0x04 22.--31. 1. "SATA_PWRCTL_CLK_FREQ,Frequency of SYSCLK1 in MHz (rounded)" newline abitfld.long 0x04 14.--21. "SATA_PWRCTL_CLK_CMD,Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules" "0x00=Powers down SATA_PHY_TX and SATA_PHY_RX,0x01=Powers up SATA_PHY_RX,0x02=Powers up SATA_PHY_TX,0x03=Powers up SATA_PHY_TX and SATA_PHY_RX.." group.long 0x380++0x1B line.long 0x00 "CTRL_CORE_BANDGAP_MASK_1,bgap_mask" bitfld.long 0x00 30.--31. "SIDLEMODE,sidlemode for bandgap" "No Idle,Force Idle,Smart Idle,Reserved" newline bitfld.long 0x00 27.--29. "COUNTER_DELAY,Counter delay" "Imediat,Delay of 1ms,Delay of 10ms,Delay of 100ms,Delay of 250ms,Delay of 500ms,?..." newline bitfld.long 0x00 23. "FREEZE_CORE,Freeze the FIFO CORE" "No operation,Freeze the FIFO" newline bitfld.long 0x00 22. "FREEZE_GPU,Freeze the FIFO GPU" "No operation,Freeze the FIFO" newline bitfld.long 0x00 21. "FREEZE_MPU,Freeze the FIFO MPU" "No operation,Freeze the FIFO" newline bitfld.long 0x00 20. "CLEAR_CORE,Reset the FIFO CORE" "No operation,Reset the FIFO" newline bitfld.long 0x00 19. "CLEAR_GPU,Reset the FIFO GPU" "No operation,Reset the FIFO" newline bitfld.long 0x00 18. "CLEAR_MPU,Reset the FIFO MPU" "No operation,Reset the FIFO" newline bitfld.long 0x00 5. "MASK_HOT_CORE,Mask for hot event CORE" "hot event is masked,hot event is not masked" newline bitfld.long 0x00 4. "MASK_COLD_CORE,Mask for cold event CORE" "cold event is masked,cold event is not masked" newline bitfld.long 0x00 3. "MASK_HOT_GPU,Mask for hot event GPU" "hot event is masked,hot event is not masked" newline bitfld.long 0x00 2. "MASK_COLD_GPU,Mask for cold event GPU" "cold event is masked,cold event is not masked" newline bitfld.long 0x00 1. "MASK_HOT_MPU,Mask for hot event MPU" "hot event is masked,hot event is not masked" newline bitfld.long 0x00 0. "MASK_COLD_MPU,Mask for cold event MPU" "cold event is masked,cold event is not masked" line.long 0x04 "CTRL_CORE_BANDGAP_THRESHOLD_MPU,BGAP THRESHOLD MPU" hexmask.long.word 0x04 16.--25. 1. "THOLD_HOT_MPU,Value for the high temperature threshold" newline hexmask.long.word 0x04 0.--9. 1. "THOLD_COLD_MPU,Value for the low temperature threshold" line.long 0x08 "CTRL_CORE_BANDGAP_THRESHOLD_GPU,BGAP THRESHOLD MM" hexmask.long.word 0x08 16.--25. 1. "THOLD_HOT_GPU,Value for the high temperature threshold" newline hexmask.long.word 0x08 0.--9. 1. "THOLD_COLD_GPU,Value for the low temperature threshold" line.long 0x0C "CTRL_CORE_BANDGAP_THRESHOLD_CORE,BGAP THRESHOLD CORE" hexmask.long.word 0x0C 16.--25. 1. "THOLD_HOT_CORE,Value for the high temperature threshold" newline hexmask.long.word 0x0C 0.--9. 1. "THOLD_COLD_CORE,Value for the low temperature threshold" line.long 0x10 "CTRL_CORE_BANDGAP_TSHUT_MPU,BGAP TSHUT THRESHOLD MPU" hexmask.long.word 0x10 16.--25. 1. "TSHUT_HOT_MPU,tshut value hot Software should not modify this bit field" newline hexmask.long.word 0x10 0.--9. 1. "TSHUT_COLD_MPU,tshut value cold Software should not modify this bit field" line.long 0x14 "CTRL_CORE_BANDGAP_TSHUT_GPU,BGAP TSHUT THRESHOLD GPU" hexmask.long.word 0x14 16.--25. 1. "TSHUT_HOT_GPU,tshut value hot Software should not modify this bit field" newline hexmask.long.word 0x14 0.--9. 1. "TSHUT_COLD_GPU,tshut value cold Software should not modify this bit field" line.long 0x18 "CTRL_CORE_BANDGAP_TSHUT_CORE,BGAP TSHUT THRESHOLD CORE" hexmask.long.word 0x18 16.--25. 1. "TSHUT_HOT_CORE,tshut value hot Software should not modify this bit field" newline hexmask.long.word 0x18 0.--9. 1. "TSHUT_COLD_CORE,tshut value cold Software should not modify this bit field" rgroup.long 0x3A8++0x07 line.long 0x00 "CTRL_CORE_BANDGAP_STATUS_1,BGAP STATUS" bitfld.long 0x00 31. "ALERT,Alert temperature when '1'" "0,1" newline bitfld.long 0x00 5. "HOT_CORE,Event for hot temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 4. "COLD_CORE,Event for cold temperature mpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 3. "HOT_GPU,Event for hot temperature gpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 2. "COLD_GPU,Event for cold temperature gpu bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 1. "HOT_MPU,Event for hot temperature core bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 0. "COLD_MPU,Event for cold temperature core bandgap when '1'" "event not detected,event detected" line.long 0x04 "CTRL_CORE_SATA_EXT_MODE,SATA EXTENDED MODE" bitfld.long 0x04 0. "SATA_EXTENDED_MODE,sata extended mode" "no extended mode,extended mode" rgroup.long 0x3C0++0x3F line.long 0x00 "CTRL_CORE_DTEMP_MPU_0,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_MPU_0,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_MPU_0,temperature" line.long 0x04 "CTRL_CORE_DTEMP_MPU_1,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_MPU_1,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_MPU_1,temperature" line.long 0x08 "CTRL_CORE_DTEMP_MPU_2,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x08 10.--31. 1. "DTEMP_TAG_MPU_2,tag" newline hexmask.long.word 0x08 0.--9. 1. "DTEMP_TEMPERATURE_MPU_2,temperature" line.long 0x0C "CTRL_CORE_DTEMP_MPU_3,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x0C 10.--31. 1. "DTEMP_TAG_MPU_3,tag" newline hexmask.long.word 0x0C 0.--9. 1. "DTEMP_TEMPERATURE_MPU_3,temperature" line.long 0x10 "CTRL_CORE_DTEMP_MPU_4,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x10 10.--31. 1. "DTEMP_TAG_MPU_4,tag" newline hexmask.long.word 0x10 0.--9. 1. "DTEMP_TEMPERATURE_MPU_4,temperature" line.long 0x14 "CTRL_CORE_DTEMP_GPU_0,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x14 10.--31. 1. "DTEMP_TAG_GPU_0,tag" newline hexmask.long.word 0x14 0.--9. 1. "DTEMP_TEMPERATURE_GPU_0,temperature" line.long 0x18 "CTRL_CORE_DTEMP_GPU_1,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x18 10.--31. 1. "DTEMP_TAG_GPU_1,tag" newline hexmask.long.word 0x18 0.--9. 1. "DTEMP_TEMPERATURE_GPU_1,temperature" line.long 0x1C "CTRL_CORE_DTEMP_GPU_2,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x1C 10.--31. 1. "DTEMP_TAG_GPU_2,tag" newline hexmask.long.word 0x1C 0.--9. 1. "DTEMP_TEMPERATURE_GPU_2,temperature" line.long 0x20 "CTRL_CORE_DTEMP_GPU_3,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x20 10.--31. 1. "DTEMP_TAG_GPU_3,tag" newline hexmask.long.word 0x20 0.--9. 1. "DTEMP_TEMPERATURE_GPU_3,temperature" line.long 0x24 "CTRL_CORE_DTEMP_GPU_4,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x24 10.--31. 1. "DTEMP_TAG_GPU_4,tag" newline hexmask.long.word 0x24 0.--9. 1. "DTEMP_TEMPERATURE_GPU_4,temperature" line.long 0x28 "CTRL_CORE_DTEMP_CORE_0,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x28 10.--31. 1. "DTEMP_TAG_CORE_0,tag" newline hexmask.long.word 0x28 0.--9. 1. "DTEMP_TEMPERATURE_CORE_0,temperature" line.long 0x2C "CTRL_CORE_DTEMP_CORE_1,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x2C 10.--31. 1. "DTEMP_TAG_CORE_1,tag" newline hexmask.long.word 0x2C 0.--9. 1. "DTEMP_TEMPERATURE_CORE_1,temperature" line.long 0x30 "CTRL_CORE_DTEMP_CORE_2,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x30 10.--31. 1. "DTEMP_TAG_CORE_2,tag" newline hexmask.long.word 0x30 0.--9. 1. "DTEMP_TEMPERATURE_CORE_2,temperature" line.long 0x34 "CTRL_CORE_DTEMP_CORE_3,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x34 10.--31. 1. "DTEMP_TAG_CORE_3,tag" newline hexmask.long.word 0x34 0.--9. 1. "DTEMP_TEMPERATURE_CORE_3,temperature" line.long 0x38 "CTRL_CORE_DTEMP_CORE_4,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x38 10.--31. 1. "DTEMP_TAG_CORE_4,tag" newline hexmask.long.word 0x38 0.--9. 1. "DTEMP_TEMPERATURE_CORE_4,temperature" line.long 0x3C "CTRL_CORE_SMA_SW_0,OCP Spare Register" rbitfld.long 0x3C 31. "MCAN_CLK_HSDIV_CHANGE_ACK,Acknowledge flag which indicates that the on-the-fly change of H14 divider of DPLL_GMAC is done" "0,1" newline bitfld.long 0x3C 30. "MCAN_CLK_HSDIV_EN_ACK,Indicates whether CLKOUTX2_H14 of DPLL_GMAC is enabled or not" "CLKOUTX2_H14 is disabled,CLKOUTX2_H14 is enabled" newline bitfld.long 0x3C 29. "MCAN_CLK_TENABLEDIV_SEL,TENABLEDIV control select for H14 of DPLL_GMAC" "Control from PRCM,Control from Control Module (bit [26].." newline bitfld.long 0x3C 27. "MCAN_CLK_HSDIV_EN,Output clock (CLKOUTX2_H14) enable for H14 of DPLL_GMAC" "Output clock disabled,Output clock enabled" newline bitfld.long 0x3C 26. "MCAN_CLK_HSDIV_LATCH_EN,To be toggled (LO->HI->LO) to latch MCAN_CLK_HSDIV value in H14 of DPLL_GMAC" "0,1" newline bitfld.long 0x3C 20.--25. "MCAN_CLK_HSDIV,This field programs the H14 divider of DPLL_GMAC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x3C 18. "SATA_PLL_SOFT_RESET,Software reset control for SATA PLL" "0,1" newline bitfld.long 0x3C 6. "WARM_SFORCE_EN,Enable feature to force self refresh after warm reset" "Feature disabled,Feature enabled" newline bitfld.long 0x3C 5. "WARM_SFORCE,Force self refresh after warm reset" "Each EMIF controls the corresponding CKE pad,If WARM_SFORCE_EN bit is set to 0x1 the EMIF1.." newline bitfld.long 0x3C 2. "ISOLATE,This bit is used during the isolation/de-isolation sequence described in Isolation Requirements" "0,1" newline bitfld.long 0x3C 1. "EMIF2_CKE_GATING_CTRL,Forces the EMIF2 CKE pad to tri-state" "The CKE pad is not in tri-state and can be..,The CKE pad is in tri-state" newline bitfld.long 0x3C 0. "EMIF1_CKE_GATING_CTRL,Forces the EMIF1 CKE pad to tri-state" "The CKE pad is not in tri-state and can be..,The CKE pad is in tri-state" group.long 0x414++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_2,Firewall Error Status functional Register 2" bitfld.long 0x00 26. "TC1_EDMA_FW_ERROR,EDMA TC1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 22. "QSPI_FW_ERROR,QSPI firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 20. "PRUSS1_FW_ERROR,PRU-ICSS1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "TPCC_EDMA_FW_ERROR,EDMA TPCC firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_FW_ERROR,EDMA TC0 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 13. "MCASP3_FW_ERROR,McASP3 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 12. "MCASP2_FW_ERROR,McASP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 11. "MCASP1_FW_ERROR,McASP1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 8. "PCIESS2_FW_ERROR,PCIeSS2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 7. "PCIESS1_FW_ERROR,PCIeSS1 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 6. "IPU2_FW_ERROR,IPU2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 5. "L4_PERIPH3_FW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_FW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 3. "L3RAM3_FW_ERROR,L3RAM3 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "L3RAM2_FW_ERROR,L3RAM2 target firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "DSP2_FW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_FW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" group.long 0x41C++0x27 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_2,Firewall Error Status debug Register 2" bitfld.long 0x00 26. "TC1_EDMA_DBGFW_ERROR,EDMA TC1 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 22. "QSPI_DBGFW_ERROR,QSPI debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 20. "PRUSS1_DBGFW_ERROR,PRU-ICSS1 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 17. "TPCC_EDMA_DBGFW_ERROR,EDMA TPCC debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 16. "TC0_EDMA_DBGFW_ERROR,EDMA TC0 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 13. "MCASP3_DBGFW_ERROR,McASP3 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 12. "MCASP2_DBGFW_ERROR,McASP2 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 11. "MCASP1_DBGFW_ERROR,McASP1 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 8. "PCIESS2_DBGFW_ERROR,PCIeSS2 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 7. "PCIESS1_DBGFW_ERROR,PCIeSS1 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 6. "IPU2_DBGFW_ERROR,IPU2 debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 5. "L4_PERIPH3_DBGFW_ERROR,L4 periph3 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 4. "L4_PERIPH2_DBGFW_ERROR,L4 periph2 init firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 3. "L3RAM3_DBGFW_ERROR,L3RAM3 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 2. "L3RAM2_DBGFW_ERROR,L3RAM2 target debug firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 1. "DSP2_DBGFW_ERROR,DSP2 firewall" "No error from firewall,Error from firewall" newline bitfld.long 0x00 0. "DSP1_DBGFW_ERROR,DSP1 firewall" "No error from firewall,Error from firewall" line.long 0x04 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_1,Register for priority settings for EMIF arbitration" bitfld.long 0x04 28.--30. "MPU_EMIF_PRIORITY,MPU priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x04 16.--18. "DSP1_MDMA_EMIF_PRIORITY,DSP1 MDMA priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x04 12.--14. "DSP1_CFG_EMIF_PRIORITY,DSP1 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x04 8.--10. "DSP1_EDMA_EMIF_PRIORITY,DSP1 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x04 4.--6. "DSP2_EDMA_EMIF_PRIORITY,DSP2 EDMA priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x04 0.--2. "DSP2_CFG_EMIF_PRIORITY,DSP2 CFG priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x08 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_2,Register for priority settings for EMIF arbitration" bitfld.long 0x08 28.--30. "DSP2_MDMA_EMIF_PRIORITY,DSP2 MDMA priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 24.--26. "IVA_ICONT1_EMIF_PRIORITY,IVA ICONT1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 16.--18. "EVE1_TC0_EMIF_PRIORITY,EVE1 TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 12.--14. "EVE2_TC0_EMIF_PRIORITY,EVE2 TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 8.--10. "EVE3_TC0_EMIF_PRIORITY,EVE3 TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 4.--6. "EVE4_TC0_EMIF_PRIORITY,ISS_RT priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x08 0.--2. "PRUSS1_PRU0_EMIF_PRIORITY,PRU-ICSS1 PRU0 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x0C "CTRL_CORE_EMIF_INITIATOR_PRIORITY_3,Register for priority settings for EMIF arbitration" bitfld.long 0x0C 28.--30. "PRUSS1_PRU1_EMIF_PRIORITY,PRU-ICSS1 PRU1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x0C 16.--18. "IPU1_EMIF_PRIORITY,IPU1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x0C 12.--14. "IPU2_EMIF_PRIORITY,IPU2 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x0C 8.--10. "DMA_SYSTEM_EMIF_PRIORITY,DMA SYSTEM priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x0C 0.--2. "EDMA_TC0_EMIF_PRIORITY,EDMA TC0 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x10 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_4,Register for priority settings for EMIF arbitration" bitfld.long 0x10 28.--30. "EDMA_TC1_EMIF_PRIORITY,EDMA TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x10 24.--26. "DSS_EMIF_PRIORITY,DSS priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x10 16.--18. "PCIESS1_EMIF_PRIORITY,PCIeSS1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x10 12.--14. "PCIESS2_EMIF_PRIORITY,PCIeSS2 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x10 8.--10. "VIP1_P1_P2_EMIF_PRIORITY,VIP1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x10 4.--6. "VIP2_P1_P2_EMIF_PRIORITY,VIP2 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x10 0.--2. "VIP3_P1_P2_EMIF_PRIORITY,VIP3 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x14 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_5,Register for priority settings for EMIF arbitration" bitfld.long 0x14 28.--30. "VPE_P1_P2_EMIF_PRIORITY,VPE priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 24.--26. "MMC1_GPU_P1_EMIF_PRIORITY,MMC1 GPU P1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 20.--22. "MMC2_GPU_P2_EMIF_PRIORITY,MMC2 GPU P2 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 16.--18. "BB2D_P1_P2_EMIF_PRIORITY,BB2D priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 12.--14. "GMAC_SW_EMIF_PRIORITY,GMAC_SW priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 8.--10. "USB1_EMIF_PRIORITY,USB1 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 4.--6. "USB2_EMIF_PRIORITY,USB2 priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x14 0.--2. "USB3_EMIF_PRIORITY,USB3 priority setting" "highest priority,?,?,?,?,?,?,lowest priorty" line.long 0x18 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_6,Register for priority settings for EMIF arbitration" bitfld.long 0x18 28.--30. "USB4_EMIF_PRIORITY,USB4 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x18 12.--14. "SATA_EMIF_PRIORITY,SATA priority setting" "highest priority,?,?,?,?,?,?,lowest priority" newline bitfld.long 0x18 8.--10. "EVE1_TC1_EMIF_PRIORITY,EVE1 TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x18 4.--6. "EVE2_TC1_EMIF_PRIORITY,EVE2 TC1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" newline bitfld.long 0x18 0.--2. "EVE3_TC1_EMIF_PRIORITY,ISS_NRT2 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x1C "CTRL_CORE_EMIF_INITIATOR_PRIORITY_7,Register for priority settings for EMIF arbitration" bitfld.long 0x1C 28.--30. "EVE4_TC1_EMIF_PRIORITY,ISS_NRT1 priority setting" "highest priority,?,?,?,?,?,?,lowest prority" line.long 0x20 "CTRL_CORE_L3_INITIATOR_PRESSURE_1,Register for pressure settings for L3 arbitration" bitfld.long 0x20 26.--27. "MPU_L3_PRESSURE,MPU pressure setting" "lowest,?,?,highest" newline bitfld.long 0x20 17.--18. "DSP1_CFG_L3_PRESSURE,DSP1 CFG pressure setting" "lowest,?,?,highest" newline bitfld.long 0x20 9.--10. "DSP2_CFG_L3_PRESSURE,DSP2 CFG pressure setting" "lowest,?,?,highest" line.long 0x24 "CTRL_CORE_L3_INITIATOR_PRESSURE_2,Register for pressure settings for L3 arbitration" bitfld.long 0x24 12.--13. "IPU1_L3_PRESSURE,IPU1 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x24 9.--10. "IPU2_L3_PRESSURE,IPU2 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x24 6.--7. "PRUSS1_PRU0_L3_PRESSURE,PRU-ICSS1 PRU0 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x24 3.--4. "PRUSS1_PRU1_L3_PRESSURE,PRU-ICSS1 PRU1 pressure setting" "lowest,?,?,highest" group.long 0x448++0x2B line.long 0x00 "CTRL_CORE_L3_INITIATOR_PRESSURE_4,Register for pressure settings for L3 arbitration" bitfld.long 0x00 23.--24. "GPU_P1_L3_PRESSURE,GPU P1 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x00 20.--21. "GPU_P2_L3_PRESSURE,GPU P2 pressure setting" "lowest,?,?,highest" line.long 0x04 "CTRL_CORE_L3_INITIATOR_PRESSURE_5,Register for pressure settings for L3 arbitration" bitfld.long 0x04 3.--4. "SATA_L3_PRESSURE,SATA pressure setting" "lowest,?,?,highest" newline bitfld.long 0x04 0.--1. "MMC1_L3_PRESSURE,MMC1 pressure setting" "lowest,?,?,highest" line.long 0x08 "CTRL_CORE_L3_INITIATOR_PRESSURE_6,Register for pressure settings for L3 arbitration" bitfld.long 0x08 17.--18. "MMC2_L3_PRESSURE,MMC2 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x08 15.--16. "USB1_L3_PRESSURE,USB1 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x08 12.--13. "USB2_L3_PRESSURE,USB2 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x08 9.--10. "USB3_L3_PRESSURE,USB3 pressure setting" "lowest,?,?,highest" newline bitfld.long 0x08 6.--7. "USB4_L3_PRESSURE,USB4 pressure setting" "lowest,?,?,highest" line.long 0x0C "CTRL_CORE_L3_INITIATOR_PRESSURE_7,ISS clocking control register.[New TDA2Px feature versus TDA2x]" rbitfld.long 0x0C 31. "ISS_CORE_CLK_HSDIV_CHANGE_ACK,Acknowledge flag which indicates that the on-the-fly change of H21 divider of DPLL_CORE is done" "0,1" newline bitfld.long 0x0C 30. "ISS_CORE_CLK_HSDIV_EN_ACK,Indicates whether CLKOUTX2_H21 of DPLL_CORE is enabled or not" "CLKOUTX2_H21 is disabled,CLKOUTX2_H21 is enabled" newline bitfld.long 0x0C 29. "ISS_CORE_CLK_TENABLEDIV_SEL,TENABLEDIV control select for H21 of DPLL_CORE" "Control from PRCM,Control from Control Module (bit [26].." newline bitfld.long 0x0C 27. "ISS_CORE_CLK_HSDIV_EN,Output clock (CLKOUTX2_H21) enable for H21 of DPLL_CORE" "Output clock disabled,Output clock enabled" newline bitfld.long 0x0C 26. "ISS_CORE_CLK_HSDIV_LATCH_EN,To be toggled (LO->HI->LO) to latch ISS_CORE_CLK_HSDIV value in H21 of DPLL_CORE" "0,1" newline bitfld.long 0x0C 20.--25. "ISS_CORE_CLK_HSDIV,This field programs the H21 divider of DPLL_CORE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "ISS_BRIDGE_MULTI_EN,ISS config slave bridge multi-issue enable" "Multi-issue is disabled,Multi-issue is enabled" newline bitfld.long 0x0C 5. "ISS_DPLLPER_H14_EN,Clock enable for DPLL_PER H14" "Clock disabled,Clock enabled" newline bitfld.long 0x0C 4. "ISS_DPLLDSP_CLKOUTHIF_EN,Clock enable for DPLL_DSP CLKOUTHIF" "Clock disabled,Clock enabled" newline bitfld.long 0x0C 0.--1. "ISS_CLK_MUX,ISS clock selection" "EVE3_GFCLK divided by 2 selected,Clock from CLKOUTHIF of DPLL_DSP selected,Clock from H14 of DPLL_PER selected,Clock from H21 of DPLL_CORE selected" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0,Standard Fuse OPP VDD_iva [31:0]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1,Standard Fuse OPP VDD_iva [63:32]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2,Standard Fuse OPP VDD_iva [95:64]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3,Standard Fuse OPP VDD_iva [127:96]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4,Standard Fuse OPP VDD_iva [159:128]" line.long 0x24 "CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL,DSPEVE Voltage Body Bias LDO Control register" bitfld.long 0x24 10. "LDOVBBDSPEVE_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "efuse value is used,override value is used" newline rbitfld.long 0x24 5.--9. "LDOVBBDSPEVE_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 0.--4. "LDOVBBDSPEVE_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x28 "CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL,IVA Voltage Body Bias LDO Control register" bitfld.long 0x28 10. "LDOVBBIVA_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "efuse value is used,override value is used" newline rbitfld.long 0x28 5.--9. "LDOVBBIVA_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x28 0.--4. "LDOVBBIVA_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x4E8++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_UID_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_UID_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_UID_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_UID_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_UID_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_UID_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_UID_6,Customer Fuse keys" rgroup.long 0x508++0x03 line.long 0x00 "CTRL_CORE_CUST_FUSE_PCIE_ID_0,Customer Fuse keys" rgroup.long 0x510++0x13 line.long 0x00 "CTRL_CORE_CUST_FUSE_USB_ID_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_MAC_ID_SW_0,Standard Fuse keys. MAC ID_1 [63:32]" hexmask.long 0x04 0.--24. 1. "STD_FUSE_MAC_ID_SW_0,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0" line.long 0x08 "CTRL_CORE_MAC_ID_SW_1,Standard Fuse keys. MAC ID_1 [31:0]" hexmask.long 0x08 0.--24. 1. "STD_FUSE_MAC_ID_SW_1,This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0" line.long 0x0C "CTRL_CORE_MAC_ID_SW_2,Standard Fuse keys. MAC ID_2 [63:32]" hexmask.long 0x0C 0.--24. 1. "STD_FUSE_MAC_ID_SW_2,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1" line.long 0x10 "CTRL_CORE_MAC_ID_SW_3,Standard Fuse keys. MAC ID_2 [31:0]" hexmask.long 0x10 0.--24. 1. "STD_FUSE_MAC_ID_SW_3,This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1" group.long 0x534++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_1,OCP Spare Register" bitfld.long 0x00 26. "RGMII2_ID_MODE_N,Ethernet RGMII port 2 internal delay on transmit" "Internal delay enabled,Internal delay disabled" newline bitfld.long 0x00 25. "RGMII1_ID_MODE_N,Ethernet RGMII port 1 internal delay on transmit" "Internal delay enabled,Internal delay disabled" newline bitfld.long 0x00 22. "DSS_CH0_ON_OFF,DSS Channel 0 Pixel clock control On/Off" "HSYNC and VSYNC are driven on opposite edges of..,HSYNC and VSYNC are driven according to bit.." newline bitfld.long 0x00 19. "DSS_CH0_IPC,DSS Channel 0 IPC control" "Data is driven on the LCD data lines on the..,Data is driven on the LCD data lines on the.." newline bitfld.long 0x00 16. "DSS_CH0_RF,DSS Channel 0 Rise/Fall control" "HSYNC and VSYNC are driven on falling edge of..,HSYNC and VSYNC are driven on rising edge of.." newline bitfld.long 0x00 10. "VIP3_CLK_INV_PORT_1A,VIP3 Slice 1 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 9. "VIP3_CLK_INV_PORT_2A,VIP3 Slice 0 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 8. "VPE_CLK_DIV_BY_2_EN,Selects alternative clock source for VPE" "Default clock source from DPLL_CORE is selected,Alternative clock source from DPLL_VIDEO1 is.." newline bitfld.long 0x00 7. "VIP2_CLK_INV_PORT_2B,VIP2 Slice 1 Clock inversion for Port B enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 6. "VIP2_CLK_INV_PORT_1B,VIP2 Slice 0 Clock inversion for Port B enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 5. "VIP2_CLK_INV_PORT_2A,VIP2 Slice 1 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 4. "VIP2_CLK_INV_PORT_1A,VIP2 Slice 0 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 3. "VIP1_CLK_INV_PORT_2B,VIP1 Slice 1 Clock inversion for Port B enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 2. "VIP1_CLK_INV_PORT_1B,VIP1 Slice 0 Clock inversion for Port B enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 1. "VIP1_CLK_INV_PORT_2A,VIP1 Slice 1 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" newline bitfld.long 0x00 0. "VIP1_CLK_INV_PORT_1A,VIP1 Slice 0 Clock inversion for Port A enable" "clock inversion is disabled,clock inversion is enabled" line.long 0x04 "CTRL_CORE_DSS_PLL_CONTROL,DSS PLLs Mux control register" bitfld.long 0x04 29.--31. "ALTCLK2_SEL,Alternative clock selection for DSI1_B_CLK1 DSI1_C_CLK1 or both based on fields DSI1_B_CLK1_ALTCLK2_SEL and DSI1_C_CLK1_ALTCLK12_SEL" "wakeup0 pin,wakeup1 pin,vin1a_clk pin,vin1b_clk pin,DPLL_PCIE_REF,Reserved,DPLL_SATA,Reserved" newline bitfld.long 0x04 26.--28. "ALTCLK1_SEL,Alternative clock selection for DSI1_A_CLK1 DSI1_C_CLK1 or both based on fields DSI1_A_CLK1_ALTCLK1_SEL and DSI1_C_CLK1_ALTCLK12_SEL" "wakeup0 pin,wakeup1 pin,vin1a_clk pin,vin1b_clk pin,DPLL_PCIE_REF,Reserved,DPLL_SATA,Reserved" newline bitfld.long 0x04 24.--25. "DSI1_C_CLK1_ALTCLK12_SEL,DSI1_C_CLK1 alternative clock selection" "Clock selection based on DSI1_C_CLK1_SELECTION,Clock selection based on ALTCLK1_SEL,Clock selection based on ALTCLK2_SEL,Reserved" newline bitfld.long 0x04 23. "DSI1_B_CLK1_ALTCLK2_SEL,DSI1_B_CLK1 alternative clock selection" "Clock selection based on DSI1_B_CLK1_SELECTION,Clock selection based on ALTCLK2_SEL" newline bitfld.long 0x04 22. "DSI1_A_CLK1_ALTCLK1_SEL,DSI1_A_CLK1 alternative clock selection" "Clock selection based on DSI1_A_CLK1_SELECTION,Clock selection based on ALTCLK1_SEL" newline bitfld.long 0x04 18. "PLL_HDMI_LOOPBW_INCR_DECRZ," "0,1" newline bitfld.long 0x04 16.--17. "PLL_HDMI_LOOPBW,DPLL_HDMI loop bandwidth mode If PLL_HDMI_LOOPBW_INCR_DECRZ =" "1x Mode (Loop BW is..,2x Mode (Loop BW is..,Reserved,Reserved" newline bitfld.long 0x04 14.--15. "PLL_VIDEO2_LOOPBW,DPLL_VIDEO2 loop bandwidth mode" "1x Mode (Loop BW is REF_CLK/50),0.5x Mode (Loop BW is REF_CLK/100),0.25x Mode (Loop BW is REF_CLK/200),0.125x Mode (Loop BW is REF_CLK/400)" newline bitfld.long 0x04 12.--13. "PLL_VIDEO1_LOOPBW,DPLL_VIDEO1 loop bandwidth mode" "1x Mode (Loop BW is REF_CLK/50),0.5x Mode (Loop BW is REF_CLK/100),0.25x Mode (Loop BW is REF_CLK/200),0.125x Mode (Loop BW is REF_CLK/400)" newline bitfld.long 0x04 9.--10. "SDVENC_CLK_SELECTION,SDVENC_CLK mux configuration" "HDMI_CLK,..,?..." newline bitfld.long 0x04 7.--8. "DSI1_C_CLK1_SELECTION,DSI1_C_CLK1 mux configuration" "DPLL_VIDEO2,DPLL_VIDEO1,DPLL_HDMI,?..." newline bitfld.long 0x04 5.--6. "DSI1_B_CLK1_SELECTION,DSI1_B_CLK1 mux configuration" "DPLL_VIDEO1,DPLL_VIDEO2,DPLL_HDMI,DPLL_ABE" newline bitfld.long 0x04 3.--4. "DSI1_A_CLK1_SELECTION,DSI1_A_CLK1 mux configuration" "DPLL_VIDEO1,DPLL_HDMI,?..." newline bitfld.long 0x04 2. "PLL_HDMI_DSS_CONTROL_DISABLE,HDMI PLL disable" "PLL enabled,PLL disabled" newline bitfld.long 0x04 1. "PLL_VIDEO2_DSS_CONTROL_DISABLE,VIDEO2 PLL disable" "PLL enabled,PLL disabled" newline bitfld.long 0x04 0. "PLL_VIDEO1_DSS_CONTROL_DISABLE,VIDEO1 PLL disable" "PLL enabled,PLL disabled" group.long 0x540++0x4F line.long 0x00 "CTRL_CORE_MMR_LOCK_1,Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F" line.long 0x04 "CTRL_CORE_MMR_LOCK_2,Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F" line.long 0x08 "CTRL_CORE_MMR_LOCK_3,Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF" line.long 0x0C "CTRL_CORE_MMR_LOCK_4,Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF" line.long 0x10 "CTRL_CORE_MMR_LOCK_5,Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF" line.long 0x14 "CTRL_CORE_CONTROL_IO_1,Register to configure some IP level signals" bitfld.long 0x14 20. "MMU2_DISABLE,MMU2 DISABLE setting" "0,1" newline bitfld.long 0x14 16. "MMU1_DISABLE,MMU1 DISABLE setting" "0,1" newline bitfld.long 0x14 12.--13. "TC1_DEFAULT_BURST_SIZE,EDMA TC1 Default Burst Size (DBS) setting" "16 byte burst,32 byte burst,64 byte burst,128 byte burst" newline bitfld.long 0x14 8.--9. "TC0_DEFAULT_BURST_SIZE,EDMA TC0 Default Burst Size (DBS) setting" "16 byte burst,32 byte burst,64 byte burst,128 byte burst" newline bitfld.long 0x14 4.--5. "GMII2_SEL,GMII2 selection setting" "GMII/MII,RMII,RGMII,Reserved" newline bitfld.long 0x14 0.--1. "GMII1_SEL,GMII1 selection setting" "GMII/MII,RMII,RGMII,Reserved" line.long 0x18 "CTRL_CORE_CONTROL_IO_2,Register to configure some IP level signals" bitfld.long 0x18 23. "GMAC_RESET_ISOLATION_ENABLE,Reset isolation enable setting" "Reset is not isolated,Reset is isolated" newline bitfld.long 0x18 22. "PWMSS3_TBCLKEN,PWMSS3 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 21. "PWMSS2_TBCLKEN,PWMSS2 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 20. "PWMSS1_TBCLKEN,PWMSS1 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 13. "PCIE_1LANE_2LANE_SELECTION,Reserved" "0,1" newline bitfld.long 0x18 8.--10. "QSPI_MEMMAPPED_CS,QSPI CS MAPPING setting" "The QSPI configuration registers are accessed,An external device connected to CS0 is accessed,An external device connected to CS1 is accessed,An external device connected to CS2 is accessed..,?..." newline bitfld.long 0x18 5. "DCAN2_RAMINIT_START,DCAN2 RAM INIT START setting To initialize DCAN2 RAM the bit should be set to 0x1" "0,1" newline bitfld.long 0x18 4. "DSS_DESHDCP_DISABLE,DSS DESHDCP DISABLE setting" "0,1" newline bitfld.long 0x18 3. "DCAN1_RAMINIT_START,DCAN1 RAM INIT START setting To initialize DCAN1 RAM the bit should be set to 0x1" "0,1" newline bitfld.long 0x18 2. "DCAN2_RAMINIT_DONE,DCAN2 RAM INIT DONE status" "0,1" newline bitfld.long 0x18 1. "DCAN1_RAMINIT_DONE,DCAN1 RAM INIT DONE status" "0,1" newline bitfld.long 0x18 0. "DSS_DESHDCP_CLKEN,DSS DESHDCP CLOCK ENABLE setting" "0,1" line.long 0x1C "CTRL_CORE_CONTROL_DSP1_RST_VECT,Register for storing DSP1 reset vector" bitfld.long 0x1C 24.--26. "DSP1_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline hexmask.long.tbyte 0x1C 0.--21. 1. "DSP1_RST_VECT,DSP1 reset vector address" line.long 0x20 "CTRL_CORE_CONTROL_DSP2_RST_VECT,Register for storing DSP2 reset vector" bitfld.long 0x20 24.--26. "DSP2_NUM_MM,Number of DSP instances in the SoC" "?,1,2,?..." newline hexmask.long.tbyte 0x20 0.--21. 1. "DSP2_RST_VECT,DSP2 reset vector address" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE,Trim values for DSPEVE associated bandgap" hexmask.long.byte 0x24 8.--15. 1. "STD_FUSE_OPP_BGAP_DSPEVE_0,Trim values for DSPEVE associated bandgap" newline hexmask.long.byte 0x24 0.--7. 1. "STD_FUSE_OPP_BGAP_DSPEVE_1,Trim values for DSPEVE associated bandgap" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_BGAP_IVA,Trim values for IVA associated temperature sensor and bandgap" hexmask.long.byte 0x28 24.--31. 1. "STD_FUSE_OPP_BGAP_IVA_0,Trim values for IVA associated temperature sensor and bandgap" newline hexmask.long.byte 0x28 16.--23. 1. "STD_FUSE_OPP_BGAP_IVA_1,Trim values for IVA associated temperature sensor and bandgap" newline hexmask.long.byte 0x28 8.--15. 1. "STD_FUSE_OPP_BGAP_IVA_2,Trim values for IVA associated temperature sensor and bandgap" newline hexmask.long.byte 0x28 0.--7. 1. "STD_FUSE_OPP_BGAP_IVA_3,Trim values for IVA associated temperature sensor and bandgap" line.long 0x2C "CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL,DSPEVE SRAM LDO Control register" bitfld.long 0x2C 26. "LDOSRAMDSPEVE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x2C 21.--25. "LDOSRAMDSPEVE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 16.--20. "LDOSRAMDSPEVE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 10. "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x2C 5.--9. "LDOSRAMDSPEVE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 0.--4. "LDOSRAMDSPEVE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL,IVA SRAM LDO Control register" bitfld.long 0x30 26. "LDOSRAMIVA_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMIVA_RETMODE_MUX_CTRL_0,LDOSRAMIVA_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x30 21.--25. "LDOSRAMIVA_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 16.--20. "LDOSRAMIVA_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 10. "LDOSRAMIVA_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMIVA_ACTMODE_MUX_CTRL_0,LDOSRAMIVA_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x30 5.--9. "LDOSRAMIVA_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0.--4. "LDOSRAMIVA_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "CTRL_CORE_TEMP_SENSOR_DSPEVE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x34 11. "BGAP_TMPSOFF_DSPEVE,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x34 10. "BGAP_EOCZ_DSPEVE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x34 0.--9. 1. "BGAP_DTEMP_DSPEVE,Temperature data from the ADC" line.long 0x38 "CTRL_CORE_TEMP_SENSOR_IVA,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x38 11. "BGAP_TMPSOFF_IVA,This bit indicates the temperature sensor state" "0,1" newline bitfld.long 0x38 10. "BGAP_EOCZ_IVA,ADC End of Conversion" "0,1" newline hexmask.long.word 0x38 0.--9. 1. "BGAP_DTEMP_IVA,Temperature data from the ADC" line.long 0x3C "CTRL_CORE_BANDGAP_MASK_2,bgap_mask" bitfld.long 0x3C 22. "FREEZE_IVA,Freeze the FIFO IVA" "No operation,Freeze the FIFO" newline bitfld.long 0x3C 21. "FREEZE_DSPEVE,Freeze the FIFO DSPEVE" "No operation,Freeze the FIFO" newline bitfld.long 0x3C 19. "CLEAR_IVA,Reset the FIFO IVA" "No operation,Reset the FIFO" newline bitfld.long 0x3C 18. "CLEAR_DSPEVE,Reset the FIFO DSPEVE" "No operation,Reset the FIFO" newline bitfld.long 0x3C 3. "MASK_HOT_IVA,Mask for hot event IVA" "hot event is masked,hot event is not masked" newline bitfld.long 0x3C 2. "MASK_COLD_IVA,Mask for cold event IVA" "cold event is masked,cold event is not masked" newline bitfld.long 0x3C 1. "MASK_HOT_DSPEVE,Mask for hot event DSPEVE" "hot event is masked,hot event is not masked" newline bitfld.long 0x3C 0. "MASK_COLD_DSPEVE,Mask for cold event DSPEVE" "cold event is masked,cold event is not masked" line.long 0x40 "CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE,BGAP THRESHOLD DSPEVE" hexmask.long.word 0x40 16.--25. 1. "THOLD_HOT_DSPEVE,Value for the high temperature threshold" newline hexmask.long.word 0x40 0.--9. 1. "THOLD_COLD_DSPEVE,Value for the low temperature threshold" line.long 0x44 "CTRL_CORE_BANDGAP_THRESHOLD_IVA,BGAP THRESHOLD IVA" hexmask.long.word 0x44 16.--25. 1. "THOLD_HOT_IVA,Value for the high temperature threshold" newline hexmask.long.word 0x44 0.--9. 1. "THOLD_COLD_IVA,Value for the low temperature threshold" line.long 0x48 "CTRL_CORE_BANDGAP_TSHUT_DSPEVE,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x48 16.--25. 1. "TSHUT_HOT_DSPEVE,tshut value hot Software should not modify this bit field" newline hexmask.long.word 0x48 0.--9. 1. "TSHUT_COLD_DSPEVE,tshut value cold Software should not modify this bit field" line.long 0x4C "CTRL_CORE_BANDGAP_TSHUT_IVA,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x4C 16.--25. 1. "TSHUT_HOT_IVA,tshut value hot Software should not modify this bit field" newline hexmask.long.word 0x4C 0.--9. 1. "TSHUT_COLD_IVA,tshut value cold Software should not modify this bit field" rgroup.long 0x598++0x2B line.long 0x00 "CTRL_CORE_BANDGAP_STATUS_2,BGAP STATUS" bitfld.long 0x00 3. "HOT_IVA,Event for hot temperature iva bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 2. "COLD_IVA,Event for cold temperature iva bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 1. "HOT_DSPEVE,Event for hot temperature dspeve bandgap when '1'" "event not detected,event detected" newline bitfld.long 0x00 0. "COLD_DSPEVE,Event for cold temperature dspeve bandgap when '1'" "event not detected,event detected" line.long 0x04 "CTRL_CORE_DTEMP_DSPEVE_0,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_DSPEVE_0,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_0,temperature" line.long 0x08 "CTRL_CORE_DTEMP_DSPEVE_1,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x08 10.--31. 1. "DTEMP_TAG_DSPEVE_1,tag" newline hexmask.long.word 0x08 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_1,temperature" line.long 0x0C "CTRL_CORE_DTEMP_DSPEVE_2,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x0C 10.--31. 1. "DTEMP_TAG_DSPEVE_2,tag" newline hexmask.long.word 0x0C 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_2,temperature" line.long 0x10 "CTRL_CORE_DTEMP_DSPEVE_3,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x10 10.--31. 1. "DTEMP_TAG_DSPEVE_3,tag" newline hexmask.long.word 0x10 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_3,temperature" line.long 0x14 "CTRL_CORE_DTEMP_DSPEVE_4,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x14 10.--31. 1. "DTEMP_TAG_DSPEVE_4,tag" newline hexmask.long.word 0x14 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_4,temperature" line.long 0x18 "CTRL_CORE_DTEMP_IVA_0,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x18 10.--31. 1. "DTEMP_TAG_IVA_0,tag" newline hexmask.long.word 0x18 0.--9. 1. "DTEMP_TEMPERATURE_IVA_0,temperature" line.long 0x1C "CTRL_CORE_DTEMP_IVA_1,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x1C 10.--31. 1. "DTEMP_TAG_IVA_1,tag" newline hexmask.long.word 0x1C 0.--9. 1. "DTEMP_TEMPERATURE_IVA_1,temperature" line.long 0x20 "CTRL_CORE_DTEMP_IVA_2,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x20 10.--31. 1. "DTEMP_TAG_IVA_2,tag" newline hexmask.long.word 0x20 0.--9. 1. "DTEMP_TEMPERATURE_IVA_2,temperature" line.long 0x24 "CTRL_CORE_DTEMP_IVA_3,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x24 10.--31. 1. "DTEMP_TAG_IVA_3,tag" newline hexmask.long.word 0x24 0.--9. 1. "DTEMP_TEMPERATURE_IVA_3,temperature" line.long 0x28 "CTRL_CORE_DTEMP_IVA_4,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x28 10.--31. 1. "DTEMP_TAG_IVA_4,tag" newline hexmask.long.word 0x28 0.--9. 1. "DTEMP_TEMPERATURE_IVA_4,temperature" rgroup.long 0x5CC++0x0B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM" bitfld.long 0x00 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x00 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_IVA_2,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD" bitfld.long 0x04 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x04 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_IVA_3,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH" bitfld.long 0x08 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x08 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_IVA_4,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH" rgroup.long 0x5E0++0x0B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" bitfld.long 0x00 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x00 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_2,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" bitfld.long 0x04 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x04 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_3,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" bitfld.long 0x08 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x08 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_DSPEVE_4,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH" rgroup.long 0x5F4++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2,This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_MPU_3,AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM" group.long 0x680++0x07 line.long 0x00 "CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL,CORE 2nd SRAM LDO Control register" bitfld.long 0x00 26. "LDOSRAMCORE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_2_RETMODE_MUX_CTRL_0,LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL,CORE 3rd SRAM LDO Control register" bitfld.long 0x04 26. "LDOSRAMCORE_3_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_3_RETMODE_MUX_CTRL_0,LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x04 21.--25. "LDOSRAMCORE_3_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--20. "LDOSRAMCORE_3_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 10. "LDOSRAMCORE_3_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x04 5.--9. "LDOSRAMCORE_3_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "LDOSRAMCORE_3_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68C++0x07 line.long 0x00 "CTRL_CORE_NMI_DESTINATION_1,Register for routing NMI interrupt to respective cores" abitfld.long 0x00 16.--23. "IPU2_C1,Enable IPU2 CORE1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x00 8.--15. "IPU2_C0,Enable IPU2 CORE0 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x00 0.--7. "IPU1_C1,Enable IPU1 CORE1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" line.long 0x04 "CTRL_CORE_NMI_DESTINATION_2,Register for routing NMI interrupt to respective cores" abitfld.long 0x04 24.--31. "IPU1_C0,Enable IPU1 CORE0 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 16.--23. "DSP2,Enable DSP2 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 8.--15. "DSP1,Enable DSP1 to receive the NMI interrupt" "0x00=NMI disabled,0x01=NMI enabled" newline abitfld.long 0x04 0.--7. "MPU,Comes from Efuse (MPU_EN)" "0x00=NMI disabled,0x01=NMI enabled" rgroup.long 0x6A0++0x27 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0,Standard Fuse OPP VDD_DSPEVE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1,Standard Fuse OPP VDD_DSPEVE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2,Standard Fuse OPP VDD_DSPEVE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3,Standard Fuse OPP VDD_DSPEVE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4,Standard Fuse OPP VDD_DSPEVE [159:128]" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_7,Customer Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0,Standard Fuse Calibration override value [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1,Standard Fuse Calibration override value [63:32]" line.long 0x20 "CTRL_CORE_PCIE_POWER_STATE,Register to PCIe related controls" bitfld.long 0x20 31. "BYPASS_EN_APLL_PCIE,Bypass enable bit setting for APLL_PCIe" "0,1" newline bitfld.long 0x20 30. "CLKOOUTEN_APLL_PCIE,Clock output enable bit setting for APLL_PCIe" "0,1" newline hexmask.long.word 0x20 16.--25. 1. "EFUSE_TRIM_ACS_PCIE,MMR override capability for ACS_PCIe efuse trim bits" newline hexmask.long.word 0x20 0.--15. 1. "EFUSE_TRIM_PCIE_PLL,MMR override capability for PCIe PLL efuse trim bits" line.long 0x24 "CTRL_CORE_BOOTSTRAP,Register to view all the sysboot settings" bitfld.long 0x24 15. "DSP_CLOCK_DIVIDER,Permanently disables the internal PU/PD resistors on pads gpmc_a[27:24 " "0,1" newline bitfld.long 0x24 13. "BOOTDEVICESIZE,Select the size of the flash device on CS0" "8-bit,16-bit" newline bitfld.long 0x24 11.--12. "MUXCS0DEVICE,Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0" "Non-muxed device attached,Addr-Data Mux device attached,Reserved,Reserved" newline bitfld.long 0x24 10. "BOOTWAITEN,Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses" "Wait pin is not monitored for read accesses,Wait pin is monitored for read accesses" newline bitfld.long 0x24 8.--9. "SPEEDSELECT,Indicates the SYS_CLK1 frequency (from osc0)" "Reserved,20 MHz,27 MHz,19.2 MHz" newline bitfld.long 0x24 6.--7. "SYSBOOT_76,Sector offset for the location of the redundant SBL images in QSPI.0x0: 64 KB offset0x1: 128 KB offset0x2: 256 KB offset0x3: 512 KB offset" "0,1,2,3" newline bitfld.long 0x24 0.--5. "BOOTMODE,SYSBOOT mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x6DC++0x03 line.long 0x00 "CTRL_CORE_CONTROL_CSI,CSI control register.[New TDA2Px feature versus TDA2x]" bitfld.long 0x00 31. "CSI0_LANEENABLE4,csi0 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 30. "CSI0_LANEENABLE3,csi0 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 29. "CSI0_LANEENABLE2,csi0 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 28. "CSI0_LANEENABLE1,csi0 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 27. "CSI0_LANEENABLE0,csi0 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 26. "CSI1_LANEENABLE2,csi1 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 25. "CSI1_LANEENABLE1,csi1 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 24. "CSI1_LANEENABLE0,csi1 camera lane enable" "Lane module disabled,Lane module enabled" newline bitfld.long 0x00 11. "CSI0_MODE,csi0 mode" "0,1" newline bitfld.long 0x00 9.--10. "CSI0_CAMMODE,csi0 camera mode" "DPHY mode,Data/Strobe Transmission format,Data/Clock Transmission format,GPI mode" newline bitfld.long 0x00 8. "CSI0_CTRLCLKEN,csi0 camera clock enable control" "Disable for CTRLCLK,Active high enable for CTRLCLK" newline bitfld.long 0x00 3. "CSI1_MODE,csi1 mode" "0,1" newline bitfld.long 0x00 1.--2. "CSI1_CAMMODE,csi1 camera mode" "DPHY mode,Data/Strobe Transmission format,Data/Clock Transmission format,GPI mode" newline bitfld.long 0x00 0. "CSI1_CTRLCLKEN,csi1 camera clock enable control" "Disable for CTRLCLK,Active high enable for CTRLCLK" group.long 0x7A0++0x167 line.long 0x00 "CTRL_CORE_EVE1_IRQ_0_1," hexmask.long.word 0x00 16.--24. 1. "EVE1_IRQ_1," newline hexmask.long.word 0x00 0.--8. 1. "EVE1_IRQ_0," line.long 0x04 "CTRL_CORE_EVE1_IRQ_2_3," hexmask.long.word 0x04 16.--24. 1. "EVE1_IRQ_3," newline hexmask.long.word 0x04 0.--8. 1. "EVE1_IRQ_2," line.long 0x08 "CTRL_CORE_EVE1_IRQ_4_5," hexmask.long.word 0x08 16.--24. 1. "EVE1_IRQ_5," newline hexmask.long.word 0x08 0.--8. 1. "EVE1_IRQ_4," line.long 0x0C "CTRL_CORE_EVE1_IRQ_6_7," hexmask.long.word 0x0C 16.--24. 1. "EVE1_IRQ_7," newline hexmask.long.word 0x0C 0.--8. 1. "EVE1_IRQ_6," line.long 0x10 "CTRL_CORE_EVE2_IRQ_0_1," hexmask.long.word 0x10 16.--24. 1. "EVE2_IRQ_1," newline hexmask.long.word 0x10 0.--8. 1. "EVE2_IRQ_0," line.long 0x14 "CTRL_CORE_EVE2_IRQ_2_3," hexmask.long.word 0x14 16.--24. 1. "EVE2_IRQ_3," newline hexmask.long.word 0x14 0.--8. 1. "EVE2_IRQ_2," line.long 0x18 "CTRL_CORE_EVE2_IRQ_4_5," hexmask.long.word 0x18 16.--24. 1. "EVE2_IRQ_5," newline hexmask.long.word 0x18 0.--8. 1. "EVE2_IRQ_4," line.long 0x1C "CTRL_CORE_EVE2_IRQ_6_7," hexmask.long.word 0x1C 16.--24. 1. "EVE2_IRQ_7," newline hexmask.long.word 0x1C 0.--8. 1. "EVE2_IRQ_6," line.long 0x20 "CTRL_CORE_EVE3_IRQ_0_1," hexmask.long.word 0x20 16.--24. 1. "EVE3_IRQ_1," newline hexmask.long.word 0x20 0.--8. 1. "EVE3_IRQ_0," line.long 0x24 "CTRL_CORE_EVE3_IRQ_2_3," hexmask.long.word 0x24 16.--24. 1. "EVE3_IRQ_3," newline hexmask.long.word 0x24 0.--8. 1. "EVE3_IRQ_2," line.long 0x28 "CTRL_CORE_EVE3_IRQ_4_5," hexmask.long.word 0x28 16.--24. 1. "EVE3_IRQ_5," newline hexmask.long.word 0x28 0.--8. 1. "EVE3_IRQ_4," line.long 0x2C "CTRL_CORE_EVE3_IRQ_6_7," hexmask.long.word 0x2C 16.--24. 1. "EVE3_IRQ_7," newline hexmask.long.word 0x2C 0.--8. 1. "EVE3_IRQ_6," line.long 0x30 "CTRL_CORE_EVE4_IRQ_0_1," hexmask.long.word 0x30 16.--24. 1. "EVE4_IRQ_1," newline hexmask.long.word 0x30 0.--8. 1. "EVE4_IRQ_0," line.long 0x34 "CTRL_CORE_EVE4_IRQ_2_3," hexmask.long.word 0x34 16.--24. 1. "EVE4_IRQ_3," newline hexmask.long.word 0x34 0.--8. 1. "EVE4_IRQ_2," line.long 0x38 "CTRL_CORE_EVE4_IRQ_4_5," hexmask.long.word 0x38 16.--24. 1. "EVE4_IRQ_5," newline hexmask.long.word 0x38 0.--8. 1. "EVE4_IRQ_4," line.long 0x3C "CTRL_CORE_EVE4_IRQ_6_7," hexmask.long.word 0x3C 16.--24. 1. "EVE4_IRQ_7," newline hexmask.long.word 0x3C 0.--8. 1. "EVE4_IRQ_6," line.long 0x40 "CTRL_CORE_IPU1_IRQ_23_24," hexmask.long.word 0x40 16.--24. 1. "IPU1_IRQ_24," newline hexmask.long.word 0x40 0.--8. 1. "IPU1_IRQ_23," line.long 0x44 "CTRL_CORE_IPU1_IRQ_25_26," hexmask.long.word 0x44 16.--24. 1. "IPU1_IRQ_26," newline hexmask.long.word 0x44 0.--8. 1. "IPU1_IRQ_25," line.long 0x48 "CTRL_CORE_IPU1_IRQ_27_28," hexmask.long.word 0x48 16.--24. 1. "IPU1_IRQ_28," newline hexmask.long.word 0x48 0.--8. 1. "IPU1_IRQ_27," line.long 0x4C "CTRL_CORE_IPU1_IRQ_29_30," hexmask.long.word 0x4C 16.--24. 1. "IPU1_IRQ_30," newline hexmask.long.word 0x4C 0.--8. 1. "IPU1_IRQ_29," line.long 0x50 "CTRL_CORE_IPU1_IRQ_31_32," hexmask.long.word 0x50 16.--24. 1. "IPU1_IRQ_32," newline hexmask.long.word 0x50 0.--8. 1. "IPU1_IRQ_31," line.long 0x54 "CTRL_CORE_IPU1_IRQ_33_34," hexmask.long.word 0x54 16.--24. 1. "IPU1_IRQ_34," newline hexmask.long.word 0x54 0.--8. 1. "IPU1_IRQ_33," line.long 0x58 "CTRL_CORE_IPU1_IRQ_35_36," hexmask.long.word 0x58 16.--24. 1. "IPU1_IRQ_36," newline hexmask.long.word 0x58 0.--8. 1. "IPU1_IRQ_35," line.long 0x5C "CTRL_CORE_IPU1_IRQ_37_38," hexmask.long.word 0x5C 16.--24. 1. "IPU1_IRQ_38," newline hexmask.long.word 0x5C 0.--8. 1. "IPU1_IRQ_37," line.long 0x60 "CTRL_CORE_IPU1_IRQ_39_40," hexmask.long.word 0x60 16.--24. 1. "IPU1_IRQ_40," newline hexmask.long.word 0x60 0.--8. 1. "IPU1_IRQ_39," line.long 0x64 "CTRL_CORE_IPU1_IRQ_41_42," hexmask.long.word 0x64 16.--24. 1. "IPU1_IRQ_42," newline hexmask.long.word 0x64 0.--8. 1. "IPU1_IRQ_41," line.long 0x68 "CTRL_CORE_IPU1_IRQ_43_44," hexmask.long.word 0x68 16.--24. 1. "IPU1_IRQ_44," newline hexmask.long.word 0x68 0.--8. 1. "IPU1_IRQ_43," line.long 0x6C "CTRL_CORE_IPU1_IRQ_45_46," hexmask.long.word 0x6C 16.--24. 1. "IPU1_IRQ_46," newline hexmask.long.word 0x6C 0.--8. 1. "IPU1_IRQ_45," line.long 0x70 "CTRL_CORE_IPU1_IRQ_47_48," hexmask.long.word 0x70 16.--24. 1. "IPU1_IRQ_48," newline hexmask.long.word 0x70 0.--8. 1. "IPU1_IRQ_47," line.long 0x74 "CTRL_CORE_IPU1_IRQ_49_50," hexmask.long.word 0x74 16.--24. 1. "IPU1_IRQ_50," newline hexmask.long.word 0x74 0.--8. 1. "IPU1_IRQ_49," line.long 0x78 "CTRL_CORE_IPU1_IRQ_51_52," hexmask.long.word 0x78 16.--24. 1. "IPU1_IRQ_52," newline hexmask.long.word 0x78 0.--8. 1. "IPU1_IRQ_51," line.long 0x7C "CTRL_CORE_IPU1_IRQ_53_54," hexmask.long.word 0x7C 16.--24. 1. "IPU1_IRQ_54," newline hexmask.long.word 0x7C 0.--8. 1. "IPU1_IRQ_53," line.long 0x80 "CTRL_CORE_IPU1_IRQ_55_56," hexmask.long.word 0x80 16.--24. 1. "IPU1_IRQ_56," newline hexmask.long.word 0x80 0.--8. 1. "IPU1_IRQ_55," line.long 0x84 "CTRL_CORE_IPU1_IRQ_57_58," hexmask.long.word 0x84 16.--24. 1. "IPU1_IRQ_58," newline hexmask.long.word 0x84 0.--8. 1. "IPU1_IRQ_57," line.long 0x88 "CTRL_CORE_IPU1_IRQ_59_60," hexmask.long.word 0x88 16.--24. 1. "IPU1_IRQ_60," newline hexmask.long.word 0x88 0.--8. 1. "IPU1_IRQ_59," line.long 0x8C "CTRL_CORE_IPU1_IRQ_61_62," hexmask.long.word 0x8C 16.--24. 1. "IPU1_IRQ_62," newline hexmask.long.word 0x8C 0.--8. 1. "IPU1_IRQ_61," line.long 0x90 "CTRL_CORE_IPU1_IRQ_63_64," hexmask.long.word 0x90 16.--24. 1. "IPU1_IRQ_64," newline hexmask.long.word 0x90 0.--8. 1. "IPU1_IRQ_63," line.long 0x94 "CTRL_CORE_IPU1_IRQ_65_66," hexmask.long.word 0x94 16.--24. 1. "IPU1_IRQ_66," newline hexmask.long.word 0x94 0.--8. 1. "IPU1_IRQ_65," line.long 0x98 "CTRL_CORE_IPU1_IRQ_67_68," hexmask.long.word 0x98 16.--24. 1. "IPU1_IRQ_68," newline hexmask.long.word 0x98 0.--8. 1. "IPU1_IRQ_67," line.long 0x9C "CTRL_CORE_IPU1_IRQ_69_70," hexmask.long.word 0x9C 16.--24. 1. "IPU1_IRQ_70," newline hexmask.long.word 0x9C 0.--8. 1. "IPU1_IRQ_69," line.long 0xA0 "CTRL_CORE_IPU1_IRQ_71_72," hexmask.long.word 0xA0 16.--24. 1. "IPU1_IRQ_72," newline hexmask.long.word 0xA0 0.--8. 1. "IPU1_IRQ_71," line.long 0xA4 "CTRL_CORE_IPU1_IRQ_73_74," hexmask.long.word 0xA4 16.--24. 1. "IPU1_IRQ_74," newline hexmask.long.word 0xA4 0.--8. 1. "IPU1_IRQ_73," line.long 0xA8 "CTRL_CORE_IPU1_IRQ_75_76," hexmask.long.word 0xA8 16.--24. 1. "IPU1_IRQ_76," newline hexmask.long.word 0xA8 0.--8. 1. "IPU1_IRQ_75," line.long 0xAC "CTRL_CORE_IPU1_IRQ_77_78," hexmask.long.word 0xAC 16.--24. 1. "IPU1_IRQ_78," newline hexmask.long.word 0xAC 0.--8. 1. "IPU1_IRQ_77," line.long 0xB0 "CTRL_CORE_IPU1_IRQ_79_80," hexmask.long.word 0xB0 0.--8. 1. "IPU1_IRQ_79," line.long 0xB4 "CTRL_CORE_IPU2_IRQ_23_24," hexmask.long.word 0xB4 16.--24. 1. "IPU2_IRQ_24," newline hexmask.long.word 0xB4 0.--8. 1. "IPU2_IRQ_23," line.long 0xB8 "CTRL_CORE_IPU2_IRQ_25_26," hexmask.long.word 0xB8 16.--24. 1. "IPU2_IRQ_26," newline hexmask.long.word 0xB8 0.--8. 1. "IPU2_IRQ_25," line.long 0xBC "CTRL_CORE_IPU2_IRQ_27_28," hexmask.long.word 0xBC 16.--24. 1. "IPU2_IRQ_28," newline hexmask.long.word 0xBC 0.--8. 1. "IPU2_IRQ_27," line.long 0xC0 "CTRL_CORE_IPU2_IRQ_29_30," hexmask.long.word 0xC0 16.--24. 1. "IPU2_IRQ_30," newline hexmask.long.word 0xC0 0.--8. 1. "IPU2_IRQ_29," line.long 0xC4 "CTRL_CORE_IPU2_IRQ_31_32," hexmask.long.word 0xC4 16.--24. 1. "IPU2_IRQ_32," newline hexmask.long.word 0xC4 0.--8. 1. "IPU2_IRQ_31," line.long 0xC8 "CTRL_CORE_IPU2_IRQ_33_34," hexmask.long.word 0xC8 16.--24. 1. "IPU2_IRQ_34," newline hexmask.long.word 0xC8 0.--8. 1. "IPU2_IRQ_33," line.long 0xCC "CTRL_CORE_IPU2_IRQ_35_36," hexmask.long.word 0xCC 16.--24. 1. "IPU2_IRQ_36," newline hexmask.long.word 0xCC 0.--8. 1. "IPU2_IRQ_35," line.long 0xD0 "CTRL_CORE_IPU2_IRQ_37_38," hexmask.long.word 0xD0 16.--24. 1. "IPU2_IRQ_38," newline hexmask.long.word 0xD0 0.--8. 1. "IPU2_IRQ_37," line.long 0xD4 "CTRL_CORE_IPU2_IRQ_39_40," hexmask.long.word 0xD4 16.--24. 1. "IPU2_IRQ_40," newline hexmask.long.word 0xD4 0.--8. 1. "IPU2_IRQ_39," line.long 0xD8 "CTRL_CORE_IPU2_IRQ_41_42," hexmask.long.word 0xD8 16.--24. 1. "IPU2_IRQ_42," newline hexmask.long.word 0xD8 0.--8. 1. "IPU2_IRQ_41," line.long 0xDC "CTRL_CORE_IPU2_IRQ_43_44," hexmask.long.word 0xDC 16.--24. 1. "IPU2_IRQ_44," newline hexmask.long.word 0xDC 0.--8. 1. "IPU2_IRQ_43," line.long 0xE0 "CTRL_CORE_IPU2_IRQ_45_46," hexmask.long.word 0xE0 16.--24. 1. "IPU2_IRQ_46," newline hexmask.long.word 0xE0 0.--8. 1. "IPU2_IRQ_45," line.long 0xE4 "CTRL_CORE_IPU2_IRQ_47_48," hexmask.long.word 0xE4 16.--24. 1. "IPU2_IRQ_48," newline hexmask.long.word 0xE4 0.--8. 1. "IPU2_IRQ_47," line.long 0xE8 "CTRL_CORE_IPU2_IRQ_49_50," hexmask.long.word 0xE8 16.--24. 1. "IPU2_IRQ_50," newline hexmask.long.word 0xE8 0.--8. 1. "IPU2_IRQ_49," line.long 0xEC "CTRL_CORE_IPU2_IRQ_51_52," hexmask.long.word 0xEC 16.--24. 1. "IPU2_IRQ_52," newline hexmask.long.word 0xEC 0.--8. 1. "IPU2_IRQ_51," line.long 0xF0 "CTRL_CORE_IPU2_IRQ_53_54," hexmask.long.word 0xF0 16.--24. 1. "IPU2_IRQ_54," newline hexmask.long.word 0xF0 0.--8. 1. "IPU2_IRQ_53," line.long 0xF4 "CTRL_CORE_IPU2_IRQ_55_56," hexmask.long.word 0xF4 16.--24. 1. "IPU2_IRQ_56," newline hexmask.long.word 0xF4 0.--8. 1. "IPU2_IRQ_55," line.long 0xF8 "CTRL_CORE_IPU2_IRQ_57_58," hexmask.long.word 0xF8 16.--24. 1. "IPU2_IRQ_58," newline hexmask.long.word 0xF8 0.--8. 1. "IPU2_IRQ_57," line.long 0xFC "CTRL_CORE_IPU2_IRQ_59_60," hexmask.long.word 0xFC 16.--24. 1. "IPU2_IRQ_60," newline hexmask.long.word 0xFC 0.--8. 1. "IPU2_IRQ_59," line.long 0x100 "CTRL_CORE_IPU2_IRQ_61_62," hexmask.long.word 0x100 16.--24. 1. "IPU2_IRQ_62," newline hexmask.long.word 0x100 0.--8. 1. "IPU2_IRQ_61," line.long 0x104 "CTRL_CORE_IPU2_IRQ_63_64," hexmask.long.word 0x104 16.--24. 1. "IPU2_IRQ_64," newline hexmask.long.word 0x104 0.--8. 1. "IPU2_IRQ_63," line.long 0x108 "CTRL_CORE_IPU2_IRQ_65_66," hexmask.long.word 0x108 16.--24. 1. "IPU2_IRQ_66," newline hexmask.long.word 0x108 0.--8. 1. "IPU2_IRQ_65," line.long 0x10C "CTRL_CORE_IPU2_IRQ_67_68," hexmask.long.word 0x10C 16.--24. 1. "IPU2_IRQ_68," newline hexmask.long.word 0x10C 0.--8. 1. "IPU2_IRQ_67," line.long 0x110 "CTRL_CORE_IPU2_IRQ_69_70," hexmask.long.word 0x110 16.--24. 1. "IPU2_IRQ_70," newline hexmask.long.word 0x110 0.--8. 1. "IPU2_IRQ_69," line.long 0x114 "CTRL_CORE_IPU2_IRQ_71_72," hexmask.long.word 0x114 16.--24. 1. "IPU2_IRQ_72," newline hexmask.long.word 0x114 0.--8. 1. "IPU2_IRQ_71," line.long 0x118 "CTRL_CORE_IPU2_IRQ_73_74," hexmask.long.word 0x118 16.--24. 1. "IPU2_IRQ_74," newline hexmask.long.word 0x118 0.--8. 1. "IPU2_IRQ_73," line.long 0x11C "CTRL_CORE_IPU2_IRQ_75_76," hexmask.long.word 0x11C 16.--24. 1. "IPU2_IRQ_76," newline hexmask.long.word 0x11C 0.--8. 1. "IPU2_IRQ_75," line.long 0x120 "CTRL_CORE_IPU2_IRQ_77_78," hexmask.long.word 0x120 16.--24. 1. "IPU2_IRQ_78," newline hexmask.long.word 0x120 0.--8. 1. "IPU2_IRQ_77," line.long 0x124 "CTRL_CORE_IPU2_IRQ_79_80," hexmask.long.word 0x124 0.--8. 1. "IPU2_IRQ_79," line.long 0x128 "CTRL_CORE_PRUSS1_IRQ_32_33," hexmask.long.word 0x128 16.--24. 1. "PRUSS1_IRQ_33," newline hexmask.long.word 0x128 0.--8. 1. "PRUSS1_IRQ_32," line.long 0x12C "CTRL_CORE_PRUSS1_IRQ_34_35," hexmask.long.word 0x12C 16.--24. 1. "PRUSS1_IRQ_35," newline hexmask.long.word 0x12C 0.--8. 1. "PRUSS1_IRQ_34," line.long 0x130 "CTRL_CORE_PRUSS1_IRQ_36_37," hexmask.long.word 0x130 16.--24. 1. "PRUSS1_IRQ_37," newline hexmask.long.word 0x130 0.--8. 1. "PRUSS1_IRQ_36," line.long 0x134 "CTRL_CORE_PRUSS1_IRQ_38_39," hexmask.long.word 0x134 16.--24. 1. "PRUSS1_IRQ_39," newline hexmask.long.word 0x134 0.--8. 1. "PRUSS1_IRQ_38," line.long 0x138 "CTRL_CORE_PRUSS1_IRQ_40_41," hexmask.long.word 0x138 16.--24. 1. "PRUSS1_IRQ_41," newline hexmask.long.word 0x138 0.--8. 1. "PRUSS1_IRQ_40," line.long 0x13C "CTRL_CORE_PRUSS1_IRQ_42_43," hexmask.long.word 0x13C 16.--24. 1. "PRUSS1_IRQ_43," newline hexmask.long.word 0x13C 0.--8. 1. "PRUSS1_IRQ_42," line.long 0x140 "CTRL_CORE_PRUSS1_IRQ_44_45," hexmask.long.word 0x140 16.--24. 1. "PRUSS1_IRQ_45," newline hexmask.long.word 0x140 0.--8. 1. "PRUSS1_IRQ_44," line.long 0x144 "CTRL_CORE_PRUSS1_IRQ_46_47," hexmask.long.word 0x144 16.--24. 1. "PRUSS1_IRQ_47," newline hexmask.long.word 0x144 0.--8. 1. "PRUSS1_IRQ_46," line.long 0x148 "CTRL_CORE_PRUSS1_IRQ_48_49," hexmask.long.word 0x148 16.--24. 1. "PRUSS1_IRQ_49," newline hexmask.long.word 0x148 0.--8. 1. "PRUSS1_IRQ_48," line.long 0x14C "CTRL_CORE_PRUSS1_IRQ_50_51," hexmask.long.word 0x14C 16.--24. 1. "PRUSS1_IRQ_51," newline hexmask.long.word 0x14C 0.--8. 1. "PRUSS1_IRQ_50," line.long 0x150 "CTRL_CORE_PRUSS1_IRQ_52_53," hexmask.long.word 0x150 16.--24. 1. "PRUSS1_IRQ_53," newline hexmask.long.word 0x150 0.--8. 1. "PRUSS1_IRQ_52," line.long 0x154 "CTRL_CORE_PRUSS1_IRQ_54_55," hexmask.long.word 0x154 16.--24. 1. "PRUSS1_IRQ_55," newline hexmask.long.word 0x154 0.--8. 1. "PRUSS1_IRQ_54," line.long 0x158 "CTRL_CORE_PRUSS1_IRQ_56_57," hexmask.long.word 0x158 16.--24. 1. "PRUSS1_IRQ_57," newline hexmask.long.word 0x158 0.--8. 1. "PRUSS1_IRQ_56," line.long 0x15C "CTRL_CORE_PRUSS1_IRQ_58_59," hexmask.long.word 0x15C 16.--24. 1. "PRUSS1_IRQ_59," newline hexmask.long.word 0x15C 0.--8. 1. "PRUSS1_IRQ_58," line.long 0x160 "CTRL_CORE_PRUSS1_IRQ_60_61," hexmask.long.word 0x160 16.--24. 1. "PRUSS1_IRQ_61," newline hexmask.long.word 0x160 0.--8. 1. "PRUSS1_IRQ_60," line.long 0x164 "CTRL_CORE_PRUSS1_IRQ_62_63," hexmask.long.word 0x164 16.--24. 1. "PRUSS1_IRQ_63," newline hexmask.long.word 0x164 0.--8. 1. "PRUSS1_IRQ_62," group.long 0x948++0x3FF line.long 0x00 "CTRL_CORE_DSP1_IRQ_32_33," hexmask.long.word 0x00 16.--24. 1. "DSP1_IRQ_33," newline hexmask.long.word 0x00 0.--8. 1. "DSP1_IRQ_32," line.long 0x04 "CTRL_CORE_DSP1_IRQ_34_35," hexmask.long.word 0x04 16.--24. 1. "DSP1_IRQ_35," newline hexmask.long.word 0x04 0.--8. 1. "DSP1_IRQ_34," line.long 0x08 "CTRL_CORE_DSP1_IRQ_36_37," hexmask.long.word 0x08 16.--24. 1. "DSP1_IRQ_37," newline hexmask.long.word 0x08 0.--8. 1. "DSP1_IRQ_36," line.long 0x0C "CTRL_CORE_DSP1_IRQ_38_39," hexmask.long.word 0x0C 16.--24. 1. "DSP1_IRQ_39," newline hexmask.long.word 0x0C 0.--8. 1. "DSP1_IRQ_38," line.long 0x10 "CTRL_CORE_DSP1_IRQ_40_41," hexmask.long.word 0x10 16.--24. 1. "DSP1_IRQ_41," newline hexmask.long.word 0x10 0.--8. 1. "DSP1_IRQ_40," line.long 0x14 "CTRL_CORE_DSP1_IRQ_42_43," hexmask.long.word 0x14 16.--24. 1. "DSP1_IRQ_43," newline hexmask.long.word 0x14 0.--8. 1. "DSP1_IRQ_42," line.long 0x18 "CTRL_CORE_DSP1_IRQ_44_45," hexmask.long.word 0x18 16.--24. 1. "DSP1_IRQ_45," newline hexmask.long.word 0x18 0.--8. 1. "DSP1_IRQ_44," line.long 0x1C "CTRL_CORE_DSP1_IRQ_46_47," hexmask.long.word 0x1C 16.--24. 1. "DSP1_IRQ_47," newline hexmask.long.word 0x1C 0.--8. 1. "DSP1_IRQ_46," line.long 0x20 "CTRL_CORE_DSP1_IRQ_48_49," hexmask.long.word 0x20 16.--24. 1. "DSP1_IRQ_49," newline hexmask.long.word 0x20 0.--8. 1. "DSP1_IRQ_48," line.long 0x24 "CTRL_CORE_DSP1_IRQ_50_51," hexmask.long.word 0x24 16.--24. 1. "DSP1_IRQ_51," newline hexmask.long.word 0x24 0.--8. 1. "DSP1_IRQ_50," line.long 0x28 "CTRL_CORE_DSP1_IRQ_52_53," hexmask.long.word 0x28 16.--24. 1. "DSP1_IRQ_53," newline hexmask.long.word 0x28 0.--8. 1. "DSP1_IRQ_52," line.long 0x2C "CTRL_CORE_DSP1_IRQ_54_55," hexmask.long.word 0x2C 16.--24. 1. "DSP1_IRQ_55," newline hexmask.long.word 0x2C 0.--8. 1. "DSP1_IRQ_54," line.long 0x30 "CTRL_CORE_DSP1_IRQ_56_57," hexmask.long.word 0x30 16.--24. 1. "DSP1_IRQ_57," newline hexmask.long.word 0x30 0.--8. 1. "DSP1_IRQ_56," line.long 0x34 "CTRL_CORE_DSP1_IRQ_58_59," hexmask.long.word 0x34 16.--24. 1. "DSP1_IRQ_59," newline hexmask.long.word 0x34 0.--8. 1. "DSP1_IRQ_58," line.long 0x38 "CTRL_CORE_DSP1_IRQ_60_61," hexmask.long.word 0x38 16.--24. 1. "DSP1_IRQ_61," newline hexmask.long.word 0x38 0.--8. 1. "DSP1_IRQ_60," line.long 0x3C "CTRL_CORE_DSP1_IRQ_62_63," hexmask.long.word 0x3C 16.--24. 1. "DSP1_IRQ_63," newline hexmask.long.word 0x3C 0.--8. 1. "DSP1_IRQ_62," line.long 0x40 "CTRL_CORE_DSP1_IRQ_64_65," hexmask.long.word 0x40 16.--24. 1. "DSP1_IRQ_65," newline hexmask.long.word 0x40 0.--8. 1. "DSP1_IRQ_64," line.long 0x44 "CTRL_CORE_DSP1_IRQ_66_67," hexmask.long.word 0x44 16.--24. 1. "DSP1_IRQ_67," newline hexmask.long.word 0x44 0.--8. 1. "DSP1_IRQ_66," line.long 0x48 "CTRL_CORE_DSP1_IRQ_68_69," hexmask.long.word 0x48 16.--24. 1. "DSP1_IRQ_69," newline hexmask.long.word 0x48 0.--8. 1. "DSP1_IRQ_68," line.long 0x4C "CTRL_CORE_DSP1_IRQ_70_71," hexmask.long.word 0x4C 16.--24. 1. "DSP1_IRQ_71," newline hexmask.long.word 0x4C 0.--8. 1. "DSP1_IRQ_70," line.long 0x50 "CTRL_CORE_DSP1_IRQ_72_73," hexmask.long.word 0x50 16.--24. 1. "DSP1_IRQ_73," newline hexmask.long.word 0x50 0.--8. 1. "DSP1_IRQ_72," line.long 0x54 "CTRL_CORE_DSP1_IRQ_74_75," hexmask.long.word 0x54 16.--24. 1. "DSP1_IRQ_75," newline hexmask.long.word 0x54 0.--8. 1. "DSP1_IRQ_74," line.long 0x58 "CTRL_CORE_DSP1_IRQ_76_77," hexmask.long.word 0x58 16.--24. 1. "DSP1_IRQ_77," newline hexmask.long.word 0x58 0.--8. 1. "DSP1_IRQ_76," line.long 0x5C "CTRL_CORE_DSP1_IRQ_78_79," hexmask.long.word 0x5C 16.--24. 1. "DSP1_IRQ_79," newline hexmask.long.word 0x5C 0.--8. 1. "DSP1_IRQ_78," line.long 0x60 "CTRL_CORE_DSP1_IRQ_80_81," hexmask.long.word 0x60 16.--24. 1. "DSP1_IRQ_81," newline hexmask.long.word 0x60 0.--8. 1. "DSP1_IRQ_80," line.long 0x64 "CTRL_CORE_DSP1_IRQ_82_83," hexmask.long.word 0x64 16.--24. 1. "DSP1_IRQ_83," newline hexmask.long.word 0x64 0.--8. 1. "DSP1_IRQ_82," line.long 0x68 "CTRL_CORE_DSP1_IRQ_84_85," hexmask.long.word 0x68 16.--24. 1. "DSP1_IRQ_85," newline hexmask.long.word 0x68 0.--8. 1. "DSP1_IRQ_84," line.long 0x6C "CTRL_CORE_DSP1_IRQ_86_87," hexmask.long.word 0x6C 16.--24. 1. "DSP1_IRQ_87," newline hexmask.long.word 0x6C 0.--8. 1. "DSP1_IRQ_86," line.long 0x70 "CTRL_CORE_DSP1_IRQ_88_89," hexmask.long.word 0x70 16.--24. 1. "DSP1_IRQ_89," newline hexmask.long.word 0x70 0.--8. 1. "DSP1_IRQ_88," line.long 0x74 "CTRL_CORE_DSP1_IRQ_90_91," hexmask.long.word 0x74 16.--24. 1. "DSP1_IRQ_91," newline hexmask.long.word 0x74 0.--8. 1. "DSP1_IRQ_90," line.long 0x78 "CTRL_CORE_DSP1_IRQ_92_93," hexmask.long.word 0x78 16.--24. 1. "DSP1_IRQ_93," newline hexmask.long.word 0x78 0.--8. 1. "DSP1_IRQ_92," line.long 0x7C "CTRL_CORE_DSP1_IRQ_94_95," hexmask.long.word 0x7C 16.--24. 1. "DSP1_IRQ_95," newline hexmask.long.word 0x7C 0.--8. 1. "DSP1_IRQ_94," line.long 0x80 "CTRL_CORE_DSP2_IRQ_32_33," hexmask.long.word 0x80 16.--24. 1. "DSP2_IRQ_33," newline hexmask.long.word 0x80 0.--8. 1. "DSP2_IRQ_32," line.long 0x84 "CTRL_CORE_DSP2_IRQ_34_35," hexmask.long.word 0x84 16.--24. 1. "DSP2_IRQ_35," newline hexmask.long.word 0x84 0.--8. 1. "DSP2_IRQ_34," line.long 0x88 "CTRL_CORE_DSP2_IRQ_36_37," hexmask.long.word 0x88 16.--24. 1. "DSP2_IRQ_37," newline hexmask.long.word 0x88 0.--8. 1. "DSP2_IRQ_36," line.long 0x8C "CTRL_CORE_DSP2_IRQ_38_39," hexmask.long.word 0x8C 16.--24. 1. "DSP2_IRQ_39," newline hexmask.long.word 0x8C 0.--8. 1. "DSP2_IRQ_38," line.long 0x90 "CTRL_CORE_DSP2_IRQ_40_41," hexmask.long.word 0x90 16.--24. 1. "DSP2_IRQ_41," newline hexmask.long.word 0x90 0.--8. 1. "DSP2_IRQ_40," line.long 0x94 "CTRL_CORE_DSP2_IRQ_42_43," hexmask.long.word 0x94 16.--24. 1. "DSP2_IRQ_43," newline hexmask.long.word 0x94 0.--8. 1. "DSP2_IRQ_42," line.long 0x98 "CTRL_CORE_DSP2_IRQ_44_45," hexmask.long.word 0x98 16.--24. 1. "DSP2_IRQ_45," newline hexmask.long.word 0x98 0.--8. 1. "DSP2_IRQ_44," line.long 0x9C "CTRL_CORE_DSP2_IRQ_46_47," hexmask.long.word 0x9C 16.--24. 1. "DSP2_IRQ_47," newline hexmask.long.word 0x9C 0.--8. 1. "DSP2_IRQ_46," line.long 0xA0 "CTRL_CORE_DSP2_IRQ_48_49," hexmask.long.word 0xA0 16.--24. 1. "DSP2_IRQ_49," newline hexmask.long.word 0xA0 0.--8. 1. "DSP2_IRQ_48," line.long 0xA4 "CTRL_CORE_DSP2_IRQ_50_51," hexmask.long.word 0xA4 16.--24. 1. "DSP2_IRQ_51," newline hexmask.long.word 0xA4 0.--8. 1. "DSP2_IRQ_50," line.long 0xA8 "CTRL_CORE_DSP2_IRQ_52_53," hexmask.long.word 0xA8 16.--24. 1. "DSP2_IRQ_53," newline hexmask.long.word 0xA8 0.--8. 1. "DSP2_IRQ_52," line.long 0xAC "CTRL_CORE_DSP2_IRQ_54_55," hexmask.long.word 0xAC 16.--24. 1. "DSP2_IRQ_55," newline hexmask.long.word 0xAC 0.--8. 1. "DSP2_IRQ_54," line.long 0xB0 "CTRL_CORE_DSP2_IRQ_56_57," hexmask.long.word 0xB0 16.--24. 1. "DSP2_IRQ_57," newline hexmask.long.word 0xB0 0.--8. 1. "DSP2_IRQ_56," line.long 0xB4 "CTRL_CORE_DSP2_IRQ_58_59," hexmask.long.word 0xB4 16.--24. 1. "DSP2_IRQ_59," newline hexmask.long.word 0xB4 0.--8. 1. "DSP2_IRQ_58," line.long 0xB8 "CTRL_CORE_DSP2_IRQ_60_61," hexmask.long.word 0xB8 16.--24. 1. "DSP2_IRQ_61," newline hexmask.long.word 0xB8 0.--8. 1. "DSP2_IRQ_60," line.long 0xBC "CTRL_CORE_DSP2_IRQ_62_63," hexmask.long.word 0xBC 16.--24. 1. "DSP2_IRQ_63," newline hexmask.long.word 0xBC 0.--8. 1. "DSP2_IRQ_62," line.long 0xC0 "CTRL_CORE_DSP2_IRQ_64_65," hexmask.long.word 0xC0 16.--24. 1. "DSP2_IRQ_65," newline hexmask.long.word 0xC0 0.--8. 1. "DSP2_IRQ_64," line.long 0xC4 "CTRL_CORE_DSP2_IRQ_66_67," hexmask.long.word 0xC4 16.--24. 1. "DSP2_IRQ_67," newline hexmask.long.word 0xC4 0.--8. 1. "DSP2_IRQ_66," line.long 0xC8 "CTRL_CORE_DSP2_IRQ_68_69," hexmask.long.word 0xC8 16.--24. 1. "DSP2_IRQ_69," newline hexmask.long.word 0xC8 0.--8. 1. "DSP2_IRQ_68," line.long 0xCC "CTRL_CORE_DSP2_IRQ_70_71," hexmask.long.word 0xCC 16.--24. 1. "DSP2_IRQ_71," newline hexmask.long.word 0xCC 0.--8. 1. "DSP2_IRQ_70," line.long 0xD0 "CTRL_CORE_DSP2_IRQ_72_73," hexmask.long.word 0xD0 16.--24. 1. "DSP2_IRQ_73," newline hexmask.long.word 0xD0 0.--8. 1. "DSP2_IRQ_72," line.long 0xD4 "CTRL_CORE_DSP2_IRQ_74_75," hexmask.long.word 0xD4 16.--24. 1. "DSP2_IRQ_75," newline hexmask.long.word 0xD4 0.--8. 1. "DSP2_IRQ_74," line.long 0xD8 "CTRL_CORE_DSP2_IRQ_76_77," hexmask.long.word 0xD8 16.--24. 1. "DSP2_IRQ_77," newline hexmask.long.word 0xD8 0.--8. 1. "DSP2_IRQ_76," line.long 0xDC "CTRL_CORE_DSP2_IRQ_78_79," hexmask.long.word 0xDC 16.--24. 1. "DSP2_IRQ_79," newline hexmask.long.word 0xDC 0.--8. 1. "DSP2_IRQ_78," line.long 0xE0 "CTRL_CORE_DSP2_IRQ_80_81," hexmask.long.word 0xE0 16.--24. 1. "DSP2_IRQ_81," newline hexmask.long.word 0xE0 0.--8. 1. "DSP2_IRQ_80," line.long 0xE4 "CTRL_CORE_DSP2_IRQ_82_83," hexmask.long.word 0xE4 16.--24. 1. "DSP2_IRQ_83," newline hexmask.long.word 0xE4 0.--8. 1. "DSP2_IRQ_82," line.long 0xE8 "CTRL_CORE_DSP2_IRQ_84_85," hexmask.long.word 0xE8 16.--24. 1. "DSP2_IRQ_85," newline hexmask.long.word 0xE8 0.--8. 1. "DSP2_IRQ_84," line.long 0xEC "CTRL_CORE_DSP2_IRQ_86_87," hexmask.long.word 0xEC 16.--24. 1. "DSP2_IRQ_87," newline hexmask.long.word 0xEC 0.--8. 1. "DSP2_IRQ_86," line.long 0xF0 "CTRL_CORE_DSP2_IRQ_88_89," hexmask.long.word 0xF0 16.--24. 1. "DSP2_IRQ_89," newline hexmask.long.word 0xF0 0.--8. 1. "DSP2_IRQ_88," line.long 0xF4 "CTRL_CORE_DSP2_IRQ_90_91," hexmask.long.word 0xF4 16.--24. 1. "DSP2_IRQ_91," newline hexmask.long.word 0xF4 0.--8. 1. "DSP2_IRQ_90," line.long 0xF8 "CTRL_CORE_DSP2_IRQ_92_93," hexmask.long.word 0xF8 16.--24. 1. "DSP2_IRQ_93," newline hexmask.long.word 0xF8 0.--8. 1. "DSP2_IRQ_92," line.long 0xFC "CTRL_CORE_DSP2_IRQ_94_95," hexmask.long.word 0xFC 16.--24. 1. "DSP2_IRQ_95," newline hexmask.long.word 0xFC 0.--8. 1. "DSP2_IRQ_94," line.long 0x100 "CTRL_CORE_MPU_IRQ_4_7," hexmask.long.word 0x100 16.--24. 1. "MPU_IRQ_7," newline hexmask.long.word 0x100 0.--8. 1. "MPU_IRQ_4," line.long 0x104 "CTRL_CORE_MPU_IRQ_8_9," hexmask.long.word 0x104 16.--24. 1. "MPU_IRQ_9," newline hexmask.long.word 0x104 0.--8. 1. "MPU_IRQ_8," line.long 0x108 "CTRL_CORE_MPU_IRQ_10_11," hexmask.long.word 0x108 16.--24. 1. "MPU_IRQ_11," newline hexmask.long.word 0x108 0.--8. 1. "MPU_IRQ_10,NOTE: This bit field is not functional" line.long 0x10C "CTRL_CORE_MPU_IRQ_12_13," hexmask.long.word 0x10C 16.--24. 1. "MPU_IRQ_13," newline hexmask.long.word 0x10C 0.--8. 1. "MPU_IRQ_12," line.long 0x110 "CTRL_CORE_MPU_IRQ_14_15," hexmask.long.word 0x110 16.--24. 1. "MPU_IRQ_15," newline hexmask.long.word 0x110 0.--8. 1. "MPU_IRQ_14," line.long 0x114 "CTRL_CORE_MPU_IRQ_16_17," hexmask.long.word 0x114 16.--24. 1. "MPU_IRQ_17," newline hexmask.long.word 0x114 0.--8. 1. "MPU_IRQ_16," line.long 0x118 "CTRL_CORE_MPU_IRQ_18_19," hexmask.long.word 0x118 16.--24. 1. "MPU_IRQ_19," newline hexmask.long.word 0x118 0.--8. 1. "MPU_IRQ_18," line.long 0x11C "CTRL_CORE_MPU_IRQ_20_21," hexmask.long.word 0x11C 16.--24. 1. "MPU_IRQ_21," newline hexmask.long.word 0x11C 0.--8. 1. "MPU_IRQ_20," line.long 0x120 "CTRL_CORE_MPU_IRQ_22_23," hexmask.long.word 0x120 16.--24. 1. "MPU_IRQ_23," newline hexmask.long.word 0x120 0.--8. 1. "MPU_IRQ_22," line.long 0x124 "CTRL_CORE_MPU_IRQ_24_25," hexmask.long.word 0x124 16.--24. 1. "MPU_IRQ_25," newline hexmask.long.word 0x124 0.--8. 1. "MPU_IRQ_24," line.long 0x128 "CTRL_CORE_MPU_IRQ_26_27," hexmask.long.word 0x128 16.--24. 1. "MPU_IRQ_27," newline hexmask.long.word 0x128 0.--8. 1. "MPU_IRQ_26," line.long 0x12C "CTRL_CORE_MPU_IRQ_28_29," hexmask.long.word 0x12C 16.--24. 1. "MPU_IRQ_29," newline hexmask.long.word 0x12C 0.--8. 1. "MPU_IRQ_28," line.long 0x130 "CTRL_CORE_MPU_IRQ_30_31," hexmask.long.word 0x130 16.--24. 1. "MPU_IRQ_31," newline hexmask.long.word 0x130 0.--8. 1. "MPU_IRQ_30," line.long 0x134 "CTRL_CORE_MPU_IRQ_32_33," hexmask.long.word 0x134 16.--24. 1. "MPU_IRQ_33," newline hexmask.long.word 0x134 0.--8. 1. "MPU_IRQ_32," line.long 0x138 "CTRL_CORE_MPU_IRQ_34_35," hexmask.long.word 0x138 16.--24. 1. "MPU_IRQ_35," newline hexmask.long.word 0x138 0.--8. 1. "MPU_IRQ_34," line.long 0x13C "CTRL_CORE_MPU_IRQ_36_37," hexmask.long.word 0x13C 16.--24. 1. "MPU_IRQ_37," newline hexmask.long.word 0x13C 0.--8. 1. "MPU_IRQ_36," line.long 0x140 "CTRL_CORE_MPU_IRQ_38_39," hexmask.long.word 0x140 16.--24. 1. "MPU_IRQ_39," newline hexmask.long.word 0x140 0.--8. 1. "MPU_IRQ_38," line.long 0x144 "CTRL_CORE_MPU_IRQ_40_41," hexmask.long.word 0x144 16.--24. 1. "MPU_IRQ_41," newline hexmask.long.word 0x144 0.--8. 1. "MPU_IRQ_40," line.long 0x148 "CTRL_CORE_MPU_IRQ_42_43," hexmask.long.word 0x148 16.--24. 1. "MPU_IRQ_43," newline hexmask.long.word 0x148 0.--8. 1. "MPU_IRQ_42," line.long 0x14C "CTRL_CORE_MPU_IRQ_44_45," hexmask.long.word 0x14C 16.--24. 1. "MPU_IRQ_45," newline hexmask.long.word 0x14C 0.--8. 1. "MPU_IRQ_44," line.long 0x150 "CTRL_CORE_MPU_IRQ_46_47," hexmask.long.word 0x150 16.--24. 1. "MPU_IRQ_47," newline hexmask.long.word 0x150 0.--8. 1. "MPU_IRQ_46," line.long 0x154 "CTRL_CORE_MPU_IRQ_48_49," hexmask.long.word 0x154 16.--24. 1. "MPU_IRQ_49," newline hexmask.long.word 0x154 0.--8. 1. "MPU_IRQ_48," line.long 0x158 "CTRL_CORE_MPU_IRQ_50_51," hexmask.long.word 0x158 16.--24. 1. "MPU_IRQ_51," newline hexmask.long.word 0x158 0.--8. 1. "MPU_IRQ_50," line.long 0x15C "CTRL_CORE_MPU_IRQ_52_53," hexmask.long.word 0x15C 16.--24. 1. "MPU_IRQ_53," newline hexmask.long.word 0x15C 0.--8. 1. "MPU_IRQ_52," line.long 0x160 "CTRL_CORE_MPU_IRQ_54_55," hexmask.long.word 0x160 16.--24. 1. "MPU_IRQ_55," newline hexmask.long.word 0x160 0.--8. 1. "MPU_IRQ_54," line.long 0x164 "CTRL_CORE_MPU_IRQ_56_57," hexmask.long.word 0x164 16.--24. 1. "MPU_IRQ_57," newline hexmask.long.word 0x164 0.--8. 1. "MPU_IRQ_56," line.long 0x168 "CTRL_CORE_MPU_IRQ_58_59," hexmask.long.word 0x168 16.--24. 1. "MPU_IRQ_59," newline hexmask.long.word 0x168 0.--8. 1. "MPU_IRQ_58," line.long 0x16C "CTRL_CORE_MPU_IRQ_60_61," hexmask.long.word 0x16C 16.--24. 1. "MPU_IRQ_61," newline hexmask.long.word 0x16C 0.--8. 1. "MPU_IRQ_60," line.long 0x170 "CTRL_CORE_MPU_IRQ_62_63," hexmask.long.word 0x170 16.--24. 1. "MPU_IRQ_63," newline hexmask.long.word 0x170 0.--8. 1. "MPU_IRQ_62," line.long 0x174 "CTRL_CORE_MPU_IRQ_64_65," hexmask.long.word 0x174 16.--24. 1. "MPU_IRQ_65," newline hexmask.long.word 0x174 0.--8. 1. "MPU_IRQ_64," line.long 0x178 "CTRL_CORE_MPU_IRQ_66_67," hexmask.long.word 0x178 16.--24. 1. "MPU_IRQ_67," newline hexmask.long.word 0x178 0.--8. 1. "MPU_IRQ_66," line.long 0x17C "CTRL_CORE_MPU_IRQ_68_69," hexmask.long.word 0x17C 16.--24. 1. "MPU_IRQ_69," newline hexmask.long.word 0x17C 0.--8. 1. "MPU_IRQ_68," line.long 0x180 "CTRL_CORE_MPU_IRQ_70_71," hexmask.long.word 0x180 16.--24. 1. "MPU_IRQ_71," newline hexmask.long.word 0x180 0.--8. 1. "MPU_IRQ_70," line.long 0x184 "CTRL_CORE_MPU_IRQ_72_73," hexmask.long.word 0x184 16.--24. 1. "MPU_IRQ_73," newline hexmask.long.word 0x184 0.--8. 1. "MPU_IRQ_72," line.long 0x188 "CTRL_CORE_MPU_IRQ_74_75," hexmask.long.word 0x188 16.--24. 1. "MPU_IRQ_75," newline hexmask.long.word 0x188 0.--8. 1. "MPU_IRQ_74," line.long 0x18C "CTRL_CORE_MPU_IRQ_76_77," hexmask.long.word 0x18C 16.--24. 1. "MPU_IRQ_77," newline hexmask.long.word 0x18C 0.--8. 1. "MPU_IRQ_76," line.long 0x190 "CTRL_CORE_MPU_IRQ_78_79," hexmask.long.word 0x190 16.--24. 1. "MPU_IRQ_79," newline hexmask.long.word 0x190 0.--8. 1. "MPU_IRQ_78," line.long 0x194 "CTRL_CORE_MPU_IRQ_80_81," hexmask.long.word 0x194 16.--24. 1. "MPU_IRQ_81," newline hexmask.long.word 0x194 0.--8. 1. "MPU_IRQ_80," line.long 0x198 "CTRL_CORE_MPU_IRQ_82_83," hexmask.long.word 0x198 16.--24. 1. "MPU_IRQ_83," newline hexmask.long.word 0x198 0.--8. 1. "MPU_IRQ_82," line.long 0x19C "CTRL_CORE_MPU_IRQ_84_85," hexmask.long.word 0x19C 16.--24. 1. "MPU_IRQ_85," newline hexmask.long.word 0x19C 0.--8. 1. "MPU_IRQ_84," line.long 0x1A0 "CTRL_CORE_MPU_IRQ_86_87," hexmask.long.word 0x1A0 16.--24. 1. "MPU_IRQ_87," newline hexmask.long.word 0x1A0 0.--8. 1. "MPU_IRQ_86," line.long 0x1A4 "CTRL_CORE_MPU_IRQ_88_89," hexmask.long.word 0x1A4 16.--24. 1. "MPU_IRQ_89," newline hexmask.long.word 0x1A4 0.--8. 1. "MPU_IRQ_88," line.long 0x1A8 "CTRL_CORE_MPU_IRQ_90_91," hexmask.long.word 0x1A8 16.--24. 1. "MPU_IRQ_91," newline hexmask.long.word 0x1A8 0.--8. 1. "MPU_IRQ_90," line.long 0x1AC "CTRL_CORE_MPU_IRQ_92_93," hexmask.long.word 0x1AC 16.--24. 1. "MPU_IRQ_93," newline hexmask.long.word 0x1AC 0.--8. 1. "MPU_IRQ_92," line.long 0x1B0 "CTRL_CORE_MPU_IRQ_94_95," hexmask.long.word 0x1B0 16.--24. 1. "MPU_IRQ_95," newline hexmask.long.word 0x1B0 0.--8. 1. "MPU_IRQ_94," line.long 0x1B4 "CTRL_CORE_MPU_IRQ_96_97," hexmask.long.word 0x1B4 16.--24. 1. "MPU_IRQ_97," newline hexmask.long.word 0x1B4 0.--8. 1. "MPU_IRQ_96," line.long 0x1B8 "CTRL_CORE_MPU_IRQ_98_99," hexmask.long.word 0x1B8 16.--24. 1. "MPU_IRQ_99," newline hexmask.long.word 0x1B8 0.--8. 1. "MPU_IRQ_98," line.long 0x1BC "CTRL_CORE_MPU_IRQ_100_101," hexmask.long.word 0x1BC 16.--24. 1. "MPU_IRQ_101," newline hexmask.long.word 0x1BC 0.--8. 1. "MPU_IRQ_100," line.long 0x1C0 "CTRL_CORE_MPU_IRQ_102_103," hexmask.long.word 0x1C0 16.--24. 1. "MPU_IRQ_103," newline hexmask.long.word 0x1C0 0.--8. 1. "MPU_IRQ_102," line.long 0x1C4 "CTRL_CORE_MPU_IRQ_104_105," hexmask.long.word 0x1C4 16.--24. 1. "MPU_IRQ_105," newline hexmask.long.word 0x1C4 0.--8. 1. "MPU_IRQ_104," line.long 0x1C8 "CTRL_CORE_MPU_IRQ_106_107," hexmask.long.word 0x1C8 16.--24. 1. "MPU_IRQ_107," newline hexmask.long.word 0x1C8 0.--8. 1. "MPU_IRQ_106," line.long 0x1CC "CTRL_CORE_MPU_IRQ_108_109," hexmask.long.word 0x1CC 16.--24. 1. "MPU_IRQ_109," newline hexmask.long.word 0x1CC 0.--8. 1. "MPU_IRQ_108," line.long 0x1D0 "CTRL_CORE_MPU_IRQ_110_111," hexmask.long.word 0x1D0 16.--24. 1. "MPU_IRQ_111," newline hexmask.long.word 0x1D0 0.--8. 1. "MPU_IRQ_110," line.long 0x1D4 "CTRL_CORE_MPU_IRQ_112_113," hexmask.long.word 0x1D4 16.--24. 1. "MPU_IRQ_113," newline hexmask.long.word 0x1D4 0.--8. 1. "MPU_IRQ_112," line.long 0x1D8 "CTRL_CORE_MPU_IRQ_114_115," hexmask.long.word 0x1D8 16.--24. 1. "MPU_IRQ_115," newline hexmask.long.word 0x1D8 0.--8. 1. "MPU_IRQ_114," line.long 0x1DC "CTRL_CORE_MPU_IRQ_116_117," hexmask.long.word 0x1DC 16.--24. 1. "MPU_IRQ_117," newline hexmask.long.word 0x1DC 0.--8. 1. "MPU_IRQ_116," line.long 0x1E0 "CTRL_CORE_MPU_IRQ_118_119," hexmask.long.word 0x1E0 16.--24. 1. "MPU_IRQ_119," newline hexmask.long.word 0x1E0 0.--8. 1. "MPU_IRQ_118," line.long 0x1E4 "CTRL_CORE_MPU_IRQ_120_121," hexmask.long.word 0x1E4 16.--24. 1. "MPU_IRQ_121," newline hexmask.long.word 0x1E4 0.--8. 1. "MPU_IRQ_120," line.long 0x1E8 "CTRL_CORE_MPU_IRQ_122_123," hexmask.long.word 0x1E8 16.--24. 1. "MPU_IRQ_123," newline hexmask.long.word 0x1E8 0.--8. 1. "MPU_IRQ_122," line.long 0x1EC "CTRL_CORE_MPU_IRQ_124_125," hexmask.long.word 0x1EC 16.--24. 1. "MPU_IRQ_125," newline hexmask.long.word 0x1EC 0.--8. 1. "MPU_IRQ_124," line.long 0x1F0 "CTRL_CORE_MPU_IRQ_126_127," hexmask.long.word 0x1F0 16.--24. 1. "MPU_IRQ_127," newline hexmask.long.word 0x1F0 0.--8. 1. "MPU_IRQ_126," line.long 0x1F4 "CTRL_CORE_MPU_IRQ_128_129," hexmask.long.word 0x1F4 16.--24. 1. "MPU_IRQ_129," newline hexmask.long.word 0x1F4 0.--8. 1. "MPU_IRQ_128," line.long 0x1F8 "CTRL_CORE_MPU_IRQ_130_133," hexmask.long.word 0x1F8 16.--24. 1. "MPU_IRQ_133," newline hexmask.long.word 0x1F8 0.--8. 1. "MPU_IRQ_130," line.long 0x1FC "CTRL_CORE_MPU_IRQ_134_135," hexmask.long.word 0x1FC 16.--24. 1. "MPU_IRQ_135," newline hexmask.long.word 0x1FC 0.--8. 1. "MPU_IRQ_134," line.long 0x200 "CTRL_CORE_MPU_IRQ_136_137," hexmask.long.word 0x200 16.--24. 1. "MPU_IRQ_137," newline hexmask.long.word 0x200 0.--8. 1. "MPU_IRQ_136," line.long 0x204 "CTRL_CORE_MPU_IRQ_138_139," hexmask.long.word 0x204 16.--24. 1. "MPU_IRQ_139," newline hexmask.long.word 0x204 0.--8. 1. "MPU_IRQ_138," line.long 0x208 "CTRL_CORE_MPU_IRQ_140_141," hexmask.long.word 0x208 16.--24. 1. "MPU_IRQ_141," newline hexmask.long.word 0x208 0.--8. 1. "MPU_IRQ_140," line.long 0x20C "CTRL_CORE_MPU_IRQ_142_143," hexmask.long.word 0x20C 16.--24. 1. "MPU_IRQ_143," newline hexmask.long.word 0x20C 0.--8. 1. "MPU_IRQ_142," line.long 0x210 "CTRL_CORE_MPU_IRQ_144_145," hexmask.long.word 0x210 16.--24. 1. "MPU_IRQ_145," newline hexmask.long.word 0x210 0.--8. 1. "MPU_IRQ_144," line.long 0x214 "CTRL_CORE_MPU_IRQ_146_147," hexmask.long.word 0x214 16.--24. 1. "MPU_IRQ_147," newline hexmask.long.word 0x214 0.--8. 1. "MPU_IRQ_146," line.long 0x218 "CTRL_CORE_MPU_IRQ_148_149," hexmask.long.word 0x218 16.--24. 1. "MPU_IRQ_149," newline hexmask.long.word 0x218 0.--8. 1. "MPU_IRQ_148," line.long 0x21C "CTRL_CORE_MPU_IRQ_150_151," hexmask.long.word 0x21C 16.--24. 1. "MPU_IRQ_151," newline hexmask.long.word 0x21C 0.--8. 1. "MPU_IRQ_150," line.long 0x220 "CTRL_CORE_MPU_IRQ_152_153," hexmask.long.word 0x220 16.--24. 1. "MPU_IRQ_153," newline hexmask.long.word 0x220 0.--8. 1. "MPU_IRQ_152," line.long 0x224 "CTRL_CORE_MPU_IRQ_154_155," hexmask.long.word 0x224 16.--24. 1. "MPU_IRQ_155," newline hexmask.long.word 0x224 0.--8. 1. "MPU_IRQ_154," line.long 0x228 "CTRL_CORE_MPU_IRQ_156_157," hexmask.long.word 0x228 16.--24. 1. "MPU_IRQ_157," newline hexmask.long.word 0x228 0.--8. 1. "MPU_IRQ_156," line.long 0x22C "CTRL_CORE_MPU_IRQ_158_159," hexmask.long.word 0x22C 16.--24. 1. "MPU_IRQ_159," newline hexmask.long.word 0x22C 0.--8. 1. "MPU_IRQ_158," line.long 0x230 "CTRL_CORE_DMA_SYSTEM_DREQ_0_1," hexmask.long.byte 0x230 16.--23. 1. "DMA_SYSTEM_DREQ_1_IRQ_1," newline hexmask.long.byte 0x230 0.--7. 1. "DMA_SYSTEM_DREQ_0_IRQ_0," line.long 0x234 "CTRL_CORE_DMA_SYSTEM_DREQ_2_3," hexmask.long.byte 0x234 16.--23. 1. "DMA_SYSTEM_DREQ_3_IRQ_3," newline hexmask.long.byte 0x234 0.--7. 1. "DMA_SYSTEM_DREQ_2_IRQ_2," line.long 0x238 "CTRL_CORE_DMA_SYSTEM_DREQ_4_5," hexmask.long.byte 0x238 16.--23. 1. "DMA_SYSTEM_DREQ_5_IRQ_5," newline hexmask.long.byte 0x238 0.--7. 1. "DMA_SYSTEM_DREQ_4_IRQ_4," line.long 0x23C "CTRL_CORE_DMA_SYSTEM_DREQ_6_7," hexmask.long.byte 0x23C 16.--23. 1. "DMA_SYSTEM_DREQ_7_IRQ_7," newline hexmask.long.byte 0x23C 0.--7. 1. "DMA_SYSTEM_DREQ_6_IRQ_6," line.long 0x240 "CTRL_CORE_DMA_SYSTEM_DREQ_8_9," hexmask.long.byte 0x240 16.--23. 1. "DMA_SYSTEM_DREQ_9_IRQ_9," newline hexmask.long.byte 0x240 0.--7. 1. "DMA_SYSTEM_DREQ_8_IRQ_8," line.long 0x244 "CTRL_CORE_DMA_SYSTEM_DREQ_10_11," hexmask.long.byte 0x244 16.--23. 1. "DMA_SYSTEM_DREQ_11_IRQ_11," newline hexmask.long.byte 0x244 0.--7. 1. "DMA_SYSTEM_DREQ_10_IRQ_10," line.long 0x248 "CTRL_CORE_DMA_SYSTEM_DREQ_12_13," hexmask.long.byte 0x248 16.--23. 1. "DMA_SYSTEM_DREQ_13_IRQ_13," newline hexmask.long.byte 0x248 0.--7. 1. "DMA_SYSTEM_DREQ_12_IRQ_12," line.long 0x24C "CTRL_CORE_DMA_SYSTEM_DREQ_14_15," hexmask.long.byte 0x24C 16.--23. 1. "DMA_SYSTEM_DREQ_15_IRQ_15," newline hexmask.long.byte 0x24C 0.--7. 1. "DMA_SYSTEM_DREQ_14_IRQ_14," line.long 0x250 "CTRL_CORE_DMA_SYSTEM_DREQ_16_17," hexmask.long.byte 0x250 16.--23. 1. "DMA_SYSTEM_DREQ_17_IRQ_17," newline hexmask.long.byte 0x250 0.--7. 1. "DMA_SYSTEM_DREQ_16_IRQ_16," line.long 0x254 "CTRL_CORE_DMA_SYSTEM_DREQ_18_19," hexmask.long.byte 0x254 16.--23. 1. "DMA_SYSTEM_DREQ_19_IRQ_19," newline hexmask.long.byte 0x254 0.--7. 1. "DMA_SYSTEM_DREQ_18_IRQ_18," line.long 0x258 "CTRL_CORE_DMA_SYSTEM_DREQ_20_21," hexmask.long.byte 0x258 16.--23. 1. "DMA_SYSTEM_DREQ_21_IRQ_21," newline hexmask.long.byte 0x258 0.--7. 1. "DMA_SYSTEM_DREQ_20_IRQ_20," line.long 0x25C "CTRL_CORE_DMA_SYSTEM_DREQ_22_23," hexmask.long.byte 0x25C 16.--23. 1. "DMA_SYSTEM_DREQ_23_IRQ_23," newline hexmask.long.byte 0x25C 0.--7. 1. "DMA_SYSTEM_DREQ_22_IRQ_22," line.long 0x260 "CTRL_CORE_DMA_SYSTEM_DREQ_24_25," hexmask.long.byte 0x260 16.--23. 1. "DMA_SYSTEM_DREQ_25_IRQ_25," newline hexmask.long.byte 0x260 0.--7. 1. "DMA_SYSTEM_DREQ_24_IRQ_24," line.long 0x264 "CTRL_CORE_DMA_SYSTEM_DREQ_26_27," hexmask.long.byte 0x264 16.--23. 1. "DMA_SYSTEM_DREQ_27_IRQ_27," newline hexmask.long.byte 0x264 0.--7. 1. "DMA_SYSTEM_DREQ_26_IRQ_26," line.long 0x268 "CTRL_CORE_DMA_SYSTEM_DREQ_28_29," hexmask.long.byte 0x268 16.--23. 1. "DMA_SYSTEM_DREQ_29_IRQ_29," newline hexmask.long.byte 0x268 0.--7. 1. "DMA_SYSTEM_DREQ_28_IRQ_28," line.long 0x26C "CTRL_CORE_DMA_SYSTEM_DREQ_30_31," hexmask.long.byte 0x26C 16.--23. 1. "DMA_SYSTEM_DREQ_31_IRQ_31," newline hexmask.long.byte 0x26C 0.--7. 1. "DMA_SYSTEM_DREQ_30_IRQ_30," line.long 0x270 "CTRL_CORE_DMA_SYSTEM_DREQ_32_33," hexmask.long.byte 0x270 16.--23. 1. "DMA_SYSTEM_DREQ_33_IRQ_33," newline hexmask.long.byte 0x270 0.--7. 1. "DMA_SYSTEM_DREQ_32_IRQ_32," line.long 0x274 "CTRL_CORE_DMA_SYSTEM_DREQ_34_35," hexmask.long.byte 0x274 16.--23. 1. "DMA_SYSTEM_DREQ_35_IRQ_35," newline hexmask.long.byte 0x274 0.--7. 1. "DMA_SYSTEM_DREQ_34_IRQ_34," line.long 0x278 "CTRL_CORE_DMA_SYSTEM_DREQ_36_37," hexmask.long.byte 0x278 16.--23. 1. "DMA_SYSTEM_DREQ_37_IRQ_37," newline hexmask.long.byte 0x278 0.--7. 1. "DMA_SYSTEM_DREQ_36_IRQ_36," line.long 0x27C "CTRL_CORE_DMA_SYSTEM_DREQ_38_39," hexmask.long.byte 0x27C 16.--23. 1. "DMA_SYSTEM_DREQ_39_IRQ_39," newline hexmask.long.byte 0x27C 0.--7. 1. "DMA_SYSTEM_DREQ_38_IRQ_38," line.long 0x280 "CTRL_CORE_DMA_SYSTEM_DREQ_40_41," hexmask.long.byte 0x280 16.--23. 1. "DMA_SYSTEM_DREQ_41_IRQ_41," newline hexmask.long.byte 0x280 0.--7. 1. "DMA_SYSTEM_DREQ_40_IRQ_40," line.long 0x284 "CTRL_CORE_DMA_SYSTEM_DREQ_42_43," hexmask.long.byte 0x284 16.--23. 1. "DMA_SYSTEM_DREQ_43_IRQ_43," newline hexmask.long.byte 0x284 0.--7. 1. "DMA_SYSTEM_DREQ_42_IRQ_42," line.long 0x288 "CTRL_CORE_DMA_SYSTEM_DREQ_44_45," hexmask.long.byte 0x288 16.--23. 1. "DMA_SYSTEM_DREQ_45_IRQ_45," newline hexmask.long.byte 0x288 0.--7. 1. "DMA_SYSTEM_DREQ_44_IRQ_44," line.long 0x28C "CTRL_CORE_DMA_SYSTEM_DREQ_46_47," hexmask.long.byte 0x28C 16.--23. 1. "DMA_SYSTEM_DREQ_47_IRQ_47," newline hexmask.long.byte 0x28C 0.--7. 1. "DMA_SYSTEM_DREQ_46_IRQ_46," line.long 0x290 "CTRL_CORE_DMA_SYSTEM_DREQ_48_49," hexmask.long.byte 0x290 16.--23. 1. "DMA_SYSTEM_DREQ_49_IRQ_49," newline hexmask.long.byte 0x290 0.--7. 1. "DMA_SYSTEM_DREQ_48_IRQ_48," line.long 0x294 "CTRL_CORE_DMA_SYSTEM_DREQ_50_51," hexmask.long.byte 0x294 16.--23. 1. "DMA_SYSTEM_DREQ_51_IRQ_51," newline hexmask.long.byte 0x294 0.--7. 1. "DMA_SYSTEM_DREQ_50_IRQ_50," line.long 0x298 "CTRL_CORE_DMA_SYSTEM_DREQ_52_53," hexmask.long.byte 0x298 16.--23. 1. "DMA_SYSTEM_DREQ_53_IRQ_53," newline hexmask.long.byte 0x298 0.--7. 1. "DMA_SYSTEM_DREQ_52_IRQ_52," line.long 0x29C "CTRL_CORE_DMA_SYSTEM_DREQ_54_55," hexmask.long.byte 0x29C 16.--23. 1. "DMA_SYSTEM_DREQ_55_IRQ_55," newline hexmask.long.byte 0x29C 0.--7. 1. "DMA_SYSTEM_DREQ_54_IRQ_54," line.long 0x2A0 "CTRL_CORE_DMA_SYSTEM_DREQ_56_57," hexmask.long.byte 0x2A0 16.--23. 1. "DMA_SYSTEM_DREQ_57_IRQ_57," newline hexmask.long.byte 0x2A0 0.--7. 1. "DMA_SYSTEM_DREQ_56_IRQ_56," line.long 0x2A4 "CTRL_CORE_DMA_SYSTEM_DREQ_58_59," hexmask.long.byte 0x2A4 16.--23. 1. "DMA_SYSTEM_DREQ_59_IRQ_59," newline hexmask.long.byte 0x2A4 0.--7. 1. "DMA_SYSTEM_DREQ_58_IRQ_58," line.long 0x2A8 "CTRL_CORE_DMA_SYSTEM_DREQ_60_61," hexmask.long.byte 0x2A8 16.--23. 1. "DMA_SYSTEM_DREQ_61_IRQ_61," newline hexmask.long.byte 0x2A8 0.--7. 1. "DMA_SYSTEM_DREQ_60_IRQ_60," line.long 0x2AC "CTRL_CORE_DMA_SYSTEM_DREQ_62_63," hexmask.long.byte 0x2AC 16.--23. 1. "DMA_SYSTEM_DREQ_63_IRQ_63," newline hexmask.long.byte 0x2AC 0.--7. 1. "DMA_SYSTEM_DREQ_62_IRQ_62," line.long 0x2B0 "CTRL_CORE_DMA_SYSTEM_DREQ_64_65," hexmask.long.byte 0x2B0 16.--23. 1. "DMA_SYSTEM_DREQ_65_IRQ_65," newline hexmask.long.byte 0x2B0 0.--7. 1. "DMA_SYSTEM_DREQ_64_IRQ_64," line.long 0x2B4 "CTRL_CORE_DMA_SYSTEM_DREQ_66_67," hexmask.long.byte 0x2B4 16.--23. 1. "DMA_SYSTEM_DREQ_67_IRQ_67," newline hexmask.long.byte 0x2B4 0.--7. 1. "DMA_SYSTEM_DREQ_66_IRQ_66," line.long 0x2B8 "CTRL_CORE_DMA_SYSTEM_DREQ_68_69," hexmask.long.byte 0x2B8 16.--23. 1. "DMA_SYSTEM_DREQ_69_IRQ_69," newline hexmask.long.byte 0x2B8 0.--7. 1. "DMA_SYSTEM_DREQ_68_IRQ_68," line.long 0x2BC "CTRL_CORE_DMA_SYSTEM_DREQ_70_71," hexmask.long.byte 0x2BC 16.--23. 1. "DMA_SYSTEM_DREQ_71_IRQ_71," newline hexmask.long.byte 0x2BC 0.--7. 1. "DMA_SYSTEM_DREQ_70_IRQ_70," line.long 0x2C0 "CTRL_CORE_DMA_SYSTEM_DREQ_72_73," hexmask.long.byte 0x2C0 16.--23. 1. "DMA_SYSTEM_DREQ_73_IRQ_73," newline hexmask.long.byte 0x2C0 0.--7. 1. "DMA_SYSTEM_DREQ_72_IRQ_72," line.long 0x2C4 "CTRL_CORE_DMA_SYSTEM_DREQ_74_75," hexmask.long.byte 0x2C4 16.--23. 1. "DMA_SYSTEM_DREQ_75_IRQ_75," newline hexmask.long.byte 0x2C4 0.--7. 1. "DMA_SYSTEM_DREQ_74_IRQ_74," line.long 0x2C8 "CTRL_CORE_DMA_SYSTEM_DREQ_76_77," hexmask.long.byte 0x2C8 16.--23. 1. "DMA_SYSTEM_DREQ_77_IRQ_77," newline hexmask.long.byte 0x2C8 0.--7. 1. "DMA_SYSTEM_DREQ_76_IRQ_76," line.long 0x2CC "CTRL_CORE_DMA_SYSTEM_DREQ_78_79," hexmask.long.byte 0x2CC 16.--23. 1. "DMA_SYSTEM_DREQ_79_IRQ_79," newline hexmask.long.byte 0x2CC 0.--7. 1. "DMA_SYSTEM_DREQ_78_IRQ_78," line.long 0x2D0 "CTRL_CORE_DMA_SYSTEM_DREQ_80_81," hexmask.long.byte 0x2D0 16.--23. 1. "DMA_SYSTEM_DREQ_81_IRQ_81," newline hexmask.long.byte 0x2D0 0.--7. 1. "DMA_SYSTEM_DREQ_80_IRQ_80," line.long 0x2D4 "CTRL_CORE_DMA_SYSTEM_DREQ_82_83," hexmask.long.byte 0x2D4 16.--23. 1. "DMA_SYSTEM_DREQ_83_IRQ_83," newline hexmask.long.byte 0x2D4 0.--7. 1. "DMA_SYSTEM_DREQ_82_IRQ_82," line.long 0x2D8 "CTRL_CORE_DMA_SYSTEM_DREQ_84_85," hexmask.long.byte 0x2D8 16.--23. 1. "DMA_SYSTEM_DREQ_85_IRQ_85," newline hexmask.long.byte 0x2D8 0.--7. 1. "DMA_SYSTEM_DREQ_84_IRQ_84," line.long 0x2DC "CTRL_CORE_DMA_SYSTEM_DREQ_86_87," hexmask.long.byte 0x2DC 16.--23. 1. "DMA_SYSTEM_DREQ_87_IRQ_87," newline hexmask.long.byte 0x2DC 0.--7. 1. "DMA_SYSTEM_DREQ_86_IRQ_86," line.long 0x2E0 "CTRL_CORE_DMA_SYSTEM_DREQ_88_89," hexmask.long.byte 0x2E0 16.--23. 1. "DMA_SYSTEM_DREQ_89_IRQ_89," newline hexmask.long.byte 0x2E0 0.--7. 1. "DMA_SYSTEM_DREQ_88_IRQ_88," line.long 0x2E4 "CTRL_CORE_DMA_SYSTEM_DREQ_90_91," hexmask.long.byte 0x2E4 16.--23. 1. "DMA_SYSTEM_DREQ_91_IRQ_91," newline hexmask.long.byte 0x2E4 0.--7. 1. "DMA_SYSTEM_DREQ_90_IRQ_90," line.long 0x2E8 "CTRL_CORE_DMA_SYSTEM_DREQ_92_93," hexmask.long.byte 0x2E8 16.--23. 1. "DMA_SYSTEM_DREQ_93_IRQ_93," newline hexmask.long.byte 0x2E8 0.--7. 1. "DMA_SYSTEM_DREQ_92_IRQ_92," line.long 0x2EC "CTRL_CORE_DMA_SYSTEM_DREQ_94_95," hexmask.long.byte 0x2EC 16.--23. 1. "DMA_SYSTEM_DREQ_95_IRQ_95," newline hexmask.long.byte 0x2EC 0.--7. 1. "DMA_SYSTEM_DREQ_94_IRQ_94," line.long 0x2F0 "CTRL_CORE_DMA_SYSTEM_DREQ_96_97," hexmask.long.byte 0x2F0 16.--23. 1. "DMA_SYSTEM_DREQ_97_IRQ_97," newline hexmask.long.byte 0x2F0 0.--7. 1. "DMA_SYSTEM_DREQ_96_IRQ_96," line.long 0x2F4 "CTRL_CORE_DMA_SYSTEM_DREQ_98_99," hexmask.long.byte 0x2F4 16.--23. 1. "DMA_SYSTEM_DREQ_99_IRQ_99," newline hexmask.long.byte 0x2F4 0.--7. 1. "DMA_SYSTEM_DREQ_98_IRQ_98," line.long 0x2F8 "CTRL_CORE_DMA_SYSTEM_DREQ_100_101," hexmask.long.byte 0x2F8 16.--23. 1. "DMA_SYSTEM_DREQ_101_IRQ_101," newline hexmask.long.byte 0x2F8 0.--7. 1. "DMA_SYSTEM_DREQ_100_IRQ_100," line.long 0x2FC "CTRL_CORE_DMA_SYSTEM_DREQ_102_103," hexmask.long.byte 0x2FC 16.--23. 1. "DMA_SYSTEM_DREQ_103_IRQ_103," newline hexmask.long.byte 0x2FC 0.--7. 1. "DMA_SYSTEM_DREQ_102_IRQ_102," line.long 0x300 "CTRL_CORE_DMA_SYSTEM_DREQ_104_105," hexmask.long.byte 0x300 16.--23. 1. "DMA_SYSTEM_DREQ_105_IRQ_105," newline hexmask.long.byte 0x300 0.--7. 1. "DMA_SYSTEM_DREQ_104_IRQ_104," line.long 0x304 "CTRL_CORE_DMA_SYSTEM_DREQ_106_107," hexmask.long.byte 0x304 16.--23. 1. "DMA_SYSTEM_DREQ_107_IRQ_107," newline hexmask.long.byte 0x304 0.--7. 1. "DMA_SYSTEM_DREQ_106_IRQ_106," line.long 0x308 "CTRL_CORE_DMA_SYSTEM_DREQ_108_109," hexmask.long.byte 0x308 16.--23. 1. "DMA_SYSTEM_DREQ_109_IRQ_109," newline hexmask.long.byte 0x308 0.--7. 1. "DMA_SYSTEM_DREQ_108_IRQ_108," line.long 0x30C "CTRL_CORE_DMA_SYSTEM_DREQ_110_111," hexmask.long.byte 0x30C 16.--23. 1. "DMA_SYSTEM_DREQ_111_IRQ_111," newline hexmask.long.byte 0x30C 0.--7. 1. "DMA_SYSTEM_DREQ_110_IRQ_110," line.long 0x310 "CTRL_CORE_DMA_SYSTEM_DREQ_112_113," hexmask.long.byte 0x310 16.--23. 1. "DMA_SYSTEM_DREQ_113_IRQ_113," newline hexmask.long.byte 0x310 0.--7. 1. "DMA_SYSTEM_DREQ_112_IRQ_112," line.long 0x314 "CTRL_CORE_DMA_SYSTEM_DREQ_114_115," hexmask.long.byte 0x314 16.--23. 1. "DMA_SYSTEM_DREQ_115_IRQ_115," newline hexmask.long.byte 0x314 0.--7. 1. "DMA_SYSTEM_DREQ_114_IRQ_114," line.long 0x318 "CTRL_CORE_DMA_SYSTEM_DREQ_116_117," hexmask.long.byte 0x318 16.--23. 1. "DMA_SYSTEM_DREQ_117_IRQ_117," newline hexmask.long.byte 0x318 0.--7. 1. "DMA_SYSTEM_DREQ_116_IRQ_116," line.long 0x31C "CTRL_CORE_DMA_SYSTEM_DREQ_118_119," hexmask.long.byte 0x31C 16.--23. 1. "DMA_SYSTEM_DREQ_119_IRQ_119," newline hexmask.long.byte 0x31C 0.--7. 1. "DMA_SYSTEM_DREQ_118_IRQ_118," line.long 0x320 "CTRL_CORE_DMA_SYSTEM_DREQ_120_121," hexmask.long.byte 0x320 16.--23. 1. "DMA_SYSTEM_DREQ_121_IRQ_121," newline hexmask.long.byte 0x320 0.--7. 1. "DMA_SYSTEM_DREQ_120_IRQ_120," line.long 0x324 "CTRL_CORE_DMA_SYSTEM_DREQ_122_123," hexmask.long.byte 0x324 16.--23. 1. "DMA_SYSTEM_DREQ_123_IRQ_123," newline hexmask.long.byte 0x324 0.--7. 1. "DMA_SYSTEM_DREQ_122_IRQ_122," line.long 0x328 "CTRL_CORE_DMA_SYSTEM_DREQ_124_125," hexmask.long.byte 0x328 16.--23. 1. "DMA_SYSTEM_DREQ_125_IRQ_125," newline hexmask.long.byte 0x328 0.--7. 1. "DMA_SYSTEM_DREQ_124_IRQ_124," line.long 0x32C "CTRL_CORE_DMA_SYSTEM_DREQ_126_127," hexmask.long.byte 0x32C 0.--7. 1. "DMA_SYSTEM_DREQ_126_IRQ_126," line.long 0x330 "CTRL_CORE_DMA_EDMA_DREQ_0_1," hexmask.long.byte 0x330 16.--23. 1. "DMA_EDMA_DREQ_1_IRQ_1," newline hexmask.long.byte 0x330 0.--7. 1. "DMA_EDMA_DREQ_0_IRQ_0," line.long 0x334 "CTRL_CORE_DMA_EDMA_DREQ_2_3," hexmask.long.byte 0x334 16.--23. 1. "DMA_EDMA_DREQ_3_IRQ_3," newline hexmask.long.byte 0x334 0.--7. 1. "DMA_EDMA_DREQ_2_IRQ_2," line.long 0x338 "CTRL_CORE_DMA_EDMA_DREQ_4_5," hexmask.long.byte 0x338 16.--23. 1. "DMA_EDMA_DREQ_5_IRQ_5," newline hexmask.long.byte 0x338 0.--7. 1. "DMA_EDMA_DREQ_4_IRQ_4," line.long 0x33C "CTRL_CORE_DMA_EDMA_DREQ_6_7," hexmask.long.byte 0x33C 16.--23. 1. "DMA_EDMA_DREQ_7_IRQ_7," newline hexmask.long.byte 0x33C 0.--7. 1. "DMA_EDMA_DREQ_6_IRQ_6," line.long 0x340 "CTRL_CORE_DMA_EDMA_DREQ_8_9," hexmask.long.byte 0x340 16.--23. 1. "DMA_EDMA_DREQ_9_IRQ_9," newline hexmask.long.byte 0x340 0.--7. 1. "DMA_EDMA_DREQ_8_IRQ_8," line.long 0x344 "CTRL_CORE_DMA_EDMA_DREQ_10_11," hexmask.long.byte 0x344 16.--23. 1. "DMA_EDMA_DREQ_11_IRQ_11," newline hexmask.long.byte 0x344 0.--7. 1. "DMA_EDMA_DREQ_10_IRQ_10," line.long 0x348 "CTRL_CORE_DMA_EDMA_DREQ_12_13," hexmask.long.byte 0x348 16.--23. 1. "DMA_EDMA_DREQ_13_IRQ_13," newline hexmask.long.byte 0x348 0.--7. 1. "DMA_EDMA_DREQ_12_IRQ_12," line.long 0x34C "CTRL_CORE_DMA_EDMA_DREQ_14_15," hexmask.long.byte 0x34C 16.--23. 1. "DMA_EDMA_DREQ_15_IRQ_15," newline hexmask.long.byte 0x34C 0.--7. 1. "DMA_EDMA_DREQ_14_IRQ_14," line.long 0x350 "CTRL_CORE_DMA_EDMA_DREQ_16_17," hexmask.long.byte 0x350 16.--23. 1. "DMA_EDMA_DREQ_17_IRQ_17," newline hexmask.long.byte 0x350 0.--7. 1. "DMA_EDMA_DREQ_16_IRQ_16," line.long 0x354 "CTRL_CORE_DMA_EDMA_DREQ_18_19," hexmask.long.byte 0x354 16.--23. 1. "DMA_EDMA_DREQ_19_IRQ_19," newline hexmask.long.byte 0x354 0.--7. 1. "DMA_EDMA_DREQ_18_IRQ_18," line.long 0x358 "CTRL_CORE_DMA_EDMA_DREQ_20_21," hexmask.long.byte 0x358 16.--23. 1. "DMA_EDMA_DREQ_21_IRQ_21," newline hexmask.long.byte 0x358 0.--7. 1. "DMA_EDMA_DREQ_20_IRQ_20," line.long 0x35C "CTRL_CORE_DMA_EDMA_DREQ_22_23," hexmask.long.byte 0x35C 16.--23. 1. "DMA_EDMA_DREQ_23_IRQ_23," newline hexmask.long.byte 0x35C 0.--7. 1. "DMA_EDMA_DREQ_22_IRQ_22," line.long 0x360 "CTRL_CORE_DMA_EDMA_DREQ_24_25," hexmask.long.byte 0x360 16.--23. 1. "DMA_EDMA_DREQ_25_IRQ_25," newline hexmask.long.byte 0x360 0.--7. 1. "DMA_EDMA_DREQ_24_IRQ_24," line.long 0x364 "CTRL_CORE_DMA_EDMA_DREQ_26_27," hexmask.long.byte 0x364 16.--23. 1. "DMA_EDMA_DREQ_27_IRQ_27," newline hexmask.long.byte 0x364 0.--7. 1. "DMA_EDMA_DREQ_26_IRQ_26," line.long 0x368 "CTRL_CORE_DMA_EDMA_DREQ_28_29," hexmask.long.byte 0x368 16.--23. 1. "DMA_EDMA_DREQ_29_IRQ_29," newline hexmask.long.byte 0x368 0.--7. 1. "DMA_EDMA_DREQ_28_IRQ_28," line.long 0x36C "CTRL_CORE_DMA_EDMA_DREQ_30_31," hexmask.long.byte 0x36C 16.--23. 1. "DMA_EDMA_DREQ_31_IRQ_31," newline hexmask.long.byte 0x36C 0.--7. 1. "DMA_EDMA_DREQ_30_IRQ_30," line.long 0x370 "CTRL_CORE_DMA_EDMA_DREQ_32_33," hexmask.long.byte 0x370 16.--23. 1. "DMA_EDMA_DREQ_33_IRQ_33," newline hexmask.long.byte 0x370 0.--7. 1. "DMA_EDMA_DREQ_32_IRQ_32," line.long 0x374 "CTRL_CORE_DMA_EDMA_DREQ_34_35," hexmask.long.byte 0x374 16.--23. 1. "DMA_EDMA_DREQ_35_IRQ_35," newline hexmask.long.byte 0x374 0.--7. 1. "DMA_EDMA_DREQ_34_IRQ_34," line.long 0x378 "CTRL_CORE_DMA_EDMA_DREQ_36_37," hexmask.long.byte 0x378 16.--23. 1. "DMA_EDMA_DREQ_37_IRQ_37," newline hexmask.long.byte 0x378 0.--7. 1. "DMA_EDMA_DREQ_36_IRQ_36," line.long 0x37C "CTRL_CORE_DMA_EDMA_DREQ_38_39," hexmask.long.byte 0x37C 16.--23. 1. "DMA_EDMA_DREQ_39_IRQ_39," newline hexmask.long.byte 0x37C 0.--7. 1. "DMA_EDMA_DREQ_38_IRQ_38," line.long 0x380 "CTRL_CORE_DMA_EDMA_DREQ_40_41," hexmask.long.byte 0x380 16.--23. 1. "DMA_EDMA_DREQ_41_IRQ_41," newline hexmask.long.byte 0x380 0.--7. 1. "DMA_EDMA_DREQ_40_IRQ_40," line.long 0x384 "CTRL_CORE_DMA_EDMA_DREQ_42_43," hexmask.long.byte 0x384 16.--23. 1. "DMA_EDMA_DREQ_43_IRQ_43," newline hexmask.long.byte 0x384 0.--7. 1. "DMA_EDMA_DREQ_42_IRQ_42," line.long 0x388 "CTRL_CORE_DMA_EDMA_DREQ_44_45," hexmask.long.byte 0x388 16.--23. 1. "DMA_EDMA_DREQ_45_IRQ_45," newline hexmask.long.byte 0x388 0.--7. 1. "DMA_EDMA_DREQ_44_IRQ_44," line.long 0x38C "CTRL_CORE_DMA_EDMA_DREQ_46_47," hexmask.long.byte 0x38C 16.--23. 1. "DMA_EDMA_DREQ_47_IRQ_47," newline hexmask.long.byte 0x38C 0.--7. 1. "DMA_EDMA_DREQ_46_IRQ_46," line.long 0x390 "CTRL_CORE_DMA_EDMA_DREQ_48_49," hexmask.long.byte 0x390 16.--23. 1. "DMA_EDMA_DREQ_49_IRQ_49," newline hexmask.long.byte 0x390 0.--7. 1. "DMA_EDMA_DREQ_48_IRQ_48," line.long 0x394 "CTRL_CORE_DMA_EDMA_DREQ_50_51," hexmask.long.byte 0x394 16.--23. 1. "DMA_EDMA_DREQ_51_IRQ_51," newline hexmask.long.byte 0x394 0.--7. 1. "DMA_EDMA_DREQ_50_IRQ_50," line.long 0x398 "CTRL_CORE_DMA_EDMA_DREQ_52_53," hexmask.long.byte 0x398 16.--23. 1. "DMA_EDMA_DREQ_53_IRQ_53," newline hexmask.long.byte 0x398 0.--7. 1. "DMA_EDMA_DREQ_52_IRQ_52," line.long 0x39C "CTRL_CORE_DMA_EDMA_DREQ_54_55," hexmask.long.byte 0x39C 16.--23. 1. "DMA_EDMA_DREQ_55_IRQ_55," newline hexmask.long.byte 0x39C 0.--7. 1. "DMA_EDMA_DREQ_54_IRQ_54," line.long 0x3A0 "CTRL_CORE_DMA_EDMA_DREQ_56_57," hexmask.long.byte 0x3A0 16.--23. 1. "DMA_EDMA_DREQ_57_IRQ_57," newline hexmask.long.byte 0x3A0 0.--7. 1. "DMA_EDMA_DREQ_56_IRQ_56," line.long 0x3A4 "CTRL_CORE_DMA_EDMA_DREQ_58_59," hexmask.long.byte 0x3A4 16.--23. 1. "DMA_EDMA_DREQ_59_IRQ_59," newline hexmask.long.byte 0x3A4 0.--7. 1. "DMA_EDMA_DREQ_58_IRQ_58," line.long 0x3A8 "CTRL_CORE_DMA_EDMA_DREQ_60_61," hexmask.long.byte 0x3A8 16.--23. 1. "DMA_EDMA_DREQ_61_IRQ_61," newline hexmask.long.byte 0x3A8 0.--7. 1. "DMA_EDMA_DREQ_60_IRQ_60," line.long 0x3AC "CTRL_CORE_DMA_EDMA_DREQ_62_63," hexmask.long.byte 0x3AC 16.--23. 1. "DMA_EDMA_DREQ_63_IRQ_63," newline hexmask.long.byte 0x3AC 0.--7. 1. "DMA_EDMA_DREQ_62_IRQ_62," line.long 0x3B0 "CTRL_CORE_DMA_DSP1_DREQ_0_1," hexmask.long.byte 0x3B0 16.--23. 1. "DMA_DSP1_DREQ_1_IRQ_1," newline hexmask.long.byte 0x3B0 0.--7. 1. "DMA_DSP1_DREQ_0_IRQ_0," line.long 0x3B4 "CTRL_CORE_DMA_DSP1_DREQ_2_3," hexmask.long.byte 0x3B4 16.--23. 1. "DMA_DSP1_DREQ_3_IRQ_3," newline hexmask.long.byte 0x3B4 0.--7. 1. "DMA_DSP1_DREQ_2_IRQ_2," line.long 0x3B8 "CTRL_CORE_DMA_DSP1_DREQ_4_5," hexmask.long.byte 0x3B8 16.--23. 1. "DMA_DSP1_DREQ_5_IRQ_5," newline hexmask.long.byte 0x3B8 0.--7. 1. "DMA_DSP1_DREQ_4_IRQ_4," line.long 0x3BC "CTRL_CORE_DMA_DSP1_DREQ_6_7," hexmask.long.byte 0x3BC 16.--23. 1. "DMA_DSP1_DREQ_7_IRQ_7," newline hexmask.long.byte 0x3BC 0.--7. 1. "DMA_DSP1_DREQ_6_IRQ_6," line.long 0x3C0 "CTRL_CORE_DMA_DSP1_DREQ_8_9," hexmask.long.byte 0x3C0 16.--23. 1. "DMA_DSP1_DREQ_9_IRQ_9," newline hexmask.long.byte 0x3C0 0.--7. 1. "DMA_DSP1_DREQ_8_IRQ_8," line.long 0x3C4 "CTRL_CORE_DMA_DSP1_DREQ_10_11," hexmask.long.byte 0x3C4 16.--23. 1. "DMA_DSP1_DREQ_11_IRQ_11," newline hexmask.long.byte 0x3C4 0.--7. 1. "DMA_DSP1_DREQ_10_IRQ_10," line.long 0x3C8 "CTRL_CORE_DMA_DSP1_DREQ_12_13," hexmask.long.byte 0x3C8 16.--23. 1. "DMA_DSP1_DREQ_13_IRQ_13," newline hexmask.long.byte 0x3C8 0.--7. 1. "DMA_DSP1_DREQ_12_IRQ_12," line.long 0x3CC "CTRL_CORE_DMA_DSP1_DREQ_14_15," hexmask.long.byte 0x3CC 16.--23. 1. "DMA_DSP1_DREQ_15_IRQ_15," newline hexmask.long.byte 0x3CC 0.--7. 1. "DMA_DSP1_DREQ_14_IRQ_14," line.long 0x3D0 "CTRL_CORE_DMA_DSP1_DREQ_16_17," hexmask.long.byte 0x3D0 16.--23. 1. "DMA_DSP1_DREQ_17_IRQ_17," newline hexmask.long.byte 0x3D0 0.--7. 1. "DMA_DSP1_DREQ_16_IRQ_16," line.long 0x3D4 "CTRL_CORE_DMA_DSP1_DREQ_18_19," hexmask.long.byte 0x3D4 16.--23. 1. "DMA_DSP1_DREQ_19_IRQ_19," newline hexmask.long.byte 0x3D4 0.--7. 1. "DMA_DSP1_DREQ_18_IRQ_18," line.long 0x3D8 "CTRL_CORE_DMA_DSP2_DREQ_0_1," hexmask.long.byte 0x3D8 16.--23. 1. "DMA_DSP2_DREQ_1_IRQ_1," newline hexmask.long.byte 0x3D8 0.--7. 1. "DMA_DSP2_DREQ_0_IRQ_0," line.long 0x3DC "CTRL_CORE_DMA_DSP2_DREQ_2_3," hexmask.long.byte 0x3DC 16.--23. 1. "DMA_DSP2_DREQ_3_IRQ_3," newline hexmask.long.byte 0x3DC 0.--7. 1. "DMA_DSP2_DREQ_2_IRQ_2," line.long 0x3E0 "CTRL_CORE_DMA_DSP2_DREQ_4_5," hexmask.long.byte 0x3E0 16.--23. 1. "DMA_DSP2_DREQ_5_IRQ_5," newline hexmask.long.byte 0x3E0 0.--7. 1. "DMA_DSP2_DREQ_4_IRQ_4," line.long 0x3E4 "CTRL_CORE_DMA_DSP2_DREQ_6_7," hexmask.long.byte 0x3E4 16.--23. 1. "DMA_DSP2_DREQ_7_IRQ_7," newline hexmask.long.byte 0x3E4 0.--7. 1. "DMA_DSP2_DREQ_6_IRQ_6," line.long 0x3E8 "CTRL_CORE_DMA_DSP2_DREQ_8_9," hexmask.long.byte 0x3E8 16.--23. 1. "DMA_DSP2_DREQ_9_IRQ_9," newline hexmask.long.byte 0x3E8 0.--7. 1. "DMA_DSP2_DREQ_8_IRQ_8," line.long 0x3EC "CTRL_CORE_DMA_DSP2_DREQ_10_11," hexmask.long.byte 0x3EC 16.--23. 1. "DMA_DSP2_DREQ_11_IRQ_11," newline hexmask.long.byte 0x3EC 0.--7. 1. "DMA_DSP2_DREQ_10_IRQ_10," line.long 0x3F0 "CTRL_CORE_DMA_DSP2_DREQ_12_13," hexmask.long.byte 0x3F0 16.--23. 1. "DMA_DSP2_DREQ_13_IRQ_13," newline hexmask.long.byte 0x3F0 0.--7. 1. "DMA_DSP2_DREQ_12_IRQ_12," line.long 0x3F4 "CTRL_CORE_DMA_DSP2_DREQ_14_15," hexmask.long.byte 0x3F4 16.--23. 1. "DMA_DSP2_DREQ_15_IRQ_15," newline hexmask.long.byte 0x3F4 0.--7. 1. "DMA_DSP2_DREQ_14_IRQ_14," line.long 0x3F8 "CTRL_CORE_DMA_DSP2_DREQ_16_17," hexmask.long.byte 0x3F8 16.--23. 1. "DMA_DSP2_DREQ_17_IRQ_17," newline hexmask.long.byte 0x3F8 0.--7. 1. "DMA_DSP2_DREQ_16_IRQ_16," line.long 0x3FC "CTRL_CORE_DMA_DSP2_DREQ_18_19," hexmask.long.byte 0x3FC 16.--23. 1. "DMA_DSP2_DREQ_19_IRQ_19," newline hexmask.long.byte 0x3FC 0.--7. 1. "DMA_DSP2_DREQ_18_IRQ_18," group.long 0xD4C++0x07 line.long 0x00 "CTRL_CORE_OVS_DMARQ_IO_MUX," hexmask.long.byte 0x00 8.--15. 1. "OVS_DMARQ_IO_MUX_2," newline hexmask.long.byte 0x00 0.--7. 1. "OVS_DMARQ_IO_MUX_1," line.long 0x04 "CTRL_CORE_OVS_IRQ_IO_MUX," hexmask.long.word 0x04 9.--17. 1. "OVS_IRQ_IO_MUX_2," newline hexmask.long.word 0x04 0.--8. 1. "OVS_IRQ_IO_MUX_1," group.long 0xE00++0x03 line.long 0x00 "CTRL_CORE_CONTROL_PBIAS,PBIASLITE control" bitfld.long 0x00 27. "SDCARD_BIAS_PWRDNZ,PWRDNZ control to SDCARD BIAS" "This signal is used to protect SDCARD BIAS when..,SW keep this bit to 1'b1 after VDDS stabilizing" newline bitfld.long 0x00 26. "SDCARD_IO_PWRDNZ,PWRDNZ control to SDCARD IO" "This signal is used to protect SDCARD IOs when..,SW keep this bit to 1'b1 after VDDS stabilizing" newline bitfld.long 0x00 25. "SDCARD_BIAS_HIZ_MODE,HIZ_MODE from SDCARD PBIAS" "PBIAS in normal operation mode,PBIAS output is in high impedance state" newline bitfld.long 0x00 24. "SDCARD_BIAS_SUPPLY_HI_OUT,SUPPLY_HI_OUT from SDCARD PBIAS" "VDDS = 1.8V,VDDS = 3.3V" newline bitfld.long 0x00 23. "SDCARD_BIAS_VMODE_ERROR,VMODE ERROR from SDCARD PBIAS" "VMODE level is same as SUPPLY_HI_OUT,VMODE level is not same as SUPPLY_HI_OUT" newline bitfld.long 0x00 21. "SDCARD_BIAS_VMODE,VMODE control to SDCARD PBIAS" "VDDS = 1.8V,VDDS = 3.3V" group.long 0xE0C++0x03 line.long 0x00 "CTRL_CORE_CONTROL_HDMI_TX_PHY,HDMI TX PHY control" bitfld.long 0x00 30. "HDMITXPHY_TXVALID," "0,1" newline bitfld.long 0x00 29. "HDMITXPHY_ENBYPASSCLK," "0,1" newline bitfld.long 0x00 28. "HDMITXPHY_PD_PULLUPDET," "0,1" group.long 0xE1C++0x07 line.long 0x00 "CTRL_CORE_CONTROL_USB2PHYCORE,This register is related to the USB2_PHY1" bitfld.long 0x00 31. "USB2PHY_AUTORESUME_EN,Auto resume enable" "disable autoresume,enable autoresume" newline bitfld.long 0x00 30. "USB2PHY_DISCHGDET,Disable charger detect" "charger detect function enabled,charger detect function disabled" newline bitfld.long 0x00 29. "USB2PHY_GPIOMODE,GPIO mode" "USB mode enabled,GPIO mode enabled" newline bitfld.long 0x00 28. "USB2PHY_CHG_DET_EXT_CTL,Charge detect external control" "charger detect internal state machine used,charge detect statemachine is bypassed" newline bitfld.long 0x00 27. "USB2PHY_RDM_PD_CHGDET_EN,DM Pull down control" "PD disabled,PD enabled" newline bitfld.long 0x00 26. "USB2PHY_RDP_PU_CHGDET_EN,DP Pull up control" "PU disabled,PU enabled" newline bitfld.long 0x00 25. "USB2PHY_CHG_VSRC_EN,VSRC enable on DP line:Host charger case" "disable VSRC drive on DP,drives VSRC 600mV on DP line" newline bitfld.long 0x00 24. "USB2PHY_CHG_ISINK_EN,ISINK enable on DM line:Host charger case" "disable the isink on DM,enables the ISINK (100uA) on DM line" newline bitfld.long 0x00 21.--23. "USB2PHY_CHG_DET_STATUS,Status of charger detection" "Wait state,No contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" newline bitfld.long 0x00 20. "USB2PHY_CHG_DET_DM_COMP,Output of the comparator on DM during the resistor host detect protocol" "DM line is below 0.75V to 0.95V,DM line is above 0.75V to 0.95V" newline bitfld.long 0x00 19. "USB2PHY_CHG_DET_DP_COMP,Output of the comparator on DP during the resistor host detect protocol" "DP line is below 0.75V to 0.95V,DP line is above 0.75V to 0.95V" newline bitfld.long 0x00 18. "USB2PHY_DATADET,Output of the charger detect comparator" "DM line is below 0.25V to 0.4V,DM line is above 0.25V to 0.4V" newline bitfld.long 0x00 17. "USB2PHY_SINKONDP,When '1' current sink is connected to DP instead of DM" "Default value,enables the ISINK on DP instead of DM" newline bitfld.long 0x00 16. "USB2PHY_SRCONDM,When '1' voltage source is connected to DP instead of DM" "Default value,enable the VSRC on DM instead of DP" newline bitfld.long 0x00 15. "USB2PHY_RESTARTCHGDET,restartchgdet = '1' for 1 msec cause the CD_START to reset" "Default value,a high pulse of 1 msec causes the.." newline bitfld.long 0x00 14. "USB2PHY_CHGDETDONE,Status indicates that charger detection protocol is over" "charger detection protocol is not over,charger detection protocol is over" newline bitfld.long 0x00 13. "USB2PHY_CHGDETECTED,Output of the charger detection protocol" "charger not detected,charger detected" newline bitfld.long 0x00 12. "USB2PHY_MCPCPUEN,MCPC Pull up enable" "disable the MCPC pull up,enable the 4.7K to10K pull up on receive line DP.." newline bitfld.long 0x00 11. "USB2PHY_MCPCMODEEN,MCPC Mode enable" "disable MCPC mode,enable MCPC mode" newline bitfld.long 0x00 10. "USB2PHY_RESETDONEMCLK,OCP reset status" "OCP domain is in reset,OCP domain is out of reset" newline bitfld.long 0x00 9. "USB2PHY_UTMIRESETDONE,UTMI FSM reset status" "UTMI FSMs are in reset,UTMI FSMs are out of reset" newline bitfld.long 0x00 7. "USB2PHY_DATAPOLARITYN,Data polarity" "DP functionality is on DP and DM funcationality..,DP functionality is on DM and DM functionality.." newline rbitfld.long 0x00 6. "USBDPLL_FREQLOCK,Status from USB DPLL" "0,1" newline rbitfld.long 0x00 5. "USB2PHY_RESETDONETCLK,resetdonetclk status from USB2PHY" "0,1" line.long 0x04 "CTRL_CORE_CONTROL_HDMI_1,HDMI pads control 1" bitfld.long 0x04 31. "HDMI_DDC_SDA_GLFENB,Active_high glitch free operation enable pin for hdmi_ddc_sda receiver - DISABLE" "HDMI_DDC_SDA_GLFENB_0,HDMI_DDC_SDA_GLFENB_1" newline bitfld.long 0x04 30. "HDMI_DDC_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for hdmi_ddc_sda - ENABLE" "HDMI_DDC_SDA_PULLUPRESX_0,HDMI_DDC_SDA_PULLUPRESX_1" newline bitfld.long 0x04 29. "HDMI_DDC_SCL_GLFENB,Active_high glitch free operation enable pin for hdmi_ddc_scl receiver - DISABLE" "HDMI_DDC_SCL_GLFENB_0,HDMI_DDC_SCL_GLFENB_1" newline bitfld.long 0x04 28. "HDMI_DDC_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for hdmi_ddc_scl - ENABLE" "HDMI_DDC_SCL_PULLUPRESX_0,HDMI_DDC_SCL_PULLUPRESX_1" newline bitfld.long 0x04 27. "HDMI_DDC_SDA_HSMODE,Active-high selection for I2C High-Speed mode - DISABLE" "HDMI_DDC_SDA_HSMODE_0,HDMI_DDC_SDA_HSMODE_1" newline bitfld.long 0x04 26. "HDMI_DDC_SCL_HSMODE,Active-high selection for I2C High-Speed mode - DISABLE" "HDMI_DDC_SCL_HSMODE_0,HDMI_DDC_SCL_HSMODE_1" group.long 0xE30++0x1B line.long 0x00 "CTRL_CORE_CONTROL_DDRCACH1_0,ddrcaCH1 control" bitfld.long 0x00 29.--31. "DDRCH1_PART0_I,PART0 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 26.--28. "DDRCH1_PART0_SR,PART0 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 24.--25. "DDRCH1_PART0_WD,PART0 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 21.--23. "DDRCH1_PART5A_I,PART5A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 18.--20. "DDRCH1_PART5A_SR,PART5A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 16.--17. "DDRCH1_PART5A_WD,PART5A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 13.--15. "DDRCH1_PART5B_I,PART5B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 10.--12. "DDRCH1_PART5B_SR,PART5B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 8.--9. "DDRCH1_PART5B_WD,PART5B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x00 5.--7. "DDRCH1_PART6_I,PART6 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x00 2.--4. "DDRCH1_PART6_SR,PART6 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x00 0.--1. "DDRCH1_PART6_WD,PART6 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x04 "CTRL_CORE_CONTROL_DDRCACH2_0,ddrcaCH2 control" bitfld.long 0x04 29.--31. "DDRCH2_PART0_I,PART0 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 26.--28. "DDRCH2_PART0_SR,PART0 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 24.--25. "DDRCH2_PART0_WD,PART0 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 21.--23. "DDRCH2_PART5A_I,PART5A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 18.--20. "DDRCH2_PART5A_SR,PART5A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 16.--17. "DDRCH2_PART5A_WD,PART5A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 13.--15. "DDRCH2_PART5B_I,PART5B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 10.--12. "DDRCH2_PART5B_SR,PART5B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 8.--9. "DDRCH2_PART5B_WD,PART5B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x04 5.--7. "DDRCH2_PART6_I,PART6 Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x04 2.--4. "DDRCH2_PART6_SR,PART6 Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x04 0.--1. "DDRCH2_PART6_WD,PART6 Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x08 "CTRL_CORE_CONTROL_DDRCH1_0,DDRCH1 control 0" bitfld.long 0x08 29.--31. "DDRCH1_PART1A_I,PART1A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x08 26.--28. "DDRCH1_PART1A_SR,PART1A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x08 24.--25. "DDRCH1_PART1A_WD,PART1A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x08 21.--23. "DDRCH1_PART1B_I,PART1B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x08 18.--20. "DDRCH1_PART1B_SR,PART1B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x08 16.--17. "DDRCH1_PART1B_WD,PART1B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x08 13.--15. "DDRCH1_PART2A_I,PART2A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x08 10.--12. "DDRCH1_PART2A_SR,PART2A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x08 8.--9. "DDRCH1_PART2A_WD,PART2A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x08 5.--7. "DDRCH1_PART2B_I,PART2B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x08 2.--4. "DDRCH1_PART2B_SR,PART2B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x08 0.--1. "DDRCH1_PART2B_WD,PART2B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x0C "CTRL_CORE_CONTROL_DDRCH1_1,DDRCH1 control 1" bitfld.long 0x0C 29.--31. "DDRCH1_PART3A_I,PART3A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 26.--28. "DDRCH1_PART3A_SR,PART3A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x0C 24.--25. "DDRCH1_PART3A_WD,PART3A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x0C 21.--23. "DDRCH1_PART3B_I,PART3B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 18.--20. "DDRCH1_PART3B_SR,PART3B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x0C 16.--17. "DDRCH1_PART3B_WD,PART3B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x0C 13.--15. "DDRCH1_PART4A_I,PART4A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 10.--12. "DDRCH1_PART4A_SR,PART4A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x0C 8.--9. "DDRCH1_PART4A_WD,PART4A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x0C 5.--7. "DDRCH1_PART4B_I,PART4B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 2.--4. "DDRCH1_PART4B_SR,PART4B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x0C 0.--1. "DDRCH1_PART4B_WD,PART4B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x10 "CTRL_CORE_CONTROL_DDRCH2_0,DDRCH2 control 0" bitfld.long 0x10 29.--31. "DDRCH2_PART1A_I,PART1A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x10 26.--28. "DDRCH2_PART1A_SR,PART1A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x10 24.--25. "DDRCH2_PART1A_WD,PART1A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x10 21.--23. "DDRCH2_PART1B_I,PART1B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x10 18.--20. "DDRCH2_PART1B_SR,PART1B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x10 16.--17. "DDRCH2_PART1B_WD,PART1B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x10 13.--15. "DDRCH2_PART2A_I,PART2A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x10 10.--12. "DDRCH2_PART2A_SR,PART2A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x10 8.--9. "DDRCH2_PART2A_WD,PART2A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x10 5.--7. "DDRCH2_PART2B_I,PART2B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x10 2.--4. "DDRCH2_PART2B_SR,PART2B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x10 0.--1. "DDRCH2_PART2B_WD,PART2B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x14 "CTRL_CORE_CONTROL_DDRCH2_1,DDRCH2 control 1" bitfld.long 0x14 29.--31. "DDRCH2_PART3A_I,PART3A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x14 26.--28. "DDRCH2_PART3A_SR,PART3A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x14 24.--25. "DDRCH2_PART3A_WD,PART3A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x14 21.--23. "DDRCH2_PART3B_I,PART3B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x14 18.--20. "DDRCH2_PART3B_SR,PART3B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x14 16.--17. "DDRCH2_PART3B_WD,PART3B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x14 13.--15. "DDRCH2_PART4A_I,PART4A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x14 10.--12. "DDRCH2_PART4A_SR,PART4A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x14 8.--9. "DDRCH2_PART4A_WD,PART4A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x14 5.--7. "DDRCH2_PART4B_I,PART4B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x14 2.--4. "DDRCH2_PART4B_SR,PART4B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x14 0.--1. "DDRCH2_PART4B_WD,PART4B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" line.long 0x18 "CTRL_CORE_CONTROL_DDRCH1_2," bitfld.long 0x18 21.--23. "DDRCH1_PART7A_I,PART7A Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x18 18.--20. "DDRCH1_PART7A_SR,PART7A Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x18 16.--17. "DDRCH1_PART7A_WD,PART7A Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" newline bitfld.long 0x18 13.--15. "DDRCH1_PART7B_I,PART7B Impedence control I[2:0]" "Imp80,Imp60,Imp48,Imp40,Imp34,Reserved,Reserved,Reserved" newline bitfld.long 0x18 10.--12. "DDRCH1_PART7B_SR,PART7B Slew Rate control SR[2:0]" "Fastest,?,?,?,?,?,?,Slowest" newline bitfld.long 0x18 8.--9. "DDRCH1_PART7B_WD,PART7B Weak driver control WD[1:0] -For single-ended operation" "Pull logic is disabled,Pull-up selected for padp pull-down selected for..,Pull-down selected for padp pull-up selected for..,Maintain the previous output value" group.long 0xE50++0x07 line.long 0x00 "CTRL_CORE_CONTROL_DDRIO_0," bitfld.long 0x00 19. "DDRCH1_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ0_INT_CCAP0_0,DDRCH1_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x00 18. "DDRCH1_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ0_INT_CCAP1_0,DDRCH1_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x00 17. "DDRCH1_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ0_INT_TAP0_0,DDRCH1_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x00 16. "DDRCH1_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ0_INT_TAP1_0,DDRCH1_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x00 15. "DDRCH1_VREF_DQ0_INT_EN,Enable - DISABLE" "DDRCH1_VREF_DQ0_INT_EN_0,DDRCH1_VREF_DQ0_INT_EN_1" newline bitfld.long 0x00 14. "DDRCH1_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ1_INT_CCAP0_0,DDRCH1_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x00 13. "DDRCH1_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ1_INT_CCAP1_0,DDRCH1_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x00 12. "DDRCH1_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ1_INT_TAP0_0,DDRCH1_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x00 11. "DDRCH1_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ1_INT_TAP1_0,DDRCH1_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x00 10. "DDRCH1_VREF_DQ1_INT_EN,Enable - DISABLE" "DDRCH1_VREF_DQ1_INT_EN_0,DDRCH1_VREF_DQ1_INT_EN_1" line.long 0x04 "CTRL_CORE_CONTROL_DDRIO_1," bitfld.long 0x04 26. "DDRCH2_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ0_INT_CCAP0_0,DDRCH2_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x04 25. "DDRCH2_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ0_INT_CCAP1_0,DDRCH2_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x04 24. "DDRCH2_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ0_INT_TAP0_0,DDRCH2_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x04 23. "DDRCH2_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ0_INT_TAP1_0,DDRCH2_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x04 22. "DDRCH2_VREF_DQ0_INT_EN,Enable - DISABLE" "DDRCH2_VREF_DQ0_INT_EN_0,DDRCH2_VREF_DQ0_INT_EN_1" newline bitfld.long 0x04 21. "DDRCH2_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ1_INT_CCAP0_0,DDRCH2_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x04 20. "DDRCH2_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ1_INT_CCAP1_0,DDRCH2_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x04 19. "DDRCH2_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ1_INT_TAP0_0,DDRCH2_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x04 18. "DDRCH2_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ1_INT_TAP1_0,DDRCH2_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x04 17. "DDRCH2_VREF_DQ1_INT_EN,Enable - DISABLE" "DDRCH2_VREF_DQ1_INT_EN_0,DDRCH2_VREF_DQ1_INT_EN_1" group.long 0xE5C++0x03 line.long 0x00 "CTRL_CORE_CONTROL_HYST_1,Register for hysteresis and impedance control of the MMC1 pads" bitfld.long 0x00 31. "SDCARD_HYST,hysteresis control for the pads associated with the PBIAS cell" "Disabled,Enabled" newline bitfld.long 0x00 29.--30. "SDCARD_IC,Drive strength control for MMC1 pads In 3.3V signaling mode" "44 Ohms Drive Strength,33 Ohms Drive Strength,58 Ohms Drive Strength,100 Ohms Drive Strength" group.long 0xE64++0x07 line.long 0x00 "CTRL_CORE_CONTROL_C2C,Loop Bandwidth control for DPLL_SATA and DPLL_PCIE_REF.[New TDA2Px feature versus TDA2x]" bitfld.long 0x00 31. "PLL_SATA_LOOPBW_INCR_DECRZ," "0,1" newline bitfld.long 0x00 29.--30. "PLL_SATA_LOOPBW,DPLL_SATA loop bandwidth mode If PLL_SATA_LOOPBW_INCR_DECRZ =" "1x Mode (Loop BW is..,2x Mode (Loop BW is..,Reserved,Reserved" newline bitfld.long 0x00 28. "PLL_PCIEREF_LOOPBW_INCR_DECRZ," "0,1" newline bitfld.long 0x00 26.--27. "PLL_PCIEREF_LOOPBW,DPLL_PCIE_REF loop bandwidth mode If PLL_PCIEREF_LOOPBW_INCR_DECRZ =" "1x Mode (Loop BW is..,2x Mode (Loop BW is..,Reserved,Reserved" newline bitfld.long 0x00 24.--25. "C2C_SPARE_RESERVED,Reserved bits" "0,1,2,3" line.long 0x04 "CTRL_CORE_CONTROL_SPARE_RW," hexmask.long.word 0x04 17.--31. 1. "CORE_CONTROL_SPARE_RW,Spare bits" newline bitfld.long 0x04 16. "SEL_GPMC_CLK_INTLB,Selects the source of loopback clock for gpmc_clk" "Loopback clock from the I/O pad is selected,Internal loopback clock is selected" newline bitfld.long 0x04 15. "CORE_CONTROL_SPARE_RW_15,Spare bits" "0,1" newline bitfld.long 0x04 13.--14. "SEL_ALT_MCAN,Selection for MCAN signal muxing" "The dcan2_tx and dcan2_rx signals are on the..,The mcan_tx and mcan_rx signals are on the..,The mcan_tx and mcan_rx signals are on the..,Reserved" newline bitfld.long 0x04 12. "VIP_SEL_4A," "0,1" newline bitfld.long 0x04 11. "VIP_SEL_3A," "0,1" newline bitfld.long 0x04 10. "VIP_SEL_2A," "0,1" newline bitfld.long 0x04 9. "VIP_SEL_1A," "0,1" newline bitfld.long 0x04 8. "CORE_CONTROL_SPARE_RW,Spare bit" "0,1" newline bitfld.long 0x04 7. "SEL_ALT_GROUP4,Selects a signal as described in" "0,1" newline bitfld.long 0x04 6. "SEL_ALT_GROUP3," "0,1" newline bitfld.long 0x04 5. "SEL_ALT_GROUP2,Selects a signal as described in" "0,1" newline bitfld.long 0x04 4. "SEL_ALT_GROUP1," "0,1" newline bitfld.long 0x04 2.--3. "CORE_CONTROL_SPARE_RW,Spare bits" "0,1,2,3" newline bitfld.long 0x04 1. "CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK,Selects the source of loopback clock for mmc2_clk" "Loopback clock from the I/O pad is selected,Internal loopback clock is selected" newline bitfld.long 0x04 0. "CORE_CONTROL_SPARE_RW_MMC1_LOOPBACK,Selects the source of loopback clock for mmc1_clk" "Loopback clock from the I/O pad is selected,Internal loopback clock is selected" group.long 0xE74++0x07 line.long 0x00 "CTRL_CORE_SRCOMP_NORTH_SIDE,This register is related to the USB2_PHY2" bitfld.long 0x00 30. "USB2PHY_AUTORESUME_EN,Auto resume enable" "disable autoresume,enable autoresume" newline bitfld.long 0x00 29. "USB2PHY_DISCHGDET,Disable charger detect" "charger detect function enabled,charger detect function disabled" newline bitfld.long 0x00 28. "USB2PHY_PD,Power down the entire USB2_PHY2 (data common module and UTMI)" "Normal operation,Power down the USB2_PHY2" newline bitfld.long 0x00 20. "USB2PHY_CHG_DET_DM_COMP,Output of the comparator on DM during the resistor host detect protocol" "DM line is below 0.75V to 0.95V,DM line is above 0.75V to 0.95V" newline bitfld.long 0x00 19. "USB2PHY_CHG_DET_DP_COMP,Output of the comparator on DP during the resistor host detect protocol" "DP line is below 0.75V to 0.95V,DP line is above 0.75V to 0.95V" newline bitfld.long 0x00 18. "USB2PHY_DATADET,Output of the charger detect comparator" "DM line is below 0.25V to 0.4V,DM line is above 0.25V to 0.4V" newline bitfld.long 0x00 17. "USB2PHY_CHGDETDONE,Status indicates that charger detection protocol is over" "charger detection protocol is not over,charger detection protocol is over" newline bitfld.long 0x00 16. "USB2PHY_CHGDETECTED,Output of the charger detection protocol" "charger not detected,charger detected" newline bitfld.long 0x00 15. "USB2PHY_RESETDONEMCLK,OCP reset status" "OCP domain is in reset,OCP domain is out of reset" newline bitfld.long 0x00 14. "USB2PHY_UTMIRESETDONE,UTMI FSM reset status" "UTMI FSMs are in reset,UTMI FSMs are out of reset" newline rbitfld.long 0x00 13. "USBDPLL_FREQLOCK,Status from USB DPLL" "0,1" newline rbitfld.long 0x00 12. "USB2PHY_RESETDONETCLK,resetdonetclk status from USB2_PHY2" "0,1" newline bitfld.long 0x00 11. "USB2PHY_GPIOMODE,GPIO mode" "USB mode enabled,GPIO mode enabled" newline bitfld.long 0x00 10. "USB2PHY_CHG_DET_EXT_CTL,Charge detect external control" "charger detect internal state machine used,charge detect statemachine is bypassed" newline bitfld.long 0x00 9. "USB2PHY_RDM_PD_CHGDET_EN,DM Pull down control" "PD disabled,PD enabled" newline bitfld.long 0x00 8. "USB2PHY_RDP_PU_CHGDET_EN,DP Pull up control" "PU disabled,PU enabled" newline bitfld.long 0x00 7. "USB2PHY_CHG_VSRC_EN,VSRC enable on DP line: Host charger case" "disable VSRC drive on DP,drives VSRC 600mV on DP line" newline bitfld.long 0x00 6. "USB2PHY_CHG_ISINK_EN,ISINK enable on DM line: Host charger case" "disable the ISINK on DM,enables the ISINK (100microA) on DM line" newline bitfld.long 0x00 5. "USB2PHY_SINKONDP,When '1' current sink is connected to DP instead of DM" "Default value,enables the ISINK on DP instead of DM" newline bitfld.long 0x00 4. "USB2PHY_SRCONDM,When '1' voltage source is connected to DP instead of DM" "Default value,enable the VSRC on DM instead of DP" newline bitfld.long 0x00 3. "USB2PHY_RESTARTCHGDET,restartchgdet: '1' for 1 msec cause the CD_START to reset" "Default value,a high pulse of 1 msec causes the.." newline bitfld.long 0x00 2. "USB2PHY_MCPCPUEN,MCPC Pull up enable" "disable the MCPC pull up,enable the 4.7K to10K pull up on receive line DP.." newline bitfld.long 0x00 1. "USB2PHY_MCPCMODEEN,MCPC Mode enable" "disable MCPC mode,enable MCPC mode" newline bitfld.long 0x00 0. "USB2PHY_DATAPOLARITYN,Data polarity" "DP functionality is on DP and DM funcationality..,DP functionality is on DM and DM functionality.." line.long 0x04 "CTRL_CORE_SRCOMP_SOUTH_SIDE,This register is related to the USB2_PHY2" bitfld.long 0x04 12.--14. "USB2PHY_CHG_DET_STATUS,Status of charger detection" "Wait state,No contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" group.long 0x1400++0x3D7 line.long 0x00 "CTRL_CORE_PAD_GPMC_AD0," rbitfld.long 0x00 25. "GPMC_AD0_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD0_WAKEUPEVENT_0,GPMC_AD0_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "GPMC_AD0_WAKEUPENABLE,- DISABLE" "GPMC_AD0_WAKEUPENABLE_0,GPMC_AD0_WAKEUPENABLE_1" newline bitfld.long 0x00 19. "GPMC_AD0_SLEWCONTROL,- FAST_SLEW" "GPMC_AD0_SLEWCONTROL_0,GPMC_AD0_SLEWCONTROL_1" newline bitfld.long 0x00 18. "GPMC_AD0_INPUTENABLE,- DISABLE" "GPMC_AD0_INPUTENABLE_0,GPMC_AD0_INPUTENABLE_1" newline bitfld.long 0x00 17. "GPMC_AD0_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD0_PULLTYPESELECT_0,GPMC_AD0_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "GPMC_AD0_PULLUDENABLE,- ENABLE" "GPMC_AD0_PULLUDENABLE_0,GPMC_AD0_PULLUDENABLE_1" newline bitfld.long 0x00 8. "GPMC_AD0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD0_MODESELECT_0,GPMC_AD0_MODESELECT_1" newline bitfld.long 0x00 4.--7. "GPMC_AD0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "GPMC_AD0_MUXMODE,- GPMC_AD0" "GPMC_AD0_MUXMODE_0,?,GPMC_AD0_MUXMODE_2,GPMC_AD0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD0_MUXMODE_14,GPMC_AD0_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_GPMC_AD1," rbitfld.long 0x04 25. "GPMC_AD1_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD1_WAKEUPEVENT_0,GPMC_AD1_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "GPMC_AD1_WAKEUPENABLE,- DISABLE" "GPMC_AD1_WAKEUPENABLE_0,GPMC_AD1_WAKEUPENABLE_1" newline bitfld.long 0x04 19. "GPMC_AD1_SLEWCONTROL,- FAST_SLEW" "GPMC_AD1_SLEWCONTROL_0,GPMC_AD1_SLEWCONTROL_1" newline bitfld.long 0x04 18. "GPMC_AD1_INPUTENABLE,- DISABLE" "GPMC_AD1_INPUTENABLE_0,GPMC_AD1_INPUTENABLE_1" newline bitfld.long 0x04 17. "GPMC_AD1_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD1_PULLTYPESELECT_0,GPMC_AD1_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "GPMC_AD1_PULLUDENABLE,- ENABLE" "GPMC_AD1_PULLUDENABLE_0,GPMC_AD1_PULLUDENABLE_1" newline bitfld.long 0x04 8. "GPMC_AD1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD1_MODESELECT_0,GPMC_AD1_MODESELECT_1" newline bitfld.long 0x04 4.--7. "GPMC_AD1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "GPMC_AD1_MUXMODE,- GPMC_AD1" "GPMC_AD1_MUXMODE_0,?,GPMC_AD1_MUXMODE_2,GPMC_AD1_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD1_MUXMODE_14,GPMC_AD1_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_GPMC_AD2," rbitfld.long 0x08 25. "GPMC_AD2_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD2_WAKEUPEVENT_0,GPMC_AD2_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "GPMC_AD2_WAKEUPENABLE,- DISABLE" "GPMC_AD2_WAKEUPENABLE_0,GPMC_AD2_WAKEUPENABLE_1" newline bitfld.long 0x08 19. "GPMC_AD2_SLEWCONTROL,- FAST_SLEW" "GPMC_AD2_SLEWCONTROL_0,GPMC_AD2_SLEWCONTROL_1" newline bitfld.long 0x08 18. "GPMC_AD2_INPUTENABLE,- DISABLE" "GPMC_AD2_INPUTENABLE_0,GPMC_AD2_INPUTENABLE_1" newline bitfld.long 0x08 17. "GPMC_AD2_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD2_PULLTYPESELECT_0,GPMC_AD2_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "GPMC_AD2_PULLUDENABLE,- ENABLE" "GPMC_AD2_PULLUDENABLE_0,GPMC_AD2_PULLUDENABLE_1" newline bitfld.long 0x08 8. "GPMC_AD2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD2_MODESELECT_0,GPMC_AD2_MODESELECT_1" newline bitfld.long 0x08 4.--7. "GPMC_AD2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GPMC_AD2_MUXMODE,- GPMC_AD2" "GPMC_AD2_MUXMODE_0,?,GPMC_AD2_MUXMODE_2,GPMC_AD2_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD2_MUXMODE_14,GPMC_AD2_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_GPMC_AD3," rbitfld.long 0x0C 25. "GPMC_AD3_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD3_WAKEUPEVENT_0,GPMC_AD3_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "GPMC_AD3_WAKEUPENABLE,- DISABLE" "GPMC_AD3_WAKEUPENABLE_0,GPMC_AD3_WAKEUPENABLE_1" newline bitfld.long 0x0C 19. "GPMC_AD3_SLEWCONTROL,- FAST_SLEW" "GPMC_AD3_SLEWCONTROL_0,GPMC_AD3_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "GPMC_AD3_INPUTENABLE,- DISABLE" "GPMC_AD3_INPUTENABLE_0,GPMC_AD3_INPUTENABLE_1" newline bitfld.long 0x0C 17. "GPMC_AD3_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD3_PULLTYPESELECT_0,GPMC_AD3_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "GPMC_AD3_PULLUDENABLE,- ENABLE" "GPMC_AD3_PULLUDENABLE_0,GPMC_AD3_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "GPMC_AD3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD3_MODESELECT_0,GPMC_AD3_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "GPMC_AD3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "GPMC_AD3_MUXMODE,- GPMC_AD3" "GPMC_AD3_MUXMODE_0,?,GPMC_AD3_MUXMODE_2,GPMC_AD3_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD3_MUXMODE_14,GPMC_AD3_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_GPMC_AD4," rbitfld.long 0x10 25. "GPMC_AD4_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD4_WAKEUPEVENT_0,GPMC_AD4_WAKEUPEVENT_1" newline bitfld.long 0x10 24. "GPMC_AD4_WAKEUPENABLE,- DISABLE" "GPMC_AD4_WAKEUPENABLE_0,GPMC_AD4_WAKEUPENABLE_1" newline bitfld.long 0x10 19. "GPMC_AD4_SLEWCONTROL,- FAST_SLEW" "GPMC_AD4_SLEWCONTROL_0,GPMC_AD4_SLEWCONTROL_1" newline bitfld.long 0x10 18. "GPMC_AD4_INPUTENABLE,- DISABLE" "GPMC_AD4_INPUTENABLE_0,GPMC_AD4_INPUTENABLE_1" newline bitfld.long 0x10 17. "GPMC_AD4_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD4_PULLTYPESELECT_0,GPMC_AD4_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "GPMC_AD4_PULLUDENABLE,- ENABLE" "GPMC_AD4_PULLUDENABLE_0,GPMC_AD4_PULLUDENABLE_1" newline bitfld.long 0x10 8. "GPMC_AD4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD4_MODESELECT_0,GPMC_AD4_MODESELECT_1" newline bitfld.long 0x10 4.--7. "GPMC_AD4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "GPMC_AD4_MUXMODE,- GPMC_AD4" "GPMC_AD4_MUXMODE_0,?,GPMC_AD4_MUXMODE_2,GPMC_AD4_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD4_MUXMODE_14,GPMC_AD4_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_GPMC_AD5," rbitfld.long 0x14 25. "GPMC_AD5_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD5_WAKEUPEVENT_0,GPMC_AD5_WAKEUPEVENT_1" newline bitfld.long 0x14 24. "GPMC_AD5_WAKEUPENABLE,- DISABLE" "GPMC_AD5_WAKEUPENABLE_0,GPMC_AD5_WAKEUPENABLE_1" newline bitfld.long 0x14 19. "GPMC_AD5_SLEWCONTROL,- FAST_SLEW" "GPMC_AD5_SLEWCONTROL_0,GPMC_AD5_SLEWCONTROL_1" newline bitfld.long 0x14 18. "GPMC_AD5_INPUTENABLE,- DISABLE" "GPMC_AD5_INPUTENABLE_0,GPMC_AD5_INPUTENABLE_1" newline bitfld.long 0x14 17. "GPMC_AD5_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD5_PULLTYPESELECT_0,GPMC_AD5_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "GPMC_AD5_PULLUDENABLE,- ENABLE" "GPMC_AD5_PULLUDENABLE_0,GPMC_AD5_PULLUDENABLE_1" newline bitfld.long 0x14 8. "GPMC_AD5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD5_MODESELECT_0,GPMC_AD5_MODESELECT_1" newline bitfld.long 0x14 4.--7. "GPMC_AD5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "GPMC_AD5_MUXMODE,- GPMC_AD5" "GPMC_AD5_MUXMODE_0,?,GPMC_AD5_MUXMODE_2,GPMC_AD5_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD5_MUXMODE_14,GPMC_AD5_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_GPMC_AD6," rbitfld.long 0x18 25. "GPMC_AD6_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD6_WAKEUPEVENT_0,GPMC_AD6_WAKEUPEVENT_1" newline bitfld.long 0x18 24. "GPMC_AD6_WAKEUPENABLE,- DISABLE" "GPMC_AD6_WAKEUPENABLE_0,GPMC_AD6_WAKEUPENABLE_1" newline bitfld.long 0x18 19. "GPMC_AD6_SLEWCONTROL,- FAST_SLEW" "GPMC_AD6_SLEWCONTROL_0,GPMC_AD6_SLEWCONTROL_1" newline bitfld.long 0x18 18. "GPMC_AD6_INPUTENABLE,- DISABLE" "GPMC_AD6_INPUTENABLE_0,GPMC_AD6_INPUTENABLE_1" newline bitfld.long 0x18 17. "GPMC_AD6_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD6_PULLTYPESELECT_0,GPMC_AD6_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "GPMC_AD6_PULLUDENABLE,- ENABLE" "GPMC_AD6_PULLUDENABLE_0,GPMC_AD6_PULLUDENABLE_1" newline bitfld.long 0x18 8. "GPMC_AD6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD6_MODESELECT_0,GPMC_AD6_MODESELECT_1" newline bitfld.long 0x18 4.--7. "GPMC_AD6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. "GPMC_AD6_MUXMODE,- GPMC_AD6" "GPMC_AD6_MUXMODE_0,?,GPMC_AD6_MUXMODE_2,GPMC_AD6_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD6_MUXMODE_14,GPMC_AD6_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_GPMC_AD7," rbitfld.long 0x1C 25. "GPMC_AD7_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD7_WAKEUPEVENT_0,GPMC_AD7_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "GPMC_AD7_WAKEUPENABLE,- DISABLE" "GPMC_AD7_WAKEUPENABLE_0,GPMC_AD7_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "GPMC_AD7_SLEWCONTROL,- FAST_SLEW" "GPMC_AD7_SLEWCONTROL_0,GPMC_AD7_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "GPMC_AD7_INPUTENABLE,- DISABLE" "GPMC_AD7_INPUTENABLE_0,GPMC_AD7_INPUTENABLE_1" newline bitfld.long 0x1C 17. "GPMC_AD7_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD7_PULLTYPESELECT_0,GPMC_AD7_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "GPMC_AD7_PULLUDENABLE,- ENABLE" "GPMC_AD7_PULLUDENABLE_0,GPMC_AD7_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "GPMC_AD7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD7_MODESELECT_0,GPMC_AD7_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "GPMC_AD7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "GPMC_AD7_MUXMODE,- GPMC_AD7" "GPMC_AD7_MUXMODE_0,?,GPMC_AD7_MUXMODE_2,GPMC_AD7_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD7_MUXMODE_14,GPMC_AD7_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_GPMC_AD8," rbitfld.long 0x20 25. "GPMC_AD8_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD8_WAKEUPEVENT_0,GPMC_AD8_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "GPMC_AD8_WAKEUPENABLE,- DISABLE" "GPMC_AD8_WAKEUPENABLE_0,GPMC_AD8_WAKEUPENABLE_1" newline bitfld.long 0x20 19. "GPMC_AD8_SLEWCONTROL,- FAST_SLEW" "GPMC_AD8_SLEWCONTROL_0,GPMC_AD8_SLEWCONTROL_1" newline bitfld.long 0x20 18. "GPMC_AD8_INPUTENABLE,- DISABLE" "GPMC_AD8_INPUTENABLE_0,GPMC_AD8_INPUTENABLE_1" newline bitfld.long 0x20 17. "GPMC_AD8_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD8_PULLTYPESELECT_0,GPMC_AD8_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "GPMC_AD8_PULLUDENABLE,- ENABLE" "GPMC_AD8_PULLUDENABLE_0,GPMC_AD8_PULLUDENABLE_1" newline bitfld.long 0x20 8. "GPMC_AD8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD8_MODESELECT_0,GPMC_AD8_MODESELECT_1" newline bitfld.long 0x20 4.--7. "GPMC_AD8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--3. "GPMC_AD8_MUXMODE,- GPMC_AD8" "GPMC_AD8_MUXMODE_0,?,GPMC_AD8_MUXMODE_2,GPMC_AD8_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD8_MUXMODE_14,GPMC_AD8_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_GPMC_AD9," rbitfld.long 0x24 25. "GPMC_AD9_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD9_WAKEUPEVENT_0,GPMC_AD9_WAKEUPEVENT_1" newline bitfld.long 0x24 24. "GPMC_AD9_WAKEUPENABLE,- DISABLE" "GPMC_AD9_WAKEUPENABLE_0,GPMC_AD9_WAKEUPENABLE_1" newline bitfld.long 0x24 19. "GPMC_AD9_SLEWCONTROL,- FAST_SLEW" "GPMC_AD9_SLEWCONTROL_0,GPMC_AD9_SLEWCONTROL_1" newline bitfld.long 0x24 18. "GPMC_AD9_INPUTENABLE,- DISABLE" "GPMC_AD9_INPUTENABLE_0,GPMC_AD9_INPUTENABLE_1" newline bitfld.long 0x24 17. "GPMC_AD9_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD9_PULLTYPESELECT_0,GPMC_AD9_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "GPMC_AD9_PULLUDENABLE,- ENABLE" "GPMC_AD9_PULLUDENABLE_0,GPMC_AD9_PULLUDENABLE_1" newline bitfld.long 0x24 8. "GPMC_AD9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD9_MODESELECT_0,GPMC_AD9_MODESELECT_1" newline bitfld.long 0x24 4.--7. "GPMC_AD9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24 0.--3. "GPMC_AD9_MUXMODE,- GPMC_AD9" "GPMC_AD9_MUXMODE_0,?,GPMC_AD9_MUXMODE_2,GPMC_AD9_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD9_MUXMODE_14,GPMC_AD9_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_GPMC_AD10," rbitfld.long 0x28 25. "GPMC_AD10_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD10_WAKEUPEVENT_0,GPMC_AD10_WAKEUPEVENT_1" newline bitfld.long 0x28 24. "GPMC_AD10_WAKEUPENABLE,- DISABLE" "GPMC_AD10_WAKEUPENABLE_0,GPMC_AD10_WAKEUPENABLE_1" newline bitfld.long 0x28 19. "GPMC_AD10_SLEWCONTROL,- FAST_SLEW" "GPMC_AD10_SLEWCONTROL_0,GPMC_AD10_SLEWCONTROL_1" newline bitfld.long 0x28 18. "GPMC_AD10_INPUTENABLE,- DISABLE" "GPMC_AD10_INPUTENABLE_0,GPMC_AD10_INPUTENABLE_1" newline bitfld.long 0x28 17. "GPMC_AD10_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD10_PULLTYPESELECT_0,GPMC_AD10_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "GPMC_AD10_PULLUDENABLE,- ENABLE" "GPMC_AD10_PULLUDENABLE_0,GPMC_AD10_PULLUDENABLE_1" newline bitfld.long 0x28 8. "GPMC_AD10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD10_MODESELECT_0,GPMC_AD10_MODESELECT_1" newline bitfld.long 0x28 4.--7. "GPMC_AD10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "GPMC_AD10_MUXMODE,- GPMC_AD10" "GPMC_AD10_MUXMODE_0,?,GPMC_AD10_MUXMODE_2,GPMC_AD10_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD10_MUXMODE_14,GPMC_AD10_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_GPMC_AD11," rbitfld.long 0x2C 25. "GPMC_AD11_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD11_WAKEUPEVENT_0,GPMC_AD11_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "GPMC_AD11_WAKEUPENABLE,- DISABLE" "GPMC_AD11_WAKEUPENABLE_0,GPMC_AD11_WAKEUPENABLE_1" newline bitfld.long 0x2C 19. "GPMC_AD11_SLEWCONTROL,- FAST_SLEW" "GPMC_AD11_SLEWCONTROL_0,GPMC_AD11_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "GPMC_AD11_INPUTENABLE,- DISABLE" "GPMC_AD11_INPUTENABLE_0,GPMC_AD11_INPUTENABLE_1" newline bitfld.long 0x2C 17. "GPMC_AD11_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD11_PULLTYPESELECT_0,GPMC_AD11_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "GPMC_AD11_PULLUDENABLE,- ENABLE" "GPMC_AD11_PULLUDENABLE_0,GPMC_AD11_PULLUDENABLE_1" newline bitfld.long 0x2C 8. "GPMC_AD11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD11_MODESELECT_0,GPMC_AD11_MODESELECT_1" newline bitfld.long 0x2C 4.--7. "GPMC_AD11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 0.--3. "GPMC_AD11_MUXMODE,- GPMC_AD11" "GPMC_AD11_MUXMODE_0,?,GPMC_AD11_MUXMODE_2,GPMC_AD11_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD11_MUXMODE_14,GPMC_AD11_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_GPMC_AD12," rbitfld.long 0x30 25. "GPMC_AD12_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD12_WAKEUPEVENT_0,GPMC_AD12_WAKEUPEVENT_1" newline bitfld.long 0x30 24. "GPMC_AD12_WAKEUPENABLE,- DISABLE" "GPMC_AD12_WAKEUPENABLE_0,GPMC_AD12_WAKEUPENABLE_1" newline bitfld.long 0x30 19. "GPMC_AD12_SLEWCONTROL,- FAST_SLEW" "GPMC_AD12_SLEWCONTROL_0,GPMC_AD12_SLEWCONTROL_1" newline bitfld.long 0x30 18. "GPMC_AD12_INPUTENABLE,- DISABLE" "GPMC_AD12_INPUTENABLE_0,GPMC_AD12_INPUTENABLE_1" newline bitfld.long 0x30 17. "GPMC_AD12_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD12_PULLTYPESELECT_0,GPMC_AD12_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "GPMC_AD12_PULLUDENABLE,- ENABLE" "GPMC_AD12_PULLUDENABLE_0,GPMC_AD12_PULLUDENABLE_1" newline bitfld.long 0x30 8. "GPMC_AD12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD12_MODESELECT_0,GPMC_AD12_MODESELECT_1" newline bitfld.long 0x30 4.--7. "GPMC_AD12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "GPMC_AD12_MUXMODE,- GPMC_AD12" "GPMC_AD12_MUXMODE_0,?,GPMC_AD12_MUXMODE_2,GPMC_AD12_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD12_MUXMODE_14,GPMC_AD12_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_GPMC_AD13," rbitfld.long 0x34 25. "GPMC_AD13_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD13_WAKEUPEVENT_0,GPMC_AD13_WAKEUPEVENT_1" newline bitfld.long 0x34 24. "GPMC_AD13_WAKEUPENABLE,- DISABLE" "GPMC_AD13_WAKEUPENABLE_0,GPMC_AD13_WAKEUPENABLE_1" newline bitfld.long 0x34 19. "GPMC_AD13_SLEWCONTROL,- FAST_SLEW" "GPMC_AD13_SLEWCONTROL_0,GPMC_AD13_SLEWCONTROL_1" newline bitfld.long 0x34 18. "GPMC_AD13_INPUTENABLE,- DISABLE" "GPMC_AD13_INPUTENABLE_0,GPMC_AD13_INPUTENABLE_1" newline bitfld.long 0x34 17. "GPMC_AD13_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD13_PULLTYPESELECT_0,GPMC_AD13_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "GPMC_AD13_PULLUDENABLE,- ENABLE" "GPMC_AD13_PULLUDENABLE_0,GPMC_AD13_PULLUDENABLE_1" newline bitfld.long 0x34 8. "GPMC_AD13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD13_MODESELECT_0,GPMC_AD13_MODESELECT_1" newline bitfld.long 0x34 4.--7. "GPMC_AD13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34 0.--3. "GPMC_AD13_MUXMODE,- GPMC_AD13" "GPMC_AD13_MUXMODE_0,?,GPMC_AD13_MUXMODE_2,GPMC_AD13_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD13_MUXMODE_14,GPMC_AD13_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_GPMC_AD14," rbitfld.long 0x38 25. "GPMC_AD14_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD14_WAKEUPEVENT_0,GPMC_AD14_WAKEUPEVENT_1" newline bitfld.long 0x38 24. "GPMC_AD14_WAKEUPENABLE,- DISABLE" "GPMC_AD14_WAKEUPENABLE_0,GPMC_AD14_WAKEUPENABLE_1" newline bitfld.long 0x38 19. "GPMC_AD14_SLEWCONTROL,- FAST_SLEW" "GPMC_AD14_SLEWCONTROL_0,GPMC_AD14_SLEWCONTROL_1" newline bitfld.long 0x38 18. "GPMC_AD14_INPUTENABLE,- DISABLE" "GPMC_AD14_INPUTENABLE_0,GPMC_AD14_INPUTENABLE_1" newline bitfld.long 0x38 17. "GPMC_AD14_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD14_PULLTYPESELECT_0,GPMC_AD14_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "GPMC_AD14_PULLUDENABLE,- ENABLE" "GPMC_AD14_PULLUDENABLE_0,GPMC_AD14_PULLUDENABLE_1" newline bitfld.long 0x38 8. "GPMC_AD14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD14_MODESELECT_0,GPMC_AD14_MODESELECT_1" newline bitfld.long 0x38 4.--7. "GPMC_AD14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 0.--3. "GPMC_AD14_MUXMODE,- GPMC_AD14" "GPMC_AD14_MUXMODE_0,?,GPMC_AD14_MUXMODE_2,GPMC_AD14_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD14_MUXMODE_14,GPMC_AD14_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_GPMC_AD15," rbitfld.long 0x3C 25. "GPMC_AD15_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD15_WAKEUPEVENT_0,GPMC_AD15_WAKEUPEVENT_1" newline bitfld.long 0x3C 24. "GPMC_AD15_WAKEUPENABLE,- DISABLE" "GPMC_AD15_WAKEUPENABLE_0,GPMC_AD15_WAKEUPENABLE_1" newline bitfld.long 0x3C 19. "GPMC_AD15_SLEWCONTROL,- FAST_SLEW" "GPMC_AD15_SLEWCONTROL_0,GPMC_AD15_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "GPMC_AD15_INPUTENABLE,- DISABLE" "GPMC_AD15_INPUTENABLE_0,GPMC_AD15_INPUTENABLE_1" newline bitfld.long 0x3C 17. "GPMC_AD15_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD15_PULLTYPESELECT_0,GPMC_AD15_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "GPMC_AD15_PULLUDENABLE,- ENABLE" "GPMC_AD15_PULLUDENABLE_0,GPMC_AD15_PULLUDENABLE_1" newline bitfld.long 0x3C 8. "GPMC_AD15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_AD15_MODESELECT_0,GPMC_AD15_MODESELECT_1" newline bitfld.long 0x3C 4.--7. "GPMC_AD15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 0.--3. "GPMC_AD15_MUXMODE,- GPMC_AD15" "GPMC_AD15_MUXMODE_0,?,GPMC_AD15_MUXMODE_2,GPMC_AD15_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD15_MUXMODE_14,GPMC_AD15_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_GPMC_A0," rbitfld.long 0x40 25. "GPMC_A0_WAKEUPEVENT,- NOWAKEUP" "GPMC_A0_WAKEUPEVENT_0,GPMC_A0_WAKEUPEVENT_1" newline bitfld.long 0x40 24. "GPMC_A0_WAKEUPENABLE,- DISABLE" "GPMC_A0_WAKEUPENABLE_0,GPMC_A0_WAKEUPENABLE_1" newline bitfld.long 0x40 19. "GPMC_A0_SLEWCONTROL,- FAST_SLEW" "GPMC_A0_SLEWCONTROL_0,GPMC_A0_SLEWCONTROL_1" newline bitfld.long 0x40 18. "GPMC_A0_INPUTENABLE,- DISABLE" "GPMC_A0_INPUTENABLE_0,GPMC_A0_INPUTENABLE_1" newline bitfld.long 0x40 17. "GPMC_A0_PULLTYPESELECT,- PULL_DOWN" "GPMC_A0_PULLTYPESELECT_0,GPMC_A0_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "GPMC_A0_PULLUDENABLE,- ENABLE" "GPMC_A0_PULLUDENABLE_0,GPMC_A0_PULLUDENABLE_1" newline bitfld.long 0x40 8. "GPMC_A0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A0_MODESELECT_0,GPMC_A0_MODESELECT_1" newline bitfld.long 0x40 4.--7. "GPMC_A0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 0.--3. "GPMC_A0_MUXMODE,- GPMC_A0" "GPMC_A0_MUXMODE_0,?,GPMC_A0_MUXMODE_2,GPMC_A0_MUXMODE_3,GPMC_A0_MUXMODE_4,?,GPMC_A0_MUXMODE_6,GPMC_A0_MUXMODE_7,GPMC_A0_MUXMODE_8,?,?,?,?,?,GPMC_A0_MUXMODE_14,GPMC_A0_MUXMODE_15" line.long 0x44 "CTRL_CORE_PAD_GPMC_A1," rbitfld.long 0x44 25. "GPMC_A1_WAKEUPEVENT,- NOWAKEUP" "GPMC_A1_WAKEUPEVENT_0,GPMC_A1_WAKEUPEVENT_1" newline bitfld.long 0x44 24. "GPMC_A1_WAKEUPENABLE,- DISABLE" "GPMC_A1_WAKEUPENABLE_0,GPMC_A1_WAKEUPENABLE_1" newline bitfld.long 0x44 19. "GPMC_A1_SLEWCONTROL,- FAST_SLEW" "GPMC_A1_SLEWCONTROL_0,GPMC_A1_SLEWCONTROL_1" newline bitfld.long 0x44 18. "GPMC_A1_INPUTENABLE,- DISABLE" "GPMC_A1_INPUTENABLE_0,GPMC_A1_INPUTENABLE_1" newline bitfld.long 0x44 17. "GPMC_A1_PULLTYPESELECT,- PULL_DOWN" "GPMC_A1_PULLTYPESELECT_0,GPMC_A1_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "GPMC_A1_PULLUDENABLE,- ENABLE" "GPMC_A1_PULLUDENABLE_0,GPMC_A1_PULLUDENABLE_1" newline bitfld.long 0x44 8. "GPMC_A1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A1_MODESELECT_0,GPMC_A1_MODESELECT_1" newline bitfld.long 0x44 4.--7. "GPMC_A1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x44 0.--3. "GPMC_A1_MUXMODE,- GPMC_A1" "GPMC_A1_MUXMODE_0,?,GPMC_A1_MUXMODE_2,GPMC_A1_MUXMODE_3,GPMC_A1_MUXMODE_4,?,GPMC_A1_MUXMODE_6,GPMC_A1_MUXMODE_7,GPMC_A1_MUXMODE_8,?,?,?,?,?,GPMC_A1_MUXMODE_14,GPMC_A1_MUXMODE_15" line.long 0x48 "CTRL_CORE_PAD_GPMC_A2," rbitfld.long 0x48 25. "GPMC_A2_WAKEUPEVENT,- NOWAKEUP" "GPMC_A2_WAKEUPEVENT_0,GPMC_A2_WAKEUPEVENT_1" newline bitfld.long 0x48 24. "GPMC_A2_WAKEUPENABLE,- DISABLE" "GPMC_A2_WAKEUPENABLE_0,GPMC_A2_WAKEUPENABLE_1" newline bitfld.long 0x48 19. "GPMC_A2_SLEWCONTROL,- FAST_SLEW" "GPMC_A2_SLEWCONTROL_0,GPMC_A2_SLEWCONTROL_1" newline bitfld.long 0x48 18. "GPMC_A2_INPUTENABLE,- DISABLE" "GPMC_A2_INPUTENABLE_0,GPMC_A2_INPUTENABLE_1" newline bitfld.long 0x48 17. "GPMC_A2_PULLTYPESELECT,- PULL_DOWN" "GPMC_A2_PULLTYPESELECT_0,GPMC_A2_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "GPMC_A2_PULLUDENABLE,- ENABLE" "GPMC_A2_PULLUDENABLE_0,GPMC_A2_PULLUDENABLE_1" newline bitfld.long 0x48 8. "GPMC_A2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A2_MODESELECT_0,GPMC_A2_MODESELECT_1" newline bitfld.long 0x48 4.--7. "GPMC_A2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x48 0.--3. "GPMC_A2_MUXMODE,- GPMC_A2" "GPMC_A2_MUXMODE_0,?,GPMC_A2_MUXMODE_2,GPMC_A2_MUXMODE_3,GPMC_A2_MUXMODE_4,?,GPMC_A2_MUXMODE_6,GPMC_A2_MUXMODE_7,GPMC_A2_MUXMODE_8,?,?,?,?,?,GPMC_A2_MUXMODE_14,GPMC_A2_MUXMODE_15" line.long 0x4C "CTRL_CORE_PAD_GPMC_A3," rbitfld.long 0x4C 25. "GPMC_A3_WAKEUPEVENT,- NOWAKEUP" "GPMC_A3_WAKEUPEVENT_0,GPMC_A3_WAKEUPEVENT_1" newline bitfld.long 0x4C 24. "GPMC_A3_WAKEUPENABLE,- DISABLE" "GPMC_A3_WAKEUPENABLE_0,GPMC_A3_WAKEUPENABLE_1" newline bitfld.long 0x4C 19. "GPMC_A3_SLEWCONTROL,- FAST_SLEW" "GPMC_A3_SLEWCONTROL_0,GPMC_A3_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "GPMC_A3_INPUTENABLE,- DISABLE" "GPMC_A3_INPUTENABLE_0,GPMC_A3_INPUTENABLE_1" newline bitfld.long 0x4C 17. "GPMC_A3_PULLTYPESELECT,- PULL_DOWN" "GPMC_A3_PULLTYPESELECT_0,GPMC_A3_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "GPMC_A3_PULLUDENABLE,- ENABLE" "GPMC_A3_PULLUDENABLE_0,GPMC_A3_PULLUDENABLE_1" newline bitfld.long 0x4C 8. "GPMC_A3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A3_MODESELECT_0,GPMC_A3_MODESELECT_1" newline bitfld.long 0x4C 4.--7. "GPMC_A3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x4C 0.--3. "GPMC_A3_MUXMODE,- GPMC_A3" "GPMC_A3_MUXMODE_0,GPMC_A3_MUXMODE_1,GPMC_A3_MUXMODE_2,GPMC_A3_MUXMODE_3,GPMC_A3_MUXMODE_4,?,GPMC_A3_MUXMODE_6,GPMC_A3_MUXMODE_7,GPMC_A3_MUXMODE_8,?,?,?,?,?,GPMC_A3_MUXMODE_14,GPMC_A3_MUXMODE_15" line.long 0x50 "CTRL_CORE_PAD_GPMC_A4," rbitfld.long 0x50 25. "GPMC_A4_WAKEUPEVENT,- NOWAKEUP" "GPMC_A4_WAKEUPEVENT_0,GPMC_A4_WAKEUPEVENT_1" newline bitfld.long 0x50 24. "GPMC_A4_WAKEUPENABLE,- DISABLE" "GPMC_A4_WAKEUPENABLE_0,GPMC_A4_WAKEUPENABLE_1" newline bitfld.long 0x50 19. "GPMC_A4_SLEWCONTROL,- FAST_SLEW" "GPMC_A4_SLEWCONTROL_0,GPMC_A4_SLEWCONTROL_1" newline bitfld.long 0x50 18. "GPMC_A4_INPUTENABLE,- DISABLE" "GPMC_A4_INPUTENABLE_0,GPMC_A4_INPUTENABLE_1" newline bitfld.long 0x50 17. "GPMC_A4_PULLTYPESELECT,- PULL_DOWN" "GPMC_A4_PULLTYPESELECT_0,GPMC_A4_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "GPMC_A4_PULLUDENABLE,- ENABLE" "GPMC_A4_PULLUDENABLE_0,GPMC_A4_PULLUDENABLE_1" newline bitfld.long 0x50 8. "GPMC_A4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A4_MODESELECT_0,GPMC_A4_MODESELECT_1" newline bitfld.long 0x50 4.--7. "GPMC_A4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x50 0.--3. "GPMC_A4_MUXMODE,- GPMC_A4" "GPMC_A4_MUXMODE_0,GPMC_A4_MUXMODE_1,GPMC_A4_MUXMODE_2,GPMC_A4_MUXMODE_3,GPMC_A4_MUXMODE_4,?,GPMC_A4_MUXMODE_6,GPMC_A4_MUXMODE_7,GPMC_A4_MUXMODE_8,?,?,?,?,?,GPMC_A4_MUXMODE_14,GPMC_A4_MUXMODE_15" line.long 0x54 "CTRL_CORE_PAD_GPMC_A5," rbitfld.long 0x54 25. "GPMC_A5_WAKEUPEVENT,- NOWAKEUP" "GPMC_A5_WAKEUPEVENT_0,GPMC_A5_WAKEUPEVENT_1" newline bitfld.long 0x54 24. "GPMC_A5_WAKEUPENABLE,- DISABLE" "GPMC_A5_WAKEUPENABLE_0,GPMC_A5_WAKEUPENABLE_1" newline bitfld.long 0x54 19. "GPMC_A5_SLEWCONTROL,- FAST_SLEW" "GPMC_A5_SLEWCONTROL_0,GPMC_A5_SLEWCONTROL_1" newline bitfld.long 0x54 18. "GPMC_A5_INPUTENABLE,- DISABLE" "GPMC_A5_INPUTENABLE_0,GPMC_A5_INPUTENABLE_1" newline bitfld.long 0x54 17. "GPMC_A5_PULLTYPESELECT,- PULL_DOWN" "GPMC_A5_PULLTYPESELECT_0,GPMC_A5_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "GPMC_A5_PULLUDENABLE,- ENABLE" "GPMC_A5_PULLUDENABLE_0,GPMC_A5_PULLUDENABLE_1" newline bitfld.long 0x54 8. "GPMC_A5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A5_MODESELECT_0,GPMC_A5_MODESELECT_1" newline bitfld.long 0x54 4.--7. "GPMC_A5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x54 0.--3. "GPMC_A5_MUXMODE,- GPMC_A5" "GPMC_A5_MUXMODE_0,?,GPMC_A5_MUXMODE_2,GPMC_A5_MUXMODE_3,GPMC_A5_MUXMODE_4,?,GPMC_A5_MUXMODE_6,GPMC_A5_MUXMODE_7,GPMC_A5_MUXMODE_8,?,?,?,?,?,GPMC_A5_MUXMODE_14,GPMC_A5_MUXMODE_15" line.long 0x58 "CTRL_CORE_PAD_GPMC_A6," rbitfld.long 0x58 25. "GPMC_A6_WAKEUPEVENT,- NOWAKEUP" "GPMC_A6_WAKEUPEVENT_0,GPMC_A6_WAKEUPEVENT_1" newline bitfld.long 0x58 24. "GPMC_A6_WAKEUPENABLE,- DISABLE" "GPMC_A6_WAKEUPENABLE_0,GPMC_A6_WAKEUPENABLE_1" newline bitfld.long 0x58 19. "GPMC_A6_SLEWCONTROL,- FAST_SLEW" "GPMC_A6_SLEWCONTROL_0,GPMC_A6_SLEWCONTROL_1" newline bitfld.long 0x58 18. "GPMC_A6_INPUTENABLE,- DISABLE" "GPMC_A6_INPUTENABLE_0,GPMC_A6_INPUTENABLE_1" newline bitfld.long 0x58 17. "GPMC_A6_PULLTYPESELECT,- PULL_DOWN" "GPMC_A6_PULLTYPESELECT_0,GPMC_A6_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "GPMC_A6_PULLUDENABLE,- ENABLE" "GPMC_A6_PULLUDENABLE_0,GPMC_A6_PULLUDENABLE_1" newline bitfld.long 0x58 8. "GPMC_A6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A6_MODESELECT_0,GPMC_A6_MODESELECT_1" newline bitfld.long 0x58 4.--7. "GPMC_A6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x58 0.--3. "GPMC_A6_MUXMODE,- GPMC_A6" "GPMC_A6_MUXMODE_0,?,GPMC_A6_MUXMODE_2,GPMC_A6_MUXMODE_3,GPMC_A6_MUXMODE_4,?,GPMC_A6_MUXMODE_6,GPMC_A6_MUXMODE_7,GPMC_A6_MUXMODE_8,?,?,?,?,?,GPMC_A6_MUXMODE_14,GPMC_A6_MUXMODE_15" line.long 0x5C "CTRL_CORE_PAD_GPMC_A7," rbitfld.long 0x5C 25. "GPMC_A7_WAKEUPEVENT,- NOWAKEUP" "GPMC_A7_WAKEUPEVENT_0,GPMC_A7_WAKEUPEVENT_1" newline bitfld.long 0x5C 24. "GPMC_A7_WAKEUPENABLE,- DISABLE" "GPMC_A7_WAKEUPENABLE_0,GPMC_A7_WAKEUPENABLE_1" newline bitfld.long 0x5C 19. "GPMC_A7_SLEWCONTROL,- FAST_SLEW" "GPMC_A7_SLEWCONTROL_0,GPMC_A7_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "GPMC_A7_INPUTENABLE,- DISABLE" "GPMC_A7_INPUTENABLE_0,GPMC_A7_INPUTENABLE_1" newline bitfld.long 0x5C 17. "GPMC_A7_PULLTYPESELECT,- PULL_DOWN" "GPMC_A7_PULLTYPESELECT_0,GPMC_A7_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "GPMC_A7_PULLUDENABLE,- ENABLE" "GPMC_A7_PULLUDENABLE_0,GPMC_A7_PULLUDENABLE_1" newline bitfld.long 0x5C 8. "GPMC_A7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A7_MODESELECT_0,GPMC_A7_MODESELECT_1" newline bitfld.long 0x5C 4.--7. "GPMC_A7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x5C 0.--3. "GPMC_A7_MUXMODE,- GPMC_A7" "GPMC_A7_MUXMODE_0,?,GPMC_A7_MUXMODE_2,GPMC_A7_MUXMODE_3,GPMC_A7_MUXMODE_4,?,GPMC_A7_MUXMODE_6,GPMC_A7_MUXMODE_7,GPMC_A7_MUXMODE_8,?,?,?,?,?,GPMC_A7_MUXMODE_14,GPMC_A7_MUXMODE_15" line.long 0x60 "CTRL_CORE_PAD_GPMC_A8," rbitfld.long 0x60 25. "GPMC_A8_WAKEUPEVENT,- NOWAKEUP" "GPMC_A8_WAKEUPEVENT_0,GPMC_A8_WAKEUPEVENT_1" newline bitfld.long 0x60 24. "GPMC_A8_WAKEUPENABLE,- DISABLE" "GPMC_A8_WAKEUPENABLE_0,GPMC_A8_WAKEUPENABLE_1" newline bitfld.long 0x60 19. "GPMC_A8_SLEWCONTROL,- FAST_SLEW" "GPMC_A8_SLEWCONTROL_0,GPMC_A8_SLEWCONTROL_1" newline bitfld.long 0x60 18. "GPMC_A8_INPUTENABLE,- DISABLE" "GPMC_A8_INPUTENABLE_0,GPMC_A8_INPUTENABLE_1" newline bitfld.long 0x60 17. "GPMC_A8_PULLTYPESELECT,- PULL_DOWN" "GPMC_A8_PULLTYPESELECT_0,GPMC_A8_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "GPMC_A8_PULLUDENABLE,- ENABLE" "GPMC_A8_PULLUDENABLE_0,GPMC_A8_PULLUDENABLE_1" newline bitfld.long 0x60 8. "GPMC_A8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A8_MODESELECT_0,GPMC_A8_MODESELECT_1" newline bitfld.long 0x60 4.--7. "GPMC_A8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x60 0.--3. "GPMC_A8_MUXMODE,- GPMC_A8" "GPMC_A8_MUXMODE_0,?,GPMC_A8_MUXMODE_2,GPMC_A8_MUXMODE_3,?,?,GPMC_A8_MUXMODE_6,GPMC_A8_MUXMODE_7,GPMC_A8_MUXMODE_8,?,?,?,?,?,GPMC_A8_MUXMODE_14,GPMC_A8_MUXMODE_15" line.long 0x64 "CTRL_CORE_PAD_GPMC_A9," rbitfld.long 0x64 25. "GPMC_A9_WAKEUPEVENT,- NOWAKEUP" "GPMC_A9_WAKEUPEVENT_0,GPMC_A9_WAKEUPEVENT_1" newline bitfld.long 0x64 24. "GPMC_A9_WAKEUPENABLE,- DISABLE" "GPMC_A9_WAKEUPENABLE_0,GPMC_A9_WAKEUPENABLE_1" newline bitfld.long 0x64 19. "GPMC_A9_SLEWCONTROL,- FAST_SLEW" "GPMC_A9_SLEWCONTROL_0,GPMC_A9_SLEWCONTROL_1" newline bitfld.long 0x64 18. "GPMC_A9_INPUTENABLE,- DISABLE" "GPMC_A9_INPUTENABLE_0,GPMC_A9_INPUTENABLE_1" newline bitfld.long 0x64 17. "GPMC_A9_PULLTYPESELECT,- PULL_DOWN" "GPMC_A9_PULLTYPESELECT_0,GPMC_A9_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "GPMC_A9_PULLUDENABLE,- ENABLE" "GPMC_A9_PULLUDENABLE_0,GPMC_A9_PULLUDENABLE_1" newline bitfld.long 0x64 8. "GPMC_A9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A9_MODESELECT_0,GPMC_A9_MODESELECT_1" newline bitfld.long 0x64 4.--7. "GPMC_A9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x64 0.--3. "GPMC_A9_MUXMODE,- GPMC_A9" "GPMC_A9_MUXMODE_0,?,GPMC_A9_MUXMODE_2,GPMC_A9_MUXMODE_3,?,?,GPMC_A9_MUXMODE_6,GPMC_A9_MUXMODE_7,GPMC_A9_MUXMODE_8,?,?,?,?,?,GPMC_A9_MUXMODE_14,GPMC_A9_MUXMODE_15" line.long 0x68 "CTRL_CORE_PAD_GPMC_A10," rbitfld.long 0x68 25. "GPMC_A10_WAKEUPEVENT,- NOWAKEUP" "GPMC_A10_WAKEUPEVENT_0,GPMC_A10_WAKEUPEVENT_1" newline bitfld.long 0x68 24. "GPMC_A10_WAKEUPENABLE,- DISABLE" "GPMC_A10_WAKEUPENABLE_0,GPMC_A10_WAKEUPENABLE_1" newline bitfld.long 0x68 19. "GPMC_A10_SLEWCONTROL,- FAST_SLEW" "GPMC_A10_SLEWCONTROL_0,GPMC_A10_SLEWCONTROL_1" newline bitfld.long 0x68 18. "GPMC_A10_INPUTENABLE,- DISABLE" "GPMC_A10_INPUTENABLE_0,GPMC_A10_INPUTENABLE_1" newline bitfld.long 0x68 17. "GPMC_A10_PULLTYPESELECT,- PULL_DOWN" "GPMC_A10_PULLTYPESELECT_0,GPMC_A10_PULLTYPESELECT_1" newline bitfld.long 0x68 16. "GPMC_A10_PULLUDENABLE,- ENABLE" "GPMC_A10_PULLUDENABLE_0,GPMC_A10_PULLUDENABLE_1" newline bitfld.long 0x68 8. "GPMC_A10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A10_MODESELECT_0,GPMC_A10_MODESELECT_1" newline bitfld.long 0x68 4.--7. "GPMC_A10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x68 0.--3. "GPMC_A10_MUXMODE,- GPMC_A10" "GPMC_A10_MUXMODE_0,?,GPMC_A10_MUXMODE_2,GPMC_A10_MUXMODE_3,?,?,GPMC_A10_MUXMODE_6,GPMC_A10_MUXMODE_7,GPMC_A10_MUXMODE_8,?,?,?,?,?,GPMC_A10_MUXMODE_14,GPMC_A10_MUXMODE_15" line.long 0x6C "CTRL_CORE_PAD_GPMC_A11," rbitfld.long 0x6C 25. "GPMC_A11_WAKEUPEVENT,- NOWAKEUP" "GPMC_A11_WAKEUPEVENT_0,GPMC_A11_WAKEUPEVENT_1" newline bitfld.long 0x6C 24. "GPMC_A11_WAKEUPENABLE,- DISABLE" "GPMC_A11_WAKEUPENABLE_0,GPMC_A11_WAKEUPENABLE_1" newline bitfld.long 0x6C 19. "GPMC_A11_SLEWCONTROL,- FAST_SLEW" "GPMC_A11_SLEWCONTROL_0,GPMC_A11_SLEWCONTROL_1" newline bitfld.long 0x6C 18. "GPMC_A11_INPUTENABLE,- DISABLE" "GPMC_A11_INPUTENABLE_0,GPMC_A11_INPUTENABLE_1" newline bitfld.long 0x6C 17. "GPMC_A11_PULLTYPESELECT,- PULL_DOWN" "GPMC_A11_PULLTYPESELECT_0,GPMC_A11_PULLTYPESELECT_1" newline bitfld.long 0x6C 16. "GPMC_A11_PULLUDENABLE,- ENABLE" "GPMC_A11_PULLUDENABLE_0,GPMC_A11_PULLUDENABLE_1" newline bitfld.long 0x6C 8. "GPMC_A11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A11_MODESELECT_0,GPMC_A11_MODESELECT_1" newline bitfld.long 0x6C 4.--7. "GPMC_A11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x6C 0.--3. "GPMC_A11_MUXMODE,- GPMC_A11" "GPMC_A11_MUXMODE_0,?,GPMC_A11_MUXMODE_2,GPMC_A11_MUXMODE_3,GPMC_A11_MUXMODE_4,?,GPMC_A11_MUXMODE_6,GPMC_A11_MUXMODE_7,GPMC_A11_MUXMODE_8,?,?,?,?,?,GPMC_A11_MUXMODE_14,GPMC_A11_MUXMODE_15" line.long 0x70 "CTRL_CORE_PAD_GPMC_A12," rbitfld.long 0x70 25. "GPMC_A12_WAKEUPEVENT,- NOWAKEUP" "GPMC_A12_WAKEUPEVENT_0,GPMC_A12_WAKEUPEVENT_1" newline bitfld.long 0x70 24. "GPMC_A12_WAKEUPENABLE,- DISABLE" "GPMC_A12_WAKEUPENABLE_0,GPMC_A12_WAKEUPENABLE_1" newline bitfld.long 0x70 19. "GPMC_A12_SLEWCONTROL,- FAST_SLEW" "GPMC_A12_SLEWCONTROL_0,GPMC_A12_SLEWCONTROL_1" newline bitfld.long 0x70 18. "GPMC_A12_INPUTENABLE,- DISABLE" "GPMC_A12_INPUTENABLE_0,GPMC_A12_INPUTENABLE_1" newline bitfld.long 0x70 17. "GPMC_A12_PULLTYPESELECT,- PULL_DOWN" "GPMC_A12_PULLTYPESELECT_0,GPMC_A12_PULLTYPESELECT_1" newline bitfld.long 0x70 16. "GPMC_A12_PULLUDENABLE,- ENABLE" "GPMC_A12_PULLUDENABLE_0,GPMC_A12_PULLUDENABLE_1" newline bitfld.long 0x70 8. "GPMC_A12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A12_MODESELECT_0,GPMC_A12_MODESELECT_1" newline bitfld.long 0x70 4.--7. "GPMC_A12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x70 0.--3. "GPMC_A12_MUXMODE,- GPMC_A12" "GPMC_A12_MUXMODE_0,?,?,?,GPMC_A12_MUXMODE_4,GPMC_A12_MUXMODE_5,GPMC_A12_MUXMODE_6,GPMC_A12_MUXMODE_7,GPMC_A12_MUXMODE_8,GPMC_A12_MUXMODE_9,?,?,?,?,GPMC_A12_MUXMODE_14,GPMC_A12_MUXMODE_15" line.long 0x74 "CTRL_CORE_PAD_GPMC_A13," rbitfld.long 0x74 25. "GPMC_A13_WAKEUPEVENT,- NOWAKEUP" "GPMC_A13_WAKEUPEVENT_0,GPMC_A13_WAKEUPEVENT_1" newline bitfld.long 0x74 24. "GPMC_A13_WAKEUPENABLE,- DISABLE" "GPMC_A13_WAKEUPENABLE_0,GPMC_A13_WAKEUPENABLE_1" newline bitfld.long 0x74 19. "GPMC_A13_SLEWCONTROL,- FAST_SLEW" "GPMC_A13_SLEWCONTROL_0,GPMC_A13_SLEWCONTROL_1" newline bitfld.long 0x74 18. "GPMC_A13_INPUTENABLE,- DISABLE" "GPMC_A13_INPUTENABLE_0,GPMC_A13_INPUTENABLE_1" newline bitfld.long 0x74 17. "GPMC_A13_PULLTYPESELECT,- PULL_DOWN" "GPMC_A13_PULLTYPESELECT_0,GPMC_A13_PULLTYPESELECT_1" newline bitfld.long 0x74 16. "GPMC_A13_PULLUDENABLE,- ENABLE" "GPMC_A13_PULLUDENABLE_0,GPMC_A13_PULLUDENABLE_1" newline bitfld.long 0x74 8. "GPMC_A13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A13_MODESELECT_0,GPMC_A13_MODESELECT_1" newline bitfld.long 0x74 4.--7. "GPMC_A13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x74 0.--3. "GPMC_A13_MUXMODE,- GPMC_A13" "GPMC_A13_MUXMODE_0,GPMC_A13_MUXMODE_1,?,?,GPMC_A13_MUXMODE_4,?,?,GPMC_A13_MUXMODE_7,GPMC_A13_MUXMODE_8,GPMC_A13_MUXMODE_9,?,?,?,?,GPMC_A13_MUXMODE_14,GPMC_A13_MUXMODE_15" line.long 0x78 "CTRL_CORE_PAD_GPMC_A14," rbitfld.long 0x78 25. "GPMC_A14_WAKEUPEVENT,- NOWAKEUP" "GPMC_A14_WAKEUPEVENT_0,GPMC_A14_WAKEUPEVENT_1" newline bitfld.long 0x78 24. "GPMC_A14_WAKEUPENABLE,- DISABLE" "GPMC_A14_WAKEUPENABLE_0,GPMC_A14_WAKEUPENABLE_1" newline bitfld.long 0x78 19. "GPMC_A14_SLEWCONTROL,- FAST_SLEW" "GPMC_A14_SLEWCONTROL_0,GPMC_A14_SLEWCONTROL_1" newline bitfld.long 0x78 18. "GPMC_A14_INPUTENABLE,- DISABLE" "GPMC_A14_INPUTENABLE_0,GPMC_A14_INPUTENABLE_1" newline bitfld.long 0x78 17. "GPMC_A14_PULLTYPESELECT,- PULL_DOWN" "GPMC_A14_PULLTYPESELECT_0,GPMC_A14_PULLTYPESELECT_1" newline bitfld.long 0x78 16. "GPMC_A14_PULLUDENABLE,- ENABLE" "GPMC_A14_PULLUDENABLE_0,GPMC_A14_PULLUDENABLE_1" newline bitfld.long 0x78 8. "GPMC_A14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A14_MODESELECT_0,GPMC_A14_MODESELECT_1" newline bitfld.long 0x78 4.--7. "GPMC_A14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x78 0.--3. "GPMC_A14_MUXMODE,- GPMC_A14" "GPMC_A14_MUXMODE_0,GPMC_A14_MUXMODE_1,?,?,GPMC_A14_MUXMODE_4,?,?,GPMC_A14_MUXMODE_7,GPMC_A14_MUXMODE_8,?,?,?,?,?,GPMC_A14_MUXMODE_14,GPMC_A14_MUXMODE_15" line.long 0x7C "CTRL_CORE_PAD_GPMC_A15," rbitfld.long 0x7C 25. "GPMC_A15_WAKEUPEVENT,- NOWAKEUP" "GPMC_A15_WAKEUPEVENT_0,GPMC_A15_WAKEUPEVENT_1" newline bitfld.long 0x7C 24. "GPMC_A15_WAKEUPENABLE,- DISABLE" "GPMC_A15_WAKEUPENABLE_0,GPMC_A15_WAKEUPENABLE_1" newline bitfld.long 0x7C 19. "GPMC_A15_SLEWCONTROL,- FAST_SLEW" "GPMC_A15_SLEWCONTROL_0,GPMC_A15_SLEWCONTROL_1" newline bitfld.long 0x7C 18. "GPMC_A15_INPUTENABLE,- DISABLE" "GPMC_A15_INPUTENABLE_0,GPMC_A15_INPUTENABLE_1" newline bitfld.long 0x7C 17. "GPMC_A15_PULLTYPESELECT,- PULL_DOWN" "GPMC_A15_PULLTYPESELECT_0,GPMC_A15_PULLTYPESELECT_1" newline bitfld.long 0x7C 16. "GPMC_A15_PULLUDENABLE,- ENABLE" "GPMC_A15_PULLUDENABLE_0,GPMC_A15_PULLUDENABLE_1" newline bitfld.long 0x7C 8. "GPMC_A15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A15_MODESELECT_0,GPMC_A15_MODESELECT_1" newline bitfld.long 0x7C 4.--7. "GPMC_A15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x7C 0.--3. "GPMC_A15_MUXMODE,- GPMC_A15" "GPMC_A15_MUXMODE_0,GPMC_A15_MUXMODE_1,?,?,GPMC_A15_MUXMODE_4,?,?,GPMC_A15_MUXMODE_7,?,?,?,?,?,?,GPMC_A15_MUXMODE_14,GPMC_A15_MUXMODE_15" line.long 0x80 "CTRL_CORE_PAD_GPMC_A16," rbitfld.long 0x80 25. "GPMC_A16_WAKEUPEVENT,- NOWAKEUP" "GPMC_A16_WAKEUPEVENT_0,GPMC_A16_WAKEUPEVENT_1" newline bitfld.long 0x80 24. "GPMC_A16_WAKEUPENABLE,- DISABLE" "GPMC_A16_WAKEUPENABLE_0,GPMC_A16_WAKEUPENABLE_1" newline bitfld.long 0x80 19. "GPMC_A16_SLEWCONTROL,- FAST_SLEW" "GPMC_A16_SLEWCONTROL_0,GPMC_A16_SLEWCONTROL_1" newline bitfld.long 0x80 18. "GPMC_A16_INPUTENABLE,- DISABLE" "GPMC_A16_INPUTENABLE_0,GPMC_A16_INPUTENABLE_1" newline bitfld.long 0x80 17. "GPMC_A16_PULLTYPESELECT,- PULL_DOWN" "GPMC_A16_PULLTYPESELECT_0,GPMC_A16_PULLTYPESELECT_1" newline bitfld.long 0x80 16. "GPMC_A16_PULLUDENABLE,- ENABLE" "GPMC_A16_PULLUDENABLE_0,GPMC_A16_PULLUDENABLE_1" newline bitfld.long 0x80 8. "GPMC_A16_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A16_MODESELECT_0,GPMC_A16_MODESELECT_1" newline bitfld.long 0x80 4.--7. "GPMC_A16_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x80 0.--3. "GPMC_A16_MUXMODE,- GPMC_A16" "GPMC_A16_MUXMODE_0,GPMC_A16_MUXMODE_1,?,?,GPMC_A16_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A16_MUXMODE_14,GPMC_A16_MUXMODE_15" line.long 0x84 "CTRL_CORE_PAD_GPMC_A17," rbitfld.long 0x84 25. "GPMC_A17_WAKEUPEVENT,- NOWAKEUP" "GPMC_A17_WAKEUPEVENT_0,GPMC_A17_WAKEUPEVENT_1" newline bitfld.long 0x84 24. "GPMC_A17_WAKEUPENABLE,- DISABLE" "GPMC_A17_WAKEUPENABLE_0,GPMC_A17_WAKEUPENABLE_1" newline bitfld.long 0x84 19. "GPMC_A17_SLEWCONTROL,- FAST_SLEW" "GPMC_A17_SLEWCONTROL_0,GPMC_A17_SLEWCONTROL_1" newline bitfld.long 0x84 18. "GPMC_A17_INPUTENABLE,- DISABLE" "GPMC_A17_INPUTENABLE_0,GPMC_A17_INPUTENABLE_1" newline bitfld.long 0x84 17. "GPMC_A17_PULLTYPESELECT,- PULL_DOWN" "GPMC_A17_PULLTYPESELECT_0,GPMC_A17_PULLTYPESELECT_1" newline bitfld.long 0x84 16. "GPMC_A17_PULLUDENABLE,- ENABLE" "GPMC_A17_PULLUDENABLE_0,GPMC_A17_PULLUDENABLE_1" newline bitfld.long 0x84 8. "GPMC_A17_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A17_MODESELECT_0,GPMC_A17_MODESELECT_1" newline bitfld.long 0x84 4.--7. "GPMC_A17_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x84 0.--3. "GPMC_A17_MUXMODE,- GPMC_A17" "GPMC_A17_MUXMODE_0,GPMC_A17_MUXMODE_1,?,?,GPMC_A17_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A17_MUXMODE_14,GPMC_A17_MUXMODE_15" line.long 0x88 "CTRL_CORE_PAD_GPMC_A18," rbitfld.long 0x88 25. "GPMC_A18_WAKEUPEVENT,- NOWAKEUP" "GPMC_A18_WAKEUPEVENT_0,GPMC_A18_WAKEUPEVENT_1" newline bitfld.long 0x88 24. "GPMC_A18_WAKEUPENABLE,- DISABLE" "GPMC_A18_WAKEUPENABLE_0,GPMC_A18_WAKEUPENABLE_1" newline bitfld.long 0x88 19. "GPMC_A18_SLEWCONTROL,- FAST_SLEW" "GPMC_A18_SLEWCONTROL_0,GPMC_A18_SLEWCONTROL_1" newline bitfld.long 0x88 18. "GPMC_A18_INPUTENABLE,- DISABLE" "GPMC_A18_INPUTENABLE_0,GPMC_A18_INPUTENABLE_1" newline bitfld.long 0x88 17. "GPMC_A18_PULLTYPESELECT,- PULL_DOWN" "GPMC_A18_PULLTYPESELECT_0,GPMC_A18_PULLTYPESELECT_1" newline bitfld.long 0x88 16. "GPMC_A18_PULLUDENABLE,- ENABLE" "GPMC_A18_PULLUDENABLE_0,GPMC_A18_PULLUDENABLE_1" newline bitfld.long 0x88 8. "GPMC_A18_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A18_MODESELECT_0,GPMC_A18_MODESELECT_1" newline bitfld.long 0x88 4.--7. "GPMC_A18_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x88 0.--3. "GPMC_A18_MUXMODE,- GPMC_A18" "GPMC_A18_MUXMODE_0,GPMC_A18_MUXMODE_1,?,?,GPMC_A18_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A18_MUXMODE_14,GPMC_A18_MUXMODE_15" line.long 0x8C "CTRL_CORE_PAD_GPMC_A19," rbitfld.long 0x8C 25. "GPMC_A19_WAKEUPEVENT,- NOWAKEUP" "GPMC_A19_WAKEUPEVENT_0,GPMC_A19_WAKEUPEVENT_1" newline bitfld.long 0x8C 24. "GPMC_A19_WAKEUPENABLE,- DISABLE" "GPMC_A19_WAKEUPENABLE_0,GPMC_A19_WAKEUPENABLE_1" newline bitfld.long 0x8C 19. "GPMC_A19_SLEWCONTROL,- FAST_SLEW" "GPMC_A19_SLEWCONTROL_0,GPMC_A19_SLEWCONTROL_1" newline bitfld.long 0x8C 18. "GPMC_A19_INPUTENABLE,- DISABLE" "GPMC_A19_INPUTENABLE_0,GPMC_A19_INPUTENABLE_1" newline bitfld.long 0x8C 17. "GPMC_A19_PULLTYPESELECT,- PULL_DOWN" "GPMC_A19_PULLTYPESELECT_0,GPMC_A19_PULLTYPESELECT_1" newline bitfld.long 0x8C 16. "GPMC_A19_PULLUDENABLE,- ENABLE" "GPMC_A19_PULLUDENABLE_0,GPMC_A19_PULLUDENABLE_1" newline bitfld.long 0x8C 8. "GPMC_A19_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A19_MODESELECT_0,GPMC_A19_MODESELECT_1" newline bitfld.long 0x8C 4.--7. "GPMC_A19_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x8C 0.--3. "GPMC_A19_MUXMODE,- GPMC_A19" "GPMC_A19_MUXMODE_0,GPMC_A19_MUXMODE_1,GPMC_A19_MUXMODE_2,?,GPMC_A19_MUXMODE_4,?,GPMC_A19_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A19_MUXMODE_14,GPMC_A19_MUXMODE_15" line.long 0x90 "CTRL_CORE_PAD_GPMC_A20," rbitfld.long 0x90 25. "GPMC_A20_WAKEUPEVENT,- NOWAKEUP" "GPMC_A20_WAKEUPEVENT_0,GPMC_A20_WAKEUPEVENT_1" newline bitfld.long 0x90 24. "GPMC_A20_WAKEUPENABLE,- DISABLE" "GPMC_A20_WAKEUPENABLE_0,GPMC_A20_WAKEUPENABLE_1" newline bitfld.long 0x90 19. "GPMC_A20_SLEWCONTROL,- FAST_SLEW" "GPMC_A20_SLEWCONTROL_0,GPMC_A20_SLEWCONTROL_1" newline bitfld.long 0x90 18. "GPMC_A20_INPUTENABLE,- DISABLE" "GPMC_A20_INPUTENABLE_0,GPMC_A20_INPUTENABLE_1" newline bitfld.long 0x90 17. "GPMC_A20_PULLTYPESELECT,- PULL_DOWN" "GPMC_A20_PULLTYPESELECT_0,GPMC_A20_PULLTYPESELECT_1" newline bitfld.long 0x90 16. "GPMC_A20_PULLUDENABLE,- ENABLE" "GPMC_A20_PULLUDENABLE_0,GPMC_A20_PULLUDENABLE_1" newline bitfld.long 0x90 8. "GPMC_A20_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A20_MODESELECT_0,GPMC_A20_MODESELECT_1" newline bitfld.long 0x90 4.--7. "GPMC_A20_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x90 0.--3. "GPMC_A20_MUXMODE,- GPMC_A20" "GPMC_A20_MUXMODE_0,GPMC_A20_MUXMODE_1,GPMC_A20_MUXMODE_2,?,GPMC_A20_MUXMODE_4,?,GPMC_A20_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A20_MUXMODE_14,GPMC_A20_MUXMODE_15" line.long 0x94 "CTRL_CORE_PAD_GPMC_A21," rbitfld.long 0x94 25. "GPMC_A21_WAKEUPEVENT,- NOWAKEUP" "GPMC_A21_WAKEUPEVENT_0,GPMC_A21_WAKEUPEVENT_1" newline bitfld.long 0x94 24. "GPMC_A21_WAKEUPENABLE,- DISABLE" "GPMC_A21_WAKEUPENABLE_0,GPMC_A21_WAKEUPENABLE_1" newline bitfld.long 0x94 19. "GPMC_A21_SLEWCONTROL,- FAST_SLEW" "GPMC_A21_SLEWCONTROL_0,GPMC_A21_SLEWCONTROL_1" newline bitfld.long 0x94 18. "GPMC_A21_INPUTENABLE,- DISABLE" "GPMC_A21_INPUTENABLE_0,GPMC_A21_INPUTENABLE_1" newline bitfld.long 0x94 17. "GPMC_A21_PULLTYPESELECT,- PULL_DOWN" "GPMC_A21_PULLTYPESELECT_0,GPMC_A21_PULLTYPESELECT_1" newline bitfld.long 0x94 16. "GPMC_A21_PULLUDENABLE,- ENABLE" "GPMC_A21_PULLUDENABLE_0,GPMC_A21_PULLUDENABLE_1" newline bitfld.long 0x94 8. "GPMC_A21_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A21_MODESELECT_0,GPMC_A21_MODESELECT_1" newline bitfld.long 0x94 4.--7. "GPMC_A21_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x94 0.--3. "GPMC_A21_MUXMODE,- GPMC_A21" "GPMC_A21_MUXMODE_0,GPMC_A21_MUXMODE_1,GPMC_A21_MUXMODE_2,?,GPMC_A21_MUXMODE_4,?,GPMC_A21_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A21_MUXMODE_14,GPMC_A21_MUXMODE_15" line.long 0x98 "CTRL_CORE_PAD_GPMC_A22," rbitfld.long 0x98 25. "GPMC_A22_WAKEUPEVENT,- NOWAKEUP" "GPMC_A22_WAKEUPEVENT_0,GPMC_A22_WAKEUPEVENT_1" newline bitfld.long 0x98 24. "GPMC_A22_WAKEUPENABLE,- DISABLE" "GPMC_A22_WAKEUPENABLE_0,GPMC_A22_WAKEUPENABLE_1" newline bitfld.long 0x98 19. "GPMC_A22_SLEWCONTROL,- FAST_SLEW" "GPMC_A22_SLEWCONTROL_0,GPMC_A22_SLEWCONTROL_1" newline bitfld.long 0x98 18. "GPMC_A22_INPUTENABLE,- DISABLE" "GPMC_A22_INPUTENABLE_0,GPMC_A22_INPUTENABLE_1" newline bitfld.long 0x98 17. "GPMC_A22_PULLTYPESELECT,- PULL_DOWN" "GPMC_A22_PULLTYPESELECT_0,GPMC_A22_PULLTYPESELECT_1" newline bitfld.long 0x98 16. "GPMC_A22_PULLUDENABLE,- ENABLE" "GPMC_A22_PULLUDENABLE_0,GPMC_A22_PULLUDENABLE_1" newline bitfld.long 0x98 8. "GPMC_A22_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A22_MODESELECT_0,GPMC_A22_MODESELECT_1" newline bitfld.long 0x98 4.--7. "GPMC_A22_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x98 0.--3. "GPMC_A22_MUXMODE,- GPMC_A22" "GPMC_A22_MUXMODE_0,GPMC_A22_MUXMODE_1,GPMC_A22_MUXMODE_2,?,GPMC_A22_MUXMODE_4,?,GPMC_A22_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A22_MUXMODE_14,GPMC_A22_MUXMODE_15" line.long 0x9C "CTRL_CORE_PAD_GPMC_A23," rbitfld.long 0x9C 25. "GPMC_A23_WAKEUPEVENT,- NOWAKEUP" "GPMC_A23_WAKEUPEVENT_0,GPMC_A23_WAKEUPEVENT_1" newline bitfld.long 0x9C 24. "GPMC_A23_WAKEUPENABLE,- DISABLE" "GPMC_A23_WAKEUPENABLE_0,GPMC_A23_WAKEUPENABLE_1" newline bitfld.long 0x9C 19. "GPMC_A23_SLEWCONTROL,- FAST_SLEW" "GPMC_A23_SLEWCONTROL_0,GPMC_A23_SLEWCONTROL_1" newline bitfld.long 0x9C 18. "GPMC_A23_INPUTENABLE,- DISABLE" "GPMC_A23_INPUTENABLE_0,GPMC_A23_INPUTENABLE_1" newline bitfld.long 0x9C 17. "GPMC_A23_PULLTYPESELECT,- PULL_DOWN" "GPMC_A23_PULLTYPESELECT_0,GPMC_A23_PULLTYPESELECT_1" newline bitfld.long 0x9C 16. "GPMC_A23_PULLUDENABLE,- ENABLE" "GPMC_A23_PULLUDENABLE_0,GPMC_A23_PULLUDENABLE_1" newline bitfld.long 0x9C 8. "GPMC_A23_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A23_MODESELECT_0,GPMC_A23_MODESELECT_1" newline bitfld.long 0x9C 4.--7. "GPMC_A23_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x9C 0.--3. "GPMC_A23_MUXMODE,- GPMC_A23" "GPMC_A23_MUXMODE_0,GPMC_A23_MUXMODE_1,GPMC_A23_MUXMODE_2,?,GPMC_A23_MUXMODE_4,?,GPMC_A23_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A23_MUXMODE_14,GPMC_A23_MUXMODE_15" line.long 0xA0 "CTRL_CORE_PAD_GPMC_A24," rbitfld.long 0xA0 25. "GPMC_A24_WAKEUPEVENT,- NOWAKEUP" "GPMC_A24_WAKEUPEVENT_0,GPMC_A24_WAKEUPEVENT_1" newline bitfld.long 0xA0 24. "GPMC_A24_WAKEUPENABLE,- DISABLE" "GPMC_A24_WAKEUPENABLE_0,GPMC_A24_WAKEUPENABLE_1" newline bitfld.long 0xA0 19. "GPMC_A24_SLEWCONTROL,- FAST_SLEW" "GPMC_A24_SLEWCONTROL_0,GPMC_A24_SLEWCONTROL_1" newline bitfld.long 0xA0 18. "GPMC_A24_INPUTENABLE,- DISABLE" "GPMC_A24_INPUTENABLE_0,GPMC_A24_INPUTENABLE_1" newline bitfld.long 0xA0 17. "GPMC_A24_PULLTYPESELECT,- PULL_DOWN" "GPMC_A24_PULLTYPESELECT_0,GPMC_A24_PULLTYPESELECT_1" newline bitfld.long 0xA0 16. "GPMC_A24_PULLUDENABLE,- ENABLE" "GPMC_A24_PULLUDENABLE_0,GPMC_A24_PULLUDENABLE_1" newline bitfld.long 0xA0 8. "GPMC_A24_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A24_MODESELECT_0,GPMC_A24_MODESELECT_1" newline bitfld.long 0xA0 4.--7. "GPMC_A24_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA0 0.--3. "GPMC_A24_MUXMODE,- GPMC_A24" "GPMC_A24_MUXMODE_0,GPMC_A24_MUXMODE_1,GPMC_A24_MUXMODE_2,?,?,?,GPMC_A24_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A24_MUXMODE_14,GPMC_A24_MUXMODE_15" line.long 0xA4 "CTRL_CORE_PAD_GPMC_A25," rbitfld.long 0xA4 25. "GPMC_A25_WAKEUPEVENT,- NOWAKEUP" "GPMC_A25_WAKEUPEVENT_0,GPMC_A25_WAKEUPEVENT_1" newline bitfld.long 0xA4 24. "GPMC_A25_WAKEUPENABLE,- DISABLE" "GPMC_A25_WAKEUPENABLE_0,GPMC_A25_WAKEUPENABLE_1" newline bitfld.long 0xA4 19. "GPMC_A25_SLEWCONTROL,- FAST_SLEW" "GPMC_A25_SLEWCONTROL_0,GPMC_A25_SLEWCONTROL_1" newline bitfld.long 0xA4 18. "GPMC_A25_INPUTENABLE,- DISABLE" "GPMC_A25_INPUTENABLE_0,GPMC_A25_INPUTENABLE_1" newline bitfld.long 0xA4 17. "GPMC_A25_PULLTYPESELECT,- PULL_DOWN" "GPMC_A25_PULLTYPESELECT_0,GPMC_A25_PULLTYPESELECT_1" newline bitfld.long 0xA4 16. "GPMC_A25_PULLUDENABLE,- ENABLE" "GPMC_A25_PULLUDENABLE_0,GPMC_A25_PULLUDENABLE_1" newline bitfld.long 0xA4 8. "GPMC_A25_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A25_MODESELECT_0,GPMC_A25_MODESELECT_1" newline bitfld.long 0xA4 4.--7. "GPMC_A25_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA4 0.--3. "GPMC_A25_MUXMODE,- GPMC_A25" "GPMC_A25_MUXMODE_0,GPMC_A25_MUXMODE_1,GPMC_A25_MUXMODE_2,?,?,?,GPMC_A25_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A25_MUXMODE_14,GPMC_A25_MUXMODE_15" line.long 0xA8 "CTRL_CORE_PAD_GPMC_A26," rbitfld.long 0xA8 25. "GPMC_A26_WAKEUPEVENT,- NOWAKEUP" "GPMC_A26_WAKEUPEVENT_0,GPMC_A26_WAKEUPEVENT_1" newline bitfld.long 0xA8 24. "GPMC_A26_WAKEUPENABLE,- DISABLE" "GPMC_A26_WAKEUPENABLE_0,GPMC_A26_WAKEUPENABLE_1" newline bitfld.long 0xA8 19. "GPMC_A26_SLEWCONTROL,- FAST_SLEW" "GPMC_A26_SLEWCONTROL_0,GPMC_A26_SLEWCONTROL_1" newline bitfld.long 0xA8 18. "GPMC_A26_INPUTENABLE,- DISABLE" "GPMC_A26_INPUTENABLE_0,GPMC_A26_INPUTENABLE_1" newline bitfld.long 0xA8 17. "GPMC_A26_PULLTYPESELECT,- PULL_DOWN" "GPMC_A26_PULLTYPESELECT_0,GPMC_A26_PULLTYPESELECT_1" newline bitfld.long 0xA8 16. "GPMC_A26_PULLUDENABLE,- ENABLE" "GPMC_A26_PULLUDENABLE_0,GPMC_A26_PULLUDENABLE_1" newline bitfld.long 0xA8 8. "GPMC_A26_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A26_MODESELECT_0,GPMC_A26_MODESELECT_1" newline bitfld.long 0xA8 4.--7. "GPMC_A26_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA8 0.--3. "GPMC_A26_MUXMODE,- GPMC_A26" "GPMC_A26_MUXMODE_0,GPMC_A26_MUXMODE_1,GPMC_A26_MUXMODE_2,?,?,?,GPMC_A26_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A26_MUXMODE_14,GPMC_A26_MUXMODE_15" line.long 0xAC "CTRL_CORE_PAD_GPMC_A27," rbitfld.long 0xAC 25. "GPMC_A27_WAKEUPEVENT,- NOWAKEUP" "GPMC_A27_WAKEUPEVENT_0,GPMC_A27_WAKEUPEVENT_1" newline bitfld.long 0xAC 24. "GPMC_A27_WAKEUPENABLE,- DISABLE" "GPMC_A27_WAKEUPENABLE_0,GPMC_A27_WAKEUPENABLE_1" newline bitfld.long 0xAC 19. "GPMC_A27_SLEWCONTROL,- FAST_SLEW" "GPMC_A27_SLEWCONTROL_0,GPMC_A27_SLEWCONTROL_1" newline bitfld.long 0xAC 18. "GPMC_A27_INPUTENABLE,- DISABLE" "GPMC_A27_INPUTENABLE_0,GPMC_A27_INPUTENABLE_1" newline bitfld.long 0xAC 17. "GPMC_A27_PULLTYPESELECT,- PULL_DOWN" "GPMC_A27_PULLTYPESELECT_0,GPMC_A27_PULLTYPESELECT_1" newline bitfld.long 0xAC 16. "GPMC_A27_PULLUDENABLE,- ENABLE" "GPMC_A27_PULLUDENABLE_0,GPMC_A27_PULLUDENABLE_1" newline bitfld.long 0xAC 8. "GPMC_A27_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_A27_MODESELECT_0,GPMC_A27_MODESELECT_1" newline bitfld.long 0xAC 4.--7. "GPMC_A27_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xAC 0.--3. "GPMC_A27_MUXMODE,- GPMC_A27" "GPMC_A27_MUXMODE_0,GPMC_A27_MUXMODE_1,GPMC_A27_MUXMODE_2,?,?,?,GPMC_A27_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A27_MUXMODE_14,GPMC_A27_MUXMODE_15" line.long 0xB0 "CTRL_CORE_PAD_GPMC_CS1," rbitfld.long 0xB0 25. "GPMC_CS1_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS1_WAKEUPEVENT_0,GPMC_CS1_WAKEUPEVENT_1" newline bitfld.long 0xB0 24. "GPMC_CS1_WAKEUPENABLE,- DISABLE" "GPMC_CS1_WAKEUPENABLE_0,GPMC_CS1_WAKEUPENABLE_1" newline bitfld.long 0xB0 19. "GPMC_CS1_SLEWCONTROL,- FAST_SLEW" "GPMC_CS1_SLEWCONTROL_0,GPMC_CS1_SLEWCONTROL_1" newline bitfld.long 0xB0 18. "GPMC_CS1_INPUTENABLE,- DISABLE" "GPMC_CS1_INPUTENABLE_0,GPMC_CS1_INPUTENABLE_1" newline bitfld.long 0xB0 17. "GPMC_CS1_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS1_PULLTYPESELECT_0,GPMC_CS1_PULLTYPESELECT_1" newline bitfld.long 0xB0 16. "GPMC_CS1_PULLUDENABLE,- ENABLE" "GPMC_CS1_PULLUDENABLE_0,GPMC_CS1_PULLUDENABLE_1" newline bitfld.long 0xB0 8. "GPMC_CS1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_CS1_MODESELECT_0,GPMC_CS1_MODESELECT_1" newline bitfld.long 0xB0 4.--7. "GPMC_CS1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB0 0.--3. "GPMC_CS1_MUXMODE,- GPMC_CS1" "GPMC_CS1_MUXMODE_0,GPMC_CS1_MUXMODE_1,GPMC_CS1_MUXMODE_2,?,GPMC_CS1_MUXMODE_4,?,GPMC_CS1_MUXMODE_6,?,?,?,?,?,?,?,GPMC_CS1_MUXMODE_14,GPMC_CS1_MUXMODE_15" line.long 0xB4 "CTRL_CORE_PAD_GPMC_CS0," rbitfld.long 0xB4 25. "GPMC_CS0_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS0_WAKEUPEVENT_0,GPMC_CS0_WAKEUPEVENT_1" newline bitfld.long 0xB4 24. "GPMC_CS0_WAKEUPENABLE,- DISABLE" "GPMC_CS0_WAKEUPENABLE_0,GPMC_CS0_WAKEUPENABLE_1" newline bitfld.long 0xB4 19. "GPMC_CS0_SLEWCONTROL,- FAST_SLEW" "GPMC_CS0_SLEWCONTROL_0,GPMC_CS0_SLEWCONTROL_1" newline bitfld.long 0xB4 18. "GPMC_CS0_INPUTENABLE,- DISABLE" "GPMC_CS0_INPUTENABLE_0,GPMC_CS0_INPUTENABLE_1" newline bitfld.long 0xB4 17. "GPMC_CS0_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS0_PULLTYPESELECT_0,GPMC_CS0_PULLTYPESELECT_1" newline bitfld.long 0xB4 16. "GPMC_CS0_PULLUDENABLE,- ENABLE" "GPMC_CS0_PULLUDENABLE_0,GPMC_CS0_PULLUDENABLE_1" newline bitfld.long 0xB4 8. "GPMC_CS0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_CS0_MODESELECT_0,GPMC_CS0_MODESELECT_1" newline bitfld.long 0xB4 4.--7. "GPMC_CS0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB4 0.--3. "GPMC_CS0_MUXMODE,- GPMC_CS0" "GPMC_CS0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS0_MUXMODE_14,GPMC_CS0_MUXMODE_15" line.long 0xB8 "CTRL_CORE_PAD_GPMC_CS2," rbitfld.long 0xB8 25. "GPMC_CS2_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS2_WAKEUPEVENT_0,GPMC_CS2_WAKEUPEVENT_1" newline bitfld.long 0xB8 24. "GPMC_CS2_WAKEUPENABLE,- DISABLE" "GPMC_CS2_WAKEUPENABLE_0,GPMC_CS2_WAKEUPENABLE_1" newline bitfld.long 0xB8 19. "GPMC_CS2_SLEWCONTROL,- FAST_SLEW" "GPMC_CS2_SLEWCONTROL_0,GPMC_CS2_SLEWCONTROL_1" newline bitfld.long 0xB8 18. "GPMC_CS2_INPUTENABLE,- DISABLE" "GPMC_CS2_INPUTENABLE_0,GPMC_CS2_INPUTENABLE_1" newline bitfld.long 0xB8 17. "GPMC_CS2_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS2_PULLTYPESELECT_0,GPMC_CS2_PULLTYPESELECT_1" newline bitfld.long 0xB8 16. "GPMC_CS2_PULLUDENABLE,- ENABLE" "GPMC_CS2_PULLUDENABLE_0,GPMC_CS2_PULLUDENABLE_1" newline bitfld.long 0xB8 8. "GPMC_CS2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_CS2_MODESELECT_0,GPMC_CS2_MODESELECT_1" newline bitfld.long 0xB8 4.--7. "GPMC_CS2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB8 0.--3. "GPMC_CS2_MUXMODE,- GPMC_CS2" "GPMC_CS2_MUXMODE_0,GPMC_CS2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS2_MUXMODE_14,GPMC_CS2_MUXMODE_15" line.long 0xBC "CTRL_CORE_PAD_GPMC_CS3," rbitfld.long 0xBC 25. "GPMC_CS3_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS3_WAKEUPEVENT_0,GPMC_CS3_WAKEUPEVENT_1" newline bitfld.long 0xBC 24. "GPMC_CS3_WAKEUPENABLE,- DISABLE" "GPMC_CS3_WAKEUPENABLE_0,GPMC_CS3_WAKEUPENABLE_1" newline bitfld.long 0xBC 19. "GPMC_CS3_SLEWCONTROL,- FAST_SLEW" "GPMC_CS3_SLEWCONTROL_0,GPMC_CS3_SLEWCONTROL_1" newline bitfld.long 0xBC 18. "GPMC_CS3_INPUTENABLE,- DISABLE" "GPMC_CS3_INPUTENABLE_0,GPMC_CS3_INPUTENABLE_1" newline bitfld.long 0xBC 17. "GPMC_CS3_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS3_PULLTYPESELECT_0,GPMC_CS3_PULLTYPESELECT_1" newline bitfld.long 0xBC 16. "GPMC_CS3_PULLUDENABLE,- ENABLE" "GPMC_CS3_PULLUDENABLE_0,GPMC_CS3_PULLUDENABLE_1" newline bitfld.long 0xBC 8. "GPMC_CS3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_CS3_MODESELECT_0,GPMC_CS3_MODESELECT_1" newline bitfld.long 0xBC 4.--7. "GPMC_CS3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xBC 0.--3. "GPMC_CS3_MUXMODE,- GPMC_CS3" "GPMC_CS3_MUXMODE_0,GPMC_CS3_MUXMODE_1,GPMC_CS3_MUXMODE_2,GPMC_CS3_MUXMODE_3,?,GPMC_CS3_MUXMODE_5,?,?,?,?,?,?,?,?,GPMC_CS3_MUXMODE_14,GPMC_CS3_MUXMODE_15" line.long 0xC0 "CTRL_CORE_PAD_GPMC_CLK," rbitfld.long 0xC0 25. "GPMC_CLK_WAKEUPEVENT,- NOWAKEUP" "GPMC_CLK_WAKEUPEVENT_0,GPMC_CLK_WAKEUPEVENT_1" newline bitfld.long 0xC0 24. "GPMC_CLK_WAKEUPENABLE,- DISABLE" "GPMC_CLK_WAKEUPENABLE_0,GPMC_CLK_WAKEUPENABLE_1" newline bitfld.long 0xC0 19. "GPMC_CLK_SLEWCONTROL,- FAST_SLEW" "GPMC_CLK_SLEWCONTROL_0,GPMC_CLK_SLEWCONTROL_1" newline bitfld.long 0xC0 18. "GPMC_CLK_INPUTENABLE,- DISABLE" "GPMC_CLK_INPUTENABLE_0,GPMC_CLK_INPUTENABLE_1" newline bitfld.long 0xC0 17. "GPMC_CLK_PULLTYPESELECT,- PULL_DOWN" "GPMC_CLK_PULLTYPESELECT_0,GPMC_CLK_PULLTYPESELECT_1" newline bitfld.long 0xC0 16. "GPMC_CLK_PULLUDENABLE,- ENABLE" "GPMC_CLK_PULLUDENABLE_0,GPMC_CLK_PULLUDENABLE_1" newline bitfld.long 0xC0 8. "GPMC_CLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_CLK_MODESELECT_0,GPMC_CLK_MODESELECT_1" newline bitfld.long 0xC0 4.--7. "GPMC_CLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC0 0.--3. "GPMC_CLK_MUXMODE,- GPMC_CLK" "GPMC_CLK_MUXMODE_0,GPMC_CLK_MUXMODE_1,GPMC_CLK_MUXMODE_2,GPMC_CLK_MUXMODE_3,GPMC_CLK_MUXMODE_4,GPMC_CLK_MUXMODE_5,GPMC_CLK_MUXMODE_6,GPMC_CLK_MUXMODE_7,GPMC_CLK_MUXMODE_8,GPMC_CLK_MUXMODE_9,?,?,?,?,GPMC_CLK_MUXMODE_14,GPMC_CLK_MUXMODE_15" line.long 0xC4 "CTRL_CORE_PAD_GPMC_ADVN_ALE," rbitfld.long 0xC4 25. "GPMC_ADVN_ALE_WAKEUPEVENT,- NOWAKEUP" "GPMC_ADVN_ALE_WAKEUPEVENT_0,GPMC_ADVN_ALE_WAKEUPEVENT_1" newline bitfld.long 0xC4 24. "GPMC_ADVN_ALE_WAKEUPENABLE,- DISABLE" "GPMC_ADVN_ALE_WAKEUPENABLE_0,GPMC_ADVN_ALE_WAKEUPENABLE_1" newline bitfld.long 0xC4 19. "GPMC_ADVN_ALE_SLEWCONTROL,- FAST_SLEW" "GPMC_ADVN_ALE_SLEWCONTROL_0,GPMC_ADVN_ALE_SLEWCONTROL_1" newline bitfld.long 0xC4 18. "GPMC_ADVN_ALE_INPUTENABLE,- DISABLE" "GPMC_ADVN_ALE_INPUTENABLE_0,GPMC_ADVN_ALE_INPUTENABLE_1" newline bitfld.long 0xC4 17. "GPMC_ADVN_ALE_PULLTYPESELECT,- PULL_DOWN" "GPMC_ADVN_ALE_PULLTYPESELECT_0,GPMC_ADVN_ALE_PULLTYPESELECT_1" newline bitfld.long 0xC4 16. "GPMC_ADVN_ALE_PULLUDENABLE,- ENABLE" "GPMC_ADVN_ALE_PULLUDENABLE_0,GPMC_ADVN_ALE_PULLUDENABLE_1" newline bitfld.long 0xC4 8. "GPMC_ADVN_ALE_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_ADVN_ALE_MODESELECT_0,GPMC_ADVN_ALE_MODESELECT_1" newline bitfld.long 0xC4 4.--7. "GPMC_ADVN_ALE_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC4 0.--3. "GPMC_ADVN_ALE_MUXMODE,- GPMC_ADVN_ALE" "GPMC_ADVN_ALE_MUXMODE_0,GPMC_ADVN_ALE_MUXMODE_1,GPMC_ADVN_ALE_MUXMODE_2,GPMC_ADVN_ALE_MUXMODE_3,GPMC_ADVN_ALE_MUXMODE_4,GPMC_ADVN_ALE_MUXMODE_5,GPMC_ADVN_ALE_MUXMODE_6,GPMC_ADVN_ALE_MUXMODE_7,GPMC_ADVN_ALE_MUXMODE_8,GPMC_ADVN_ALE_MUXMODE_9,?,?,?,?,GPMC_ADVN_ALE_MUXMODE_14,GPMC_ADVN_ALE_MUXMODE_15" line.long 0xC8 "CTRL_CORE_PAD_GPMC_OEN_REN," rbitfld.long 0xC8 25. "GPMC_OEN_REN_WAKEUPEVENT,- NOWAKEUP" "GPMC_OEN_REN_WAKEUPEVENT_0,GPMC_OEN_REN_WAKEUPEVENT_1" newline bitfld.long 0xC8 24. "GPMC_OEN_REN_WAKEUPENABLE,- DISABLE" "GPMC_OEN_REN_WAKEUPENABLE_0,GPMC_OEN_REN_WAKEUPENABLE_1" newline bitfld.long 0xC8 19. "GPMC_OEN_REN_SLEWCONTROL,- FAST_SLEW" "GPMC_OEN_REN_SLEWCONTROL_0,GPMC_OEN_REN_SLEWCONTROL_1" newline bitfld.long 0xC8 18. "GPMC_OEN_REN_INPUTENABLE,- DISABLE" "GPMC_OEN_REN_INPUTENABLE_0,GPMC_OEN_REN_INPUTENABLE_1" newline bitfld.long 0xC8 17. "GPMC_OEN_REN_PULLTYPESELECT,- PULL_DOWN" "GPMC_OEN_REN_PULLTYPESELECT_0,GPMC_OEN_REN_PULLTYPESELECT_1" newline bitfld.long 0xC8 16. "GPMC_OEN_REN_PULLUDENABLE,- ENABLE" "GPMC_OEN_REN_PULLUDENABLE_0,GPMC_OEN_REN_PULLUDENABLE_1" newline bitfld.long 0xC8 8. "GPMC_OEN_REN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_OEN_REN_MODESELECT_0,GPMC_OEN_REN_MODESELECT_1" newline bitfld.long 0xC8 4.--7. "GPMC_OEN_REN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC8 0.--3. "GPMC_OEN_REN_MUXMODE,- GPMC_OEN_REN" "GPMC_OEN_REN_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_OEN_REN_MUXMODE_14,GPMC_OEN_REN_MUXMODE_15" line.long 0xCC "CTRL_CORE_PAD_GPMC_WEN," rbitfld.long 0xCC 25. "GPMC_WEN_WAKEUPEVENT,- NOWAKEUP" "GPMC_WEN_WAKEUPEVENT_0,GPMC_WEN_WAKEUPEVENT_1" newline bitfld.long 0xCC 24. "GPMC_WEN_WAKEUPENABLE,- DISABLE" "GPMC_WEN_WAKEUPENABLE_0,GPMC_WEN_WAKEUPENABLE_1" newline bitfld.long 0xCC 19. "GPMC_WEN_SLEWCONTROL,- FAST_SLEW" "GPMC_WEN_SLEWCONTROL_0,GPMC_WEN_SLEWCONTROL_1" newline bitfld.long 0xCC 18. "GPMC_WEN_INPUTENABLE,- DISABLE" "GPMC_WEN_INPUTENABLE_0,GPMC_WEN_INPUTENABLE_1" newline bitfld.long 0xCC 17. "GPMC_WEN_PULLTYPESELECT,- PULL_DOWN" "GPMC_WEN_PULLTYPESELECT_0,GPMC_WEN_PULLTYPESELECT_1" newline bitfld.long 0xCC 16. "GPMC_WEN_PULLUDENABLE,- ENABLE" "GPMC_WEN_PULLUDENABLE_0,GPMC_WEN_PULLUDENABLE_1" newline bitfld.long 0xCC 8. "GPMC_WEN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_WEN_MODESELECT_0,GPMC_WEN_MODESELECT_1" newline bitfld.long 0xCC 4.--7. "GPMC_WEN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xCC 0.--3. "GPMC_WEN_MUXMODE,- GPMC_WEN" "GPMC_WEN_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_WEN_MUXMODE_14,GPMC_WEN_MUXMODE_15" line.long 0xD0 "CTRL_CORE_PAD_GPMC_BEN0," rbitfld.long 0xD0 25. "GPMC_BEN0_WAKEUPEVENT,- NOWAKEUP" "GPMC_BEN0_WAKEUPEVENT_0,GPMC_BEN0_WAKEUPEVENT_1" newline bitfld.long 0xD0 24. "GPMC_BEN0_WAKEUPENABLE,- DISABLE" "GPMC_BEN0_WAKEUPENABLE_0,GPMC_BEN0_WAKEUPENABLE_1" newline bitfld.long 0xD0 19. "GPMC_BEN0_SLEWCONTROL,- FAST_SLEW" "GPMC_BEN0_SLEWCONTROL_0,GPMC_BEN0_SLEWCONTROL_1" newline bitfld.long 0xD0 18. "GPMC_BEN0_INPUTENABLE,- DISABLE" "GPMC_BEN0_INPUTENABLE_0,GPMC_BEN0_INPUTENABLE_1" newline bitfld.long 0xD0 17. "GPMC_BEN0_PULLTYPESELECT,- PULL_DOWN" "GPMC_BEN0_PULLTYPESELECT_0,GPMC_BEN0_PULLTYPESELECT_1" newline bitfld.long 0xD0 16. "GPMC_BEN0_PULLUDENABLE,- ENABLE" "GPMC_BEN0_PULLUDENABLE_0,GPMC_BEN0_PULLUDENABLE_1" newline bitfld.long 0xD0 8. "GPMC_BEN0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_BEN0_MODESELECT_0,GPMC_BEN0_MODESELECT_1" newline bitfld.long 0xD0 4.--7. "GPMC_BEN0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD0 0.--3. "GPMC_BEN0_MUXMODE,- GPMC_BEN0" "GPMC_BEN0_MUXMODE_0,GPMC_BEN0_MUXMODE_1,?,GPMC_BEN0_MUXMODE_3,?,?,GPMC_BEN0_MUXMODE_6,GPMC_BEN0_MUXMODE_7,?,GPMC_BEN0_MUXMODE_9,?,?,?,?,GPMC_BEN0_MUXMODE_14,GPMC_BEN0_MUXMODE_15" line.long 0xD4 "CTRL_CORE_PAD_GPMC_BEN1," rbitfld.long 0xD4 25. "GPMC_BEN1_WAKEUPEVENT,- NOWAKEUP" "GPMC_BEN1_WAKEUPEVENT_0,GPMC_BEN1_WAKEUPEVENT_1" newline bitfld.long 0xD4 24. "GPMC_BEN1_WAKEUPENABLE,- DISABLE" "GPMC_BEN1_WAKEUPENABLE_0,GPMC_BEN1_WAKEUPENABLE_1" newline bitfld.long 0xD4 19. "GPMC_BEN1_SLEWCONTROL,- FAST_SLEW" "GPMC_BEN1_SLEWCONTROL_0,GPMC_BEN1_SLEWCONTROL_1" newline bitfld.long 0xD4 18. "GPMC_BEN1_INPUTENABLE,- DISABLE" "GPMC_BEN1_INPUTENABLE_0,GPMC_BEN1_INPUTENABLE_1" newline bitfld.long 0xD4 17. "GPMC_BEN1_PULLTYPESELECT,- PULL_DOWN" "GPMC_BEN1_PULLTYPESELECT_0,GPMC_BEN1_PULLTYPESELECT_1" newline bitfld.long 0xD4 16. "GPMC_BEN1_PULLUDENABLE,- ENABLE" "GPMC_BEN1_PULLUDENABLE_0,GPMC_BEN1_PULLUDENABLE_1" newline bitfld.long 0xD4 8. "GPMC_BEN1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_BEN1_MODESELECT_0,GPMC_BEN1_MODESELECT_1" newline bitfld.long 0xD4 4.--7. "GPMC_BEN1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD4 0.--3. "GPMC_BEN1_MUXMODE,- GPMC_BEN1" "GPMC_BEN1_MUXMODE_0,GPMC_BEN1_MUXMODE_1,?,GPMC_BEN1_MUXMODE_3,GPMC_BEN1_MUXMODE_4,GPMC_BEN1_MUXMODE_5,GPMC_BEN1_MUXMODE_6,GPMC_BEN1_MUXMODE_7,?,GPMC_BEN1_MUXMODE_9,?,?,?,?,GPMC_BEN1_MUXMODE_14,GPMC_BEN1_MUXMODE_15" line.long 0xD8 "CTRL_CORE_PAD_GPMC_WAIT0," rbitfld.long 0xD8 25. "GPMC_WAIT0_WAKEUPEVENT,- NOWAKEUP" "GPMC_WAIT0_WAKEUPEVENT_0,GPMC_WAIT0_WAKEUPEVENT_1" newline bitfld.long 0xD8 24. "GPMC_WAIT0_WAKEUPENABLE,- DISABLE" "GPMC_WAIT0_WAKEUPENABLE_0,GPMC_WAIT0_WAKEUPENABLE_1" newline bitfld.long 0xD8 19. "GPMC_WAIT0_SLEWCONTROL,- FAST_SLEW" "GPMC_WAIT0_SLEWCONTROL_0,GPMC_WAIT0_SLEWCONTROL_1" newline bitfld.long 0xD8 18. "GPMC_WAIT0_INPUTENABLE,- DISABLE" "GPMC_WAIT0_INPUTENABLE_0,GPMC_WAIT0_INPUTENABLE_1" newline bitfld.long 0xD8 17. "GPMC_WAIT0_PULLTYPESELECT,- PULL_DOWN" "GPMC_WAIT0_PULLTYPESELECT_0,GPMC_WAIT0_PULLTYPESELECT_1" newline bitfld.long 0xD8 16. "GPMC_WAIT0_PULLUDENABLE,- ENABLE" "GPMC_WAIT0_PULLUDENABLE_0,GPMC_WAIT0_PULLUDENABLE_1" newline bitfld.long 0xD8 8. "GPMC_WAIT0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPMC_WAIT0_MODESELECT_0,GPMC_WAIT0_MODESELECT_1" newline bitfld.long 0xD8 4.--7. "GPMC_WAIT0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD8 0.--3. "GPMC_WAIT0_MUXMODE,- GPMC_WAIT0" "GPMC_WAIT0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_WAIT0_MUXMODE_14,GPMC_WAIT0_MUXMODE_15" line.long 0xDC "CTRL_CORE_PAD_VIN1A_CLK0," rbitfld.long 0xDC 25. "VIN1A_CLK0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_CLK0_WAKEUPEVENT_0,VIN1A_CLK0_WAKEUPEVENT_1" newline bitfld.long 0xDC 24. "VIN1A_CLK0_WAKEUPENABLE,- DISABLE" "VIN1A_CLK0_WAKEUPENABLE_0,VIN1A_CLK0_WAKEUPENABLE_1" newline bitfld.long 0xDC 19. "VIN1A_CLK0_SLEWCONTROL,- FAST_SLEW" "VIN1A_CLK0_SLEWCONTROL_0,VIN1A_CLK0_SLEWCONTROL_1" newline bitfld.long 0xDC 18. "VIN1A_CLK0_INPUTENABLE,- DISABLE" "VIN1A_CLK0_INPUTENABLE_0,VIN1A_CLK0_INPUTENABLE_1" newline bitfld.long 0xDC 17. "VIN1A_CLK0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_CLK0_PULLTYPESELECT_0,VIN1A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0xDC 16. "VIN1A_CLK0_PULLUDENABLE,- ENABLE" "VIN1A_CLK0_PULLUDENABLE_0,VIN1A_CLK0_PULLUDENABLE_1" newline bitfld.long 0xDC 8. "VIN1A_CLK0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_CLK0_MODESELECT_0,VIN1A_CLK0_MODESELECT_1" newline bitfld.long 0xDC 4.--7. "VIN1A_CLK0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xDC 0.--3. "VIN1A_CLK0_MUXMODE,- VIN1A_CLK0" "VIN1A_CLK0_MUXMODE_0,?,?,VIN1A_CLK0_MUXMODE_3,VIN1A_CLK0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_CLK0_MUXMODE_14,VIN1A_CLK0_MUXMODE_15" line.long 0xE0 "CTRL_CORE_PAD_VIN1B_CLK1," rbitfld.long 0xE0 25. "VIN1B_CLK1_WAKEUPEVENT,- NOWAKEUP" "VIN1B_CLK1_WAKEUPEVENT_0,VIN1B_CLK1_WAKEUPEVENT_1" newline bitfld.long 0xE0 24. "VIN1B_CLK1_WAKEUPENABLE,- DISABLE" "VIN1B_CLK1_WAKEUPENABLE_0,VIN1B_CLK1_WAKEUPENABLE_1" newline bitfld.long 0xE0 19. "VIN1B_CLK1_SLEWCONTROL,- FAST_SLEW" "VIN1B_CLK1_SLEWCONTROL_0,VIN1B_CLK1_SLEWCONTROL_1" newline bitfld.long 0xE0 18. "VIN1B_CLK1_INPUTENABLE,- DISABLE" "VIN1B_CLK1_INPUTENABLE_0,VIN1B_CLK1_INPUTENABLE_1" newline bitfld.long 0xE0 17. "VIN1B_CLK1_PULLTYPESELECT,- PULL_DOWN" "VIN1B_CLK1_PULLTYPESELECT_0,VIN1B_CLK1_PULLTYPESELECT_1" newline bitfld.long 0xE0 16. "VIN1B_CLK1_PULLUDENABLE,- ENABLE" "VIN1B_CLK1_PULLUDENABLE_0,VIN1B_CLK1_PULLUDENABLE_1" newline bitfld.long 0xE0 8. "VIN1B_CLK1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1B_CLK1_MODESELECT_0,VIN1B_CLK1_MODESELECT_1" newline bitfld.long 0xE0 4.--7. "VIN1B_CLK1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE0 0.--3. "VIN1B_CLK1_MUXMODE,- VIN1B_CLK1" "VIN1B_CLK1_MUXMODE_0,?,?,?,?,?,VIN1B_CLK1_MUXMODE_6,?,?,?,?,?,?,?,VIN1B_CLK1_MUXMODE_14,VIN1B_CLK1_MUXMODE_15" line.long 0xE4 "CTRL_CORE_PAD_VIN1A_DE0," rbitfld.long 0xE4 25. "VIN1A_DE0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_DE0_WAKEUPEVENT_0,VIN1A_DE0_WAKEUPEVENT_1" newline bitfld.long 0xE4 24. "VIN1A_DE0_WAKEUPENABLE,- DISABLE" "VIN1A_DE0_WAKEUPENABLE_0,VIN1A_DE0_WAKEUPENABLE_1" newline bitfld.long 0xE4 19. "VIN1A_DE0_SLEWCONTROL,- FAST_SLEW" "VIN1A_DE0_SLEWCONTROL_0,VIN1A_DE0_SLEWCONTROL_1" newline bitfld.long 0xE4 18. "VIN1A_DE0_INPUTENABLE,- DISABLE" "VIN1A_DE0_INPUTENABLE_0,VIN1A_DE0_INPUTENABLE_1" newline bitfld.long 0xE4 17. "VIN1A_DE0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_DE0_PULLTYPESELECT_0,VIN1A_DE0_PULLTYPESELECT_1" newline bitfld.long 0xE4 16. "VIN1A_DE0_PULLUDENABLE,- ENABLE" "VIN1A_DE0_PULLUDENABLE_0,VIN1A_DE0_PULLUDENABLE_1" newline bitfld.long 0xE4 8. "VIN1A_DE0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_DE0_MODESELECT_0,VIN1A_DE0_MODESELECT_1" newline bitfld.long 0xE4 4.--7. "VIN1A_DE0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE4 0.--3. "VIN1A_DE0_MUXMODE,- VIN1A_DE0" "VIN1A_DE0_MUXMODE_0,VIN1A_DE0_MUXMODE_1,?,VIN1A_DE0_MUXMODE_3,VIN1A_DE0_MUXMODE_4,VIN1A_DE0_MUXMODE_5,?,VIN1A_DE0_MUXMODE_7,VIN1A_DE0_MUXMODE_8,?,VIN1A_DE0_MUXMODE_10,?,?,?,VIN1A_DE0_MUXMODE_14,VIN1A_DE0_MUXMODE_15" line.long 0xE8 "CTRL_CORE_PAD_VIN1A_FLD0," rbitfld.long 0xE8 25. "VIN1A_FLD0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_FLD0_WAKEUPEVENT_0,VIN1A_FLD0_WAKEUPEVENT_1" newline bitfld.long 0xE8 24. "VIN1A_FLD0_WAKEUPENABLE,- DISABLE" "VIN1A_FLD0_WAKEUPENABLE_0,VIN1A_FLD0_WAKEUPENABLE_1" newline bitfld.long 0xE8 19. "VIN1A_FLD0_SLEWCONTROL,- FAST_SLEW" "VIN1A_FLD0_SLEWCONTROL_0,VIN1A_FLD0_SLEWCONTROL_1" newline bitfld.long 0xE8 18. "VIN1A_FLD0_INPUTENABLE,- DISABLE" "VIN1A_FLD0_INPUTENABLE_0,VIN1A_FLD0_INPUTENABLE_1" newline bitfld.long 0xE8 17. "VIN1A_FLD0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_FLD0_PULLTYPESELECT_0,VIN1A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0xE8 16. "VIN1A_FLD0_PULLUDENABLE,- ENABLE" "VIN1A_FLD0_PULLUDENABLE_0,VIN1A_FLD0_PULLUDENABLE_1" newline bitfld.long 0xE8 8. "VIN1A_FLD0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_FLD0_MODESELECT_0,VIN1A_FLD0_MODESELECT_1" newline bitfld.long 0xE8 4.--7. "VIN1A_FLD0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE8 0.--3. "VIN1A_FLD0_MUXMODE,- VIN1A_FLD0" "VIN1A_FLD0_MUXMODE_0,VIN1A_FLD0_MUXMODE_1,?,?,VIN1A_FLD0_MUXMODE_4,VIN1A_FLD0_MUXMODE_5,?,VIN1A_FLD0_MUXMODE_7,VIN1A_FLD0_MUXMODE_8,?,VIN1A_FLD0_MUXMODE_10,?,?,?,VIN1A_FLD0_MUXMODE_14,VIN1A_FLD0_MUXMODE_15" line.long 0xEC "CTRL_CORE_PAD_VIN1A_HSYNC0," rbitfld.long 0xEC 25. "VIN1A_HSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_HSYNC0_WAKEUPEVENT_0,VIN1A_HSYNC0_WAKEUPEVENT_1" newline bitfld.long 0xEC 24. "VIN1A_HSYNC0_WAKEUPENABLE,- DISABLE" "VIN1A_HSYNC0_WAKEUPENABLE_0,VIN1A_HSYNC0_WAKEUPENABLE_1" newline bitfld.long 0xEC 19. "VIN1A_HSYNC0_SLEWCONTROL,- FAST_SLEW" "VIN1A_HSYNC0_SLEWCONTROL_0,VIN1A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0xEC 18. "VIN1A_HSYNC0_INPUTENABLE,- DISABLE" "VIN1A_HSYNC0_INPUTENABLE_0,VIN1A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0xEC 17. "VIN1A_HSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_HSYNC0_PULLTYPESELECT_0,VIN1A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0xEC 16. "VIN1A_HSYNC0_PULLUDENABLE,- ENABLE" "VIN1A_HSYNC0_PULLUDENABLE_0,VIN1A_HSYNC0_PULLUDENABLE_1" newline bitfld.long 0xEC 8. "VIN1A_HSYNC0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_HSYNC0_MODESELECT_0,VIN1A_HSYNC0_MODESELECT_1" newline bitfld.long 0xEC 4.--7. "VIN1A_HSYNC0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xEC 0.--3. "VIN1A_HSYNC0_MUXMODE,- VIN1A_HSYNC0" "VIN1A_HSYNC0_MUXMODE_0,VIN1A_HSYNC0_MUXMODE_1,?,?,VIN1A_HSYNC0_MUXMODE_4,VIN1A_HSYNC0_MUXMODE_5,?,VIN1A_HSYNC0_MUXMODE_7,VIN1A_HSYNC0_MUXMODE_8,?,VIN1A_HSYNC0_MUXMODE_10,?,?,?,VIN1A_HSYNC0_MUXMODE_14,VIN1A_HSYNC0_MUXMODE_15" line.long 0xF0 "CTRL_CORE_PAD_VIN1A_VSYNC0," rbitfld.long 0xF0 25. "VIN1A_VSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_VSYNC0_WAKEUPEVENT_0,VIN1A_VSYNC0_WAKEUPEVENT_1" newline bitfld.long 0xF0 24. "VIN1A_VSYNC0_WAKEUPENABLE,- DISABLE" "VIN1A_VSYNC0_WAKEUPENABLE_0,VIN1A_VSYNC0_WAKEUPENABLE_1" newline bitfld.long 0xF0 19. "VIN1A_VSYNC0_SLEWCONTROL,- FAST_SLEW" "VIN1A_VSYNC0_SLEWCONTROL_0,VIN1A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0xF0 18. "VIN1A_VSYNC0_INPUTENABLE,- DISABLE" "VIN1A_VSYNC0_INPUTENABLE_0,VIN1A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0xF0 17. "VIN1A_VSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_VSYNC0_PULLTYPESELECT_0,VIN1A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0xF0 16. "VIN1A_VSYNC0_PULLUDENABLE,- ENABLE" "VIN1A_VSYNC0_PULLUDENABLE_0,VIN1A_VSYNC0_PULLUDENABLE_1" newline bitfld.long 0xF0 8. "VIN1A_VSYNC0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_VSYNC0_MODESELECT_0,VIN1A_VSYNC0_MODESELECT_1" newline bitfld.long 0xF0 4.--7. "VIN1A_VSYNC0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF0 0.--3. "VIN1A_VSYNC0_MUXMODE,- VIN1A_VSYNC0" "VIN1A_VSYNC0_MUXMODE_0,VIN1A_VSYNC0_MUXMODE_1,?,?,VIN1A_VSYNC0_MUXMODE_4,VIN1A_VSYNC0_MUXMODE_5,?,VIN1A_VSYNC0_MUXMODE_7,VIN1A_VSYNC0_MUXMODE_8,?,VIN1A_VSYNC0_MUXMODE_10,?,?,?,VIN1A_VSYNC0_MUXMODE_14,VIN1A_VSYNC0_MUXMODE_15" line.long 0xF4 "CTRL_CORE_PAD_VIN1A_D0," rbitfld.long 0xF4 25. "VIN1A_D0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D0_WAKEUPEVENT_0,VIN1A_D0_WAKEUPEVENT_1" newline bitfld.long 0xF4 24. "VIN1A_D0_WAKEUPENABLE,- DISABLE" "VIN1A_D0_WAKEUPENABLE_0,VIN1A_D0_WAKEUPENABLE_1" newline bitfld.long 0xF4 19. "VIN1A_D0_SLEWCONTROL,- FAST_SLEW" "VIN1A_D0_SLEWCONTROL_0,VIN1A_D0_SLEWCONTROL_1" newline bitfld.long 0xF4 18. "VIN1A_D0_INPUTENABLE,- DISABLE" "VIN1A_D0_INPUTENABLE_0,VIN1A_D0_INPUTENABLE_1" newline bitfld.long 0xF4 17. "VIN1A_D0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D0_PULLTYPESELECT_0,VIN1A_D0_PULLTYPESELECT_1" newline bitfld.long 0xF4 16. "VIN1A_D0_PULLUDENABLE,- ENABLE" "VIN1A_D0_PULLUDENABLE_0,VIN1A_D0_PULLUDENABLE_1" newline bitfld.long 0xF4 8. "VIN1A_D0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D0_MODESELECT_0,VIN1A_D0_MODESELECT_1" newline bitfld.long 0xF4 4.--7. "VIN1A_D0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF4 0.--3. "VIN1A_D0_MUXMODE,- VIN1A_D0" "VIN1A_D0_MUXMODE_0,?,?,VIN1A_D0_MUXMODE_3,VIN1A_D0_MUXMODE_4,VIN1A_D0_MUXMODE_5,?,?,?,?,VIN1A_D0_MUXMODE_10,?,?,?,VIN1A_D0_MUXMODE_14,VIN1A_D0_MUXMODE_15" line.long 0xF8 "CTRL_CORE_PAD_VIN1A_D1," rbitfld.long 0xF8 25. "VIN1A_D1_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D1_WAKEUPEVENT_0,VIN1A_D1_WAKEUPEVENT_1" newline bitfld.long 0xF8 24. "VIN1A_D1_WAKEUPENABLE,- DISABLE" "VIN1A_D1_WAKEUPENABLE_0,VIN1A_D1_WAKEUPENABLE_1" newline bitfld.long 0xF8 19. "VIN1A_D1_SLEWCONTROL,- FAST_SLEW" "VIN1A_D1_SLEWCONTROL_0,VIN1A_D1_SLEWCONTROL_1" newline bitfld.long 0xF8 18. "VIN1A_D1_INPUTENABLE,- DISABLE" "VIN1A_D1_INPUTENABLE_0,VIN1A_D1_INPUTENABLE_1" newline bitfld.long 0xF8 17. "VIN1A_D1_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D1_PULLTYPESELECT_0,VIN1A_D1_PULLTYPESELECT_1" newline bitfld.long 0xF8 16. "VIN1A_D1_PULLUDENABLE,- ENABLE" "VIN1A_D1_PULLUDENABLE_0,VIN1A_D1_PULLUDENABLE_1" newline bitfld.long 0xF8 8. "VIN1A_D1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D1_MODESELECT_0,VIN1A_D1_MODESELECT_1" newline bitfld.long 0xF8 4.--7. "VIN1A_D1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF8 0.--3. "VIN1A_D1_MUXMODE,- VIN1A_D1" "VIN1A_D1_MUXMODE_0,?,?,VIN1A_D1_MUXMODE_3,VIN1A_D1_MUXMODE_4,VIN1A_D1_MUXMODE_5,?,?,?,?,VIN1A_D1_MUXMODE_10,?,?,?,VIN1A_D1_MUXMODE_14,VIN1A_D1_MUXMODE_15" line.long 0xFC "CTRL_CORE_PAD_VIN1A_D2," rbitfld.long 0xFC 25. "VIN1A_D2_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D2_WAKEUPEVENT_0,VIN1A_D2_WAKEUPEVENT_1" newline bitfld.long 0xFC 24. "VIN1A_D2_WAKEUPENABLE,- DISABLE" "VIN1A_D2_WAKEUPENABLE_0,VIN1A_D2_WAKEUPENABLE_1" newline bitfld.long 0xFC 19. "VIN1A_D2_SLEWCONTROL,- FAST_SLEW" "VIN1A_D2_SLEWCONTROL_0,VIN1A_D2_SLEWCONTROL_1" newline bitfld.long 0xFC 18. "VIN1A_D2_INPUTENABLE,- DISABLE" "VIN1A_D2_INPUTENABLE_0,VIN1A_D2_INPUTENABLE_1" newline bitfld.long 0xFC 17. "VIN1A_D2_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D2_PULLTYPESELECT_0,VIN1A_D2_PULLTYPESELECT_1" newline bitfld.long 0xFC 16. "VIN1A_D2_PULLUDENABLE,- ENABLE" "VIN1A_D2_PULLUDENABLE_0,VIN1A_D2_PULLUDENABLE_1" newline bitfld.long 0xFC 8. "VIN1A_D2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D2_MODESELECT_0,VIN1A_D2_MODESELECT_1" newline bitfld.long 0xFC 4.--7. "VIN1A_D2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xFC 0.--3. "VIN1A_D2_MUXMODE,- VIN1A_D2" "VIN1A_D2_MUXMODE_0,?,?,VIN1A_D2_MUXMODE_3,VIN1A_D2_MUXMODE_4,VIN1A_D2_MUXMODE_5,?,?,?,?,VIN1A_D2_MUXMODE_10,?,?,?,VIN1A_D2_MUXMODE_14,VIN1A_D2_MUXMODE_15" line.long 0x100 "CTRL_CORE_PAD_VIN1A_D3," rbitfld.long 0x100 25. "VIN1A_D3_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D3_WAKEUPEVENT_0,VIN1A_D3_WAKEUPEVENT_1" newline bitfld.long 0x100 24. "VIN1A_D3_WAKEUPENABLE,- DISABLE" "VIN1A_D3_WAKEUPENABLE_0,VIN1A_D3_WAKEUPENABLE_1" newline bitfld.long 0x100 19. "VIN1A_D3_SLEWCONTROL,- FAST_SLEW" "VIN1A_D3_SLEWCONTROL_0,VIN1A_D3_SLEWCONTROL_1" newline bitfld.long 0x100 18. "VIN1A_D3_INPUTENABLE,- DISABLE" "VIN1A_D3_INPUTENABLE_0,VIN1A_D3_INPUTENABLE_1" newline bitfld.long 0x100 17. "VIN1A_D3_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D3_PULLTYPESELECT_0,VIN1A_D3_PULLTYPESELECT_1" newline bitfld.long 0x100 16. "VIN1A_D3_PULLUDENABLE,- ENABLE" "VIN1A_D3_PULLUDENABLE_0,VIN1A_D3_PULLUDENABLE_1" newline bitfld.long 0x100 8. "VIN1A_D3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D3_MODESELECT_0,VIN1A_D3_MODESELECT_1" newline bitfld.long 0x100 4.--7. "VIN1A_D3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x100 0.--3. "VIN1A_D3_MUXMODE,- VIN1A_D3" "VIN1A_D3_MUXMODE_0,?,?,VIN1A_D3_MUXMODE_3,VIN1A_D3_MUXMODE_4,VIN1A_D3_MUXMODE_5,?,?,?,?,VIN1A_D3_MUXMODE_10,?,?,?,VIN1A_D3_MUXMODE_14,VIN1A_D3_MUXMODE_15" line.long 0x104 "CTRL_CORE_PAD_VIN1A_D4," rbitfld.long 0x104 25. "VIN1A_D4_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D4_WAKEUPEVENT_0,VIN1A_D4_WAKEUPEVENT_1" newline bitfld.long 0x104 24. "VIN1A_D4_WAKEUPENABLE,- DISABLE" "VIN1A_D4_WAKEUPENABLE_0,VIN1A_D4_WAKEUPENABLE_1" newline bitfld.long 0x104 19. "VIN1A_D4_SLEWCONTROL,- FAST_SLEW" "VIN1A_D4_SLEWCONTROL_0,VIN1A_D4_SLEWCONTROL_1" newline bitfld.long 0x104 18. "VIN1A_D4_INPUTENABLE,- DISABLE" "VIN1A_D4_INPUTENABLE_0,VIN1A_D4_INPUTENABLE_1" newline bitfld.long 0x104 17. "VIN1A_D4_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D4_PULLTYPESELECT_0,VIN1A_D4_PULLTYPESELECT_1" newline bitfld.long 0x104 16. "VIN1A_D4_PULLUDENABLE,- ENABLE" "VIN1A_D4_PULLUDENABLE_0,VIN1A_D4_PULLUDENABLE_1" newline bitfld.long 0x104 8. "VIN1A_D4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D4_MODESELECT_0,VIN1A_D4_MODESELECT_1" newline bitfld.long 0x104 4.--7. "VIN1A_D4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x104 0.--3. "VIN1A_D4_MUXMODE,- VIN1A_D4" "VIN1A_D4_MUXMODE_0,?,?,VIN1A_D4_MUXMODE_3,VIN1A_D4_MUXMODE_4,?,?,?,?,?,VIN1A_D4_MUXMODE_10,?,?,?,VIN1A_D4_MUXMODE_14,VIN1A_D4_MUXMODE_15" line.long 0x108 "CTRL_CORE_PAD_VIN1A_D5," rbitfld.long 0x108 25. "VIN1A_D5_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D5_WAKEUPEVENT_0,VIN1A_D5_WAKEUPEVENT_1" newline bitfld.long 0x108 24. "VIN1A_D5_WAKEUPENABLE,- DISABLE" "VIN1A_D5_WAKEUPENABLE_0,VIN1A_D5_WAKEUPENABLE_1" newline bitfld.long 0x108 19. "VIN1A_D5_SLEWCONTROL,- FAST_SLEW" "VIN1A_D5_SLEWCONTROL_0,VIN1A_D5_SLEWCONTROL_1" newline bitfld.long 0x108 18. "VIN1A_D5_INPUTENABLE,- DISABLE" "VIN1A_D5_INPUTENABLE_0,VIN1A_D5_INPUTENABLE_1" newline bitfld.long 0x108 17. "VIN1A_D5_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D5_PULLTYPESELECT_0,VIN1A_D5_PULLTYPESELECT_1" newline bitfld.long 0x108 16. "VIN1A_D5_PULLUDENABLE,- ENABLE" "VIN1A_D5_PULLUDENABLE_0,VIN1A_D5_PULLUDENABLE_1" newline bitfld.long 0x108 8. "VIN1A_D5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D5_MODESELECT_0,VIN1A_D5_MODESELECT_1" newline bitfld.long 0x108 4.--7. "VIN1A_D5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x108 0.--3. "VIN1A_D5_MUXMODE,- VIN1A_D5" "VIN1A_D5_MUXMODE_0,?,?,VIN1A_D5_MUXMODE_3,VIN1A_D5_MUXMODE_4,?,?,?,?,?,VIN1A_D5_MUXMODE_10,?,?,?,VIN1A_D5_MUXMODE_14,VIN1A_D5_MUXMODE_15" line.long 0x10C "CTRL_CORE_PAD_VIN1A_D6," rbitfld.long 0x10C 25. "VIN1A_D6_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D6_WAKEUPEVENT_0,VIN1A_D6_WAKEUPEVENT_1" newline bitfld.long 0x10C 24. "VIN1A_D6_WAKEUPENABLE,- DISABLE" "VIN1A_D6_WAKEUPENABLE_0,VIN1A_D6_WAKEUPENABLE_1" newline bitfld.long 0x10C 19. "VIN1A_D6_SLEWCONTROL,- FAST_SLEW" "VIN1A_D6_SLEWCONTROL_0,VIN1A_D6_SLEWCONTROL_1" newline bitfld.long 0x10C 18. "VIN1A_D6_INPUTENABLE,- DISABLE" "VIN1A_D6_INPUTENABLE_0,VIN1A_D6_INPUTENABLE_1" newline bitfld.long 0x10C 17. "VIN1A_D6_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D6_PULLTYPESELECT_0,VIN1A_D6_PULLTYPESELECT_1" newline bitfld.long 0x10C 16. "VIN1A_D6_PULLUDENABLE,- ENABLE" "VIN1A_D6_PULLUDENABLE_0,VIN1A_D6_PULLUDENABLE_1" newline bitfld.long 0x10C 8. "VIN1A_D6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D6_MODESELECT_0,VIN1A_D6_MODESELECT_1" newline bitfld.long 0x10C 4.--7. "VIN1A_D6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10C 0.--3. "VIN1A_D6_MUXMODE,- VIN1A_D6" "VIN1A_D6_MUXMODE_0,?,?,VIN1A_D6_MUXMODE_3,VIN1A_D6_MUXMODE_4,?,?,?,?,?,VIN1A_D6_MUXMODE_10,?,?,?,VIN1A_D6_MUXMODE_14,VIN1A_D6_MUXMODE_15" line.long 0x110 "CTRL_CORE_PAD_VIN1A_D7," rbitfld.long 0x110 25. "VIN1A_D7_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D7_WAKEUPEVENT_0,VIN1A_D7_WAKEUPEVENT_1" newline bitfld.long 0x110 24. "VIN1A_D7_WAKEUPENABLE,- DISABLE" "VIN1A_D7_WAKEUPENABLE_0,VIN1A_D7_WAKEUPENABLE_1" newline bitfld.long 0x110 19. "VIN1A_D7_SLEWCONTROL,- FAST_SLEW" "VIN1A_D7_SLEWCONTROL_0,VIN1A_D7_SLEWCONTROL_1" newline bitfld.long 0x110 18. "VIN1A_D7_INPUTENABLE,- DISABLE" "VIN1A_D7_INPUTENABLE_0,VIN1A_D7_INPUTENABLE_1" newline bitfld.long 0x110 17. "VIN1A_D7_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D7_PULLTYPESELECT_0,VIN1A_D7_PULLTYPESELECT_1" newline bitfld.long 0x110 16. "VIN1A_D7_PULLUDENABLE,- ENABLE" "VIN1A_D7_PULLUDENABLE_0,VIN1A_D7_PULLUDENABLE_1" newline bitfld.long 0x110 8. "VIN1A_D7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D7_MODESELECT_0,VIN1A_D7_MODESELECT_1" newline bitfld.long 0x110 4.--7. "VIN1A_D7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x110 0.--3. "VIN1A_D7_MUXMODE,- VIN1A_D7" "VIN1A_D7_MUXMODE_0,?,?,VIN1A_D7_MUXMODE_3,VIN1A_D7_MUXMODE_4,?,?,?,?,?,VIN1A_D7_MUXMODE_10,?,?,?,VIN1A_D7_MUXMODE_14,VIN1A_D7_MUXMODE_15" line.long 0x114 "CTRL_CORE_PAD_VIN1A_D8," rbitfld.long 0x114 25. "VIN1A_D8_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D8_WAKEUPEVENT_0,VIN1A_D8_WAKEUPEVENT_1" newline bitfld.long 0x114 24. "VIN1A_D8_WAKEUPENABLE,- DISABLE" "VIN1A_D8_WAKEUPENABLE_0,VIN1A_D8_WAKEUPENABLE_1" newline bitfld.long 0x114 19. "VIN1A_D8_SLEWCONTROL,- FAST_SLEW" "VIN1A_D8_SLEWCONTROL_0,VIN1A_D8_SLEWCONTROL_1" newline bitfld.long 0x114 18. "VIN1A_D8_INPUTENABLE,- DISABLE" "VIN1A_D8_INPUTENABLE_0,VIN1A_D8_INPUTENABLE_1" newline bitfld.long 0x114 17. "VIN1A_D8_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D8_PULLTYPESELECT_0,VIN1A_D8_PULLTYPESELECT_1" newline bitfld.long 0x114 16. "VIN1A_D8_PULLUDENABLE,- ENABLE" "VIN1A_D8_PULLUDENABLE_0,VIN1A_D8_PULLUDENABLE_1" newline bitfld.long 0x114 8. "VIN1A_D8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D8_MODESELECT_0,VIN1A_D8_MODESELECT_1" newline bitfld.long 0x114 4.--7. "VIN1A_D8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x114 0.--3. "VIN1A_D8_MUXMODE,- VIN1A_D8" "VIN1A_D8_MUXMODE_0,VIN1A_D8_MUXMODE_1,?,?,VIN1A_D8_MUXMODE_4,?,?,?,?,?,VIN1A_D8_MUXMODE_10,?,?,?,VIN1A_D8_MUXMODE_14,VIN1A_D8_MUXMODE_15" line.long 0x118 "CTRL_CORE_PAD_VIN1A_D9," rbitfld.long 0x118 25. "VIN1A_D9_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D9_WAKEUPEVENT_0,VIN1A_D9_WAKEUPEVENT_1" newline bitfld.long 0x118 24. "VIN1A_D9_WAKEUPENABLE,- DISABLE" "VIN1A_D9_WAKEUPENABLE_0,VIN1A_D9_WAKEUPENABLE_1" newline bitfld.long 0x118 19. "VIN1A_D9_SLEWCONTROL,- FAST_SLEW" "VIN1A_D9_SLEWCONTROL_0,VIN1A_D9_SLEWCONTROL_1" newline bitfld.long 0x118 18. "VIN1A_D9_INPUTENABLE,- DISABLE" "VIN1A_D9_INPUTENABLE_0,VIN1A_D9_INPUTENABLE_1" newline bitfld.long 0x118 17. "VIN1A_D9_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D9_PULLTYPESELECT_0,VIN1A_D9_PULLTYPESELECT_1" newline bitfld.long 0x118 16. "VIN1A_D9_PULLUDENABLE,- ENABLE" "VIN1A_D9_PULLUDENABLE_0,VIN1A_D9_PULLUDENABLE_1" newline bitfld.long 0x118 8. "VIN1A_D9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D9_MODESELECT_0,VIN1A_D9_MODESELECT_1" newline bitfld.long 0x118 4.--7. "VIN1A_D9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x118 0.--3. "VIN1A_D9_MUXMODE,- VIN1A_D9" "VIN1A_D9_MUXMODE_0,VIN1A_D9_MUXMODE_1,?,?,VIN1A_D9_MUXMODE_4,?,?,?,?,?,VIN1A_D9_MUXMODE_10,?,?,?,VIN1A_D9_MUXMODE_14,VIN1A_D9_MUXMODE_15" line.long 0x11C "CTRL_CORE_PAD_VIN1A_D10," rbitfld.long 0x11C 25. "VIN1A_D10_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D10_WAKEUPEVENT_0,VIN1A_D10_WAKEUPEVENT_1" newline bitfld.long 0x11C 24. "VIN1A_D10_WAKEUPENABLE,- DISABLE" "VIN1A_D10_WAKEUPENABLE_0,VIN1A_D10_WAKEUPENABLE_1" newline bitfld.long 0x11C 19. "VIN1A_D10_SLEWCONTROL,- FAST_SLEW" "VIN1A_D10_SLEWCONTROL_0,VIN1A_D10_SLEWCONTROL_1" newline bitfld.long 0x11C 18. "VIN1A_D10_INPUTENABLE,- DISABLE" "VIN1A_D10_INPUTENABLE_0,VIN1A_D10_INPUTENABLE_1" newline bitfld.long 0x11C 17. "VIN1A_D10_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D10_PULLTYPESELECT_0,VIN1A_D10_PULLTYPESELECT_1" newline bitfld.long 0x11C 16. "VIN1A_D10_PULLUDENABLE,- ENABLE" "VIN1A_D10_PULLUDENABLE_0,VIN1A_D10_PULLUDENABLE_1" newline bitfld.long 0x11C 8. "VIN1A_D10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D10_MODESELECT_0,VIN1A_D10_MODESELECT_1" newline bitfld.long 0x11C 4.--7. "VIN1A_D10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x11C 0.--3. "VIN1A_D10_MUXMODE,- VIN1A_D10" "VIN1A_D10_MUXMODE_0,VIN1A_D10_MUXMODE_1,?,?,VIN1A_D10_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_D10_MUXMODE_14,VIN1A_D10_MUXMODE_15" line.long 0x120 "CTRL_CORE_PAD_VIN1A_D11," rbitfld.long 0x120 25. "VIN1A_D11_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D11_WAKEUPEVENT_0,VIN1A_D11_WAKEUPEVENT_1" newline bitfld.long 0x120 24. "VIN1A_D11_WAKEUPENABLE,- DISABLE" "VIN1A_D11_WAKEUPENABLE_0,VIN1A_D11_WAKEUPENABLE_1" newline bitfld.long 0x120 19. "VIN1A_D11_SLEWCONTROL,- FAST_SLEW" "VIN1A_D11_SLEWCONTROL_0,VIN1A_D11_SLEWCONTROL_1" newline bitfld.long 0x120 18. "VIN1A_D11_INPUTENABLE,- DISABLE" "VIN1A_D11_INPUTENABLE_0,VIN1A_D11_INPUTENABLE_1" newline bitfld.long 0x120 17. "VIN1A_D11_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D11_PULLTYPESELECT_0,VIN1A_D11_PULLTYPESELECT_1" newline bitfld.long 0x120 16. "VIN1A_D11_PULLUDENABLE,- ENABLE" "VIN1A_D11_PULLUDENABLE_0,VIN1A_D11_PULLUDENABLE_1" newline bitfld.long 0x120 8. "VIN1A_D11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D11_MODESELECT_0,VIN1A_D11_MODESELECT_1" newline bitfld.long 0x120 4.--7. "VIN1A_D11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x120 0.--3. "VIN1A_D11_MUXMODE,- VIN1A_D11" "VIN1A_D11_MUXMODE_0,VIN1A_D11_MUXMODE_1,?,?,VIN1A_D11_MUXMODE_4,VIN1A_D11_MUXMODE_5,?,?,?,?,?,?,?,?,VIN1A_D11_MUXMODE_14,VIN1A_D11_MUXMODE_15" line.long 0x124 "CTRL_CORE_PAD_VIN1A_D12," rbitfld.long 0x124 25. "VIN1A_D12_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D12_WAKEUPEVENT_0,VIN1A_D12_WAKEUPEVENT_1" newline bitfld.long 0x124 24. "VIN1A_D12_WAKEUPENABLE,- DISABLE" "VIN1A_D12_WAKEUPENABLE_0,VIN1A_D12_WAKEUPENABLE_1" newline bitfld.long 0x124 19. "VIN1A_D12_SLEWCONTROL,- FAST_SLEW" "VIN1A_D12_SLEWCONTROL_0,VIN1A_D12_SLEWCONTROL_1" newline bitfld.long 0x124 18. "VIN1A_D12_INPUTENABLE,- DISABLE" "VIN1A_D12_INPUTENABLE_0,VIN1A_D12_INPUTENABLE_1" newline bitfld.long 0x124 17. "VIN1A_D12_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D12_PULLTYPESELECT_0,VIN1A_D12_PULLTYPESELECT_1" newline bitfld.long 0x124 16. "VIN1A_D12_PULLUDENABLE,- ENABLE" "VIN1A_D12_PULLUDENABLE_0,VIN1A_D12_PULLUDENABLE_1" newline bitfld.long 0x124 8. "VIN1A_D12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D12_MODESELECT_0,VIN1A_D12_MODESELECT_1" newline bitfld.long 0x124 4.--7. "VIN1A_D12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x124 0.--3. "VIN1A_D12_MUXMODE,- VIN1A_D12" "VIN1A_D12_MUXMODE_0,VIN1A_D12_MUXMODE_1,VIN1A_D12_MUXMODE_2,?,VIN1A_D12_MUXMODE_4,VIN1A_D12_MUXMODE_5,?,?,?,?,?,?,?,?,VIN1A_D12_MUXMODE_14,VIN1A_D12_MUXMODE_15" line.long 0x128 "CTRL_CORE_PAD_VIN1A_D13," rbitfld.long 0x128 25. "VIN1A_D13_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D13_WAKEUPEVENT_0,VIN1A_D13_WAKEUPEVENT_1" newline bitfld.long 0x128 24. "VIN1A_D13_WAKEUPENABLE,- DISABLE" "VIN1A_D13_WAKEUPENABLE_0,VIN1A_D13_WAKEUPENABLE_1" newline bitfld.long 0x128 19. "VIN1A_D13_SLEWCONTROL,- FAST_SLEW" "VIN1A_D13_SLEWCONTROL_0,VIN1A_D13_SLEWCONTROL_1" newline bitfld.long 0x128 18. "VIN1A_D13_INPUTENABLE,- DISABLE" "VIN1A_D13_INPUTENABLE_0,VIN1A_D13_INPUTENABLE_1" newline bitfld.long 0x128 17. "VIN1A_D13_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D13_PULLTYPESELECT_0,VIN1A_D13_PULLTYPESELECT_1" newline bitfld.long 0x128 16. "VIN1A_D13_PULLUDENABLE,- ENABLE" "VIN1A_D13_PULLUDENABLE_0,VIN1A_D13_PULLUDENABLE_1" newline bitfld.long 0x128 8. "VIN1A_D13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D13_MODESELECT_0,VIN1A_D13_MODESELECT_1" newline bitfld.long 0x128 4.--7. "VIN1A_D13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x128 0.--3. "VIN1A_D13_MUXMODE,- VIN1A_D13" "VIN1A_D13_MUXMODE_0,VIN1A_D13_MUXMODE_1,VIN1A_D13_MUXMODE_2,?,VIN1A_D13_MUXMODE_4,VIN1A_D13_MUXMODE_5,?,?,?,?,?,?,?,?,VIN1A_D13_MUXMODE_14,VIN1A_D13_MUXMODE_15" line.long 0x12C "CTRL_CORE_PAD_VIN1A_D14," rbitfld.long 0x12C 25. "VIN1A_D14_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D14_WAKEUPEVENT_0,VIN1A_D14_WAKEUPEVENT_1" newline bitfld.long 0x12C 24. "VIN1A_D14_WAKEUPENABLE,- DISABLE" "VIN1A_D14_WAKEUPENABLE_0,VIN1A_D14_WAKEUPENABLE_1" newline bitfld.long 0x12C 19. "VIN1A_D14_SLEWCONTROL,- FAST_SLEW" "VIN1A_D14_SLEWCONTROL_0,VIN1A_D14_SLEWCONTROL_1" newline bitfld.long 0x12C 18. "VIN1A_D14_INPUTENABLE,- DISABLE" "VIN1A_D14_INPUTENABLE_0,VIN1A_D14_INPUTENABLE_1" newline bitfld.long 0x12C 17. "VIN1A_D14_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D14_PULLTYPESELECT_0,VIN1A_D14_PULLTYPESELECT_1" newline bitfld.long 0x12C 16. "VIN1A_D14_PULLUDENABLE,- ENABLE" "VIN1A_D14_PULLUDENABLE_0,VIN1A_D14_PULLUDENABLE_1" newline bitfld.long 0x12C 8. "VIN1A_D14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D14_MODESELECT_0,VIN1A_D14_MODESELECT_1" newline bitfld.long 0x12C 4.--7. "VIN1A_D14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x12C 0.--3. "VIN1A_D14_MUXMODE,- VIN1A_D14" "VIN1A_D14_MUXMODE_0,VIN1A_D14_MUXMODE_1,VIN1A_D14_MUXMODE_2,?,VIN1A_D14_MUXMODE_4,VIN1A_D14_MUXMODE_5,?,?,?,?,?,?,?,?,VIN1A_D14_MUXMODE_14,VIN1A_D14_MUXMODE_15" line.long 0x130 "CTRL_CORE_PAD_VIN1A_D15," rbitfld.long 0x130 25. "VIN1A_D15_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D15_WAKEUPEVENT_0,VIN1A_D15_WAKEUPEVENT_1" newline bitfld.long 0x130 24. "VIN1A_D15_WAKEUPENABLE,- DISABLE" "VIN1A_D15_WAKEUPENABLE_0,VIN1A_D15_WAKEUPENABLE_1" newline bitfld.long 0x130 19. "VIN1A_D15_SLEWCONTROL,- FAST_SLEW" "VIN1A_D15_SLEWCONTROL_0,VIN1A_D15_SLEWCONTROL_1" newline bitfld.long 0x130 18. "VIN1A_D15_INPUTENABLE,- DISABLE" "VIN1A_D15_INPUTENABLE_0,VIN1A_D15_INPUTENABLE_1" newline bitfld.long 0x130 17. "VIN1A_D15_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D15_PULLTYPESELECT_0,VIN1A_D15_PULLTYPESELECT_1" newline bitfld.long 0x130 16. "VIN1A_D15_PULLUDENABLE,- ENABLE" "VIN1A_D15_PULLUDENABLE_0,VIN1A_D15_PULLUDENABLE_1" newline bitfld.long 0x130 8. "VIN1A_D15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D15_MODESELECT_0,VIN1A_D15_MODESELECT_1" newline bitfld.long 0x130 4.--7. "VIN1A_D15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x130 0.--3. "VIN1A_D15_MUXMODE,- VIN1A_D15" "VIN1A_D15_MUXMODE_0,VIN1A_D15_MUXMODE_1,VIN1A_D15_MUXMODE_2,?,VIN1A_D15_MUXMODE_4,VIN1A_D15_MUXMODE_5,?,?,?,?,?,?,?,?,VIN1A_D15_MUXMODE_14,VIN1A_D15_MUXMODE_15" line.long 0x134 "CTRL_CORE_PAD_VIN1A_D16," rbitfld.long 0x134 25. "VIN1A_D16_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D16_WAKEUPEVENT_0,VIN1A_D16_WAKEUPEVENT_1" newline bitfld.long 0x134 24. "VIN1A_D16_WAKEUPENABLE,- DISABLE" "VIN1A_D16_WAKEUPENABLE_0,VIN1A_D16_WAKEUPENABLE_1" newline bitfld.long 0x134 19. "VIN1A_D16_SLEWCONTROL,- FAST_SLEW" "VIN1A_D16_SLEWCONTROL_0,VIN1A_D16_SLEWCONTROL_1" newline bitfld.long 0x134 18. "VIN1A_D16_INPUTENABLE,- DISABLE" "VIN1A_D16_INPUTENABLE_0,VIN1A_D16_INPUTENABLE_1" newline bitfld.long 0x134 17. "VIN1A_D16_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D16_PULLTYPESELECT_0,VIN1A_D16_PULLTYPESELECT_1" newline bitfld.long 0x134 16. "VIN1A_D16_PULLUDENABLE,- ENABLE" "VIN1A_D16_PULLUDENABLE_0,VIN1A_D16_PULLUDENABLE_1" newline bitfld.long 0x134 8. "VIN1A_D16_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D16_MODESELECT_0,VIN1A_D16_MODESELECT_1" newline bitfld.long 0x134 4.--7. "VIN1A_D16_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x134 0.--3. "VIN1A_D16_MUXMODE,- VIN1A_D16" "VIN1A_D16_MUXMODE_0,VIN1A_D16_MUXMODE_1,VIN1A_D16_MUXMODE_2,?,VIN1A_D16_MUXMODE_4,?,VIN1A_D16_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D16_MUXMODE_14,VIN1A_D16_MUXMODE_15" line.long 0x138 "CTRL_CORE_PAD_VIN1A_D17," rbitfld.long 0x138 25. "VIN1A_D17_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D17_WAKEUPEVENT_0,VIN1A_D17_WAKEUPEVENT_1" newline bitfld.long 0x138 24. "VIN1A_D17_WAKEUPENABLE,- DISABLE" "VIN1A_D17_WAKEUPENABLE_0,VIN1A_D17_WAKEUPENABLE_1" newline bitfld.long 0x138 19. "VIN1A_D17_SLEWCONTROL,- FAST_SLEW" "VIN1A_D17_SLEWCONTROL_0,VIN1A_D17_SLEWCONTROL_1" newline bitfld.long 0x138 18. "VIN1A_D17_INPUTENABLE,- DISABLE" "VIN1A_D17_INPUTENABLE_0,VIN1A_D17_INPUTENABLE_1" newline bitfld.long 0x138 17. "VIN1A_D17_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D17_PULLTYPESELECT_0,VIN1A_D17_PULLTYPESELECT_1" newline bitfld.long 0x138 16. "VIN1A_D17_PULLUDENABLE,- ENABLE" "VIN1A_D17_PULLUDENABLE_0,VIN1A_D17_PULLUDENABLE_1" newline bitfld.long 0x138 8. "VIN1A_D17_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D17_MODESELECT_0,VIN1A_D17_MODESELECT_1" newline bitfld.long 0x138 4.--7. "VIN1A_D17_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x138 0.--3. "VIN1A_D17_MUXMODE,- VIN1A_D17" "VIN1A_D17_MUXMODE_0,VIN1A_D17_MUXMODE_1,VIN1A_D17_MUXMODE_2,?,VIN1A_D17_MUXMODE_4,?,VIN1A_D17_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D17_MUXMODE_14,VIN1A_D17_MUXMODE_15" line.long 0x13C "CTRL_CORE_PAD_VIN1A_D18," rbitfld.long 0x13C 25. "VIN1A_D18_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D18_WAKEUPEVENT_0,VIN1A_D18_WAKEUPEVENT_1" newline bitfld.long 0x13C 24. "VIN1A_D18_WAKEUPENABLE,- DISABLE" "VIN1A_D18_WAKEUPENABLE_0,VIN1A_D18_WAKEUPENABLE_1" newline bitfld.long 0x13C 19. "VIN1A_D18_SLEWCONTROL,- FAST_SLEW" "VIN1A_D18_SLEWCONTROL_0,VIN1A_D18_SLEWCONTROL_1" newline bitfld.long 0x13C 18. "VIN1A_D18_INPUTENABLE,- DISABLE" "VIN1A_D18_INPUTENABLE_0,VIN1A_D18_INPUTENABLE_1" newline bitfld.long 0x13C 17. "VIN1A_D18_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D18_PULLTYPESELECT_0,VIN1A_D18_PULLTYPESELECT_1" newline bitfld.long 0x13C 16. "VIN1A_D18_PULLUDENABLE,- ENABLE" "VIN1A_D18_PULLUDENABLE_0,VIN1A_D18_PULLUDENABLE_1" newline bitfld.long 0x13C 8. "VIN1A_D18_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D18_MODESELECT_0,VIN1A_D18_MODESELECT_1" newline bitfld.long 0x13C 4.--7. "VIN1A_D18_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x13C 0.--3. "VIN1A_D18_MUXMODE,- VIN1A_D18" "VIN1A_D18_MUXMODE_0,VIN1A_D18_MUXMODE_1,VIN1A_D18_MUXMODE_2,?,VIN1A_D18_MUXMODE_4,?,VIN1A_D18_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D18_MUXMODE_14,VIN1A_D18_MUXMODE_15" line.long 0x140 "CTRL_CORE_PAD_VIN1A_D19," rbitfld.long 0x140 25. "VIN1A_D19_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D19_WAKEUPEVENT_0,VIN1A_D19_WAKEUPEVENT_1" newline bitfld.long 0x140 24. "VIN1A_D19_WAKEUPENABLE,- DISABLE" "VIN1A_D19_WAKEUPENABLE_0,VIN1A_D19_WAKEUPENABLE_1" newline bitfld.long 0x140 19. "VIN1A_D19_SLEWCONTROL,- FAST_SLEW" "VIN1A_D19_SLEWCONTROL_0,VIN1A_D19_SLEWCONTROL_1" newline bitfld.long 0x140 18. "VIN1A_D19_INPUTENABLE,- DISABLE" "VIN1A_D19_INPUTENABLE_0,VIN1A_D19_INPUTENABLE_1" newline bitfld.long 0x140 17. "VIN1A_D19_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D19_PULLTYPESELECT_0,VIN1A_D19_PULLTYPESELECT_1" newline bitfld.long 0x140 16. "VIN1A_D19_PULLUDENABLE,- ENABLE" "VIN1A_D19_PULLUDENABLE_0,VIN1A_D19_PULLUDENABLE_1" newline bitfld.long 0x140 8. "VIN1A_D19_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D19_MODESELECT_0,VIN1A_D19_MODESELECT_1" newline bitfld.long 0x140 4.--7. "VIN1A_D19_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x140 0.--3. "VIN1A_D19_MUXMODE,- VIN1A_D19" "VIN1A_D19_MUXMODE_0,VIN1A_D19_MUXMODE_1,VIN1A_D19_MUXMODE_2,?,VIN1A_D19_MUXMODE_4,?,VIN1A_D19_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D19_MUXMODE_14,VIN1A_D19_MUXMODE_15" line.long 0x144 "CTRL_CORE_PAD_VIN1A_D20," rbitfld.long 0x144 25. "VIN1A_D20_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D20_WAKEUPEVENT_0,VIN1A_D20_WAKEUPEVENT_1" newline bitfld.long 0x144 24. "VIN1A_D20_WAKEUPENABLE,- DISABLE" "VIN1A_D20_WAKEUPENABLE_0,VIN1A_D20_WAKEUPENABLE_1" newline bitfld.long 0x144 19. "VIN1A_D20_SLEWCONTROL,- FAST_SLEW" "VIN1A_D20_SLEWCONTROL_0,VIN1A_D20_SLEWCONTROL_1" newline bitfld.long 0x144 18. "VIN1A_D20_INPUTENABLE,- DISABLE" "VIN1A_D20_INPUTENABLE_0,VIN1A_D20_INPUTENABLE_1" newline bitfld.long 0x144 17. "VIN1A_D20_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D20_PULLTYPESELECT_0,VIN1A_D20_PULLTYPESELECT_1" newline bitfld.long 0x144 16. "VIN1A_D20_PULLUDENABLE,- ENABLE" "VIN1A_D20_PULLUDENABLE_0,VIN1A_D20_PULLUDENABLE_1" newline bitfld.long 0x144 8. "VIN1A_D20_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D20_MODESELECT_0,VIN1A_D20_MODESELECT_1" newline bitfld.long 0x144 4.--7. "VIN1A_D20_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x144 0.--3. "VIN1A_D20_MUXMODE,- VIN1A_D20" "VIN1A_D20_MUXMODE_0,VIN1A_D20_MUXMODE_1,VIN1A_D20_MUXMODE_2,?,VIN1A_D20_MUXMODE_4,?,VIN1A_D20_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D20_MUXMODE_14,VIN1A_D20_MUXMODE_15" line.long 0x148 "CTRL_CORE_PAD_VIN1A_D21," rbitfld.long 0x148 25. "VIN1A_D21_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D21_WAKEUPEVENT_0,VIN1A_D21_WAKEUPEVENT_1" newline bitfld.long 0x148 24. "VIN1A_D21_WAKEUPENABLE,- DISABLE" "VIN1A_D21_WAKEUPENABLE_0,VIN1A_D21_WAKEUPENABLE_1" newline bitfld.long 0x148 19. "VIN1A_D21_SLEWCONTROL,- FAST_SLEW" "VIN1A_D21_SLEWCONTROL_0,VIN1A_D21_SLEWCONTROL_1" newline bitfld.long 0x148 18. "VIN1A_D21_INPUTENABLE,- DISABLE" "VIN1A_D21_INPUTENABLE_0,VIN1A_D21_INPUTENABLE_1" newline bitfld.long 0x148 17. "VIN1A_D21_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D21_PULLTYPESELECT_0,VIN1A_D21_PULLTYPESELECT_1" newline bitfld.long 0x148 16. "VIN1A_D21_PULLUDENABLE,- ENABLE" "VIN1A_D21_PULLUDENABLE_0,VIN1A_D21_PULLUDENABLE_1" newline bitfld.long 0x148 8. "VIN1A_D21_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D21_MODESELECT_0,VIN1A_D21_MODESELECT_1" newline bitfld.long 0x148 4.--7. "VIN1A_D21_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x148 0.--3. "VIN1A_D21_MUXMODE,- VIN1A_D21" "VIN1A_D21_MUXMODE_0,VIN1A_D21_MUXMODE_1,VIN1A_D21_MUXMODE_2,?,VIN1A_D21_MUXMODE_4,?,VIN1A_D21_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D21_MUXMODE_14,VIN1A_D21_MUXMODE_15" line.long 0x14C "CTRL_CORE_PAD_VIN1A_D22," rbitfld.long 0x14C 25. "VIN1A_D22_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D22_WAKEUPEVENT_0,VIN1A_D22_WAKEUPEVENT_1" newline bitfld.long 0x14C 24. "VIN1A_D22_WAKEUPENABLE,- DISABLE" "VIN1A_D22_WAKEUPENABLE_0,VIN1A_D22_WAKEUPENABLE_1" newline bitfld.long 0x14C 19. "VIN1A_D22_SLEWCONTROL,- FAST_SLEW" "VIN1A_D22_SLEWCONTROL_0,VIN1A_D22_SLEWCONTROL_1" newline bitfld.long 0x14C 18. "VIN1A_D22_INPUTENABLE,- DISABLE" "VIN1A_D22_INPUTENABLE_0,VIN1A_D22_INPUTENABLE_1" newline bitfld.long 0x14C 17. "VIN1A_D22_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D22_PULLTYPESELECT_0,VIN1A_D22_PULLTYPESELECT_1" newline bitfld.long 0x14C 16. "VIN1A_D22_PULLUDENABLE,- ENABLE" "VIN1A_D22_PULLUDENABLE_0,VIN1A_D22_PULLUDENABLE_1" newline bitfld.long 0x14C 8. "VIN1A_D22_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D22_MODESELECT_0,VIN1A_D22_MODESELECT_1" newline bitfld.long 0x14C 4.--7. "VIN1A_D22_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14C 0.--3. "VIN1A_D22_MUXMODE,- VIN1A_D22" "VIN1A_D22_MUXMODE_0,VIN1A_D22_MUXMODE_1,VIN1A_D22_MUXMODE_2,?,VIN1A_D22_MUXMODE_4,?,VIN1A_D22_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D22_MUXMODE_14,VIN1A_D22_MUXMODE_15" line.long 0x150 "CTRL_CORE_PAD_VIN1A_D23," rbitfld.long 0x150 25. "VIN1A_D23_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D23_WAKEUPEVENT_0,VIN1A_D23_WAKEUPEVENT_1" newline bitfld.long 0x150 24. "VIN1A_D23_WAKEUPENABLE,- DISABLE" "VIN1A_D23_WAKEUPENABLE_0,VIN1A_D23_WAKEUPENABLE_1" newline bitfld.long 0x150 19. "VIN1A_D23_SLEWCONTROL,- FAST_SLEW" "VIN1A_D23_SLEWCONTROL_0,VIN1A_D23_SLEWCONTROL_1" newline bitfld.long 0x150 18. "VIN1A_D23_INPUTENABLE,- DISABLE" "VIN1A_D23_INPUTENABLE_0,VIN1A_D23_INPUTENABLE_1" newline bitfld.long 0x150 17. "VIN1A_D23_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D23_PULLTYPESELECT_0,VIN1A_D23_PULLTYPESELECT_1" newline bitfld.long 0x150 16. "VIN1A_D23_PULLUDENABLE,- ENABLE" "VIN1A_D23_PULLUDENABLE_0,VIN1A_D23_PULLUDENABLE_1" newline bitfld.long 0x150 8. "VIN1A_D23_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN1A_D23_MODESELECT_0,VIN1A_D23_MODESELECT_1" newline bitfld.long 0x150 4.--7. "VIN1A_D23_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x150 0.--3. "VIN1A_D23_MUXMODE,- VIN1A_D23" "VIN1A_D23_MUXMODE_0,VIN1A_D23_MUXMODE_1,VIN1A_D23_MUXMODE_2,?,VIN1A_D23_MUXMODE_4,?,VIN1A_D23_MUXMODE_6,?,?,?,?,?,?,?,VIN1A_D23_MUXMODE_14,VIN1A_D23_MUXMODE_15" line.long 0x154 "CTRL_CORE_PAD_VIN2A_CLK0," rbitfld.long 0x154 25. "VIN2A_CLK0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_CLK0_WAKEUPEVENT_0,VIN2A_CLK0_WAKEUPEVENT_1" newline bitfld.long 0x154 24. "VIN2A_CLK0_WAKEUPENABLE,- DISABLE" "VIN2A_CLK0_WAKEUPENABLE_0,VIN2A_CLK0_WAKEUPENABLE_1" newline bitfld.long 0x154 19. "VIN2A_CLK0_SLEWCONTROL,- FAST_SLEW" "VIN2A_CLK0_SLEWCONTROL_0,VIN2A_CLK0_SLEWCONTROL_1" newline bitfld.long 0x154 18. "VIN2A_CLK0_INPUTENABLE,- DISABLE" "VIN2A_CLK0_INPUTENABLE_0,VIN2A_CLK0_INPUTENABLE_1" newline bitfld.long 0x154 17. "VIN2A_CLK0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_CLK0_PULLTYPESELECT_0,VIN2A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x154 16. "VIN2A_CLK0_PULLUDENABLE,- ENABLE" "VIN2A_CLK0_PULLUDENABLE_0,VIN2A_CLK0_PULLUDENABLE_1" newline bitfld.long 0x154 8. "VIN2A_CLK0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_CLK0_MODESELECT_0,VIN2A_CLK0_MODESELECT_1" newline bitfld.long 0x154 4.--7. "VIN2A_CLK0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x154 0.--3. "VIN2A_CLK0_MUXMODE,- VIN2A_CLK0" "VIN2A_CLK0_MUXMODE_0,?,?,?,VIN2A_CLK0_MUXMODE_4,VIN2A_CLK0_MUXMODE_5,?,?,?,?,VIN2A_CLK0_MUXMODE_10,?,?,?,VIN2A_CLK0_MUXMODE_14,VIN2A_CLK0_MUXMODE_15" line.long 0x158 "CTRL_CORE_PAD_VIN2A_DE0," rbitfld.long 0x158 25. "VIN2A_DE0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_DE0_WAKEUPEVENT_0,VIN2A_DE0_WAKEUPEVENT_1" newline bitfld.long 0x158 24. "VIN2A_DE0_WAKEUPENABLE,- DISABLE" "VIN2A_DE0_WAKEUPENABLE_0,VIN2A_DE0_WAKEUPENABLE_1" newline bitfld.long 0x158 19. "VIN2A_DE0_SLEWCONTROL,- FAST_SLEW" "VIN2A_DE0_SLEWCONTROL_0,VIN2A_DE0_SLEWCONTROL_1" newline bitfld.long 0x158 18. "VIN2A_DE0_INPUTENABLE,- DISABLE" "VIN2A_DE0_INPUTENABLE_0,VIN2A_DE0_INPUTENABLE_1" newline bitfld.long 0x158 17. "VIN2A_DE0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_DE0_PULLTYPESELECT_0,VIN2A_DE0_PULLTYPESELECT_1" newline bitfld.long 0x158 16. "VIN2A_DE0_PULLUDENABLE,- ENABLE" "VIN2A_DE0_PULLUDENABLE_0,VIN2A_DE0_PULLUDENABLE_1" newline bitfld.long 0x158 8. "VIN2A_DE0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_DE0_MODESELECT_0,VIN2A_DE0_MODESELECT_1" newline bitfld.long 0x158 4.--7. "VIN2A_DE0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x158 0.--3. "VIN2A_DE0_MUXMODE,- VIN2A_DE0" "VIN2A_DE0_MUXMODE_0,VIN2A_DE0_MUXMODE_1,VIN2A_DE0_MUXMODE_2,VIN2A_DE0_MUXMODE_3,VIN2A_DE0_MUXMODE_4,VIN2A_DE0_MUXMODE_5,?,?,?,?,VIN2A_DE0_MUXMODE_10,?,?,?,VIN2A_DE0_MUXMODE_14,VIN2A_DE0_MUXMODE_15" line.long 0x15C "CTRL_CORE_PAD_VIN2A_FLD0," rbitfld.long 0x15C 25. "VIN2A_FLD0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_FLD0_WAKEUPEVENT_0,VIN2A_FLD0_WAKEUPEVENT_1" newline bitfld.long 0x15C 24. "VIN2A_FLD0_WAKEUPENABLE,- DISABLE" "VIN2A_FLD0_WAKEUPENABLE_0,VIN2A_FLD0_WAKEUPENABLE_1" newline bitfld.long 0x15C 19. "VIN2A_FLD0_SLEWCONTROL,- FAST_SLEW" "VIN2A_FLD0_SLEWCONTROL_0,VIN2A_FLD0_SLEWCONTROL_1" newline bitfld.long 0x15C 18. "VIN2A_FLD0_INPUTENABLE,- DISABLE" "VIN2A_FLD0_INPUTENABLE_0,VIN2A_FLD0_INPUTENABLE_1" newline bitfld.long 0x15C 17. "VIN2A_FLD0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_FLD0_PULLTYPESELECT_0,VIN2A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0x15C 16. "VIN2A_FLD0_PULLUDENABLE,- ENABLE" "VIN2A_FLD0_PULLUDENABLE_0,VIN2A_FLD0_PULLUDENABLE_1" newline bitfld.long 0x15C 8. "VIN2A_FLD0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_FLD0_MODESELECT_0,VIN2A_FLD0_MODESELECT_1" newline bitfld.long 0x15C 4.--7. "VIN2A_FLD0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x15C 0.--3. "VIN2A_FLD0_MUXMODE,- VIN2A_FLD0" "VIN2A_FLD0_MUXMODE_0,?,VIN2A_FLD0_MUXMODE_2,?,VIN2A_FLD0_MUXMODE_4,VIN2A_FLD0_MUXMODE_5,?,?,?,?,VIN2A_FLD0_MUXMODE_10,?,?,?,VIN2A_FLD0_MUXMODE_14,VIN2A_FLD0_MUXMODE_15" line.long 0x160 "CTRL_CORE_PAD_VIN2A_HSYNC0," rbitfld.long 0x160 25. "VIN2A_HSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_HSYNC0_WAKEUPEVENT_0,VIN2A_HSYNC0_WAKEUPEVENT_1" newline bitfld.long 0x160 24. "VIN2A_HSYNC0_WAKEUPENABLE,- DISABLE" "VIN2A_HSYNC0_WAKEUPENABLE_0,VIN2A_HSYNC0_WAKEUPENABLE_1" newline bitfld.long 0x160 19. "VIN2A_HSYNC0_SLEWCONTROL,- FAST_SLEW" "VIN2A_HSYNC0_SLEWCONTROL_0,VIN2A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0x160 18. "VIN2A_HSYNC0_INPUTENABLE,- DISABLE" "VIN2A_HSYNC0_INPUTENABLE_0,VIN2A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0x160 17. "VIN2A_HSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_HSYNC0_PULLTYPESELECT_0,VIN2A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x160 16. "VIN2A_HSYNC0_PULLUDENABLE,- ENABLE" "VIN2A_HSYNC0_PULLUDENABLE_0,VIN2A_HSYNC0_PULLUDENABLE_1" newline bitfld.long 0x160 8. "VIN2A_HSYNC0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_HSYNC0_MODESELECT_0,VIN2A_HSYNC0_MODESELECT_1" newline bitfld.long 0x160 4.--7. "VIN2A_HSYNC0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x160 0.--3. "VIN2A_HSYNC0_MUXMODE,- VIN2A_HSYNC0" "VIN2A_HSYNC0_MUXMODE_0,?,?,VIN2A_HSYNC0_MUXMODE_3,VIN2A_HSYNC0_MUXMODE_4,VIN2A_HSYNC0_MUXMODE_5,?,VIN2A_HSYNC0_MUXMODE_7,VIN2A_HSYNC0_MUXMODE_8,?,VIN2A_HSYNC0_MUXMODE_10,?,?,?,VIN2A_HSYNC0_MUXMODE_14,VIN2A_HSYNC0_MUXMODE_15" line.long 0x164 "CTRL_CORE_PAD_VIN2A_VSYNC0," rbitfld.long 0x164 25. "VIN2A_VSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_VSYNC0_WAKEUPEVENT_0,VIN2A_VSYNC0_WAKEUPEVENT_1" newline bitfld.long 0x164 24. "VIN2A_VSYNC0_WAKEUPENABLE,- DISABLE" "VIN2A_VSYNC0_WAKEUPENABLE_0,VIN2A_VSYNC0_WAKEUPENABLE_1" newline bitfld.long 0x164 19. "VIN2A_VSYNC0_SLEWCONTROL,- FAST_SLEW" "VIN2A_VSYNC0_SLEWCONTROL_0,VIN2A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0x164 18. "VIN2A_VSYNC0_INPUTENABLE,- DISABLE" "VIN2A_VSYNC0_INPUTENABLE_0,VIN2A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0x164 17. "VIN2A_VSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_VSYNC0_PULLTYPESELECT_0,VIN2A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x164 16. "VIN2A_VSYNC0_PULLUDENABLE,- ENABLE" "VIN2A_VSYNC0_PULLUDENABLE_0,VIN2A_VSYNC0_PULLUDENABLE_1" newline bitfld.long 0x164 8. "VIN2A_VSYNC0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_VSYNC0_MODESELECT_0,VIN2A_VSYNC0_MODESELECT_1" newline bitfld.long 0x164 4.--7. "VIN2A_VSYNC0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x164 0.--3. "VIN2A_VSYNC0_MUXMODE,- VIN2A_VSYNC0" "VIN2A_VSYNC0_MUXMODE_0,?,?,VIN2A_VSYNC0_MUXMODE_3,VIN2A_VSYNC0_MUXMODE_4,VIN2A_VSYNC0_MUXMODE_5,?,VIN2A_VSYNC0_MUXMODE_7,VIN2A_VSYNC0_MUXMODE_8,?,VIN2A_VSYNC0_MUXMODE_10,?,?,?,VIN2A_VSYNC0_MUXMODE_14,VIN2A_VSYNC0_MUXMODE_15" line.long 0x168 "CTRL_CORE_PAD_VIN2A_D0," rbitfld.long 0x168 25. "VIN2A_D0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D0_WAKEUPEVENT_0,VIN2A_D0_WAKEUPEVENT_1" newline bitfld.long 0x168 24. "VIN2A_D0_WAKEUPENABLE,- DISABLE" "VIN2A_D0_WAKEUPENABLE_0,VIN2A_D0_WAKEUPENABLE_1" newline bitfld.long 0x168 19. "VIN2A_D0_SLEWCONTROL,- FAST_SLEW" "VIN2A_D0_SLEWCONTROL_0,VIN2A_D0_SLEWCONTROL_1" newline bitfld.long 0x168 18. "VIN2A_D0_INPUTENABLE,- DISABLE" "VIN2A_D0_INPUTENABLE_0,VIN2A_D0_INPUTENABLE_1" newline bitfld.long 0x168 17. "VIN2A_D0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D0_PULLTYPESELECT_0,VIN2A_D0_PULLTYPESELECT_1" newline bitfld.long 0x168 16. "VIN2A_D0_PULLUDENABLE,- ENABLE" "VIN2A_D0_PULLUDENABLE_0,VIN2A_D0_PULLUDENABLE_1" newline bitfld.long 0x168 8. "VIN2A_D0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D0_MODESELECT_0,VIN2A_D0_MODESELECT_1" newline bitfld.long 0x168 4.--7. "VIN2A_D0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x168 0.--3. "VIN2A_D0_MUXMODE,- VIN2A_D0" "VIN2A_D0_MUXMODE_0,?,?,?,VIN2A_D0_MUXMODE_4,VIN2A_D0_MUXMODE_5,?,VIN2A_D0_MUXMODE_7,VIN2A_D0_MUXMODE_8,?,VIN2A_D0_MUXMODE_10,?,?,?,VIN2A_D0_MUXMODE_14,VIN2A_D0_MUXMODE_15" line.long 0x16C "CTRL_CORE_PAD_VIN2A_D1," rbitfld.long 0x16C 25. "VIN2A_D1_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D1_WAKEUPEVENT_0,VIN2A_D1_WAKEUPEVENT_1" newline bitfld.long 0x16C 24. "VIN2A_D1_WAKEUPENABLE,- DISABLE" "VIN2A_D1_WAKEUPENABLE_0,VIN2A_D1_WAKEUPENABLE_1" newline bitfld.long 0x16C 19. "VIN2A_D1_SLEWCONTROL,- FAST_SLEW" "VIN2A_D1_SLEWCONTROL_0,VIN2A_D1_SLEWCONTROL_1" newline bitfld.long 0x16C 18. "VIN2A_D1_INPUTENABLE,- DISABLE" "VIN2A_D1_INPUTENABLE_0,VIN2A_D1_INPUTENABLE_1" newline bitfld.long 0x16C 17. "VIN2A_D1_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D1_PULLTYPESELECT_0,VIN2A_D1_PULLTYPESELECT_1" newline bitfld.long 0x16C 16. "VIN2A_D1_PULLUDENABLE,- ENABLE" "VIN2A_D1_PULLUDENABLE_0,VIN2A_D1_PULLUDENABLE_1" newline bitfld.long 0x16C 8. "VIN2A_D1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D1_MODESELECT_0,VIN2A_D1_MODESELECT_1" newline bitfld.long 0x16C 4.--7. "VIN2A_D1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x16C 0.--3. "VIN2A_D1_MUXMODE,- VIN2A_D1" "VIN2A_D1_MUXMODE_0,?,?,?,VIN2A_D1_MUXMODE_4,VIN2A_D1_MUXMODE_5,?,VIN2A_D1_MUXMODE_7,VIN2A_D1_MUXMODE_8,?,VIN2A_D1_MUXMODE_10,?,?,?,VIN2A_D1_MUXMODE_14,VIN2A_D1_MUXMODE_15" line.long 0x170 "CTRL_CORE_PAD_VIN2A_D2," rbitfld.long 0x170 25. "VIN2A_D2_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D2_WAKEUPEVENT_0,VIN2A_D2_WAKEUPEVENT_1" newline bitfld.long 0x170 24. "VIN2A_D2_WAKEUPENABLE,- DISABLE" "VIN2A_D2_WAKEUPENABLE_0,VIN2A_D2_WAKEUPENABLE_1" newline bitfld.long 0x170 19. "VIN2A_D2_SLEWCONTROL,- FAST_SLEW" "VIN2A_D2_SLEWCONTROL_0,VIN2A_D2_SLEWCONTROL_1" newline bitfld.long 0x170 18. "VIN2A_D2_INPUTENABLE,- DISABLE" "VIN2A_D2_INPUTENABLE_0,VIN2A_D2_INPUTENABLE_1" newline bitfld.long 0x170 17. "VIN2A_D2_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D2_PULLTYPESELECT_0,VIN2A_D2_PULLTYPESELECT_1" newline bitfld.long 0x170 16. "VIN2A_D2_PULLUDENABLE,- ENABLE" "VIN2A_D2_PULLUDENABLE_0,VIN2A_D2_PULLUDENABLE_1" newline bitfld.long 0x170 8. "VIN2A_D2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D2_MODESELECT_0,VIN2A_D2_MODESELECT_1" newline bitfld.long 0x170 4.--7. "VIN2A_D2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x170 0.--3. "VIN2A_D2_MUXMODE,- VIN2A_D2" "VIN2A_D2_MUXMODE_0,?,?,?,VIN2A_D2_MUXMODE_4,VIN2A_D2_MUXMODE_5,?,?,VIN2A_D2_MUXMODE_8,?,VIN2A_D2_MUXMODE_10,?,?,?,VIN2A_D2_MUXMODE_14,VIN2A_D2_MUXMODE_15" line.long 0x174 "CTRL_CORE_PAD_VIN2A_D3," rbitfld.long 0x174 25. "VIN2A_D3_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D3_WAKEUPEVENT_0,VIN2A_D3_WAKEUPEVENT_1" newline bitfld.long 0x174 24. "VIN2A_D3_WAKEUPENABLE,- DISABLE" "VIN2A_D3_WAKEUPENABLE_0,VIN2A_D3_WAKEUPENABLE_1" newline bitfld.long 0x174 19. "VIN2A_D3_SLEWCONTROL,- FAST_SLEW" "VIN2A_D3_SLEWCONTROL_0,VIN2A_D3_SLEWCONTROL_1" newline bitfld.long 0x174 18. "VIN2A_D3_INPUTENABLE,- DISABLE" "VIN2A_D3_INPUTENABLE_0,VIN2A_D3_INPUTENABLE_1" newline bitfld.long 0x174 17. "VIN2A_D3_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D3_PULLTYPESELECT_0,VIN2A_D3_PULLTYPESELECT_1" newline bitfld.long 0x174 16. "VIN2A_D3_PULLUDENABLE,- ENABLE" "VIN2A_D3_PULLUDENABLE_0,VIN2A_D3_PULLUDENABLE_1" newline bitfld.long 0x174 8. "VIN2A_D3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D3_MODESELECT_0,VIN2A_D3_MODESELECT_1" newline bitfld.long 0x174 4.--7. "VIN2A_D3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x174 0.--3. "VIN2A_D3_MUXMODE,- VIN2A_D3" "VIN2A_D3_MUXMODE_0,?,?,?,VIN2A_D3_MUXMODE_4,VIN2A_D3_MUXMODE_5,?,?,VIN2A_D3_MUXMODE_8,?,VIN2A_D3_MUXMODE_10,?,?,?,VIN2A_D3_MUXMODE_14,VIN2A_D3_MUXMODE_15" line.long 0x178 "CTRL_CORE_PAD_VIN2A_D4," rbitfld.long 0x178 25. "VIN2A_D4_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D4_WAKEUPEVENT_0,VIN2A_D4_WAKEUPEVENT_1" newline bitfld.long 0x178 24. "VIN2A_D4_WAKEUPENABLE,- DISABLE" "VIN2A_D4_WAKEUPENABLE_0,VIN2A_D4_WAKEUPENABLE_1" newline bitfld.long 0x178 19. "VIN2A_D4_SLEWCONTROL,- FAST_SLEW" "VIN2A_D4_SLEWCONTROL_0,VIN2A_D4_SLEWCONTROL_1" newline bitfld.long 0x178 18. "VIN2A_D4_INPUTENABLE,- DISABLE" "VIN2A_D4_INPUTENABLE_0,VIN2A_D4_INPUTENABLE_1" newline bitfld.long 0x178 17. "VIN2A_D4_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D4_PULLTYPESELECT_0,VIN2A_D4_PULLTYPESELECT_1" newline bitfld.long 0x178 16. "VIN2A_D4_PULLUDENABLE,- ENABLE" "VIN2A_D4_PULLUDENABLE_0,VIN2A_D4_PULLUDENABLE_1" newline bitfld.long 0x178 8. "VIN2A_D4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D4_MODESELECT_0,VIN2A_D4_MODESELECT_1" newline bitfld.long 0x178 4.--7. "VIN2A_D4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x178 0.--3. "VIN2A_D4_MUXMODE,- VIN2A_D4" "VIN2A_D4_MUXMODE_0,?,?,?,VIN2A_D4_MUXMODE_4,VIN2A_D4_MUXMODE_5,?,?,VIN2A_D4_MUXMODE_8,?,VIN2A_D4_MUXMODE_10,?,?,?,VIN2A_D4_MUXMODE_14,VIN2A_D4_MUXMODE_15" line.long 0x17C "CTRL_CORE_PAD_VIN2A_D5," rbitfld.long 0x17C 25. "VIN2A_D5_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D5_WAKEUPEVENT_0,VIN2A_D5_WAKEUPEVENT_1" newline bitfld.long 0x17C 24. "VIN2A_D5_WAKEUPENABLE,- DISABLE" "VIN2A_D5_WAKEUPENABLE_0,VIN2A_D5_WAKEUPENABLE_1" newline bitfld.long 0x17C 19. "VIN2A_D5_SLEWCONTROL,- FAST_SLEW" "VIN2A_D5_SLEWCONTROL_0,VIN2A_D5_SLEWCONTROL_1" newline bitfld.long 0x17C 18. "VIN2A_D5_INPUTENABLE,- DISABLE" "VIN2A_D5_INPUTENABLE_0,VIN2A_D5_INPUTENABLE_1" newline bitfld.long 0x17C 17. "VIN2A_D5_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D5_PULLTYPESELECT_0,VIN2A_D5_PULLTYPESELECT_1" newline bitfld.long 0x17C 16. "VIN2A_D5_PULLUDENABLE,- ENABLE" "VIN2A_D5_PULLUDENABLE_0,VIN2A_D5_PULLUDENABLE_1" newline bitfld.long 0x17C 8. "VIN2A_D5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D5_MODESELECT_0,VIN2A_D5_MODESELECT_1" newline bitfld.long 0x17C 4.--7. "VIN2A_D5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x17C 0.--3. "VIN2A_D5_MUXMODE,- VIN2A_D5" "VIN2A_D5_MUXMODE_0,?,?,?,VIN2A_D5_MUXMODE_4,VIN2A_D5_MUXMODE_5,?,?,VIN2A_D5_MUXMODE_8,?,VIN2A_D5_MUXMODE_10,?,?,?,VIN2A_D5_MUXMODE_14,VIN2A_D5_MUXMODE_15" line.long 0x180 "CTRL_CORE_PAD_VIN2A_D6," rbitfld.long 0x180 25. "VIN2A_D6_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D6_WAKEUPEVENT_0,VIN2A_D6_WAKEUPEVENT_1" newline bitfld.long 0x180 24. "VIN2A_D6_WAKEUPENABLE,- DISABLE" "VIN2A_D6_WAKEUPENABLE_0,VIN2A_D6_WAKEUPENABLE_1" newline bitfld.long 0x180 19. "VIN2A_D6_SLEWCONTROL,- FAST_SLEW" "VIN2A_D6_SLEWCONTROL_0,VIN2A_D6_SLEWCONTROL_1" newline bitfld.long 0x180 18. "VIN2A_D6_INPUTENABLE,- DISABLE" "VIN2A_D6_INPUTENABLE_0,VIN2A_D6_INPUTENABLE_1" newline bitfld.long 0x180 17. "VIN2A_D6_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D6_PULLTYPESELECT_0,VIN2A_D6_PULLTYPESELECT_1" newline bitfld.long 0x180 16. "VIN2A_D6_PULLUDENABLE,- ENABLE" "VIN2A_D6_PULLUDENABLE_0,VIN2A_D6_PULLUDENABLE_1" newline bitfld.long 0x180 8. "VIN2A_D6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D6_MODESELECT_0,VIN2A_D6_MODESELECT_1" newline bitfld.long 0x180 4.--7. "VIN2A_D6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x180 0.--3. "VIN2A_D6_MUXMODE,- VIN2A_D6" "VIN2A_D6_MUXMODE_0,?,?,?,VIN2A_D6_MUXMODE_4,VIN2A_D6_MUXMODE_5,?,?,VIN2A_D6_MUXMODE_8,?,VIN2A_D6_MUXMODE_10,?,?,?,VIN2A_D6_MUXMODE_14,VIN2A_D6_MUXMODE_15" line.long 0x184 "CTRL_CORE_PAD_VIN2A_D7," rbitfld.long 0x184 25. "VIN2A_D7_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D7_WAKEUPEVENT_0,VIN2A_D7_WAKEUPEVENT_1" newline bitfld.long 0x184 24. "VIN2A_D7_WAKEUPENABLE,- DISABLE" "VIN2A_D7_WAKEUPENABLE_0,VIN2A_D7_WAKEUPENABLE_1" newline bitfld.long 0x184 19. "VIN2A_D7_SLEWCONTROL,- FAST_SLEW" "VIN2A_D7_SLEWCONTROL_0,VIN2A_D7_SLEWCONTROL_1" newline bitfld.long 0x184 18. "VIN2A_D7_INPUTENABLE,- DISABLE" "VIN2A_D7_INPUTENABLE_0,VIN2A_D7_INPUTENABLE_1" newline bitfld.long 0x184 17. "VIN2A_D7_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D7_PULLTYPESELECT_0,VIN2A_D7_PULLTYPESELECT_1" newline bitfld.long 0x184 16. "VIN2A_D7_PULLUDENABLE,- ENABLE" "VIN2A_D7_PULLUDENABLE_0,VIN2A_D7_PULLUDENABLE_1" newline bitfld.long 0x184 8. "VIN2A_D7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D7_MODESELECT_0,VIN2A_D7_MODESELECT_1" newline bitfld.long 0x184 4.--7. "VIN2A_D7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x184 0.--3. "VIN2A_D7_MUXMODE,- VIN2A_D7" "VIN2A_D7_MUXMODE_0,?,?,?,VIN2A_D7_MUXMODE_4,VIN2A_D7_MUXMODE_5,?,?,VIN2A_D7_MUXMODE_8,?,VIN2A_D7_MUXMODE_10,?,?,?,VIN2A_D7_MUXMODE_14,VIN2A_D7_MUXMODE_15" line.long 0x188 "CTRL_CORE_PAD_VIN2A_D8," rbitfld.long 0x188 25. "VIN2A_D8_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D8_WAKEUPEVENT_0,VIN2A_D8_WAKEUPEVENT_1" newline bitfld.long 0x188 24. "VIN2A_D8_WAKEUPENABLE,- DISABLE" "VIN2A_D8_WAKEUPENABLE_0,VIN2A_D8_WAKEUPENABLE_1" newline bitfld.long 0x188 19. "VIN2A_D8_SLEWCONTROL,- FAST_SLEW" "VIN2A_D8_SLEWCONTROL_0,VIN2A_D8_SLEWCONTROL_1" newline bitfld.long 0x188 18. "VIN2A_D8_INPUTENABLE,- DISABLE" "VIN2A_D8_INPUTENABLE_0,VIN2A_D8_INPUTENABLE_1" newline bitfld.long 0x188 17. "VIN2A_D8_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D8_PULLTYPESELECT_0,VIN2A_D8_PULLTYPESELECT_1" newline bitfld.long 0x188 16. "VIN2A_D8_PULLUDENABLE,- ENABLE" "VIN2A_D8_PULLUDENABLE_0,VIN2A_D8_PULLUDENABLE_1" newline bitfld.long 0x188 8. "VIN2A_D8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D8_MODESELECT_0,VIN2A_D8_MODESELECT_1" newline bitfld.long 0x188 4.--7. "VIN2A_D8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x188 0.--3. "VIN2A_D8_MUXMODE,- VIN2A_D8" "VIN2A_D8_MUXMODE_0,?,?,?,VIN2A_D8_MUXMODE_4,VIN2A_D8_MUXMODE_5,?,?,VIN2A_D8_MUXMODE_8,?,VIN2A_D8_MUXMODE_10,?,?,?,VIN2A_D8_MUXMODE_14,VIN2A_D8_MUXMODE_15" line.long 0x18C "CTRL_CORE_PAD_VIN2A_D9," rbitfld.long 0x18C 25. "VIN2A_D9_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D9_WAKEUPEVENT_0,VIN2A_D9_WAKEUPEVENT_1" newline bitfld.long 0x18C 24. "VIN2A_D9_WAKEUPENABLE,- DISABLE" "VIN2A_D9_WAKEUPENABLE_0,VIN2A_D9_WAKEUPENABLE_1" newline bitfld.long 0x18C 19. "VIN2A_D9_SLEWCONTROL,- FAST_SLEW" "VIN2A_D9_SLEWCONTROL_0,VIN2A_D9_SLEWCONTROL_1" newline bitfld.long 0x18C 18. "VIN2A_D9_INPUTENABLE,- DISABLE" "VIN2A_D9_INPUTENABLE_0,VIN2A_D9_INPUTENABLE_1" newline bitfld.long 0x18C 17. "VIN2A_D9_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D9_PULLTYPESELECT_0,VIN2A_D9_PULLTYPESELECT_1" newline bitfld.long 0x18C 16. "VIN2A_D9_PULLUDENABLE,- ENABLE" "VIN2A_D9_PULLUDENABLE_0,VIN2A_D9_PULLUDENABLE_1" newline bitfld.long 0x18C 8. "VIN2A_D9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D9_MODESELECT_0,VIN2A_D9_MODESELECT_1" newline bitfld.long 0x18C 4.--7. "VIN2A_D9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18C 0.--3. "VIN2A_D9_MUXMODE,- VIN2A_D9" "VIN2A_D9_MUXMODE_0,?,?,?,VIN2A_D9_MUXMODE_4,VIN2A_D9_MUXMODE_5,?,?,VIN2A_D9_MUXMODE_8,?,VIN2A_D9_MUXMODE_10,?,?,?,VIN2A_D9_MUXMODE_14,VIN2A_D9_MUXMODE_15" line.long 0x190 "CTRL_CORE_PAD_VIN2A_D10," rbitfld.long 0x190 25. "VIN2A_D10_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D10_WAKEUPEVENT_0,VIN2A_D10_WAKEUPEVENT_1" newline bitfld.long 0x190 24. "VIN2A_D10_WAKEUPENABLE,- DISABLE" "VIN2A_D10_WAKEUPENABLE_0,VIN2A_D10_WAKEUPENABLE_1" newline bitfld.long 0x190 19. "VIN2A_D10_SLEWCONTROL,- FAST_SLEW" "VIN2A_D10_SLEWCONTROL_0,VIN2A_D10_SLEWCONTROL_1" newline bitfld.long 0x190 18. "VIN2A_D10_INPUTENABLE,- DISABLE" "VIN2A_D10_INPUTENABLE_0,VIN2A_D10_INPUTENABLE_1" newline bitfld.long 0x190 17. "VIN2A_D10_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D10_PULLTYPESELECT_0,VIN2A_D10_PULLTYPESELECT_1" newline bitfld.long 0x190 16. "VIN2A_D10_PULLUDENABLE,- ENABLE" "VIN2A_D10_PULLUDENABLE_0,VIN2A_D10_PULLUDENABLE_1" newline bitfld.long 0x190 8. "VIN2A_D10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D10_MODESELECT_0,VIN2A_D10_MODESELECT_1" newline bitfld.long 0x190 4.--7. "VIN2A_D10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x190 0.--3. "VIN2A_D10_MUXMODE,- VIN2A_D10" "VIN2A_D10_MUXMODE_0,?,?,VIN2A_D10_MUXMODE_3,VIN2A_D10_MUXMODE_4,?,?,?,?,?,VIN2A_D10_MUXMODE_10,?,?,?,VIN2A_D10_MUXMODE_14,VIN2A_D10_MUXMODE_15" line.long 0x194 "CTRL_CORE_PAD_VIN2A_D11," rbitfld.long 0x194 25. "VIN2A_D11_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D11_WAKEUPEVENT_0,VIN2A_D11_WAKEUPEVENT_1" newline bitfld.long 0x194 24. "VIN2A_D11_WAKEUPENABLE,- DISABLE" "VIN2A_D11_WAKEUPENABLE_0,VIN2A_D11_WAKEUPENABLE_1" newline bitfld.long 0x194 19. "VIN2A_D11_SLEWCONTROL,- FAST_SLEW" "VIN2A_D11_SLEWCONTROL_0,VIN2A_D11_SLEWCONTROL_1" newline bitfld.long 0x194 18. "VIN2A_D11_INPUTENABLE,- DISABLE" "VIN2A_D11_INPUTENABLE_0,VIN2A_D11_INPUTENABLE_1" newline bitfld.long 0x194 17. "VIN2A_D11_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D11_PULLTYPESELECT_0,VIN2A_D11_PULLTYPESELECT_1" newline bitfld.long 0x194 16. "VIN2A_D11_PULLUDENABLE,- ENABLE" "VIN2A_D11_PULLUDENABLE_0,VIN2A_D11_PULLUDENABLE_1" newline bitfld.long 0x194 8. "VIN2A_D11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D11_MODESELECT_0,VIN2A_D11_MODESELECT_1" newline bitfld.long 0x194 4.--7. "VIN2A_D11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x194 0.--3. "VIN2A_D11_MUXMODE,- VIN2A_D11" "VIN2A_D11_MUXMODE_0,?,?,VIN2A_D11_MUXMODE_3,VIN2A_D11_MUXMODE_4,?,?,?,?,?,VIN2A_D11_MUXMODE_10,?,?,?,VIN2A_D11_MUXMODE_14,VIN2A_D11_MUXMODE_15" line.long 0x198 "CTRL_CORE_PAD_VIN2A_D12," rbitfld.long 0x198 25. "VIN2A_D12_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D12_WAKEUPEVENT_0,VIN2A_D12_WAKEUPEVENT_1" newline bitfld.long 0x198 24. "VIN2A_D12_WAKEUPENABLE,- DISABLE" "VIN2A_D12_WAKEUPENABLE_0,VIN2A_D12_WAKEUPENABLE_1" newline bitfld.long 0x198 19. "VIN2A_D12_SLEWCONTROL,- FAST_SLEW" "VIN2A_D12_SLEWCONTROL_0,VIN2A_D12_SLEWCONTROL_1" newline bitfld.long 0x198 18. "VIN2A_D12_INPUTENABLE,- DISABLE" "VIN2A_D12_INPUTENABLE_0,VIN2A_D12_INPUTENABLE_1" newline bitfld.long 0x198 17. "VIN2A_D12_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D12_PULLTYPESELECT_0,VIN2A_D12_PULLTYPESELECT_1" newline bitfld.long 0x198 16. "VIN2A_D12_PULLUDENABLE,- ENABLE" "VIN2A_D12_PULLUDENABLE_0,VIN2A_D12_PULLUDENABLE_1" newline bitfld.long 0x198 8. "VIN2A_D12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D12_MODESELECT_0,VIN2A_D12_MODESELECT_1" newline bitfld.long 0x198 4.--7. "VIN2A_D12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x198 0.--3. "VIN2A_D12_MUXMODE,- VIN2A_D12" "VIN2A_D12_MUXMODE_0,?,?,VIN2A_D12_MUXMODE_3,VIN2A_D12_MUXMODE_4,?,?,?,VIN2A_D12_MUXMODE_8,?,VIN2A_D12_MUXMODE_10,?,?,?,VIN2A_D12_MUXMODE_14,VIN2A_D12_MUXMODE_15" line.long 0x19C "CTRL_CORE_PAD_VIN2A_D13," rbitfld.long 0x19C 25. "VIN2A_D13_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D13_WAKEUPEVENT_0,VIN2A_D13_WAKEUPEVENT_1" newline bitfld.long 0x19C 24. "VIN2A_D13_WAKEUPENABLE,- DISABLE" "VIN2A_D13_WAKEUPENABLE_0,VIN2A_D13_WAKEUPENABLE_1" newline bitfld.long 0x19C 19. "VIN2A_D13_SLEWCONTROL,- FAST_SLEW" "VIN2A_D13_SLEWCONTROL_0,VIN2A_D13_SLEWCONTROL_1" newline bitfld.long 0x19C 18. "VIN2A_D13_INPUTENABLE,- DISABLE" "VIN2A_D13_INPUTENABLE_0,VIN2A_D13_INPUTENABLE_1" newline bitfld.long 0x19C 17. "VIN2A_D13_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D13_PULLTYPESELECT_0,VIN2A_D13_PULLTYPESELECT_1" newline bitfld.long 0x19C 16. "VIN2A_D13_PULLUDENABLE,- ENABLE" "VIN2A_D13_PULLUDENABLE_0,VIN2A_D13_PULLUDENABLE_1" newline bitfld.long 0x19C 8. "VIN2A_D13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D13_MODESELECT_0,VIN2A_D13_MODESELECT_1" newline bitfld.long 0x19C 4.--7. "VIN2A_D13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x19C 0.--3. "VIN2A_D13_MUXMODE,- VIN2A_D13" "VIN2A_D13_MUXMODE_0,?,?,VIN2A_D13_MUXMODE_3,VIN2A_D13_MUXMODE_4,?,?,?,VIN2A_D13_MUXMODE_8,?,VIN2A_D13_MUXMODE_10,?,?,?,VIN2A_D13_MUXMODE_14,VIN2A_D13_MUXMODE_15" line.long 0x1A0 "CTRL_CORE_PAD_VIN2A_D14," rbitfld.long 0x1A0 25. "VIN2A_D14_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D14_WAKEUPEVENT_0,VIN2A_D14_WAKEUPEVENT_1" newline bitfld.long 0x1A0 24. "VIN2A_D14_WAKEUPENABLE,- DISABLE" "VIN2A_D14_WAKEUPENABLE_0,VIN2A_D14_WAKEUPENABLE_1" newline bitfld.long 0x1A0 19. "VIN2A_D14_SLEWCONTROL,- FAST_SLEW" "VIN2A_D14_SLEWCONTROL_0,VIN2A_D14_SLEWCONTROL_1" newline bitfld.long 0x1A0 18. "VIN2A_D14_INPUTENABLE,- DISABLE" "VIN2A_D14_INPUTENABLE_0,VIN2A_D14_INPUTENABLE_1" newline bitfld.long 0x1A0 17. "VIN2A_D14_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D14_PULLTYPESELECT_0,VIN2A_D14_PULLTYPESELECT_1" newline bitfld.long 0x1A0 16. "VIN2A_D14_PULLUDENABLE,- ENABLE" "VIN2A_D14_PULLUDENABLE_0,VIN2A_D14_PULLUDENABLE_1" newline bitfld.long 0x1A0 8. "VIN2A_D14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D14_MODESELECT_0,VIN2A_D14_MODESELECT_1" newline bitfld.long 0x1A0 4.--7. "VIN2A_D14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A0 0.--3. "VIN2A_D14_MUXMODE,- VIN2A_D14" "VIN2A_D14_MUXMODE_0,?,?,VIN2A_D14_MUXMODE_3,VIN2A_D14_MUXMODE_4,?,?,?,VIN2A_D14_MUXMODE_8,?,VIN2A_D14_MUXMODE_10,?,?,?,VIN2A_D14_MUXMODE_14,VIN2A_D14_MUXMODE_15" line.long 0x1A4 "CTRL_CORE_PAD_VIN2A_D15," rbitfld.long 0x1A4 25. "VIN2A_D15_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D15_WAKEUPEVENT_0,VIN2A_D15_WAKEUPEVENT_1" newline bitfld.long 0x1A4 24. "VIN2A_D15_WAKEUPENABLE,- DISABLE" "VIN2A_D15_WAKEUPENABLE_0,VIN2A_D15_WAKEUPENABLE_1" newline bitfld.long 0x1A4 19. "VIN2A_D15_SLEWCONTROL,- FAST_SLEW" "VIN2A_D15_SLEWCONTROL_0,VIN2A_D15_SLEWCONTROL_1" newline bitfld.long 0x1A4 18. "VIN2A_D15_INPUTENABLE,- DISABLE" "VIN2A_D15_INPUTENABLE_0,VIN2A_D15_INPUTENABLE_1" newline bitfld.long 0x1A4 17. "VIN2A_D15_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D15_PULLTYPESELECT_0,VIN2A_D15_PULLTYPESELECT_1" newline bitfld.long 0x1A4 16. "VIN2A_D15_PULLUDENABLE,- ENABLE" "VIN2A_D15_PULLUDENABLE_0,VIN2A_D15_PULLUDENABLE_1" newline bitfld.long 0x1A4 8. "VIN2A_D15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D15_MODESELECT_0,VIN2A_D15_MODESELECT_1" newline bitfld.long 0x1A4 4.--7. "VIN2A_D15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A4 0.--3. "VIN2A_D15_MUXMODE,- VIN2A_D15" "VIN2A_D15_MUXMODE_0,?,?,VIN2A_D15_MUXMODE_3,VIN2A_D15_MUXMODE_4,?,?,?,VIN2A_D15_MUXMODE_8,?,VIN2A_D15_MUXMODE_10,?,?,?,VIN2A_D15_MUXMODE_14,VIN2A_D15_MUXMODE_15" line.long 0x1A8 "CTRL_CORE_PAD_VIN2A_D16," rbitfld.long 0x1A8 25. "VIN2A_D16_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D16_WAKEUPEVENT_0,VIN2A_D16_WAKEUPEVENT_1" newline bitfld.long 0x1A8 24. "VIN2A_D16_WAKEUPENABLE,- DISABLE" "VIN2A_D16_WAKEUPENABLE_0,VIN2A_D16_WAKEUPENABLE_1" newline bitfld.long 0x1A8 19. "VIN2A_D16_SLEWCONTROL,- FAST_SLEW" "VIN2A_D16_SLEWCONTROL_0,VIN2A_D16_SLEWCONTROL_1" newline bitfld.long 0x1A8 18. "VIN2A_D16_INPUTENABLE,- DISABLE" "VIN2A_D16_INPUTENABLE_0,VIN2A_D16_INPUTENABLE_1" newline bitfld.long 0x1A8 17. "VIN2A_D16_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D16_PULLTYPESELECT_0,VIN2A_D16_PULLTYPESELECT_1" newline bitfld.long 0x1A8 16. "VIN2A_D16_PULLUDENABLE,- ENABLE" "VIN2A_D16_PULLUDENABLE_0,VIN2A_D16_PULLUDENABLE_1" newline bitfld.long 0x1A8 8. "VIN2A_D16_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D16_MODESELECT_0,VIN2A_D16_MODESELECT_1" newline bitfld.long 0x1A8 4.--7. "VIN2A_D16_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A8 0.--3. "VIN2A_D16_MUXMODE,- VIN2A_D16" "VIN2A_D16_MUXMODE_0,?,VIN2A_D16_MUXMODE_2,VIN2A_D16_MUXMODE_3,VIN2A_D16_MUXMODE_4,?,VIN2A_D16_MUXMODE_6,?,VIN2A_D16_MUXMODE_8,?,VIN2A_D16_MUXMODE_10,?,?,?,VIN2A_D16_MUXMODE_14,VIN2A_D16_MUXMODE_15" line.long 0x1AC "CTRL_CORE_PAD_VIN2A_D17," rbitfld.long 0x1AC 25. "VIN2A_D17_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D17_WAKEUPEVENT_0,VIN2A_D17_WAKEUPEVENT_1" newline bitfld.long 0x1AC 24. "VIN2A_D17_WAKEUPENABLE,- DISABLE" "VIN2A_D17_WAKEUPENABLE_0,VIN2A_D17_WAKEUPENABLE_1" newline bitfld.long 0x1AC 19. "VIN2A_D17_SLEWCONTROL,- FAST_SLEW" "VIN2A_D17_SLEWCONTROL_0,VIN2A_D17_SLEWCONTROL_1" newline bitfld.long 0x1AC 18. "VIN2A_D17_INPUTENABLE,- DISABLE" "VIN2A_D17_INPUTENABLE_0,VIN2A_D17_INPUTENABLE_1" newline bitfld.long 0x1AC 17. "VIN2A_D17_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D17_PULLTYPESELECT_0,VIN2A_D17_PULLTYPESELECT_1" newline bitfld.long 0x1AC 16. "VIN2A_D17_PULLUDENABLE,- ENABLE" "VIN2A_D17_PULLUDENABLE_0,VIN2A_D17_PULLUDENABLE_1" newline bitfld.long 0x1AC 8. "VIN2A_D17_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D17_MODESELECT_0,VIN2A_D17_MODESELECT_1" newline bitfld.long 0x1AC 4.--7. "VIN2A_D17_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1AC 0.--3. "VIN2A_D17_MUXMODE,- VIN2A_D17" "VIN2A_D17_MUXMODE_0,?,VIN2A_D17_MUXMODE_2,VIN2A_D17_MUXMODE_3,VIN2A_D17_MUXMODE_4,?,VIN2A_D17_MUXMODE_6,?,VIN2A_D17_MUXMODE_8,?,VIN2A_D17_MUXMODE_10,?,?,?,VIN2A_D17_MUXMODE_14,VIN2A_D17_MUXMODE_15" line.long 0x1B0 "CTRL_CORE_PAD_VIN2A_D18," rbitfld.long 0x1B0 25. "VIN2A_D18_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D18_WAKEUPEVENT_0,VIN2A_D18_WAKEUPEVENT_1" newline bitfld.long 0x1B0 24. "VIN2A_D18_WAKEUPENABLE,- DISABLE" "VIN2A_D18_WAKEUPENABLE_0,VIN2A_D18_WAKEUPENABLE_1" newline bitfld.long 0x1B0 19. "VIN2A_D18_SLEWCONTROL,- FAST_SLEW" "VIN2A_D18_SLEWCONTROL_0,VIN2A_D18_SLEWCONTROL_1" newline bitfld.long 0x1B0 18. "VIN2A_D18_INPUTENABLE,- DISABLE" "VIN2A_D18_INPUTENABLE_0,VIN2A_D18_INPUTENABLE_1" newline bitfld.long 0x1B0 17. "VIN2A_D18_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D18_PULLTYPESELECT_0,VIN2A_D18_PULLTYPESELECT_1" newline bitfld.long 0x1B0 16. "VIN2A_D18_PULLUDENABLE,- ENABLE" "VIN2A_D18_PULLUDENABLE_0,VIN2A_D18_PULLUDENABLE_1" newline bitfld.long 0x1B0 8. "VIN2A_D18_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D18_MODESELECT_0,VIN2A_D18_MODESELECT_1" newline bitfld.long 0x1B0 4.--7. "VIN2A_D18_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B0 0.--3. "VIN2A_D18_MUXMODE,- VIN2A_D18" "VIN2A_D18_MUXMODE_0,?,VIN2A_D18_MUXMODE_2,VIN2A_D18_MUXMODE_3,VIN2A_D18_MUXMODE_4,?,VIN2A_D18_MUXMODE_6,?,VIN2A_D18_MUXMODE_8,?,VIN2A_D18_MUXMODE_10,?,?,?,VIN2A_D18_MUXMODE_14,VIN2A_D18_MUXMODE_15" line.long 0x1B4 "CTRL_CORE_PAD_VIN2A_D19," rbitfld.long 0x1B4 25. "VIN2A_D19_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D19_WAKEUPEVENT_0,VIN2A_D19_WAKEUPEVENT_1" newline bitfld.long 0x1B4 24. "VIN2A_D19_WAKEUPENABLE,- DISABLE" "VIN2A_D19_WAKEUPENABLE_0,VIN2A_D19_WAKEUPENABLE_1" newline bitfld.long 0x1B4 19. "VIN2A_D19_SLEWCONTROL,- FAST_SLEW" "VIN2A_D19_SLEWCONTROL_0,VIN2A_D19_SLEWCONTROL_1" newline bitfld.long 0x1B4 18. "VIN2A_D19_INPUTENABLE,- DISABLE" "VIN2A_D19_INPUTENABLE_0,VIN2A_D19_INPUTENABLE_1" newline bitfld.long 0x1B4 17. "VIN2A_D19_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D19_PULLTYPESELECT_0,VIN2A_D19_PULLTYPESELECT_1" newline bitfld.long 0x1B4 16. "VIN2A_D19_PULLUDENABLE,- ENABLE" "VIN2A_D19_PULLUDENABLE_0,VIN2A_D19_PULLUDENABLE_1" newline bitfld.long 0x1B4 8. "VIN2A_D19_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D19_MODESELECT_0,VIN2A_D19_MODESELECT_1" newline bitfld.long 0x1B4 4.--7. "VIN2A_D19_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B4 0.--3. "VIN2A_D19_MUXMODE,- VIN2A_D19" "VIN2A_D19_MUXMODE_0,?,VIN2A_D19_MUXMODE_2,VIN2A_D19_MUXMODE_3,VIN2A_D19_MUXMODE_4,?,VIN2A_D19_MUXMODE_6,?,VIN2A_D19_MUXMODE_8,?,VIN2A_D19_MUXMODE_10,?,?,?,VIN2A_D19_MUXMODE_14,VIN2A_D19_MUXMODE_15" line.long 0x1B8 "CTRL_CORE_PAD_VIN2A_D20," rbitfld.long 0x1B8 25. "VIN2A_D20_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D20_WAKEUPEVENT_0,VIN2A_D20_WAKEUPEVENT_1" newline bitfld.long 0x1B8 24. "VIN2A_D20_WAKEUPENABLE,- DISABLE" "VIN2A_D20_WAKEUPENABLE_0,VIN2A_D20_WAKEUPENABLE_1" newline bitfld.long 0x1B8 19. "VIN2A_D20_SLEWCONTROL,- FAST_SLEW" "VIN2A_D20_SLEWCONTROL_0,VIN2A_D20_SLEWCONTROL_1" newline bitfld.long 0x1B8 18. "VIN2A_D20_INPUTENABLE,- DISABLE" "VIN2A_D20_INPUTENABLE_0,VIN2A_D20_INPUTENABLE_1" newline bitfld.long 0x1B8 17. "VIN2A_D20_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D20_PULLTYPESELECT_0,VIN2A_D20_PULLTYPESELECT_1" newline bitfld.long 0x1B8 16. "VIN2A_D20_PULLUDENABLE,- ENABLE" "VIN2A_D20_PULLUDENABLE_0,VIN2A_D20_PULLUDENABLE_1" newline bitfld.long 0x1B8 8. "VIN2A_D20_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D20_MODESELECT_0,VIN2A_D20_MODESELECT_1" newline bitfld.long 0x1B8 4.--7. "VIN2A_D20_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B8 0.--3. "VIN2A_D20_MUXMODE,- VIN2A_D20" "VIN2A_D20_MUXMODE_0,?,VIN2A_D20_MUXMODE_2,VIN2A_D20_MUXMODE_3,VIN2A_D20_MUXMODE_4,VIN2A_D20_MUXMODE_5,VIN2A_D20_MUXMODE_6,?,VIN2A_D20_MUXMODE_8,?,VIN2A_D20_MUXMODE_10,?,?,?,VIN2A_D20_MUXMODE_14,VIN2A_D20_MUXMODE_15" line.long 0x1BC "CTRL_CORE_PAD_VIN2A_D21," rbitfld.long 0x1BC 25. "VIN2A_D21_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D21_WAKEUPEVENT_0,VIN2A_D21_WAKEUPEVENT_1" newline bitfld.long 0x1BC 24. "VIN2A_D21_WAKEUPENABLE,- DISABLE" "VIN2A_D21_WAKEUPENABLE_0,VIN2A_D21_WAKEUPENABLE_1" newline bitfld.long 0x1BC 19. "VIN2A_D21_SLEWCONTROL,- FAST_SLEW" "VIN2A_D21_SLEWCONTROL_0,VIN2A_D21_SLEWCONTROL_1" newline bitfld.long 0x1BC 18. "VIN2A_D21_INPUTENABLE,- DISABLE" "VIN2A_D21_INPUTENABLE_0,VIN2A_D21_INPUTENABLE_1" newline bitfld.long 0x1BC 17. "VIN2A_D21_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D21_PULLTYPESELECT_0,VIN2A_D21_PULLTYPESELECT_1" newline bitfld.long 0x1BC 16. "VIN2A_D21_PULLUDENABLE,- ENABLE" "VIN2A_D21_PULLUDENABLE_0,VIN2A_D21_PULLUDENABLE_1" newline bitfld.long 0x1BC 8. "VIN2A_D21_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D21_MODESELECT_0,VIN2A_D21_MODESELECT_1" newline bitfld.long 0x1BC 4.--7. "VIN2A_D21_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1BC 0.--3. "VIN2A_D21_MUXMODE,- VIN2A_D21" "VIN2A_D21_MUXMODE_0,?,VIN2A_D21_MUXMODE_2,VIN2A_D21_MUXMODE_3,VIN2A_D21_MUXMODE_4,VIN2A_D21_MUXMODE_5,VIN2A_D21_MUXMODE_6,?,VIN2A_D21_MUXMODE_8,?,?,?,?,?,VIN2A_D21_MUXMODE_14,VIN2A_D21_MUXMODE_15" line.long 0x1C0 "CTRL_CORE_PAD_VIN2A_D22," rbitfld.long 0x1C0 25. "VIN2A_D22_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D22_WAKEUPEVENT_0,VIN2A_D22_WAKEUPEVENT_1" newline bitfld.long 0x1C0 24. "VIN2A_D22_WAKEUPENABLE,- DISABLE" "VIN2A_D22_WAKEUPENABLE_0,VIN2A_D22_WAKEUPENABLE_1" newline bitfld.long 0x1C0 19. "VIN2A_D22_SLEWCONTROL,- FAST_SLEW" "VIN2A_D22_SLEWCONTROL_0,VIN2A_D22_SLEWCONTROL_1" newline bitfld.long 0x1C0 18. "VIN2A_D22_INPUTENABLE,- DISABLE" "VIN2A_D22_INPUTENABLE_0,VIN2A_D22_INPUTENABLE_1" newline bitfld.long 0x1C0 17. "VIN2A_D22_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D22_PULLTYPESELECT_0,VIN2A_D22_PULLTYPESELECT_1" newline bitfld.long 0x1C0 16. "VIN2A_D22_PULLUDENABLE,- ENABLE" "VIN2A_D22_PULLUDENABLE_0,VIN2A_D22_PULLUDENABLE_1" newline bitfld.long 0x1C0 8. "VIN2A_D22_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D22_MODESELECT_0,VIN2A_D22_MODESELECT_1" newline bitfld.long 0x1C0 4.--7. "VIN2A_D22_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C0 0.--3. "VIN2A_D22_MUXMODE,- VIN2A_D22" "VIN2A_D22_MUXMODE_0,?,VIN2A_D22_MUXMODE_2,VIN2A_D22_MUXMODE_3,VIN2A_D22_MUXMODE_4,VIN2A_D22_MUXMODE_5,VIN2A_D22_MUXMODE_6,?,VIN2A_D22_MUXMODE_8,?,?,?,?,?,VIN2A_D22_MUXMODE_14,VIN2A_D22_MUXMODE_15" line.long 0x1C4 "CTRL_CORE_PAD_VIN2A_D23," rbitfld.long 0x1C4 25. "VIN2A_D23_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D23_WAKEUPEVENT_0,VIN2A_D23_WAKEUPEVENT_1" newline bitfld.long 0x1C4 24. "VIN2A_D23_WAKEUPENABLE,- DISABLE" "VIN2A_D23_WAKEUPENABLE_0,VIN2A_D23_WAKEUPENABLE_1" newline bitfld.long 0x1C4 19. "VIN2A_D23_SLEWCONTROL,- FAST_SLEW" "VIN2A_D23_SLEWCONTROL_0,VIN2A_D23_SLEWCONTROL_1" newline bitfld.long 0x1C4 18. "VIN2A_D23_INPUTENABLE,- DISABLE" "VIN2A_D23_INPUTENABLE_0,VIN2A_D23_INPUTENABLE_1" newline bitfld.long 0x1C4 17. "VIN2A_D23_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D23_PULLTYPESELECT_0,VIN2A_D23_PULLTYPESELECT_1" newline bitfld.long 0x1C4 16. "VIN2A_D23_PULLUDENABLE,- ENABLE" "VIN2A_D23_PULLUDENABLE_0,VIN2A_D23_PULLUDENABLE_1" newline bitfld.long 0x1C4 8. "VIN2A_D23_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VIN2A_D23_MODESELECT_0,VIN2A_D23_MODESELECT_1" newline bitfld.long 0x1C4 4.--7. "VIN2A_D23_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C4 0.--3. "VIN2A_D23_MUXMODE,- VIN2A_D23" "VIN2A_D23_MUXMODE_0,?,VIN2A_D23_MUXMODE_2,VIN2A_D23_MUXMODE_3,VIN2A_D23_MUXMODE_4,VIN2A_D23_MUXMODE_5,VIN2A_D23_MUXMODE_6,?,VIN2A_D23_MUXMODE_8,?,?,?,?,?,VIN2A_D23_MUXMODE_14,VIN2A_D23_MUXMODE_15" line.long 0x1C8 "CTRL_CORE_PAD_VOUT1_CLK," rbitfld.long 0x1C8 25. "VOUT1_CLK_WAKEUPEVENT,- NOWAKEUP" "VOUT1_CLK_WAKEUPEVENT_0,VOUT1_CLK_WAKEUPEVENT_1" newline bitfld.long 0x1C8 24. "VOUT1_CLK_WAKEUPENABLE,- DISABLE" "VOUT1_CLK_WAKEUPENABLE_0,VOUT1_CLK_WAKEUPENABLE_1" newline bitfld.long 0x1C8 19. "VOUT1_CLK_SLEWCONTROL,- FAST_SLEW" "VOUT1_CLK_SLEWCONTROL_0,VOUT1_CLK_SLEWCONTROL_1" newline bitfld.long 0x1C8 18. "VOUT1_CLK_INPUTENABLE,- DISABLE" "VOUT1_CLK_INPUTENABLE_0,VOUT1_CLK_INPUTENABLE_1" newline bitfld.long 0x1C8 17. "VOUT1_CLK_PULLTYPESELECT,- PULL_DOWN" "VOUT1_CLK_PULLTYPESELECT_0,VOUT1_CLK_PULLTYPESELECT_1" newline bitfld.long 0x1C8 16. "VOUT1_CLK_PULLUDENABLE,- ENABLE" "VOUT1_CLK_PULLUDENABLE_0,VOUT1_CLK_PULLUDENABLE_1" newline bitfld.long 0x1C8 8. "VOUT1_CLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_CLK_MODESELECT_0,VOUT1_CLK_MODESELECT_1" newline bitfld.long 0x1C8 4.--7. "VOUT1_CLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C8 0.--3. "VOUT1_CLK_MUXMODE,- VOUT1_CLK" "VOUT1_CLK_MUXMODE_0,?,?,VOUT1_CLK_MUXMODE_3,VOUT1_CLK_MUXMODE_4,?,?,?,VOUT1_CLK_MUXMODE_8,?,?,?,?,?,VOUT1_CLK_MUXMODE_14,VOUT1_CLK_MUXMODE_15" line.long 0x1CC "CTRL_CORE_PAD_VOUT1_DE," rbitfld.long 0x1CC 25. "VOUT1_DE_WAKEUPEVENT,- NOWAKEUP" "VOUT1_DE_WAKEUPEVENT_0,VOUT1_DE_WAKEUPEVENT_1" newline bitfld.long 0x1CC 24. "VOUT1_DE_WAKEUPENABLE,- DISABLE" "VOUT1_DE_WAKEUPENABLE_0,VOUT1_DE_WAKEUPENABLE_1" newline bitfld.long 0x1CC 19. "VOUT1_DE_SLEWCONTROL,- FAST_SLEW" "VOUT1_DE_SLEWCONTROL_0,VOUT1_DE_SLEWCONTROL_1" newline bitfld.long 0x1CC 18. "VOUT1_DE_INPUTENABLE,- DISABLE" "VOUT1_DE_INPUTENABLE_0,VOUT1_DE_INPUTENABLE_1" newline bitfld.long 0x1CC 17. "VOUT1_DE_PULLTYPESELECT,- PULL_DOWN" "VOUT1_DE_PULLTYPESELECT_0,VOUT1_DE_PULLTYPESELECT_1" newline bitfld.long 0x1CC 16. "VOUT1_DE_PULLUDENABLE,- ENABLE" "VOUT1_DE_PULLUDENABLE_0,VOUT1_DE_PULLUDENABLE_1" newline bitfld.long 0x1CC 8. "VOUT1_DE_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_DE_MODESELECT_0,VOUT1_DE_MODESELECT_1" newline bitfld.long 0x1CC 4.--7. "VOUT1_DE_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1CC 0.--3. "VOUT1_DE_MUXMODE,- VOUT1_DE" "VOUT1_DE_MUXMODE_0,?,?,VOUT1_DE_MUXMODE_3,VOUT1_DE_MUXMODE_4,?,?,?,VOUT1_DE_MUXMODE_8,?,?,?,?,?,VOUT1_DE_MUXMODE_14,VOUT1_DE_MUXMODE_15" line.long 0x1D0 "CTRL_CORE_PAD_VOUT1_FLD," rbitfld.long 0x1D0 25. "VOUT1_FLD_WAKEUPEVENT,- NOWAKEUP" "VOUT1_FLD_WAKEUPEVENT_0,VOUT1_FLD_WAKEUPEVENT_1" newline bitfld.long 0x1D0 24. "VOUT1_FLD_WAKEUPENABLE,- DISABLE" "VOUT1_FLD_WAKEUPENABLE_0,VOUT1_FLD_WAKEUPENABLE_1" newline bitfld.long 0x1D0 19. "VOUT1_FLD_SLEWCONTROL,- FAST_SLEW" "VOUT1_FLD_SLEWCONTROL_0,VOUT1_FLD_SLEWCONTROL_1" newline bitfld.long 0x1D0 18. "VOUT1_FLD_INPUTENABLE,- DISABLE" "VOUT1_FLD_INPUTENABLE_0,VOUT1_FLD_INPUTENABLE_1" newline bitfld.long 0x1D0 17. "VOUT1_FLD_PULLTYPESELECT,- PULL_DOWN" "VOUT1_FLD_PULLTYPESELECT_0,VOUT1_FLD_PULLTYPESELECT_1" newline bitfld.long 0x1D0 16. "VOUT1_FLD_PULLUDENABLE,- ENABLE" "VOUT1_FLD_PULLUDENABLE_0,VOUT1_FLD_PULLUDENABLE_1" newline bitfld.long 0x1D0 8. "VOUT1_FLD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_FLD_MODESELECT_0,VOUT1_FLD_MODESELECT_1" newline bitfld.long 0x1D0 4.--7. "VOUT1_FLD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D0 0.--3. "VOUT1_FLD_MUXMODE,- VOUT1_FLD" "VOUT1_FLD_MUXMODE_0,?,?,VOUT1_FLD_MUXMODE_3,VOUT1_FLD_MUXMODE_4,?,?,?,VOUT1_FLD_MUXMODE_8,?,?,?,?,?,VOUT1_FLD_MUXMODE_14,VOUT1_FLD_MUXMODE_15" line.long 0x1D4 "CTRL_CORE_PAD_VOUT1_HSYNC," rbitfld.long 0x1D4 25. "VOUT1_HSYNC_WAKEUPEVENT,- NOWAKEUP" "VOUT1_HSYNC_WAKEUPEVENT_0,VOUT1_HSYNC_WAKEUPEVENT_1" newline bitfld.long 0x1D4 24. "VOUT1_HSYNC_WAKEUPENABLE,- DISABLE" "VOUT1_HSYNC_WAKEUPENABLE_0,VOUT1_HSYNC_WAKEUPENABLE_1" newline bitfld.long 0x1D4 19. "VOUT1_HSYNC_SLEWCONTROL,- FAST_SLEW" "VOUT1_HSYNC_SLEWCONTROL_0,VOUT1_HSYNC_SLEWCONTROL_1" newline bitfld.long 0x1D4 18. "VOUT1_HSYNC_INPUTENABLE,- DISABLE" "VOUT1_HSYNC_INPUTENABLE_0,VOUT1_HSYNC_INPUTENABLE_1" newline bitfld.long 0x1D4 17. "VOUT1_HSYNC_PULLTYPESELECT,- PULL_DOWN" "VOUT1_HSYNC_PULLTYPESELECT_0,VOUT1_HSYNC_PULLTYPESELECT_1" newline bitfld.long 0x1D4 16. "VOUT1_HSYNC_PULLUDENABLE,- ENABLE" "VOUT1_HSYNC_PULLUDENABLE_0,VOUT1_HSYNC_PULLUDENABLE_1" newline bitfld.long 0x1D4 8. "VOUT1_HSYNC_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_HSYNC_MODESELECT_0,VOUT1_HSYNC_MODESELECT_1" newline bitfld.long 0x1D4 4.--7. "VOUT1_HSYNC_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D4 0.--3. "VOUT1_HSYNC_MUXMODE,- VOUT1_HSYNC" "VOUT1_HSYNC_MUXMODE_0,?,?,VOUT1_HSYNC_MUXMODE_3,VOUT1_HSYNC_MUXMODE_4,?,?,?,VOUT1_HSYNC_MUXMODE_8,?,?,?,?,?,VOUT1_HSYNC_MUXMODE_14,VOUT1_HSYNC_MUXMODE_15" line.long 0x1D8 "CTRL_CORE_PAD_VOUT1_VSYNC," rbitfld.long 0x1D8 25. "VOUT1_VSYNC_WAKEUPEVENT,- NOWAKEUP" "VOUT1_VSYNC_WAKEUPEVENT_0,VOUT1_VSYNC_WAKEUPEVENT_1" newline bitfld.long 0x1D8 24. "VOUT1_VSYNC_WAKEUPENABLE,- DISABLE" "VOUT1_VSYNC_WAKEUPENABLE_0,VOUT1_VSYNC_WAKEUPENABLE_1" newline bitfld.long 0x1D8 19. "VOUT1_VSYNC_SLEWCONTROL,- FAST_SLEW" "VOUT1_VSYNC_SLEWCONTROL_0,VOUT1_VSYNC_SLEWCONTROL_1" newline bitfld.long 0x1D8 18. "VOUT1_VSYNC_INPUTENABLE,- DISABLE" "VOUT1_VSYNC_INPUTENABLE_0,VOUT1_VSYNC_INPUTENABLE_1" newline bitfld.long 0x1D8 17. "VOUT1_VSYNC_PULLTYPESELECT,- PULL_DOWN" "VOUT1_VSYNC_PULLTYPESELECT_0,VOUT1_VSYNC_PULLTYPESELECT_1" newline bitfld.long 0x1D8 16. "VOUT1_VSYNC_PULLUDENABLE,- ENABLE" "VOUT1_VSYNC_PULLUDENABLE_0,VOUT1_VSYNC_PULLUDENABLE_1" newline bitfld.long 0x1D8 8. "VOUT1_VSYNC_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_VSYNC_MODESELECT_0,VOUT1_VSYNC_MODESELECT_1" newline bitfld.long 0x1D8 4.--7. "VOUT1_VSYNC_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D8 0.--3. "VOUT1_VSYNC_MUXMODE,- VOUT1_VSYNC" "VOUT1_VSYNC_MUXMODE_0,?,?,VOUT1_VSYNC_MUXMODE_3,VOUT1_VSYNC_MUXMODE_4,?,?,?,VOUT1_VSYNC_MUXMODE_8,?,?,?,?,?,VOUT1_VSYNC_MUXMODE_14,VOUT1_VSYNC_MUXMODE_15" line.long 0x1DC "CTRL_CORE_PAD_VOUT1_D0," rbitfld.long 0x1DC 25. "VOUT1_D0_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D0_WAKEUPEVENT_0,VOUT1_D0_WAKEUPEVENT_1" newline bitfld.long 0x1DC 24. "VOUT1_D0_WAKEUPENABLE,- DISABLE" "VOUT1_D0_WAKEUPENABLE_0,VOUT1_D0_WAKEUPENABLE_1" newline bitfld.long 0x1DC 19. "VOUT1_D0_SLEWCONTROL,- FAST_SLEW" "VOUT1_D0_SLEWCONTROL_0,VOUT1_D0_SLEWCONTROL_1" newline bitfld.long 0x1DC 18. "VOUT1_D0_INPUTENABLE,- DISABLE" "VOUT1_D0_INPUTENABLE_0,VOUT1_D0_INPUTENABLE_1" newline bitfld.long 0x1DC 17. "VOUT1_D0_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D0_PULLTYPESELECT_0,VOUT1_D0_PULLTYPESELECT_1" newline bitfld.long 0x1DC 16. "VOUT1_D0_PULLUDENABLE,- ENABLE" "VOUT1_D0_PULLUDENABLE_0,VOUT1_D0_PULLUDENABLE_1" newline bitfld.long 0x1DC 8. "VOUT1_D0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D0_MODESELECT_0,VOUT1_D0_MODESELECT_1" newline bitfld.long 0x1DC 4.--7. "VOUT1_D0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1DC 0.--3. "VOUT1_D0_MUXMODE,- VOUT1_D0" "VOUT1_D0_MUXMODE_0,?,VOUT1_D0_MUXMODE_2,VOUT1_D0_MUXMODE_3,VOUT1_D0_MUXMODE_4,?,?,?,VOUT1_D0_MUXMODE_8,?,?,?,?,?,VOUT1_D0_MUXMODE_14,VOUT1_D0_MUXMODE_15" line.long 0x1E0 "CTRL_CORE_PAD_VOUT1_D1," rbitfld.long 0x1E0 25. "VOUT1_D1_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D1_WAKEUPEVENT_0,VOUT1_D1_WAKEUPEVENT_1" newline bitfld.long 0x1E0 24. "VOUT1_D1_WAKEUPENABLE,- DISABLE" "VOUT1_D1_WAKEUPENABLE_0,VOUT1_D1_WAKEUPENABLE_1" newline bitfld.long 0x1E0 19. "VOUT1_D1_SLEWCONTROL,- FAST_SLEW" "VOUT1_D1_SLEWCONTROL_0,VOUT1_D1_SLEWCONTROL_1" newline bitfld.long 0x1E0 18. "VOUT1_D1_INPUTENABLE,- DISABLE" "VOUT1_D1_INPUTENABLE_0,VOUT1_D1_INPUTENABLE_1" newline bitfld.long 0x1E0 17. "VOUT1_D1_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D1_PULLTYPESELECT_0,VOUT1_D1_PULLTYPESELECT_1" newline bitfld.long 0x1E0 16. "VOUT1_D1_PULLUDENABLE,- ENABLE" "VOUT1_D1_PULLUDENABLE_0,VOUT1_D1_PULLUDENABLE_1" newline bitfld.long 0x1E0 8. "VOUT1_D1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D1_MODESELECT_0,VOUT1_D1_MODESELECT_1" newline bitfld.long 0x1E0 4.--7. "VOUT1_D1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E0 0.--3. "VOUT1_D1_MUXMODE,- VOUT1_D1" "VOUT1_D1_MUXMODE_0,?,VOUT1_D1_MUXMODE_2,VOUT1_D1_MUXMODE_3,VOUT1_D1_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D1_MUXMODE_14,VOUT1_D1_MUXMODE_15" line.long 0x1E4 "CTRL_CORE_PAD_VOUT1_D2," rbitfld.long 0x1E4 25. "VOUT1_D2_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D2_WAKEUPEVENT_0,VOUT1_D2_WAKEUPEVENT_1" newline bitfld.long 0x1E4 24. "VOUT1_D2_WAKEUPENABLE,- DISABLE" "VOUT1_D2_WAKEUPENABLE_0,VOUT1_D2_WAKEUPENABLE_1" newline bitfld.long 0x1E4 19. "VOUT1_D2_SLEWCONTROL,- FAST_SLEW" "VOUT1_D2_SLEWCONTROL_0,VOUT1_D2_SLEWCONTROL_1" newline bitfld.long 0x1E4 18. "VOUT1_D2_INPUTENABLE,- DISABLE" "VOUT1_D2_INPUTENABLE_0,VOUT1_D2_INPUTENABLE_1" newline bitfld.long 0x1E4 17. "VOUT1_D2_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D2_PULLTYPESELECT_0,VOUT1_D2_PULLTYPESELECT_1" newline bitfld.long 0x1E4 16. "VOUT1_D2_PULLUDENABLE,- ENABLE" "VOUT1_D2_PULLUDENABLE_0,VOUT1_D2_PULLUDENABLE_1" newline bitfld.long 0x1E4 8. "VOUT1_D2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D2_MODESELECT_0,VOUT1_D2_MODESELECT_1" newline bitfld.long 0x1E4 4.--7. "VOUT1_D2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E4 0.--3. "VOUT1_D2_MUXMODE,- VOUT1_D2" "VOUT1_D2_MUXMODE_0,?,VOUT1_D2_MUXMODE_2,VOUT1_D2_MUXMODE_3,VOUT1_D2_MUXMODE_4,VOUT1_D2_MUXMODE_5,VOUT1_D2_MUXMODE_6,VOUT1_D2_MUXMODE_7,?,?,?,?,?,?,VOUT1_D2_MUXMODE_14,VOUT1_D2_MUXMODE_15" line.long 0x1E8 "CTRL_CORE_PAD_VOUT1_D3," rbitfld.long 0x1E8 25. "VOUT1_D3_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D3_WAKEUPEVENT_0,VOUT1_D3_WAKEUPEVENT_1" newline bitfld.long 0x1E8 24. "VOUT1_D3_WAKEUPENABLE,- DISABLE" "VOUT1_D3_WAKEUPENABLE_0,VOUT1_D3_WAKEUPENABLE_1" newline bitfld.long 0x1E8 19. "VOUT1_D3_SLEWCONTROL,- FAST_SLEW" "VOUT1_D3_SLEWCONTROL_0,VOUT1_D3_SLEWCONTROL_1" newline bitfld.long 0x1E8 18. "VOUT1_D3_INPUTENABLE,- DISABLE" "VOUT1_D3_INPUTENABLE_0,VOUT1_D3_INPUTENABLE_1" newline bitfld.long 0x1E8 17. "VOUT1_D3_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D3_PULLTYPESELECT_0,VOUT1_D3_PULLTYPESELECT_1" newline bitfld.long 0x1E8 16. "VOUT1_D3_PULLUDENABLE,- ENABLE" "VOUT1_D3_PULLUDENABLE_0,VOUT1_D3_PULLUDENABLE_1" newline bitfld.long 0x1E8 8. "VOUT1_D3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D3_MODESELECT_0,VOUT1_D3_MODESELECT_1" newline bitfld.long 0x1E8 4.--7. "VOUT1_D3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E8 0.--3. "VOUT1_D3_MUXMODE,- VOUT1_D3" "VOUT1_D3_MUXMODE_0,?,VOUT1_D3_MUXMODE_2,VOUT1_D3_MUXMODE_3,VOUT1_D3_MUXMODE_4,VOUT1_D3_MUXMODE_5,VOUT1_D3_MUXMODE_6,VOUT1_D3_MUXMODE_7,?,?,?,?,?,?,VOUT1_D3_MUXMODE_14,VOUT1_D3_MUXMODE_15" line.long 0x1EC "CTRL_CORE_PAD_VOUT1_D4," rbitfld.long 0x1EC 25. "VOUT1_D4_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D4_WAKEUPEVENT_0,VOUT1_D4_WAKEUPEVENT_1" newline bitfld.long 0x1EC 24. "VOUT1_D4_WAKEUPENABLE,- DISABLE" "VOUT1_D4_WAKEUPENABLE_0,VOUT1_D4_WAKEUPENABLE_1" newline bitfld.long 0x1EC 19. "VOUT1_D4_SLEWCONTROL,- FAST_SLEW" "VOUT1_D4_SLEWCONTROL_0,VOUT1_D4_SLEWCONTROL_1" newline bitfld.long 0x1EC 18. "VOUT1_D4_INPUTENABLE,- DISABLE" "VOUT1_D4_INPUTENABLE_0,VOUT1_D4_INPUTENABLE_1" newline bitfld.long 0x1EC 17. "VOUT1_D4_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D4_PULLTYPESELECT_0,VOUT1_D4_PULLTYPESELECT_1" newline bitfld.long 0x1EC 16. "VOUT1_D4_PULLUDENABLE,- ENABLE" "VOUT1_D4_PULLUDENABLE_0,VOUT1_D4_PULLUDENABLE_1" newline bitfld.long 0x1EC 8. "VOUT1_D4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D4_MODESELECT_0,VOUT1_D4_MODESELECT_1" newline bitfld.long 0x1EC 4.--7. "VOUT1_D4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1EC 0.--3. "VOUT1_D4_MUXMODE,- VOUT1_D4" "VOUT1_D4_MUXMODE_0,?,VOUT1_D4_MUXMODE_2,VOUT1_D4_MUXMODE_3,VOUT1_D4_MUXMODE_4,VOUT1_D4_MUXMODE_5,VOUT1_D4_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D4_MUXMODE_14,VOUT1_D4_MUXMODE_15" line.long 0x1F0 "CTRL_CORE_PAD_VOUT1_D5," rbitfld.long 0x1F0 25. "VOUT1_D5_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D5_WAKEUPEVENT_0,VOUT1_D5_WAKEUPEVENT_1" newline bitfld.long 0x1F0 24. "VOUT1_D5_WAKEUPENABLE,- DISABLE" "VOUT1_D5_WAKEUPENABLE_0,VOUT1_D5_WAKEUPENABLE_1" newline bitfld.long 0x1F0 19. "VOUT1_D5_SLEWCONTROL,- FAST_SLEW" "VOUT1_D5_SLEWCONTROL_0,VOUT1_D5_SLEWCONTROL_1" newline bitfld.long 0x1F0 18. "VOUT1_D5_INPUTENABLE,- DISABLE" "VOUT1_D5_INPUTENABLE_0,VOUT1_D5_INPUTENABLE_1" newline bitfld.long 0x1F0 17. "VOUT1_D5_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D5_PULLTYPESELECT_0,VOUT1_D5_PULLTYPESELECT_1" newline bitfld.long 0x1F0 16. "VOUT1_D5_PULLUDENABLE,- ENABLE" "VOUT1_D5_PULLUDENABLE_0,VOUT1_D5_PULLUDENABLE_1" newline bitfld.long 0x1F0 8. "VOUT1_D5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D5_MODESELECT_0,VOUT1_D5_MODESELECT_1" newline bitfld.long 0x1F0 4.--7. "VOUT1_D5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F0 0.--3. "VOUT1_D5_MUXMODE,- VOUT1_D5" "VOUT1_D5_MUXMODE_0,?,VOUT1_D5_MUXMODE_2,VOUT1_D5_MUXMODE_3,VOUT1_D5_MUXMODE_4,VOUT1_D5_MUXMODE_5,VOUT1_D5_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D5_MUXMODE_14,VOUT1_D5_MUXMODE_15" line.long 0x1F4 "CTRL_CORE_PAD_VOUT1_D6," rbitfld.long 0x1F4 25. "VOUT1_D6_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D6_WAKEUPEVENT_0,VOUT1_D6_WAKEUPEVENT_1" newline bitfld.long 0x1F4 24. "VOUT1_D6_WAKEUPENABLE,- DISABLE" "VOUT1_D6_WAKEUPENABLE_0,VOUT1_D6_WAKEUPENABLE_1" newline bitfld.long 0x1F4 19. "VOUT1_D6_SLEWCONTROL,- FAST_SLEW" "VOUT1_D6_SLEWCONTROL_0,VOUT1_D6_SLEWCONTROL_1" newline bitfld.long 0x1F4 18. "VOUT1_D6_INPUTENABLE,- DISABLE" "VOUT1_D6_INPUTENABLE_0,VOUT1_D6_INPUTENABLE_1" newline bitfld.long 0x1F4 17. "VOUT1_D6_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D6_PULLTYPESELECT_0,VOUT1_D6_PULLTYPESELECT_1" newline bitfld.long 0x1F4 16. "VOUT1_D6_PULLUDENABLE,- ENABLE" "VOUT1_D6_PULLUDENABLE_0,VOUT1_D6_PULLUDENABLE_1" newline bitfld.long 0x1F4 8. "VOUT1_D6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D6_MODESELECT_0,VOUT1_D6_MODESELECT_1" newline bitfld.long 0x1F4 4.--7. "VOUT1_D6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F4 0.--3. "VOUT1_D6_MUXMODE,- VOUT1_D6" "VOUT1_D6_MUXMODE_0,?,VOUT1_D6_MUXMODE_2,VOUT1_D6_MUXMODE_3,VOUT1_D6_MUXMODE_4,VOUT1_D6_MUXMODE_5,VOUT1_D6_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D6_MUXMODE_14,VOUT1_D6_MUXMODE_15" line.long 0x1F8 "CTRL_CORE_PAD_VOUT1_D7," rbitfld.long 0x1F8 25. "VOUT1_D7_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D7_WAKEUPEVENT_0,VOUT1_D7_WAKEUPEVENT_1" newline bitfld.long 0x1F8 24. "VOUT1_D7_WAKEUPENABLE,- DISABLE" "VOUT1_D7_WAKEUPENABLE_0,VOUT1_D7_WAKEUPENABLE_1" newline bitfld.long 0x1F8 19. "VOUT1_D7_SLEWCONTROL,- FAST_SLEW" "VOUT1_D7_SLEWCONTROL_0,VOUT1_D7_SLEWCONTROL_1" newline bitfld.long 0x1F8 18. "VOUT1_D7_INPUTENABLE,- DISABLE" "VOUT1_D7_INPUTENABLE_0,VOUT1_D7_INPUTENABLE_1" newline bitfld.long 0x1F8 17. "VOUT1_D7_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D7_PULLTYPESELECT_0,VOUT1_D7_PULLTYPESELECT_1" newline bitfld.long 0x1F8 16. "VOUT1_D7_PULLUDENABLE,- ENABLE" "VOUT1_D7_PULLUDENABLE_0,VOUT1_D7_PULLUDENABLE_1" newline bitfld.long 0x1F8 8. "VOUT1_D7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D7_MODESELECT_0,VOUT1_D7_MODESELECT_1" newline bitfld.long 0x1F8 4.--7. "VOUT1_D7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F8 0.--3. "VOUT1_D7_MUXMODE,- VOUT1_D7" "VOUT1_D7_MUXMODE_0,?,VOUT1_D7_MUXMODE_2,VOUT1_D7_MUXMODE_3,VOUT1_D7_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D7_MUXMODE_14,VOUT1_D7_MUXMODE_15" line.long 0x1FC "CTRL_CORE_PAD_VOUT1_D8," rbitfld.long 0x1FC 25. "VOUT1_D8_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D8_WAKEUPEVENT_0,VOUT1_D8_WAKEUPEVENT_1" newline bitfld.long 0x1FC 24. "VOUT1_D8_WAKEUPENABLE,- DISABLE" "VOUT1_D8_WAKEUPENABLE_0,VOUT1_D8_WAKEUPENABLE_1" newline bitfld.long 0x1FC 19. "VOUT1_D8_SLEWCONTROL,- FAST_SLEW" "VOUT1_D8_SLEWCONTROL_0,VOUT1_D8_SLEWCONTROL_1" newline bitfld.long 0x1FC 18. "VOUT1_D8_INPUTENABLE,- DISABLE" "VOUT1_D8_INPUTENABLE_0,VOUT1_D8_INPUTENABLE_1" newline bitfld.long 0x1FC 17. "VOUT1_D8_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D8_PULLTYPESELECT_0,VOUT1_D8_PULLTYPESELECT_1" newline bitfld.long 0x1FC 16. "VOUT1_D8_PULLUDENABLE,- ENABLE" "VOUT1_D8_PULLUDENABLE_0,VOUT1_D8_PULLUDENABLE_1" newline bitfld.long 0x1FC 8. "VOUT1_D8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D8_MODESELECT_0,VOUT1_D8_MODESELECT_1" newline bitfld.long 0x1FC 4.--7. "VOUT1_D8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1FC 0.--3. "VOUT1_D8_MUXMODE,- VOUT1_D8" "VOUT1_D8_MUXMODE_0,?,VOUT1_D8_MUXMODE_2,VOUT1_D8_MUXMODE_3,VOUT1_D8_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D8_MUXMODE_14,VOUT1_D8_MUXMODE_15" line.long 0x200 "CTRL_CORE_PAD_VOUT1_D9," rbitfld.long 0x200 25. "VOUT1_D9_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D9_WAKEUPEVENT_0,VOUT1_D9_WAKEUPEVENT_1" newline bitfld.long 0x200 24. "VOUT1_D9_WAKEUPENABLE,- DISABLE" "VOUT1_D9_WAKEUPENABLE_0,VOUT1_D9_WAKEUPENABLE_1" newline bitfld.long 0x200 19. "VOUT1_D9_SLEWCONTROL,- FAST_SLEW" "VOUT1_D9_SLEWCONTROL_0,VOUT1_D9_SLEWCONTROL_1" newline bitfld.long 0x200 18. "VOUT1_D9_INPUTENABLE,- DISABLE" "VOUT1_D9_INPUTENABLE_0,VOUT1_D9_INPUTENABLE_1" newline bitfld.long 0x200 17. "VOUT1_D9_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D9_PULLTYPESELECT_0,VOUT1_D9_PULLTYPESELECT_1" newline bitfld.long 0x200 16. "VOUT1_D9_PULLUDENABLE,- ENABLE" "VOUT1_D9_PULLUDENABLE_0,VOUT1_D9_PULLUDENABLE_1" newline bitfld.long 0x200 8. "VOUT1_D9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D9_MODESELECT_0,VOUT1_D9_MODESELECT_1" newline bitfld.long 0x200 4.--7. "VOUT1_D9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x200 0.--3. "VOUT1_D9_MUXMODE,- VOUT1_D9" "VOUT1_D9_MUXMODE_0,?,VOUT1_D9_MUXMODE_2,VOUT1_D9_MUXMODE_3,VOUT1_D9_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D9_MUXMODE_14,VOUT1_D9_MUXMODE_15" line.long 0x204 "CTRL_CORE_PAD_VOUT1_D10," rbitfld.long 0x204 25. "VOUT1_D10_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D10_WAKEUPEVENT_0,VOUT1_D10_WAKEUPEVENT_1" newline bitfld.long 0x204 24. "VOUT1_D10_WAKEUPENABLE,- DISABLE" "VOUT1_D10_WAKEUPENABLE_0,VOUT1_D10_WAKEUPENABLE_1" newline bitfld.long 0x204 19. "VOUT1_D10_SLEWCONTROL,- FAST_SLEW" "VOUT1_D10_SLEWCONTROL_0,VOUT1_D10_SLEWCONTROL_1" newline bitfld.long 0x204 18. "VOUT1_D10_INPUTENABLE,- DISABLE" "VOUT1_D10_INPUTENABLE_0,VOUT1_D10_INPUTENABLE_1" newline bitfld.long 0x204 17. "VOUT1_D10_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D10_PULLTYPESELECT_0,VOUT1_D10_PULLTYPESELECT_1" newline bitfld.long 0x204 16. "VOUT1_D10_PULLUDENABLE,- ENABLE" "VOUT1_D10_PULLUDENABLE_0,VOUT1_D10_PULLUDENABLE_1" newline bitfld.long 0x204 8. "VOUT1_D10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D10_MODESELECT_0,VOUT1_D10_MODESELECT_1" newline bitfld.long 0x204 4.--7. "VOUT1_D10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x204 0.--3. "VOUT1_D10_MUXMODE,- VOUT1_D10" "VOUT1_D10_MUXMODE_0,?,VOUT1_D10_MUXMODE_2,VOUT1_D10_MUXMODE_3,VOUT1_D10_MUXMODE_4,VOUT1_D10_MUXMODE_5,VOUT1_D10_MUXMODE_6,VOUT1_D10_MUXMODE_7,?,?,?,?,?,?,VOUT1_D10_MUXMODE_14,VOUT1_D10_MUXMODE_15" line.long 0x208 "CTRL_CORE_PAD_VOUT1_D11," rbitfld.long 0x208 25. "VOUT1_D11_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D11_WAKEUPEVENT_0,VOUT1_D11_WAKEUPEVENT_1" newline bitfld.long 0x208 24. "VOUT1_D11_WAKEUPENABLE,- DISABLE" "VOUT1_D11_WAKEUPENABLE_0,VOUT1_D11_WAKEUPENABLE_1" newline bitfld.long 0x208 19. "VOUT1_D11_SLEWCONTROL,- FAST_SLEW" "VOUT1_D11_SLEWCONTROL_0,VOUT1_D11_SLEWCONTROL_1" newline bitfld.long 0x208 18. "VOUT1_D11_INPUTENABLE,- DISABLE" "VOUT1_D11_INPUTENABLE_0,VOUT1_D11_INPUTENABLE_1" newline bitfld.long 0x208 17. "VOUT1_D11_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D11_PULLTYPESELECT_0,VOUT1_D11_PULLTYPESELECT_1" newline bitfld.long 0x208 16. "VOUT1_D11_PULLUDENABLE,- ENABLE" "VOUT1_D11_PULLUDENABLE_0,VOUT1_D11_PULLUDENABLE_1" newline bitfld.long 0x208 8. "VOUT1_D11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D11_MODESELECT_0,VOUT1_D11_MODESELECT_1" newline bitfld.long 0x208 4.--7. "VOUT1_D11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x208 0.--3. "VOUT1_D11_MUXMODE,- VOUT1_D11" "VOUT1_D11_MUXMODE_0,?,VOUT1_D11_MUXMODE_2,VOUT1_D11_MUXMODE_3,VOUT1_D11_MUXMODE_4,VOUT1_D11_MUXMODE_5,VOUT1_D11_MUXMODE_6,VOUT1_D11_MUXMODE_7,?,?,?,?,?,?,VOUT1_D11_MUXMODE_14,VOUT1_D11_MUXMODE_15" line.long 0x20C "CTRL_CORE_PAD_VOUT1_D12," rbitfld.long 0x20C 25. "VOUT1_D12_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D12_WAKEUPEVENT_0,VOUT1_D12_WAKEUPEVENT_1" newline bitfld.long 0x20C 24. "VOUT1_D12_WAKEUPENABLE,- DISABLE" "VOUT1_D12_WAKEUPENABLE_0,VOUT1_D12_WAKEUPENABLE_1" newline bitfld.long 0x20C 19. "VOUT1_D12_SLEWCONTROL,- FAST_SLEW" "VOUT1_D12_SLEWCONTROL_0,VOUT1_D12_SLEWCONTROL_1" newline bitfld.long 0x20C 18. "VOUT1_D12_INPUTENABLE,- DISABLE" "VOUT1_D12_INPUTENABLE_0,VOUT1_D12_INPUTENABLE_1" newline bitfld.long 0x20C 17. "VOUT1_D12_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D12_PULLTYPESELECT_0,VOUT1_D12_PULLTYPESELECT_1" newline bitfld.long 0x20C 16. "VOUT1_D12_PULLUDENABLE,- ENABLE" "VOUT1_D12_PULLUDENABLE_0,VOUT1_D12_PULLUDENABLE_1" newline bitfld.long 0x20C 8. "VOUT1_D12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D12_MODESELECT_0,VOUT1_D12_MODESELECT_1" newline bitfld.long 0x20C 4.--7. "VOUT1_D12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20C 0.--3. "VOUT1_D12_MUXMODE,- VOUT1_D12" "VOUT1_D12_MUXMODE_0,?,VOUT1_D12_MUXMODE_2,VOUT1_D12_MUXMODE_3,VOUT1_D12_MUXMODE_4,VOUT1_D12_MUXMODE_5,VOUT1_D12_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D12_MUXMODE_14,VOUT1_D12_MUXMODE_15" line.long 0x210 "CTRL_CORE_PAD_VOUT1_D13," rbitfld.long 0x210 25. "VOUT1_D13_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D13_WAKEUPEVENT_0,VOUT1_D13_WAKEUPEVENT_1" newline bitfld.long 0x210 24. "VOUT1_D13_WAKEUPENABLE,- DISABLE" "VOUT1_D13_WAKEUPENABLE_0,VOUT1_D13_WAKEUPENABLE_1" newline bitfld.long 0x210 19. "VOUT1_D13_SLEWCONTROL,- FAST_SLEW" "VOUT1_D13_SLEWCONTROL_0,VOUT1_D13_SLEWCONTROL_1" newline bitfld.long 0x210 18. "VOUT1_D13_INPUTENABLE,- DISABLE" "VOUT1_D13_INPUTENABLE_0,VOUT1_D13_INPUTENABLE_1" newline bitfld.long 0x210 17. "VOUT1_D13_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D13_PULLTYPESELECT_0,VOUT1_D13_PULLTYPESELECT_1" newline bitfld.long 0x210 16. "VOUT1_D13_PULLUDENABLE,- ENABLE" "VOUT1_D13_PULLUDENABLE_0,VOUT1_D13_PULLUDENABLE_1" newline bitfld.long 0x210 8. "VOUT1_D13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D13_MODESELECT_0,VOUT1_D13_MODESELECT_1" newline bitfld.long 0x210 4.--7. "VOUT1_D13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x210 0.--3. "VOUT1_D13_MUXMODE,- VOUT1_D13" "VOUT1_D13_MUXMODE_0,?,VOUT1_D13_MUXMODE_2,VOUT1_D13_MUXMODE_3,VOUT1_D13_MUXMODE_4,VOUT1_D13_MUXMODE_5,VOUT1_D13_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D13_MUXMODE_14,VOUT1_D13_MUXMODE_15" line.long 0x214 "CTRL_CORE_PAD_VOUT1_D14," rbitfld.long 0x214 25. "VOUT1_D14_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D14_WAKEUPEVENT_0,VOUT1_D14_WAKEUPEVENT_1" newline bitfld.long 0x214 24. "VOUT1_D14_WAKEUPENABLE,- DISABLE" "VOUT1_D14_WAKEUPENABLE_0,VOUT1_D14_WAKEUPENABLE_1" newline bitfld.long 0x214 19. "VOUT1_D14_SLEWCONTROL,- FAST_SLEW" "VOUT1_D14_SLEWCONTROL_0,VOUT1_D14_SLEWCONTROL_1" newline bitfld.long 0x214 18. "VOUT1_D14_INPUTENABLE,- DISABLE" "VOUT1_D14_INPUTENABLE_0,VOUT1_D14_INPUTENABLE_1" newline bitfld.long 0x214 17. "VOUT1_D14_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D14_PULLTYPESELECT_0,VOUT1_D14_PULLTYPESELECT_1" newline bitfld.long 0x214 16. "VOUT1_D14_PULLUDENABLE,- ENABLE" "VOUT1_D14_PULLUDENABLE_0,VOUT1_D14_PULLUDENABLE_1" newline bitfld.long 0x214 8. "VOUT1_D14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D14_MODESELECT_0,VOUT1_D14_MODESELECT_1" newline bitfld.long 0x214 4.--7. "VOUT1_D14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x214 0.--3. "VOUT1_D14_MUXMODE,- VOUT1_D14" "VOUT1_D14_MUXMODE_0,?,VOUT1_D14_MUXMODE_2,VOUT1_D14_MUXMODE_3,VOUT1_D14_MUXMODE_4,VOUT1_D14_MUXMODE_5,VOUT1_D14_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D14_MUXMODE_14,VOUT1_D14_MUXMODE_15" line.long 0x218 "CTRL_CORE_PAD_VOUT1_D15," rbitfld.long 0x218 25. "VOUT1_D15_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D15_WAKEUPEVENT_0,VOUT1_D15_WAKEUPEVENT_1" newline bitfld.long 0x218 24. "VOUT1_D15_WAKEUPENABLE,- DISABLE" "VOUT1_D15_WAKEUPENABLE_0,VOUT1_D15_WAKEUPENABLE_1" newline bitfld.long 0x218 19. "VOUT1_D15_SLEWCONTROL,- FAST_SLEW" "VOUT1_D15_SLEWCONTROL_0,VOUT1_D15_SLEWCONTROL_1" newline bitfld.long 0x218 18. "VOUT1_D15_INPUTENABLE,- DISABLE" "VOUT1_D15_INPUTENABLE_0,VOUT1_D15_INPUTENABLE_1" newline bitfld.long 0x218 17. "VOUT1_D15_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D15_PULLTYPESELECT_0,VOUT1_D15_PULLTYPESELECT_1" newline bitfld.long 0x218 16. "VOUT1_D15_PULLUDENABLE,- ENABLE" "VOUT1_D15_PULLUDENABLE_0,VOUT1_D15_PULLUDENABLE_1" newline bitfld.long 0x218 8. "VOUT1_D15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D15_MODESELECT_0,VOUT1_D15_MODESELECT_1" newline bitfld.long 0x218 4.--7. "VOUT1_D15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x218 0.--3. "VOUT1_D15_MUXMODE,- VOUT1_D15" "VOUT1_D15_MUXMODE_0,?,VOUT1_D15_MUXMODE_2,VOUT1_D15_MUXMODE_3,VOUT1_D15_MUXMODE_4,VOUT1_D15_MUXMODE_5,VOUT1_D15_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D15_MUXMODE_14,VOUT1_D15_MUXMODE_15" line.long 0x21C "CTRL_CORE_PAD_VOUT1_D16," rbitfld.long 0x21C 25. "VOUT1_D16_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D16_WAKEUPEVENT_0,VOUT1_D16_WAKEUPEVENT_1" newline bitfld.long 0x21C 24. "VOUT1_D16_WAKEUPENABLE,- DISABLE" "VOUT1_D16_WAKEUPENABLE_0,VOUT1_D16_WAKEUPENABLE_1" newline bitfld.long 0x21C 19. "VOUT1_D16_SLEWCONTROL,- FAST_SLEW" "VOUT1_D16_SLEWCONTROL_0,VOUT1_D16_SLEWCONTROL_1" newline bitfld.long 0x21C 18. "VOUT1_D16_INPUTENABLE,- DISABLE" "VOUT1_D16_INPUTENABLE_0,VOUT1_D16_INPUTENABLE_1" newline bitfld.long 0x21C 17. "VOUT1_D16_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D16_PULLTYPESELECT_0,VOUT1_D16_PULLTYPESELECT_1" newline bitfld.long 0x21C 16. "VOUT1_D16_PULLUDENABLE,- ENABLE" "VOUT1_D16_PULLUDENABLE_0,VOUT1_D16_PULLUDENABLE_1" newline bitfld.long 0x21C 8. "VOUT1_D16_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D16_MODESELECT_0,VOUT1_D16_MODESELECT_1" newline bitfld.long 0x21C 4.--7. "VOUT1_D16_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x21C 0.--3. "VOUT1_D16_MUXMODE,- VOUT1_D16" "VOUT1_D16_MUXMODE_0,?,VOUT1_D16_MUXMODE_2,VOUT1_D16_MUXMODE_3,VOUT1_D16_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D16_MUXMODE_14,VOUT1_D16_MUXMODE_15" line.long 0x220 "CTRL_CORE_PAD_VOUT1_D17," rbitfld.long 0x220 25. "VOUT1_D17_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D17_WAKEUPEVENT_0,VOUT1_D17_WAKEUPEVENT_1" newline bitfld.long 0x220 24. "VOUT1_D17_WAKEUPENABLE,- DISABLE" "VOUT1_D17_WAKEUPENABLE_0,VOUT1_D17_WAKEUPENABLE_1" newline bitfld.long 0x220 19. "VOUT1_D17_SLEWCONTROL,- FAST_SLEW" "VOUT1_D17_SLEWCONTROL_0,VOUT1_D17_SLEWCONTROL_1" newline bitfld.long 0x220 18. "VOUT1_D17_INPUTENABLE,- DISABLE" "VOUT1_D17_INPUTENABLE_0,VOUT1_D17_INPUTENABLE_1" newline bitfld.long 0x220 17. "VOUT1_D17_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D17_PULLTYPESELECT_0,VOUT1_D17_PULLTYPESELECT_1" newline bitfld.long 0x220 16. "VOUT1_D17_PULLUDENABLE,- ENABLE" "VOUT1_D17_PULLUDENABLE_0,VOUT1_D17_PULLUDENABLE_1" newline bitfld.long 0x220 8. "VOUT1_D17_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D17_MODESELECT_0,VOUT1_D17_MODESELECT_1" newline bitfld.long 0x220 4.--7. "VOUT1_D17_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x220 0.--3. "VOUT1_D17_MUXMODE,- VOUT1_D17" "VOUT1_D17_MUXMODE_0,?,VOUT1_D17_MUXMODE_2,VOUT1_D17_MUXMODE_3,VOUT1_D17_MUXMODE_4,?,?,?,?,?,?,?,?,?,VOUT1_D17_MUXMODE_14,VOUT1_D17_MUXMODE_15" line.long 0x224 "CTRL_CORE_PAD_VOUT1_D18," rbitfld.long 0x224 25. "VOUT1_D18_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D18_WAKEUPEVENT_0,VOUT1_D18_WAKEUPEVENT_1" newline bitfld.long 0x224 24. "VOUT1_D18_WAKEUPENABLE,- DISABLE" "VOUT1_D18_WAKEUPENABLE_0,VOUT1_D18_WAKEUPENABLE_1" newline bitfld.long 0x224 19. "VOUT1_D18_SLEWCONTROL,- FAST_SLEW" "VOUT1_D18_SLEWCONTROL_0,VOUT1_D18_SLEWCONTROL_1" newline bitfld.long 0x224 18. "VOUT1_D18_INPUTENABLE,- DISABLE" "VOUT1_D18_INPUTENABLE_0,VOUT1_D18_INPUTENABLE_1" newline bitfld.long 0x224 17. "VOUT1_D18_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D18_PULLTYPESELECT_0,VOUT1_D18_PULLTYPESELECT_1" newline bitfld.long 0x224 16. "VOUT1_D18_PULLUDENABLE,- ENABLE" "VOUT1_D18_PULLUDENABLE_0,VOUT1_D18_PULLUDENABLE_1" newline bitfld.long 0x224 8. "VOUT1_D18_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D18_MODESELECT_0,VOUT1_D18_MODESELECT_1" newline bitfld.long 0x224 4.--7. "VOUT1_D18_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x224 0.--3. "VOUT1_D18_MUXMODE,- VOUT1_D18" "VOUT1_D18_MUXMODE_0,?,VOUT1_D18_MUXMODE_2,VOUT1_D18_MUXMODE_3,VOUT1_D18_MUXMODE_4,VOUT1_D18_MUXMODE_5,VOUT1_D18_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D18_MUXMODE_14,VOUT1_D18_MUXMODE_15" line.long 0x228 "CTRL_CORE_PAD_VOUT1_D19," rbitfld.long 0x228 25. "VOUT1_D19_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D19_WAKEUPEVENT_0,VOUT1_D19_WAKEUPEVENT_1" newline bitfld.long 0x228 24. "VOUT1_D19_WAKEUPENABLE,- DISABLE" "VOUT1_D19_WAKEUPENABLE_0,VOUT1_D19_WAKEUPENABLE_1" newline bitfld.long 0x228 19. "VOUT1_D19_SLEWCONTROL,- FAST_SLEW" "VOUT1_D19_SLEWCONTROL_0,VOUT1_D19_SLEWCONTROL_1" newline bitfld.long 0x228 18. "VOUT1_D19_INPUTENABLE,- DISABLE" "VOUT1_D19_INPUTENABLE_0,VOUT1_D19_INPUTENABLE_1" newline bitfld.long 0x228 17. "VOUT1_D19_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D19_PULLTYPESELECT_0,VOUT1_D19_PULLTYPESELECT_1" newline bitfld.long 0x228 16. "VOUT1_D19_PULLUDENABLE,- ENABLE" "VOUT1_D19_PULLUDENABLE_0,VOUT1_D19_PULLUDENABLE_1" newline bitfld.long 0x228 8. "VOUT1_D19_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D19_MODESELECT_0,VOUT1_D19_MODESELECT_1" newline bitfld.long 0x228 4.--7. "VOUT1_D19_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x228 0.--3. "VOUT1_D19_MUXMODE,- VOUT1_D19" "VOUT1_D19_MUXMODE_0,?,VOUT1_D19_MUXMODE_2,VOUT1_D19_MUXMODE_3,VOUT1_D19_MUXMODE_4,VOUT1_D19_MUXMODE_5,VOUT1_D19_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D19_MUXMODE_14,VOUT1_D19_MUXMODE_15" line.long 0x22C "CTRL_CORE_PAD_VOUT1_D20," rbitfld.long 0x22C 25. "VOUT1_D20_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D20_WAKEUPEVENT_0,VOUT1_D20_WAKEUPEVENT_1" newline bitfld.long 0x22C 24. "VOUT1_D20_WAKEUPENABLE,- DISABLE" "VOUT1_D20_WAKEUPENABLE_0,VOUT1_D20_WAKEUPENABLE_1" newline bitfld.long 0x22C 19. "VOUT1_D20_SLEWCONTROL,- FAST_SLEW" "VOUT1_D20_SLEWCONTROL_0,VOUT1_D20_SLEWCONTROL_1" newline bitfld.long 0x22C 18. "VOUT1_D20_INPUTENABLE,- DISABLE" "VOUT1_D20_INPUTENABLE_0,VOUT1_D20_INPUTENABLE_1" newline bitfld.long 0x22C 17. "VOUT1_D20_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D20_PULLTYPESELECT_0,VOUT1_D20_PULLTYPESELECT_1" newline bitfld.long 0x22C 16. "VOUT1_D20_PULLUDENABLE,- ENABLE" "VOUT1_D20_PULLUDENABLE_0,VOUT1_D20_PULLUDENABLE_1" newline bitfld.long 0x22C 8. "VOUT1_D20_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D20_MODESELECT_0,VOUT1_D20_MODESELECT_1" newline bitfld.long 0x22C 4.--7. "VOUT1_D20_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x22C 0.--3. "VOUT1_D20_MUXMODE,- VOUT1_D20" "VOUT1_D20_MUXMODE_0,?,VOUT1_D20_MUXMODE_2,VOUT1_D20_MUXMODE_3,VOUT1_D20_MUXMODE_4,VOUT1_D20_MUXMODE_5,VOUT1_D20_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D20_MUXMODE_14,VOUT1_D20_MUXMODE_15" line.long 0x230 "CTRL_CORE_PAD_VOUT1_D21," rbitfld.long 0x230 25. "VOUT1_D21_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D21_WAKEUPEVENT_0,VOUT1_D21_WAKEUPEVENT_1" newline bitfld.long 0x230 24. "VOUT1_D21_WAKEUPENABLE,- DISABLE" "VOUT1_D21_WAKEUPENABLE_0,VOUT1_D21_WAKEUPENABLE_1" newline bitfld.long 0x230 19. "VOUT1_D21_SLEWCONTROL,- FAST_SLEW" "VOUT1_D21_SLEWCONTROL_0,VOUT1_D21_SLEWCONTROL_1" newline bitfld.long 0x230 18. "VOUT1_D21_INPUTENABLE,- DISABLE" "VOUT1_D21_INPUTENABLE_0,VOUT1_D21_INPUTENABLE_1" newline bitfld.long 0x230 17. "VOUT1_D21_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D21_PULLTYPESELECT_0,VOUT1_D21_PULLTYPESELECT_1" newline bitfld.long 0x230 16. "VOUT1_D21_PULLUDENABLE,- ENABLE" "VOUT1_D21_PULLUDENABLE_0,VOUT1_D21_PULLUDENABLE_1" newline bitfld.long 0x230 8. "VOUT1_D21_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D21_MODESELECT_0,VOUT1_D21_MODESELECT_1" newline bitfld.long 0x230 4.--7. "VOUT1_D21_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x230 0.--3. "VOUT1_D21_MUXMODE,- VOUT1_D21" "VOUT1_D21_MUXMODE_0,?,VOUT1_D21_MUXMODE_2,VOUT1_D21_MUXMODE_3,VOUT1_D21_MUXMODE_4,VOUT1_D21_MUXMODE_5,VOUT1_D21_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D21_MUXMODE_14,VOUT1_D21_MUXMODE_15" line.long 0x234 "CTRL_CORE_PAD_VOUT1_D22," rbitfld.long 0x234 25. "VOUT1_D22_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D22_WAKEUPEVENT_0,VOUT1_D22_WAKEUPEVENT_1" newline bitfld.long 0x234 24. "VOUT1_D22_WAKEUPENABLE,- DISABLE" "VOUT1_D22_WAKEUPENABLE_0,VOUT1_D22_WAKEUPENABLE_1" newline bitfld.long 0x234 19. "VOUT1_D22_SLEWCONTROL,- FAST_SLEW" "VOUT1_D22_SLEWCONTROL_0,VOUT1_D22_SLEWCONTROL_1" newline bitfld.long 0x234 18. "VOUT1_D22_INPUTENABLE,- DISABLE" "VOUT1_D22_INPUTENABLE_0,VOUT1_D22_INPUTENABLE_1" newline bitfld.long 0x234 17. "VOUT1_D22_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D22_PULLTYPESELECT_0,VOUT1_D22_PULLTYPESELECT_1" newline bitfld.long 0x234 16. "VOUT1_D22_PULLUDENABLE,- ENABLE" "VOUT1_D22_PULLUDENABLE_0,VOUT1_D22_PULLUDENABLE_1" newline bitfld.long 0x234 8. "VOUT1_D22_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D22_MODESELECT_0,VOUT1_D22_MODESELECT_1" newline bitfld.long 0x234 4.--7. "VOUT1_D22_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x234 0.--3. "VOUT1_D22_MUXMODE,- VOUT1_D22" "VOUT1_D22_MUXMODE_0,?,VOUT1_D22_MUXMODE_2,VOUT1_D22_MUXMODE_3,VOUT1_D22_MUXMODE_4,VOUT1_D22_MUXMODE_5,VOUT1_D22_MUXMODE_6,?,?,?,?,?,?,?,VOUT1_D22_MUXMODE_14,VOUT1_D22_MUXMODE_15" line.long 0x238 "CTRL_CORE_PAD_VOUT1_D23," rbitfld.long 0x238 25. "VOUT1_D23_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D23_WAKEUPEVENT_0,VOUT1_D23_WAKEUPEVENT_1" newline bitfld.long 0x238 24. "VOUT1_D23_WAKEUPENABLE,- DISABLE" "VOUT1_D23_WAKEUPENABLE_0,VOUT1_D23_WAKEUPENABLE_1" newline bitfld.long 0x238 19. "VOUT1_D23_SLEWCONTROL,- FAST_SLEW" "VOUT1_D23_SLEWCONTROL_0,VOUT1_D23_SLEWCONTROL_1" newline bitfld.long 0x238 18. "VOUT1_D23_INPUTENABLE,- DISABLE" "VOUT1_D23_INPUTENABLE_0,VOUT1_D23_INPUTENABLE_1" newline bitfld.long 0x238 17. "VOUT1_D23_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D23_PULLTYPESELECT_0,VOUT1_D23_PULLTYPESELECT_1" newline bitfld.long 0x238 16. "VOUT1_D23_PULLUDENABLE,- ENABLE" "VOUT1_D23_PULLUDENABLE_0,VOUT1_D23_PULLUDENABLE_1" newline bitfld.long 0x238 8. "VOUT1_D23_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "VOUT1_D23_MODESELECT_0,VOUT1_D23_MODESELECT_1" newline bitfld.long 0x238 4.--7. "VOUT1_D23_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x238 0.--3. "VOUT1_D23_MUXMODE,- VOUT1_D23" "VOUT1_D23_MUXMODE_0,?,VOUT1_D23_MUXMODE_2,VOUT1_D23_MUXMODE_3,VOUT1_D23_MUXMODE_4,?,?,?,VOUT1_D23_MUXMODE_8,?,?,?,?,?,VOUT1_D23_MUXMODE_14,VOUT1_D23_MUXMODE_15" line.long 0x23C "CTRL_CORE_PAD_MDIO_MCLK," rbitfld.long 0x23C 25. "MDIO_MCLK_WAKEUPEVENT,- NOWAKEUP" "MDIO_MCLK_WAKEUPEVENT_0,MDIO_MCLK_WAKEUPEVENT_1" newline bitfld.long 0x23C 24. "MDIO_MCLK_WAKEUPENABLE,- DISABLE" "MDIO_MCLK_WAKEUPENABLE_0,MDIO_MCLK_WAKEUPENABLE_1" newline bitfld.long 0x23C 19. "MDIO_MCLK_SLEWCONTROL,- FAST_SLEW" "MDIO_MCLK_SLEWCONTROL_0,MDIO_MCLK_SLEWCONTROL_1" newline bitfld.long 0x23C 18. "MDIO_MCLK_INPUTENABLE,- DISABLE" "MDIO_MCLK_INPUTENABLE_0,MDIO_MCLK_INPUTENABLE_1" newline bitfld.long 0x23C 17. "MDIO_MCLK_PULLTYPESELECT,- PULL_DOWN" "MDIO_MCLK_PULLTYPESELECT_0,MDIO_MCLK_PULLTYPESELECT_1" newline bitfld.long 0x23C 16. "MDIO_MCLK_PULLUDENABLE,- ENABLE" "MDIO_MCLK_PULLUDENABLE_0,MDIO_MCLK_PULLUDENABLE_1" newline bitfld.long 0x23C 8. "MDIO_MCLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MDIO_MCLK_MODESELECT_0,MDIO_MCLK_MODESELECT_1" newline bitfld.long 0x23C 4.--7. "MDIO_MCLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x23C 0.--3. "MDIO_MCLK_MUXMODE,- MDIO_MCLK" "MDIO_MCLK_MUXMODE_0,MDIO_MCLK_MUXMODE_1,?,MDIO_MCLK_MUXMODE_3,MDIO_MCLK_MUXMODE_4,MDIO_MCLK_MUXMODE_5,?,?,?,?,?,?,?,?,MDIO_MCLK_MUXMODE_14,MDIO_MCLK_MUXMODE_15" line.long 0x240 "CTRL_CORE_PAD_MDIO_D," rbitfld.long 0x240 25. "MDIO_D_WAKEUPEVENT,- NOWAKEUP" "MDIO_D_WAKEUPEVENT_0,MDIO_D_WAKEUPEVENT_1" newline bitfld.long 0x240 24. "MDIO_D_WAKEUPENABLE,- DISABLE" "MDIO_D_WAKEUPENABLE_0,MDIO_D_WAKEUPENABLE_1" newline bitfld.long 0x240 19. "MDIO_D_SLEWCONTROL,- FAST_SLEW" "MDIO_D_SLEWCONTROL_0,MDIO_D_SLEWCONTROL_1" newline bitfld.long 0x240 18. "MDIO_D_INPUTENABLE,- DISABLE" "MDIO_D_INPUTENABLE_0,MDIO_D_INPUTENABLE_1" newline bitfld.long 0x240 17. "MDIO_D_PULLTYPESELECT,- PULL_DOWN" "MDIO_D_PULLTYPESELECT_0,MDIO_D_PULLTYPESELECT_1" newline bitfld.long 0x240 16. "MDIO_D_PULLUDENABLE,- ENABLE" "MDIO_D_PULLUDENABLE_0,MDIO_D_PULLUDENABLE_1" newline bitfld.long 0x240 8. "MDIO_D_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MDIO_D_MODESELECT_0,MDIO_D_MODESELECT_1" newline bitfld.long 0x240 4.--7. "MDIO_D_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x240 0.--3. "MDIO_D_MUXMODE,- MDIO_D" "MDIO_D_MUXMODE_0,MDIO_D_MUXMODE_1,?,MDIO_D_MUXMODE_3,MDIO_D_MUXMODE_4,MDIO_D_MUXMODE_5,?,?,?,?,?,?,?,?,MDIO_D_MUXMODE_14,MDIO_D_MUXMODE_15" line.long 0x244 "CTRL_CORE_PAD_RMII_MHZ_50_CLK," rbitfld.long 0x244 25. "RMII_MHZ_50_CLK_WAKEUPEVENT,- NOWAKEUP" "RMII_MHZ_50_CLK_WAKEUPEVENT_0,RMII_MHZ_50_CLK_WAKEUPEVENT_1" newline bitfld.long 0x244 24. "RMII_MHZ_50_CLK_WAKEUPENABLE,- DISABLE" "RMII_MHZ_50_CLK_WAKEUPENABLE_0,RMII_MHZ_50_CLK_WAKEUPENABLE_1" newline bitfld.long 0x244 19. "RMII_MHZ_50_CLK_SLEWCONTROL,- FAST_SLEW" "RMII_MHZ_50_CLK_SLEWCONTROL_0,RMII_MHZ_50_CLK_SLEWCONTROL_1" newline bitfld.long 0x244 18. "RMII_MHZ_50_CLK_INPUTENABLE,- DISABLE" "RMII_MHZ_50_CLK_INPUTENABLE_0,RMII_MHZ_50_CLK_INPUTENABLE_1" newline bitfld.long 0x244 17. "RMII_MHZ_50_CLK_PULLTYPESELECT,- PULL_DOWN" "RMII_MHZ_50_CLK_PULLTYPESELECT_0,RMII_MHZ_50_CLK_PULLTYPESELECT_1" newline bitfld.long 0x244 16. "RMII_MHZ_50_CLK_PULLUDENABLE,- ENABLE" "RMII_MHZ_50_CLK_PULLUDENABLE_0,RMII_MHZ_50_CLK_PULLUDENABLE_1" newline bitfld.long 0x244 8. "RMII_MHZ_50_CLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RMII_MHZ_50_CLK_MODESELECT_0,RMII_MHZ_50_CLK_MODESELECT_1" newline bitfld.long 0x244 4.--7. "RMII_MHZ_50_CLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x244 0.--3. "RMII_MHZ_50_CLK_MUXMODE,- RMII_MHZ_50_CLK" "RMII_MHZ_50_CLK_MUXMODE_0,?,?,?,RMII_MHZ_50_CLK_MUXMODE_4,?,?,?,?,?,?,?,?,?,RMII_MHZ_50_CLK_MUXMODE_14,RMII_MHZ_50_CLK_MUXMODE_15" line.long 0x248 "CTRL_CORE_PAD_UART3_RXD," rbitfld.long 0x248 25. "UART3_RXD_WAKEUPEVENT,- NOWAKEUP" "UART3_RXD_WAKEUPEVENT_0,UART3_RXD_WAKEUPEVENT_1" newline bitfld.long 0x248 24. "UART3_RXD_WAKEUPENABLE,- DISABLE" "UART3_RXD_WAKEUPENABLE_0,UART3_RXD_WAKEUPENABLE_1" newline bitfld.long 0x248 19. "UART3_RXD_SLEWCONTROL,- FAST_SLEW" "UART3_RXD_SLEWCONTROL_0,UART3_RXD_SLEWCONTROL_1" newline bitfld.long 0x248 18. "UART3_RXD_INPUTENABLE,- DISABLE" "UART3_RXD_INPUTENABLE_0,UART3_RXD_INPUTENABLE_1" newline bitfld.long 0x248 17. "UART3_RXD_PULLTYPESELECT,- PULL_DOWN" "UART3_RXD_PULLTYPESELECT_0,UART3_RXD_PULLTYPESELECT_1" newline bitfld.long 0x248 16. "UART3_RXD_PULLUDENABLE,- ENABLE" "UART3_RXD_PULLUDENABLE_0,UART3_RXD_PULLUDENABLE_1" newline bitfld.long 0x248 8. "UART3_RXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART3_RXD_MODESELECT_0,UART3_RXD_MODESELECT_1" newline bitfld.long 0x248 4.--7. "UART3_RXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x248 0.--3. "UART3_RXD_MUXMODE,- UART3_RXD" "UART3_RXD_MUXMODE_0,?,UART3_RXD_MUXMODE_2,UART3_RXD_MUXMODE_3,UART3_RXD_MUXMODE_4,UART3_RXD_MUXMODE_5,?,UART3_RXD_MUXMODE_7,?,?,?,?,?,?,UART3_RXD_MUXMODE_14,UART3_RXD_MUXMODE_15" line.long 0x24C "CTRL_CORE_PAD_UART3_TXD," rbitfld.long 0x24C 25. "UART3_TXD_WAKEUPEVENT,- NOWAKEUP" "UART3_TXD_WAKEUPEVENT_0,UART3_TXD_WAKEUPEVENT_1" newline bitfld.long 0x24C 24. "UART3_TXD_WAKEUPENABLE,- DISABLE" "UART3_TXD_WAKEUPENABLE_0,UART3_TXD_WAKEUPENABLE_1" newline bitfld.long 0x24C 19. "UART3_TXD_SLEWCONTROL,- FAST_SLEW" "UART3_TXD_SLEWCONTROL_0,UART3_TXD_SLEWCONTROL_1" newline bitfld.long 0x24C 18. "UART3_TXD_INPUTENABLE,- DISABLE" "UART3_TXD_INPUTENABLE_0,UART3_TXD_INPUTENABLE_1" newline bitfld.long 0x24C 17. "UART3_TXD_PULLTYPESELECT,- PULL_DOWN" "UART3_TXD_PULLTYPESELECT_0,UART3_TXD_PULLTYPESELECT_1" newline bitfld.long 0x24C 16. "UART3_TXD_PULLUDENABLE,- ENABLE" "UART3_TXD_PULLUDENABLE_0,UART3_TXD_PULLUDENABLE_1" newline bitfld.long 0x24C 8. "UART3_TXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART3_TXD_MODESELECT_0,UART3_TXD_MODESELECT_1" newline bitfld.long 0x24C 4.--7. "UART3_TXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24C 0.--3. "UART3_TXD_MUXMODE,- UART3_TXD" "UART3_TXD_MUXMODE_0,?,UART3_TXD_MUXMODE_2,UART3_TXD_MUXMODE_3,UART3_TXD_MUXMODE_4,UART3_TXD_MUXMODE_5,?,UART3_TXD_MUXMODE_7,UART3_TXD_MUXMODE_8,?,?,?,?,?,UART3_TXD_MUXMODE_14,UART3_TXD_MUXMODE_15" line.long 0x250 "CTRL_CORE_PAD_RGMII0_TXC," rbitfld.long 0x250 25. "RGMII0_TXC_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXC_WAKEUPEVENT_0,RGMII0_TXC_WAKEUPEVENT_1" newline bitfld.long 0x250 24. "RGMII0_TXC_WAKEUPENABLE,- DISABLE" "RGMII0_TXC_WAKEUPENABLE_0,RGMII0_TXC_WAKEUPENABLE_1" newline bitfld.long 0x250 19. "RGMII0_TXC_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXC_SLEWCONTROL_0,RGMII0_TXC_SLEWCONTROL_1" newline bitfld.long 0x250 18. "RGMII0_TXC_INPUTENABLE,- DISABLE" "RGMII0_TXC_INPUTENABLE_0,RGMII0_TXC_INPUTENABLE_1" newline bitfld.long 0x250 17. "RGMII0_TXC_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXC_PULLTYPESELECT_0,RGMII0_TXC_PULLTYPESELECT_1" newline bitfld.long 0x250 16. "RGMII0_TXC_PULLUDENABLE,- ENABLE" "RGMII0_TXC_PULLUDENABLE_0,RGMII0_TXC_PULLUDENABLE_1" newline bitfld.long 0x250 8. "RGMII0_TXC_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXC_MODESELECT_0,RGMII0_TXC_MODESELECT_1" newline bitfld.long 0x250 4.--7. "RGMII0_TXC_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x250 0.--3. "RGMII0_TXC_MUXMODE,- RGMII0_TXC" "RGMII0_TXC_MUXMODE_0,RGMII0_TXC_MUXMODE_1,RGMII0_TXC_MUXMODE_2,RGMII0_TXC_MUXMODE_3,RGMII0_TXC_MUXMODE_4,RGMII0_TXC_MUXMODE_5,RGMII0_TXC_MUXMODE_6,RGMII0_TXC_MUXMODE_7,RGMII0_TXC_MUXMODE_8,?,?,?,?,?,RGMII0_TXC_MUXMODE_14,RGMII0_TXC_MUXMODE_15" line.long 0x254 "CTRL_CORE_PAD_RGMII0_TXCTL," rbitfld.long 0x254 25. "RGMII0_TXCTL_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXCTL_WAKEUPEVENT_0,RGMII0_TXCTL_WAKEUPEVENT_1" newline bitfld.long 0x254 24. "RGMII0_TXCTL_WAKEUPENABLE,- DISABLE" "RGMII0_TXCTL_WAKEUPENABLE_0,RGMII0_TXCTL_WAKEUPENABLE_1" newline bitfld.long 0x254 19. "RGMII0_TXCTL_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXCTL_SLEWCONTROL_0,RGMII0_TXCTL_SLEWCONTROL_1" newline bitfld.long 0x254 18. "RGMII0_TXCTL_INPUTENABLE,- DISABLE" "RGMII0_TXCTL_INPUTENABLE_0,RGMII0_TXCTL_INPUTENABLE_1" newline bitfld.long 0x254 17. "RGMII0_TXCTL_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXCTL_PULLTYPESELECT_0,RGMII0_TXCTL_PULLTYPESELECT_1" newline bitfld.long 0x254 16. "RGMII0_TXCTL_PULLUDENABLE,- ENABLE" "RGMII0_TXCTL_PULLUDENABLE_0,RGMII0_TXCTL_PULLUDENABLE_1" newline bitfld.long 0x254 8. "RGMII0_TXCTL_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXCTL_MODESELECT_0,RGMII0_TXCTL_MODESELECT_1" newline bitfld.long 0x254 4.--7. "RGMII0_TXCTL_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x254 0.--3. "RGMII0_TXCTL_MUXMODE,- RGMII0_TXCTL" "RGMII0_TXCTL_MUXMODE_0,RGMII0_TXCTL_MUXMODE_1,RGMII0_TXCTL_MUXMODE_2,RGMII0_TXCTL_MUXMODE_3,RGMII0_TXCTL_MUXMODE_4,RGMII0_TXCTL_MUXMODE_5,RGMII0_TXCTL_MUXMODE_6,RGMII0_TXCTL_MUXMODE_7,RGMII0_TXCTL_MUXMODE_8,?,?,?,?,?,RGMII0_TXCTL_MUXMODE_14,RGMII0_TXCTL_MUXMODE_15" line.long 0x258 "CTRL_CORE_PAD_RGMII0_TXD3," rbitfld.long 0x258 25. "RGMII0_TXD3_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD3_WAKEUPEVENT_0,RGMII0_TXD3_WAKEUPEVENT_1" newline bitfld.long 0x258 24. "RGMII0_TXD3_WAKEUPENABLE,- DISABLE" "RGMII0_TXD3_WAKEUPENABLE_0,RGMII0_TXD3_WAKEUPENABLE_1" newline bitfld.long 0x258 19. "RGMII0_TXD3_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXD3_SLEWCONTROL_0,RGMII0_TXD3_SLEWCONTROL_1" newline bitfld.long 0x258 18. "RGMII0_TXD3_INPUTENABLE,- DISABLE" "RGMII0_TXD3_INPUTENABLE_0,RGMII0_TXD3_INPUTENABLE_1" newline bitfld.long 0x258 17. "RGMII0_TXD3_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD3_PULLTYPESELECT_0,RGMII0_TXD3_PULLTYPESELECT_1" newline bitfld.long 0x258 16. "RGMII0_TXD3_PULLUDENABLE,- ENABLE" "RGMII0_TXD3_PULLUDENABLE_0,RGMII0_TXD3_PULLUDENABLE_1" newline bitfld.long 0x258 8. "RGMII0_TXD3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXD3_MODESELECT_0,RGMII0_TXD3_MODESELECT_1" newline bitfld.long 0x258 4.--7. "RGMII0_TXD3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x258 0.--3. "RGMII0_TXD3_MUXMODE,- RGMII0_TXD3" "RGMII0_TXD3_MUXMODE_0,RGMII0_TXD3_MUXMODE_1,?,RGMII0_TXD3_MUXMODE_3,RGMII0_TXD3_MUXMODE_4,RGMII0_TXD3_MUXMODE_5,RGMII0_TXD3_MUXMODE_6,RGMII0_TXD3_MUXMODE_7,RGMII0_TXD3_MUXMODE_8,?,?,?,?,?,RGMII0_TXD3_MUXMODE_14,RGMII0_TXD3_MUXMODE_15" line.long 0x25C "CTRL_CORE_PAD_RGMII0_TXD2," rbitfld.long 0x25C 25. "RGMII0_TXD2_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD2_WAKEUPEVENT_0,RGMII0_TXD2_WAKEUPEVENT_1" newline bitfld.long 0x25C 24. "RGMII0_TXD2_WAKEUPENABLE,- DISABLE" "RGMII0_TXD2_WAKEUPENABLE_0,RGMII0_TXD2_WAKEUPENABLE_1" newline bitfld.long 0x25C 19. "RGMII0_TXD2_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXD2_SLEWCONTROL_0,RGMII0_TXD2_SLEWCONTROL_1" newline bitfld.long 0x25C 18. "RGMII0_TXD2_INPUTENABLE,- DISABLE" "RGMII0_TXD2_INPUTENABLE_0,RGMII0_TXD2_INPUTENABLE_1" newline bitfld.long 0x25C 17. "RGMII0_TXD2_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD2_PULLTYPESELECT_0,RGMII0_TXD2_PULLTYPESELECT_1" newline bitfld.long 0x25C 16. "RGMII0_TXD2_PULLUDENABLE,- ENABLE" "RGMII0_TXD2_PULLUDENABLE_0,RGMII0_TXD2_PULLUDENABLE_1" newline bitfld.long 0x25C 8. "RGMII0_TXD2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXD2_MODESELECT_0,RGMII0_TXD2_MODESELECT_1" newline bitfld.long 0x25C 4.--7. "RGMII0_TXD2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x25C 0.--3. "RGMII0_TXD2_MUXMODE,- RGMII0_TXD2" "RGMII0_TXD2_MUXMODE_0,RGMII0_TXD2_MUXMODE_1,?,RGMII0_TXD2_MUXMODE_3,RGMII0_TXD2_MUXMODE_4,RGMII0_TXD2_MUXMODE_5,RGMII0_TXD2_MUXMODE_6,RGMII0_TXD2_MUXMODE_7,RGMII0_TXD2_MUXMODE_8,?,?,?,?,?,RGMII0_TXD2_MUXMODE_14,RGMII0_TXD2_MUXMODE_15" line.long 0x260 "CTRL_CORE_PAD_RGMII0_TXD1," rbitfld.long 0x260 25. "RGMII0_TXD1_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD1_WAKEUPEVENT_0,RGMII0_TXD1_WAKEUPEVENT_1" newline bitfld.long 0x260 24. "RGMII0_TXD1_WAKEUPENABLE,- DISABLE" "RGMII0_TXD1_WAKEUPENABLE_0,RGMII0_TXD1_WAKEUPENABLE_1" newline bitfld.long 0x260 19. "RGMII0_TXD1_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXD1_SLEWCONTROL_0,RGMII0_TXD1_SLEWCONTROL_1" newline bitfld.long 0x260 18. "RGMII0_TXD1_INPUTENABLE,- DISABLE" "RGMII0_TXD1_INPUTENABLE_0,RGMII0_TXD1_INPUTENABLE_1" newline bitfld.long 0x260 17. "RGMII0_TXD1_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD1_PULLTYPESELECT_0,RGMII0_TXD1_PULLTYPESELECT_1" newline bitfld.long 0x260 16. "RGMII0_TXD1_PULLUDENABLE,- ENABLE" "RGMII0_TXD1_PULLUDENABLE_0,RGMII0_TXD1_PULLUDENABLE_1" newline bitfld.long 0x260 8. "RGMII0_TXD1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXD1_MODESELECT_0,RGMII0_TXD1_MODESELECT_1" newline bitfld.long 0x260 4.--7. "RGMII0_TXD1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x260 0.--3. "RGMII0_TXD1_MUXMODE,- RGMII0_TXD1" "RGMII0_TXD1_MUXMODE_0,RGMII0_TXD1_MUXMODE_1,?,RGMII0_TXD1_MUXMODE_3,RGMII0_TXD1_MUXMODE_4,RGMII0_TXD1_MUXMODE_5,RGMII0_TXD1_MUXMODE_6,RGMII0_TXD1_MUXMODE_7,RGMII0_TXD1_MUXMODE_8,?,?,?,?,?,RGMII0_TXD1_MUXMODE_14,RGMII0_TXD1_MUXMODE_15" line.long 0x264 "CTRL_CORE_PAD_RGMII0_TXD0," rbitfld.long 0x264 25. "RGMII0_TXD0_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD0_WAKEUPEVENT_0,RGMII0_TXD0_WAKEUPEVENT_1" newline bitfld.long 0x264 24. "RGMII0_TXD0_WAKEUPENABLE,- DISABLE" "RGMII0_TXD0_WAKEUPENABLE_0,RGMII0_TXD0_WAKEUPENABLE_1" newline bitfld.long 0x264 19. "RGMII0_TXD0_SLEWCONTROL,- FAST_SLEW" "RGMII0_TXD0_SLEWCONTROL_0,RGMII0_TXD0_SLEWCONTROL_1" newline bitfld.long 0x264 18. "RGMII0_TXD0_INPUTENABLE,- DISABLE" "RGMII0_TXD0_INPUTENABLE_0,RGMII0_TXD0_INPUTENABLE_1" newline bitfld.long 0x264 17. "RGMII0_TXD0_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD0_PULLTYPESELECT_0,RGMII0_TXD0_PULLTYPESELECT_1" newline bitfld.long 0x264 16. "RGMII0_TXD0_PULLUDENABLE,- ENABLE" "RGMII0_TXD0_PULLUDENABLE_0,RGMII0_TXD0_PULLUDENABLE_1" newline bitfld.long 0x264 8. "RGMII0_TXD0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_TXD0_MODESELECT_0,RGMII0_TXD0_MODESELECT_1" newline bitfld.long 0x264 4.--7. "RGMII0_TXD0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x264 0.--3. "RGMII0_TXD0_MUXMODE,- RGMII0_TXD0" "RGMII0_TXD0_MUXMODE_0,RGMII0_TXD0_MUXMODE_1,?,RGMII0_TXD0_MUXMODE_3,RGMII0_TXD0_MUXMODE_4,?,RGMII0_TXD0_MUXMODE_6,RGMII0_TXD0_MUXMODE_7,RGMII0_TXD0_MUXMODE_8,?,?,?,?,?,RGMII0_TXD0_MUXMODE_14,RGMII0_TXD0_MUXMODE_15" line.long 0x268 "CTRL_CORE_PAD_RGMII0_RXC," rbitfld.long 0x268 25. "RGMII0_RXC_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXC_WAKEUPEVENT_0,RGMII0_RXC_WAKEUPEVENT_1" newline bitfld.long 0x268 24. "RGMII0_RXC_WAKEUPENABLE,- DISABLE" "RGMII0_RXC_WAKEUPENABLE_0,RGMII0_RXC_WAKEUPENABLE_1" newline bitfld.long 0x268 19. "RGMII0_RXC_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXC_SLEWCONTROL_0,RGMII0_RXC_SLEWCONTROL_1" newline bitfld.long 0x268 18. "RGMII0_RXC_INPUTENABLE,- DISABLE" "RGMII0_RXC_INPUTENABLE_0,RGMII0_RXC_INPUTENABLE_1" newline bitfld.long 0x268 17. "RGMII0_RXC_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXC_PULLTYPESELECT_0,RGMII0_RXC_PULLTYPESELECT_1" newline bitfld.long 0x268 16. "RGMII0_RXC_PULLUDENABLE,- ENABLE" "RGMII0_RXC_PULLUDENABLE_0,RGMII0_RXC_PULLUDENABLE_1" newline bitfld.long 0x268 8. "RGMII0_RXC_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXC_MODESELECT_0,RGMII0_RXC_MODESELECT_1" newline bitfld.long 0x268 4.--7. "RGMII0_RXC_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x268 0.--3. "RGMII0_RXC_MUXMODE,- RGMII0_RXC" "RGMII0_RXC_MUXMODE_0,?,RGMII0_RXC_MUXMODE_2,RGMII0_RXC_MUXMODE_3,RGMII0_RXC_MUXMODE_4,RGMII0_RXC_MUXMODE_5,RGMII0_RXC_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXC_MUXMODE_14,RGMII0_RXC_MUXMODE_15" line.long 0x26C "CTRL_CORE_PAD_RGMII0_RXCTL," rbitfld.long 0x26C 25. "RGMII0_RXCTL_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXCTL_WAKEUPEVENT_0,RGMII0_RXCTL_WAKEUPEVENT_1" newline bitfld.long 0x26C 24. "RGMII0_RXCTL_WAKEUPENABLE,- DISABLE" "RGMII0_RXCTL_WAKEUPENABLE_0,RGMII0_RXCTL_WAKEUPENABLE_1" newline bitfld.long 0x26C 19. "RGMII0_RXCTL_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXCTL_SLEWCONTROL_0,RGMII0_RXCTL_SLEWCONTROL_1" newline bitfld.long 0x26C 18. "RGMII0_RXCTL_INPUTENABLE,- DISABLE" "RGMII0_RXCTL_INPUTENABLE_0,RGMII0_RXCTL_INPUTENABLE_1" newline bitfld.long 0x26C 17. "RGMII0_RXCTL_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXCTL_PULLTYPESELECT_0,RGMII0_RXCTL_PULLTYPESELECT_1" newline bitfld.long 0x26C 16. "RGMII0_RXCTL_PULLUDENABLE,- ENABLE" "RGMII0_RXCTL_PULLUDENABLE_0,RGMII0_RXCTL_PULLUDENABLE_1" newline bitfld.long 0x26C 8. "RGMII0_RXCTL_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXCTL_MODESELECT_0,RGMII0_RXCTL_MODESELECT_1" newline bitfld.long 0x26C 4.--7. "RGMII0_RXCTL_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x26C 0.--3. "RGMII0_RXCTL_MUXMODE,- RGMII0_RXCTL" "RGMII0_RXCTL_MUXMODE_0,?,RGMII0_RXCTL_MUXMODE_2,RGMII0_RXCTL_MUXMODE_3,RGMII0_RXCTL_MUXMODE_4,RGMII0_RXCTL_MUXMODE_5,RGMII0_RXCTL_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXCTL_MUXMODE_14,RGMII0_RXCTL_MUXMODE_15" line.long 0x270 "CTRL_CORE_PAD_RGMII0_RXD3," rbitfld.long 0x270 25. "RGMII0_RXD3_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD3_WAKEUPEVENT_0,RGMII0_RXD3_WAKEUPEVENT_1" newline bitfld.long 0x270 24. "RGMII0_RXD3_WAKEUPENABLE,- DISABLE" "RGMII0_RXD3_WAKEUPENABLE_0,RGMII0_RXD3_WAKEUPENABLE_1" newline bitfld.long 0x270 19. "RGMII0_RXD3_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXD3_SLEWCONTROL_0,RGMII0_RXD3_SLEWCONTROL_1" newline bitfld.long 0x270 18. "RGMII0_RXD3_INPUTENABLE,- DISABLE" "RGMII0_RXD3_INPUTENABLE_0,RGMII0_RXD3_INPUTENABLE_1" newline bitfld.long 0x270 17. "RGMII0_RXD3_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD3_PULLTYPESELECT_0,RGMII0_RXD3_PULLTYPESELECT_1" newline bitfld.long 0x270 16. "RGMII0_RXD3_PULLUDENABLE,- ENABLE" "RGMII0_RXD3_PULLUDENABLE_0,RGMII0_RXD3_PULLUDENABLE_1" newline bitfld.long 0x270 8. "RGMII0_RXD3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXD3_MODESELECT_0,RGMII0_RXD3_MODESELECT_1" newline bitfld.long 0x270 4.--7. "RGMII0_RXD3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x270 0.--3. "RGMII0_RXD3_MUXMODE,- RGMII0_RXD3" "RGMII0_RXD3_MUXMODE_0,?,RGMII0_RXD3_MUXMODE_2,RGMII0_RXD3_MUXMODE_3,RGMII0_RXD3_MUXMODE_4,RGMII0_RXD3_MUXMODE_5,RGMII0_RXD3_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXD3_MUXMODE_14,RGMII0_RXD3_MUXMODE_15" line.long 0x274 "CTRL_CORE_PAD_RGMII0_RXD2," rbitfld.long 0x274 25. "RGMII0_RXD2_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD2_WAKEUPEVENT_0,RGMII0_RXD2_WAKEUPEVENT_1" newline bitfld.long 0x274 24. "RGMII0_RXD2_WAKEUPENABLE,- DISABLE" "RGMII0_RXD2_WAKEUPENABLE_0,RGMII0_RXD2_WAKEUPENABLE_1" newline bitfld.long 0x274 19. "RGMII0_RXD2_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXD2_SLEWCONTROL_0,RGMII0_RXD2_SLEWCONTROL_1" newline bitfld.long 0x274 18. "RGMII0_RXD2_INPUTENABLE,- DISABLE" "RGMII0_RXD2_INPUTENABLE_0,RGMII0_RXD2_INPUTENABLE_1" newline bitfld.long 0x274 17. "RGMII0_RXD2_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD2_PULLTYPESELECT_0,RGMII0_RXD2_PULLTYPESELECT_1" newline bitfld.long 0x274 16. "RGMII0_RXD2_PULLUDENABLE,- ENABLE" "RGMII0_RXD2_PULLUDENABLE_0,RGMII0_RXD2_PULLUDENABLE_1" newline bitfld.long 0x274 8. "RGMII0_RXD2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXD2_MODESELECT_0,RGMII0_RXD2_MODESELECT_1" newline bitfld.long 0x274 4.--7. "RGMII0_RXD2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x274 0.--3. "RGMII0_RXD2_MUXMODE,- RGMII0_RXD2" "RGMII0_RXD2_MUXMODE_0,RGMII0_RXD2_MUXMODE_1,?,RGMII0_RXD2_MUXMODE_3,RGMII0_RXD2_MUXMODE_4,?,RGMII0_RXD2_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXD2_MUXMODE_14,RGMII0_RXD2_MUXMODE_15" line.long 0x278 "CTRL_CORE_PAD_RGMII0_RXD1," rbitfld.long 0x278 25. "RGMII0_RXD1_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD1_WAKEUPEVENT_0,RGMII0_RXD1_WAKEUPEVENT_1" newline bitfld.long 0x278 24. "RGMII0_RXD1_WAKEUPENABLE,- DISABLE" "RGMII0_RXD1_WAKEUPENABLE_0,RGMII0_RXD1_WAKEUPENABLE_1" newline bitfld.long 0x278 19. "RGMII0_RXD1_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXD1_SLEWCONTROL_0,RGMII0_RXD1_SLEWCONTROL_1" newline bitfld.long 0x278 18. "RGMII0_RXD1_INPUTENABLE,- DISABLE" "RGMII0_RXD1_INPUTENABLE_0,RGMII0_RXD1_INPUTENABLE_1" newline bitfld.long 0x278 17. "RGMII0_RXD1_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD1_PULLTYPESELECT_0,RGMII0_RXD1_PULLTYPESELECT_1" newline bitfld.long 0x278 16. "RGMII0_RXD1_PULLUDENABLE,- ENABLE" "RGMII0_RXD1_PULLUDENABLE_0,RGMII0_RXD1_PULLUDENABLE_1" newline bitfld.long 0x278 8. "RGMII0_RXD1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXD1_MODESELECT_0,RGMII0_RXD1_MODESELECT_1" newline bitfld.long 0x278 4.--7. "RGMII0_RXD1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x278 0.--3. "RGMII0_RXD1_MUXMODE,- RGMII0_RXD1" "RGMII0_RXD1_MUXMODE_0,RGMII0_RXD1_MUXMODE_1,?,RGMII0_RXD1_MUXMODE_3,RGMII0_RXD1_MUXMODE_4,?,RGMII0_RXD1_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXD1_MUXMODE_14,RGMII0_RXD1_MUXMODE_15" line.long 0x27C "CTRL_CORE_PAD_RGMII0_RXD0," rbitfld.long 0x27C 25. "RGMII0_RXD0_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD0_WAKEUPEVENT_0,RGMII0_RXD0_WAKEUPEVENT_1" newline bitfld.long 0x27C 24. "RGMII0_RXD0_WAKEUPENABLE,- DISABLE" "RGMII0_RXD0_WAKEUPENABLE_0,RGMII0_RXD0_WAKEUPENABLE_1" newline bitfld.long 0x27C 19. "RGMII0_RXD0_SLEWCONTROL,- FAST_SLEW" "RGMII0_RXD0_SLEWCONTROL_0,RGMII0_RXD0_SLEWCONTROL_1" newline bitfld.long 0x27C 18. "RGMII0_RXD0_INPUTENABLE,- DISABLE" "RGMII0_RXD0_INPUTENABLE_0,RGMII0_RXD0_INPUTENABLE_1" newline bitfld.long 0x27C 17. "RGMII0_RXD0_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD0_PULLTYPESELECT_0,RGMII0_RXD0_PULLTYPESELECT_1" newline bitfld.long 0x27C 16. "RGMII0_RXD0_PULLUDENABLE,- ENABLE" "RGMII0_RXD0_PULLUDENABLE_0,RGMII0_RXD0_PULLUDENABLE_1" newline bitfld.long 0x27C 8. "RGMII0_RXD0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RGMII0_RXD0_MODESELECT_0,RGMII0_RXD0_MODESELECT_1" newline bitfld.long 0x27C 4.--7. "RGMII0_RXD0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x27C 0.--3. "RGMII0_RXD0_MUXMODE,- RGMII0_RXD0" "RGMII0_RXD0_MUXMODE_0,RGMII0_RXD0_MUXMODE_1,?,RGMII0_RXD0_MUXMODE_3,RGMII0_RXD0_MUXMODE_4,RGMII0_RXD0_MUXMODE_5,RGMII0_RXD0_MUXMODE_6,?,?,?,?,?,?,?,RGMII0_RXD0_MUXMODE_14,RGMII0_RXD0_MUXMODE_15" line.long 0x280 "CTRL_CORE_PAD_USB1_DRVVBUS," rbitfld.long 0x280 25. "USB1_DRVVBUS_WAKEUPEVENT,- NOWAKEUP" "USB1_DRVVBUS_WAKEUPEVENT_0,USB1_DRVVBUS_WAKEUPEVENT_1" newline bitfld.long 0x280 24. "USB1_DRVVBUS_WAKEUPENABLE,- DISABLE" "USB1_DRVVBUS_WAKEUPENABLE_0,USB1_DRVVBUS_WAKEUPENABLE_1" newline bitfld.long 0x280 19. "USB1_DRVVBUS_SLEWCONTROL,- FAST_SLEW" "USB1_DRVVBUS_SLEWCONTROL_0,USB1_DRVVBUS_SLEWCONTROL_1" newline bitfld.long 0x280 18. "USB1_DRVVBUS_INPUTENABLE,- DISABLE" "USB1_DRVVBUS_INPUTENABLE_0,USB1_DRVVBUS_INPUTENABLE_1" newline bitfld.long 0x280 17. "USB1_DRVVBUS_PULLTYPESELECT,- PULL_DOWN" "USB1_DRVVBUS_PULLTYPESELECT_0,USB1_DRVVBUS_PULLTYPESELECT_1" newline bitfld.long 0x280 16. "USB1_DRVVBUS_PULLUDENABLE,- ENABLE" "USB1_DRVVBUS_PULLUDENABLE_0,USB1_DRVVBUS_PULLUDENABLE_1" newline bitfld.long 0x280 8. "USB1_DRVVBUS_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "USB1_DRVVBUS_MODESELECT_0,USB1_DRVVBUS_MODESELECT_1" newline bitfld.long 0x280 4.--7. "USB1_DRVVBUS_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x280 0.--3. "USB1_DRVVBUS_MUXMODE,- USB1_DRVVBUS" "USB1_DRVVBUS_MUXMODE_0,?,?,?,?,?,?,USB1_DRVVBUS_MUXMODE_7,?,?,?,?,?,?,USB1_DRVVBUS_MUXMODE_14,USB1_DRVVBUS_MUXMODE_15" line.long 0x284 "CTRL_CORE_PAD_USB2_DRVVBUS," rbitfld.long 0x284 25. "USB2_DRVVBUS_WAKEUPEVENT,- NOWAKEUP" "USB2_DRVVBUS_WAKEUPEVENT_0,USB2_DRVVBUS_WAKEUPEVENT_1" newline bitfld.long 0x284 24. "USB2_DRVVBUS_WAKEUPENABLE,- DISABLE" "USB2_DRVVBUS_WAKEUPENABLE_0,USB2_DRVVBUS_WAKEUPENABLE_1" newline bitfld.long 0x284 19. "USB2_DRVVBUS_SLEWCONTROL,- FAST_SLEW" "USB2_DRVVBUS_SLEWCONTROL_0,USB2_DRVVBUS_SLEWCONTROL_1" newline bitfld.long 0x284 18. "USB2_DRVVBUS_INPUTENABLE,- DISABLE" "USB2_DRVVBUS_INPUTENABLE_0,USB2_DRVVBUS_INPUTENABLE_1" newline bitfld.long 0x284 17. "USB2_DRVVBUS_PULLTYPESELECT,- PULL_DOWN" "USB2_DRVVBUS_PULLTYPESELECT_0,USB2_DRVVBUS_PULLTYPESELECT_1" newline bitfld.long 0x284 16. "USB2_DRVVBUS_PULLUDENABLE,- ENABLE" "USB2_DRVVBUS_PULLUDENABLE_0,USB2_DRVVBUS_PULLUDENABLE_1" newline bitfld.long 0x284 8. "USB2_DRVVBUS_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "USB2_DRVVBUS_MODESELECT_0,USB2_DRVVBUS_MODESELECT_1" newline bitfld.long 0x284 4.--7. "USB2_DRVVBUS_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x284 0.--3. "USB2_DRVVBUS_MUXMODE,- USB2_DRVVBUS" "USB2_DRVVBUS_MUXMODE_0,?,?,?,?,?,?,USB2_DRVVBUS_MUXMODE_7,?,?,?,?,?,?,USB2_DRVVBUS_MUXMODE_14,USB2_DRVVBUS_MUXMODE_15" line.long 0x288 "CTRL_CORE_PAD_GPIO6_14," rbitfld.long 0x288 25. "GPIO6_14_WAKEUPEVENT,- NOWAKEUP" "GPIO6_14_WAKEUPEVENT_0,GPIO6_14_WAKEUPEVENT_1" newline bitfld.long 0x288 24. "GPIO6_14_WAKEUPENABLE,- DISABLE" "GPIO6_14_WAKEUPENABLE_0,GPIO6_14_WAKEUPENABLE_1" newline bitfld.long 0x288 19. "GPIO6_14_SLEWCONTROL,- FAST_SLEW" "GPIO6_14_SLEWCONTROL_0,GPIO6_14_SLEWCONTROL_1" newline bitfld.long 0x288 18. "GPIO6_14_INPUTENABLE,- DISABLE" "GPIO6_14_INPUTENABLE_0,GPIO6_14_INPUTENABLE_1" newline bitfld.long 0x288 17. "GPIO6_14_PULLTYPESELECT,- PULL_DOWN" "GPIO6_14_PULLTYPESELECT_0,GPIO6_14_PULLTYPESELECT_1" newline bitfld.long 0x288 16. "GPIO6_14_PULLUDENABLE,- ENABLE" "GPIO6_14_PULLUDENABLE_0,GPIO6_14_PULLUDENABLE_1" newline bitfld.long 0x288 8. "GPIO6_14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPIO6_14_MODESELECT_0,GPIO6_14_MODESELECT_1" newline bitfld.long 0x288 4.--7. "GPIO6_14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x288 0.--3. "GPIO6_14_MUXMODE,- GPIO6_14" "GPIO6_14_MUXMODE_0,GPIO6_14_MUXMODE_1,GPIO6_14_MUXMODE_2,GPIO6_14_MUXMODE_3,?,?,GPIO6_14_MUXMODE_6,?,GPIO6_14_MUXMODE_8,GPIO6_14_MUXMODE_9,GPIO6_14_MUXMODE_10,?,?,?,GPIO6_14_MUXMODE_14,GPIO6_14_MUXMODE_15" line.long 0x28C "CTRL_CORE_PAD_GPIO6_15," rbitfld.long 0x28C 25. "GPIO6_15_WAKEUPEVENT,- NOWAKEUP" "GPIO6_15_WAKEUPEVENT_0,GPIO6_15_WAKEUPEVENT_1" newline bitfld.long 0x28C 24. "GPIO6_15_WAKEUPENABLE,- DISABLE" "GPIO6_15_WAKEUPENABLE_0,GPIO6_15_WAKEUPENABLE_1" newline bitfld.long 0x28C 19. "GPIO6_15_SLEWCONTROL,- FAST_SLEW" "GPIO6_15_SLEWCONTROL_0,GPIO6_15_SLEWCONTROL_1" newline bitfld.long 0x28C 18. "GPIO6_15_INPUTENABLE,- DISABLE" "GPIO6_15_INPUTENABLE_0,GPIO6_15_INPUTENABLE_1" newline bitfld.long 0x28C 17. "GPIO6_15_PULLTYPESELECT,- PULL_DOWN" "GPIO6_15_PULLTYPESELECT_0,GPIO6_15_PULLTYPESELECT_1" newline bitfld.long 0x28C 16. "GPIO6_15_PULLUDENABLE,- ENABLE" "GPIO6_15_PULLUDENABLE_0,GPIO6_15_PULLUDENABLE_1" newline bitfld.long 0x28C 8. "GPIO6_15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPIO6_15_MODESELECT_0,GPIO6_15_MODESELECT_1" newline bitfld.long 0x28C 4.--7. "GPIO6_15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28C 0.--3. "GPIO6_15_MUXMODE,- GPIO6_15" "GPIO6_15_MUXMODE_0,GPIO6_15_MUXMODE_1,GPIO6_15_MUXMODE_2,GPIO6_15_MUXMODE_3,?,?,GPIO6_15_MUXMODE_6,?,GPIO6_15_MUXMODE_8,GPIO6_15_MUXMODE_9,GPIO6_15_MUXMODE_10,?,?,?,GPIO6_15_MUXMODE_14,GPIO6_15_MUXMODE_15" line.long 0x290 "CTRL_CORE_PAD_GPIO6_16," rbitfld.long 0x290 25. "GPIO6_16_WAKEUPEVENT,- NOWAKEUP" "GPIO6_16_WAKEUPEVENT_0,GPIO6_16_WAKEUPEVENT_1" newline bitfld.long 0x290 24. "GPIO6_16_WAKEUPENABLE,- DISABLE" "GPIO6_16_WAKEUPENABLE_0,GPIO6_16_WAKEUPENABLE_1" newline bitfld.long 0x290 19. "GPIO6_16_SLEWCONTROL,- FAST_SLEW" "GPIO6_16_SLEWCONTROL_0,GPIO6_16_SLEWCONTROL_1" newline bitfld.long 0x290 18. "GPIO6_16_INPUTENABLE,- DISABLE" "GPIO6_16_INPUTENABLE_0,GPIO6_16_INPUTENABLE_1" newline bitfld.long 0x290 17. "GPIO6_16_PULLTYPESELECT,- PULL_DOWN" "GPIO6_16_PULLTYPESELECT_0,GPIO6_16_PULLTYPESELECT_1" newline bitfld.long 0x290 16. "GPIO6_16_PULLUDENABLE,- ENABLE" "GPIO6_16_PULLUDENABLE_0,GPIO6_16_PULLUDENABLE_1" newline bitfld.long 0x290 8. "GPIO6_16_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPIO6_16_MODESELECT_0,GPIO6_16_MODESELECT_1" newline bitfld.long 0x290 4.--7. "GPIO6_16_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x290 0.--3. "GPIO6_16_MUXMODE,- GPIO6_16" "GPIO6_16_MUXMODE_0,GPIO6_16_MUXMODE_1,?,?,?,?,GPIO6_16_MUXMODE_6,?,GPIO6_16_MUXMODE_8,GPIO6_16_MUXMODE_9,GPIO6_16_MUXMODE_10,?,?,?,GPIO6_16_MUXMODE_14,GPIO6_16_MUXMODE_15" line.long 0x294 "CTRL_CORE_PAD_XREF_CLK0," rbitfld.long 0x294 25. "XREF_CLK0_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK0_WAKEUPEVENT_0,XREF_CLK0_WAKEUPEVENT_1" newline bitfld.long 0x294 24. "XREF_CLK0_WAKEUPENABLE,- DISABLE" "XREF_CLK0_WAKEUPENABLE_0,XREF_CLK0_WAKEUPENABLE_1" newline bitfld.long 0x294 19. "XREF_CLK0_SLEWCONTROL,- FAST_SLEW" "XREF_CLK0_SLEWCONTROL_0,XREF_CLK0_SLEWCONTROL_1" newline bitfld.long 0x294 18. "XREF_CLK0_INPUTENABLE,- DISABLE" "XREF_CLK0_INPUTENABLE_0,XREF_CLK0_INPUTENABLE_1" newline bitfld.long 0x294 17. "XREF_CLK0_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK0_PULLTYPESELECT_0,XREF_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x294 16. "XREF_CLK0_PULLUDENABLE,- ENABLE" "XREF_CLK0_PULLUDENABLE_0,XREF_CLK0_PULLUDENABLE_1" newline bitfld.long 0x294 8. "XREF_CLK0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "XREF_CLK0_MODESELECT_0,XREF_CLK0_MODESELECT_1" newline bitfld.long 0x294 4.--7. "XREF_CLK0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x294 0.--3. "XREF_CLK0_MUXMODE,- XREF_CLK0" "XREF_CLK0_MUXMODE_0,XREF_CLK0_MUXMODE_1,XREF_CLK0_MUXMODE_2,XREF_CLK0_MUXMODE_3,XREF_CLK0_MUXMODE_4,?,?,XREF_CLK0_MUXMODE_7,?,XREF_CLK0_MUXMODE_9,XREF_CLK0_MUXMODE_10,?,?,?,XREF_CLK0_MUXMODE_14,XREF_CLK0_MUXMODE_15" line.long 0x298 "CTRL_CORE_PAD_XREF_CLK1," rbitfld.long 0x298 25. "XREF_CLK1_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK1_WAKEUPEVENT_0,XREF_CLK1_WAKEUPEVENT_1" newline bitfld.long 0x298 24. "XREF_CLK1_WAKEUPENABLE,- DISABLE" "XREF_CLK1_WAKEUPENABLE_0,XREF_CLK1_WAKEUPENABLE_1" newline bitfld.long 0x298 19. "XREF_CLK1_SLEWCONTROL,- FAST_SLEW" "XREF_CLK1_SLEWCONTROL_0,XREF_CLK1_SLEWCONTROL_1" newline bitfld.long 0x298 18. "XREF_CLK1_INPUTENABLE,- DISABLE" "XREF_CLK1_INPUTENABLE_0,XREF_CLK1_INPUTENABLE_1" newline bitfld.long 0x298 17. "XREF_CLK1_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK1_PULLTYPESELECT_0,XREF_CLK1_PULLTYPESELECT_1" newline bitfld.long 0x298 16. "XREF_CLK1_PULLUDENABLE,- ENABLE" "XREF_CLK1_PULLUDENABLE_0,XREF_CLK1_PULLUDENABLE_1" newline bitfld.long 0x298 8. "XREF_CLK1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "XREF_CLK1_MODESELECT_0,XREF_CLK1_MODESELECT_1" newline bitfld.long 0x298 4.--7. "XREF_CLK1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x298 0.--3. "XREF_CLK1_MUXMODE,- XREF_CLK1" "XREF_CLK1_MUXMODE_0,XREF_CLK1_MUXMODE_1,XREF_CLK1_MUXMODE_2,XREF_CLK1_MUXMODE_3,XREF_CLK1_MUXMODE_4,?,?,XREF_CLK1_MUXMODE_7,?,?,XREF_CLK1_MUXMODE_10,?,?,?,XREF_CLK1_MUXMODE_14,XREF_CLK1_MUXMODE_15" line.long 0x29C "CTRL_CORE_PAD_XREF_CLK2," rbitfld.long 0x29C 25. "XREF_CLK2_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK2_WAKEUPEVENT_0,XREF_CLK2_WAKEUPEVENT_1" newline bitfld.long 0x29C 24. "XREF_CLK2_WAKEUPENABLE,- DISABLE" "XREF_CLK2_WAKEUPENABLE_0,XREF_CLK2_WAKEUPENABLE_1" newline bitfld.long 0x29C 19. "XREF_CLK2_SLEWCONTROL,- FAST_SLEW" "XREF_CLK2_SLEWCONTROL_0,XREF_CLK2_SLEWCONTROL_1" newline bitfld.long 0x29C 18. "XREF_CLK2_INPUTENABLE,- DISABLE" "XREF_CLK2_INPUTENABLE_0,XREF_CLK2_INPUTENABLE_1" newline bitfld.long 0x29C 17. "XREF_CLK2_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK2_PULLTYPESELECT_0,XREF_CLK2_PULLTYPESELECT_1" newline bitfld.long 0x29C 16. "XREF_CLK2_PULLUDENABLE,- ENABLE" "XREF_CLK2_PULLUDENABLE_0,XREF_CLK2_PULLUDENABLE_1" newline bitfld.long 0x29C 8. "XREF_CLK2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "XREF_CLK2_MODESELECT_0,XREF_CLK2_MODESELECT_1" newline bitfld.long 0x29C 4.--7. "XREF_CLK2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x29C 0.--3. "XREF_CLK2_MUXMODE,- XREF_CLK2" "XREF_CLK2_MUXMODE_0,XREF_CLK2_MUXMODE_1,XREF_CLK2_MUXMODE_2,XREF_CLK2_MUXMODE_3,XREF_CLK2_MUXMODE_4,?,XREF_CLK2_MUXMODE_6,?,XREF_CLK2_MUXMODE_8,?,XREF_CLK2_MUXMODE_10,?,?,?,XREF_CLK2_MUXMODE_14,XREF_CLK2_MUXMODE_15" line.long 0x2A0 "CTRL_CORE_PAD_XREF_CLK3," rbitfld.long 0x2A0 25. "XREF_CLK3_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK3_WAKEUPEVENT_0,XREF_CLK3_WAKEUPEVENT_1" newline bitfld.long 0x2A0 24. "XREF_CLK3_WAKEUPENABLE,- DISABLE" "XREF_CLK3_WAKEUPENABLE_0,XREF_CLK3_WAKEUPENABLE_1" newline bitfld.long 0x2A0 19. "XREF_CLK3_SLEWCONTROL,- FAST_SLEW" "XREF_CLK3_SLEWCONTROL_0,XREF_CLK3_SLEWCONTROL_1" newline bitfld.long 0x2A0 18. "XREF_CLK3_INPUTENABLE,- DISABLE" "XREF_CLK3_INPUTENABLE_0,XREF_CLK3_INPUTENABLE_1" newline bitfld.long 0x2A0 17. "XREF_CLK3_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK3_PULLTYPESELECT_0,XREF_CLK3_PULLTYPESELECT_1" newline bitfld.long 0x2A0 16. "XREF_CLK3_PULLUDENABLE,- ENABLE" "XREF_CLK3_PULLUDENABLE_0,XREF_CLK3_PULLUDENABLE_1" newline bitfld.long 0x2A0 8. "XREF_CLK3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "XREF_CLK3_MODESELECT_0,XREF_CLK3_MODESELECT_1" newline bitfld.long 0x2A0 4.--7. "XREF_CLK3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A0 0.--3. "XREF_CLK3_MUXMODE,- XREF_CLK3" "XREF_CLK3_MUXMODE_0,XREF_CLK3_MUXMODE_1,XREF_CLK3_MUXMODE_2,XREF_CLK3_MUXMODE_3,XREF_CLK3_MUXMODE_4,?,XREF_CLK3_MUXMODE_6,?,XREF_CLK3_MUXMODE_8,XREF_CLK3_MUXMODE_9,XREF_CLK3_MUXMODE_10,?,?,?,XREF_CLK3_MUXMODE_14,XREF_CLK3_MUXMODE_15" line.long 0x2A4 "CTRL_CORE_PAD_MCASP1_ACLKX," rbitfld.long 0x2A4 25. "MCASP1_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP1_ACLKX_WAKEUPEVENT_0,MCASP1_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x2A4 24. "MCASP1_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP1_ACLKX_WAKEUPENABLE_0,MCASP1_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x2A4 19. "MCASP1_ACLKX_SLEWCONTROL,- FAST_SLEW" "MCASP1_ACLKX_SLEWCONTROL_0,MCASP1_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x2A4 18. "MCASP1_ACLKX_INPUTENABLE,- DISABLE" "MCASP1_ACLKX_INPUTENABLE_0,MCASP1_ACLKX_INPUTENABLE_1" newline bitfld.long 0x2A4 17. "MCASP1_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP1_ACLKX_PULLTYPESELECT_0,MCASP1_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x2A4 16. "MCASP1_ACLKX_PULLUDENABLE,- ENABLE" "MCASP1_ACLKX_PULLUDENABLE_0,MCASP1_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x2A4 8. "MCASP1_ACLKX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_ACLKX_MODESELECT_0,MCASP1_ACLKX_MODESELECT_1" newline bitfld.long 0x2A4 4.--7. "MCASP1_ACLKX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A4 0.--3. "MCASP1_ACLKX_MUXMODE,- MCASP1_ACLKX" "MCASP1_ACLKX_MUXMODE_0,?,?,?,?,?,?,MCASP1_ACLKX_MUXMODE_7,?,?,MCASP1_ACLKX_MUXMODE_10,?,?,?,MCASP1_ACLKX_MUXMODE_14,MCASP1_ACLKX_MUXMODE_15" line.long 0x2A8 "CTRL_CORE_PAD_MCASP1_FSX," rbitfld.long 0x2A8 25. "MCASP1_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP1_FSX_WAKEUPEVENT_0,MCASP1_FSX_WAKEUPEVENT_1" newline bitfld.long 0x2A8 24. "MCASP1_FSX_WAKEUPENABLE,- DISABLE" "MCASP1_FSX_WAKEUPENABLE_0,MCASP1_FSX_WAKEUPENABLE_1" newline bitfld.long 0x2A8 19. "MCASP1_FSX_SLEWCONTROL,- FAST_SLEW" "MCASP1_FSX_SLEWCONTROL_0,MCASP1_FSX_SLEWCONTROL_1" newline bitfld.long 0x2A8 18. "MCASP1_FSX_INPUTENABLE,- DISABLE" "MCASP1_FSX_INPUTENABLE_0,MCASP1_FSX_INPUTENABLE_1" newline bitfld.long 0x2A8 17. "MCASP1_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP1_FSX_PULLTYPESELECT_0,MCASP1_FSX_PULLTYPESELECT_1" newline bitfld.long 0x2A8 16. "MCASP1_FSX_PULLUDENABLE,- ENABLE" "MCASP1_FSX_PULLUDENABLE_0,MCASP1_FSX_PULLUDENABLE_1" newline bitfld.long 0x2A8 8. "MCASP1_FSX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_FSX_MODESELECT_0,MCASP1_FSX_MODESELECT_1" newline bitfld.long 0x2A8 4.--7. "MCASP1_FSX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A8 0.--3. "MCASP1_FSX_MUXMODE,- MCASP1_FSX" "MCASP1_FSX_MUXMODE_0,?,?,?,?,?,?,MCASP1_FSX_MUXMODE_7,?,?,MCASP1_FSX_MUXMODE_10,?,?,?,MCASP1_FSX_MUXMODE_14,MCASP1_FSX_MUXMODE_15" line.long 0x2AC "CTRL_CORE_PAD_MCASP1_ACLKR," rbitfld.long 0x2AC 25. "MCASP1_ACLKR_WAKEUPEVENT,- NOWAKEUP" "MCASP1_ACLKR_WAKEUPEVENT_0,MCASP1_ACLKR_WAKEUPEVENT_1" newline bitfld.long 0x2AC 24. "MCASP1_ACLKR_WAKEUPENABLE,- DISABLE" "MCASP1_ACLKR_WAKEUPENABLE_0,MCASP1_ACLKR_WAKEUPENABLE_1" newline bitfld.long 0x2AC 19. "MCASP1_ACLKR_SLEWCONTROL,- FAST_SLEW" "MCASP1_ACLKR_SLEWCONTROL_0,MCASP1_ACLKR_SLEWCONTROL_1" newline bitfld.long 0x2AC 18. "MCASP1_ACLKR_INPUTENABLE,- DISABLE" "MCASP1_ACLKR_INPUTENABLE_0,MCASP1_ACLKR_INPUTENABLE_1" newline bitfld.long 0x2AC 17. "MCASP1_ACLKR_PULLTYPESELECT,- PULL_DOWN" "MCASP1_ACLKR_PULLTYPESELECT_0,MCASP1_ACLKR_PULLTYPESELECT_1" newline bitfld.long 0x2AC 16. "MCASP1_ACLKR_PULLUDENABLE,- ENABLE" "MCASP1_ACLKR_PULLUDENABLE_0,MCASP1_ACLKR_PULLUDENABLE_1" newline bitfld.long 0x2AC 8. "MCASP1_ACLKR_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_ACLKR_MODESELECT_0,MCASP1_ACLKR_MODESELECT_1" newline bitfld.long 0x2AC 4.--7. "MCASP1_ACLKR_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2AC 0.--3. "MCASP1_ACLKR_MUXMODE,- MCASP1_ACLKR" "MCASP1_ACLKR_MUXMODE_0,MCASP1_ACLKR_MUXMODE_1,?,?,?,?,MCASP1_ACLKR_MUXMODE_6,?,MCASP1_ACLKR_MUXMODE_8,?,MCASP1_ACLKR_MUXMODE_10,?,?,?,MCASP1_ACLKR_MUXMODE_14,MCASP1_ACLKR_MUXMODE_15" line.long 0x2B0 "CTRL_CORE_PAD_MCASP1_FSR," rbitfld.long 0x2B0 25. "MCASP1_FSR_WAKEUPEVENT,- NOWAKEUP" "MCASP1_FSR_WAKEUPEVENT_0,MCASP1_FSR_WAKEUPEVENT_1" newline bitfld.long 0x2B0 24. "MCASP1_FSR_WAKEUPENABLE,- DISABLE" "MCASP1_FSR_WAKEUPENABLE_0,MCASP1_FSR_WAKEUPENABLE_1" newline bitfld.long 0x2B0 19. "MCASP1_FSR_SLEWCONTROL,- FAST_SLEW" "MCASP1_FSR_SLEWCONTROL_0,MCASP1_FSR_SLEWCONTROL_1" newline bitfld.long 0x2B0 18. "MCASP1_FSR_INPUTENABLE,- DISABLE" "MCASP1_FSR_INPUTENABLE_0,MCASP1_FSR_INPUTENABLE_1" newline bitfld.long 0x2B0 17. "MCASP1_FSR_PULLTYPESELECT,- PULL_DOWN" "MCASP1_FSR_PULLTYPESELECT_0,MCASP1_FSR_PULLTYPESELECT_1" newline bitfld.long 0x2B0 16. "MCASP1_FSR_PULLUDENABLE,- ENABLE" "MCASP1_FSR_PULLUDENABLE_0,MCASP1_FSR_PULLUDENABLE_1" newline bitfld.long 0x2B0 8. "MCASP1_FSR_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_FSR_MODESELECT_0,MCASP1_FSR_MODESELECT_1" newline bitfld.long 0x2B0 4.--7. "MCASP1_FSR_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B0 0.--3. "MCASP1_FSR_MUXMODE,- MCASP1_FSR" "MCASP1_FSR_MUXMODE_0,MCASP1_FSR_MUXMODE_1,?,?,?,?,MCASP1_FSR_MUXMODE_6,?,MCASP1_FSR_MUXMODE_8,?,MCASP1_FSR_MUXMODE_10,?,?,?,MCASP1_FSR_MUXMODE_14,MCASP1_FSR_MUXMODE_15" line.long 0x2B4 "CTRL_CORE_PAD_MCASP1_AXR0," rbitfld.long 0x2B4 25. "MCASP1_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR0_WAKEUPEVENT_0,MCASP1_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x2B4 24. "MCASP1_AXR0_WAKEUPENABLE,- DISABLE" "MCASP1_AXR0_WAKEUPENABLE_0,MCASP1_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x2B4 19. "MCASP1_AXR0_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR0_SLEWCONTROL_0,MCASP1_AXR0_SLEWCONTROL_1" newline bitfld.long 0x2B4 18. "MCASP1_AXR0_INPUTENABLE,- DISABLE" "MCASP1_AXR0_INPUTENABLE_0,MCASP1_AXR0_INPUTENABLE_1" newline bitfld.long 0x2B4 17. "MCASP1_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR0_PULLTYPESELECT_0,MCASP1_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x2B4 16. "MCASP1_AXR0_PULLUDENABLE,- ENABLE" "MCASP1_AXR0_PULLUDENABLE_0,MCASP1_AXR0_PULLUDENABLE_1" newline bitfld.long 0x2B4 8. "MCASP1_AXR0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR0_MODESELECT_0,MCASP1_AXR0_MODESELECT_1" newline bitfld.long 0x2B4 4.--7. "MCASP1_AXR0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B4 0.--3. "MCASP1_AXR0_MUXMODE,- MCASP1_AXR0" "MCASP1_AXR0_MUXMODE_0,?,?,MCASP1_AXR0_MUXMODE_3,?,?,?,MCASP1_AXR0_MUXMODE_7,?,?,MCASP1_AXR0_MUXMODE_10,?,?,?,MCASP1_AXR0_MUXMODE_14,MCASP1_AXR0_MUXMODE_15" line.long 0x2B8 "CTRL_CORE_PAD_MCASP1_AXR1," rbitfld.long 0x2B8 25. "MCASP1_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR1_WAKEUPEVENT_0,MCASP1_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x2B8 24. "MCASP1_AXR1_WAKEUPENABLE,- DISABLE" "MCASP1_AXR1_WAKEUPENABLE_0,MCASP1_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x2B8 19. "MCASP1_AXR1_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR1_SLEWCONTROL_0,MCASP1_AXR1_SLEWCONTROL_1" newline bitfld.long 0x2B8 18. "MCASP1_AXR1_INPUTENABLE,- DISABLE" "MCASP1_AXR1_INPUTENABLE_0,MCASP1_AXR1_INPUTENABLE_1" newline bitfld.long 0x2B8 17. "MCASP1_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR1_PULLTYPESELECT_0,MCASP1_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x2B8 16. "MCASP1_AXR1_PULLUDENABLE,- ENABLE" "MCASP1_AXR1_PULLUDENABLE_0,MCASP1_AXR1_PULLUDENABLE_1" newline bitfld.long 0x2B8 8. "MCASP1_AXR1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR1_MODESELECT_0,MCASP1_AXR1_MODESELECT_1" newline bitfld.long 0x2B8 4.--7. "MCASP1_AXR1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B8 0.--3. "MCASP1_AXR1_MUXMODE,- MCASP1_AXR1" "MCASP1_AXR1_MUXMODE_0,?,?,MCASP1_AXR1_MUXMODE_3,?,?,?,MCASP1_AXR1_MUXMODE_7,?,?,MCASP1_AXR1_MUXMODE_10,?,?,?,MCASP1_AXR1_MUXMODE_14,MCASP1_AXR1_MUXMODE_15" line.long 0x2BC "CTRL_CORE_PAD_MCASP1_AXR2," rbitfld.long 0x2BC 25. "MCASP1_AXR2_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR2_WAKEUPEVENT_0,MCASP1_AXR2_WAKEUPEVENT_1" newline bitfld.long 0x2BC 24. "MCASP1_AXR2_WAKEUPENABLE,- DISABLE" "MCASP1_AXR2_WAKEUPENABLE_0,MCASP1_AXR2_WAKEUPENABLE_1" newline bitfld.long 0x2BC 19. "MCASP1_AXR2_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR2_SLEWCONTROL_0,MCASP1_AXR2_SLEWCONTROL_1" newline bitfld.long 0x2BC 18. "MCASP1_AXR2_INPUTENABLE,- DISABLE" "MCASP1_AXR2_INPUTENABLE_0,MCASP1_AXR2_INPUTENABLE_1" newline bitfld.long 0x2BC 17. "MCASP1_AXR2_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR2_PULLTYPESELECT_0,MCASP1_AXR2_PULLTYPESELECT_1" newline bitfld.long 0x2BC 16. "MCASP1_AXR2_PULLUDENABLE,- ENABLE" "MCASP1_AXR2_PULLUDENABLE_0,MCASP1_AXR2_PULLUDENABLE_1" newline bitfld.long 0x2BC 8. "MCASP1_AXR2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR2_MODESELECT_0,MCASP1_AXR2_MODESELECT_1" newline bitfld.long 0x2BC 4.--7. "MCASP1_AXR2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2BC 0.--3. "MCASP1_AXR2_MUXMODE,- MCASP1_AXR2" "MCASP1_AXR2_MUXMODE_0,MCASP1_AXR2_MUXMODE_1,?,MCASP1_AXR2_MUXMODE_3,?,?,MCASP1_AXR2_MUXMODE_6,?,MCASP1_AXR2_MUXMODE_8,?,?,?,?,?,MCASP1_AXR2_MUXMODE_14,MCASP1_AXR2_MUXMODE_15" line.long 0x2C0 "CTRL_CORE_PAD_MCASP1_AXR3," rbitfld.long 0x2C0 25. "MCASP1_AXR3_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR3_WAKEUPEVENT_0,MCASP1_AXR3_WAKEUPEVENT_1" newline bitfld.long 0x2C0 24. "MCASP1_AXR3_WAKEUPENABLE,- DISABLE" "MCASP1_AXR3_WAKEUPENABLE_0,MCASP1_AXR3_WAKEUPENABLE_1" newline bitfld.long 0x2C0 19. "MCASP1_AXR3_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR3_SLEWCONTROL_0,MCASP1_AXR3_SLEWCONTROL_1" newline bitfld.long 0x2C0 18. "MCASP1_AXR3_INPUTENABLE,- DISABLE" "MCASP1_AXR3_INPUTENABLE_0,MCASP1_AXR3_INPUTENABLE_1" newline bitfld.long 0x2C0 17. "MCASP1_AXR3_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR3_PULLTYPESELECT_0,MCASP1_AXR3_PULLTYPESELECT_1" newline bitfld.long 0x2C0 16. "MCASP1_AXR3_PULLUDENABLE,- ENABLE" "MCASP1_AXR3_PULLUDENABLE_0,MCASP1_AXR3_PULLUDENABLE_1" newline bitfld.long 0x2C0 8. "MCASP1_AXR3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR3_MODESELECT_0,MCASP1_AXR3_MODESELECT_1" newline bitfld.long 0x2C0 4.--7. "MCASP1_AXR3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C0 0.--3. "MCASP1_AXR3_MUXMODE,- MCASP1_AXR3" "MCASP1_AXR3_MUXMODE_0,MCASP1_AXR3_MUXMODE_1,?,MCASP1_AXR3_MUXMODE_3,?,?,MCASP1_AXR3_MUXMODE_6,?,MCASP1_AXR3_MUXMODE_8,?,?,?,?,?,MCASP1_AXR3_MUXMODE_14,MCASP1_AXR3_MUXMODE_15" line.long 0x2C4 "CTRL_CORE_PAD_MCASP1_AXR4," rbitfld.long 0x2C4 25. "MCASP1_AXR4_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR4_WAKEUPEVENT_0,MCASP1_AXR4_WAKEUPEVENT_1" newline bitfld.long 0x2C4 24. "MCASP1_AXR4_WAKEUPENABLE,- DISABLE" "MCASP1_AXR4_WAKEUPENABLE_0,MCASP1_AXR4_WAKEUPENABLE_1" newline bitfld.long 0x2C4 19. "MCASP1_AXR4_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR4_SLEWCONTROL_0,MCASP1_AXR4_SLEWCONTROL_1" newline bitfld.long 0x2C4 18. "MCASP1_AXR4_INPUTENABLE,- DISABLE" "MCASP1_AXR4_INPUTENABLE_0,MCASP1_AXR4_INPUTENABLE_1" newline bitfld.long 0x2C4 17. "MCASP1_AXR4_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR4_PULLTYPESELECT_0,MCASP1_AXR4_PULLTYPESELECT_1" newline bitfld.long 0x2C4 16. "MCASP1_AXR4_PULLUDENABLE,- ENABLE" "MCASP1_AXR4_PULLUDENABLE_0,MCASP1_AXR4_PULLUDENABLE_1" newline bitfld.long 0x2C4 8. "MCASP1_AXR4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR4_MODESELECT_0,MCASP1_AXR4_MODESELECT_1" newline bitfld.long 0x2C4 4.--7. "MCASP1_AXR4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C4 0.--3. "MCASP1_AXR4_MUXMODE,- MCASP1_AXR4" "MCASP1_AXR4_MUXMODE_0,MCASP1_AXR4_MUXMODE_1,?,?,?,?,MCASP1_AXR4_MUXMODE_6,?,MCASP1_AXR4_MUXMODE_8,?,?,?,?,?,MCASP1_AXR4_MUXMODE_14,MCASP1_AXR4_MUXMODE_15" line.long 0x2C8 "CTRL_CORE_PAD_MCASP1_AXR5," rbitfld.long 0x2C8 25. "MCASP1_AXR5_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR5_WAKEUPEVENT_0,MCASP1_AXR5_WAKEUPEVENT_1" newline bitfld.long 0x2C8 24. "MCASP1_AXR5_WAKEUPENABLE,- DISABLE" "MCASP1_AXR5_WAKEUPENABLE_0,MCASP1_AXR5_WAKEUPENABLE_1" newline bitfld.long 0x2C8 19. "MCASP1_AXR5_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR5_SLEWCONTROL_0,MCASP1_AXR5_SLEWCONTROL_1" newline bitfld.long 0x2C8 18. "MCASP1_AXR5_INPUTENABLE,- DISABLE" "MCASP1_AXR5_INPUTENABLE_0,MCASP1_AXR5_INPUTENABLE_1" newline bitfld.long 0x2C8 17. "MCASP1_AXR5_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR5_PULLTYPESELECT_0,MCASP1_AXR5_PULLTYPESELECT_1" newline bitfld.long 0x2C8 16. "MCASP1_AXR5_PULLUDENABLE,- ENABLE" "MCASP1_AXR5_PULLUDENABLE_0,MCASP1_AXR5_PULLUDENABLE_1" newline bitfld.long 0x2C8 8. "MCASP1_AXR5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR5_MODESELECT_0,MCASP1_AXR5_MODESELECT_1" newline bitfld.long 0x2C8 4.--7. "MCASP1_AXR5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C8 0.--3. "MCASP1_AXR5_MUXMODE,- MCASP1_AXR5" "MCASP1_AXR5_MUXMODE_0,MCASP1_AXR5_MUXMODE_1,?,?,?,?,MCASP1_AXR5_MUXMODE_6,?,MCASP1_AXR5_MUXMODE_8,?,?,?,?,?,MCASP1_AXR5_MUXMODE_14,MCASP1_AXR5_MUXMODE_15" line.long 0x2CC "CTRL_CORE_PAD_MCASP1_AXR6," rbitfld.long 0x2CC 25. "MCASP1_AXR6_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR6_WAKEUPEVENT_0,MCASP1_AXR6_WAKEUPEVENT_1" newline bitfld.long 0x2CC 24. "MCASP1_AXR6_WAKEUPENABLE,- DISABLE" "MCASP1_AXR6_WAKEUPENABLE_0,MCASP1_AXR6_WAKEUPENABLE_1" newline bitfld.long 0x2CC 19. "MCASP1_AXR6_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR6_SLEWCONTROL_0,MCASP1_AXR6_SLEWCONTROL_1" newline bitfld.long 0x2CC 18. "MCASP1_AXR6_INPUTENABLE,- DISABLE" "MCASP1_AXR6_INPUTENABLE_0,MCASP1_AXR6_INPUTENABLE_1" newline bitfld.long 0x2CC 17. "MCASP1_AXR6_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR6_PULLTYPESELECT_0,MCASP1_AXR6_PULLTYPESELECT_1" newline bitfld.long 0x2CC 16. "MCASP1_AXR6_PULLUDENABLE,- ENABLE" "MCASP1_AXR6_PULLUDENABLE_0,MCASP1_AXR6_PULLUDENABLE_1" newline bitfld.long 0x2CC 8. "MCASP1_AXR6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR6_MODESELECT_0,MCASP1_AXR6_MODESELECT_1" newline bitfld.long 0x2CC 4.--7. "MCASP1_AXR6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2CC 0.--3. "MCASP1_AXR6_MUXMODE,- MCASP1_AXR6" "MCASP1_AXR6_MUXMODE_0,MCASP1_AXR6_MUXMODE_1,?,?,?,?,MCASP1_AXR6_MUXMODE_6,?,MCASP1_AXR6_MUXMODE_8,?,?,?,?,?,MCASP1_AXR6_MUXMODE_14,MCASP1_AXR6_MUXMODE_15" line.long 0x2D0 "CTRL_CORE_PAD_MCASP1_AXR7," rbitfld.long 0x2D0 25. "MCASP1_AXR7_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR7_WAKEUPEVENT_0,MCASP1_AXR7_WAKEUPEVENT_1" newline bitfld.long 0x2D0 24. "MCASP1_AXR7_WAKEUPENABLE,- DISABLE" "MCASP1_AXR7_WAKEUPENABLE_0,MCASP1_AXR7_WAKEUPENABLE_1" newline bitfld.long 0x2D0 19. "MCASP1_AXR7_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR7_SLEWCONTROL_0,MCASP1_AXR7_SLEWCONTROL_1" newline bitfld.long 0x2D0 18. "MCASP1_AXR7_INPUTENABLE,- DISABLE" "MCASP1_AXR7_INPUTENABLE_0,MCASP1_AXR7_INPUTENABLE_1" newline bitfld.long 0x2D0 17. "MCASP1_AXR7_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR7_PULLTYPESELECT_0,MCASP1_AXR7_PULLTYPESELECT_1" newline bitfld.long 0x2D0 16. "MCASP1_AXR7_PULLUDENABLE,- ENABLE" "MCASP1_AXR7_PULLUDENABLE_0,MCASP1_AXR7_PULLUDENABLE_1" newline bitfld.long 0x2D0 8. "MCASP1_AXR7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR7_MODESELECT_0,MCASP1_AXR7_MODESELECT_1" newline bitfld.long 0x2D0 4.--7. "MCASP1_AXR7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D0 0.--3. "MCASP1_AXR7_MUXMODE,- MCASP1_AXR7" "MCASP1_AXR7_MUXMODE_0,MCASP1_AXR7_MUXMODE_1,?,?,?,?,MCASP1_AXR7_MUXMODE_6,?,MCASP1_AXR7_MUXMODE_8,?,MCASP1_AXR7_MUXMODE_10,?,?,?,MCASP1_AXR7_MUXMODE_14,MCASP1_AXR7_MUXMODE_15" line.long 0x2D4 "CTRL_CORE_PAD_MCASP1_AXR8," rbitfld.long 0x2D4 25. "MCASP1_AXR8_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR8_WAKEUPEVENT_0,MCASP1_AXR8_WAKEUPEVENT_1" newline bitfld.long 0x2D4 24. "MCASP1_AXR8_WAKEUPENABLE,- DISABLE" "MCASP1_AXR8_WAKEUPENABLE_0,MCASP1_AXR8_WAKEUPENABLE_1" newline bitfld.long 0x2D4 19. "MCASP1_AXR8_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR8_SLEWCONTROL_0,MCASP1_AXR8_SLEWCONTROL_1" newline bitfld.long 0x2D4 18. "MCASP1_AXR8_INPUTENABLE,- DISABLE" "MCASP1_AXR8_INPUTENABLE_0,MCASP1_AXR8_INPUTENABLE_1" newline bitfld.long 0x2D4 17. "MCASP1_AXR8_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR8_PULLTYPESELECT_0,MCASP1_AXR8_PULLTYPESELECT_1" newline bitfld.long 0x2D4 16. "MCASP1_AXR8_PULLUDENABLE,- ENABLE" "MCASP1_AXR8_PULLUDENABLE_0,MCASP1_AXR8_PULLUDENABLE_1" newline bitfld.long 0x2D4 8. "MCASP1_AXR8_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR8_MODESELECT_0,MCASP1_AXR8_MODESELECT_1" newline bitfld.long 0x2D4 4.--7. "MCASP1_AXR8_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D4 0.--3. "MCASP1_AXR8_MUXMODE,- MCASP1_AXR8" "MCASP1_AXR8_MUXMODE_0,MCASP1_AXR8_MUXMODE_1,?,MCASP1_AXR8_MUXMODE_3,?,?,?,MCASP1_AXR8_MUXMODE_7,?,?,MCASP1_AXR8_MUXMODE_10,?,?,?,MCASP1_AXR8_MUXMODE_14,MCASP1_AXR8_MUXMODE_15" line.long 0x2D8 "CTRL_CORE_PAD_MCASP1_AXR9," rbitfld.long 0x2D8 25. "MCASP1_AXR9_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR9_WAKEUPEVENT_0,MCASP1_AXR9_WAKEUPEVENT_1" newline bitfld.long 0x2D8 24. "MCASP1_AXR9_WAKEUPENABLE,- DISABLE" "MCASP1_AXR9_WAKEUPENABLE_0,MCASP1_AXR9_WAKEUPENABLE_1" newline bitfld.long 0x2D8 19. "MCASP1_AXR9_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR9_SLEWCONTROL_0,MCASP1_AXR9_SLEWCONTROL_1" newline bitfld.long 0x2D8 18. "MCASP1_AXR9_INPUTENABLE,- DISABLE" "MCASP1_AXR9_INPUTENABLE_0,MCASP1_AXR9_INPUTENABLE_1" newline bitfld.long 0x2D8 17. "MCASP1_AXR9_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR9_PULLTYPESELECT_0,MCASP1_AXR9_PULLTYPESELECT_1" newline bitfld.long 0x2D8 16. "MCASP1_AXR9_PULLUDENABLE,- ENABLE" "MCASP1_AXR9_PULLUDENABLE_0,MCASP1_AXR9_PULLUDENABLE_1" newline bitfld.long 0x2D8 8. "MCASP1_AXR9_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR9_MODESELECT_0,MCASP1_AXR9_MODESELECT_1" newline bitfld.long 0x2D8 4.--7. "MCASP1_AXR9_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D8 0.--3. "MCASP1_AXR9_MUXMODE,- MCASP1_AXR9" "MCASP1_AXR9_MUXMODE_0,MCASP1_AXR9_MUXMODE_1,?,MCASP1_AXR9_MUXMODE_3,?,?,?,MCASP1_AXR9_MUXMODE_7,?,?,MCASP1_AXR9_MUXMODE_10,?,?,?,MCASP1_AXR9_MUXMODE_14,MCASP1_AXR9_MUXMODE_15" line.long 0x2DC "CTRL_CORE_PAD_MCASP1_AXR10," rbitfld.long 0x2DC 25. "MCASP1_AXR10_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR10_WAKEUPEVENT_0,MCASP1_AXR10_WAKEUPEVENT_1" newline bitfld.long 0x2DC 24. "MCASP1_AXR10_WAKEUPENABLE,- DISABLE" "MCASP1_AXR10_WAKEUPENABLE_0,MCASP1_AXR10_WAKEUPENABLE_1" newline bitfld.long 0x2DC 19. "MCASP1_AXR10_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR10_SLEWCONTROL_0,MCASP1_AXR10_SLEWCONTROL_1" newline bitfld.long 0x2DC 18. "MCASP1_AXR10_INPUTENABLE,- DISABLE" "MCASP1_AXR10_INPUTENABLE_0,MCASP1_AXR10_INPUTENABLE_1" newline bitfld.long 0x2DC 17. "MCASP1_AXR10_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR10_PULLTYPESELECT_0,MCASP1_AXR10_PULLTYPESELECT_1" newline bitfld.long 0x2DC 16. "MCASP1_AXR10_PULLUDENABLE,- ENABLE" "MCASP1_AXR10_PULLUDENABLE_0,MCASP1_AXR10_PULLUDENABLE_1" newline bitfld.long 0x2DC 8. "MCASP1_AXR10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR10_MODESELECT_0,MCASP1_AXR10_MODESELECT_1" newline bitfld.long 0x2DC 4.--7. "MCASP1_AXR10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2DC 0.--3. "MCASP1_AXR10_MUXMODE,- MCASP1_AXR10" "MCASP1_AXR10_MUXMODE_0,MCASP1_AXR10_MUXMODE_1,MCASP1_AXR10_MUXMODE_2,MCASP1_AXR10_MUXMODE_3,?,?,?,MCASP1_AXR10_MUXMODE_7,?,?,MCASP1_AXR10_MUXMODE_10,?,?,?,MCASP1_AXR10_MUXMODE_14,MCASP1_AXR10_MUXMODE_15" line.long 0x2E0 "CTRL_CORE_PAD_MCASP1_AXR11," rbitfld.long 0x2E0 25. "MCASP1_AXR11_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR11_WAKEUPEVENT_0,MCASP1_AXR11_WAKEUPEVENT_1" newline bitfld.long 0x2E0 24. "MCASP1_AXR11_WAKEUPENABLE,- DISABLE" "MCASP1_AXR11_WAKEUPENABLE_0,MCASP1_AXR11_WAKEUPENABLE_1" newline bitfld.long 0x2E0 19. "MCASP1_AXR11_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR11_SLEWCONTROL_0,MCASP1_AXR11_SLEWCONTROL_1" newline bitfld.long 0x2E0 18. "MCASP1_AXR11_INPUTENABLE,- DISABLE" "MCASP1_AXR11_INPUTENABLE_0,MCASP1_AXR11_INPUTENABLE_1" newline bitfld.long 0x2E0 17. "MCASP1_AXR11_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR11_PULLTYPESELECT_0,MCASP1_AXR11_PULLTYPESELECT_1" newline bitfld.long 0x2E0 16. "MCASP1_AXR11_PULLUDENABLE,- ENABLE" "MCASP1_AXR11_PULLUDENABLE_0,MCASP1_AXR11_PULLUDENABLE_1" newline bitfld.long 0x2E0 8. "MCASP1_AXR11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR11_MODESELECT_0,MCASP1_AXR11_MODESELECT_1" newline bitfld.long 0x2E0 4.--7. "MCASP1_AXR11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E0 0.--3. "MCASP1_AXR11_MUXMODE,- MCASP1_AXR11" "MCASP1_AXR11_MUXMODE_0,MCASP1_AXR11_MUXMODE_1,MCASP1_AXR11_MUXMODE_2,MCASP1_AXR11_MUXMODE_3,?,?,?,MCASP1_AXR11_MUXMODE_7,?,?,MCASP1_AXR11_MUXMODE_10,?,?,?,MCASP1_AXR11_MUXMODE_14,MCASP1_AXR11_MUXMODE_15" line.long 0x2E4 "CTRL_CORE_PAD_MCASP1_AXR12," rbitfld.long 0x2E4 25. "MCASP1_AXR12_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR12_WAKEUPEVENT_0,MCASP1_AXR12_WAKEUPEVENT_1" newline bitfld.long 0x2E4 24. "MCASP1_AXR12_WAKEUPENABLE,- DISABLE" "MCASP1_AXR12_WAKEUPENABLE_0,MCASP1_AXR12_WAKEUPENABLE_1" newline bitfld.long 0x2E4 19. "MCASP1_AXR12_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR12_SLEWCONTROL_0,MCASP1_AXR12_SLEWCONTROL_1" newline bitfld.long 0x2E4 18. "MCASP1_AXR12_INPUTENABLE,- DISABLE" "MCASP1_AXR12_INPUTENABLE_0,MCASP1_AXR12_INPUTENABLE_1" newline bitfld.long 0x2E4 17. "MCASP1_AXR12_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR12_PULLTYPESELECT_0,MCASP1_AXR12_PULLTYPESELECT_1" newline bitfld.long 0x2E4 16. "MCASP1_AXR12_PULLUDENABLE,- ENABLE" "MCASP1_AXR12_PULLUDENABLE_0,MCASP1_AXR12_PULLUDENABLE_1" newline bitfld.long 0x2E4 8. "MCASP1_AXR12_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR12_MODESELECT_0,MCASP1_AXR12_MODESELECT_1" newline bitfld.long 0x2E4 4.--7. "MCASP1_AXR12_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E4 0.--3. "MCASP1_AXR12_MUXMODE,- MCASP1_AXR12" "MCASP1_AXR12_MUXMODE_0,MCASP1_AXR12_MUXMODE_1,?,MCASP1_AXR12_MUXMODE_3,?,?,?,MCASP1_AXR12_MUXMODE_7,?,?,MCASP1_AXR12_MUXMODE_10,?,?,?,MCASP1_AXR12_MUXMODE_14,MCASP1_AXR12_MUXMODE_15" line.long 0x2E8 "CTRL_CORE_PAD_MCASP1_AXR13," rbitfld.long 0x2E8 25. "MCASP1_AXR13_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR13_WAKEUPEVENT_0,MCASP1_AXR13_WAKEUPEVENT_1" newline bitfld.long 0x2E8 24. "MCASP1_AXR13_WAKEUPENABLE,- DISABLE" "MCASP1_AXR13_WAKEUPENABLE_0,MCASP1_AXR13_WAKEUPENABLE_1" newline bitfld.long 0x2E8 19. "MCASP1_AXR13_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR13_SLEWCONTROL_0,MCASP1_AXR13_SLEWCONTROL_1" newline bitfld.long 0x2E8 18. "MCASP1_AXR13_INPUTENABLE,- DISABLE" "MCASP1_AXR13_INPUTENABLE_0,MCASP1_AXR13_INPUTENABLE_1" newline bitfld.long 0x2E8 17. "MCASP1_AXR13_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR13_PULLTYPESELECT_0,MCASP1_AXR13_PULLTYPESELECT_1" newline bitfld.long 0x2E8 16. "MCASP1_AXR13_PULLUDENABLE,- ENABLE" "MCASP1_AXR13_PULLUDENABLE_0,MCASP1_AXR13_PULLUDENABLE_1" newline bitfld.long 0x2E8 8. "MCASP1_AXR13_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR13_MODESELECT_0,MCASP1_AXR13_MODESELECT_1" newline bitfld.long 0x2E8 4.--7. "MCASP1_AXR13_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E8 0.--3. "MCASP1_AXR13_MUXMODE,- MCASP1_AXR13" "MCASP1_AXR13_MUXMODE_0,MCASP1_AXR13_MUXMODE_1,?,?,?,?,?,MCASP1_AXR13_MUXMODE_7,?,?,MCASP1_AXR13_MUXMODE_10,?,?,?,MCASP1_AXR13_MUXMODE_14,MCASP1_AXR13_MUXMODE_15" line.long 0x2EC "CTRL_CORE_PAD_MCASP1_AXR14," rbitfld.long 0x2EC 25. "MCASP1_AXR14_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR14_WAKEUPEVENT_0,MCASP1_AXR14_WAKEUPEVENT_1" newline bitfld.long 0x2EC 24. "MCASP1_AXR14_WAKEUPENABLE,- DISABLE" "MCASP1_AXR14_WAKEUPENABLE_0,MCASP1_AXR14_WAKEUPENABLE_1" newline bitfld.long 0x2EC 19. "MCASP1_AXR14_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR14_SLEWCONTROL_0,MCASP1_AXR14_SLEWCONTROL_1" newline bitfld.long 0x2EC 18. "MCASP1_AXR14_INPUTENABLE,- DISABLE" "MCASP1_AXR14_INPUTENABLE_0,MCASP1_AXR14_INPUTENABLE_1" newline bitfld.long 0x2EC 17. "MCASP1_AXR14_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR14_PULLTYPESELECT_0,MCASP1_AXR14_PULLTYPESELECT_1" newline bitfld.long 0x2EC 16. "MCASP1_AXR14_PULLUDENABLE,- ENABLE" "MCASP1_AXR14_PULLUDENABLE_0,MCASP1_AXR14_PULLUDENABLE_1" newline bitfld.long 0x2EC 8. "MCASP1_AXR14_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR14_MODESELECT_0,MCASP1_AXR14_MODESELECT_1" newline bitfld.long 0x2EC 4.--7. "MCASP1_AXR14_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2EC 0.--3. "MCASP1_AXR14_MUXMODE,- MCASP1_AXR14" "MCASP1_AXR14_MUXMODE_0,MCASP1_AXR14_MUXMODE_1,MCASP1_AXR14_MUXMODE_2,?,?,?,?,MCASP1_AXR14_MUXMODE_7,?,?,MCASP1_AXR14_MUXMODE_10,?,?,?,MCASP1_AXR14_MUXMODE_14,MCASP1_AXR14_MUXMODE_15" line.long 0x2F0 "CTRL_CORE_PAD_MCASP1_AXR15," rbitfld.long 0x2F0 25. "MCASP1_AXR15_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR15_WAKEUPEVENT_0,MCASP1_AXR15_WAKEUPEVENT_1" newline bitfld.long 0x2F0 24. "MCASP1_AXR15_WAKEUPENABLE,- DISABLE" "MCASP1_AXR15_WAKEUPENABLE_0,MCASP1_AXR15_WAKEUPENABLE_1" newline bitfld.long 0x2F0 19. "MCASP1_AXR15_SLEWCONTROL,- FAST_SLEW" "MCASP1_AXR15_SLEWCONTROL_0,MCASP1_AXR15_SLEWCONTROL_1" newline bitfld.long 0x2F0 18. "MCASP1_AXR15_INPUTENABLE,- DISABLE" "MCASP1_AXR15_INPUTENABLE_0,MCASP1_AXR15_INPUTENABLE_1" newline bitfld.long 0x2F0 17. "MCASP1_AXR15_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR15_PULLTYPESELECT_0,MCASP1_AXR15_PULLTYPESELECT_1" newline bitfld.long 0x2F0 16. "MCASP1_AXR15_PULLUDENABLE,- ENABLE" "MCASP1_AXR15_PULLUDENABLE_0,MCASP1_AXR15_PULLUDENABLE_1" newline bitfld.long 0x2F0 8. "MCASP1_AXR15_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP1_AXR15_MODESELECT_0,MCASP1_AXR15_MODESELECT_1" newline bitfld.long 0x2F0 4.--7. "MCASP1_AXR15_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F0 0.--3. "MCASP1_AXR15_MUXMODE,- MCASP1_AXR15" "MCASP1_AXR15_MUXMODE_0,MCASP1_AXR15_MUXMODE_1,MCASP1_AXR15_MUXMODE_2,?,?,?,?,MCASP1_AXR15_MUXMODE_7,?,?,MCASP1_AXR15_MUXMODE_10,?,?,?,MCASP1_AXR15_MUXMODE_14,MCASP1_AXR15_MUXMODE_15" line.long 0x2F4 "CTRL_CORE_PAD_MCASP2_ACLKX," rbitfld.long 0x2F4 25. "MCASP2_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP2_ACLKX_WAKEUPEVENT_0,MCASP2_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x2F4 24. "MCASP2_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP2_ACLKX_WAKEUPENABLE_0,MCASP2_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x2F4 19. "MCASP2_ACLKX_SLEWCONTROL,- FAST_SLEW" "MCASP2_ACLKX_SLEWCONTROL_0,MCASP2_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x2F4 18. "MCASP2_ACLKX_INPUTENABLE,- DISABLE" "MCASP2_ACLKX_INPUTENABLE_0,MCASP2_ACLKX_INPUTENABLE_1" newline bitfld.long 0x2F4 17. "MCASP2_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP2_ACLKX_PULLTYPESELECT_0,MCASP2_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x2F4 16. "MCASP2_ACLKX_PULLUDENABLE,- ENABLE" "MCASP2_ACLKX_PULLUDENABLE_0,MCASP2_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x2F4 8. "MCASP2_ACLKX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_ACLKX_MODESELECT_0,MCASP2_ACLKX_MODESELECT_1" newline bitfld.long 0x2F4 4.--7. "MCASP2_ACLKX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F4 0.--3. "MCASP2_ACLKX_MUXMODE,- MCASP2_ACLKX" "MCASP2_ACLKX_MUXMODE_0,?,?,?,?,?,?,MCASP2_ACLKX_MUXMODE_7,?,?,?,?,?,?,?,MCASP2_ACLKX_MUXMODE_15" line.long 0x2F8 "CTRL_CORE_PAD_MCASP2_FSX," rbitfld.long 0x2F8 25. "MCASP2_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP2_FSX_WAKEUPEVENT_0,MCASP2_FSX_WAKEUPEVENT_1" newline bitfld.long 0x2F8 24. "MCASP2_FSX_WAKEUPENABLE,- DISABLE" "MCASP2_FSX_WAKEUPENABLE_0,MCASP2_FSX_WAKEUPENABLE_1" newline bitfld.long 0x2F8 19. "MCASP2_FSX_SLEWCONTROL,- FAST_SLEW" "MCASP2_FSX_SLEWCONTROL_0,MCASP2_FSX_SLEWCONTROL_1" newline bitfld.long 0x2F8 18. "MCASP2_FSX_INPUTENABLE,- DISABLE" "MCASP2_FSX_INPUTENABLE_0,MCASP2_FSX_INPUTENABLE_1" newline bitfld.long 0x2F8 17. "MCASP2_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP2_FSX_PULLTYPESELECT_0,MCASP2_FSX_PULLTYPESELECT_1" newline bitfld.long 0x2F8 16. "MCASP2_FSX_PULLUDENABLE,- ENABLE" "MCASP2_FSX_PULLUDENABLE_0,MCASP2_FSX_PULLUDENABLE_1" newline bitfld.long 0x2F8 8. "MCASP2_FSX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_FSX_MODESELECT_0,MCASP2_FSX_MODESELECT_1" newline bitfld.long 0x2F8 4.--7. "MCASP2_FSX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F8 0.--3. "MCASP2_FSX_MUXMODE,- MCASP2_FSX" "MCASP2_FSX_MUXMODE_0,?,?,?,?,?,?,MCASP2_FSX_MUXMODE_7,?,?,?,?,?,?,?,MCASP2_FSX_MUXMODE_15" line.long 0x2FC "CTRL_CORE_PAD_MCASP2_ACLKR," rbitfld.long 0x2FC 25. "MCASP2_ACLKR_WAKEUPEVENT,- NOWAKEUP" "MCASP2_ACLKR_WAKEUPEVENT_0,MCASP2_ACLKR_WAKEUPEVENT_1" newline bitfld.long 0x2FC 24. "MCASP2_ACLKR_WAKEUPENABLE,- DISABLE" "MCASP2_ACLKR_WAKEUPENABLE_0,MCASP2_ACLKR_WAKEUPENABLE_1" newline bitfld.long 0x2FC 19. "MCASP2_ACLKR_SLEWCONTROL,- FAST_SLEW" "MCASP2_ACLKR_SLEWCONTROL_0,MCASP2_ACLKR_SLEWCONTROL_1" newline bitfld.long 0x2FC 18. "MCASP2_ACLKR_INPUTENABLE,- DISABLE" "MCASP2_ACLKR_INPUTENABLE_0,MCASP2_ACLKR_INPUTENABLE_1" newline bitfld.long 0x2FC 17. "MCASP2_ACLKR_PULLTYPESELECT,- PULL_DOWN" "MCASP2_ACLKR_PULLTYPESELECT_0,MCASP2_ACLKR_PULLTYPESELECT_1" newline bitfld.long 0x2FC 16. "MCASP2_ACLKR_PULLUDENABLE,- ENABLE" "MCASP2_ACLKR_PULLUDENABLE_0,MCASP2_ACLKR_PULLUDENABLE_1" newline bitfld.long 0x2FC 8. "MCASP2_ACLKR_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_ACLKR_MODESELECT_0,MCASP2_ACLKR_MODESELECT_1" newline bitfld.long 0x2FC 4.--7. "MCASP2_ACLKR_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2FC 0.--3. "MCASP2_ACLKR_MUXMODE,- MCASP2_ACLKR" "MCASP2_ACLKR_MUXMODE_0,MCASP2_ACLKR_MUXMODE_1,?,?,?,?,MCASP2_ACLKR_MUXMODE_6,?,MCASP2_ACLKR_MUXMODE_8,?,?,?,?,?,?,MCASP2_ACLKR_MUXMODE_15" line.long 0x300 "CTRL_CORE_PAD_MCASP2_FSR," rbitfld.long 0x300 25. "MCASP2_FSR_WAKEUPEVENT,- NOWAKEUP" "MCASP2_FSR_WAKEUPEVENT_0,MCASP2_FSR_WAKEUPEVENT_1" newline bitfld.long 0x300 24. "MCASP2_FSR_WAKEUPENABLE,- DISABLE" "MCASP2_FSR_WAKEUPENABLE_0,MCASP2_FSR_WAKEUPENABLE_1" newline bitfld.long 0x300 19. "MCASP2_FSR_SLEWCONTROL,- FAST_SLEW" "MCASP2_FSR_SLEWCONTROL_0,MCASP2_FSR_SLEWCONTROL_1" newline bitfld.long 0x300 18. "MCASP2_FSR_INPUTENABLE,- DISABLE" "MCASP2_FSR_INPUTENABLE_0,MCASP2_FSR_INPUTENABLE_1" newline bitfld.long 0x300 17. "MCASP2_FSR_PULLTYPESELECT,- PULL_DOWN" "MCASP2_FSR_PULLTYPESELECT_0,MCASP2_FSR_PULLTYPESELECT_1" newline bitfld.long 0x300 16. "MCASP2_FSR_PULLUDENABLE,- ENABLE" "MCASP2_FSR_PULLUDENABLE_0,MCASP2_FSR_PULLUDENABLE_1" newline bitfld.long 0x300 8. "MCASP2_FSR_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_FSR_MODESELECT_0,MCASP2_FSR_MODESELECT_1" newline bitfld.long 0x300 4.--7. "MCASP2_FSR_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x300 0.--3. "MCASP2_FSR_MUXMODE,- MCASP2_FSR" "MCASP2_FSR_MUXMODE_0,MCASP2_FSR_MUXMODE_1,?,?,?,?,MCASP2_FSR_MUXMODE_6,?,MCASP2_FSR_MUXMODE_8,?,?,?,?,?,?,MCASP2_FSR_MUXMODE_15" line.long 0x304 "CTRL_CORE_PAD_MCASP2_AXR0," rbitfld.long 0x304 25. "MCASP2_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR0_WAKEUPEVENT_0,MCASP2_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x304 24. "MCASP2_AXR0_WAKEUPENABLE,- DISABLE" "MCASP2_AXR0_WAKEUPENABLE_0,MCASP2_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x304 19. "MCASP2_AXR0_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR0_SLEWCONTROL_0,MCASP2_AXR0_SLEWCONTROL_1" newline bitfld.long 0x304 18. "MCASP2_AXR0_INPUTENABLE,- DISABLE" "MCASP2_AXR0_INPUTENABLE_0,MCASP2_AXR0_INPUTENABLE_1" newline bitfld.long 0x304 17. "MCASP2_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR0_PULLTYPESELECT_0,MCASP2_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x304 16. "MCASP2_AXR0_PULLUDENABLE,- ENABLE" "MCASP2_AXR0_PULLUDENABLE_0,MCASP2_AXR0_PULLUDENABLE_1" newline bitfld.long 0x304 8. "MCASP2_AXR0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR0_MODESELECT_0,MCASP2_AXR0_MODESELECT_1" newline bitfld.long 0x304 4.--7. "MCASP2_AXR0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x304 0.--3. "MCASP2_AXR0_MUXMODE,- MCASP2_AXR0" "MCASP2_AXR0_MUXMODE_0,?,?,?,?,?,MCASP2_AXR0_MUXMODE_6,?,MCASP2_AXR0_MUXMODE_8,?,?,?,?,?,?,MCASP2_AXR0_MUXMODE_15" line.long 0x308 "CTRL_CORE_PAD_MCASP2_AXR1," rbitfld.long 0x308 25. "MCASP2_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR1_WAKEUPEVENT_0,MCASP2_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x308 24. "MCASP2_AXR1_WAKEUPENABLE,- DISABLE" "MCASP2_AXR1_WAKEUPENABLE_0,MCASP2_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x308 19. "MCASP2_AXR1_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR1_SLEWCONTROL_0,MCASP2_AXR1_SLEWCONTROL_1" newline bitfld.long 0x308 18. "MCASP2_AXR1_INPUTENABLE,- DISABLE" "MCASP2_AXR1_INPUTENABLE_0,MCASP2_AXR1_INPUTENABLE_1" newline bitfld.long 0x308 17. "MCASP2_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR1_PULLTYPESELECT_0,MCASP2_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x308 16. "MCASP2_AXR1_PULLUDENABLE,- ENABLE" "MCASP2_AXR1_PULLUDENABLE_0,MCASP2_AXR1_PULLUDENABLE_1" newline bitfld.long 0x308 8. "MCASP2_AXR1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR1_MODESELECT_0,MCASP2_AXR1_MODESELECT_1" newline bitfld.long 0x308 4.--7. "MCASP2_AXR1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x308 0.--3. "MCASP2_AXR1_MUXMODE,- MCASP2_AXR1" "MCASP2_AXR1_MUXMODE_0,?,?,?,?,?,MCASP2_AXR1_MUXMODE_6,?,MCASP2_AXR1_MUXMODE_8,?,?,?,?,?,?,MCASP2_AXR1_MUXMODE_15" line.long 0x30C "CTRL_CORE_PAD_MCASP2_AXR2," rbitfld.long 0x30C 25. "MCASP2_AXR2_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR2_WAKEUPEVENT_0,MCASP2_AXR2_WAKEUPEVENT_1" newline bitfld.long 0x30C 24. "MCASP2_AXR2_WAKEUPENABLE,- DISABLE" "MCASP2_AXR2_WAKEUPENABLE_0,MCASP2_AXR2_WAKEUPENABLE_1" newline bitfld.long 0x30C 19. "MCASP2_AXR2_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR2_SLEWCONTROL_0,MCASP2_AXR2_SLEWCONTROL_1" newline bitfld.long 0x30C 18. "MCASP2_AXR2_INPUTENABLE,- DISABLE" "MCASP2_AXR2_INPUTENABLE_0,MCASP2_AXR2_INPUTENABLE_1" newline bitfld.long 0x30C 17. "MCASP2_AXR2_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR2_PULLTYPESELECT_0,MCASP2_AXR2_PULLTYPESELECT_1" newline bitfld.long 0x30C 16. "MCASP2_AXR2_PULLUDENABLE,- ENABLE" "MCASP2_AXR2_PULLUDENABLE_0,MCASP2_AXR2_PULLUDENABLE_1" newline bitfld.long 0x30C 8. "MCASP2_AXR2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR2_MODESELECT_0,MCASP2_AXR2_MODESELECT_1" newline bitfld.long 0x30C 4.--7. "MCASP2_AXR2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30C 0.--3. "MCASP2_AXR2_MUXMODE,- MCASP2_AXR2" "MCASP2_AXR2_MUXMODE_0,MCASP2_AXR2_MUXMODE_1,?,?,?,?,?,MCASP2_AXR2_MUXMODE_7,?,?,?,?,?,?,MCASP2_AXR2_MUXMODE_14,MCASP2_AXR2_MUXMODE_15" line.long 0x310 "CTRL_CORE_PAD_MCASP2_AXR3," rbitfld.long 0x310 25. "MCASP2_AXR3_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR3_WAKEUPEVENT_0,MCASP2_AXR3_WAKEUPEVENT_1" newline bitfld.long 0x310 24. "MCASP2_AXR3_WAKEUPENABLE,- DISABLE" "MCASP2_AXR3_WAKEUPENABLE_0,MCASP2_AXR3_WAKEUPENABLE_1" newline bitfld.long 0x310 19. "MCASP2_AXR3_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR3_SLEWCONTROL_0,MCASP2_AXR3_SLEWCONTROL_1" newline bitfld.long 0x310 18. "MCASP2_AXR3_INPUTENABLE,- DISABLE" "MCASP2_AXR3_INPUTENABLE_0,MCASP2_AXR3_INPUTENABLE_1" newline bitfld.long 0x310 17. "MCASP2_AXR3_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR3_PULLTYPESELECT_0,MCASP2_AXR3_PULLTYPESELECT_1" newline bitfld.long 0x310 16. "MCASP2_AXR3_PULLUDENABLE,- ENABLE" "MCASP2_AXR3_PULLUDENABLE_0,MCASP2_AXR3_PULLUDENABLE_1" newline bitfld.long 0x310 8. "MCASP2_AXR3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR3_MODESELECT_0,MCASP2_AXR3_MODESELECT_1" newline bitfld.long 0x310 4.--7. "MCASP2_AXR3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x310 0.--3. "MCASP2_AXR3_MUXMODE,- MCASP2_AXR3" "MCASP2_AXR3_MUXMODE_0,MCASP2_AXR3_MUXMODE_1,?,?,?,?,?,MCASP2_AXR3_MUXMODE_7,?,?,?,?,?,?,MCASP2_AXR3_MUXMODE_14,MCASP2_AXR3_MUXMODE_15" line.long 0x314 "CTRL_CORE_PAD_MCASP2_AXR4," rbitfld.long 0x314 25. "MCASP2_AXR4_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR4_WAKEUPEVENT_0,MCASP2_AXR4_WAKEUPEVENT_1" newline bitfld.long 0x314 24. "MCASP2_AXR4_WAKEUPENABLE,- DISABLE" "MCASP2_AXR4_WAKEUPENABLE_0,MCASP2_AXR4_WAKEUPENABLE_1" newline bitfld.long 0x314 19. "MCASP2_AXR4_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR4_SLEWCONTROL_0,MCASP2_AXR4_SLEWCONTROL_1" newline bitfld.long 0x314 18. "MCASP2_AXR4_INPUTENABLE,- DISABLE" "MCASP2_AXR4_INPUTENABLE_0,MCASP2_AXR4_INPUTENABLE_1" newline bitfld.long 0x314 17. "MCASP2_AXR4_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR4_PULLTYPESELECT_0,MCASP2_AXR4_PULLTYPESELECT_1" newline bitfld.long 0x314 16. "MCASP2_AXR4_PULLUDENABLE,- ENABLE" "MCASP2_AXR4_PULLUDENABLE_0,MCASP2_AXR4_PULLUDENABLE_1" newline bitfld.long 0x314 8. "MCASP2_AXR4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR4_MODESELECT_0,MCASP2_AXR4_MODESELECT_1" newline bitfld.long 0x314 4.--7. "MCASP2_AXR4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x314 0.--3. "MCASP2_AXR4_MUXMODE,- MCASP2_AXR4" "MCASP2_AXR4_MUXMODE_0,MCASP2_AXR4_MUXMODE_1,?,?,?,?,MCASP2_AXR4_MUXMODE_6,?,MCASP2_AXR4_MUXMODE_8,?,?,?,?,?,MCASP2_AXR4_MUXMODE_14,MCASP2_AXR4_MUXMODE_15" line.long 0x318 "CTRL_CORE_PAD_MCASP2_AXR5," rbitfld.long 0x318 25. "MCASP2_AXR5_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR5_WAKEUPEVENT_0,MCASP2_AXR5_WAKEUPEVENT_1" newline bitfld.long 0x318 24. "MCASP2_AXR5_WAKEUPENABLE,- DISABLE" "MCASP2_AXR5_WAKEUPENABLE_0,MCASP2_AXR5_WAKEUPENABLE_1" newline bitfld.long 0x318 19. "MCASP2_AXR5_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR5_SLEWCONTROL_0,MCASP2_AXR5_SLEWCONTROL_1" newline bitfld.long 0x318 18. "MCASP2_AXR5_INPUTENABLE,- DISABLE" "MCASP2_AXR5_INPUTENABLE_0,MCASP2_AXR5_INPUTENABLE_1" newline bitfld.long 0x318 17. "MCASP2_AXR5_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR5_PULLTYPESELECT_0,MCASP2_AXR5_PULLTYPESELECT_1" newline bitfld.long 0x318 16. "MCASP2_AXR5_PULLUDENABLE,- ENABLE" "MCASP2_AXR5_PULLUDENABLE_0,MCASP2_AXR5_PULLUDENABLE_1" newline bitfld.long 0x318 8. "MCASP2_AXR5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR5_MODESELECT_0,MCASP2_AXR5_MODESELECT_1" newline bitfld.long 0x318 4.--7. "MCASP2_AXR5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x318 0.--3. "MCASP2_AXR5_MUXMODE,- MCASP2_AXR5" "MCASP2_AXR5_MUXMODE_0,MCASP2_AXR5_MUXMODE_1,?,?,?,?,MCASP2_AXR5_MUXMODE_6,?,MCASP2_AXR5_MUXMODE_8,?,?,?,?,?,MCASP2_AXR5_MUXMODE_14,MCASP2_AXR5_MUXMODE_15" line.long 0x31C "CTRL_CORE_PAD_MCASP2_AXR6," rbitfld.long 0x31C 25. "MCASP2_AXR6_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR6_WAKEUPEVENT_0,MCASP2_AXR6_WAKEUPEVENT_1" newline bitfld.long 0x31C 24. "MCASP2_AXR6_WAKEUPENABLE,- DISABLE" "MCASP2_AXR6_WAKEUPENABLE_0,MCASP2_AXR6_WAKEUPENABLE_1" newline bitfld.long 0x31C 19. "MCASP2_AXR6_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR6_SLEWCONTROL_0,MCASP2_AXR6_SLEWCONTROL_1" newline bitfld.long 0x31C 18. "MCASP2_AXR6_INPUTENABLE,- DISABLE" "MCASP2_AXR6_INPUTENABLE_0,MCASP2_AXR6_INPUTENABLE_1" newline bitfld.long 0x31C 17. "MCASP2_AXR6_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR6_PULLTYPESELECT_0,MCASP2_AXR6_PULLTYPESELECT_1" newline bitfld.long 0x31C 16. "MCASP2_AXR6_PULLUDENABLE,- ENABLE" "MCASP2_AXR6_PULLUDENABLE_0,MCASP2_AXR6_PULLUDENABLE_1" newline bitfld.long 0x31C 8. "MCASP2_AXR6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR6_MODESELECT_0,MCASP2_AXR6_MODESELECT_1" newline bitfld.long 0x31C 4.--7. "MCASP2_AXR6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x31C 0.--3. "MCASP2_AXR6_MUXMODE,- MCASP2_AXR6" "MCASP2_AXR6_MUXMODE_0,MCASP2_AXR6_MUXMODE_1,MCASP2_AXR6_MUXMODE_2,?,?,?,MCASP2_AXR6_MUXMODE_6,?,MCASP2_AXR6_MUXMODE_8,?,?,?,?,?,MCASP2_AXR6_MUXMODE_14,MCASP2_AXR6_MUXMODE_15" line.long 0x320 "CTRL_CORE_PAD_MCASP2_AXR7," rbitfld.long 0x320 25. "MCASP2_AXR7_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR7_WAKEUPEVENT_0,MCASP2_AXR7_WAKEUPEVENT_1" newline bitfld.long 0x320 24. "MCASP2_AXR7_WAKEUPENABLE,- DISABLE" "MCASP2_AXR7_WAKEUPENABLE_0,MCASP2_AXR7_WAKEUPENABLE_1" newline bitfld.long 0x320 19. "MCASP2_AXR7_SLEWCONTROL,- FAST_SLEW" "MCASP2_AXR7_SLEWCONTROL_0,MCASP2_AXR7_SLEWCONTROL_1" newline bitfld.long 0x320 18. "MCASP2_AXR7_INPUTENABLE,- DISABLE" "MCASP2_AXR7_INPUTENABLE_0,MCASP2_AXR7_INPUTENABLE_1" newline bitfld.long 0x320 17. "MCASP2_AXR7_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR7_PULLTYPESELECT_0,MCASP2_AXR7_PULLTYPESELECT_1" newline bitfld.long 0x320 16. "MCASP2_AXR7_PULLUDENABLE,- ENABLE" "MCASP2_AXR7_PULLUDENABLE_0,MCASP2_AXR7_PULLUDENABLE_1" newline bitfld.long 0x320 8. "MCASP2_AXR7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP2_AXR7_MODESELECT_0,MCASP2_AXR7_MODESELECT_1" newline bitfld.long 0x320 4.--7. "MCASP2_AXR7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x320 0.--3. "MCASP2_AXR7_MUXMODE,- MCASP2_AXR7" "MCASP2_AXR7_MUXMODE_0,MCASP2_AXR7_MUXMODE_1,MCASP2_AXR7_MUXMODE_2,?,?,?,MCASP2_AXR7_MUXMODE_6,?,MCASP2_AXR7_MUXMODE_8,?,?,?,?,?,MCASP2_AXR7_MUXMODE_14,MCASP2_AXR7_MUXMODE_15" line.long 0x324 "CTRL_CORE_PAD_MCASP3_ACLKX," rbitfld.long 0x324 25. "MCASP3_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP3_ACLKX_WAKEUPEVENT_0,MCASP3_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x324 24. "MCASP3_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP3_ACLKX_WAKEUPENABLE_0,MCASP3_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x324 19. "MCASP3_ACLKX_SLEWCONTROL,- FAST_SLEW" "MCASP3_ACLKX_SLEWCONTROL_0,MCASP3_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x324 18. "MCASP3_ACLKX_INPUTENABLE,- DISABLE" "MCASP3_ACLKX_INPUTENABLE_0,MCASP3_ACLKX_INPUTENABLE_1" newline bitfld.long 0x324 17. "MCASP3_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP3_ACLKX_PULLTYPESELECT_0,MCASP3_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x324 16. "MCASP3_ACLKX_PULLUDENABLE,- ENABLE" "MCASP3_ACLKX_PULLUDENABLE_0,MCASP3_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x324 8. "MCASP3_ACLKX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP3_ACLKX_MODESELECT_0,MCASP3_ACLKX_MODESELECT_1" newline bitfld.long 0x324 4.--7. "MCASP3_ACLKX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x324 0.--3. "MCASP3_ACLKX_MUXMODE,- MCASP3_ACLKX" "MCASP3_ACLKX_MUXMODE_0,MCASP3_ACLKX_MUXMODE_1,MCASP3_ACLKX_MUXMODE_2,MCASP3_ACLKX_MUXMODE_3,?,?,?,MCASP3_ACLKX_MUXMODE_7,?,?,?,?,?,?,MCASP3_ACLKX_MUXMODE_14,MCASP3_ACLKX_MUXMODE_15" line.long 0x328 "CTRL_CORE_PAD_MCASP3_FSX," rbitfld.long 0x328 25. "MCASP3_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP3_FSX_WAKEUPEVENT_0,MCASP3_FSX_WAKEUPEVENT_1" newline bitfld.long 0x328 24. "MCASP3_FSX_WAKEUPENABLE,- DISABLE" "MCASP3_FSX_WAKEUPENABLE_0,MCASP3_FSX_WAKEUPENABLE_1" newline bitfld.long 0x328 19. "MCASP3_FSX_SLEWCONTROL,- FAST_SLEW" "MCASP3_FSX_SLEWCONTROL_0,MCASP3_FSX_SLEWCONTROL_1" newline bitfld.long 0x328 18. "MCASP3_FSX_INPUTENABLE,- DISABLE" "MCASP3_FSX_INPUTENABLE_0,MCASP3_FSX_INPUTENABLE_1" newline bitfld.long 0x328 17. "MCASP3_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP3_FSX_PULLTYPESELECT_0,MCASP3_FSX_PULLTYPESELECT_1" newline bitfld.long 0x328 16. "MCASP3_FSX_PULLUDENABLE,- ENABLE" "MCASP3_FSX_PULLUDENABLE_0,MCASP3_FSX_PULLUDENABLE_1" newline bitfld.long 0x328 8. "MCASP3_FSX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP3_FSX_MODESELECT_0,MCASP3_FSX_MODESELECT_1" newline bitfld.long 0x328 4.--7. "MCASP3_FSX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x328 0.--3. "MCASP3_FSX_MUXMODE,- MCASP3_FSX" "MCASP3_FSX_MUXMODE_0,MCASP3_FSX_MUXMODE_1,MCASP3_FSX_MUXMODE_2,MCASP3_FSX_MUXMODE_3,?,?,?,MCASP3_FSX_MUXMODE_7,?,?,?,?,?,?,MCASP3_FSX_MUXMODE_14,MCASP3_FSX_MUXMODE_15" line.long 0x32C "CTRL_CORE_PAD_MCASP3_AXR0," rbitfld.long 0x32C 25. "MCASP3_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP3_AXR0_WAKEUPEVENT_0,MCASP3_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x32C 24. "MCASP3_AXR0_WAKEUPENABLE,- DISABLE" "MCASP3_AXR0_WAKEUPENABLE_0,MCASP3_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x32C 19. "MCASP3_AXR0_SLEWCONTROL,- FAST_SLEW" "MCASP3_AXR0_SLEWCONTROL_0,MCASP3_AXR0_SLEWCONTROL_1" newline bitfld.long 0x32C 18. "MCASP3_AXR0_INPUTENABLE,- DISABLE" "MCASP3_AXR0_INPUTENABLE_0,MCASP3_AXR0_INPUTENABLE_1" newline bitfld.long 0x32C 17. "MCASP3_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP3_AXR0_PULLTYPESELECT_0,MCASP3_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x32C 16. "MCASP3_AXR0_PULLUDENABLE,- ENABLE" "MCASP3_AXR0_PULLUDENABLE_0,MCASP3_AXR0_PULLUDENABLE_1" newline bitfld.long 0x32C 8. "MCASP3_AXR0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP3_AXR0_MODESELECT_0,MCASP3_AXR0_MODESELECT_1" newline bitfld.long 0x32C 4.--7. "MCASP3_AXR0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x32C 0.--3. "MCASP3_AXR0_MUXMODE,- MCASP3_AXR0" "MCASP3_AXR0_MUXMODE_0,?,MCASP3_AXR0_MUXMODE_2,MCASP3_AXR0_MUXMODE_3,MCASP3_AXR0_MUXMODE_4,?,?,MCASP3_AXR0_MUXMODE_7,?,?,?,?,?,?,?,MCASP3_AXR0_MUXMODE_15" line.long 0x330 "CTRL_CORE_PAD_MCASP3_AXR1," rbitfld.long 0x330 25. "MCASP3_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP3_AXR1_WAKEUPEVENT_0,MCASP3_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x330 24. "MCASP3_AXR1_WAKEUPENABLE,- DISABLE" "MCASP3_AXR1_WAKEUPENABLE_0,MCASP3_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x330 19. "MCASP3_AXR1_SLEWCONTROL,- FAST_SLEW" "MCASP3_AXR1_SLEWCONTROL_0,MCASP3_AXR1_SLEWCONTROL_1" newline bitfld.long 0x330 18. "MCASP3_AXR1_INPUTENABLE,- DISABLE" "MCASP3_AXR1_INPUTENABLE_0,MCASP3_AXR1_INPUTENABLE_1" newline bitfld.long 0x330 17. "MCASP3_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP3_AXR1_PULLTYPESELECT_0,MCASP3_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x330 16. "MCASP3_AXR1_PULLUDENABLE,- ENABLE" "MCASP3_AXR1_PULLUDENABLE_0,MCASP3_AXR1_PULLUDENABLE_1" newline bitfld.long 0x330 8. "MCASP3_AXR1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP3_AXR1_MODESELECT_0,MCASP3_AXR1_MODESELECT_1" newline bitfld.long 0x330 4.--7. "MCASP3_AXR1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x330 0.--3. "MCASP3_AXR1_MUXMODE,- MCASP3_AXR1" "MCASP3_AXR1_MUXMODE_0,?,MCASP3_AXR1_MUXMODE_2,MCASP3_AXR1_MUXMODE_3,MCASP3_AXR1_MUXMODE_4,?,?,MCASP3_AXR1_MUXMODE_7,?,MCASP3_AXR1_MUXMODE_9,?,?,?,?,?,MCASP3_AXR1_MUXMODE_15" line.long 0x334 "CTRL_CORE_PAD_MCASP4_ACLKX," rbitfld.long 0x334 25. "MCASP4_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP4_ACLKX_WAKEUPEVENT_0,MCASP4_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x334 24. "MCASP4_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP4_ACLKX_WAKEUPENABLE_0,MCASP4_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x334 19. "MCASP4_ACLKX_SLEWCONTROL,- FAST_SLEW" "MCASP4_ACLKX_SLEWCONTROL_0,MCASP4_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x334 18. "MCASP4_ACLKX_INPUTENABLE,- DISABLE" "MCASP4_ACLKX_INPUTENABLE_0,MCASP4_ACLKX_INPUTENABLE_1" newline bitfld.long 0x334 17. "MCASP4_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP4_ACLKX_PULLTYPESELECT_0,MCASP4_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x334 16. "MCASP4_ACLKX_PULLUDENABLE,- ENABLE" "MCASP4_ACLKX_PULLUDENABLE_0,MCASP4_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x334 8. "MCASP4_ACLKX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP4_ACLKX_MODESELECT_0,MCASP4_ACLKX_MODESELECT_1" newline bitfld.long 0x334 4.--7. "MCASP4_ACLKX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x334 0.--3. "MCASP4_ACLKX_MUXMODE,- MCASP4_ACLKX" "MCASP4_ACLKX_MUXMODE_0,MCASP4_ACLKX_MUXMODE_1,MCASP4_ACLKX_MUXMODE_2,MCASP4_ACLKX_MUXMODE_3,MCASP4_ACLKX_MUXMODE_4,?,MCASP4_ACLKX_MUXMODE_6,?,MCASP4_ACLKX_MUXMODE_8,MCASP4_ACLKX_MUXMODE_9,?,?,?,?,?,MCASP4_ACLKX_MUXMODE_15" line.long 0x338 "CTRL_CORE_PAD_MCASP4_FSX," rbitfld.long 0x338 25. "MCASP4_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP4_FSX_WAKEUPEVENT_0,MCASP4_FSX_WAKEUPEVENT_1" newline bitfld.long 0x338 24. "MCASP4_FSX_WAKEUPENABLE,- DISABLE" "MCASP4_FSX_WAKEUPENABLE_0,MCASP4_FSX_WAKEUPENABLE_1" newline bitfld.long 0x338 19. "MCASP4_FSX_SLEWCONTROL,- FAST_SLEW" "MCASP4_FSX_SLEWCONTROL_0,MCASP4_FSX_SLEWCONTROL_1" newline bitfld.long 0x338 18. "MCASP4_FSX_INPUTENABLE,- DISABLE" "MCASP4_FSX_INPUTENABLE_0,MCASP4_FSX_INPUTENABLE_1" newline bitfld.long 0x338 17. "MCASP4_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP4_FSX_PULLTYPESELECT_0,MCASP4_FSX_PULLTYPESELECT_1" newline bitfld.long 0x338 16. "MCASP4_FSX_PULLUDENABLE,- ENABLE" "MCASP4_FSX_PULLUDENABLE_0,MCASP4_FSX_PULLUDENABLE_1" newline bitfld.long 0x338 8. "MCASP4_FSX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP4_FSX_MODESELECT_0,MCASP4_FSX_MODESELECT_1" newline bitfld.long 0x338 4.--7. "MCASP4_FSX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x338 0.--3. "MCASP4_FSX_MUXMODE,- MCASP4_FSX" "MCASP4_FSX_MUXMODE_0,MCASP4_FSX_MUXMODE_1,MCASP4_FSX_MUXMODE_2,MCASP4_FSX_MUXMODE_3,MCASP4_FSX_MUXMODE_4,?,MCASP4_FSX_MUXMODE_6,?,MCASP4_FSX_MUXMODE_8,MCASP4_FSX_MUXMODE_9,?,?,?,?,?,MCASP4_FSX_MUXMODE_15" line.long 0x33C "CTRL_CORE_PAD_MCASP4_AXR0," rbitfld.long 0x33C 25. "MCASP4_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP4_AXR0_WAKEUPEVENT_0,MCASP4_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x33C 24. "MCASP4_AXR0_WAKEUPENABLE,- DISABLE" "MCASP4_AXR0_WAKEUPENABLE_0,MCASP4_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x33C 19. "MCASP4_AXR0_SLEWCONTROL,- FAST_SLEW" "MCASP4_AXR0_SLEWCONTROL_0,MCASP4_AXR0_SLEWCONTROL_1" newline bitfld.long 0x33C 18. "MCASP4_AXR0_INPUTENABLE,- DISABLE" "MCASP4_AXR0_INPUTENABLE_0,MCASP4_AXR0_INPUTENABLE_1" newline bitfld.long 0x33C 17. "MCASP4_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP4_AXR0_PULLTYPESELECT_0,MCASP4_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x33C 16. "MCASP4_AXR0_PULLUDENABLE,- ENABLE" "MCASP4_AXR0_PULLUDENABLE_0,MCASP4_AXR0_PULLUDENABLE_1" newline bitfld.long 0x33C 8. "MCASP4_AXR0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP4_AXR0_MODESELECT_0,MCASP4_AXR0_MODESELECT_1" newline bitfld.long 0x33C 4.--7. "MCASP4_AXR0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x33C 0.--3. "MCASP4_AXR0_MUXMODE,- MCASP4_AXR0" "MCASP4_AXR0_MUXMODE_0,?,MCASP4_AXR0_MUXMODE_2,MCASP4_AXR0_MUXMODE_3,MCASP4_AXR0_MUXMODE_4,?,MCASP4_AXR0_MUXMODE_6,?,MCASP4_AXR0_MUXMODE_8,MCASP4_AXR0_MUXMODE_9,?,?,?,?,?,MCASP4_AXR0_MUXMODE_15" line.long 0x340 "CTRL_CORE_PAD_MCASP4_AXR1," rbitfld.long 0x340 25. "MCASP4_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP4_AXR1_WAKEUPEVENT_0,MCASP4_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x340 24. "MCASP4_AXR1_WAKEUPENABLE,- DISABLE" "MCASP4_AXR1_WAKEUPENABLE_0,MCASP4_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x340 19. "MCASP4_AXR1_SLEWCONTROL,- FAST_SLEW" "MCASP4_AXR1_SLEWCONTROL_0,MCASP4_AXR1_SLEWCONTROL_1" newline bitfld.long 0x340 18. "MCASP4_AXR1_INPUTENABLE,- DISABLE" "MCASP4_AXR1_INPUTENABLE_0,MCASP4_AXR1_INPUTENABLE_1" newline bitfld.long 0x340 17. "MCASP4_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP4_AXR1_PULLTYPESELECT_0,MCASP4_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x340 16. "MCASP4_AXR1_PULLUDENABLE,- ENABLE" "MCASP4_AXR1_PULLUDENABLE_0,MCASP4_AXR1_PULLUDENABLE_1" newline bitfld.long 0x340 8. "MCASP4_AXR1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP4_AXR1_MODESELECT_0,MCASP4_AXR1_MODESELECT_1" newline bitfld.long 0x340 4.--7. "MCASP4_AXR1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x340 0.--3. "MCASP4_AXR1_MUXMODE,- MCASP4_AXR1" "MCASP4_AXR1_MUXMODE_0,?,MCASP4_AXR1_MUXMODE_2,MCASP4_AXR1_MUXMODE_3,MCASP4_AXR1_MUXMODE_4,?,MCASP4_AXR1_MUXMODE_6,?,MCASP4_AXR1_MUXMODE_8,MCASP4_AXR1_MUXMODE_9,?,?,?,?,?,MCASP4_AXR1_MUXMODE_15" line.long 0x344 "CTRL_CORE_PAD_MCASP5_ACLKX," rbitfld.long 0x344 25. "MCASP5_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP5_ACLKX_WAKEUPEVENT_0,MCASP5_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x344 24. "MCASP5_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP5_ACLKX_WAKEUPENABLE_0,MCASP5_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x344 19. "MCASP5_ACLKX_SLEWCONTROL,- FAST_SLEW" "MCASP5_ACLKX_SLEWCONTROL_0,MCASP5_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x344 18. "MCASP5_ACLKX_INPUTENABLE,- DISABLE" "MCASP5_ACLKX_INPUTENABLE_0,MCASP5_ACLKX_INPUTENABLE_1" newline bitfld.long 0x344 17. "MCASP5_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP5_ACLKX_PULLTYPESELECT_0,MCASP5_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x344 16. "MCASP5_ACLKX_PULLUDENABLE,- ENABLE" "MCASP5_ACLKX_PULLUDENABLE_0,MCASP5_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x344 8. "MCASP5_ACLKX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP5_ACLKX_MODESELECT_0,MCASP5_ACLKX_MODESELECT_1" newline bitfld.long 0x344 4.--7. "MCASP5_ACLKX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x344 0.--3. "MCASP5_ACLKX_MUXMODE,- MCASP5_ACLKX" "MCASP5_ACLKX_MUXMODE_0,MCASP5_ACLKX_MUXMODE_1,MCASP5_ACLKX_MUXMODE_2,MCASP5_ACLKX_MUXMODE_3,MCASP5_ACLKX_MUXMODE_4,?,MCASP5_ACLKX_MUXMODE_6,?,MCASP5_ACLKX_MUXMODE_8,MCASP5_ACLKX_MUXMODE_9,?,?,?,?,?,MCASP5_ACLKX_MUXMODE_15" line.long 0x348 "CTRL_CORE_PAD_MCASP5_FSX," rbitfld.long 0x348 25. "MCASP5_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP5_FSX_WAKEUPEVENT_0,MCASP5_FSX_WAKEUPEVENT_1" newline bitfld.long 0x348 24. "MCASP5_FSX_WAKEUPENABLE,- DISABLE" "MCASP5_FSX_WAKEUPENABLE_0,MCASP5_FSX_WAKEUPENABLE_1" newline bitfld.long 0x348 19. "MCASP5_FSX_SLEWCONTROL,- FAST_SLEW" "MCASP5_FSX_SLEWCONTROL_0,MCASP5_FSX_SLEWCONTROL_1" newline bitfld.long 0x348 18. "MCASP5_FSX_INPUTENABLE,- DISABLE" "MCASP5_FSX_INPUTENABLE_0,MCASP5_FSX_INPUTENABLE_1" newline bitfld.long 0x348 17. "MCASP5_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP5_FSX_PULLTYPESELECT_0,MCASP5_FSX_PULLTYPESELECT_1" newline bitfld.long 0x348 16. "MCASP5_FSX_PULLUDENABLE,- ENABLE" "MCASP5_FSX_PULLUDENABLE_0,MCASP5_FSX_PULLUDENABLE_1" newline bitfld.long 0x348 8. "MCASP5_FSX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP5_FSX_MODESELECT_0,MCASP5_FSX_MODESELECT_1" newline bitfld.long 0x348 4.--7. "MCASP5_FSX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x348 0.--3. "MCASP5_FSX_MUXMODE,- MCASP5_FSX" "MCASP5_FSX_MUXMODE_0,MCASP5_FSX_MUXMODE_1,MCASP5_FSX_MUXMODE_2,MCASP5_FSX_MUXMODE_3,MCASP5_FSX_MUXMODE_4,?,MCASP5_FSX_MUXMODE_6,?,MCASP5_FSX_MUXMODE_8,MCASP5_FSX_MUXMODE_9,?,?,?,?,?,MCASP5_FSX_MUXMODE_15" line.long 0x34C "CTRL_CORE_PAD_MCASP5_AXR0," rbitfld.long 0x34C 25. "MCASP5_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP5_AXR0_WAKEUPEVENT_0,MCASP5_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x34C 24. "MCASP5_AXR0_WAKEUPENABLE,- DISABLE" "MCASP5_AXR0_WAKEUPENABLE_0,MCASP5_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x34C 19. "MCASP5_AXR0_SLEWCONTROL,- FAST_SLEW" "MCASP5_AXR0_SLEWCONTROL_0,MCASP5_AXR0_SLEWCONTROL_1" newline bitfld.long 0x34C 18. "MCASP5_AXR0_INPUTENABLE,- DISABLE" "MCASP5_AXR0_INPUTENABLE_0,MCASP5_AXR0_INPUTENABLE_1" newline bitfld.long 0x34C 17. "MCASP5_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP5_AXR0_PULLTYPESELECT_0,MCASP5_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x34C 16. "MCASP5_AXR0_PULLUDENABLE,- ENABLE" "MCASP5_AXR0_PULLUDENABLE_0,MCASP5_AXR0_PULLUDENABLE_1" newline bitfld.long 0x34C 8. "MCASP5_AXR0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP5_AXR0_MODESELECT_0,MCASP5_AXR0_MODESELECT_1" newline bitfld.long 0x34C 4.--7. "MCASP5_AXR0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34C 0.--3. "MCASP5_AXR0_MUXMODE,- MCASP5_AXR0" "MCASP5_AXR0_MUXMODE_0,?,MCASP5_AXR0_MUXMODE_2,MCASP5_AXR0_MUXMODE_3,MCASP5_AXR0_MUXMODE_4,?,MCASP5_AXR0_MUXMODE_6,?,MCASP5_AXR0_MUXMODE_8,MCASP5_AXR0_MUXMODE_9,?,?,?,?,?,MCASP5_AXR0_MUXMODE_15" line.long 0x350 "CTRL_CORE_PAD_MCASP5_AXR1," rbitfld.long 0x350 25. "MCASP5_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP5_AXR1_WAKEUPEVENT_0,MCASP5_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x350 24. "MCASP5_AXR1_WAKEUPENABLE,- DISABLE" "MCASP5_AXR1_WAKEUPENABLE_0,MCASP5_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x350 19. "MCASP5_AXR1_SLEWCONTROL,- FAST_SLEW" "MCASP5_AXR1_SLEWCONTROL_0,MCASP5_AXR1_SLEWCONTROL_1" newline bitfld.long 0x350 18. "MCASP5_AXR1_INPUTENABLE,- DISABLE" "MCASP5_AXR1_INPUTENABLE_0,MCASP5_AXR1_INPUTENABLE_1" newline bitfld.long 0x350 17. "MCASP5_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP5_AXR1_PULLTYPESELECT_0,MCASP5_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x350 16. "MCASP5_AXR1_PULLUDENABLE,- ENABLE" "MCASP5_AXR1_PULLUDENABLE_0,MCASP5_AXR1_PULLUDENABLE_1" newline bitfld.long 0x350 8. "MCASP5_AXR1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MCASP5_AXR1_MODESELECT_0,MCASP5_AXR1_MODESELECT_1" newline bitfld.long 0x350 4.--7. "MCASP5_AXR1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x350 0.--3. "MCASP5_AXR1_MUXMODE,- MCASP5_AXR1" "MCASP5_AXR1_MUXMODE_0,?,MCASP5_AXR1_MUXMODE_2,MCASP5_AXR1_MUXMODE_3,MCASP5_AXR1_MUXMODE_4,?,MCASP5_AXR1_MUXMODE_6,?,MCASP5_AXR1_MUXMODE_8,MCASP5_AXR1_MUXMODE_9,?,?,?,?,?,MCASP5_AXR1_MUXMODE_15" line.long 0x354 "CTRL_CORE_PAD_MMC1_CLK," rbitfld.long 0x354 25. "MMC1_CLK_WAKEUPEVENT,- NOWAKEUP" "MMC1_CLK_WAKEUPEVENT_0,MMC1_CLK_WAKEUPEVENT_1" newline bitfld.long 0x354 24. "MMC1_CLK_WAKEUPENABLE,- DISABLE" "MMC1_CLK_WAKEUPENABLE_0,MMC1_CLK_WAKEUPENABLE_1" newline bitfld.long 0x354 18. "MMC1_CLK_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x354 17. "MMC1_CLK_PULLTYPESELECT,- PULL_DOWN" "MMC1_CLK_PULLTYPESELECT_0,MMC1_CLK_PULLTYPESELECT_1" newline bitfld.long 0x354 16. "MMC1_CLK_PULLUDENABLE,- ENABLE" "MMC1_CLK_PULLUDENABLE_0,MMC1_CLK_PULLUDENABLE_1" newline bitfld.long 0x354 8. "MMC1_CLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_CLK_MODESELECT_0,MMC1_CLK_MODESELECT_1" newline bitfld.long 0x354 4.--7. "MMC1_CLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x354 0.--3. "MMC1_CLK_MUXMODE,- MMC1_CLK" "MMC1_CLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_CLK_MUXMODE_14,MMC1_CLK_MUXMODE_15" line.long 0x358 "CTRL_CORE_PAD_MMC1_CMD," rbitfld.long 0x358 25. "MMC1_CMD_WAKEUPEVENT,- NOWAKEUP" "MMC1_CMD_WAKEUPEVENT_0,MMC1_CMD_WAKEUPEVENT_1" newline bitfld.long 0x358 24. "MMC1_CMD_WAKEUPENABLE,- DISABLE" "MMC1_CMD_WAKEUPENABLE_0,MMC1_CMD_WAKEUPENABLE_1" newline bitfld.long 0x358 18. "MMC1_CMD_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x358 17. "MMC1_CMD_PULLTYPESELECT,- PULL_DOWN" "MMC1_CMD_PULLTYPESELECT_0,MMC1_CMD_PULLTYPESELECT_1" newline bitfld.long 0x358 16. "MMC1_CMD_PULLUDENABLE,- ENABLE" "MMC1_CMD_PULLUDENABLE_0,MMC1_CMD_PULLUDENABLE_1" newline bitfld.long 0x358 8. "MMC1_CMD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_CMD_MODESELECT_0,MMC1_CMD_MODESELECT_1" newline bitfld.long 0x358 4.--7. "MMC1_CMD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x358 0.--3. "MMC1_CMD_MUXMODE,- MMC1_CMD" "MMC1_CMD_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_CMD_MUXMODE_14,MMC1_CMD_MUXMODE_15" line.long 0x35C "CTRL_CORE_PAD_MMC1_DAT0," rbitfld.long 0x35C 25. "MMC1_DAT0_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT0_WAKEUPEVENT_0,MMC1_DAT0_WAKEUPEVENT_1" newline bitfld.long 0x35C 24. "MMC1_DAT0_WAKEUPENABLE,- DISABLE" "MMC1_DAT0_WAKEUPENABLE_0,MMC1_DAT0_WAKEUPENABLE_1" newline bitfld.long 0x35C 18. "MMC1_DAT0_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x35C 17. "MMC1_DAT0_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT0_PULLTYPESELECT_0,MMC1_DAT0_PULLTYPESELECT_1" newline bitfld.long 0x35C 16. "MMC1_DAT0_PULLUDENABLE,- ENABLE" "MMC1_DAT0_PULLUDENABLE_0,MMC1_DAT0_PULLUDENABLE_1" newline bitfld.long 0x35C 8. "MMC1_DAT0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_DAT0_MODESELECT_0,MMC1_DAT0_MODESELECT_1" newline bitfld.long 0x35C 4.--7. "MMC1_DAT0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x35C 0.--3. "MMC1_DAT0_MUXMODE,- MMC1_DAT0" "MMC1_DAT0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT0_MUXMODE_14,MMC1_DAT0_MUXMODE_15" line.long 0x360 "CTRL_CORE_PAD_MMC1_DAT1," rbitfld.long 0x360 25. "MMC1_DAT1_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT1_WAKEUPEVENT_0,MMC1_DAT1_WAKEUPEVENT_1" newline bitfld.long 0x360 24. "MMC1_DAT1_WAKEUPENABLE,- DISABLE" "MMC1_DAT1_WAKEUPENABLE_0,MMC1_DAT1_WAKEUPENABLE_1" newline bitfld.long 0x360 18. "MMC1_DAT1_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x360 17. "MMC1_DAT1_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT1_PULLTYPESELECT_0,MMC1_DAT1_PULLTYPESELECT_1" newline bitfld.long 0x360 16. "MMC1_DAT1_PULLUDENABLE,- ENABLE" "MMC1_DAT1_PULLUDENABLE_0,MMC1_DAT1_PULLUDENABLE_1" newline bitfld.long 0x360 8. "MMC1_DAT1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_DAT1_MODESELECT_0,MMC1_DAT1_MODESELECT_1" newline bitfld.long 0x360 4.--7. "MMC1_DAT1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x360 0.--3. "MMC1_DAT1_MUXMODE,- MMC1_DAT1" "MMC1_DAT1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT1_MUXMODE_14,MMC1_DAT1_MUXMODE_15" line.long 0x364 "CTRL_CORE_PAD_MMC1_DAT2," rbitfld.long 0x364 25. "MMC1_DAT2_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT2_WAKEUPEVENT_0,MMC1_DAT2_WAKEUPEVENT_1" newline bitfld.long 0x364 24. "MMC1_DAT2_WAKEUPENABLE,- DISABLE" "MMC1_DAT2_WAKEUPENABLE_0,MMC1_DAT2_WAKEUPENABLE_1" newline bitfld.long 0x364 18. "MMC1_DAT2_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x364 17. "MMC1_DAT2_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT2_PULLTYPESELECT_0,MMC1_DAT2_PULLTYPESELECT_1" newline bitfld.long 0x364 16. "MMC1_DAT2_PULLUDENABLE,- ENABLE" "MMC1_DAT2_PULLUDENABLE_0,MMC1_DAT2_PULLUDENABLE_1" newline bitfld.long 0x364 8. "MMC1_DAT2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_DAT2_MODESELECT_0,MMC1_DAT2_MODESELECT_1" newline bitfld.long 0x364 4.--7. "MMC1_DAT2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x364 0.--3. "MMC1_DAT2_MUXMODE,- MMC1_DAT2" "MMC1_DAT2_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT2_MUXMODE_14,MMC1_DAT2_MUXMODE_15" line.long 0x368 "CTRL_CORE_PAD_MMC1_DAT3," rbitfld.long 0x368 25. "MMC1_DAT3_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT3_WAKEUPEVENT_0,MMC1_DAT3_WAKEUPEVENT_1" newline bitfld.long 0x368 24. "MMC1_DAT3_WAKEUPENABLE,- DISABLE" "MMC1_DAT3_WAKEUPENABLE_0,MMC1_DAT3_WAKEUPENABLE_1" newline bitfld.long 0x368 18. "MMC1_DAT3_ACTIVE,Controls enabling/disabling of the input buffer" "Input buffer is disabled,Input buffer is enabled" newline bitfld.long 0x368 17. "MMC1_DAT3_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT3_PULLTYPESELECT_0,MMC1_DAT3_PULLTYPESELECT_1" newline bitfld.long 0x368 16. "MMC1_DAT3_PULLUDENABLE,- ENABLE" "MMC1_DAT3_PULLUDENABLE_0,MMC1_DAT3_PULLUDENABLE_1" newline bitfld.long 0x368 8. "MMC1_DAT3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_DAT3_MODESELECT_0,MMC1_DAT3_MODESELECT_1" newline bitfld.long 0x368 4.--7. "MMC1_DAT3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x368 0.--3. "MMC1_DAT3_MUXMODE,- MMC1_DAT3" "MMC1_DAT3_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT3_MUXMODE_14,MMC1_DAT3_MUXMODE_15" line.long 0x36C "CTRL_CORE_PAD_MMC1_SDCD," rbitfld.long 0x36C 25. "MMC1_SDCD_WAKEUPEVENT,- NOWAKEUP" "MMC1_SDCD_WAKEUPEVENT_0,MMC1_SDCD_WAKEUPEVENT_1" newline bitfld.long 0x36C 24. "MMC1_SDCD_WAKEUPENABLE,- DISABLE" "MMC1_SDCD_WAKEUPENABLE_0,MMC1_SDCD_WAKEUPENABLE_1" newline bitfld.long 0x36C 19. "MMC1_SDCD_SLEWCONTROL,- FAST_SLEW" "MMC1_SDCD_SLEWCONTROL_0,MMC1_SDCD_SLEWCONTROL_1" newline bitfld.long 0x36C 18. "MMC1_SDCD_INPUTENABLE,- DISABLE" "MMC1_SDCD_INPUTENABLE_0,MMC1_SDCD_INPUTENABLE_1" newline bitfld.long 0x36C 17. "MMC1_SDCD_PULLTYPESELECT,- PULL_DOWN" "MMC1_SDCD_PULLTYPESELECT_0,MMC1_SDCD_PULLTYPESELECT_1" newline bitfld.long 0x36C 16. "MMC1_SDCD_PULLUDENABLE,- ENABLE" "MMC1_SDCD_PULLUDENABLE_0,MMC1_SDCD_PULLUDENABLE_1" newline bitfld.long 0x36C 8. "MMC1_SDCD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_SDCD_MODESELECT_0,MMC1_SDCD_MODESELECT_1" newline bitfld.long 0x36C 4.--7. "MMC1_SDCD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x36C 0.--3. "MMC1_SDCD_MUXMODE,- MMC1_SDCD" "MMC1_SDCD_MUXMODE_0,?,?,MMC1_SDCD_MUXMODE_3,MMC1_SDCD_MUXMODE_4,?,?,?,?,?,?,?,?,?,MMC1_SDCD_MUXMODE_14,MMC1_SDCD_MUXMODE_15" line.long 0x370 "CTRL_CORE_PAD_MMC1_SDWP," rbitfld.long 0x370 25. "MMC1_SDWP_WAKEUPEVENT,- NOWAKEUP" "MMC1_SDWP_WAKEUPEVENT_0,MMC1_SDWP_WAKEUPEVENT_1" newline bitfld.long 0x370 24. "MMC1_SDWP_WAKEUPENABLE,- DISABLE" "MMC1_SDWP_WAKEUPENABLE_0,MMC1_SDWP_WAKEUPENABLE_1" newline bitfld.long 0x370 19. "MMC1_SDWP_SLEWCONTROL,- FAST_SLEW" "MMC1_SDWP_SLEWCONTROL_0,MMC1_SDWP_SLEWCONTROL_1" newline bitfld.long 0x370 18. "MMC1_SDWP_INPUTENABLE,- DISABLE" "MMC1_SDWP_INPUTENABLE_0,MMC1_SDWP_INPUTENABLE_1" newline bitfld.long 0x370 17. "MMC1_SDWP_PULLTYPESELECT,- PULL_DOWN" "MMC1_SDWP_PULLTYPESELECT_0,MMC1_SDWP_PULLTYPESELECT_1" newline bitfld.long 0x370 16. "MMC1_SDWP_PULLUDENABLE,- ENABLE" "MMC1_SDWP_PULLUDENABLE_0,MMC1_SDWP_PULLUDENABLE_1" newline bitfld.long 0x370 8. "MMC1_SDWP_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC1_SDWP_MODESELECT_0,MMC1_SDWP_MODESELECT_1" newline bitfld.long 0x370 4.--7. "MMC1_SDWP_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x370 0.--3. "MMC1_SDWP_MUXMODE,- MMC1_SDWP" "MMC1_SDWP_MUXMODE_0,?,?,MMC1_SDWP_MUXMODE_3,MMC1_SDWP_MUXMODE_4,?,?,?,?,?,?,?,?,?,MMC1_SDWP_MUXMODE_14,MMC1_SDWP_MUXMODE_15" line.long 0x374 "CTRL_CORE_PAD_GPIO6_10," rbitfld.long 0x374 25. "GPIO6_10_WAKEUPEVENT,- NOWAKEUP" "GPIO6_10_WAKEUPEVENT_0,GPIO6_10_WAKEUPEVENT_1" newline bitfld.long 0x374 24. "GPIO6_10_WAKEUPENABLE,- DISABLE" "GPIO6_10_WAKEUPENABLE_0,GPIO6_10_WAKEUPENABLE_1" newline bitfld.long 0x374 19. "GPIO6_10_SLEWCONTROL,- FAST_SLEW" "GPIO6_10_SLEWCONTROL_0,GPIO6_10_SLEWCONTROL_1" newline bitfld.long 0x374 18. "GPIO6_10_INPUTENABLE,- DISABLE" "GPIO6_10_INPUTENABLE_0,GPIO6_10_INPUTENABLE_1" newline bitfld.long 0x374 17. "GPIO6_10_PULLTYPESELECT,- PULL_DOWN" "GPIO6_10_PULLTYPESELECT_0,GPIO6_10_PULLTYPESELECT_1" newline bitfld.long 0x374 16. "GPIO6_10_PULLUDENABLE,- ENABLE" "GPIO6_10_PULLUDENABLE_0,GPIO6_10_PULLUDENABLE_1" newline bitfld.long 0x374 8. "GPIO6_10_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPIO6_10_MODESELECT_0,GPIO6_10_MODESELECT_1" newline bitfld.long 0x374 4.--7. "GPIO6_10_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x374 0.--3. "GPIO6_10_MUXMODE,- GPIO6_10" "GPIO6_10_MUXMODE_0,GPIO6_10_MUXMODE_1,GPIO6_10_MUXMODE_2,GPIO6_10_MUXMODE_3,GPIO6_10_MUXMODE_4,?,?,?,?,GPIO6_10_MUXMODE_9,GPIO6_10_MUXMODE_10,?,?,?,GPIO6_10_MUXMODE_14,GPIO6_10_MUXMODE_15" line.long 0x378 "CTRL_CORE_PAD_GPIO6_11," rbitfld.long 0x378 25. "GPIO6_11_WAKEUPEVENT,- NOWAKEUP" "GPIO6_11_WAKEUPEVENT_0,GPIO6_11_WAKEUPEVENT_1" newline bitfld.long 0x378 24. "GPIO6_11_WAKEUPENABLE,- DISABLE" "GPIO6_11_WAKEUPENABLE_0,GPIO6_11_WAKEUPENABLE_1" newline bitfld.long 0x378 19. "GPIO6_11_SLEWCONTROL,- FAST_SLEW" "GPIO6_11_SLEWCONTROL_0,GPIO6_11_SLEWCONTROL_1" newline bitfld.long 0x378 18. "GPIO6_11_INPUTENABLE,- DISABLE" "GPIO6_11_INPUTENABLE_0,GPIO6_11_INPUTENABLE_1" newline bitfld.long 0x378 17. "GPIO6_11_PULLTYPESELECT,- PULL_DOWN" "GPIO6_11_PULLTYPESELECT_0,GPIO6_11_PULLTYPESELECT_1" newline bitfld.long 0x378 16. "GPIO6_11_PULLUDENABLE,- ENABLE" "GPIO6_11_PULLUDENABLE_0,GPIO6_11_PULLUDENABLE_1" newline bitfld.long 0x378 8. "GPIO6_11_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "GPIO6_11_MODESELECT_0,GPIO6_11_MODESELECT_1" newline bitfld.long 0x378 4.--7. "GPIO6_11_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x378 0.--3. "GPIO6_11_MUXMODE,- GPIO6_11" "GPIO6_11_MUXMODE_0,GPIO6_11_MUXMODE_1,GPIO6_11_MUXMODE_2,GPIO6_11_MUXMODE_3,GPIO6_11_MUXMODE_4,?,?,?,?,GPIO6_11_MUXMODE_9,GPIO6_11_MUXMODE_10,?,?,?,GPIO6_11_MUXMODE_14,GPIO6_11_MUXMODE_15" line.long 0x37C "CTRL_CORE_PAD_MMC3_CLK," rbitfld.long 0x37C 25. "MMC3_CLK_WAKEUPEVENT,- NOWAKEUP" "MMC3_CLK_WAKEUPEVENT_0,MMC3_CLK_WAKEUPEVENT_1" newline bitfld.long 0x37C 24. "MMC3_CLK_WAKEUPENABLE,- DISABLE" "MMC3_CLK_WAKEUPENABLE_0,MMC3_CLK_WAKEUPENABLE_1" newline bitfld.long 0x37C 19. "MMC3_CLK_SLEWCONTROL,- FAST_SLEW" "MMC3_CLK_SLEWCONTROL_0,MMC3_CLK_SLEWCONTROL_1" newline bitfld.long 0x37C 18. "MMC3_CLK_INPUTENABLE,- DISABLE" "MMC3_CLK_INPUTENABLE_0,MMC3_CLK_INPUTENABLE_1" newline bitfld.long 0x37C 17. "MMC3_CLK_PULLTYPESELECT,- PULL_DOWN" "MMC3_CLK_PULLTYPESELECT_0,MMC3_CLK_PULLTYPESELECT_1" newline bitfld.long 0x37C 16. "MMC3_CLK_PULLUDENABLE,- ENABLE" "MMC3_CLK_PULLUDENABLE_0,MMC3_CLK_PULLUDENABLE_1" newline bitfld.long 0x37C 8. "MMC3_CLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_CLK_MODESELECT_0,MMC3_CLK_MODESELECT_1" newline bitfld.long 0x37C 4.--7. "MMC3_CLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x37C 0.--3. "MMC3_CLK_MUXMODE,- MMC3_CLK" "MMC3_CLK_MUXMODE_0,?,?,MMC3_CLK_MUXMODE_3,MMC3_CLK_MUXMODE_4,?,?,?,?,MMC3_CLK_MUXMODE_9,MMC3_CLK_MUXMODE_10,?,?,?,MMC3_CLK_MUXMODE_14,MMC3_CLK_MUXMODE_15" line.long 0x380 "CTRL_CORE_PAD_MMC3_CMD," rbitfld.long 0x380 25. "MMC3_CMD_WAKEUPEVENT,- NOWAKEUP" "MMC3_CMD_WAKEUPEVENT_0,MMC3_CMD_WAKEUPEVENT_1" newline bitfld.long 0x380 24. "MMC3_CMD_WAKEUPENABLE,- DISABLE" "MMC3_CMD_WAKEUPENABLE_0,MMC3_CMD_WAKEUPENABLE_1" newline bitfld.long 0x380 19. "MMC3_CMD_SLEWCONTROL,- FAST_SLEW" "MMC3_CMD_SLEWCONTROL_0,MMC3_CMD_SLEWCONTROL_1" newline bitfld.long 0x380 18. "MMC3_CMD_INPUTENABLE,- DISABLE" "MMC3_CMD_INPUTENABLE_0,MMC3_CMD_INPUTENABLE_1" newline bitfld.long 0x380 17. "MMC3_CMD_PULLTYPESELECT,- PULL_DOWN" "MMC3_CMD_PULLTYPESELECT_0,MMC3_CMD_PULLTYPESELECT_1" newline bitfld.long 0x380 16. "MMC3_CMD_PULLUDENABLE,- ENABLE" "MMC3_CMD_PULLUDENABLE_0,MMC3_CMD_PULLUDENABLE_1" newline bitfld.long 0x380 8. "MMC3_CMD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_CMD_MODESELECT_0,MMC3_CMD_MODESELECT_1" newline bitfld.long 0x380 4.--7. "MMC3_CMD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x380 0.--3. "MMC3_CMD_MUXMODE,- MMC3_CMD" "MMC3_CMD_MUXMODE_0,MMC3_CMD_MUXMODE_1,?,MMC3_CMD_MUXMODE_3,MMC3_CMD_MUXMODE_4,?,?,?,?,MMC3_CMD_MUXMODE_9,MMC3_CMD_MUXMODE_10,?,?,?,MMC3_CMD_MUXMODE_14,MMC3_CMD_MUXMODE_15" line.long 0x384 "CTRL_CORE_PAD_MMC3_DAT0," rbitfld.long 0x384 25. "MMC3_DAT0_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT0_WAKEUPEVENT_0,MMC3_DAT0_WAKEUPEVENT_1" newline bitfld.long 0x384 24. "MMC3_DAT0_WAKEUPENABLE,- DISABLE" "MMC3_DAT0_WAKEUPENABLE_0,MMC3_DAT0_WAKEUPENABLE_1" newline bitfld.long 0x384 19. "MMC3_DAT0_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT0_SLEWCONTROL_0,MMC3_DAT0_SLEWCONTROL_1" newline bitfld.long 0x384 18. "MMC3_DAT0_INPUTENABLE,- DISABLE" "MMC3_DAT0_INPUTENABLE_0,MMC3_DAT0_INPUTENABLE_1" newline bitfld.long 0x384 17. "MMC3_DAT0_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT0_PULLTYPESELECT_0,MMC3_DAT0_PULLTYPESELECT_1" newline bitfld.long 0x384 16. "MMC3_DAT0_PULLUDENABLE,- ENABLE" "MMC3_DAT0_PULLUDENABLE_0,MMC3_DAT0_PULLUDENABLE_1" newline bitfld.long 0x384 8. "MMC3_DAT0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT0_MODESELECT_0,MMC3_DAT0_MODESELECT_1" newline bitfld.long 0x384 4.--7. "MMC3_DAT0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x384 0.--3. "MMC3_DAT0_MUXMODE,- MMC3_DAT0" "MMC3_DAT0_MUXMODE_0,MMC3_DAT0_MUXMODE_1,MMC3_DAT0_MUXMODE_2,MMC3_DAT0_MUXMODE_3,MMC3_DAT0_MUXMODE_4,?,?,?,?,MMC3_DAT0_MUXMODE_9,MMC3_DAT0_MUXMODE_10,?,?,?,MMC3_DAT0_MUXMODE_14,MMC3_DAT0_MUXMODE_15" line.long 0x388 "CTRL_CORE_PAD_MMC3_DAT1," rbitfld.long 0x388 25. "MMC3_DAT1_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT1_WAKEUPEVENT_0,MMC3_DAT1_WAKEUPEVENT_1" newline bitfld.long 0x388 24. "MMC3_DAT1_WAKEUPENABLE,- DISABLE" "MMC3_DAT1_WAKEUPENABLE_0,MMC3_DAT1_WAKEUPENABLE_1" newline bitfld.long 0x388 19. "MMC3_DAT1_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT1_SLEWCONTROL_0,MMC3_DAT1_SLEWCONTROL_1" newline bitfld.long 0x388 18. "MMC3_DAT1_INPUTENABLE,- DISABLE" "MMC3_DAT1_INPUTENABLE_0,MMC3_DAT1_INPUTENABLE_1" newline bitfld.long 0x388 17. "MMC3_DAT1_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT1_PULLTYPESELECT_0,MMC3_DAT1_PULLTYPESELECT_1" newline bitfld.long 0x388 16. "MMC3_DAT1_PULLUDENABLE,- ENABLE" "MMC3_DAT1_PULLUDENABLE_0,MMC3_DAT1_PULLUDENABLE_1" newline bitfld.long 0x388 8. "MMC3_DAT1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT1_MODESELECT_0,MMC3_DAT1_MODESELECT_1" newline bitfld.long 0x388 4.--7. "MMC3_DAT1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x388 0.--3. "MMC3_DAT1_MUXMODE,- MMC3_DAT1" "MMC3_DAT1_MUXMODE_0,MMC3_DAT1_MUXMODE_1,MMC3_DAT1_MUXMODE_2,MMC3_DAT1_MUXMODE_3,MMC3_DAT1_MUXMODE_4,?,?,?,?,MMC3_DAT1_MUXMODE_9,MMC3_DAT1_MUXMODE_10,?,?,?,MMC3_DAT1_MUXMODE_14,MMC3_DAT1_MUXMODE_15" line.long 0x38C "CTRL_CORE_PAD_MMC3_DAT2," rbitfld.long 0x38C 25. "MMC3_DAT2_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT2_WAKEUPEVENT_0,MMC3_DAT2_WAKEUPEVENT_1" newline bitfld.long 0x38C 24. "MMC3_DAT2_WAKEUPENABLE,- DISABLE" "MMC3_DAT2_WAKEUPENABLE_0,MMC3_DAT2_WAKEUPENABLE_1" newline bitfld.long 0x38C 19. "MMC3_DAT2_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT2_SLEWCONTROL_0,MMC3_DAT2_SLEWCONTROL_1" newline bitfld.long 0x38C 18. "MMC3_DAT2_INPUTENABLE,- DISABLE" "MMC3_DAT2_INPUTENABLE_0,MMC3_DAT2_INPUTENABLE_1" newline bitfld.long 0x38C 17. "MMC3_DAT2_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT2_PULLTYPESELECT_0,MMC3_DAT2_PULLTYPESELECT_1" newline bitfld.long 0x38C 16. "MMC3_DAT2_PULLUDENABLE,- ENABLE" "MMC3_DAT2_PULLUDENABLE_0,MMC3_DAT2_PULLUDENABLE_1" newline bitfld.long 0x38C 8. "MMC3_DAT2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT2_MODESELECT_0,MMC3_DAT2_MODESELECT_1" newline bitfld.long 0x38C 4.--7. "MMC3_DAT2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38C 0.--3. "MMC3_DAT2_MUXMODE,- MMC3_DAT2" "MMC3_DAT2_MUXMODE_0,MMC3_DAT2_MUXMODE_1,MMC3_DAT2_MUXMODE_2,MMC3_DAT2_MUXMODE_3,MMC3_DAT2_MUXMODE_4,?,?,?,?,MMC3_DAT2_MUXMODE_9,MMC3_DAT2_MUXMODE_10,?,?,?,MMC3_DAT2_MUXMODE_14,MMC3_DAT2_MUXMODE_15" line.long 0x390 "CTRL_CORE_PAD_MMC3_DAT3," rbitfld.long 0x390 25. "MMC3_DAT3_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT3_WAKEUPEVENT_0,MMC3_DAT3_WAKEUPEVENT_1" newline bitfld.long 0x390 24. "MMC3_DAT3_WAKEUPENABLE,- DISABLE" "MMC3_DAT3_WAKEUPENABLE_0,MMC3_DAT3_WAKEUPENABLE_1" newline bitfld.long 0x390 19. "MMC3_DAT3_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT3_SLEWCONTROL_0,MMC3_DAT3_SLEWCONTROL_1" newline bitfld.long 0x390 18. "MMC3_DAT3_INPUTENABLE,- DISABLE" "MMC3_DAT3_INPUTENABLE_0,MMC3_DAT3_INPUTENABLE_1" newline bitfld.long 0x390 17. "MMC3_DAT3_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT3_PULLTYPESELECT_0,MMC3_DAT3_PULLTYPESELECT_1" newline bitfld.long 0x390 16. "MMC3_DAT3_PULLUDENABLE,- ENABLE" "MMC3_DAT3_PULLUDENABLE_0,MMC3_DAT3_PULLUDENABLE_1" newline bitfld.long 0x390 8. "MMC3_DAT3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT3_MODESELECT_0,MMC3_DAT3_MODESELECT_1" newline bitfld.long 0x390 4.--7. "MMC3_DAT3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x390 0.--3. "MMC3_DAT3_MUXMODE,- MMC3_DAT3" "MMC3_DAT3_MUXMODE_0,MMC3_DAT3_MUXMODE_1,MMC3_DAT3_MUXMODE_2,MMC3_DAT3_MUXMODE_3,MMC3_DAT3_MUXMODE_4,?,?,?,?,MMC3_DAT3_MUXMODE_9,MMC3_DAT3_MUXMODE_10,?,?,?,MMC3_DAT3_MUXMODE_14,MMC3_DAT3_MUXMODE_15" line.long 0x394 "CTRL_CORE_PAD_MMC3_DAT4," rbitfld.long 0x394 25. "MMC3_DAT4_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT4_WAKEUPEVENT_0,MMC3_DAT4_WAKEUPEVENT_1" newline bitfld.long 0x394 24. "MMC3_DAT4_WAKEUPENABLE,- DISABLE" "MMC3_DAT4_WAKEUPENABLE_0,MMC3_DAT4_WAKEUPENABLE_1" newline bitfld.long 0x394 19. "MMC3_DAT4_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT4_SLEWCONTROL_0,MMC3_DAT4_SLEWCONTROL_1" newline bitfld.long 0x394 18. "MMC3_DAT4_INPUTENABLE,- DISABLE" "MMC3_DAT4_INPUTENABLE_0,MMC3_DAT4_INPUTENABLE_1" newline bitfld.long 0x394 17. "MMC3_DAT4_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT4_PULLTYPESELECT_0,MMC3_DAT4_PULLTYPESELECT_1" newline bitfld.long 0x394 16. "MMC3_DAT4_PULLUDENABLE,- ENABLE" "MMC3_DAT4_PULLUDENABLE_0,MMC3_DAT4_PULLUDENABLE_1" newline bitfld.long 0x394 8. "MMC3_DAT4_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT4_MODESELECT_0,MMC3_DAT4_MODESELECT_1" newline bitfld.long 0x394 4.--7. "MMC3_DAT4_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x394 0.--3. "MMC3_DAT4_MUXMODE,- MMC3_DAT4" "MMC3_DAT4_MUXMODE_0,MMC3_DAT4_MUXMODE_1,MMC3_DAT4_MUXMODE_2,MMC3_DAT4_MUXMODE_3,MMC3_DAT4_MUXMODE_4,?,?,?,?,MMC3_DAT4_MUXMODE_9,MMC3_DAT4_MUXMODE_10,?,?,?,MMC3_DAT4_MUXMODE_14,MMC3_DAT4_MUXMODE_15" line.long 0x398 "CTRL_CORE_PAD_MMC3_DAT5," rbitfld.long 0x398 25. "MMC3_DAT5_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT5_WAKEUPEVENT_0,MMC3_DAT5_WAKEUPEVENT_1" newline bitfld.long 0x398 24. "MMC3_DAT5_WAKEUPENABLE,- DISABLE" "MMC3_DAT5_WAKEUPENABLE_0,MMC3_DAT5_WAKEUPENABLE_1" newline bitfld.long 0x398 19. "MMC3_DAT5_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT5_SLEWCONTROL_0,MMC3_DAT5_SLEWCONTROL_1" newline bitfld.long 0x398 18. "MMC3_DAT5_INPUTENABLE,- DISABLE" "MMC3_DAT5_INPUTENABLE_0,MMC3_DAT5_INPUTENABLE_1" newline bitfld.long 0x398 17. "MMC3_DAT5_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT5_PULLTYPESELECT_0,MMC3_DAT5_PULLTYPESELECT_1" newline bitfld.long 0x398 16. "MMC3_DAT5_PULLUDENABLE,- ENABLE" "MMC3_DAT5_PULLUDENABLE_0,MMC3_DAT5_PULLUDENABLE_1" newline bitfld.long 0x398 8. "MMC3_DAT5_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT5_MODESELECT_0,MMC3_DAT5_MODESELECT_1" newline bitfld.long 0x398 4.--7. "MMC3_DAT5_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x398 0.--3. "MMC3_DAT5_MUXMODE,- MMC3_DAT5" "MMC3_DAT5_MUXMODE_0,MMC3_DAT5_MUXMODE_1,MMC3_DAT5_MUXMODE_2,MMC3_DAT5_MUXMODE_3,MMC3_DAT5_MUXMODE_4,?,?,?,?,MMC3_DAT5_MUXMODE_9,MMC3_DAT5_MUXMODE_10,?,?,?,MMC3_DAT5_MUXMODE_14,MMC3_DAT5_MUXMODE_15" line.long 0x39C "CTRL_CORE_PAD_MMC3_DAT6," rbitfld.long 0x39C 25. "MMC3_DAT6_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT6_WAKEUPEVENT_0,MMC3_DAT6_WAKEUPEVENT_1" newline bitfld.long 0x39C 24. "MMC3_DAT6_WAKEUPENABLE,- DISABLE" "MMC3_DAT6_WAKEUPENABLE_0,MMC3_DAT6_WAKEUPENABLE_1" newline bitfld.long 0x39C 19. "MMC3_DAT6_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT6_SLEWCONTROL_0,MMC3_DAT6_SLEWCONTROL_1" newline bitfld.long 0x39C 18. "MMC3_DAT6_INPUTENABLE,- DISABLE" "MMC3_DAT6_INPUTENABLE_0,MMC3_DAT6_INPUTENABLE_1" newline bitfld.long 0x39C 17. "MMC3_DAT6_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT6_PULLTYPESELECT_0,MMC3_DAT6_PULLTYPESELECT_1" newline bitfld.long 0x39C 16. "MMC3_DAT6_PULLUDENABLE,- ENABLE" "MMC3_DAT6_PULLUDENABLE_0,MMC3_DAT6_PULLUDENABLE_1" newline bitfld.long 0x39C 8. "MMC3_DAT6_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT6_MODESELECT_0,MMC3_DAT6_MODESELECT_1" newline bitfld.long 0x39C 4.--7. "MMC3_DAT6_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x39C 0.--3. "MMC3_DAT6_MUXMODE,- MMC3_DAT6" "MMC3_DAT6_MUXMODE_0,MMC3_DAT6_MUXMODE_1,MMC3_DAT6_MUXMODE_2,MMC3_DAT6_MUXMODE_3,MMC3_DAT6_MUXMODE_4,?,?,?,?,MMC3_DAT6_MUXMODE_9,MMC3_DAT6_MUXMODE_10,?,?,?,MMC3_DAT6_MUXMODE_14,MMC3_DAT6_MUXMODE_15" line.long 0x3A0 "CTRL_CORE_PAD_MMC3_DAT7," rbitfld.long 0x3A0 25. "MMC3_DAT7_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT7_WAKEUPEVENT_0,MMC3_DAT7_WAKEUPEVENT_1" newline bitfld.long 0x3A0 24. "MMC3_DAT7_WAKEUPENABLE,- DISABLE" "MMC3_DAT7_WAKEUPENABLE_0,MMC3_DAT7_WAKEUPENABLE_1" newline bitfld.long 0x3A0 19. "MMC3_DAT7_SLEWCONTROL,- FAST_SLEW" "MMC3_DAT7_SLEWCONTROL_0,MMC3_DAT7_SLEWCONTROL_1" newline bitfld.long 0x3A0 18. "MMC3_DAT7_INPUTENABLE,- DISABLE" "MMC3_DAT7_INPUTENABLE_0,MMC3_DAT7_INPUTENABLE_1" newline bitfld.long 0x3A0 17. "MMC3_DAT7_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT7_PULLTYPESELECT_0,MMC3_DAT7_PULLTYPESELECT_1" newline bitfld.long 0x3A0 16. "MMC3_DAT7_PULLUDENABLE,- ENABLE" "MMC3_DAT7_PULLUDENABLE_0,MMC3_DAT7_PULLUDENABLE_1" newline bitfld.long 0x3A0 8. "MMC3_DAT7_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "MMC3_DAT7_MODESELECT_0,MMC3_DAT7_MODESELECT_1" newline bitfld.long 0x3A0 4.--7. "MMC3_DAT7_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A0 0.--3. "MMC3_DAT7_MUXMODE,- MMC3_DAT7" "MMC3_DAT7_MUXMODE_0,MMC3_DAT7_MUXMODE_1,MMC3_DAT7_MUXMODE_2,MMC3_DAT7_MUXMODE_3,MMC3_DAT7_MUXMODE_4,?,?,?,?,MMC3_DAT7_MUXMODE_9,MMC3_DAT7_MUXMODE_10,?,?,?,MMC3_DAT7_MUXMODE_14,MMC3_DAT7_MUXMODE_15" line.long 0x3A4 "CTRL_CORE_PAD_SPI1_SCLK," rbitfld.long 0x3A4 25. "SPI1_SCLK_WAKEUPEVENT,- NOWAKEUP" "SPI1_SCLK_WAKEUPEVENT_0,SPI1_SCLK_WAKEUPEVENT_1" newline bitfld.long 0x3A4 24. "SPI1_SCLK_WAKEUPENABLE,- DISABLE" "SPI1_SCLK_WAKEUPENABLE_0,SPI1_SCLK_WAKEUPENABLE_1" newline bitfld.long 0x3A4 19. "SPI1_SCLK_SLEWCONTROL,- FAST_SLEW" "SPI1_SCLK_SLEWCONTROL_0,SPI1_SCLK_SLEWCONTROL_1" newline bitfld.long 0x3A4 18. "SPI1_SCLK_INPUTENABLE,- DISABLE" "SPI1_SCLK_INPUTENABLE_0,SPI1_SCLK_INPUTENABLE_1" newline bitfld.long 0x3A4 17. "SPI1_SCLK_PULLTYPESELECT,- PULL_DOWN" "SPI1_SCLK_PULLTYPESELECT_0,SPI1_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x3A4 16. "SPI1_SCLK_PULLUDENABLE,- ENABLE" "SPI1_SCLK_PULLUDENABLE_0,SPI1_SCLK_PULLUDENABLE_1" newline bitfld.long 0x3A4 8. "SPI1_SCLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_SCLK_MODESELECT_0,SPI1_SCLK_MODESELECT_1" newline bitfld.long 0x3A4 4.--7. "SPI1_SCLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A4 0.--3. "SPI1_SCLK_MUXMODE,- SPI1_SCLK" "SPI1_SCLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_SCLK_MUXMODE_14,SPI1_SCLK_MUXMODE_15" line.long 0x3A8 "CTRL_CORE_PAD_SPI1_D1," rbitfld.long 0x3A8 25. "SPI1_D1_WAKEUPEVENT,- NOWAKEUP" "SPI1_D1_WAKEUPEVENT_0,SPI1_D1_WAKEUPEVENT_1" newline bitfld.long 0x3A8 24. "SPI1_D1_WAKEUPENABLE,- DISABLE" "SPI1_D1_WAKEUPENABLE_0,SPI1_D1_WAKEUPENABLE_1" newline bitfld.long 0x3A8 19. "SPI1_D1_SLEWCONTROL,- FAST_SLEW" "SPI1_D1_SLEWCONTROL_0,SPI1_D1_SLEWCONTROL_1" newline bitfld.long 0x3A8 18. "SPI1_D1_INPUTENABLE,- DISABLE" "SPI1_D1_INPUTENABLE_0,SPI1_D1_INPUTENABLE_1" newline bitfld.long 0x3A8 17. "SPI1_D1_PULLTYPESELECT,- PULL_DOWN" "SPI1_D1_PULLTYPESELECT_0,SPI1_D1_PULLTYPESELECT_1" newline bitfld.long 0x3A8 16. "SPI1_D1_PULLUDENABLE,- ENABLE" "SPI1_D1_PULLUDENABLE_0,SPI1_D1_PULLUDENABLE_1" newline bitfld.long 0x3A8 8. "SPI1_D1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_D1_MODESELECT_0,SPI1_D1_MODESELECT_1" newline bitfld.long 0x3A8 4.--7. "SPI1_D1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A8 0.--3. "SPI1_D1_MUXMODE,- SPI1_D1" "SPI1_D1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D1_MUXMODE_14,SPI1_D1_MUXMODE_15" line.long 0x3AC "CTRL_CORE_PAD_SPI1_D0," rbitfld.long 0x3AC 25. "SPI1_D0_WAKEUPEVENT,- NOWAKEUP" "SPI1_D0_WAKEUPEVENT_0,SPI1_D0_WAKEUPEVENT_1" newline bitfld.long 0x3AC 24. "SPI1_D0_WAKEUPENABLE,- DISABLE" "SPI1_D0_WAKEUPENABLE_0,SPI1_D0_WAKEUPENABLE_1" newline bitfld.long 0x3AC 19. "SPI1_D0_SLEWCONTROL,- FAST_SLEW" "SPI1_D0_SLEWCONTROL_0,SPI1_D0_SLEWCONTROL_1" newline bitfld.long 0x3AC 18. "SPI1_D0_INPUTENABLE,- DISABLE" "SPI1_D0_INPUTENABLE_0,SPI1_D0_INPUTENABLE_1" newline bitfld.long 0x3AC 17. "SPI1_D0_PULLTYPESELECT,- PULL_DOWN" "SPI1_D0_PULLTYPESELECT_0,SPI1_D0_PULLTYPESELECT_1" newline bitfld.long 0x3AC 16. "SPI1_D0_PULLUDENABLE,- ENABLE" "SPI1_D0_PULLUDENABLE_0,SPI1_D0_PULLUDENABLE_1" newline bitfld.long 0x3AC 8. "SPI1_D0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_D0_MODESELECT_0,SPI1_D0_MODESELECT_1" newline bitfld.long 0x3AC 4.--7. "SPI1_D0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3AC 0.--3. "SPI1_D0_MUXMODE,- SPI1_D0" "SPI1_D0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D0_MUXMODE_14,SPI1_D0_MUXMODE_15" line.long 0x3B0 "CTRL_CORE_PAD_SPI1_CS0," rbitfld.long 0x3B0 25. "SPI1_CS0_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS0_WAKEUPEVENT_0,SPI1_CS0_WAKEUPEVENT_1" newline bitfld.long 0x3B0 24. "SPI1_CS0_WAKEUPENABLE,- DISABLE" "SPI1_CS0_WAKEUPENABLE_0,SPI1_CS0_WAKEUPENABLE_1" newline bitfld.long 0x3B0 19. "SPI1_CS0_SLEWCONTROL,- FAST_SLEW" "SPI1_CS0_SLEWCONTROL_0,SPI1_CS0_SLEWCONTROL_1" newline bitfld.long 0x3B0 18. "SPI1_CS0_INPUTENABLE,- DISABLE" "SPI1_CS0_INPUTENABLE_0,SPI1_CS0_INPUTENABLE_1" newline bitfld.long 0x3B0 17. "SPI1_CS0_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS0_PULLTYPESELECT_0,SPI1_CS0_PULLTYPESELECT_1" newline bitfld.long 0x3B0 16. "SPI1_CS0_PULLUDENABLE,- ENABLE" "SPI1_CS0_PULLUDENABLE_0,SPI1_CS0_PULLUDENABLE_1" newline bitfld.long 0x3B0 8. "SPI1_CS0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_CS0_MODESELECT_0,SPI1_CS0_MODESELECT_1" newline bitfld.long 0x3B0 4.--7. "SPI1_CS0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B0 0.--3. "SPI1_CS0_MUXMODE,- SPI1_CS0" "SPI1_CS0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_CS0_MUXMODE_14,SPI1_CS0_MUXMODE_15" line.long 0x3B4 "CTRL_CORE_PAD_SPI1_CS1," rbitfld.long 0x3B4 25. "SPI1_CS1_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS1_WAKEUPEVENT_0,SPI1_CS1_WAKEUPEVENT_1" newline bitfld.long 0x3B4 24. "SPI1_CS1_WAKEUPENABLE,- DISABLE" "SPI1_CS1_WAKEUPENABLE_0,SPI1_CS1_WAKEUPENABLE_1" newline bitfld.long 0x3B4 19. "SPI1_CS1_SLEWCONTROL,- FAST_SLEW" "SPI1_CS1_SLEWCONTROL_0,SPI1_CS1_SLEWCONTROL_1" newline bitfld.long 0x3B4 18. "SPI1_CS1_INPUTENABLE,- DISABLE" "SPI1_CS1_INPUTENABLE_0,SPI1_CS1_INPUTENABLE_1" newline bitfld.long 0x3B4 17. "SPI1_CS1_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS1_PULLTYPESELECT_0,SPI1_CS1_PULLTYPESELECT_1" newline bitfld.long 0x3B4 16. "SPI1_CS1_PULLUDENABLE,- ENABLE" "SPI1_CS1_PULLUDENABLE_0,SPI1_CS1_PULLUDENABLE_1" newline bitfld.long 0x3B4 8. "SPI1_CS1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_CS1_MODESELECT_0,SPI1_CS1_MODESELECT_1" newline bitfld.long 0x3B4 4.--7. "SPI1_CS1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B4 0.--3. "SPI1_CS1_MUXMODE,- SPI1_CS1" "SPI1_CS1_MUXMODE_0,?,SPI1_CS1_MUXMODE_2,SPI1_CS1_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI1_CS1_MUXMODE_14,SPI1_CS1_MUXMODE_15" line.long 0x3B8 "CTRL_CORE_PAD_SPI1_CS2," rbitfld.long 0x3B8 25. "SPI1_CS2_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS2_WAKEUPEVENT_0,SPI1_CS2_WAKEUPEVENT_1" newline bitfld.long 0x3B8 24. "SPI1_CS2_WAKEUPENABLE,- DISABLE" "SPI1_CS2_WAKEUPENABLE_0,SPI1_CS2_WAKEUPENABLE_1" newline bitfld.long 0x3B8 19. "SPI1_CS2_SLEWCONTROL,- FAST_SLEW" "SPI1_CS2_SLEWCONTROL_0,SPI1_CS2_SLEWCONTROL_1" newline bitfld.long 0x3B8 18. "SPI1_CS2_INPUTENABLE,- DISABLE" "SPI1_CS2_INPUTENABLE_0,SPI1_CS2_INPUTENABLE_1" newline bitfld.long 0x3B8 17. "SPI1_CS2_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS2_PULLTYPESELECT_0,SPI1_CS2_PULLTYPESELECT_1" newline bitfld.long 0x3B8 16. "SPI1_CS2_PULLUDENABLE,- ENABLE" "SPI1_CS2_PULLUDENABLE_0,SPI1_CS2_PULLUDENABLE_1" newline bitfld.long 0x3B8 8. "SPI1_CS2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_CS2_MODESELECT_0,SPI1_CS2_MODESELECT_1" newline bitfld.long 0x3B8 4.--7. "SPI1_CS2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B8 0.--3. "SPI1_CS2_MUXMODE,- SPI1_CS2" "SPI1_CS2_MUXMODE_0,SPI1_CS2_MUXMODE_1,SPI1_CS2_MUXMODE_2,SPI1_CS2_MUXMODE_3,SPI1_CS2_MUXMODE_4,SPI1_CS2_MUXMODE_5,SPI1_CS2_MUXMODE_6,?,?,?,?,?,?,?,SPI1_CS2_MUXMODE_14,SPI1_CS2_MUXMODE_15" line.long 0x3BC "CTRL_CORE_PAD_SPI1_CS3," rbitfld.long 0x3BC 25. "SPI1_CS3_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS3_WAKEUPEVENT_0,SPI1_CS3_WAKEUPEVENT_1" newline bitfld.long 0x3BC 24. "SPI1_CS3_WAKEUPENABLE,- DISABLE" "SPI1_CS3_WAKEUPENABLE_0,SPI1_CS3_WAKEUPENABLE_1" newline bitfld.long 0x3BC 19. "SPI1_CS3_SLEWCONTROL,- FAST_SLEW" "SPI1_CS3_SLEWCONTROL_0,SPI1_CS3_SLEWCONTROL_1" newline bitfld.long 0x3BC 18. "SPI1_CS3_INPUTENABLE,- DISABLE" "SPI1_CS3_INPUTENABLE_0,SPI1_CS3_INPUTENABLE_1" newline bitfld.long 0x3BC 17. "SPI1_CS3_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS3_PULLTYPESELECT_0,SPI1_CS3_PULLTYPESELECT_1" newline bitfld.long 0x3BC 16. "SPI1_CS3_PULLUDENABLE,- ENABLE" "SPI1_CS3_PULLUDENABLE_0,SPI1_CS3_PULLUDENABLE_1" newline bitfld.long 0x3BC 8. "SPI1_CS3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI1_CS3_MODESELECT_0,SPI1_CS3_MODESELECT_1" newline bitfld.long 0x3BC 4.--7. "SPI1_CS3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3BC 0.--3. "SPI1_CS3_MUXMODE,- SPI1_CS3" "SPI1_CS3_MUXMODE_0,SPI1_CS3_MUXMODE_1,SPI1_CS3_MUXMODE_2,SPI1_CS3_MUXMODE_3,SPI1_CS3_MUXMODE_4,SPI1_CS3_MUXMODE_5,SPI1_CS3_MUXMODE_6,?,?,?,?,?,?,?,SPI1_CS3_MUXMODE_14,SPI1_CS3_MUXMODE_15" line.long 0x3C0 "CTRL_CORE_PAD_SPI2_SCLK," rbitfld.long 0x3C0 25. "SPI2_SCLK_WAKEUPEVENT,- NOWAKEUP" "SPI2_SCLK_WAKEUPEVENT_0,SPI2_SCLK_WAKEUPEVENT_1" newline bitfld.long 0x3C0 24. "SPI2_SCLK_WAKEUPENABLE,- DISABLE" "SPI2_SCLK_WAKEUPENABLE_0,SPI2_SCLK_WAKEUPENABLE_1" newline bitfld.long 0x3C0 19. "SPI2_SCLK_SLEWCONTROL,- FAST_SLEW" "SPI2_SCLK_SLEWCONTROL_0,SPI2_SCLK_SLEWCONTROL_1" newline bitfld.long 0x3C0 18. "SPI2_SCLK_INPUTENABLE,- DISABLE" "SPI2_SCLK_INPUTENABLE_0,SPI2_SCLK_INPUTENABLE_1" newline bitfld.long 0x3C0 17. "SPI2_SCLK_PULLTYPESELECT,- PULL_DOWN" "SPI2_SCLK_PULLTYPESELECT_0,SPI2_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x3C0 16. "SPI2_SCLK_PULLUDENABLE,- ENABLE" "SPI2_SCLK_PULLUDENABLE_0,SPI2_SCLK_PULLUDENABLE_1" newline bitfld.long 0x3C0 8. "SPI2_SCLK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI2_SCLK_MODESELECT_0,SPI2_SCLK_MODESELECT_1" newline bitfld.long 0x3C0 4.--7. "SPI2_SCLK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C0 0.--3. "SPI2_SCLK_MUXMODE,- SPI2_SCLK" "SPI2_SCLK_MUXMODE_0,SPI2_SCLK_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI2_SCLK_MUXMODE_14,SPI2_SCLK_MUXMODE_15" line.long 0x3C4 "CTRL_CORE_PAD_SPI2_D1," rbitfld.long 0x3C4 25. "SPI2_D1_WAKEUPEVENT,- NOWAKEUP" "SPI2_D1_WAKEUPEVENT_0,SPI2_D1_WAKEUPEVENT_1" newline bitfld.long 0x3C4 24. "SPI2_D1_WAKEUPENABLE,- DISABLE" "SPI2_D1_WAKEUPENABLE_0,SPI2_D1_WAKEUPENABLE_1" newline bitfld.long 0x3C4 19. "SPI2_D1_SLEWCONTROL,- FAST_SLEW" "SPI2_D1_SLEWCONTROL_0,SPI2_D1_SLEWCONTROL_1" newline bitfld.long 0x3C4 18. "SPI2_D1_INPUTENABLE,- DISABLE" "SPI2_D1_INPUTENABLE_0,SPI2_D1_INPUTENABLE_1" newline bitfld.long 0x3C4 17. "SPI2_D1_PULLTYPESELECT,- PULL_DOWN" "SPI2_D1_PULLTYPESELECT_0,SPI2_D1_PULLTYPESELECT_1" newline bitfld.long 0x3C4 16. "SPI2_D1_PULLUDENABLE,- ENABLE" "SPI2_D1_PULLUDENABLE_0,SPI2_D1_PULLUDENABLE_1" newline bitfld.long 0x3C4 8. "SPI2_D1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI2_D1_MODESELECT_0,SPI2_D1_MODESELECT_1" newline bitfld.long 0x3C4 4.--7. "SPI2_D1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C4 0.--3. "SPI2_D1_MUXMODE,- SPI2_D1" "SPI2_D1_MUXMODE_0,SPI2_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI2_D1_MUXMODE_14,SPI2_D1_MUXMODE_15" line.long 0x3C8 "CTRL_CORE_PAD_SPI2_D0," rbitfld.long 0x3C8 25. "SPI2_D0_WAKEUPEVENT,- NOWAKEUP" "SPI2_D0_WAKEUPEVENT_0,SPI2_D0_WAKEUPEVENT_1" newline bitfld.long 0x3C8 24. "SPI2_D0_WAKEUPENABLE,- DISABLE" "SPI2_D0_WAKEUPENABLE_0,SPI2_D0_WAKEUPENABLE_1" newline bitfld.long 0x3C8 19. "SPI2_D0_SLEWCONTROL,- FAST_SLEW" "SPI2_D0_SLEWCONTROL_0,SPI2_D0_SLEWCONTROL_1" newline bitfld.long 0x3C8 18. "SPI2_D0_INPUTENABLE,- DISABLE" "SPI2_D0_INPUTENABLE_0,SPI2_D0_INPUTENABLE_1" newline bitfld.long 0x3C8 17. "SPI2_D0_PULLTYPESELECT,- PULL_DOWN" "SPI2_D0_PULLTYPESELECT_0,SPI2_D0_PULLTYPESELECT_1" newline bitfld.long 0x3C8 16. "SPI2_D0_PULLUDENABLE,- ENABLE" "SPI2_D0_PULLUDENABLE_0,SPI2_D0_PULLUDENABLE_1" newline bitfld.long 0x3C8 8. "SPI2_D0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI2_D0_MODESELECT_0,SPI2_D0_MODESELECT_1" newline bitfld.long 0x3C8 4.--7. "SPI2_D0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C8 0.--3. "SPI2_D0_MUXMODE,- SPI2_D0" "SPI2_D0_MUXMODE_0,SPI2_D0_MUXMODE_1,SPI2_D0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,SPI2_D0_MUXMODE_14,SPI2_D0_MUXMODE_15" line.long 0x3CC "CTRL_CORE_PAD_SPI2_CS0," rbitfld.long 0x3CC 25. "SPI2_CS0_WAKEUPEVENT,- NOWAKEUP" "SPI2_CS0_WAKEUPEVENT_0,SPI2_CS0_WAKEUPEVENT_1" newline bitfld.long 0x3CC 24. "SPI2_CS0_WAKEUPENABLE,- DISABLE" "SPI2_CS0_WAKEUPENABLE_0,SPI2_CS0_WAKEUPENABLE_1" newline bitfld.long 0x3CC 19. "SPI2_CS0_SLEWCONTROL,- FAST_SLEW" "SPI2_CS0_SLEWCONTROL_0,SPI2_CS0_SLEWCONTROL_1" newline bitfld.long 0x3CC 18. "SPI2_CS0_INPUTENABLE,- DISABLE" "SPI2_CS0_INPUTENABLE_0,SPI2_CS0_INPUTENABLE_1" newline bitfld.long 0x3CC 17. "SPI2_CS0_PULLTYPESELECT,- PULL_DOWN" "SPI2_CS0_PULLTYPESELECT_0,SPI2_CS0_PULLTYPESELECT_1" newline bitfld.long 0x3CC 16. "SPI2_CS0_PULLUDENABLE,- ENABLE" "SPI2_CS0_PULLUDENABLE_0,SPI2_CS0_PULLUDENABLE_1" newline bitfld.long 0x3CC 8. "SPI2_CS0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "SPI2_CS0_MODESELECT_0,SPI2_CS0_MODESELECT_1" newline bitfld.long 0x3CC 4.--7. "SPI2_CS0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3CC 0.--3. "SPI2_CS0_MUXMODE,- SPI2_CS0" "SPI2_CS0_MUXMODE_0,SPI2_CS0_MUXMODE_1,SPI2_CS0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,SPI2_CS0_MUXMODE_14,SPI2_CS0_MUXMODE_15" line.long 0x3D0 "CTRL_CORE_PAD_DCAN1_TX," rbitfld.long 0x3D0 25. "DCAN1_TX_WAKEUPEVENT,- NOWAKEUP" "DCAN1_TX_WAKEUPEVENT_0,DCAN1_TX_WAKEUPEVENT_1" newline bitfld.long 0x3D0 24. "DCAN1_TX_WAKEUPENABLE,- DISABLE" "DCAN1_TX_WAKEUPENABLE_0,DCAN1_TX_WAKEUPENABLE_1" newline bitfld.long 0x3D0 19. "DCAN1_TX_SLEWCONTROL,- FAST_SLEW" "DCAN1_TX_SLEWCONTROL_0,DCAN1_TX_SLEWCONTROL_1" newline bitfld.long 0x3D0 18. "DCAN1_TX_INPUTENABLE,- DISABLE" "DCAN1_TX_INPUTENABLE_0,DCAN1_TX_INPUTENABLE_1" newline bitfld.long 0x3D0 17. "DCAN1_TX_PULLTYPESELECT,- PULL_DOWN" "DCAN1_TX_PULLTYPESELECT_0,DCAN1_TX_PULLTYPESELECT_1" newline bitfld.long 0x3D0 16. "DCAN1_TX_PULLUDENABLE,- ENABLE" "DCAN1_TX_PULLUDENABLE_0,DCAN1_TX_PULLUDENABLE_1" newline bitfld.long 0x3D0 8. "DCAN1_TX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "DCAN1_TX_MODESELECT_0,DCAN1_TX_MODESELECT_1" newline bitfld.long 0x3D0 4.--7. "DCAN1_TX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3D0 0.--3. "DCAN1_TX_MUXMODE,- DCAN1_TX" "DCAN1_TX_MUXMODE_0,?,DCAN1_TX_MUXMODE_2,DCAN1_TX_MUXMODE_3,?,?,DCAN1_TX_MUXMODE_6,?,?,?,?,?,?,?,DCAN1_TX_MUXMODE_14,DCAN1_TX_MUXMODE_15" line.long 0x3D4 "CTRL_CORE_PAD_DCAN1_RX," rbitfld.long 0x3D4 25. "DCAN1_RX_WAKEUPEVENT,- NOWAKEUP" "DCAN1_RX_WAKEUPEVENT_0,DCAN1_RX_WAKEUPEVENT_1" newline bitfld.long 0x3D4 24. "DCAN1_RX_WAKEUPENABLE,- DISABLE" "DCAN1_RX_WAKEUPENABLE_0,DCAN1_RX_WAKEUPENABLE_1" newline bitfld.long 0x3D4 19. "DCAN1_RX_SLEWCONTROL,- FAST_SLEW" "DCAN1_RX_SLEWCONTROL_0,DCAN1_RX_SLEWCONTROL_1" newline bitfld.long 0x3D4 18. "DCAN1_RX_INPUTENABLE,- DISABLE" "DCAN1_RX_INPUTENABLE_0,DCAN1_RX_INPUTENABLE_1" newline bitfld.long 0x3D4 17. "DCAN1_RX_PULLTYPESELECT,- PULL_DOWN" "DCAN1_RX_PULLTYPESELECT_0,DCAN1_RX_PULLTYPESELECT_1" newline bitfld.long 0x3D4 16. "DCAN1_RX_PULLUDENABLE,- ENABLE" "DCAN1_RX_PULLUDENABLE_0,DCAN1_RX_PULLUDENABLE_1" newline bitfld.long 0x3D4 8. "DCAN1_RX_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "DCAN1_RX_MODESELECT_0,DCAN1_RX_MODESELECT_1" newline bitfld.long 0x3D4 4.--7. "DCAN1_RX_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3D4 0.--3. "DCAN1_RX_MUXMODE,- DCAN1_RX" "DCAN1_RX_MUXMODE_0,?,DCAN1_RX_MUXMODE_2,DCAN1_RX_MUXMODE_3,DCAN1_RX_MUXMODE_4,?,DCAN1_RX_MUXMODE_6,?,?,?,?,?,?,?,DCAN1_RX_MUXMODE_14,DCAN1_RX_MUXMODE_15" group.long 0x17E0++0x2F line.long 0x00 "CTRL_CORE_PAD_UART1_RXD," rbitfld.long 0x00 25. "UART1_RXD_WAKEUPEVENT,- NOWAKEUP" "UART1_RXD_WAKEUPEVENT_0,UART1_RXD_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "UART1_RXD_WAKEUPENABLE,- DISABLE" "UART1_RXD_WAKEUPENABLE_0,UART1_RXD_WAKEUPENABLE_1" newline bitfld.long 0x00 19. "UART1_RXD_SLEWCONTROL,- FAST_SLEW" "UART1_RXD_SLEWCONTROL_0,UART1_RXD_SLEWCONTROL_1" newline bitfld.long 0x00 18. "UART1_RXD_INPUTENABLE,- DISABLE" "UART1_RXD_INPUTENABLE_0,UART1_RXD_INPUTENABLE_1" newline bitfld.long 0x00 17. "UART1_RXD_PULLTYPESELECT,- PULL_DOWN" "UART1_RXD_PULLTYPESELECT_0,UART1_RXD_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "UART1_RXD_PULLUDENABLE,- ENABLE" "UART1_RXD_PULLUDENABLE_0,UART1_RXD_PULLUDENABLE_1" newline bitfld.long 0x00 8. "UART1_RXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART1_RXD_MODESELECT_0,UART1_RXD_MODESELECT_1" newline bitfld.long 0x00 4.--7. "UART1_RXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "UART1_RXD_MUXMODE,- UART1_RXD" "UART1_RXD_MUXMODE_0,?,?,UART1_RXD_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_RXD_MUXMODE_14,UART1_RXD_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_UART1_TXD," rbitfld.long 0x04 25. "UART1_TXD_WAKEUPEVENT,- NOWAKEUP" "UART1_TXD_WAKEUPEVENT_0,UART1_TXD_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "UART1_TXD_WAKEUPENABLE,- DISABLE" "UART1_TXD_WAKEUPENABLE_0,UART1_TXD_WAKEUPENABLE_1" newline bitfld.long 0x04 19. "UART1_TXD_SLEWCONTROL,- FAST_SLEW" "UART1_TXD_SLEWCONTROL_0,UART1_TXD_SLEWCONTROL_1" newline bitfld.long 0x04 18. "UART1_TXD_INPUTENABLE,- DISABLE" "UART1_TXD_INPUTENABLE_0,UART1_TXD_INPUTENABLE_1" newline bitfld.long 0x04 17. "UART1_TXD_PULLTYPESELECT,- PULL_DOWN" "UART1_TXD_PULLTYPESELECT_0,UART1_TXD_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "UART1_TXD_PULLUDENABLE,- ENABLE" "UART1_TXD_PULLUDENABLE_0,UART1_TXD_PULLUDENABLE_1" newline bitfld.long 0x04 8. "UART1_TXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART1_TXD_MODESELECT_0,UART1_TXD_MODESELECT_1" newline bitfld.long 0x04 4.--7. "UART1_TXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "UART1_TXD_MUXMODE,- UART1_TXD" "UART1_TXD_MUXMODE_0,?,?,UART1_TXD_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_TXD_MUXMODE_14,UART1_TXD_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_UART1_CTSN," rbitfld.long 0x08 25. "UART1_CTSN_WAKEUPEVENT,- NOWAKEUP" "UART1_CTSN_WAKEUPEVENT_0,UART1_CTSN_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "UART1_CTSN_WAKEUPENABLE,- DISABLE" "UART1_CTSN_WAKEUPENABLE_0,UART1_CTSN_WAKEUPENABLE_1" newline bitfld.long 0x08 19. "UART1_CTSN_SLEWCONTROL,- FAST_SLEW" "UART1_CTSN_SLEWCONTROL_0,UART1_CTSN_SLEWCONTROL_1" newline bitfld.long 0x08 18. "UART1_CTSN_INPUTENABLE,- DISABLE" "UART1_CTSN_INPUTENABLE_0,UART1_CTSN_INPUTENABLE_1" newline bitfld.long 0x08 17. "UART1_CTSN_PULLTYPESELECT,- PULL_DOWN" "UART1_CTSN_PULLTYPESELECT_0,UART1_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "UART1_CTSN_PULLUDENABLE,- ENABLE" "UART1_CTSN_PULLUDENABLE_0,UART1_CTSN_PULLUDENABLE_1" newline bitfld.long 0x08 8. "UART1_CTSN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART1_CTSN_MODESELECT_0,UART1_CTSN_MODESELECT_1" newline bitfld.long 0x08 4.--7. "UART1_CTSN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "UART1_CTSN_MUXMODE,- UART1_CTSN" "UART1_CTSN_MUXMODE_0,?,UART1_CTSN_MUXMODE_2,UART1_CTSN_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_CTSN_MUXMODE_14,UART1_CTSN_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_UART1_RTSN," rbitfld.long 0x0C 25. "UART1_RTSN_WAKEUPEVENT,- NOWAKEUP" "UART1_RTSN_WAKEUPEVENT_0,UART1_RTSN_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "UART1_RTSN_WAKEUPENABLE,- DISABLE" "UART1_RTSN_WAKEUPENABLE_0,UART1_RTSN_WAKEUPENABLE_1" newline bitfld.long 0x0C 19. "UART1_RTSN_SLEWCONTROL,- FAST_SLEW" "UART1_RTSN_SLEWCONTROL_0,UART1_RTSN_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "UART1_RTSN_INPUTENABLE,- DISABLE" "UART1_RTSN_INPUTENABLE_0,UART1_RTSN_INPUTENABLE_1" newline bitfld.long 0x0C 17. "UART1_RTSN_PULLTYPESELECT,- PULL_DOWN" "UART1_RTSN_PULLTYPESELECT_0,UART1_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "UART1_RTSN_PULLUDENABLE,- ENABLE" "UART1_RTSN_PULLUDENABLE_0,UART1_RTSN_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "UART1_RTSN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART1_RTSN_MODESELECT_0,UART1_RTSN_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "UART1_RTSN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "UART1_RTSN_MUXMODE,- UART1_RTSN" "UART1_RTSN_MUXMODE_0,?,UART1_RTSN_MUXMODE_2,UART1_RTSN_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_RTSN_MUXMODE_14,UART1_RTSN_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_UART2_RXD," rbitfld.long 0x10 25. "UART2_RXD_WAKEUPEVENT,- NOWAKEUP" "UART2_RXD_WAKEUPEVENT_0,UART2_RXD_WAKEUPEVENT_1" newline bitfld.long 0x10 24. "UART2_RXD_WAKEUPENABLE,- DISABLE" "UART2_RXD_WAKEUPENABLE_0,UART2_RXD_WAKEUPENABLE_1" newline bitfld.long 0x10 19. "UART2_RXD_SLEWCONTROL,- FAST_SLEW" "UART2_RXD_SLEWCONTROL_0,UART2_RXD_SLEWCONTROL_1" newline bitfld.long 0x10 18. "UART2_RXD_INPUTENABLE,- DISABLE" "UART2_RXD_INPUTENABLE_0,UART2_RXD_INPUTENABLE_1" newline bitfld.long 0x10 17. "UART2_RXD_PULLTYPESELECT,- PULL_DOWN" "UART2_RXD_PULLTYPESELECT_0,UART2_RXD_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "UART2_RXD_PULLUDENABLE,- ENABLE" "UART2_RXD_PULLUDENABLE_0,UART2_RXD_PULLUDENABLE_1" newline bitfld.long 0x10 8. "UART2_RXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART2_RXD_MODESELECT_0,UART2_RXD_MODESELECT_1" newline bitfld.long 0x10 4.--7. "UART2_RXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "UART2_RXD_MUXMODE,- UART3_CTSN" "?,UART2_RXD_MUXMODE_1,UART2_RXD_MUXMODE_2,UART2_RXD_MUXMODE_3,UART2_RXD_MUXMODE_4,UART2_RXD_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_RXD_MUXMODE_14,UART2_RXD_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_UART2_TXD," rbitfld.long 0x14 25. "UART2_TXD_WAKEUPEVENT,- NOWAKEUP" "UART2_TXD_WAKEUPEVENT_0,UART2_TXD_WAKEUPEVENT_1" newline bitfld.long 0x14 24. "UART2_TXD_WAKEUPENABLE,- DISABLE" "UART2_TXD_WAKEUPENABLE_0,UART2_TXD_WAKEUPENABLE_1" newline bitfld.long 0x14 19. "UART2_TXD_SLEWCONTROL,- FAST_SLEW" "UART2_TXD_SLEWCONTROL_0,UART2_TXD_SLEWCONTROL_1" newline bitfld.long 0x14 18. "UART2_TXD_INPUTENABLE,- DISABLE" "UART2_TXD_INPUTENABLE_0,UART2_TXD_INPUTENABLE_1" newline bitfld.long 0x14 17. "UART2_TXD_PULLTYPESELECT,- PULL_DOWN" "UART2_TXD_PULLTYPESELECT_0,UART2_TXD_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "UART2_TXD_PULLUDENABLE,- ENABLE" "UART2_TXD_PULLUDENABLE_0,UART2_TXD_PULLUDENABLE_1" newline bitfld.long 0x14 8. "UART2_TXD_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART2_TXD_MODESELECT_0,UART2_TXD_MODESELECT_1" newline bitfld.long 0x14 4.--7. "UART2_TXD_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "UART2_TXD_MUXMODE,- UART2_TXD" "UART2_TXD_MUXMODE_0,UART2_TXD_MUXMODE_1,UART2_TXD_MUXMODE_2,UART2_TXD_MUXMODE_3,UART2_TXD_MUXMODE_4,UART2_TXD_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_TXD_MUXMODE_14,UART2_TXD_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_UART2_CTSN," rbitfld.long 0x18 25. "UART2_CTSN_WAKEUPEVENT,- NOWAKEUP" "UART2_CTSN_WAKEUPEVENT_0,UART2_CTSN_WAKEUPEVENT_1" newline bitfld.long 0x18 24. "UART2_CTSN_WAKEUPENABLE,- DISABLE" "UART2_CTSN_WAKEUPENABLE_0,UART2_CTSN_WAKEUPENABLE_1" newline bitfld.long 0x18 19. "UART2_CTSN_SLEWCONTROL,- FAST_SLEW" "UART2_CTSN_SLEWCONTROL_0,UART2_CTSN_SLEWCONTROL_1" newline bitfld.long 0x18 18. "UART2_CTSN_INPUTENABLE,- DISABLE" "UART2_CTSN_INPUTENABLE_0,UART2_CTSN_INPUTENABLE_1" newline bitfld.long 0x18 17. "UART2_CTSN_PULLTYPESELECT,- PULL_DOWN" "UART2_CTSN_PULLTYPESELECT_0,UART2_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "UART2_CTSN_PULLUDENABLE,- ENABLE" "UART2_CTSN_PULLUDENABLE_0,UART2_CTSN_PULLUDENABLE_1" newline bitfld.long 0x18 8. "UART2_CTSN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART2_CTSN_MODESELECT_0,UART2_CTSN_MODESELECT_1" newline bitfld.long 0x18 4.--7. "UART2_CTSN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. "UART2_CTSN_MUXMODE,- UART2_CTSN" "UART2_CTSN_MUXMODE_0,?,UART2_CTSN_MUXMODE_2,UART2_CTSN_MUXMODE_3,UART2_CTSN_MUXMODE_4,UART2_CTSN_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_CTSN_MUXMODE_14,UART2_CTSN_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_UART2_RTSN," rbitfld.long 0x1C 25. "UART2_RTSN_WAKEUPEVENT,- NOWAKEUP" "UART2_RTSN_WAKEUPEVENT_0,UART2_RTSN_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "UART2_RTSN_WAKEUPENABLE,- DISABLE" "UART2_RTSN_WAKEUPENABLE_0,UART2_RTSN_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "UART2_RTSN_SLEWCONTROL,- FAST_SLEW" "UART2_RTSN_SLEWCONTROL_0,UART2_RTSN_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "UART2_RTSN_INPUTENABLE,- DISABLE" "UART2_RTSN_INPUTENABLE_0,UART2_RTSN_INPUTENABLE_1" newline bitfld.long 0x1C 17. "UART2_RTSN_PULLTYPESELECT,- PULL_DOWN" "UART2_RTSN_PULLTYPESELECT_0,UART2_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "UART2_RTSN_PULLUDENABLE,- ENABLE" "UART2_RTSN_PULLUDENABLE_0,UART2_RTSN_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "UART2_RTSN_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "UART2_RTSN_MODESELECT_0,UART2_RTSN_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "UART2_RTSN_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "UART2_RTSN_MUXMODE,- UART2_RTSN" "UART2_RTSN_MUXMODE_0,UART2_RTSN_MUXMODE_1,UART2_RTSN_MUXMODE_2,UART2_RTSN_MUXMODE_3,UART2_RTSN_MUXMODE_4,UART2_RTSN_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_RTSN_MUXMODE_14,UART2_RTSN_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_I2C1_SDA," rbitfld.long 0x20 25. "I2C1_SDA_WAKEUPEVENT,- NOWAKEUP" "I2C1_SDA_WAKEUPEVENT_0,I2C1_SDA_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "I2C1_SDA_WAKEUPENABLE,- DISABLE" "I2C1_SDA_WAKEUPENABLE_0,I2C1_SDA_WAKEUPENABLE_1" newline bitfld.long 0x20 18. "I2C1_SDA_INPUTENABLE,- DISABLE" "I2C1_SDA_INPUTENABLE_0,I2C1_SDA_INPUTENABLE_1" newline bitfld.long 0x20 17. "I2C1_SDA_PULLTYPESELECT,- PULL_DOWN" "I2C1_SDA_PULLTYPESELECT_0,I2C1_SDA_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "I2C1_SDA_PULLUDENABLE,- ENABLE" "I2C1_SDA_PULLUDENABLE_0,I2C1_SDA_PULLUDENABLE_1" line.long 0x24 "CTRL_CORE_PAD_I2C1_SCL," rbitfld.long 0x24 25. "I2C1_SCL_WAKEUPEVENT,- NOWAKEUP" "I2C1_SCL_WAKEUPEVENT_0,I2C1_SCL_WAKEUPEVENT_1" newline bitfld.long 0x24 24. "I2C1_SCL_WAKEUPENABLE,- DISABLE" "I2C1_SCL_WAKEUPENABLE_0,I2C1_SCL_WAKEUPENABLE_1" newline bitfld.long 0x24 18. "I2C1_SCL_INPUTENABLE,- DISABLE" "I2C1_SCL_INPUTENABLE_0,I2C1_SCL_INPUTENABLE_1" newline bitfld.long 0x24 17. "I2C1_SCL_PULLTYPESELECT,- PULL_DOWN" "I2C1_SCL_PULLTYPESELECT_0,I2C1_SCL_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "I2C1_SCL_PULLUDENABLE,- ENABLE" "I2C1_SCL_PULLUDENABLE_0,I2C1_SCL_PULLUDENABLE_1" line.long 0x28 "CTRL_CORE_PAD_I2C2_SDA," rbitfld.long 0x28 25. "I2C2_SDA_WAKEUPEVENT,- NOWAKEUP" "I2C2_SDA_WAKEUPEVENT_0,I2C2_SDA_WAKEUPEVENT_1" newline bitfld.long 0x28 24. "I2C2_SDA_WAKEUPENABLE,- DISABLE" "I2C2_SDA_WAKEUPENABLE_0,I2C2_SDA_WAKEUPENABLE_1" newline bitfld.long 0x28 18. "I2C2_SDA_INPUTENABLE,- DISABLE" "I2C2_SDA_INPUTENABLE_0,I2C2_SDA_INPUTENABLE_1" newline bitfld.long 0x28 17. "I2C2_SDA_PULLTYPESELECT,- PULL_DOWN" "I2C2_SDA_PULLTYPESELECT_0,I2C2_SDA_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "I2C2_SDA_PULLUDENABLE,- ENABLE" "I2C2_SDA_PULLUDENABLE_0,I2C2_SDA_PULLUDENABLE_1" newline bitfld.long 0x28 0.--3. "I2C2_SDA_MUXMODE,- I2C2_SDA" "I2C2_SDA_MUXMODE_0,I2C2_SDA_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,I2C2_SDA_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_I2C2_SCL," rbitfld.long 0x2C 25. "I2C2_SCL_WAKEUPEVENT,- NOWAKEUP" "I2C2_SCL_WAKEUPEVENT_0,I2C2_SCL_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "I2C2_SCL_WAKEUPENABLE,- DISABLE" "I2C2_SCL_WAKEUPENABLE_0,I2C2_SCL_WAKEUPENABLE_1" newline bitfld.long 0x2C 18. "I2C2_SCL_INPUTENABLE,- DISABLE" "I2C2_SCL_INPUTENABLE_0,I2C2_SCL_INPUTENABLE_1" newline bitfld.long 0x2C 17. "I2C2_SCL_PULLTYPESELECT,- PULL_DOWN" "I2C2_SCL_PULLTYPESELECT_0,I2C2_SCL_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "I2C2_SCL_PULLUDENABLE,- ENABLE" "I2C2_SCL_PULLUDENABLE_0,I2C2_SCL_PULLUDENABLE_1" newline bitfld.long 0x2C 0.--3. "I2C2_SCL_MUXMODE,- I2C2_SCL" "I2C2_SCL_MUXMODE_0,I2C2_SCL_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,I2C2_SCL_MUXMODE_15" group.long 0x1818++0x37 line.long 0x00 "CTRL_CORE_PAD_WAKEUP0," rbitfld.long 0x00 25. "WAKEUP0_WAKEUPEVENT,- NOWAKEUP" "WAKEUP0_WAKEUPEVENT_0,WAKEUP0_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "WAKEUP0_WAKEUPENABLE,- DISABLE" "WAKEUP0_WAKEUPENABLE_0,WAKEUP0_WAKEUPENABLE_1" newline bitfld.long 0x00 17. "WAKEUP0_PULLTYPESELECT,- PULL_DOWN" "WAKEUP0_PULLTYPESELECT_0,WAKEUP0_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "WAKEUP0_PULLUDENABLE,- ENABLE" "WAKEUP0_PULLUDENABLE_0,WAKEUP0_PULLUDENABLE_1" newline bitfld.long 0x00 8. "WAKEUP0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "WAKEUP0_MODESELECT_0,WAKEUP0_MODESELECT_1" newline bitfld.long 0x00 4.--7. "WAKEUP0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "WAKEUP0_MUXMODE,- WAKEUP0" "WAKEUP0_MUXMODE_0,WAKEUP0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP0_MUXMODE_14,WAKEUP0_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_WAKEUP1," rbitfld.long 0x04 25. "WAKEUP1_WAKEUPEVENT,- NOWAKEUP" "WAKEUP1_WAKEUPEVENT_0,WAKEUP1_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "WAKEUP1_WAKEUPENABLE,- DISABLE" "WAKEUP1_WAKEUPENABLE_0,WAKEUP1_WAKEUPENABLE_1" newline bitfld.long 0x04 17. "WAKEUP1_PULLTYPESELECT,- PULL_DOWN" "WAKEUP1_PULLTYPESELECT_0,WAKEUP1_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "WAKEUP1_PULLUDENABLE,- ENABLE" "WAKEUP1_PULLUDENABLE_0,WAKEUP1_PULLUDENABLE_1" newline bitfld.long 0x04 8. "WAKEUP1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "WAKEUP1_MODESELECT_0,WAKEUP1_MODESELECT_1" newline bitfld.long 0x04 4.--7. "WAKEUP1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "WAKEUP1_MUXMODE,- WAKEUP1" "WAKEUP1_MUXMODE_0,WAKEUP1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP1_MUXMODE_14,WAKEUP1_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_WAKEUP2," rbitfld.long 0x08 25. "WAKEUP2_WAKEUPEVENT,- NOWAKEUP" "WAKEUP2_WAKEUPEVENT_0,WAKEUP2_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "WAKEUP2_WAKEUPENABLE,- DISABLE" "WAKEUP2_WAKEUPENABLE_0,WAKEUP2_WAKEUPENABLE_1" newline bitfld.long 0x08 17. "WAKEUP2_PULLTYPESELECT,- PULL_DOWN" "WAKEUP2_PULLTYPESELECT_0,WAKEUP2_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "WAKEUP2_PULLUDENABLE,- ENABLE" "WAKEUP2_PULLUDENABLE_0,WAKEUP2_PULLUDENABLE_1" newline bitfld.long 0x08 8. "WAKEUP2_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "WAKEUP2_MODESELECT_0,WAKEUP2_MODESELECT_1" newline bitfld.long 0x08 4.--7. "WAKEUP2_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "WAKEUP2_MUXMODE,- WAKEUP2" "WAKEUP2_MUXMODE_0,WAKEUP2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP2_MUXMODE_14,WAKEUP2_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_WAKEUP3," rbitfld.long 0x0C 25. "WAKEUP3_WAKEUPEVENT,- NOWAKEUP" "WAKEUP3_WAKEUPEVENT_0,WAKEUP3_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "WAKEUP3_WAKEUPENABLE,- DISABLE" "WAKEUP3_WAKEUPENABLE_0,WAKEUP3_WAKEUPENABLE_1" newline bitfld.long 0x0C 17. "WAKEUP3_PULLTYPESELECT,- PULL_DOWN" "WAKEUP3_PULLTYPESELECT_0,WAKEUP3_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "WAKEUP3_PULLUDENABLE,- ENABLE" "WAKEUP3_PULLUDENABLE_0,WAKEUP3_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "WAKEUP3_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "WAKEUP3_MODESELECT_0,WAKEUP3_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "WAKEUP3_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "WAKEUP3_MUXMODE,- WAKEUP3" "WAKEUP3_MUXMODE_0,WAKEUP3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP3_MUXMODE_14,WAKEUP3_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_ON_OFF," bitfld.long 0x10 17. "ON_OFF_PULLTYPESELECT,- PULL_DOWN" "ON_OFF_PULLTYPESELECT_0,ON_OFF_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "ON_OFF_PULLUDENABLE,- ENABLE" "ON_OFF_PULLUDENABLE_0,ON_OFF_PULLUDENABLE_1" line.long 0x14 "CTRL_CORE_PAD_RTC_PORZ," bitfld.long 0x14 17. "RTC_PORZ_PULLTYPESELECT,- PULL_DOWN" "RTC_PORZ_PULLTYPESELECT_0,RTC_PORZ_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "RTC_PORZ_PULLUDENABLE,- ENABLE" "RTC_PORZ_PULLUDENABLE_0,RTC_PORZ_PULLUDENABLE_1" line.long 0x18 "CTRL_CORE_PAD_TMS," bitfld.long 0x18 19. "TMS_SLEWCONTROL,- FAST_SLEW" "TMS_SLEWCONTROL_0,TMS_SLEWCONTROL_1" newline bitfld.long 0x18 18. "TMS_INPUTENABLE,- DISABLE" "TMS_INPUTENABLE_0,TMS_INPUTENABLE_1" newline bitfld.long 0x18 17. "TMS_PULLTYPESELECT,- PULL_DOWN" "TMS_PULLTYPESELECT_0,TMS_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "TMS_PULLUDENABLE,- ENABLE" "TMS_PULLUDENABLE_0,TMS_PULLUDENABLE_1" line.long 0x1C "CTRL_CORE_PAD_TDI," rbitfld.long 0x1C 25. "TDI_WAKEUPEVENT,- NOWAKEUP" "TDI_WAKEUPEVENT_0,TDI_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "TDI_WAKEUPENABLE,- DISABLE" "TDI_WAKEUPENABLE_0,TDI_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "TDI_SLEWCONTROL,- FAST_SLEW" "TDI_SLEWCONTROL_0,TDI_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "TDI_INPUTENABLE,- DISABLE" "TDI_INPUTENABLE_0,TDI_INPUTENABLE_1" newline bitfld.long 0x1C 17. "TDI_PULLTYPESELECT,- PULL_DOWN" "TDI_PULLTYPESELECT_0,TDI_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "TDI_PULLUDENABLE,- ENABLE" "TDI_PULLUDENABLE_0,TDI_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "TDI_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "TDI_MODESELECT_0,TDI_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "TDI_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "TDI_MUXMODE,- TDI" "TDI_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDI_MUXMODE_14,?" line.long 0x20 "CTRL_CORE_PAD_TDO," rbitfld.long 0x20 25. "TDO_WAKEUPEVENT,- NOWAKEUP" "TDO_WAKEUPEVENT_0,TDO_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "TDO_WAKEUPENABLE,- DISABLE" "TDO_WAKEUPENABLE_0,TDO_WAKEUPENABLE_1" newline bitfld.long 0x20 19. "TDO_SLEWCONTROL,- FAST_SLEW" "TDO_SLEWCONTROL_0,TDO_SLEWCONTROL_1" newline bitfld.long 0x20 18. "TDO_INPUTENABLE,- DISABLE" "TDO_INPUTENABLE_0,TDO_INPUTENABLE_1" newline bitfld.long 0x20 17. "TDO_PULLTYPESELECT,- PULL_DOWN" "TDO_PULLTYPESELECT_0,TDO_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "TDO_PULLUDENABLE,- ENABLE" "TDO_PULLUDENABLE_0,TDO_PULLUDENABLE_1" newline bitfld.long 0x20 8. "TDO_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "TDO_MODESELECT_0,TDO_MODESELECT_1" newline bitfld.long 0x20 4.--7. "TDO_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--3. "TDO_MUXMODE,- TDO" "TDO_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDO_MUXMODE_14,?" line.long 0x24 "CTRL_CORE_PAD_TCLK," bitfld.long 0x24 18. "TCLK_INPUTENABLE,- DISABLE" "TCLK_INPUTENABLE_0,TCLK_INPUTENABLE_1" newline bitfld.long 0x24 17. "TCLK_PULLTYPESELECT,- PULL_DOWN" "TCLK_PULLTYPESELECT_0,TCLK_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "TCLK_PULLUDENABLE,- ENABLE" "TCLK_PULLUDENABLE_0,TCLK_PULLUDENABLE_1" line.long 0x28 "CTRL_CORE_PAD_TRSTN," bitfld.long 0x28 19. "TRSTN_SLEWCONTROL,- FAST_SLEW" "TRSTN_SLEWCONTROL_0,TRSTN_SLEWCONTROL_1" newline bitfld.long 0x28 18. "TRSTN_INPUTENABLE,- DISABLE" "TRSTN_INPUTENABLE_0,TRSTN_INPUTENABLE_1" newline bitfld.long 0x28 17. "TRSTN_PULLTYPESELECT,- PULL_DOWN" "TRSTN_PULLTYPESELECT_0,TRSTN_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "TRSTN_PULLUDENABLE,- ENABLE" "TRSTN_PULLUDENABLE_0,TRSTN_PULLUDENABLE_1" line.long 0x2C "CTRL_CORE_PAD_RTCK," rbitfld.long 0x2C 25. "RTCK_WAKEUPEVENT,- NOWAKEUP" "RTCK_WAKEUPEVENT_0,RTCK_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "RTCK_WAKEUPENABLE,- DISABLE" "RTCK_WAKEUPENABLE_0,RTCK_WAKEUPENABLE_1" newline bitfld.long 0x2C 19. "RTCK_SLEWCONTROL,- FAST_SLEW" "RTCK_SLEWCONTROL_0,RTCK_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "RTCK_INPUTENABLE,- DISABLE" "RTCK_INPUTENABLE_0,RTCK_INPUTENABLE_1" newline bitfld.long 0x2C 17. "RTCK_PULLTYPESELECT,- PULL_DOWN" "RTCK_PULLTYPESELECT_0,RTCK_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "RTCK_PULLUDENABLE,- ENABLE" "RTCK_PULLUDENABLE_0,RTCK_PULLUDENABLE_1" newline bitfld.long 0x2C 8. "RTCK_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "RTCK_MODESELECT_0,RTCK_MODESELECT_1" newline bitfld.long 0x2C 4.--7. "RTCK_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 0.--3. "RTCK_MUXMODE,- RTCK" "RTCK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,RTCK_MUXMODE_14,?" line.long 0x30 "CTRL_CORE_PAD_EMU0," rbitfld.long 0x30 25. "EMU0_WAKEUPEVENT,- NOWAKEUP" "EMU0_WAKEUPEVENT_0,EMU0_WAKEUPEVENT_1" newline bitfld.long 0x30 24. "EMU0_WAKEUPENABLE,- DISABLE" "EMU0_WAKEUPENABLE_0,EMU0_WAKEUPENABLE_1" newline bitfld.long 0x30 19. "EMU0_SLEWCONTROL,- FAST_SLEW" "EMU0_SLEWCONTROL_0,EMU0_SLEWCONTROL_1" newline bitfld.long 0x30 18. "EMU0_INPUTENABLE,- DISABLE" "EMU0_INPUTENABLE_0,EMU0_INPUTENABLE_1" newline bitfld.long 0x30 17. "EMU0_PULLTYPESELECT,- PULL_DOWN" "EMU0_PULLTYPESELECT_0,EMU0_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "EMU0_PULLUDENABLE,- ENABLE" "EMU0_PULLUDENABLE_0,EMU0_PULLUDENABLE_1" newline bitfld.long 0x30 8. "EMU0_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "EMU0_MODESELECT_0,EMU0_MODESELECT_1" newline bitfld.long 0x30 4.--7. "EMU0_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "EMU0_MUXMODE,- EMU0" "EMU0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU0_MUXMODE_14,?" line.long 0x34 "CTRL_CORE_PAD_EMU1," rbitfld.long 0x34 25. "EMU1_WAKEUPEVENT,- NOWAKEUP" "EMU1_WAKEUPEVENT_0,EMU1_WAKEUPEVENT_1" newline bitfld.long 0x34 24. "EMU1_WAKEUPENABLE,- DISABLE" "EMU1_WAKEUPENABLE_0,EMU1_WAKEUPENABLE_1" newline bitfld.long 0x34 19. "EMU1_SLEWCONTROL,- FAST_SLEW" "EMU1_SLEWCONTROL_0,EMU1_SLEWCONTROL_1" newline bitfld.long 0x34 18. "EMU1_INPUTENABLE,- DISABLE" "EMU1_INPUTENABLE_0,EMU1_INPUTENABLE_1" newline bitfld.long 0x34 17. "EMU1_PULLTYPESELECT,- PULL_DOWN" "EMU1_PULLTYPESELECT_0,EMU1_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "EMU1_PULLUDENABLE,- ENABLE" "EMU1_PULLUDENABLE_0,EMU1_PULLUDENABLE_1" newline bitfld.long 0x34 8. "EMU1_MODESELECT,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode" "EMU1_MODESELECT_0,EMU1_MODESELECT_1" newline bitfld.long 0x34 4.--7. "EMU1_DELAYMODE,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34 0.--3. "EMU1_MUXMODE,- EMU1" "EMU1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU1_MUXMODE_14,?" group.long 0x185C++0x2F line.long 0x00 "CTRL_CORE_PAD_RESETN," bitfld.long 0x00 17. "RESETN_PULLTYPESELECT,- PULL_DOWN" "RESETN_PULLTYPESELECT_0,RESETN_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "RESETN_PULLUDENABLE,- ENABLE" "RESETN_PULLUDENABLE_0,RESETN_PULLUDENABLE_1" line.long 0x04 "CTRL_CORE_PAD_NMIN_DSP," rbitfld.long 0x04 25. "NMIN_WAKEUPEVENT,- NOWAKEUP" "NMIN_WAKEUPEVENT_0,NMIN_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "NMIN_WAKEUPENABLE,- DISABLE" "NMIN_WAKEUPENABLE_0,NMIN_WAKEUPENABLE_1" newline bitfld.long 0x04 17. "NMIN_PULLTYPESELECT,- PULL_DOWN" "NMIN_PULLTYPESELECT_0,NMIN_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "NMIN_PULLUDENABLE,- ENABLE" "NMIN_PULLUDENABLE_0,NMIN_PULLUDENABLE_1" line.long 0x08 "CTRL_CORE_PAD_RSTOUTN," bitfld.long 0x08 17. "RSTOUTN_PULLTYPESELECT,- PULL_DOWN" "RSTOUTN_PULLTYPESELECT_0,RSTOUTN_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "RSTOUTN_PULLUDENABLE,- ENABLE" "RSTOUTN_PULLUDENABLE_0,RSTOUTN_PULLUDENABLE_1" line.long 0x0C "CTRL_CORE_PADCONF_WAKEUPEVENT_0," bitfld.long 0x0C 31. "GPMC_A15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 30. "GPMC_A14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 29. "GPMC_A13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 28. "GPMC_A12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 27. "GPMC_A11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 26. "GPMC_A10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 25. "GPMC_A9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 24. "GPMC_A8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 23. "GPMC_A7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 22. "GPMC_A6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 21. "GPMC_A5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 20. "GPMC_A4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 19. "GPMC_A3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 18. "GPMC_A2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 17. "GPMC_A1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 16. "GPMC_A0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 15. "GPMC_AD15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 14. "GPMC_AD14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 13. "GPMC_AD13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 12. "GPMC_AD12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 11. "GPMC_AD11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 10. "GPMC_AD10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 9. "GPMC_AD9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 8. "GPMC_AD8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 7. "GPMC_AD7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 6. "GPMC_AD6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 5. "GPMC_AD5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 4. "GPMC_AD4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 3. "GPMC_AD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 2. "GPMC_AD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 1. "GPMC_AD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 0. "GPMC_AD0_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x10 "CTRL_CORE_PADCONF_WAKEUPEVENT_1," bitfld.long 0x10 31. "VIN1A_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 30. "VIN1A_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 29. "VIN1A_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 28. "VIN1A_VSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 27. "VIN1A_HSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 26. "VIN1A_FLD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 25. "VIN1A_DE0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 24. "VIN1B_CLK1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 23. "VIN1A_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 22. "GPMC_WAIT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 21. "GPMC_BEN1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 20. "GPMC_BEN0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 19. "GPMC_WEN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 18. "GPMC_OEN_REN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 17. "GPMC_ADVN_ALE_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 16. "GPMC_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 15. "GPMC_CS3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 14. "GPMC_CS2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 13. "GPMC_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 12. "GPMC_CS1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 11. "GPMC_A27_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 10. "GPMC_A26_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 9. "GPMC_A25_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 8. "GPMC_A24_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 7. "GPMC_A23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 6. "GPMC_A22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 5. "GPMC_A21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 4. "GPMC_A20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 3. "GPMC_A19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 2. "GPMC_A18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 1. "GPMC_A17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 0. "GPMC_A16_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x14 "CTRL_CORE_PADCONF_WAKEUPEVENT_2," bitfld.long 0x14 31. "VIN2A_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 30. "VIN2A_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 29. "VIN2A_D3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 28. "VIN2A_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 27. "VIN2A_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 26. "VIN2A_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 25. "VIN2A_VSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 24. "VIN2A_HSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 23. "VIN2A_FLD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 22. "VIN2A_DE0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 21. "VIN2A_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 20. "VIN1A_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 19. "VIN1A_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 18. "VIN1A_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 17. "VIN1A_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 16. "VIN1A_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 15. "VIN1A_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 14. "VIN1A_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 13. "VIN1A_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 12. "VIN1A_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 11. "VIN1A_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 10. "VIN1A_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 9. "VIN1A_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 8. "VIN1A_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 7. "VIN1A_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 6. "VIN1A_D9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 5. "VIN1A_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 4. "VIN1A_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 3. "VIN1A_D6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 2. "VIN1A_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 1. "VIN1A_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 0. "VIN1A_D3_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x18 "CTRL_CORE_PADCONF_WAKEUPEVENT_3," bitfld.long 0x18 31. "VOUT1_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 30. "VOUT1_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 29. "VOUT1_D6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 28. "VOUT1_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 27. "VOUT1_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 26. "VOUT1_D3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 25. "VOUT1_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 24. "VOUT1_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 23. "VOUT1_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 22. "VOUT1_VSYNC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 21. "VOUT1_HSYNC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 20. "VOUT1_FLD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 19. "VOUT1_DE_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 18. "VOUT1_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 17. "VIN2A_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 16. "VIN2A_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 15. "VIN2A_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 14. "VIN2A_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 13. "VIN2A_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 12. "VIN2A_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 11. "VIN2A_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 10. "VIN2A_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 9. "VIN2A_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 8. "VIN2A_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 7. "VIN2A_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 6. "VIN2A_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 5. "VIN2A_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 4. "VIN2A_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 3. "VIN2A_D9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 2. "VIN2A_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 1. "VIN2A_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 0. "VIN2A_D6_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x1C "CTRL_CORE_PADCONF_WAKEUPEVENT_4," bitfld.long 0x1C 31. "RGMII0_RXD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 30. "RGMII0_RXD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 29. "RGMII0_RXD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 28. "RGMII0_RXD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 27. "RGMII0_RXCTL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 26. "RGMII0_RXC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 25. "RGMII0_TXD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 24. "RGMII0_TXD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 23. "RGMII0_TXD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 22. "RGMII0_TXD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 21. "RGMII0_TXCTL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 20. "RGMII0_TXC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 19. "UART3_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 18. "UART3_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 17. "RMII_MHZ_50_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 16. "MDIO_D_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 15. "MDIO_MCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 14. "VOUT1_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 13. "VOUT1_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 12. "VOUT1_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 11. "VOUT1_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 10. "VOUT1_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 9. "VOUT1_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 8. "VOUT1_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 7. "VOUT1_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 6. "VOUT1_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 5. "VOUT1_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 4. "VOUT1_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 3. "VOUT1_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 2. "VOUT1_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 1. "VOUT1_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 0. "VOUT1_D9_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x20 "CTRL_CORE_PADCONF_WAKEUPEVENT_5," bitfld.long 0x20 31. "MCASP2_ACLKR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 30. "MCASP2_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 29. "MCASP2_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 28. "MCASP1_AXR15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 27. "MCASP1_AXR14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 26. "MCASP1_AXR13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 25. "MCASP1_AXR12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 24. "MCASP1_AXR11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 23. "MCASP1_AXR10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 22. "MCASP1_AXR9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 21. "MCASP1_AXR8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 20. "MCASP1_AXR7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 19. "MCASP1_AXR6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 18. "MCASP1_AXR5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 17. "MCASP1_AXR4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 16. "MCASP1_AXR3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 15. "MCASP1_AXR2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 14. "MCASP1_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 13. "MCASP1_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 12. "MCASP1_FSR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 11. "MCASP1_ACLKR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 10. "MCASP1_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 9. "MCASP1_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 8. "XREF_CLK3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 7. "XREF_CLK2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 6. "XREF_CLK1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 5. "XREF_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 4. "GPIO6_16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 3. "GPIO6_15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 2. "GPIO6_14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 1. "USB2_DRVVBUS_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 0. "USB1_DRVVBUS_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x24 "CTRL_CORE_PADCONF_WAKEUPEVENT_6," bitfld.long 0x24 31. "MMC3_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 30. "GPIO6_11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 29. "GPIO6_10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 28. "MMC1_SDWP_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 27. "MMC1_SDCD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 26. "MMC1_DAT3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 25. "MMC1_DAT2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 24. "MMC1_DAT1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 23. "MMC1_DAT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 22. "MMC1_CMD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 21. "MMC1_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 20. "MCASP5_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 19. "MCASP5_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 18. "MCASP5_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 17. "MCASP5_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 16. "MCASP4_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 15. "MCASP4_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 14. "MCASP4_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 13. "MCASP4_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 12. "MCASP3_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 11. "MCASP3_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 10. "MCASP3_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 9. "MCASP3_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 8. "MCASP2_AXR7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 7. "MCASP2_AXR6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 6. "MCASP2_AXR5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 5. "MCASP2_AXR4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 4. "MCASP2_AXR3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 3. "MCASP2_AXR2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 2. "MCASP2_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 1. "MCASP2_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 0. "MCASP2_FSR_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x28 "CTRL_CORE_PADCONF_WAKEUPEVENT_7," bitfld.long 0x28 31. "UART2_RTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 30. "UART2_CTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 29. "UART2_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 28. "UART2_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 27. "UART1_RTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 26. "UART1_CTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 25. "UART1_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 24. "UART1_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 23. "DCAN2_RX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 22. "DCAN2_TX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 21. "DCAN1_RX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 20. "DCAN1_TX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 19. "SPI2_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 18. "SPI2_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 17. "SPI2_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 16. "SPI2_SCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 15. "SPI1_CS3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 14. "SPI1_CS2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 13. "SPI1_CS1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 12. "SPI1_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 11. "SPI1_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 10. "SPI1_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 9. "SPI1_SCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 8. "MMC3_DAT7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 7. "MMC3_DAT6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 6. "MMC3_DAT5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 5. "MMC3_DAT4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 4. "MMC3_DAT3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 3. "MMC3_DAT2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 2. "MMC3_DAT1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 1. "MMC3_DAT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 0. "MMC3_CMD_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x2C "CTRL_CORE_PADCONF_WAKEUPEVENT_8," bitfld.long 0x2C 18. "NMIN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 17. "EMU4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 16. "EMU3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 15. "EMU2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 14. "EMU1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 13. "EMU0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 12. "RTCK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 11. "TDO_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 10. "TDI_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 9. "WAKEUP3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 8. "WAKEUP2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 7. "WAKEUP1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 6. "WAKEUP0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 5. "I2C3_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 4. "I2C3_SDA_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 3. "I2C2_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 2. "I2C2_SDA_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 1. "I2C1_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 0. "I2C1_SDA_DUPLICATEWAKEUPEVENT," "0,1" rgroup.long 0x1B08++0x0B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_2,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM" bitfld.long 0x00 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x00 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_GPU_2,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_3,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD" bitfld.long 0x04 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x04 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_GPU_3,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_4,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH" bitfld.long 0x08 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x08 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL[4:0] LDOVBBGPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_GPU_4,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH" rgroup.long 0x1B1C++0x0F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_1,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_LOW" bitfld.long 0x00 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x00 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_LOW which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "STD_FUSE_OPP_VMIN_MPU_1,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_LOW" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_2,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM" bitfld.long 0x04 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x04 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL [4:0] LDOVBBMPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x04 0.--11. 1. "STD_FUSE_OPP_VMIN_MPU_2,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_3,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD" bitfld.long 0x08 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x08 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL [4:0] LDOVBBMPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--11. 1. "STD_FUSE_OPP_VMIN_MPU_3,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_4,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH This register also stores information about ABB configuration for that OPP" bitfld.long 0x0C 25. "ABBEN,- ABB_disabled" "ABBEN_0,ABBEN_1" newline bitfld.long 0x0C 20.--24. "VSETABB,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field if ABB is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x0C 0.--11. 1. "STD_FUSE_OPP_VMIN_MPU_4,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH" rgroup.long 0x1B38++0x47 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_0,Standard Fuse OPP VDD_IVA [31:0]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_1,Standard Fuse OPP VDD_IVA [63:32]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_2,Standard Fuse OPP VDD_IVA [95:64]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_3,Standard Fuse OPP VDD_IVA [127:96]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_4,Standard Fuse OPP VDD_IVA [159:128]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x3C "CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL,CORE 4th SRAM LDO Control register" bitfld.long 0x3C 26. "LDOSRAMCORE_4_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_4_RETMODE_MUX_CTRL_0,LDOSRAMCORE_4_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x3C 21.--25. "LDOSRAMCORE_4_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 16.--20. "LDOSRAMCORE_4_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 10. "LDOSRAMCORE_4_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_4_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_4_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x3C 5.--9. "LDOSRAMCORE_4_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 0.--4. "LDOSRAMCORE_4_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL,CORE 5th SRAM LDO Control register" bitfld.long 0x40 26. "LDOSRAMCORE_5_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_5_RETMODE_MUX_CTRL_0,LDOSRAMCORE_5_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x40 21.--25. "LDOSRAMCORE_5_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 16.--20. "LDOSRAMCORE_5_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 10. "LDOSRAMCORE_5_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_5_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_5_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x40 5.--9. "LDOSRAMCORE_5_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 0.--4. "LDOSRAMCORE_5_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL,DSPEVE 2nd SRAM LDO Control register" bitfld.long 0x44 26. "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x44 21.--25. "LDOSRAMDSPEVE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 16.--20. "LDOSRAMDSPEVE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 10. "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x44 5.--9. "LDOSRAMDSPEVE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 0.--4. "LDOSRAMDSPEVE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C04++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_2,OCP Spare Register" hexmask.long.word 0x00 18.--31. 1. "SMA_SW_2,Spare bits" newline hexmask.long.tbyte 0x00 0.--17. 1. "ABE_DPLL_REGMF_CONTROL,Fractional part of the software-configured multiplication ratio M of DPLL_ABE" line.long 0x04 "CTRL_CORE_SMA_SW_3,OCP Spare Register" bitfld.long 0x04 31. "CAL_BASELINE_EN,CAL baseline enable" "All 4 video ports enabled,Baseline mode (only video port 1 enabled)" newline bitfld.long 0x04 30. "CAL_TILED_MEMORY_SPACE,This is the 33rd address bit on the L3_MAIN associated with CAL" "The lower 4GiB address space (Q0-Q3) is accessed,The address space associated with the 8 TILER.." newline bitfld.long 0x04 21. "CSI2_0_XY_IE,Input buffer enable for all DX and DY lanes of CSI2_PHY1" "0,1" newline bitfld.long 0x04 20. "CSI2_1_XY_IE,Input buffer enable for all DX and DY lanes of CSI2_PHY2" "0,1" newline bitfld.long 0x04 19. "CSI2_0_XY_PIPD,Pull-down enable (active low) for all DX and DY lanes of CSI2_PHY1" "0,1" newline bitfld.long 0x04 18. "CSI2_1_XY_PIPD,Pull-down enable (active low) for all DX and DY lanes of CSI2_PHY2" "0,1" newline bitfld.long 0x04 17. "CSI2_0_XY_PIPU,Pull-up enable (active low) for all DX and DY lanes of CSI2_PHY1" "0,1" newline bitfld.long 0x04 16. "CSI2_1_XY_PIPU,Pull-up enable (active low) for all DX and DY lanes of CSI2_PHY2" "0,1" group.long 0x1C14++0x33 line.long 0x00 "CTRL_CORE_SMA_SW_6,OCP Spare Register" bitfld.long 0x00 27.--28. "PLLEN_CONTROL,PLLEN control setting" "CLKOUT is disabled,CLKOUT is enabled,?..." newline bitfld.long 0x00 16.--17. "PCIE_TX_RX_CONTROL,PCIe RX and TX control of ACSPCIe" "ACSPCIe Power Down Mode,ACSPCIe TX Mode,ACSPCIe RX Mode,Reserved" newline bitfld.long 0x00 8. "RMII_CLK_SETTING,RMII CLK setting" "Internal clock from DPLL_GMAC,External clock from RMII_MHZ_50_CLK pin" newline bitfld.long 0x00 0. "MUXSEL_32K_CLKIN,Setting for mux to select 32KHz clock input to PRCM" "0,1" line.long 0x04 "CTRL_CORE_SMA_SW_7,OCP Spare Register" bitfld.long 0x04 17. "MMU2_ABORT_ENABLE,MMU2 abort enable" "0,1" newline bitfld.long 0x04 16. "MMU1_ABORT_ENABLE,MMU1 abort enable" "0,1" newline bitfld.long 0x04 13. "PCIE_SS1_MMU_ROUTE_ENABLE,PCIe_SS1 MMU route enable" "0,1" newline bitfld.long 0x04 12. "PCIE_SS2_MMU_ROUTE_ENABLE,PCIe_SS2 MMU route enable" "0,1" newline bitfld.long 0x04 11. "EDMA_TC0_RD_MMU_ROUTE_ENABLE,EDMA TC0 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 10. "EDMA_TC1_RD_MMU_ROUTE_ENABLE,EDMA TC1 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 9. "EDMA_TC0_WR_MMU_ROUTE_ENABLE,EDMA TC0 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 8. "EDMA_TC1_WR_MMU_ROUTE_ENABLE,EDMA TC1 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 1. "PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE,PCIe_SS1 AXI2OCP legacy mode enable" "0,1" newline bitfld.long 0x04 0. "PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLE,PCIe_SS2 AXI2OCP legacy mode enable" "0,1" line.long 0x08 "CTRL_CORE_SMA_SW_8,Test control inputs used by the module" line.long 0x0C "CTRL_CORE_SMA_SW_9,Test control inputs used by the module" line.long 0x10 "CTRL_CORE_PCIESS1_PCS1," hexmask.long.word 0x10 22.--31. 1. "PCIESS1_PCS_TEST_TXDATA," newline hexmask.long.word 0x10 12.--21. 1. "PCIESS1_PCS_ERR_BIT_EN," newline hexmask.long.byte 0x10 4.--11. 1. "PCIESS1_PCS_CFG_HOLDOFF," newline bitfld.long 0x10 0.--3. "PCIESS1_PCS_DET_DELAY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "CTRL_CORE_PCIESS1_PCS2," bitfld.long 0x14 27.--31. "PCIESS1_PCS_CFG_SYNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 23.--26. "PCIESS1_PCS_CFG_EQ_FUNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 19.--22. "PCIESS1_PCS_CFG_EQ_HOLD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 15.--18. "PCIESS1_PCS_CFG_EQ_INIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 12.--14. "PCIESS1_PCS_TEST_OSEL," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9. "PCIESS1_PCS_TEST_LSEL," "0,1" newline bitfld.long 0x14 6.--7. "PCIESS1_PCS_ERR_MODE," "0,1,2,3" newline bitfld.long 0x14 5. "PCIESS1_PCS_L1_SLEEP," "0,1" newline bitfld.long 0x14 4. "PCIESS1_PCS_TEST_MODE," "0,1" newline bitfld.long 0x14 2.--3. "PCIESS1_PCS_ERR_LN_EN," "0,1,2,3" newline bitfld.long 0x14 0. "PCIESS1_PCS_SHORT_TIMES," "0,1" line.long 0x18 "CTRL_CORE_PCIESS2_PCS1," hexmask.long.word 0x18 22.--31. 1. "PCIESS2_PCS_TEST_TXDATA," newline hexmask.long.word 0x18 12.--21. 1. "PCIESS2_PCS_ERR_BIT_EN," newline hexmask.long.byte 0x18 4.--11. 1. "PCIESS2_PCS_CFG_HOLDOFF," newline bitfld.long 0x18 0.--3. "PCIESS2_PCS_DET_DELAY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "CTRL_CORE_PCIESS2_PCS2," bitfld.long 0x1C 27.--31. "PCIESS2_PCS_CFG_SYNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 23.--26. "PCIESS2_PCS_CFG_EQ_FUNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 19.--22. "PCIESS2_PCS_CFG_EQ_HOLD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 15.--18. "PCIESS2_PCS_CFG_EQ_INIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--14. "PCIESS2_PCS_TEST_OSEL," "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 9. "PCIESS2_PCS_TEST_LSEL," "0,1" newline bitfld.long 0x1C 6.--7. "PCIESS2_PCS_ERR_MODE," "0,1,2,3" newline bitfld.long 0x1C 5. "PCIESS2_PCS_L1_SLEEP," "0,1" newline bitfld.long 0x1C 4. "PCIESS2_PCS_TEST_MODE," "0,1" newline bitfld.long 0x1C 2.--3. "PCIESS2_PCS_ERR_LN_EN," "0,1,2,3" newline bitfld.long 0x1C 0. "PCIESS2_PCS_SHORT_TIMES," "0,1" line.long 0x20 "CTRL_CORE_PCIE_PCS," hexmask.long.byte 0x20 16.--23. 1. "PCIESS_PCS_RC_DELAY_COUNT,Set to 0x96 for proper functional and compliance-mode behavior on both PCIESS1 and PCIESS2" line.long 0x24 "CTRL_CORE_PCIE_PCS_REVISION,pcs_revision" bitfld.long 0x24 23.--25. "PCIESS2_PCS_REVISION," "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--22. "PCIESS1_PCS_REVISION," "0,1,2,3,4,5,6,7" line.long 0x28 "CTRL_CORE_PCIE_CONTROL,serdes control selection PCIE C0 (0 default) vs PCIE B1 (1)" bitfld.long 0x28 2. "PCIE_B1C0_MODE_SEL," "0,1" newline bitfld.long 0x28 0. "PCIE_B0_B1_TSYNCEN," "0,1" line.long 0x2C "CTRL_CORE_PHY_POWER_PCIESS1," hexmask.long.word 0x2C 22.--31. 1. "PCIESS1_PWRCTL_CLKFREQ,Frequency of SYSCLK1 in MHz (rounded)" newline abitfld.long 0x2C 14.--21. "PCIESS1_PWRCTL_CMD,Powers up/down the PCIESS1_PHY_TX and PCIESS1_PHY_RX modules" "0x00=Powers down PCIESS1_PHY_TX and PCIESS1_PHY_RX,0x01=Powers up PCIESS1_PHY_RX,0x02=Powers up PCIESS1_PHY_TX,0x03=Powers up PCIESS1_PHY_TX and PCIESS1_PHY_RX.." line.long 0x30 "CTRL_CORE_PHY_POWER_PCIESS2," hexmask.long.word 0x30 22.--31. 1. "PCIESS2_PWRCTL_CLKFREQ,Frequency of SYSCLK1 in MHz (rounded)" newline abitfld.long 0x30 14.--21. "PCIESS2_PWRCTL_CMD,Powers up/down the PCIESS2_PHY_TX and PCIESS2_PHY_RX modules" "0x00=Powers down PCIESS2_PHY_TX and PCIESS2_PHY_RX,0x01=Powers up PCIESS2_PHY_RX,0x02=Powers up PCIESS2_PHY_TX,0x03=Powers up PCIESS2_PHY_TX and PCIESS2_PHY_RX.." width 0x0B tree.end tree "CTRL_MODULE_WKUP" base ad:0x4AE0C000 group.long 0x100++0x03 line.long 0x00 "CTRL_WKUP_SEC_CTRL,Control Register" bitfld.long 0x00 31. "SECCTRLWRDISABLE,Control Register write disable control" "Write in this register is allowed,Write in this register is forbidden" newline bitfld.long 0x00 4. "SECURE_EMIF_CONFIG_RO_EN,Access mode for registers: CTRL_WKUP_EMIF1_SDRAM_CONFIG CTRL_WKUP_EMIF2_SDRAM_CONFIG" "These registers are RW,These registers are RO" group.long 0x108++0x0B line.long 0x00 "CTRL_WKUP_SEC_TAP,TAP controllers register" bitfld.long 0x00 31. "SECTAPWR_DISABLE,TAP controllers register write disable control" "0,1" newline bitfld.long 0x00 13. "IPU2_TAPENABLE,IPU2 TAP control" "IPU2_TAPENABLE_0,IPU2_TAPENABLE_1" newline bitfld.long 0x00 12. "DSP2_TAPENABLE,DSP2 TAP control" "DSP2_TAPENABLE_0,DSP2_TAPENABLE_1" newline bitfld.long 0x00 11. "JTAGEXT_TAPENABLE,External JTAG expansion TAP control" "JTAGEXT_TAPENABLE_0,JTAGEXT_TAPENABLE_1" newline bitfld.long 0x00 10. "IVA_TAPENABLE,IVA TAP control - DISABLED" "IVA_TAPENABLE_0,IVA_TAPENABLE_1" newline bitfld.long 0x00 9. "MPUGLOBALDEBUG_ENABLE,MPU TAP control - DISABLED" "MPUGLOBALDEBUG_ENABLE_0,MPUGLOBALDEBUG_ENABLE_1" newline bitfld.long 0x00 4. "IEEE1500_ENABLE,IEEE1500 and P1500 access enable" "0,1" newline bitfld.long 0x00 3. "P1500_ENABLE,P1500 access enable - DISABLED" "P1500_ENABLE_0,P1500_ENABLE_1" newline bitfld.long 0x00 2. "IPU1_TAPENABLE,IPU1 TAP control - DISABLED" "IPU1_TAPENABLE_0,IPU1_TAPENABLE_1" newline bitfld.long 0x00 1. "DSP1_TAPENABLE,DSP1 TAP control - DISABLED" "DSP1_TAPENABLE_0,DSP1_TAPENABLE_1" newline bitfld.long 0x00 0. "DAP_TAPENABLE,DAP TAP control - DISABLED" "DAP_TAPENABLE_0,DAP_TAPENABLE_1" line.long 0x04 "CTRL_WKUP_OCPREG_SPARE,OCP Spare Register" bitfld.long 0x04 31. "OCPREG_SPARE31,OCP spare register 31" "0,1" newline bitfld.long 0x04 30. "OCPREG_SPARE30,OCP spare register 30" "0,1" newline bitfld.long 0x04 29. "OCPREG_SPARE29,OCP spare register 29" "0,1" newline bitfld.long 0x04 28. "OCPREG_SPARE28,OCP spare register 28" "0,1" newline bitfld.long 0x04 27. "OCPREG_SPARE27,OCP spare register 27" "0,1" newline bitfld.long 0x04 26. "OCPREG_SPARE26,OCP spare register 26" "0,1" newline bitfld.long 0x04 25. "OCPREG_SPARE25,OCP spare register 25" "0,1" newline bitfld.long 0x04 24. "OCPREG_SPARE24,OCP spare register 24" "0,1" newline bitfld.long 0x04 23. "OCPREG_SPARE23,OCP spare register 23" "0,1" newline bitfld.long 0x04 22. "OCPREG_SPARE22,OCP spare register 22" "0,1" newline bitfld.long 0x04 21. "OCPREG_SPARE21,OCP spare register 21" "0,1" newline bitfld.long 0x04 20. "OCPREG_SPARE20,OCP spare register 20" "0,1" newline bitfld.long 0x04 19. "OCPREG_SPARE19,OCP spare register 19" "0,1" newline bitfld.long 0x04 18. "OCPREG_SPARE18,OCP spare register 18" "0,1" newline bitfld.long 0x04 17. "OCPREG_SPARE17,OCP spare register 17" "0,1" newline bitfld.long 0x04 16. "OCPREG_SPARE16,OCP spare register 16" "0,1" newline bitfld.long 0x04 15. "OCPREG_SPARE15,OCP spare register 15" "0,1" newline bitfld.long 0x04 14. "OCPREG_SPARE14,OCP spare register 14" "0,1" newline bitfld.long 0x04 13. "OCPREG_SPARE13,OCP spare register 13" "0,1" newline bitfld.long 0x04 12. "OCPREG_SPARE12,OCP spare register 12" "0,1" newline bitfld.long 0x04 11. "OCPREG_SPARE11,OCP spare register 11" "0,1" newline bitfld.long 0x04 10. "OCPREG_SPARE10,OCP spare register 10" "0,1" newline bitfld.long 0x04 9. "OCPREG_SPARE9,OCP spare register 9" "0,1" newline bitfld.long 0x04 8. "OCPREG_SPARE8,OCP spare register 8" "0,1" newline bitfld.long 0x04 7. "OCPREG_SPARE7,OCP spare register 7" "0,1" newline bitfld.long 0x04 6. "OCPREG_SPARE6,OCP spare register 6" "0,1" newline bitfld.long 0x04 5. "OCPREG_SPARE5,OCP spare register 5" "0,1" newline bitfld.long 0x04 4. "OCPREG_SPARE4,OCP spare register 4" "0,1" newline bitfld.long 0x04 3. "OCPREG_SPARE3,OCP spare register 3" "0,1" newline bitfld.long 0x04 2. "OCPREG_SPARE2,OCP spare register 2" "0,1" newline bitfld.long 0x04 1. "OCPREG_SPARE1,OCP spare register 1" "0,1" line.long 0x08 "CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG,EMIF1 SDRAM configuration register" bitfld.long 0x08 27.--28. "EMIF1_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "EMIF1_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "EMIF1_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x08 21.--22. "EMIF1_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "EMIF1_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "EMIF1_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x08 16.--17. "EMIF1_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 10.--13. "EMIF1_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "EMIF1_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "EMIF1_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--2. "EMIF1_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIG,EMIF2 SDRAM register" bitfld.long 0x00 27.--28. "EMIF2_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x00 24.--26. "EMIF2_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "EMIF2_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x00 21.--22. "EMIF2_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x00 20. "EMIF2_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x00 18.--19. "EMIF2_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x00 16.--17. "EMIF2_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x00 10.--13. "EMIF2_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7.--9. "EMIF2_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "EMIF2_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "EMIF2_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" rgroup.long 0x138++0x07 line.long 0x00 "CTRL_WKUP_STD_FUSE_USB_CONF,Standard Fuse conf [31:0]" hexmask.long.word 0x00 16.--31. 1. "USB_PROD_ID,USB Product Identification" newline hexmask.long.word 0x00 0.--15. 1. "USB_VENDOR_ID,USB Vendor Identification" line.long 0x04 "CTRL_WKUP_STD_FUSE_CONF,Standard Fuse conf [63:32]" bitfld.long 0x04 28. "STD_MCAN_CANFD_DISABLE," "0,1" newline bitfld.long 0x04 27. "STD_CAL_WDCPM_DISABLE," "0,1" newline bitfld.long 0x04 21. "STD_FUSE_EMIF2_INITREF_DEF_DIS,Disable EMIF2 DDR refresh and initialization sequence" "refresh and initialization sequence are enabled,refresh and initialization sequence are disabled" newline bitfld.long 0x04 20. "STD_FUSE_EMIF2_DDR3_LPDDR2N,EMIF2 DDR3" "reserved,DDR3 configured" newline bitfld.long 0x04 19. "STD_FUSE_EMIF1_INITREF_DEF_DIS,Disable EMIF1 DDR refresh and initialization sequence" "refresh and initialization sequence are enabled,refresh and initialization sequence are disabled" newline bitfld.long 0x04 18. "STD_FUSE_EMIF1_DDR3_LPDDR2N,EMIF1 DDR3" "reserved,DDR3 configured" newline bitfld.long 0x04 16. "STD_FUSE_HDCP_ENABLE,Enable HDCP" "enables HDCP,disables HDCP" newline bitfld.long 0x04 12. "STD_FUSE_CH_SPEEDUP_DISABLE,ROM code settings for configuration header block and speedup block" "enables CH and speedup,disables CH and speedup" newline bitfld.long 0x04 4. "STD_FUSE_SGX540_3D_CLOCK_SOURCE,Functional clock selection for the 3D accelerator engine" "GPU is fully enabled (DPLL_CORE/PER),GPU is partially enabled (DPLL_PER/8 max)" newline bitfld.long 0x04 3. "STD_FUSE_SGX540_3D_DISABLE,Disable the 3D accelerator engine" "SGX is enabled,SGX is disabled" group.long 0x144++0x27 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x00 17. "EMIF1_NARROW_ONLY,EMIF1 operates in narrow mode to allow for data macros to be powered down to save power" "narrow mode disabled,narrow mode enabled" newline bitfld.long 0x00 16. "EMIF1_EN_ECC,EMIF1 ECC enable" "ECC is disabled,ECC is enabled" newline bitfld.long 0x00 14.--15. "EMIF1_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "4 samples,8 samples,16 samples,128 samples" newline bitfld.long 0x00 13. "EMIF1_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "Algorithm 1 is used,Algorithm 2 is used" newline bitfld.long 0x00 12. "EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "if the DRAM provides a read response on only one..,if the DRAM provides a read response on all DQ.." newline bitfld.long 0x00 9.--11. "EMIF1_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "selects phy_reg_rdlvl_start_ratio[7:0],selects phy_reg_rdlvl_start_ratio[15:8],selects phy_reg_rdlvl_end_ratio[7:0],selects phy_reg_rdlvl_end_ratio[15:8],?..." newline bitfld.long 0x00 7. "EMIF1_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "DDR3 SDRAM reset signal is enabled,DDR3 SDRAM reset signal is disabled" newline bitfld.long 0x00 5.--6. "EMIF1_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "ODT disabled,60 Ohms,80 Ohms 0x3 =120 Ohms,?..." newline bitfld.long 0x00 3. "EMIF1_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180Degree)" "0,1" newline bitfld.long 0x00 2. "EMIF1_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x00 1. "EMIF1_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x00 0. "EMIF1_EN_SLICE_0,Enable command PHY 0" "0,1" line.long 0x04 "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x04 17. "EMIF2_NARROW_ONLY,EMIF2 operates in narrow mode to allow for data macros to be powered down to save power" "narrow mode disabled,narrow mode enabled" newline bitfld.long 0x04 14.--15. "EMIF2_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "4 samples,8 samples,16 samples,128 samples" newline bitfld.long 0x04 13. "EMIF2_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "Algorithm 1 is used,Algorithm 2 is used" newline bitfld.long 0x04 12. "EMIF2_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "if the DRAM provides a read response on only one..,if the DRAM provides a read response on all DQ.." newline bitfld.long 0x04 9.--11. "EMIF2_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "selects phy_reg_rdlvl_start_ratio[7:0],selects phy_reg_rdlvl_start_ratio[15:8],selects phy_reg_rdlvl_end_ratio[7:0],selects phy_reg_rdlvl_end_ratio[15:8],?..." newline bitfld.long 0x04 7. "EMIF2_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "DDR3 SDRAM reset signal is enabled,DDR3 SDRAM reset signal is disabled" newline bitfld.long 0x04 5.--6. "EMIF2_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "ODT disabled,60 Ohms,80 Ohms 0x3 =120 Ohms,?..." newline bitfld.long 0x04 3. "EMIF2_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180Degree)" "0,1" newline bitfld.long 0x04 2. "EMIF2_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x04 1. "EMIF2_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x04 0. "EMIF2_EN_SLICE_0,Enable command PHY 0" "0,1" line.long 0x08 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1," line.long 0x0C "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2," line.long 0x10 "CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL,GPU Voltage Body Bias LDO Control register" bitfld.long 0x10 10. "LDOVBBGPU_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "efuse value is used,override value is used" newline rbitfld.long 0x10 5.--9. "LDOVBBGPU_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 0.--4. "LDOVBBGPU_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL,MPU Voltage Body Bias LDO Control register" bitfld.long 0x14 10. "LDOVBBMPU_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "efuse value is used,override value is used" newline rbitfld.long 0x14 5.--9. "LDOVBBMPU_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "LDOVBBMPU_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "CTRL_WKUP_LDOSRAM_GPU_VOLTAGE_CTRL,GPU SRAM LDO Control register" bitfld.long 0x18 26. "LDOSRAMGPU_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMGPU_RETMODE_MUX_CTRL_0,LDOSRAMGPU_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x18 21.--25. "LDOSRAMGPU_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 16.--20. "LDOSRAMGPU_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 10. "LDOSRAMGPU_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMGPU_ACTMODE_MUX_CTRL_0,LDOSRAMGPU_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x18 5.--9. "LDOSRAMGPU_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 0.--4. "LDOSRAMGPU_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "CTRL_WKUP_LDOSRAM_MPU_VOLTAGE_CTRL,MPU SRAM LDO Control register" bitfld.long 0x1C 26. "LDOSRAMMPU_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMMPU_RETMODE_MUX_CTRL_0,LDOSRAMMPU_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 21.--25. "LDOSRAMMPU_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 16.--20. "LDOSRAMMPU_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 10. "LDOSRAMMPU_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMMPU_ACTMODE_MUX_CTRL_0,LDOSRAMMPU_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 5.--9. "LDOSRAMMPU_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 0.--4. "LDOSRAMMPU_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO Control register" bitfld.long 0x20 26. "LDOSRAMCORE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_RETMODE_MUX_CTRL_0,LDOSRAMCORE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x20 21.--25. "LDOSRAMCORE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 16.--20. "LDOSRAMCORE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 10. "LDOSRAMCORE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x20 5.--9. "LDOSRAMCORE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 0.--4. "LDOSRAMCORE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "CTRL_WKUP_LDOSRAM_MPU_2_VOLTAGE_CTRL,MPU 2nd SRAM LDO Control register" bitfld.long 0x24 26. "LDOSRAMMPU_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMMPU_2_RETMODE_MUX_CTRL_0,LDOSRAMMPU_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x24 21.--25. "LDOSRAMMPU_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 16.--20. "LDOSRAMMPU_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 10. "LDOSRAMMPU_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMMPU_2_ACTMODE_MUX_CTRL_0,LDOSRAMMPU_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x24 5.--9. "LDOSRAMMPU_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 0.--4. "LDOSRAMMPU_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x200++0x17 line.long 0x00 "CTRL_WKUP_STD_FUSE_DIE_ID_0,Die ID Register : Part 0" line.long 0x04 "CTRL_WKUP_ID_CODE,ID_CODE Key Register" line.long 0x08 "CTRL_WKUP_STD_FUSE_DIE_ID_1,Die ID Register : Part 1" line.long 0x0C "CTRL_WKUP_STD_FUSE_DIE_ID_2,Die ID Register : Part 2" line.long 0x10 "CTRL_WKUP_STD_FUSE_DIE_ID_3,Die ID Register : Part 3" line.long 0x14 "CTRL_WKUP_STD_FUSE_PROD_ID_0,Prod ID Register : Part 0" group.long 0x5AC++0x03 line.long 0x00 "CTRL_WKUP_CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control" bitfld.long 0x00 31. "OSCILLATOR0_BOOST,Fast startup control of OSC0" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 30. "OSCILLATOR0_OS_OUT,Oscillator output of OSC0" "low to high transition in BOOST mode,BOOST is disabled" newline bitfld.long 0x00 29. "OSCILLATOR1_BOOST,Fast startup control of OSC1" "Fast startup is disabled,Fast startup is enabled" newline bitfld.long 0x00 28. "OSCILLATOR1_OS_OUT,Oscillator output of OSC1" "low to high transition in BOOST mode,BOOST is disabled" group.long 0x5C8++0x0F line.long 0x00 "CTRL_WKUP_EFUSE_1,EFUSE compensation 1" bitfld.long 0x00 31. "DDRDIFF_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x00 30. "DDRDIFF_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x00 29. "DDRDIFF_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x00 28. "DDRDIFF_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x00 27. "DDRDIFF_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x00 26. "DDRDIFF_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x00 25. "DDRDIFF_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x00 24. "DDRDIFF_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x00 23. "DDRDIFF_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x00 22. "DDRDIFF_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x00 21. "DDRDIFF_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x00 20. "DDRDIFF_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x00 19. "DDRDIFF_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x00 18. "DDRDIFF_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x00 17. "DDRDIFF_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x00 16. "DDRDIFF_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x00 15. "DDRDIFF_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x00 14. "DDRDIFF_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x00 13. "DDRDIFF_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x00 12. "DDRDIFF_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x00 11. "DDRDIFF_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x00 10. "DDRDIFF_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x00 9. "DDRDIFF_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x00 8. "DDRDIFF_PTV_EAST_SIDE_P0," "0,1" line.long 0x04 "CTRL_WKUP_EFUSE_2,EFUSE compensation 2" bitfld.long 0x04 31. "DDRDIFF_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x04 30. "DDRDIFF_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x04 29. "DDRDIFF_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x04 28. "DDRDIFF_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x04 27. "DDRDIFF_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x04 26. "DDRDIFF_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x04 25. "DDRDIFF_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x04 24. "DDRDIFF_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x04 23. "DDRDIFF_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x04 22. "DDRDIFF_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x04 21. "DDRDIFF_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x04 20. "DDRDIFF_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x04 19. "DDRDIFF_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x04 18. "DDRDIFF_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x04 17. "DDRDIFF_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x04 16. "DDRDIFF_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x04 15. "DDRDIFF_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x04 14. "DDRDIFF_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x04 13. "DDRDIFF_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x04 12. "DDRDIFF_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x04 11. "DDRDIFF_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x04 10. "DDRDIFF_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x04 9. "DDRDIFF_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x04 8. "DDRDIFF_PTV_WEST_SIDE_P0," "0,1" line.long 0x08 "CTRL_WKUP_EFUSE_3,EFUSE compensation 3" bitfld.long 0x08 31. "DDRSE_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x08 30. "DDRSE_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x08 29. "DDRSE_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x08 28. "DDRSE_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x08 27. "DDRSE_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x08 26. "DDRSE_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x08 25. "DDRSE_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x08 24. "DDRSE_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x08 23. "DDRSE_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x08 22. "DDRSE_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x08 21. "DDRSE_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x08 20. "DDRSE_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x08 19. "DDRSE_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x08 18. "DDRSE_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x08 17. "DDRSE_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x08 16. "DDRSE_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x08 15. "DDRSE_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x08 14. "DDRSE_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x08 13. "DDRSE_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x08 12. "DDRSE_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x08 11. "DDRSE_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x08 10. "DDRSE_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x08 9. "DDRSE_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x08 8. "DDRSE_PTV_EAST_SIDE_P0," "0,1" line.long 0x0C "CTRL_WKUP_EFUSE_4,EFUSE compensation 4" bitfld.long 0x0C 31. "DDRSE_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x0C 30. "DDRSE_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x0C 29. "DDRSE_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x0C 28. "DDRSE_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x0C 27. "DDRSE_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x0C 26. "DDRSE_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x0C 25. "DDRSE_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x0C 24. "DDRSE_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x0C 23. "DDRSE_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x0C 22. "DDRSE_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x0C 21. "DDRSE_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x0C 20. "DDRSE_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x0C 19. "DDRSE_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x0C 18. "DDRSE_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x0C 17. "DDRSE_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x0C 16. "DDRSE_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x0C 15. "DDRSE_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x0C 14. "DDRSE_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x0C 13. "DDRSE_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x0C 12. "DDRSE_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x0C 11. "DDRSE_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x0C 10. "DDRSE_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x0C 9. "DDRSE_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x0C 8. "DDRSE_PTV_WEST_SIDE_P0," "0,1" group.long 0x5F8++0x03 line.long 0x00 "CTRL_WKUP_EFUSE_13," bitfld.long 0x00 31. "SDIO1833_PTV_N5," "0,1" newline bitfld.long 0x00 30. "SDIO1833_PTV_N4," "0,1" newline bitfld.long 0x00 29. "SDIO1833_PTV_N3," "0,1" newline bitfld.long 0x00 28. "SDIO1833_PTV_N2," "0,1" newline bitfld.long 0x00 27. "SDIO1833_PTV_N1," "0,1" newline bitfld.long 0x00 26. "SDIO1833_PTV_N0," "0,1" newline bitfld.long 0x00 25. "SDIO1833_PTV_P5," "0,1" newline bitfld.long 0x00 24. "SDIO1833_PTV_P4," "0,1" newline bitfld.long 0x00 23. "SDIO1833_PTV_P3," "0,1" newline bitfld.long 0x00 22. "SDIO1833_PTV_P2," "0,1" newline bitfld.long 0x00 21. "SDIO1833_PTV_P1," "0,1" newline bitfld.long 0x00 20. "SDIO1833_PTV_P0," "0,1" width 0x0B tree.end tree.end tree "DCAN" repeat 2. (list 2. 1. )(list ad:0x48480000 ad:0x4AE3C000 ) tree "DCAN$1" base $2 group.long 0x00++0x17 line.long 0x00 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit" bitfld.long 0x00 25. "WUBA,Automatic wake up on bus activity when in local power-down mode" "WUBA_0,WUBA_1" bitfld.long 0x00 24. "PDR,Request for local low power-down mode" "PDR_0,PDR_1" bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "DE3_0,DE3_1" newline bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "DE2_0,DE2_1" bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "DE1_0,DE1_1" bitfld.long 0x00 17. "IE1,Interrupt line 1 enable" "IE1_0,IE1_1" newline bitfld.long 0x00 16. "INITDBG,Internal init state while debug access" "INITDBG_0,INITDBG_1" bitfld.long 0x00 15. "SWR,Software reset enable" "SWR_0,SWR_1" bitfld.long 0x00 10.--13. "PMD,Parityon/off" "?,?,?,?,?,PMD_5,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 9. "ABO,Auto-Bus-On enable" "ABO_0,ABO_1" bitfld.long 0x00 8. "IDS,Interruption debug support enable" "IDS_0,IDS_1" bitfld.long 0x00 7. "TEST,Test mode enable" "TEST_0,TEST_1" newline bitfld.long 0x00 6. "CCE,Configuration change enable" "CCE_0,CCE_1" bitfld.long 0x00 5. "DAR,Disable automatic retransmission" "DAR_0,DAR_1" bitfld.long 0x00 3. "EIE,Error interrupt enable" "EIE_0,EIE_1" newline bitfld.long 0x00 2. "SIE,Status change interrupt enable" "SIE_0,SIE_1" bitfld.long 0x00 1. "IE0,Interrupt line 0 enable" "IE0_0,IE0_1" bitfld.long 0x00 0. "INIT,Initialization" "INIT_0,INIT_1" line.long 0x04 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER. BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND. RXOK. TXOK. and LEC (if SIE bit in is 1)" rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge" "PDA_0,PDA_1" rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "WAKEUPPND_0,WAKEUPPND_1" bitfld.long 0x04 8. "PER,Parity error detected" "PER_0_w,PER_1_w" newline rbitfld.long 0x04 7. "BOFF,Bus-Off state" "BOFF_0,BOFF_1" rbitfld.long 0x04 6. "EWARN,Warning state" "EWARN_0,EWARN_1" rbitfld.long 0x04 5. "EPASS,Error passive state" "EPASS_0,EPASS_1" newline rbitfld.long 0x04 4. "RXOK,Received a message successfully" "RXOK_0,RXOK_1" rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "TXOK_0,TXOK_1" rbitfld.long 0x04 0.--2. "LEC,Last error code" "LEC_0,LEC_1,LEC_2,LEC_3,LEC_4,LEC_5,LEC_6,LEC_7" line.long 0x08 "DCAN_ERRC,Error Counter Register" bitfld.long 0x08 15. "RP,Receive error passive" "RP_0,RP_1" hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter" line.long 0x0C "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set" bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample point - Valid programmed values are 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample point - Valid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump Width - Valid programmed values are 0 to 3" "0,1,2,3" bitfld.long 0x0C 0.--5. "BRP,Baud rate prescaler - Value by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "DCAN_INT,Interrupt register" hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)" hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)" line.long 0x14 "DCAN_TEST,Test Register For all test modes. the TEST bit in control register needs to be set to 1" bitfld.long 0x14 9. "RDA,RAM direct access enable" "RDA_0,RDA_1" bitfld.long 0x14 8. "EXL,External loopback mode" "EXL_0,EXL_1" rbitfld.long 0x14 7. "RX,Receive pin" "RX_0,RX_1" newline bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "TX_0,TX_1,TX_2,TX_3" bitfld.long 0x14 4. "LBACK,Loopback mode" "LBACK_0,LBACK_1" bitfld.long 0x14 3. "SILENT,Silent mode" "SILENT_0,SILENT_1" rgroup.long 0x1C++0x07 line.long 0x00 "DCAN_PERR,Parity Error Code Register If a parity error is detected. the PER flag will be set in" bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detected - RDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)" line.long 0x04 "DCAN_REL,Core revision register" group.long 0x80++0x53 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running. the Auto-Bus-On procedure will be aborted" line.long 0x04 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set" bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3" newline bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x08 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x0C "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x10 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x14 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x18 "DCAN_NWDAT_X,New Data X Register With the new data X register. the software can detect if one or more bits in the different new data registers are set" bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3" newline bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x1C "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x20 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x24 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x28 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x2C "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register. the software can detect if one or more bits in the different interrupt pending registers are set" bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3" newline bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x30 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x34 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x38 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x3C "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x40 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register. the software can detect if one or more bits in the different message valid registers are set" bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3" newline bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3" bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3" newline bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x44 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x48 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x4C "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x50 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" group.long 0xD8++0x0F line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" group.long 0x100++0x17 line.long 0x00 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bits" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bit" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" newline bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flag" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 update" "DMAACTIVE_0,DMAACTIVE_1" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer" line.long 0x04 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" newline hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance mask" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" newline bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" newline bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" newline hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" newline hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x120++0x17 line.long 0x00 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" newline bitfld.long 0x00 20. "CONTROL,Access control bits" "CONTROL_0,CONTROL_1" bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bit" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" newline bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" bitfld.long 0x00 15. "BUSY,Busy flag" "BUSY_0,BUSY_1" newline bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update" "DMAACTIVE_0,DMAACTIVE_1" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer" line.long 0x04 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" newline hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use acceptance mask" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" newline bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" newline bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" newline hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" newline hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x140++0x17 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update.." rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data" "IF3_UPD_0,IF3_UPD_1" rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access" "IF3_SDB_0,IF3_SDB_1" rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access" "IF3_SDA_0,IF3_SDA_1" newline rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access" "IF3_SC_0,IF3_SC_1" rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access" "IF3_SA_0,IF3_SA_1" rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access" "IF3_SM_0,IF3_SM_1" newline bitfld.long 0x00 4. "DATAB,Data B read observation" "DATAB_0,DATAB_1" bitfld.long 0x00 3. "DATAA,Data A read observation" "DATAA_0,DATAA_1" bitfld.long 0x00 2. "CTRL,Ctrl read observation" "CTRL_0,CTRL_1" newline bitfld.long 0x00 1. "ARB,Arbitration data read observation" "ARB_0,ARB_1" bitfld.long 0x00 0. "MASK,Mask data read observation" "MASK_0,MASK_1" line.long 0x04 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" rbitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x08 31. "MSGVAL,Message Valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended Identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message Direction" "DIR_0,DIR_1" newline hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28:0]: 29-bit Identifier ('extended frame')" line.long 0x0C "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x0C 15. "NEWDAT,New Data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt Pending" "INTPND_0,INTPND_1" newline bitfld.long 0x0C 12. "UMASK,Use Acceptance Mask" "UMASK_0,UMASK_1" bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable" "RXIE_0,RXIE_1" newline bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit Request" "TXRQST_0,TXRQST_1" bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" newline bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" newline hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" newline hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x160++0x0F line.long 0x00 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x04 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x08 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x0C "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed" bitfld.long 0x00 18. "PU,CAN_TX pull up/pull down select" "PU_0,PU_1" bitfld.long 0x00 17. "PD,CAN_TX pull disable" "PD_0,PD_1" bitfld.long 0x00 16. "OD,CAN_TX open drain enable" "OD_0,OD_1" newline bitfld.long 0x00 3. "FUNC,CAN_TX function" "FUNC_0,FUNC_1" bitfld.long 0x00 2. "DIR,CAN_TX data direction" "DIR_0,DIR_1" bitfld.long 0x00 1. "OUT,CAN_TX data out" "OUT_0,OUT_1" newline bitfld.long 0x00 0. "IN,CAN_TX data in" "IN_0,IN_1" line.long 0x04 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed" bitfld.long 0x04 18. "PU,CAN_RX pull up/pull down select" "PU_0,PU_1" bitfld.long 0x04 17. "PD,CAN_RX pull disable" "PD_0,PD_1" bitfld.long 0x04 16. "OD,CAN_RX open drain enable" "OD_0,OD_1" newline bitfld.long 0x04 3. "FUNC,CAN_RX function" "FUNC_0,FUNC_1" bitfld.long 0x04 2. "DIR,CAN_RX data direction" "DIR_0,DIR_1" bitfld.long 0x04 1. "OUT,CAN_RX data out" "OUT_0,OUT_1" newline bitfld.long 0x04 0. "IN,CAN_RX data in" "IN_0,IN_1" width 0x0B tree.end repeat.end tree.end tree "Display_Controller" base ad:0x58001000 tree "Channel_0" group.long 0x80++0x03 line.long 0x00 "DISPC_GFX_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger. based on the field polarity. 0 only used when graphics pipeline on the LCD output.." group.long 0x640++0x03 line.long 0x00 "DISPC_VID1_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0xE8++0x03 line.long 0x00 "DISPC_VID1_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x600++0x03 line.long 0x00 "DISPC_VID1_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 1" group.long 0xBC++0x03 line.long 0x00 "DISPC_VID1_BA_j_0,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA_0 is used)" group.long 0x648++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x688++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6AC++0x03 line.long 0x00 "DISPC_VID2_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x178++0x03 line.long 0x00 "DISPC_VID2_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x608++0x03 line.long 0x00 "DISPC_VID2_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 2" group.long 0x14C++0x03 line.long 0x00 "DISPC_VID2_BA_j_0,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID2_BA_0 is.." group.long 0x6B4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x184++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x180++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F4++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x200++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x728++0x03 line.long 0x00 "DISPC_VID3_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x300++0x03 line.long 0x00 "DISPC_VID3_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x610++0x03 line.long 0x00 "DISPC_VID3_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 3" group.long 0x308++0x03 line.long 0x00 "DISPC_VID3_BA_j_0,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID3_BA_0 is.." group.long 0x730++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x314++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x310++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x770++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x350++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x794++0x03 line.long 0x00 "DISPC_WB_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x500++0x03 line.long 0x00 "DISPC_WB_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x618++0x03 line.long 0x00 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline" group.long 0x508++0x03 line.long 0x00 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA_0 is used)" group.long 0x7A0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x514++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x510++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E0++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x550++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_1" group.long 0x84++0x03 line.long 0x00 "DISPC_GFX_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger. based on the field polarity. 0 only used when graphics pipeline on the LCD output.." group.long 0x644++0x03 line.long 0x00 "DISPC_VID1_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0xEC++0x03 line.long 0x00 "DISPC_VID1_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x604++0x03 line.long 0x00 "DISPC_VID1_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 1" group.long 0xC0++0x03 line.long 0x00 "DISPC_VID1_BA_j_1,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA_0 is used)" group.long 0x650++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xFC++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x68C++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6B0++0x03 line.long 0x00 "DISPC_VID2_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x17C++0x03 line.long 0x00 "DISPC_VID2_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x60C++0x03 line.long 0x00 "DISPC_VID2_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 2" group.long 0x150++0x03 line.long 0x00 "DISPC_VID2_BA_j_1,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID2_BA_0 is.." group.long 0x6BC++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x18C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x188++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F8++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x204++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x72C++0x03 line.long 0x00 "DISPC_VID3_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x304++0x03 line.long 0x00 "DISPC_VID3_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x614++0x03 line.long 0x00 "DISPC_VID3_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 3" group.long 0x30C++0x03 line.long 0x00 "DISPC_VID3_BA_j_1,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID3_BA_0 is.." group.long 0x738++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x31C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x318++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x774++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x354++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x798++0x03 line.long 0x00 "DISPC_WB_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x504++0x03 line.long 0x00 "DISPC_WB_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x61C++0x03 line.long 0x00 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline" group.long 0x50C++0x03 line.long 0x00 "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA_0 is used)" group.long 0x7A8++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x51C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x518++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E4++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x554++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_2" group.long 0x658++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x104++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x100++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x690++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6C4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x194++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x190++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6FC++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x208++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x740++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x324++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x320++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x778++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x358++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x524++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x520++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E8++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x558++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_3" group.long 0x660++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x10C++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x108++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x694++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1EC++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6CC++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x19C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x198++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x700++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x20C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x748++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x32C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x328++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x77C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x35C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B8++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x52C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x528++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7EC++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x55C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_4" group.long 0x668++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x114++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x110++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x698++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6D4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A4++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A0++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x704++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x210++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x750++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x334++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x330++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x780++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x360++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x534++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x530++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F0++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x560++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_5" group.long 0x670++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x11C++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x118++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x69C++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6DC++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1AC++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1A8++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x708++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x214++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x758++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x33C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x338++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x784++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x364++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7C8++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x53C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x538++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F4++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x564++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_6" group.long 0x678++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x124++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x120++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1F8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6E4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B4++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B0++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x70C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x218++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x760++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x344++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x340++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x788++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x368++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x544++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x540++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7F8++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x568++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end tree "Channel_7" group.long 0x680++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x12C++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x128++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6A4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1FC++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6EC++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1BC++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x1B8++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x710++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x21C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x768++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x34C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x348++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x78C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x36C++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7D8++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x54C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x548++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7FC++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x56C++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end group.long 0x858++0x03 line.long 0x00 "DISABLE_MSTANDBY_ENHANCEMENT,This register disables the DISPC DMA Mstandby behavior enhancement" bitfld.long 0x00 0. "DISABLE_MSTANDBY_ENHANCEMENT," "0,1" group.long 0x854++0x03 line.long 0x00 "DISPC_BA0_FLIPIMMEDIATE_EN,This register enables the flip immediate" bitfld.long 0x00 3. "VID3,Enable flip immediate for video3 pipeline" "0,1" newline bitfld.long 0x00 2. "VID2,Enable flip immediate for video2 pipeline" "0,1" newline bitfld.long 0x00 1. "VID1,Enable flip immediate for video1 pipeline" "0,1" newline bitfld.long 0x00 0. "GFX,Enable flip immediate for gfx pipeline" "0,1" group.long 0x44++0x03 line.long 0x00 "DISPC_CONFIG1,The control register configures the Display Controller module for the primary LCD output and TV output" bitfld.long 0x00 28.--29. "TVINTERLEAVE,TV Interleave Pattern" "0,1,2,3" newline bitfld.long 0x00 26.--27. "PLCDINTERLEAVE,pLCD Interleave Pattern" "0,1,2,3" newline bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONV ENABLE,Enable the color space conversion" "COLORCONV ENABLE_0,COLORCONV ENABLE_1" newline bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODE ENABLE,Selects between progressive and interlace mode for the primary LCD output" "OUTPUTMODE ENABLE_0,OUTPUTMODE ENABLE_1" newline bitfld.long 0x00 21. "BT1120ENABLE,Selects BT.1120 format on the primary LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT.656 format on the primary LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x00 19. "TVALPHABLENDER ENABLE,Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output)" "TVALPHABLENDER ENABLE_0,TVALPHABLENDER ENABLE_1" newline bitfld.long 0x00 18. "LCDALPHABLENDER ENABLE,Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output)" "LCDALPHABLENDER ENABLE_0,LCDALPHABLENDER ENABLE_1" newline bitfld.long 0x00 17. "BUFFERFILLING,Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold" "BUFFERFILLING_0,BUFFERFILLING_1" newline bitfld.long 0x00 15. "CPR,Color phase rotation control (primary LCD output)" "CPR_0,CPR_1" newline bitfld.long 0x00 14. "BUFFERMERGE,Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "BUFFERMERGE_0,BUFFERMERGE_1" newline bitfld.long 0x00 13. "TCKTV SELECTION,Transparency color key selection (TV output) wr: EVSYNC - GDTCK" "TCKTV SELECTION_0,TCKTV SELECTION_1" newline bitfld.long 0x00 12. "TCKTVENABLE,Transparency color key enabled (TV output) WR: EVSYNC - DisTCK" "TCKTVENABLE_0,TCKTVENABLE_1" newline bitfld.long 0x00 11. "TCKLCD SELECTION,Transparency color key selection (primary LCD output) wr: VFP start period of primary LCD output - GDTK" "TCKLCD SELECTION_0,TCKLCD SELECTION_1" newline bitfld.long 0x00 10. "TCKLCDENABLE,Transparency color key enabled (primary LCD output) wr: VFP start period of primary LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x00 9. "GAMATABLE ENABLE,For backward compatibility an enable bit has been added on the 2 additional gamma tables (secondary display and TV)" "GAMATABLE ENABLE_0,GAMATABLE ENABLE_1" newline bitfld.long 0x00 8. "ACBIASGATED,ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCK GATED,Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - PCGDis" "PIXELCLOCK GATED_0,PIXELCLOCK GATED_1" newline bitfld.long 0x00 4. "PIXELDATAGATED,Pixel data gated enabled (primary LCD output) wr: VFP start period of primary LCD output - PDGDis" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x00 3. "PALETTEGAMMA TABLE,Palette/gamma table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the.." "PALETTEGAMMA TABLE_0,PALETTEGAMMA TABLE_1" newline bitfld.long 0x00 1.--2. "LOADMODE,Loading mode for the palette/gamma table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the.." "LOADMODE_0,LOADMODE_1,LOADMODE_2,LOADMODE_3" newline bitfld.long 0x00 0. "PIXELGATED,Pixel gated enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" group.long 0x620++0x03 line.long 0x00 "DISPC_CONFIG2,The control register configures the Display Controller module for the secondary LCD output" bitfld.long 0x00 26.--27. "SLCDINTERLEAVE,sLCD Interleave Pattern" "0,1,2,3" newline bitfld.long 0x00 25. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONV ENABLE,Enable the color space conversion" "COLORCONV ENABLE_0,COLORCONV ENABLE_1" newline bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODE ENABLE,Selects between progressive and interlace mode for the secondary LCD output" "OUTPUTMODE ENABLE_0,OUTPUTMODE ENABLE_1" newline bitfld.long 0x00 21. "BT1120ENABLE,Selects BT.1120 format on the primary LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT.656 format on the primary LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x00 15. "CPR,Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output - CPRDis. - CPREnb" "CPR_0,CPR_1" newline bitfld.long 0x00 11. "TCKLCD SELECTION,Transparency color key selection (secondary LCD output) wr: VFP start period of secondary LCD output - GDTK" "TCKLCD SELECTION_0,TCKLCD SELECTION_1" newline bitfld.long 0x00 10. "TCKLCDENABLE,Transparency color key enabled (secondary LCD output) wr: VFP start period of secondary LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x00 8. "ACBIASGATED,ACBias gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x00 6. "HSYNCGATED,HSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCK GATED,Pixel clock gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - PCGDis" "PIXELCLOCK GATED_0,PIXELCLOCK GATED_1" newline bitfld.long 0x00 4. "PIXELDATA GATED,Pixel data gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - PDGDis" "PIXELDATA GATED_0,PIXELDATA GATED_1" newline bitfld.long 0x00 0. "PIXELGATED,Pixel gated enable (only for active matrix) (secondary LCD output) wr: VFP start period of secondary LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" group.long 0x84C++0x03 line.long 0x00 "DISPC_CONFIG3,The control register configures the display controller module for the third LCD output" bitfld.long 0x00 26.--27. "TLCDINTERLEAVE,tLCD interleave Pattern" "0,1,2,3" newline bitfld.long 0x00 25. "FULLRANGE,Color space conversion full range setting - Limrange" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the third LCD output - Disable" "OUTPUTMODEENABLE_0,OUTPUTMODEENABLE_1" newline bitfld.long 0x00 21. "BT1120ENABLE,Selects BT.1120 format on the third LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT.656 format on the third LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x00 15. "CPR,Color phase rotation control ( third LCD output)" "CPR_0,CPR_1" newline bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency color key selection (third LCD output) wr: VFP start period of the third LCD output - GDTK" "TCKLCDSELECTION_0,TCKLCDSELECTION_1" newline bitfld.long 0x00 10. "TCKLCDENABLE,Transparency color key enabled (third LCD output) wr: VFP start period of the third LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x00 8. "ACBIASGATED,ACBias gated enabled (third LCD output) wr: VFP start period of the third LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x00 6. "HSYNCGATED,HSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel clock gated enabled (third LCD output) wr: VFP start period of the third LCD output - PCGDis" "PIXELCLOCKGATED_0,PIXELCLOCKGATED_1" newline bitfld.long 0x00 4. "PIXELDATAGATED,Pixel data gated enabled (third LCD output) wr: VFP start period of the third LCD output - PDGDis" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x00 0. "PIXELGATED,Pixel gated enable (only for TFT) (third LCD output) wr: VFP start period of the third LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" group.long 0x40++0x03 line.long 0x00 "DISPC_CONTROL1,The control register configures the Display Controller module for the primary LCD and TV outputs" bitfld.long 0x00 30.--31. "SPATIALTEMPORAL DITHERINGFRAMES,Spatial/temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD - OneFrame" "SPATIALTEMPORAL DITHERINGFRAMES_0,SPATIALTEMPORAL DITHERINGFRAMES_1,SPATIALTEMPORAL DITHERINGFRAMES_2,SPATIALTEMPORAL DITHERINGFRAMES_3" newline rbitfld.long 0x00 29. "LCDENABLEPOL,Write 0s for future compatibility" "LCDENABLEPOL_0,LCDENABLEPOL_1" newline rbitfld.long 0x00 28. "LCDENABLESIGNAL,Write 0s for future compatibility" "LCDENABLESIGNAL_0,LCDENABLESIGNAL_1" newline rbitfld.long 0x00 27. "PCKFREEENABLE,Write 0s for future compatibility" "PCKFREEENABLE_0,PCKFREEENABLE_1" newline bitfld.long 0x00 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the primary LCD output" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" newline bitfld.long 0x00 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD - 1CycPerPix" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x00 21.--22. "TDMPARALLELMODE,Output interface width (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD - 8bParaInt" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" newline bitfld.long 0x00 20. "TDMENABLE,Enable the multiple cycle format for the primary LCD output" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x00 17.--19. "HT,Hold time for TV output WR: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)" "HT_0,HT_1,HT_2,HT_3,HT_4,HT_5,HT_6,HT_7" newline bitfld.long 0x00 16. "GPOUT1,General purpose output signal l WR: immediate - reset" "GPOUT1_0,GPOUT1_1" newline bitfld.long 0x00 15. "GPOUT0,General Purpose Output Signal WR:immediate - reset" "GPOUT0_0,GPOUT0_1" newline rbitfld.long 0x00 14. "GPIN1,General purpose input signal WR: immediately - reset" "GPIN1_0_r,GPIN1_1_r" newline rbitfld.long 0x00 13. "GPIN0,General purpose input signal WR: immediately - GPin0Rst" "GPIN0_0_r,GPIN0_1_r" newline bitfld.long 0x00 12. "OVERLAYOPTI MIZATION,Overlay optimization for the primary LCD output WR: VFP start period of the primary LCD - GDBVWfM" "OVERLAYOPTI MIZATION_0,OVERLAYOPTI MIZATION_1" newline bitfld.long 0x00 11. "STALLMODE,STALL mode for the primary LCD output wr: VFP start period of primary LCD" "STALLMODE_0,STALLMODE_1" newline bitfld.long 0x00 8.--9. "TFTDATALINES,Number of lines of the primary LCD interface WR: VFP start period of primary LCD - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x00 7. "STDITHERENABLE,Spatial temporal dithering enable for the primary LCD output WR: VFP start period of primary LCD - STDithDis" "STDITHERENABLE_0,STDITHERENABLE_1" newline bitfld.long 0x00 6. "GOTV,GO command for the TV output" "GOTV_0,GOTV_1" newline bitfld.long 0x00 5. "GOLCD,GO command for the primary LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x00 4. "M8B,Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x00 3. "STNTFT,LCD Display type of the primary LCD WR: VFP start period of primary LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x00 2. "MONOCOLOR,Monochrome/color selection for the primary LCD WR: VFP start period of primary LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x00 1. "TVENABLE,Enable the TV output wr: immediate effect only occurs at the end of the current frame" "TVENABLE_0,TVENABLE_1" newline bitfld.long 0x00 0. "LCDENABLE,Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" group.long 0x238++0x03 line.long 0x00 "DISPC_CONTROL2,The control register configures the Display Controller module for the secondary LCD output" bitfld.long 0x00 30.--31. "SPATIALTEMPORAL DITHERINGFRAMES,Spatial/temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output - OneFrame" "SPATIALTEMPORAL DITHERINGFRAMES_0,SPATIALTEMPORAL DITHERINGFRAMES_1,SPATIALTEMPORAL DITHERINGFRAMES_2,SPATIALTEMPORAL DITHERINGFRAMES_3" newline bitfld.long 0x00 25.--26. "TDMUNUSED BITS,State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - LowLevel" "TDMUNUSED BITS_0,TDMUNUSED BITS_1,TDMUNUSED BITS_2,TDMUNUSED BITS_3" newline bitfld.long 0x00 23.--24. "TDMCYCLE FORMAT,Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - 1CycPerPix" "TDMCYCLE FORMAT_0,TDMCYCLE FORMAT_1,TDMCYCLE FORMAT_2,TDMCYCLE FORMAT_3" newline bitfld.long 0x00 21.--22. "TDMPARALLEL MODE,Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - 8bParaInt" "TDMPARALLEL MODE_0,TDMPARALLEL MODE_1,TDMPARALLEL MODE_2,TDMPARALLEL MODE_3" newline bitfld.long 0x00 20. "TDMENABLE,Enable the multiple cycle format for the secondary LCD output wr: VFP start period of secondary LCD output - TDMDis" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x00 13. "TVOVERLAY OPTIMIZATION,Overlay optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "TVOVERLAY OPTIMIZATION_0,TVOVERLAY OPTIMIZATION_1" newline bitfld.long 0x00 12. "OVERLAY OPTIMIZATION,Overlay optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "OVERLAY OPTIMIZATION_0,OVERLAY OPTIMIZATION_1" newline bitfld.long 0x00 11. "STALLMODE,STALL mode for the secondary LCD output wr: VFP start period of secondary LCD output - nMode" "STALLMODE_0,STALLMODE_1" newline bitfld.long 0x00 8.--9. "TFTDATALINES,Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x00 7. "STDITHER ENABLE,Spatial temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output - STDithDis" "STDITHER ENABLE_0,STDITHER ENABLE_1" newline bitfld.long 0x00 6. "GOWB,GO command for the write-back output" "GOWB_0,GOWB_1" newline bitfld.long 0x00 5. "GOLCD,GO command for the secondary LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x00 4. "M8B,Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x00 3. "STNTFT,LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x00 2. "MONOCOLOR,Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x00 0. "LCDENABLE,Enable the secondary LCD output wr:immediate - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" group.long 0x848++0x03 line.long 0x00 "DISPC_CONTROL3,The control register configures the display controller module for the third LCD output" bitfld.long 0x00 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/temporal dithering number of frames for the third LCD output wr: VFP start period of the third LCD output - OneFrame" "SPATIALTEMPORALDITHERINGFRAMES_0,SPATIALTEMPORALDITHERINGFRAMES_1,SPATIALTEMPORALDITHERINGFRAMES_2,SPATIALTEMPORALDITHERINGFRAMES_3" newline bitfld.long 0x00 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output - LowLevel" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" newline bitfld.long 0x00 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the third LCD output wr: VFP start period of third LCD output - 1CycPerPix" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x00 21.--22. "TDMPARALLELMODE,Output interface width (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output - 8bParaInt" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" newline bitfld.long 0x00 20. "TDMENABLE,Enable the multiple cycle format for the third LCD output wr: VFP start period of third LCD output - TDMDis" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x00 12. "OVERLAYOPTIMIZATION,Overlay optimization for the third LCD output wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "OVERLAYOPTIMIZATION_0,OVERLAYOPTIMIZATION_1" newline bitfld.long 0x00 11. "STALLMODE,STALL mode for the third LCD output wr: VFP start period of the third LCD output - nMode" "STALLMODE_0,STALLMODE_1" newline bitfld.long 0x00 8.--9. "TFTDATALINES,Number of lines of the third LCD interface wr: VFP start period of the third LCD output - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x00 7. "STDITHERENABLE,Spatial temporal dithering enable for the third LCD output wr: VFP start period of the third LCD output - STDithDis" "STDITHERENABLE_0,STDITHERENABLE_1" newline bitfld.long 0x00 5. "GOLCD,GO command for the third LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x00 4. "M8B,Mono 8-bit mode of the third LCD wr: VFP start period of the third LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x00 3. "STNTFT,LCD Display type of the third LCD wr: VFP start period of the third LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x00 2. "MONOCOLOR,Monochrome/color selection for the third LCD wr: VFP start period of the third LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x00 0. "LCDENABLE,Enable the third LCD output wr: Immediate - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" group.long 0x228++0x03 line.long 0x00 "DISPC_CPR1_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x00 22.--31. 1. "BR,BR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "BG,BG coefficient encoded signed value (from -512 to 511" newline hexmask.long.word 0x00 0.--9. 1. "BB,BB coefficient encoded signed value (from -512 to 511)" group.long 0x224++0x03 line.long 0x00 "DISPC_CPR1_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x00 22.--31. 1. "GR,GR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "GG,GG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 0.--9. 1. "GB,GB coefficient encoded signed value (from -512 to 511)" group.long 0x220++0x03 line.long 0x00 "DISPC_CPR1_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x00 22.--31. 1. "RR,RR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "RG,RG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 0.--9. 1. "RB,RB coefficient encoded signed value (from -512 to 511)" group.long 0x3B4++0x0B line.long 0x00 "DISPC_CPR2_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x00 22.--31. 1. "BR,BR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "BG,BG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 0.--9. 1. "BB,BB coefficient encoded signed value (from -512 to 511)" line.long 0x04 "DISPC_CPR2_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x04 22.--31. 1. "GR,GR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 11.--20. 1. "GG,GG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 0.--9. 1. "GB,GB coefficient encoded signed value (from -512 to 511)" line.long 0x08 "DISPC_CPR2_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x08 22.--31. 1. "RR,RR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x08 11.--20. 1. "RG,RG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x08 0.--9. 1. "RB,RB coefficient encoded signed value (from -512 to 511)" group.long 0x81C++0x0B line.long 0x00 "DISPC_CPR3_COEF_B,The register configures the color phase rotation matrix coefficients for the blue component" hexmask.long.word 0x00 22.--31. 1. "BR,BR coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "BG,BG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 0.--9. 1. "BB,BB coefficient Encoded signed value (from -512 to 511)" line.long 0x04 "DISPC_CPR3_COEF_G,The register configures the color phase rotation matrix coefficients for the green component" hexmask.long.word 0x04 22.--31. 1. "GR,GRcoefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 11.--20. 1. "GG,GG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 0.--9. 1. "GB,GB coefficient Encoded signed value (from -512 to 511)" line.long 0x08 "DISPC_CPR3_COEF_R,The register configures the color phase rotation matrix coefficients for the red component" hexmask.long.word 0x08 22.--31. 1. "RR,RR coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x08 11.--20. 1. "RG,RG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x08 0.--9. 1. "RB,RB coefficient Encoded signed value (from -512 to 511)" group.long 0x1D4++0x0B line.long 0x00 "DISPC_DATA1_CYCLE1,The control register configures the output data format for 1st cycle" bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x04 "DISPC_DATA1_CYCLE2,The control register configures the output data format for 2nd cycle" bitfld.long 0x04 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x04 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x04 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x04 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x08 "DISPC_DATA1_CYCLE3,The control register configures the output data format for 3rd cycle" bitfld.long 0x08 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x08 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x08 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x08 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" group.long 0x3C0++0x0B line.long 0x00 "DISPC_DATA2_CYCLE1,The control register configures the output data format for 1st cycle" bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x04 "DISPC_DATA2_CYCLE2,The control register configures the output data format for 2nd cycle" bitfld.long 0x04 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x04 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x04 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x04 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x08 "DISPC_DATA2_CYCLE3,The control register configures the output data format for 3rd cycle" bitfld.long 0x08 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x08 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x08 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x08 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" group.long 0x828++0x0B line.long 0x00 "DISPC_DATA3_CYCLE1,The control register configures the output data format for the first cycle" bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DISPC_DATA3_CYCLE2,The control register configures the output data format for the second cycle" bitfld.long 0x04 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "DISPC_DATA3_CYCLE3,The control register configures the output data format for the third cycle" bitfld.long 0x08 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C++0x07 line.long 0x00 "DISPC_DEFAULT_COLOR0,The control register allows to configure the default solid background color for the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x04 "DISPC_DEFAULT_COLOR1,The control register allows to configure the default solid background color for the TV output" hexmask.long.tbyte 0x04 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" group.long 0x3AC++0x03 line.long 0x00 "DISPC_DEFAULT_COLOR2,The control register allows to configure the default solid background color for the secondary LCD Shadow register. updated on VFP start period of secondary LCD" hexmask.long.tbyte 0x00 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" group.long 0x814++0x03 line.long 0x00 "DISPC_DEFAULT_COLOR3,The control register allows to configure the default solid background color for the third LCD" hexmask.long.tbyte 0x00 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" group.long 0x804++0x03 line.long 0x00 "DISPC_DIVISOR,The register configures the divisor value for generating the core functional clock" hexmask.long.byte 0x00 16.--23. 1. "LCD,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock" newline bitfld.long 0x00 0. "ENABLE,When the bit field is set to 1 the bit field LCD is used to generated the core functional clock from the input clock" "ENABLE_0,ENABLE_1" group.long 0x70++0x03 line.long 0x00 "DISPC_DIVISOR1,The register configures the divisors" hexmask.long.byte 0x00 16.--23. 1. "LCD,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK" newline hexmask.long.byte 0x00 0.--7. 1. "PCD,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value" group.long 0x40C++0x03 line.long 0x00 "DISPC_DIVISOR2,The register configures the divisors" hexmask.long.byte 0x00 16.--23. 1. "LCD,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK" newline hexmask.long.byte 0x00 0.--7. 1. "PCD,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value" group.long 0x838++0x03 line.long 0x00 "DISPC_DIVISOR3,The register configures the divisors" hexmask.long.byte 0x00 16.--23. 1. "LCD,Display controller logic clock divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on LCD2_CLK" newline hexmask.long.byte 0x00 0.--7. 1. "PCD,Pixel clock divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on LCD2_CLK divided by the value of DISPC_DIVISOR2.LCD" group.long 0x630++0x0B line.long 0x00 "DISPC_GAMMA_TABLE0,The register configures the look up table used as color look up table for BITMAP formats (1-. 2-. 4. and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output" hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit field VALUE is stored" newline hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" line.long 0x04 "DISPC_GAMMA_TABLE1,The register configures the gamma table on the secondary LCD output" hexmask.long.byte 0x04 24.--31. 1. "INDEX,Defines the location in the table where the bit field VALUE is stored" newline hexmask.long.byte 0x04 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x04 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x04 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" line.long 0x08 "DISPC_GAMMA_TABLE2,The register configures the gamma table on the TV output" bitfld.long 0x08 31. "INDEX,Setting this bit to 1 resets the internal index counter to zero" "INDEX_0,INDEX_1" newline hexmask.long.word 0x08 20.--29. 1. "VALUE_R,10-bit color component value to store in the table" newline hexmask.long.word 0x08 10.--19. 1. "VALUE_G,10-bit color component value to store in the table" newline hexmask.long.word 0x08 0.--9. 1. "VALUE_B,10-bit color component value to store in the table" group.long 0x850++0x03 line.long 0x00 "DISPC_GAMMA_TABLE3,The register configures the gamma table on the third LCD output" hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the VALUE bit field is stored" newline hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" newline hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" newline hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" group.long 0xA0++0x03 line.long 0x00 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "ANTIFLICKER,Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4 1/2 " "ANTIFLICKER_0,ANTIFLICKER_1" newline bitfld.long 0x00 18.--20. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 15. "SELFREFRESH,Enables the self refresh of the graphics window from its own DMA buffer" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 14. "ARBITRATION,Determines the priority of the graphics pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 12.--13. "ROTATION,Graphics rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "BUFPRELOAD,Graphics preload value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 10. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline bitfld.long 0x00 9. "NIBBLEMODE,Graphics nibble mode (only for 1- 2- and 4 bpp)NOTE: BITMAP formats and associated Nibble Mode are not supported in this family of devices" "NIBBLEMODE_0,NIBBLEMODE_1" newline bitfld.long 0x00 8. "CHANNELOUT,Graphics Channel Out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 6.--7. "BURSTSIZE,Graphics DMA burst size - Burst2x128" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 5. "REPLICATIONENABLE,Graphics replication enabled: RGB" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 1.--4. "FORMAT,Graphics format" "?,?,?,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Graphics enable - GraphicsDis" "ENABLE_0,ENABLE_1" rgroup.long 0xA8++0x03 line.long 0x00 "DISPC_GFX_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,DMA buffer size in number of 128 bits" group.long 0xA4++0x03 line.long 0x00 "DISPC_GFX_BUF_THRESHOLD,The register configures the graphics buffer" hexmask.long.word 0x00 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x00 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" group.long 0x860++0x03 line.long 0x00 "DISPC_GFX_MFLAG_THRESHOLD,MFLAG thresholds for graphics pipeline" hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" group.long 0xB0++0x03 line.long 0x00 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels" hexmask.long.byte 0x00 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" group.long 0x88++0x03 line.long 0x00 "DISPC_GFX_POSITION,The register configures the position of the graphics window" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the graphics window" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the graphics window" group.long 0x240++0x03 line.long 0x00 "DISPC_GFX_POSITION2,The register configures the position of the 2nd graphics window in FramePacking mode" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the 2nd graphics window" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the 2nd graphics window" group.long 0x22C++0x03 line.long 0x00 "DISPC_GFX_PRELOAD,The register configures the graphics DMA buffer Shadow register. updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software.." hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value number of 128-bit words defining the preload value" group.long 0xAC++0x03 line.long 0x00 "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row" group.long 0x8C++0x03 line.long 0x00 "DISPC_GFX_SIZE,The register configures the size of the graphics window" hexmask.long.word 0x00 16.--27. 1. "SIZEY,Number of lines of the graphics window" newline hexmask.long.word 0x00 0.--10. 1. "SIZEX,Number of pixels of the graphics window" group.long 0xB8++0x03 line.long 0x00 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer" group.long 0x74++0x03 line.long 0x00 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and three video pipelines" hexmask.long.byte 0x00 24.--31. 1. "VID3GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x00 16.--23. 1. "VID2GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x00 8.--15. 1. "VID1GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x00 0.--7. 1. "GFXGLOBALALPHA,Global alpha value from 0 to 255" group.long 0x800++0x03 line.long 0x00 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline (graphics. video1. video2. video3 and write-back)" bitfld.long 0x00 24.--29. "WB_BUFFER,Write-back DMA buffer allocation to one of the pipelines" "WB_BUFFER_0,?,?,?,?,?,?,?,?,WB_BUFFER_9,?,?,?,?,?,?,?,?,WB_BUFFER_18,?,?,?,?,?,?,?,?,WB_BUFFER_27,?,?,?,?,?,?,?,?,WB_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 18.--23. "VID3_BUFFER,Video3 DMA buffer allocation to one of the pipelines" "VID3_BUFFER_0,?,?,?,?,?,?,?,?,VID3_BUFFER_9,?,?,?,?,?,?,?,?,VID3_BUFFER_18,?,?,?,?,?,?,?,?,VID3_BUFFER_27,?,?,?,?,?,?,?,?,VID3_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 12.--17. "VID2_BUFFER,Video2 DMA buffer allocation to one of the pipelines" "VID2_BUFFER_0,?,?,?,?,?,?,?,?,VID2_BUFFER_9,?,?,?,?,?,?,?,?,VID2_BUFFER_18,?,?,?,?,?,?,?,?,VID2_BUFFER_27,?,?,?,?,?,?,?,?,VID2_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 6.--11. "VID1_BUFFER,Video1 DMA buffer allocation to one of the pipelines" "VID1_BUFFER_0,?,?,?,?,?,?,?,?,VID1_BUFFER_9,?,?,?,?,?,?,?,?,VID1_BUFFER_18,?,?,?,?,?,?,?,?,VID1_BUFFER_27,?,?,?,?,?,?,?,?,VID1_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0.--5. "GFX_BUFFER,Graphics DMA buffer allocation to one of the pipelines" "GFX_BUFFER_0,?,?,?,?,?,?,?,?,GFX_BUFFER_9,?,?,?,?,?,?,?,?,GFX_BUFFER_18,?,?,?,?,?,?,?,?,GFX_BUFFER_27,?,?,?,?,?,?,?,?,GFX_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x85C++0x03 line.long 0x00 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,Global MFLAG atrribute control register" bitfld.long 0x00 2. "MFLAG_START,MFLAG Start - Inactive" "MFLAG_START_0,MFLAG_START_1" newline bitfld.long 0x00 0.--1. "MFLAG_CTRL,MFLAG control - MFLAG_Dis" "MFLAG_CTRL_0,MFLAG_CTRL_1,MFLAG_CTRL_2,?" group.long 0x1C++0x03 line.long 0x00 "DISPC_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x00 31. "FLIPIMMEDIATEDONE_EN,Flip Immediate Done" "FLIPIMMEDIATEDONE_EN_0,FLIPIMMEDIATEDONE_EN_1" newline bitfld.long 0x00 30. "FRAME DONE3_EN,Frame done for the third LCD" "FRAME DONE3_EN_0,FRAME DONE3_EN_1" newline bitfld.long 0x00 29. "ACBIASCOUNT STATUS3_EN,AC Bias count status for the third LCD - masked" "ACBIASCOUNT STATUS3_EN_0,ACBIASCOUNT STATUS3_EN_1" newline bitfld.long 0x00 28. "VSYNC3_EN,Vertical synchronization for the third LCD - masked" "VSYNC3_EN_0,VSYNC3_EN_1" newline bitfld.long 0x00 27. "SYNC LOST3_EN,Synchronization lost on the third LCD output" "SYNC LOST3_EN_0,SYNC LOST3_EN_1" newline bitfld.long 0x00 26. "WBUNCOMPLETE ERROR_EN,The write back buffer has been flushed before been fully drained" "WBUNCOMPLETE ERROR_EN_0,WBUNCOMPLETE ERROR_EN_1" newline bitfld.long 0x00 25. "WBBUFFER OVERFLOW_EN,Write-back DMA buffer overflow" "WBBUFFER OVERFLOW_EN_0,WBBUFFER OVERFLOW_EN_1" newline bitfld.long 0x00 24. "FRAME DONETV_EN,Frame done for the TV" "FRAME DONETV_EN_0,FRAME DONETV_EN_1" newline bitfld.long 0x00 23. "FRAME DONEWB_EN,Frame done for the write-back channel" "FRAME DONEWB_EN_0,FRAME DONEWB_EN_1" newline bitfld.long 0x00 22. "FRAME DONE2_EN,Frame done for the secondary LCD" "FRAME DONE2_EN_0,FRAME DONE2_EN_1" newline bitfld.long 0x00 21. "ACBIASCOUNT STATUS2_EN,AC Bias count status for the secondary LCD - masked" "ACBIASCOUNT STATUS2_EN_0,ACBIASCOUNT STATUS2_EN_1" newline bitfld.long 0x00 20. "VID3BUFFER UNDERFLOW_EN,Video 3 DMA Buffer Underflow" "VID3BUFFER UNDERFLOW_EN_0,VID3BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x00 19. "VID3END WINDOW_EN,The end of the video 3 window has been reached" "VID3END WINDOW_EN_0,VID3END WINDOW_EN_1" newline bitfld.long 0x00 18. "VSYNC2_EN,Vertical synchronization for the secondary LCD - masked" "VSYNC2_EN_0,VSYNC2_EN_1" newline bitfld.long 0x00 17. "SYNC LOST2_EN,Synchronization lost on the secondary LCD output" "SYNC LOST2_EN_0,SYNC LOST2_EN_1" newline bitfld.long 0x00 16. "WAKEUP_EN,Wake up mask - masked" "WAKEUP_EN_0,WAKEUP_EN_1" newline bitfld.long 0x00 15. "SYNC LOSTTV_EN,Synchronization lost on the TV output" "SYNC LOSTTV_EN_0,SYNC LOSTTV_EN_1" newline bitfld.long 0x00 14. "SYNC LOST1_EN,Synchronization lost for the primary LCD - masked" "SYNC LOST1_EN_0,SYNC LOST1_EN_1" newline bitfld.long 0x00 13. "VID2END WINDOW_EN,The end of the video 2 Window has been reached" "VID2END WINDOW_EN_0,VID2END WINDOW_EN_1" newline bitfld.long 0x00 12. "VID2BUFFER UNDERFLOW_EN,Video 2 DMA buffer underflow" "VID2BUFFER UNDERFLOW_EN_0,VID2BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x00 11. "ENDVID1 WINDOW_EN,The end of the video 1 window has been reached" "ENDVID1 WINDOW_EN_0,ENDVID1 WINDOW_EN_1" newline bitfld.long 0x00 10. "VID1BUFFER UNDERFLOW_EN,Video 1 DMA buffer underflow" "VID1BUFFER UNDERFLOW_EN_0,VID1BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x00 9. "OCPERROR_EN,OCP Error" "OCPERROR_EN_0,OCPERROR_EN_1" newline bitfld.long 0x00 8. "PALETTE GAMMA_EN,Palette gamma loading mask" "PALETTE GAMMA_EN_0,PALETTE GAMMA_EN_1" newline bitfld.long 0x00 7. "GFXEND WINDOW_EN,The end of the graphics Window has been reached" "GFXEND WINDOW_EN_0,GFXEND WINDOW_EN_1" newline bitfld.long 0x00 6. "GFXBUFFER UNDERFLOW_EN,Graphics DMA Buffer Underflow" "GFXBUFFER UNDERFLOW_EN_0,GFXBUFFER UNDERFLOW_EN_1" newline bitfld.long 0x00 5. "PROGRAMMED LINENUMBER_EN,Programmed Line Number" "PROGRAMMED LINENUMBER_EN_0,PROGRAMMED LINENUMBER_EN_1" newline bitfld.long 0x00 4. "ACBIASCOUNT STATUS1_EN,AC Bias count status for the primary LCD - masked" "ACBIASCOUNT STATUS1_EN_0,ACBIASCOUNT STATUS1_EN_1" newline bitfld.long 0x00 3. "EVSYNC_ODD_EN,VSYNC for odd field from the TV encoder (HDMI) - masked" "EVSYNC_ODD_EN_0,EVSYNC_ODD_EN_1" newline bitfld.long 0x00 2. "EVSYNC_EVEN_EN,VSYNC for even field from the TV encoder (HDMI) - masked" "EVSYNC_EVEN_EN_0,EVSYNC_EVEN_EN_1" newline bitfld.long 0x00 1. "VSYNC1_EN,Vertical synchronization for the primary LCD" "VSYNC1_EN_0,VSYNC1_EN_1" newline bitfld.long 0x00 0. "FRAMEDONE_EN,Frame done for the primary LCD" "FRAMEDONE_EN_0,FRAMEDONE_EN_1" group.long 0x18++0x03 line.long 0x00 "DISPC_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" bitfld.long 0x00 31. "FLIPIMMEDIATEDONE_IRQ,Flip Immediate Done" "FLIPIMMEDIATEDONE_IRQ_0,FLIPIMMEDIATEDONE_IRQ_1" newline bitfld.long 0x00 30. "FRAMEDONE3_IRQ,Frame done for the third LCD" "FRAMEDONE3_IRQ_0,FRAMEDONE3_IRQ_1" newline bitfld.long 0x00 29. "ACBIASCOUNT STATUS3_IRQ,AC bias count status for the third LCD - False" "ACBIASCOUNT STATUS3_IRQ_0,ACBIASCOUNT STATUS3_IRQ_1" newline bitfld.long 0x00 28. "VSYNC3_IRQ,Vertical synchronization for the third LCD - False" "VSYNC3_IRQ_0,VSYNC3_IRQ_1" newline bitfld.long 0x00 27. "SYNCLOST3_IRQ,Synchronization lost on the third LCD output" "SYNCLOST3_IRQ_0,SYNCLOST3_IRQ_1" newline bitfld.long 0x00 26. "WBUNCOMPLETE ERROR_IRQ,Write-back DMA buffer is flushed before it is completely drained" "WBUNCOMPLETE ERROR_IRQ_0,WBUNCOMPLETE ERROR_IRQ_1" newline bitfld.long 0x00 25. "WBBUFFER OVERFLOW_IRQ,Write-back DMA buffer overflow" "WBBUFFER OVERFLOW_IRQ_0,WBBUFFER OVERFLOW_IRQ_1" newline bitfld.long 0x00 24. "FRAME DONETV_IRQ,Frame done for the TV" "FRAME DONETV_IRQ_0,FRAME DONETV_IRQ_1" newline bitfld.long 0x00 23. "FRAME DONEWB_IRQ,Frame done for the write-back channel" "FRAME DONEWB_IRQ_0,FRAME DONEWB_IRQ_1" newline bitfld.long 0x00 22. "FRAME DONE2_IRQ,Frame done for the secondary LCD" "FRAME DONE2_IRQ_0,FRAME DONE2_IRQ_1" newline bitfld.long 0x00 21. "ACBIASCOUNT STATUS2_IRQ,AC bias count status for the secondary LCD - False" "ACBIASCOUNT STATUS2_IRQ_0,ACBIASCOUNT STATUS2_IRQ_1" newline bitfld.long 0x00 20. "VID3BUFFER UNDERFLOW_IRQ,Video 3 DMA buffer underflow" "VID3BUFFER UNDERFLOW_IRQ_0,VID3BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x00 19. "VID3END WINDOW_IRQ,The end of the video 3 window has been reached" "VID3END WINDOW_IRQ_0,VID3END WINDOW_IRQ_1" newline bitfld.long 0x00 18. "VSYNC2_IRQ,Vertical synchronization for the secondary LCD - False" "VSYNC2_IRQ_0,VSYNC2_IRQ_1" newline bitfld.long 0x00 17. "SYNC LOST2_IRQ,Synchronization lost on the secondary LCD output" "SYNC LOST2_IRQ_0,SYNC LOST2_IRQ_1" newline bitfld.long 0x00 16. "WAKEUP_IRQ,Wakeup - False" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline bitfld.long 0x00 15. "SYNCLOST TV_IRQ,Synchronization lost on the TV output" "SYNCLOST TV_IRQ_0,SYNCLOST TV_IRQ_1" newline bitfld.long 0x00 14. "SYNC LOST1_IRQ,Synchronizationl ost on the primary LCD output" "SYNC LOST1_IRQ_0,SYNC LOST1_IRQ_1" newline bitfld.long 0x00 13. "VID2END WINDOW_IRQ,The end of the video 2 Window has been reached" "VID2END WINDOW_IRQ_0,VID2END WINDOW_IRQ_1" newline bitfld.long 0x00 12. "VID2BUFFER UNDERFLOW_IRQ,Video 2 DMA buffer underflow" "VID2BUFFER UNDERFLOW_IRQ_0,VID2BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x00 11. "VID1END WINDOW_IRQ,The end of the video 1 Window has been reached" "VID1END WINDOW_IRQ_0,VID1END WINDOW_IRQ_1" newline bitfld.long 0x00 10. "VID1BUFFER UNDERFLOW_IRQ,Video 1 DMA buffer underflow" "VID1BUFFER UNDERFLOW_IRQ_0,VID1BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x00 9. "OCPERROR_IRQ,OCP error" "OCPERROR_IRQ_0,OCPERROR_IRQ_1" newline bitfld.long 0x00 8. "PALETTEGAMMA LOADING_IRQ,Palette Gamma loading status" "PALETTEGAMMA LOADING_IRQ_0,PALETTEGAMMA LOADING_IRQ_1" newline bitfld.long 0x00 7. "GFXEND WINDOW_IRQ,The end of the graphics wndow has been reached" "GFXEND WINDOW_IRQ_0,GFXEND WINDOW_IRQ_1" newline bitfld.long 0x00 6. "GFXBUFFER UNDERFLOW_IRQ,Graphics DMA buffer underflow" "GFXBUFFER UNDERFLOW_IRQ_0,GFXBUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x00 5. "PROGRAMMED LINENUMBER_IRQ,Programmed line number" "PROGRAMMED LINENUMBER_IRQ_0,PROGRAMMED LINENUMBER_IRQ_1" newline bitfld.long 0x00 4. "ACBIASCOUNT STATUS1_IRQ,AC bias count status for the primary LCD - False" "ACBIASCOUNT STATUS1_IRQ_0,ACBIASCOUNT STATUS1_IRQ_1" newline bitfld.long 0x00 3. "EVSYNC_ ODD_IRQ,VSYNC for odd field from the TV encoder (HDMI) - False" "EVSYNC_ ODD_IRQ_0,EVSYNC_ ODD_IRQ_1" newline bitfld.long 0x00 2. "EVSYNC_ EVEN_IRQ,VSYNC for even field from the TV encoder (HDMI) - False" "EVSYNC_ EVEN_IRQ_0,EVSYNC_ EVEN_IRQ_1" newline bitfld.long 0x00 1. "VSYNC1_IRQ,Vertical synchronization for the primary LCD" "VSYNC1_IRQ_0,VSYNC1_IRQ_1" newline bitfld.long 0x00 0. "FRAME DONE1_IRQ,Frame done for the primary LCD" "FRAME DONE1_IRQ_0,FRAME DONE1_IRQ_1" group.long 0x60++0x03 line.long 0x00 "DISPC_LINE_NUMBER,The control register indicates the primary LCD panel display line number for the interrupt and the DMA request" hexmask.long.word 0x00 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" rgroup.long 0x5C++0x03 line.long 0x00 "DISPC_LINE_STATUS,The control register indicates the current primary LCD panel display line number" hexmask.long.word 0x00 0.--11. 1. "LINENUMBER,Current LCD panel line number Current display line number" group.long 0x6C++0x03 line.long 0x00 "DISPC_POL_FREQ1,The register configures the signal configuration" bitfld.long 0x00 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x00 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x00 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x00 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x00 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x00 8.--11. "ACBI,AC Bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "ACBI_0,ACBI_1,ACBI_2,ACBI_3,ACBI_4,ACBI_5,ACBI_6,ACBI_7,ACBI_8,ACBI_9,ACBI_10,ACBI_11,ACBI_12,ACBI_13,ACBI_14,ACBI_15" newline hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias pin frequency value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin" group.long 0x408++0x03 line.long 0x00 "DISPC_POL_FREQ2,The register configures the signal configuration" bitfld.long 0x00 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x00 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x00 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x00 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x00 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x00 8.--11. "ACBI,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "ACBI_0,ACBI_1,ACBI_2,ACBI_3,ACBI_4,ACBI_5,ACBI_6,ACBI_7,ACBI_8,ACBI_9,ACBI_10,ACBI_11,ACBI_12,ACBI_13,ACBI_14,ACBI_15" newline hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin" group.long 0x83C++0x03 line.long 0x00 "DISPC_POL_FREQ3,The register configures the signal configuration" bitfld.long 0x00 18. "ALIGN,Defines the alignment betwwen HSYNC and VSYNC assertion - notAligned" "ALIGN_0,ALIGN_1" newline bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC pixel clock control on/off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC rise or fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x00 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x00 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x00 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x00 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x00 8.--11. "ACBI,AC bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "ACB,AC bias pin frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin" rgroup.long 0x00++0x03 line.long 0x00 "DISPC_REVISION,IP Revision" group.long 0x7C++0x03 line.long 0x00 "DISPC_SIZE_LCD1,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x00 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x00 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x00 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1)" group.long 0x3CC++0x03 line.long 0x00 "DISPC_SIZE_LCD2,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x00 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x00 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x00 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1)" group.long 0x834++0x03 line.long 0x00 "DISPC_SIZE_LCD3,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x00 16.--27. 1. "LPP,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x00 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x00 0.--11. 1. "PPL,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contained within each line on the display (program to value minus 1)" group.long 0x78++0x03 line.long 0x00 "DISPC_SIZE_TV,The register configures the size of the TV output field (interlace). frame (progressive) (horizontal and vertical)" hexmask.long.word 0x00 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel" newline bitfld.long 0x00 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x00 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display" group.long 0x10++0x07 line.long 0x00 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface" bitfld.long 0x00 12.--13. "MIDLEMODE,Master interface power management standby/wait control - fStandBy" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period - OCPFuncOff" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" newline bitfld.long 0x00 5. "WARMRESET,Warm reset" "WARMRESET_0,WARMRESET_1" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control - fIdle" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x00 2. "ENWAKEUP,WakeUp feature control - WakeUpDis" "ENWAKEUP_0,ENWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock gating strategy - ClkFree" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "DISPC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - rstongoing" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x64++0x03 line.long 0x00 "DISPC_TIMING_H1,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x00 20.--31. 1. "HBP,Horizontal Back Porch" newline hexmask.long.word 0x00 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x00 0.--7. 1. "HSW,Horizontal synchronization pulse width" group.long 0x400++0x03 line.long 0x00 "DISPC_TIMING_H2,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x00 20.--31. 1. "HBP,Horizontal back porch" newline hexmask.long.word 0x00 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x00 0.--7. 1. "HSW,Horizontal synchronization pulse width" group.long 0x840++0x03 line.long 0x00 "DISPC_TIMING_H3,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x00 20.--31. 1. "HBP,Horizontal back porch" newline hexmask.long.word 0x00 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x00 0.--7. 1. "HSW,Horizontal synchronization pulse width" group.long 0x68++0x03 line.long 0x00 "DISPC_TIMING_V1,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x00 20.--31. 1. "VBP,Vertical back porch" newline hexmask.long.word 0x00 8.--19. 1. "VFP,Vertical front porch" newline hexmask.long.byte 0x00 0.--7. 1. "VSW,Vertical synchronization pulse width" group.long 0x404++0x03 line.long 0x00 "DISPC_TIMING_V2,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x00 20.--31. 1. "VBP,Vertical back porch" newline hexmask.long.word 0x00 8.--19. 1. "VFP,Vertical front porch" newline hexmask.long.byte 0x00 0.--7. 1. "VSW,Vertical synchronization pulse width" group.long 0x844++0x03 line.long 0x00 "DISPC_TIMING_V3,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x00 20.--31. 1. "VBP,Vertical back porch" newline hexmask.long.word 0x00 8.--19. 1. "VFP,Vertical front porch" newline hexmask.long.byte 0x00 0.--7. 1. "VSW,Vertical synchronization pulse width" group.long 0x54++0x07 line.long 0x00 "DISPC_TRANS_COLOR0,The register sets the transparency color value for the video/graphics overlays for the primary LCD output" hexmask.long.tbyte 0x00 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." line.long 0x04 "DISPC_TRANS_COLOR1,The register sets the transparency color value for the video/graphics overlays for the TV output" hexmask.long.tbyte 0x04 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." group.long 0x3B0++0x03 line.long 0x00 "DISPC_TRANS_COLOR2,The register sets the transparency color value for the video/graphics overlays for the secondary LCD output" hexmask.long.tbyte 0x00 0.--23. 1. "TRANSCOLORKEY,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." group.long 0x818++0x03 line.long 0x00 "DISPC_TRANS_COLOR3,The register sets the transparency color value for the video/graphics overlays for the third LCD output" hexmask.long.tbyte 0x00 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." group.long 0xCC++0x03 line.long 0x00 "DISPC_VID1_ATTRIBUTES,The register configures the attributes of the video window 1" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPHYALPHA,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPHYALPHA_0,PREMULTIPHYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video vertical resize tap number" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "CHANNELOUT,Video channel out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 12.--13. "ROTATION,Video rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "REPLICATIONENABLE,Replication enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x00 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Video Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Video Enable - VideoDis" "ENABLE_0,ENABLE_1" group.long 0x624++0x03 line.long 0x00 "DISPC_VID1_ATTRIBUTES2,The register configures the attributes of the video window 1" bitfld.long 0x00 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x00 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x00 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" rgroup.long 0xD4++0x03 line.long 0x00 "DISPC_VID1_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline 1" hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video 1 DMA buffer size in number of 128-bits" group.long 0xD0++0x03 line.long 0x00 "DISPC_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline 1" hexmask.long.word 0x00 16.--31. 1. "BUFHIGHTHRESHOLD,Video DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x00 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" group.long 0x130++0x13 line.long 0x00 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x00 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x04 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x08 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x0C 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x10 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" group.long 0xE0++0x03 line.long 0x00 "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter" group.long 0x63C++0x03 line.long 0x00 "DISPC_VID1_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x864++0x03 line.long 0x00 "DISPC_VID1_MFLAG_THRESHOLD,MFLAG thresholds for video1 pipeline" hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" group.long 0xE4++0x03 line.long 0x00 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 1 before up/down-scaling" hexmask.long.word 0x00 16.--27. 1. "MEMSIZEY,Number of lines of the video picture" newline hexmask.long.word 0x00 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" group.long 0xDC++0x03 line.long 0x00 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2" hexmask.long.byte 0x00 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" group.long 0xC4++0x03 line.long 0x00 "DISPC_VID1_POSITION,The register configures the position of the video window 1" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1" group.long 0x244++0x03 line.long 0x00 "DISPC_VID1_POSITION2,The register configures the position of the 2nd video window #1 in FramePacking mode" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the X position of the video window #1" group.long 0x230++0x03 line.long 0x00 "DISPC_VID1_PRELOAD,The register configures the DMA buffer of the video 1 pipeline" hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value number of 128-bit words defining the preload value" group.long 0xD8++0x03 line.long 0x00 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1" group.long 0xC8++0x03 line.long 0x00 "DISPC_VID1_SIZE,The register configures the size of the video window 1" hexmask.long.word 0x00 16.--27. 1. "SIZEY,Number of lines of the video 1 Encoded value (from 1 to 4096) to specify the number of lines of the video window 1" newline hexmask.long.word 0x00 0.--10. 1. "SIZEX,Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1" group.long 0x15C++0x03 line.long 0x00 "DISPC_VID2_ATTRIBUTES,The register configures the attributes of the video window 2" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "CHANNELOUT,Video Channel Out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 12.--13. "ROTATION,Video Rotation Flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "REPLICATIONENABLE,Replication Enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x00 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Video Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,VidEnable - VideoDis" "ENABLE_0,ENABLE_1" group.long 0x628++0x03 line.long 0x00 "DISPC_VID2_ATTRIBUTES2,The register configures the attributes of the video window 2" bitfld.long 0x00 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x00 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x00 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" rgroup.long 0x164++0x03 line.long 0x00 "DISPC_VID2_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 2" hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,DMA buffer size in number of 128 bits" group.long 0x160++0x03 line.long 0x00 "DISPC_VID2_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 2" hexmask.long.word 0x00 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x00 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" group.long 0x1C0++0x13 line.long 0x00 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x00 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x04 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x08 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x0C 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x10 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" group.long 0x170++0x03 line.long 0x00 "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" group.long 0x6A8++0x03 line.long 0x00 "DISPC_VID2_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x868++0x03 line.long 0x00 "DISPC_VID2_MFLAG_THRESHOLD,MFLAG thresholds for video2 pipeline" hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" group.long 0x174++0x03 line.long 0x00 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 2 before up/down-scaling" hexmask.long.word 0x00 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1)" newline hexmask.long.word 0x00 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" group.long 0x16C++0x03 line.long 0x00 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2" hexmask.long.byte 0x00 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" group.long 0x154++0x03 line.long 0x00 "DISPC_VID2_POSITION,The register configures the position of the video window 2" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the video window 2 encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the video window 2 encoded value (from 0 to 2047) to specify the X position of the video window 2" group.long 0x248++0x03 line.long 0x00 "DISPC_VID2_POSITION2,The register configures the position of the 2nd video window #2 in FramePacking mode" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2" group.long 0x234++0x03 line.long 0x00 "DISPC_VID2_PRELOAD,The register configures the DMA buffer of the video 2 pipeline" hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" group.long 0x168++0x03 line.long 0x00 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2" group.long 0x158++0x03 line.long 0x00 "DISPC_VID2_SIZE,The register configures the size of the video window 2" hexmask.long.word 0x00 16.--27. 1. "SIZEY,Number of lines of the video 2 encoded value (from 1 to 4096) to specify the number of lines of the video window 2" newline hexmask.long.word 0x00 0.--10. 1. "SIZEX,Number of pixels of the video window 2 encoded value (from 1 to 2048) to specify the number of pixels of the video window 2" group.long 0x370++0x03 line.long 0x00 "DISPC_VID3_ATTRIBUTES,The register configures the attributes of the video window 3" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video vertical resize tap number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "CHANNELOUT,Video channel out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 12.--13. "ROTATION,Video rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "REPLICATIONENABLE,Replication enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x00 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Video resize enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Video format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Video Enable - VideoDis" "ENABLE_0,ENABLE_1" group.long 0x62C++0x03 line.long 0x00 "DISPC_VID3_ATTRIBUTES2,The register configures the attributes of the video window 3" bitfld.long 0x00 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x00 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x00 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" rgroup.long 0x388++0x07 line.long 0x00 "DISPC_VID3_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 3" hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128 bits" line.long 0x04 "DISPC_VID3_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 3" hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" group.long 0x374++0x13 line.long 0x00 "DISPC_VID3_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x00 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_VID3_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x04 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID3_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x08 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID3_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x0C 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID3_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x10 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" group.long 0x390++0x03 line.long 0x00 "DISPC_VID3_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" group.long 0x724++0x03 line.long 0x00 "DISPC_VID3_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x86C++0x03 line.long 0x00 "DISPC_VID3_MFLAG_THRESHOLD,MFLAG thresholds for video3 pipeline" hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" group.long 0x394++0x0B line.long 0x00 "DISPC_VID3_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 3 before up/down-scaling" hexmask.long.word 0x00 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1)" newline hexmask.long.word 0x00 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" line.long 0x04 "DISPC_VID3_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3" hexmask.long.byte 0x04 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x08 "DISPC_VID3_POSITION,The register configures the position of the video window 3" hexmask.long.word 0x08 16.--26. 1. "POSY,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x08 0.--10. 1. "POSX,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2" group.long 0x24C++0x03 line.long 0x00 "DISPC_VID3_POSITION2,The register configures the position of the 2nd video window #3 in FramePacking mode" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2" group.long 0x3A0++0x0B line.long 0x00 "DISPC_VID3_PRELOAD,The register configures the DMA buffer of the video 3 pipeline" hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x04 "DISPC_VID3_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3" line.long 0x08 "DISPC_VID3_SIZE,The register configures the size of the video window 3" hexmask.long.word 0x08 16.--27. 1. "SIZEY,Number of lines of the video 3 Encoded value (from 1 to 4096) to specify the number of lines of the video window 3" newline hexmask.long.word 0x08 0.--10. 1. "SIZEX,Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3" group.long 0x570++0x03 line.long 0x00 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline" bitfld.long 0x00 28.--31. "IDLENUMBER,Determines the number of idles between requests on the L3_MAIN interconnect" "IDLENUMBER_0,IDLENUMBER_1,IDLENUMBER_2,IDLENUMBER_3,IDLENUMBER_4,IDLENUMBER_5,IDLENUMBER_6,IDLENUMBER_7,IDLENUMBER_8,IDLENUMBER_9,IDLENUMBER_10,IDLENUMBER_11,IDLENUMBER_12,IDLENUMBER_13,IDLENUMBER_14,IDLENUMBER_15" newline bitfld.long 0x00 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "IDLESIZE_0,IDLESIZE_1" newline bitfld.long 0x00 24.--26. "CAPTUREMODE,Defines the frame rate capture" "CAPTUREMODE_0,CAPTUREMODE_1,CAPTUREMODE_2,CAPTUREMODE_3,CAPTUREMODE_4,CAPTUREMODE_5,CAPTUREMODE_6,CAPTUREMODE_7" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the write-back pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel" "Capture mode (default mode),Memory-to-memory mode" newline bitfld.long 0x00 16.--18. "CHANNELIN,Video Channel In configuration WR: immediate - Vid3" "CHANNELIN_0,CHANNELIN_1,CHANNELIN_2,CHANNELIN_3,CHANNELIN_4,CHANNELIN_5,CHANNELIN_6,CHANNELIN_7" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Write-back DMA Burst Size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "TRUNCATIONENABLE,It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32" "TRUNCATIONENABLE_0,TRUNCATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 7. "ALPHAENABLE,Premultiplied alpha enable" "The alpha value is not written back,The WB pipe copies back to memory the.." newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Write-back format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Write-back enable" "ENABLE_0,ENABLE_1" group.long 0x810++0x03 line.long 0x00 "DISPC_WB_ATTRIBUTES2,The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode" hexmask.long.byte 0x00 0.--7. 1. "WBDELAYCOUNT,Delays the WB pipe flush after the end of the frame" rgroup.long 0x588++0x07 line.long 0x00 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline" hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128 bits" line.long 0x04 "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline" hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" group.long 0x574++0x13 line.long 0x00 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24)" hexmask.long.word 0x00 16.--26. 1. "YG,YG coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "YR,YR coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x04 16.--26. 1. "CRR,CrR coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "YB,YB coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x08 16.--26. 1. "CRB,CrB coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "CRG,CrG coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x0C 16.--26. 1. "CBG,CbG coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "CBR,CbR coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x10 0.--10. 1. "CBB,CbB coefficient encoded signed value (from -1024 to 1023)" group.long 0x590++0x03 line.long 0x00 "DISPC_WB_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" group.long 0x790++0x03 line.long 0x00 "DISPC_WB_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x870++0x03 line.long 0x00 "DISPC_WB_MFLAG_THRESHOLD,MFLAG thresholds for write-back pipeline" hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" group.long 0x594++0x07 line.long 0x00 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling" hexmask.long.word 0x00 16.--27. 1. "MEMSIZEY,Number of lines of the wb picture in memory" newline hexmask.long.word 0x00 0.--10. 1. "MEMSIZEX,Number of pixels of the wb picture in memory" line.long 0x04 "DISPC_WB_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline" hexmask.long.byte 0x04 0.--7. 1. "PIXELINC,Values other than 1 are invalid" group.long 0x5A4++0x07 line.long 0x00 "DISPC_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline" line.long 0x04 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline" hexmask.long.word 0x04 16.--27. 1. "SIZEY,Number of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" newline hexmask.long.word 0x04 0.--10. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture from overlay or pipeline" width 0x0B tree.end tree "Display_Subsystem_Overview" tree "DPLL_HDMI_L3_MAIN" base ad:0x58040200 group.long 0x00++0x23 line.long 0x00 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESETN,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESETN_0,HSDIV_SYSRESETN_1" bitfld.long 0x00 3. "PLL_SYSRESETN,Force SYSRESETN" "PLL_SYSRESETN_0,PLL_SYSRESETN_1" line.long 0x04 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_INACT" "SSC_EN_ACK_0,SSC_EN_ACK_1" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on HDMI_PHY - BYPASS_ACK" "BYPASSACKZ_MERGED_0,BYPASSACKZ_MERGED_1" bitfld.long 0x04 6. "PLL_BYPASS,DPLL_HDMI Bypass status - BYPASS_IN" "PLL_BYPASS_0,PLL_BYPASS_1" newline bitfld.long 0x04 5. "PLL_HIGHJITTER,DPLL_HDMI High Jitter status - NORMAL_JITTER" "PLL_HIGHJITTER_0,PLL_HIGHJITTER_1" bitfld.long 0x04 3. "PLL_LOSSREF,DPLL_HDMI Reference Loss status - REF_INP_ACT" "PLL_LOSSREF_0,PLL_LOSSREF_1" bitfld.long 0x04 2. "PLL_RECAL,DPLL_HDMI re-calibration status If this bit is active the DPLL_HDMI needs to be re-calibrated - RECAL_NOT_REQUIRED" "PLL_RECAL_0,PLL_RECAL_1" newline bitfld.long 0x04 1. "PLL_LOCK,DPLL_HDMI Lock status See the programming guide for the use of this bit - DSI_PLL_NOLOCK" "PLL_LOCK_0,PLL_LOCK_1" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,DPLL_HDMI reset done status - NOTRD" "PLLCTRL_RESET_DONE_0,PLLCTRL_RESET_DONE_1" line.long 0x08 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the DPLL_HDMI" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for DPLL_HDMI" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for DPLL_HDMI (Reference)" line.long 0x10 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_NORMAL" "HSDIVBYPASS_0,HSDIVBYPASS_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - CLK_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_CLK_DIS" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,DPLL_HDMI reference clock control - REF_DIS" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" newline bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_REF" "PLL_CLKSEL_0,PLL_CLKSEL_1" bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the DPLL_HDMI - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,DPLL_HDMI DRIFTGUARDEN - DRIFT_GUARD_DIS" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,DPLL_HDMI LOW CURRENT STANDBY - LOWCURRSTBY_NOTSEL" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the DPLL_HDMI - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_HDMI" "?,?,PLL_SELFREQDCO_2,?,PLL_SELFREQDCO_4,?,?,?" newline bitfld.long 0x10 0. "PLL_IDLE,DPLL_HDMI IDLE: - IDLE_NOTSEL" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x14 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration" line.long 0x18 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_OFF" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLLCTRL_HDMI_SSC_CONFIGURATION2,Note: SSC feature is not supported" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for dithering" line.long 0x20 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure DPLL_HDMI M2 divider factor" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLL_HDMI_L4_CFG" base ad:0x4A0A6000 group.long 0x00++0x23 line.long 0x00 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESETN,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESETN_0,HSDIV_SYSRESETN_1" bitfld.long 0x00 3. "PLL_SYSRESETN,Force SYSRESETN" "PLL_SYSRESETN_0,PLL_SYSRESETN_1" line.long 0x04 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_INACT" "SSC_EN_ACK_0,SSC_EN_ACK_1" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on HDMI_PHY - BYPASS_ACK" "BYPASSACKZ_MERGED_0,BYPASSACKZ_MERGED_1" bitfld.long 0x04 6. "PLL_BYPASS,DPLL_HDMI Bypass status - BYPASS_IN" "PLL_BYPASS_0,PLL_BYPASS_1" newline bitfld.long 0x04 5. "PLL_HIGHJITTER,DPLL_HDMI High Jitter status - NORMAL_JITTER" "PLL_HIGHJITTER_0,PLL_HIGHJITTER_1" bitfld.long 0x04 3. "PLL_LOSSREF,DPLL_HDMI Reference Loss status - REF_INP_ACT" "PLL_LOSSREF_0,PLL_LOSSREF_1" bitfld.long 0x04 2. "PLL_RECAL,DPLL_HDMI re-calibration status If this bit is active the DPLL_HDMI needs to be re-calibrated - RECAL_NOT_REQUIRED" "PLL_RECAL_0,PLL_RECAL_1" newline bitfld.long 0x04 1. "PLL_LOCK,DPLL_HDMI Lock status See the programming guide for the use of this bit - DSI_PLL_NOLOCK" "PLL_LOCK_0,PLL_LOCK_1" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,DPLL_HDMI reset done status - NOTRD" "PLLCTRL_RESET_DONE_0,PLLCTRL_RESET_DONE_1" line.long 0x08 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the DPLL_HDMI" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for DPLL_HDMI" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for DPLL_HDMI (Reference)" line.long 0x10 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_NORMAL" "HSDIVBYPASS_0,HSDIVBYPASS_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - CLK_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_CLK_DIS" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,DPLL_HDMI reference clock control - REF_DIS" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" newline bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_REF" "PLL_CLKSEL_0,PLL_CLKSEL_1" bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the DPLL_HDMI - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,DPLL_HDMI DRIFTGUARDEN - DRIFT_GUARD_DIS" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,DPLL_HDMI LOW CURRENT STANDBY - LOWCURRSTBY_NOTSEL" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the DPLL_HDMI - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_HDMI" "?,?,PLL_SELFREQDCO_2,?,PLL_SELFREQDCO_4,?,?,?" newline bitfld.long 0x10 0. "PLL_IDLE,DPLL_HDMI IDLE: - IDLE_NOTSEL" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x14 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration" line.long 0x18 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_OFF" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLLCTRL_HDMI_SSC_CONFIGURATION2,Note: SSC feature is not supported" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for dithering" line.long 0x20 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure DPLL_HDMI M2 divider factor" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLL_VIDEO1_L3_MAIN" base ad:0x58004300 group.long 0x00++0x23 line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" newline bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" newline bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" newline bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x04 11. "M7_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "M7_CLOCK_ACK_0_r,M7_CLOCK_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" newline bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" newline bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" newline hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 25. "M7_CLOCK_EN,Enable for M7 clock source" "M7_CLOCK_EN_0,M7_CLOCK_EN_1" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" newline bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" newline bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" newline bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 5.--9. "M7_CLOCK_DIV,Divider value for M7 divider" "M7_CLOCK_DIV_0,M7_CLOCK_DIV_1,M7_CLOCK_DIV_2,M7_CLOCK_DIV_3,M7_CLOCK_DIV_4,M7_CLOCK_DIV_5,M7_CLOCK_DIV_6,M7_CLOCK_DIV_7,M7_CLOCK_DIV_8,M7_CLOCK_DIV_9,M7_CLOCK_DIV_10,M7_CLOCK_DIV_11,M7_CLOCK_DIV_12,M7_CLOCK_DIV_13,M7_CLOCK_DIV_14,M7_CLOCK_DIV_15,M7_CLOCK_DIV_16,M7_CLOCK_DIV_17,M7_CLOCK_DIV_18,M7_CLOCK_DIV_19,M7_CLOCK_DIV_20,M7_CLOCK_DIV_21,M7_CLOCK_DIV_22,M7_CLOCK_DIV_23,M7_CLOCK_DIV_24,M7_CLOCK_DIV_25,M7_CLOCK_DIV_26,M7_CLOCK_DIV_27,M7_CLOCK_DIV_28,M7_CLOCK_DIV_29,M7_CLOCK_DIV_30,M7_CLOCK_DIV_31" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "Spread Spectrum Clocking disabled,Spread Spectrum Clocking enabled" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" newline hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x20 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure PLL REGM2" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLL_VIDEO1_L4_CFG" base ad:0x4A0A4000 group.long 0x00++0x23 line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" newline bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" newline bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" newline bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x04 11. "M7_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "M7_CLOCK_ACK_0_r,M7_CLOCK_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" newline bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" newline bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" newline hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 25. "M7_CLOCK_EN,Enable for M7 clock source" "M7_CLOCK_EN_0,M7_CLOCK_EN_1" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" newline bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" newline bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" newline bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 5.--9. "M7_CLOCK_DIV,Divider value for M7 divider" "M7_CLOCK_DIV_0,M7_CLOCK_DIV_1,M7_CLOCK_DIV_2,M7_CLOCK_DIV_3,M7_CLOCK_DIV_4,M7_CLOCK_DIV_5,M7_CLOCK_DIV_6,M7_CLOCK_DIV_7,M7_CLOCK_DIV_8,M7_CLOCK_DIV_9,M7_CLOCK_DIV_10,M7_CLOCK_DIV_11,M7_CLOCK_DIV_12,M7_CLOCK_DIV_13,M7_CLOCK_DIV_14,M7_CLOCK_DIV_15,M7_CLOCK_DIV_16,M7_CLOCK_DIV_17,M7_CLOCK_DIV_18,M7_CLOCK_DIV_19,M7_CLOCK_DIV_20,M7_CLOCK_DIV_21,M7_CLOCK_DIV_22,M7_CLOCK_DIV_23,M7_CLOCK_DIV_24,M7_CLOCK_DIV_25,M7_CLOCK_DIV_26,M7_CLOCK_DIV_27,M7_CLOCK_DIV_28,M7_CLOCK_DIV_29,M7_CLOCK_DIV_30,M7_CLOCK_DIV_31" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "Spread Spectrum Clocking disabled,Spread Spectrum Clocking enabled" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" newline hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x20 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure PLL REGM2" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLL_VIDEO2_L3_MAIN" base ad:0x58009300 group.long 0x00++0x23 line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" newline bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" newline bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" newline bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x04 11. "M7_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "M7_CLOCK_ACK_0_r,M7_CLOCK_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" newline bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" newline bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" newline hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 25. "M7_CLOCK_EN,Enable for M7 clock source" "M7_CLOCK_EN_0,M7_CLOCK_EN_1" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" newline bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" newline bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" newline bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 5.--9. "M7_CLOCK_DIV,Divider value for M7 divider" "M7_CLOCK_DIV_0,M7_CLOCK_DIV_1,M7_CLOCK_DIV_2,M7_CLOCK_DIV_3,M7_CLOCK_DIV_4,M7_CLOCK_DIV_5,M7_CLOCK_DIV_6,M7_CLOCK_DIV_7,M7_CLOCK_DIV_8,M7_CLOCK_DIV_9,M7_CLOCK_DIV_10,M7_CLOCK_DIV_11,M7_CLOCK_DIV_12,M7_CLOCK_DIV_13,M7_CLOCK_DIV_14,M7_CLOCK_DIV_15,M7_CLOCK_DIV_16,M7_CLOCK_DIV_17,M7_CLOCK_DIV_18,M7_CLOCK_DIV_19,M7_CLOCK_DIV_20,M7_CLOCK_DIV_21,M7_CLOCK_DIV_22,M7_CLOCK_DIV_23,M7_CLOCK_DIV_24,M7_CLOCK_DIV_25,M7_CLOCK_DIV_26,M7_CLOCK_DIV_27,M7_CLOCK_DIV_28,M7_CLOCK_DIV_29,M7_CLOCK_DIV_30,M7_CLOCK_DIV_31" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "Spread Spectrum Clocking disabled,Spread Spectrum Clocking enabled" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" newline hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x20 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure PLL REGM2" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLL_VIDEO2_L4_CFG" base ad:0x4A0A5000 group.long 0x00++0x23 line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" newline bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" newline bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" newline bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x04 11. "M7_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "M7_CLOCK_ACK_0_r,M7_CLOCK_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" newline bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" newline bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" newline hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 25. "M7_CLOCK_EN,Enable for M7 clock source" "M7_CLOCK_EN_0,M7_CLOCK_EN_1" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" newline bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" newline bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" newline bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 5.--9. "M7_CLOCK_DIV,Divider value for M7 divider" "M7_CLOCK_DIV_0,M7_CLOCK_DIV_1,M7_CLOCK_DIV_2,M7_CLOCK_DIV_3,M7_CLOCK_DIV_4,M7_CLOCK_DIV_5,M7_CLOCK_DIV_6,M7_CLOCK_DIV_7,M7_CLOCK_DIV_8,M7_CLOCK_DIV_9,M7_CLOCK_DIV_10,M7_CLOCK_DIV_11,M7_CLOCK_DIV_12,M7_CLOCK_DIV_13,M7_CLOCK_DIV_14,M7_CLOCK_DIV_15,M7_CLOCK_DIV_16,M7_CLOCK_DIV_17,M7_CLOCK_DIV_18,M7_CLOCK_DIV_19,M7_CLOCK_DIV_20,M7_CLOCK_DIV_21,M7_CLOCK_DIV_22,M7_CLOCK_DIV_23,M7_CLOCK_DIV_24,M7_CLOCK_DIV_25,M7_CLOCK_DIV_26,M7_CLOCK_DIV_27,M7_CLOCK_DIV_28,M7_CLOCK_DIV_29,M7_CLOCK_DIV_30,M7_CLOCK_DIV_31" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "Spread Spectrum Clocking disabled,Spread Spectrum Clocking enabled" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" newline hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x20 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure PLL REGM2" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DSI1_A_L3_MAIN" base ad:0x58004000 group.long 0x54++0x03 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION" bitfld.long 0x00 30.--31. "PLL_PWR_CMD,Command for power control of the DSI PLL Control Module" "Command to change to OFF state,Command to change to ON state for PLL only..,Command to change to ON state for both PLL and..,Command to change to ON state for both PLL and.." bitfld.long 0x00 28.--29. "PLL_PWR_STATUS,Status of the power control of the DSI PLL Control module" "DSI PLL Control module in OFF state,DSI PLL Control module in ON state for PLL only..,DSI PLL Control module in ON state for both PLL..,DSI PLL Control module in ON state for both PLL.." newline bitfld.long 0x00 14. "CIO_CLK_ICG,Gates SCPClk clock provided to DSI-PHY and PLL-CTRL module" "Disabled,Enabled" width 0x0B tree.end tree "DSI1_C_L3_MAIN" base ad:0x58009000 group.long 0x54++0x03 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION" bitfld.long 0x00 30.--31. "PLL_PWR_CMD,Command for power control of the DSI PLL Control Module" "Command to change to OFF state,Command to change to ON state for PLL only..,Command to change to ON state for both PLL and..,Command to change to ON state for both PLL and.." bitfld.long 0x00 28.--29. "PLL_PWR_STATUS,Status of the power control of the DSI PLL Control module" "DSI PLL Control module in OFF state,DSI PLL Control module in ON state for PLL only..,DSI PLL Control module in ON state for both PLL..,DSI PLL Control module in ON state for both PLL.." newline bitfld.long 0x00 14. "CIO_CLK_ICG,Gates SCPClk clock provided to DSI-PHY and PLL-CTRL module" "Disabled,Enabled" width 0x0B tree.end tree "DSS_L3_MAIN" base ad:0x58000000 rgroup.long 0x00++0x03 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number" rgroup.long 0x14++0x03 line.long 0x00 "DSS_SYSSTATUS,This register provides status information about the module" bitfld.long 0x00 0. "RESETDONE,Internal reset monitoring - rstact" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x40++0x03 line.long 0x00 "DSS_CTRL,This register contains the DSS control bits" bitfld.long 0x00 19. "LCD3_CLK_SWITCH,DSS_CLK/DPLL_DSI1_C_CLK1 clock switch (multiplexer 10) Selects the clock source for the DISPC LCD3_CLK clock - DSS_CLK_Sel" "LCD3_CLK_SWITCH_0,LCD3_CLK_SWITCH_1" bitfld.long 0x00 16.--17. "PARALLEL_SEL,Selection between LCD1 LCD2 LCD3 and TV channel out on the parallel output (multiplexer" "PARALLEL_SEL_0,PARALLEL_SEL_1,PARALLEL_SEL_2,PARALLEL_SEL_3" bitfld.long 0x00 12. "LCD2_CLK_SWITCH,DSS_CLK clock switch (multiplexer 3) Selects the clock source for the DISPC LCD2_CLK clock - DSS_CLK_Sel" "LCD2_CLK_SWITCH_0,LCD2_CLK_SWITCH_1" newline bitfld.long 0x00 7.--9. "F_CLK_SWITCH,Selects the clock source for the DISPC functional clock F_CLK" "F_CLK_SWITCH_0,F_CLK_SWITCH_1,F_CLK_SWITCH_2,F_CLK_SWITCH_3,F_CLK_SWITCH_4,?,?,?" bitfld.long 0x00 0. "LCD1_CLK_SWITCH,DSS_CLK/DPLL_DSI1_A_CLK1 clock switch (multiplexer 2) Selects the clock source for the DISPC LCD1_CLK clock - DSS_CLK_Sel" "LCD1_CLK_SWITCH_0,LCD1_CLK_SWITCH_1" rgroup.long 0x5C++0x03 line.long 0x00 "DSS_STATUS,This register contains the DSS status" bitfld.long 0x00 24.--25. "LCD3_CLK_STATUS,LCD3_CLK clock selection status (multiplexer 10) indicates which clock is used by the glitch free mux selecting the source of LCD3_CLK" "LCD3_CLK_STATUS_0_r,LCD3_CLK_STATUS_1_r,LCD3_CLK_STATUS_2_r,?" bitfld.long 0x00 15.--19. "F_CLK_STATUS,F_CLK clock selection status (multiplexer 1) indicates which clock is used by the glitch free mux selecting the source of F_CLK" "F_CLK_STATUS_0_r,F_CLK_STATUS_1_r,F_CLK_STATUS_2_r,?,F_CLK_STATUS_4_r,?,?,?,F_CLK_STATUS_8_r,?,?,?,?,?,?,?,F_CLK_STATUS_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 11.--12. "LCD2_CLK_STATUS,LCD2_CLK clock selection status (multiplexer 3) indicates which clock is used by the glitch free mux selecting the source of LCD2_CLK" "LCD2_CLK_STATUS_0_r,LCD2_CLK_STATUS_1_r,LCD2_CLK_STATUS_2_r,?" newline bitfld.long 0x00 0.--1. "LCD1_CLK_STATUS,LCD1_CLK clock selection status (multiplexer 2) indicates which clock is used by the glitch free mux selecting the source of LCD1_CLK" "LCD1_CLK_STATUS_0_r,LCD1_CLK_STATUS_1_r,LCD1_CLK_STATUS_2_r,?" width 0x0B tree.end tree "HDMI_WP_L3_MAIN" base ad:0x58040000 group.long 0x40++0x03 line.long 0x00 "HDMI_WP_PWR_CTRL,Power control" bitfld.long 0x00 2.--3. "PLL_PWR_CMD,Command for power control of the HDMI PLL Control module - STATE_OFF" "PLL_PWR_CMD_0,PLL_PWR_CMD_1,PLL_PWR_CMD_2,PLL_PWR_CMD_3" rbitfld.long 0x00 0.--1. "PLL_PWR_STATUS,Status of the power control of the HDMI PLL Control module - STATE_OFF" "PLL_PWR_STATUS_0,PLL_PWR_STATUS_1,PLL_PWR_STATUS_2,PLL_PWR_STATUS_3" group.long 0x70++0x03 line.long 0x00 "HDMI_WP_CLK,Configuration of clocks" bitfld.long 0x00 8.--10. "SCP_PWR_DIV,Defines the divisor value to be used for the generation of the SCP_PWR clock (up to 66.5MHz) from the input interface clock (up to 266MHz)" "SCP_PWR_DIV_0,SCP_PWR_DIV_1,SCP_PWR_DIV_2,SCP_PWR_DIV_3,SCP_PWR_DIV_4,SCP_PWR_DIV_5,SCP_PWR_DIV_6,SCP_PWR_DIV_7" width 0x0B tree.end tree "OCP2SCP2_L4_CFG" base ad:0x4A0A0000 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 3.--4. "IDLEMODE,00 Force Idle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3_r" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,- Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Timing constraints for the OCP2SCP module" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree.end tree "DSP_Subsystem" tree "DSP1_FW_L2_NOC_CFG" base ad:0x40D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end tree "DSP2_FW_L2_NOC_CFG" base ad:0x41503000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end tree "DSP_FW_L2_NOC_CFG" base ad:0x1D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" width 0x0B tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MMU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MMU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MMU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MMU0 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP2_SYSTEM" base ad:0x41500000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MMU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MMU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MMU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MMU0 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree "DSP_SYSTEM" base ad:0x1D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MMU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MMU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MMU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MMU0 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" width 0x0B tree.end tree.end tree "Dual_Cortex_A15_MPU_Subsystem" tree "MPU_AXI2OCP_MISC" base ad:0x482A2000 group.long 0x00++0x03 line.long 0x00 "MA_PRIORITY,Memory adapter priority register" bitfld.long 0x00 8. "HIMEM_INTERLEAVE_UN,HIMEM_INTERLEAVE_UN" "0,1" bitfld.long 0x00 0.--2. "PRIORITY,MPU_MA priority value" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "MPU_MA_WP" base ad:0x482AF200 rgroup.long 0x00++0x43 line.long 0x00 "DBG_HWWP_CAP,Debug Watchpoint Capabilities Register" bitfld.long 0x00 15. "HWWP_MEM_CHAIN_REG_PRESENT,Memory Barrier Chain Control Register implementation" "Not present,Present" newline bitfld.long 0x00 14. "HWWP_TRANS_ATTR1_REG_PRESENT,Transaction Attribute 1 Register implementation" "Not present,Present" newline bitfld.long 0x00 13. "HWWP_TRANS_ATTR0_REG_PRESENT,Transaction Attribute 0 Register implementation" "Not present,Present" newline bitfld.long 0x00 12. "HWWP_AUX_CNTL_REG_PRESENT,Auxillary Control Register implementation" "Not present,Present" newline bitfld.long 0x00 8.--10. "DATA_WIDTH,Data Bus Width" "8 bits,16 bits,32 bits,64 bits,128 bits All other..,?..." newline bitfld.long 0x00 4.--6. "ADDR_WIDTH,Address Bus Width" "8 bits,16 bits,24 bits,32 bits,36 bits,40 bits,64 bits,Reserved" newline bitfld.long 0x00 0.--3. "NUM_WP,Number of Watchpoints supported (0-15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TRIG_CTRL,Trigger Control Register" bitfld.long 0x04 0. "TRIG_EN," "0,1" line.long 0x08 "DBG_HWWP0_LW_ADDR0,Debug Watchpoint Addr0 Register (lower order bits 31:0)" line.long 0x0C "DBG_HWWP0_HG_ADDR0,Debug Watchpoint Addr0 Register (higher order bits 39:32)" hexmask.long.byte 0x0C 0.--7. 1. "HIGHER_ORDER_WP_ADDR,The byte-addressable higher order AXI-4 physical watchpoint address to monitor" line.long 0x10 "DBG_HWWP0_MAIN_CNTL,Debug Watchpoint Main Control Register" bitfld.long 0x10 31. "TRIG,Watchpoint trigger" "Watchpoint not triggered,Watchpoint has triggered (Reset upon 0->1.." newline bitfld.long 0x10 20.--23. "BEAT_SEL,Beat Select (This parameter decides upon for which beat of the burst the data byte lanes should be captured data)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 14.--15. "SUPERVISOR_USER_ACCESS,Supervisor/User access" "Reserved,User,Supervisor,No preference" newline bitfld.long 0x10 12.--13. "SECURE_ACCESS,Secure/Non-secure access" "Reserved,Non-secure,Secure,No preference" newline bitfld.long 0x10 5.--10. "WP_ADDR_MASK,Watchpoint address mask (bits to ignore)" "Ignore address bit 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Ignore address bit 39,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Reserved" newline bitfld.long 0x10 4. "WP_MATCH_CRITERIA,Watchpoint match criteria" "Match if access within address range to include..,Match if access outside address range" newline bitfld.long 0x10 1.--3. "WP_LS_ACCESS,Watchpoint Load/Store access" "(Load) Load exclusive or swap,(Store) Store exclusive or swap (non-posted),(Store) Store exclusive or swap (posted),Any type of store 0x4 0x5,?,?,Reserved,No preference (valid only if CHAIN_WP_EN=0;.." newline bitfld.long 0x10 0. "WP_EN,Watchpoint enable" "Disable the watchpoint,Enable the watchpoint" line.long 0x14 "DBG_HWWP0_AUX_CNTL,Debug Watchpoint Auxilliary Control Register" bitfld.long 0x14 14.--15. "MA_SPLIT_TARG,MA splitter target" "Reserved,AXI2OCP bridge,EMIF,No preference" newline bitfld.long 0x14 4.--6. "INITIATOR_ID,Initiator ID" "CPU_0,CPU_1,CPU_2,CPU_3,Unknown source (ACP FEQ etc),CMU,Reserved,No preference" newline bitfld.long 0x14 0.--1. "ACCESS_TYPE,Access type" "Reserved,Instructions,Data/others,No preference" line.long 0x18 "DBG_HWWP0_MEM_CNTL,Debug Watchpoint Memory Barrier Control Register" bitfld.long 0x18 31. "MEM_BAR_TRIG,Memory barrier trigger" "Memory Barrier Watchpoint not triggered,Memory Barrier Watchpoint has triggered (Reset.." newline bitfld.long 0x18 3.--4. "MEM_BAR_ACCESS_TYPE,Type of memory barrier access" "Reserved,,,Don't care.." newline bitfld.long 0x18 1.--2. "MEM_BAR_TYPE,Memory barrier type" "Reserved,DSB,DMB,No preference" newline bitfld.long 0x18 0. "MEM_BAR_WP_EN,Memory barrier watchpoint enable" "Disable the watchpoint,Enable the watchpoint" line.long 0x1C "DBG_HWWP0_CHAIN_CNTL,Debug Watchpoint Data/Memory Barrier Chain Control Register" bitfld.long 0x1C 31. "CHAIN_WP_TRIG,Chained watchpoints (memory barrier and data watchpoint) trigger" "Chained Watchpoints not triggered,Chained Watchpoints have triggered (Reset upon.." newline bitfld.long 0x1C 1. "CHAIN_TYPE,Chain type" "Watchpoint match then memory barrier match,Memory barrier match then watchpoint match" newline bitfld.long 0x1C 0. "CHAIN_WP_EN,Chained watchpoints (memory barrier and data watchpoint) enable" "Disable the chained watchpoints,Enable the chained watchpoints" line.long 0x20 "DBG_HWWP0_LW_ADDR0_LOG,Debug Watchpoint Addr0 Log Register (lower order bits 31:0)" line.long 0x24 "DBG_HWWP0_HG_ADDR0_LOG,Debug Watchpoint Addr0 Log Register (higher order bits 39:32)" hexmask.long.byte 0x24 0.--7. 1. "WP_ADDR_HIGHER_ORDER_BITS,Watchpoint address higher order bits (bits 39:32) (The byte-addressable higher order AXI-4 physical watchpoint address bits which results in a match)" line.long 0x28 "DBG_HWWP0_DATA0_LOG,Debug Watchpoint Data Log Register (bits 31:0)" line.long 0x2C "DBG_HWWP0_DATA1_LOG,Debug Watchpoint Data Log Register (bits 63:32)" line.long 0x30 "DBG_HWWP0_DATA2_LOG,Debug Watchpoint Data Log Register (bits 95:64)" line.long 0x34 "DBG_HWWP0_DATA3_LOG,Debug Watchpoint Data Log Register (bits 127:96)" line.long 0x38 "DBG_HWWP0_TRANS_ATTR0_LOG,Debug Watchpoint Transaction Attributes 0 Log Register" bitfld.long 0x38 24.--25. "RESP_INFO,Response info" "Reserved,Okay,Request failed,Request error" newline bitfld.long 0x38 20.--22. "INIT_INFO,Initiator info" "CPU_0,CPU_1,CPU_2,CPU_3,Unknown source (ACP FEQ etc),CMU,?,Reserved" newline bitfld.long 0x38 16.--18. "TARGET_INFO,Target info" "AXI2OCP,EMIF All other..,?..." newline bitfld.long 0x38 10.--12. "TRANS_TYPE,Transaction type (The type of transaction which results in a watchpoint match and is protocol independent. Not all protocols support all transaction types)" "Reserved,Write posted,,Read exclusive,Read linked,Write non-posted,Write conditional,Broadcast" newline bitfld.long 0x38 4.--9. "BURST_LENGTH,Burst length (The length of the burst which results in a watchpoint match)" "?,Burst length = 1 (min value),Burst length = 2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Burst length = 63 (max value)" newline bitfld.long 0x38 0.--2. "BURST_TYPE,Burst type" "Incrementing,Wrapping,?,Fixed (streaming) All other..,?..." line.long 0x3C "DBG_HWWP0_TRANS_ATTR1_LOG,Debug Watchpoint Transaction Attributes 1 Log Register" bitfld.long 0x3C 2. "DATA,Data access/Instruction fetch" "Other data PLE eviction,Instruction" newline bitfld.long 0x3C 1. "SUPERVISOR,Supervisor/User access" "User,Supervisor" newline bitfld.long 0x3C 0. "SECURE,Secure/Non-secure access" "Non-secure,Secure" line.long 0x40 "DBG_HWWP0_DATA_TRANS_ATTR0_LOG,Debug Watchpoint Data Transaction Attributes 0 Log Register" hexmask.long.word 0x40 0.--15. 1. "BYTE_EN,Byte enable (Byte enables for the 128-bit of data captured for the transaction match)" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x48243600 ad:0x48243A00 ) tree "MPU_PRCM_CM_C$1" base $2 group.long 0x00++0x03 line.long 0x00 "CM_CPU0_CLKSTCTRL,This register enables the CPU domain power state transition" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the full domain transition of the CPU domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_CPU0_CPU0_CLKCTRL,This register manages the CPU clocks" bitfld.long 0x00 0. "STBYST,Module standby status" "STBYST_0_r,STBYST_1_r" width 0x0B tree.end repeat.end tree "MPU_PRCM_DEVICE" base ad:0x48243200 group.long 0x00++0x07 line.long 0x00 "PRM_RSTST,This register logs the global reset sources. thus contains information regarding the cold/warm reset events generated by global PRCM" bitfld.long 0x00 1. "GLOBAL_WARM_RST,Global warm reset event generated by global PRCM - _0x0" "GLOBAL_WARM_RST_0,GLOBAL_WARM_RST_1" bitfld.long 0x00 0. "GLOBAL_COLD_RST,Power-on (cold) reset event generated by global PRCM - _0x0" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x04 "PRM_PSCON_COUNT,Programmable precharge count for L1cache" bitfld.long 0x04 25. "HG_RAMPUP,Ramp-up mode selection of HG power chain switch - SLOW" "HG_RAMPUP_0,HG_RAMPUP_1" bitfld.long 0x04 24. "HG_EN,HG power chain switch enable - HG_DISABLE" "HG_EN_0,HG_EN_1" hexmask.long.byte 0x04 16.--23. 1. "HG_PONOUT_2_PGDOODIN_TIME,The value set in this field determines the slow ramp-up time and the duration (number of cycles) of the PONOUTHG to PGOODINHG (transition for power domain without DPS)" newline hexmask.long.byte 0x04 0.--7. 1. "PCHARGE_TIME,Programmable precharge count during retention" group.long 0x10++0x07 line.long 0x00 "PRM_FRAC_INCREMENTER_NUMERATOR,Fractional incrementor" hexmask.long.word 0x00 16.--27. 1. "ABE_LP_MODE_NUMERATOR,Numerator to be used in fractional incrementor when ABE_LP_CLK clock is used as PRCM clock" hexmask.long.word 0x00 0.--11. 1. "SYS_MODE_NUMERATOR,Numerator to be used in fractional incrementor when SYS_CLK1 is used as PRCM clock.NOTE: The reset value corresponds to SYS_CLK1 = 38.4 MHz" line.long 0x04 "PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD,Reload command and denominator to be used in fractional incrementor" bitfld.long 0x04 16. "RELOAD,Reload counter value from coarse counter" "0,1" hexmask.long.word 0x04 0.--11. 1. "DENOMINATOR,Denominator to be used in fractional incrementor when when SYS_CLK1 is used as PRCM clock.NOTE: The reset value corresponds to SYS_CLK1 = 38.4 MHz" width 0x0B tree.end tree "MPU_PRCM_OCP_SOCKET" base ad:0x48243000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRCM_MPU,IP Revision register" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x48243400 ad:0x48243800 ) tree "MPU_PRCM_PRM_C$1" base $2 group.long 0x00++0x07 line.long 0x00 "PM_CPU0_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "L1_BANK_ONSTATE,CPU_L1 memory state when domain is ON" "?,?,?,L1_BANK_ONSTATE_3_r" rbitfld.long 0x00 8. "L1_BANK_RETSTATE,CPU_L1 memory state when domain is RETENTION" "?,L1_BANK_RETSTATE_1_r" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_RET" "?,LOGICRETSTATE_1_r" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CPU0_PWRSTST,This register provides a status on the CPU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered - OFF" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0_r,INTRANSITION_1_r" rbitfld.long 0x04 4.--5. "L1_BANK_STATEST,CPU_L1 memory state status - MEM_OFF" "L1_BANK_STATEST_0_r,L1_BANK_STATEST_1_r,L1_BANK_STATEST_2_r,L1_BANK_STATEST_3_r" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0_r,LOGICSTATEST_1_r" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0_r,POWERSTATEST_1_r,POWERSTATEST_2_r,POWERSTATEST_3_r" group.long 0x10++0x07 line.long 0x00 "RM_CPU0_CPU0_RSTCTRL,This register controls the assertion/release of the CPU CORE reset" bitfld.long 0x00 0. "RST,CPU warm local reset control - CLEAR" "RST_0,RST_1" line.long 0x04 "RM_CPU0_CPU0_RSTST,This register logs the different reset sources of the MPU domain" bitfld.long 0x04 1. "DBGRST_REQ_RSTST,MPU_C0 processor has been reset due to MPU_C0 emulation reset request driven from MPUSS" "DBGRST_REQ_RSTST_0_r,DBGRST_REQ_RSTST_1_r" bitfld.long 0x04 0. "RSTST,MPU_C0 software reset - CLEAR" "RSTST_0_r,RSTST_1_r" group.long 0x24++0x03 line.long 0x00 "RM_CPU0_CPU0_CONTEXT,This register contains dedicated CPU context statuses" bitfld.long 0x00 8. "LOSTMEM_CPU_L1,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CPU_L1_0,LOSTMEM_CPU_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end repeat.end tree "MPU_WUGEN" base ad:0x48281000 group.long 0x00++0x03 line.long 0x00 "WKG_CONTROL_0,Wake-up generator control and status register for MPU_C0" bitfld.long 0x00 15. "DOMAINRESET,MPU always-on power domain (PD_MPUAON) reset status bit" "no reset occur,reset occur" newline bitfld.long 0x00 14. "MPU_WARM_RESET,This bit is set when the MPU_WARM_RESET signal is asserted" "MPU_WARM_RESET reset signal has not been asserted,MPU_WARM_RESET reset request has been asserted" newline bitfld.long 0x00 13. "MPU_COLD_RESET,This bit is set when the MPU_COLD_RESET signal is asserted" "MPU_COLD_RESET reset signal has not been asserted,MPU_COLD_RESET reset request has been asserted" newline bitfld.long 0x00 10. "EVENTO,EVENTO status bit" "Rising edge of EVENTO is not detected,Rising edge of EVENTO is detected" newline bitfld.long 0x00 9. "STANDBYWFE,This bit gives software the visibility to track whether WFE mode have been entered" "WFE mode has not been entered,WFE mode has been entered" newline bitfld.long 0x00 8. "STANDBYWFI,This bit gives software the visibility to track whether WFI mode have been entered" "WFI mode has not been entered,WFI mode has been entered" group.long 0x10++0x13 line.long 0x00 "WKG_ENB_A_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_0 to MPU_IRQ_31)" bitfld.long 0x00 31. "WKG_ENB_FOR_INTR31,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" newline bitfld.long 0x00 30. "WKG_ENB_FOR_INTR30,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" newline bitfld.long 0x00 29. "WKG_ENB_FOR_INTR29,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" newline bitfld.long 0x00 28. "WKG_ENB_FOR_INTR28,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" newline bitfld.long 0x00 27. "WKG_ENB_FOR_INTR27,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" newline bitfld.long 0x00 26. "WKG_ENB_FOR_INTR26,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" newline bitfld.long 0x00 25. "WKG_ENB_FOR_INTR25,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" newline bitfld.long 0x00 24. "WKG_ENB_FOR_INTR24,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" newline bitfld.long 0x00 23. "WKG_ENB_FOR_INTR23,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" newline bitfld.long 0x00 22. "WKG_ENB_FOR_INTR22,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" newline bitfld.long 0x00 21. "WKG_ENB_FOR_INTR21,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" newline bitfld.long 0x00 20. "WKG_ENB_FOR_INTR20,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" newline bitfld.long 0x00 19. "WKG_ENB_FOR_INTR19,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" newline bitfld.long 0x00 18. "WKG_ENB_FOR_INTR18,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" newline bitfld.long 0x00 17. "WKG_ENB_FOR_INTR17,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" newline bitfld.long 0x00 16. "WKG_ENB_FOR_INTR16,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" newline bitfld.long 0x00 15. "WKG_ENB_FOR_INTR15,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" newline bitfld.long 0x00 14. "WKG_ENB_FOR_INTR14,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" newline bitfld.long 0x00 13. "WKG_ENB_FOR_INTR13,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" newline bitfld.long 0x00 12. "WKG_ENB_FOR_INTR12,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" newline bitfld.long 0x00 11. "WKG_ENB_FOR_INTR11,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" newline bitfld.long 0x00 10. "WKG_ENB_FOR_INTR10,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" newline bitfld.long 0x00 9. "WKG_ENB_FOR_INTR9,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" newline bitfld.long 0x00 8. "WKG_ENB_FOR_INTR8,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" newline bitfld.long 0x00 7. "WKG_ENB_FOR_INTR7,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" newline bitfld.long 0x00 6. "WKG_ENB_FOR_INTR6,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" newline bitfld.long 0x00 5. "WKG_ENB_FOR_INTR5,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" newline bitfld.long 0x00 4. "WKG_ENB_FOR_INTR4,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" newline bitfld.long 0x00 3. "WKG_ENB_FOR_INTR3,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" newline bitfld.long 0x00 2. "WKG_ENB_FOR_INTR2,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" newline bitfld.long 0x00 1. "WKG_ENB_FOR_INTR1,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" newline bitfld.long 0x00 0. "WKG_ENB_FOR_INTR0,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" line.long 0x04 "WKG_ENB_B_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_32 to MPU_IRQ_63)" bitfld.long 0x04 31. "WKG_ENB_FOR_INTR63,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" newline bitfld.long 0x04 30. "WKG_ENB_FOR_INTR62,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" newline bitfld.long 0x04 29. "WKG_ENB_FOR_INTR61,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" newline bitfld.long 0x04 28. "WKG_ENB_FOR_INTR60,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" newline bitfld.long 0x04 27. "WKG_ENB_FOR_INTR59,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" newline bitfld.long 0x04 26. "WKG_ENB_FOR_INTR58,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" newline bitfld.long 0x04 25. "WKG_ENB_FOR_INTR57,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" newline bitfld.long 0x04 24. "WKG_ENB_FOR_INTR56,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" newline bitfld.long 0x04 23. "WKG_ENB_FOR_INTR55,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" newline bitfld.long 0x04 22. "WKG_ENB_FOR_INTR54,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" newline bitfld.long 0x04 21. "WKG_ENB_FOR_INTR53,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" newline bitfld.long 0x04 20. "WKG_ENB_FOR_INTR52,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" newline bitfld.long 0x04 19. "WKG_ENB_FOR_INTR51,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" newline bitfld.long 0x04 18. "WKG_ENB_FOR_INTR50,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" newline bitfld.long 0x04 17. "WKG_ENB_FOR_INTR49,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" newline bitfld.long 0x04 16. "WKG_ENB_FOR_INTR48,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" newline bitfld.long 0x04 15. "WKG_ENB_FOR_INTR47,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" newline bitfld.long 0x04 14. "WKG_ENB_FOR_INTR46,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" newline bitfld.long 0x04 13. "WKG_ENB_FOR_INTR45,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" newline bitfld.long 0x04 12. "WKG_ENB_FOR_INTR44,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" newline bitfld.long 0x04 11. "WKG_ENB_FOR_INTR43,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" newline bitfld.long 0x04 10. "WKG_ENB_FOR_INTR42,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" newline bitfld.long 0x04 9. "WKG_ENB_FOR_INTR41,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" newline bitfld.long 0x04 8. "WKG_ENB_FOR_INTR40,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" newline bitfld.long 0x04 7. "WKG_ENB_FOR_INTR39,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" newline bitfld.long 0x04 6. "WKG_ENB_FOR_INTR38,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" newline bitfld.long 0x04 5. "WKG_ENB_FOR_INTR37,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" newline bitfld.long 0x04 4. "WKG_ENB_FOR_INTR36,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" newline bitfld.long 0x04 3. "WKG_ENB_FOR_INTR35,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" newline bitfld.long 0x04 2. "WKG_ENB_FOR_INTR34,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" newline bitfld.long 0x04 1. "WKG_ENB_FOR_INTR33,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" newline bitfld.long 0x04 0. "WKG_ENB_FOR_INTR32,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" line.long 0x08 "WKG_ENB_C_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_64 to MPU_IRQ_95)" bitfld.long 0x08 31. "WKG_ENB_FOR_INTR95,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" newline bitfld.long 0x08 30. "WKG_ENB_FOR_INTR94,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" newline bitfld.long 0x08 29. "WKG_ENB_FOR_INTR93,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" newline bitfld.long 0x08 28. "WKG_ENB_FOR_INTR92,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" newline bitfld.long 0x08 27. "WKG_ENB_FOR_INTR91,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" newline bitfld.long 0x08 26. "WKG_ENB_FOR_INTR90,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" newline bitfld.long 0x08 25. "WKG_ENB_FOR_INTR89,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" newline bitfld.long 0x08 24. "WKG_ENB_FOR_INTR88,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" newline bitfld.long 0x08 23. "WKG_ENB_FOR_INTR87,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" newline bitfld.long 0x08 22. "WKG_ENB_FOR_INTR86,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" newline bitfld.long 0x08 21. "WKG_ENB_FOR_INTR85,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" newline bitfld.long 0x08 20. "WKG_ENB_FOR_INTR84,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" newline bitfld.long 0x08 19. "WKG_ENB_FOR_INTR83,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" newline bitfld.long 0x08 18. "WKG_ENB_FOR_INTR82,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" newline bitfld.long 0x08 17. "WKG_ENB_FOR_INTR81,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" newline bitfld.long 0x08 16. "WKG_ENB_FOR_INTR80,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" newline bitfld.long 0x08 15. "WKG_ENB_FOR_INTR79,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" newline bitfld.long 0x08 14. "WKG_ENB_FOR_INTR78,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" newline bitfld.long 0x08 13. "WKG_ENB_FOR_INTR77,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" newline bitfld.long 0x08 12. "WKG_ENB_FOR_INTR76,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" newline bitfld.long 0x08 11. "WKG_ENB_FOR_INTR75,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" newline bitfld.long 0x08 10. "WKG_ENB_FOR_INTR74,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" newline bitfld.long 0x08 9. "WKG_ENB_FOR_INTR73,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" newline bitfld.long 0x08 8. "WKG_ENB_FOR_INTR72,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" newline bitfld.long 0x08 7. "WKG_ENB_FOR_INTR71,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" newline bitfld.long 0x08 6. "WKG_ENB_FOR_INTR70,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" newline bitfld.long 0x08 5. "WKG_ENB_FOR_INTR69,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" newline bitfld.long 0x08 4. "WKG_ENB_FOR_INTR68,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" newline bitfld.long 0x08 3. "WKG_ENB_FOR_INTR67,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" newline bitfld.long 0x08 2. "WKG_ENB_FOR_INTR66,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" newline bitfld.long 0x08 1. "WKG_ENB_FOR_INTR65,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" newline bitfld.long 0x08 0. "WKG_ENB_FOR_INTR64,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" line.long 0x0C "WKG_ENB_D_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_96 to MPU_IRQ_127)" bitfld.long 0x0C 31. "WKG_ENB_FOR_INTR127,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" newline bitfld.long 0x0C 30. "WKG_ENB_FOR_INTR126,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" newline bitfld.long 0x0C 29. "WKG_ENB_FOR_INTR125,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" newline bitfld.long 0x0C 28. "WKG_ENB_FOR_INTR124,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" newline bitfld.long 0x0C 27. "WKG_ENB_FOR_INTR123,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" newline bitfld.long 0x0C 26. "WKG_ENB_FOR_INTR122,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" newline bitfld.long 0x0C 25. "WKG_ENB_FOR_INTR121,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" newline bitfld.long 0x0C 24. "WKG_ENB_FOR_INTR120,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" newline bitfld.long 0x0C 23. "WKG_ENB_FOR_INTR119,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" newline bitfld.long 0x0C 22. "WKG_ENB_FOR_INTR118,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" newline bitfld.long 0x0C 21. "WKG_ENB_FOR_INTR117,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" newline bitfld.long 0x0C 20. "WKG_ENB_FOR_INTR116,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" newline bitfld.long 0x0C 19. "WKG_ENB_FOR_INTR115,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" newline bitfld.long 0x0C 18. "WKG_ENB_FOR_INTR114,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" newline bitfld.long 0x0C 17. "WKG_ENB_FOR_INTR113,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" newline bitfld.long 0x0C 16. "WKG_ENB_FOR_INTR112,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" newline bitfld.long 0x0C 15. "WKG_ENB_FOR_INTR111,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" newline bitfld.long 0x0C 14. "WKG_ENB_FOR_INTR110,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" newline bitfld.long 0x0C 13. "WKG_ENB_FOR_INTR109,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" newline bitfld.long 0x0C 12. "WKG_ENB_FOR_INTR108,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" newline bitfld.long 0x0C 11. "WKG_ENB_FOR_INTR107,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" newline bitfld.long 0x0C 10. "WKG_ENB_FOR_INTR106,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" newline bitfld.long 0x0C 9. "WKG_ENB_FOR_INTR105,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" newline bitfld.long 0x0C 8. "WKG_ENB_FOR_INTR104,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" newline bitfld.long 0x0C 7. "WKG_ENB_FOR_INTR103,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" newline bitfld.long 0x0C 6. "WKG_ENB_FOR_INTR102,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" newline bitfld.long 0x0C 5. "WKG_ENB_FOR_INTR101,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" newline bitfld.long 0x0C 4. "WKG_ENB_FOR_INTR100,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" newline bitfld.long 0x0C 3. "WKG_ENB_FOR_INTR99,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" newline bitfld.long 0x0C 2. "WKG_ENB_FOR_INTR98,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" newline bitfld.long 0x0C 1. "WKG_ENB_FOR_INTR97,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" newline bitfld.long 0x0C 0. "WKG_ENB_FOR_INTR96,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" line.long 0x10 "WKG_ENB_E_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_128 to MPU_IRQ_159)" bitfld.long 0x10 31. "WKG_ENB_FOR_INTR159,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" newline bitfld.long 0x10 30. "WKG_ENB_FOR_INTR158,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" newline bitfld.long 0x10 29. "WKG_ENB_FOR_INTR157,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" newline bitfld.long 0x10 28. "WKG_ENB_FOR_INTR156,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" newline bitfld.long 0x10 27. "WKG_ENB_FOR_INTR155,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" newline bitfld.long 0x10 26. "WKG_ENB_FOR_INTR154,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" newline bitfld.long 0x10 25. "WKG_ENB_FOR_INTR153,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" newline bitfld.long 0x10 24. "WKG_ENB_FOR_INTR152,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" newline bitfld.long 0x10 23. "WKG_ENB_FOR_INTR151,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" newline bitfld.long 0x10 22. "WKG_ENB_FOR_INTR150,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" newline bitfld.long 0x10 21. "WKG_ENB_FOR_INTR149,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" newline bitfld.long 0x10 20. "WKG_ENB_FOR_INTR148,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" newline bitfld.long 0x10 19. "WKG_ENB_FOR_INTR147,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" newline bitfld.long 0x10 18. "WKG_ENB_FOR_INTR146,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" newline bitfld.long 0x10 17. "WKG_ENB_FOR_INTR145,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" newline bitfld.long 0x10 16. "WKG_ENB_FOR_INTR144,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" newline bitfld.long 0x10 15. "WKG_ENB_FOR_INTR143,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" newline bitfld.long 0x10 14. "WKG_ENB_FOR_INTR142,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" newline bitfld.long 0x10 13. "WKG_ENB_FOR_INTR141,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" newline bitfld.long 0x10 12. "WKG_ENB_FOR_INTR140,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" newline bitfld.long 0x10 11. "WKG_ENB_FOR_INTR139,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" newline bitfld.long 0x10 10. "WKG_ENB_FOR_INTR138,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" newline bitfld.long 0x10 9. "WKG_ENB_FOR_INTR137,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" newline bitfld.long 0x10 8. "WKG_ENB_FOR_INTR136,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" newline bitfld.long 0x10 7. "WKG_ENB_FOR_INTR135,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" newline bitfld.long 0x10 6. "WKG_ENB_FOR_INTR134,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" newline bitfld.long 0x10 5. "WKG_ENB_FOR_INTR133,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" newline bitfld.long 0x10 4. "WKG_ENB_FOR_INTR132,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" newline bitfld.long 0x10 3. "WKG_ENB_FOR_INTR131,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" newline bitfld.long 0x10 2. "WKG_ENB_FOR_INTR130,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" newline bitfld.long 0x10 1. "WKG_ENB_FOR_INTR129,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" newline bitfld.long 0x10 0. "WKG_ENB_FOR_INTR128,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" group.long 0x400++0x03 line.long 0x00 "WKG_CONTROL_1,Wake-up generator control and status register for MPU_C1" bitfld.long 0x00 15. "DOMAINRESET,MPU always-on power domain (PD_MPUAON) reset status bit" "No reset occurred,Reset occurred" newline bitfld.long 0x00 14. "MPU_WARM_RESET,This bit is set when the MPU_WARM_RESET signal is asserted" "MPU_WARM_RESET reset signal has not been asserted,MPU_WARM_RESET reset request has been asserted" newline bitfld.long 0x00 13. "MPU_COLD_RESET,This bit is set when the MPU_COLD_RESET signal is asserted" "MPU_COLD_RESET reset signal has not been asserted,MPU_COLD_RESET reset request has been asserted" newline bitfld.long 0x00 10. "EVENTO,EVENTO status bit" "Rising edge of EVENTO is not detected,Rising edge of EVENTO is detected" newline bitfld.long 0x00 9. "STANDBYWFE,This bit gives software the visibility to track whether WFE mode have been entered" "WFE mode has not been entered,WFE mode has been entered" newline bitfld.long 0x00 8. "STANDBYWFI,This bit gives software the visibility to track whether WFI mode have been entered" "WFI mode has not been entered,WFI mode has been entered" group.long 0x410++0x13 line.long 0x00 "WKG_ENB_A_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_0 to MPU_IRQ_31)" bitfld.long 0x00 31. "WKG_ENB_FOR_INTR31,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" newline bitfld.long 0x00 30. "WKG_ENB_FOR_INTR30,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" newline bitfld.long 0x00 29. "WKG_ENB_FOR_INTR29,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" newline bitfld.long 0x00 28. "WKG_ENB_FOR_INTR28,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" newline bitfld.long 0x00 27. "WKG_ENB_FOR_INTR27,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" newline bitfld.long 0x00 26. "WKG_ENB_FOR_INTR26,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" newline bitfld.long 0x00 25. "WKG_ENB_FOR_INTR25,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" newline bitfld.long 0x00 24. "WKG_ENB_FOR_INTR24,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" newline bitfld.long 0x00 23. "WKG_ENB_FOR_INTR23,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" newline bitfld.long 0x00 22. "WKG_ENB_FOR_INTR22,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" newline bitfld.long 0x00 21. "WKG_ENB_FOR_INTR21,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" newline bitfld.long 0x00 20. "WKG_ENB_FOR_INTR20,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" newline bitfld.long 0x00 19. "WKG_ENB_FOR_INTR19,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" newline bitfld.long 0x00 18. "WKG_ENB_FOR_INTR18,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" newline bitfld.long 0x00 17. "WKG_ENB_FOR_INTR17,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" newline bitfld.long 0x00 16. "WKG_ENB_FOR_INTR16,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" newline bitfld.long 0x00 15. "WKG_ENB_FOR_INTR15,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" newline bitfld.long 0x00 14. "WKG_ENB_FOR_INTR14,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" newline bitfld.long 0x00 13. "WKG_ENB_FOR_INTR13,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" newline bitfld.long 0x00 12. "WKG_ENB_FOR_INTR12,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" newline bitfld.long 0x00 11. "WKG_ENB_FOR_INTR11,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" newline bitfld.long 0x00 10. "WKG_ENB_FOR_INTR10,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" newline bitfld.long 0x00 9. "WKG_ENB_FOR_INTR9,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" newline bitfld.long 0x00 8. "WKG_ENB_FOR_INTR8,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" newline bitfld.long 0x00 7. "WKG_ENB_FOR_INTR7,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" newline bitfld.long 0x00 6. "WKG_ENB_FOR_INTR6,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" newline bitfld.long 0x00 5. "WKG_ENB_FOR_INTR5,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" newline bitfld.long 0x00 4. "WKG_ENB_FOR_INTR4,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" newline bitfld.long 0x00 3. "WKG_ENB_FOR_INTR3,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" newline bitfld.long 0x00 2. "WKG_ENB_FOR_INTR2,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" newline bitfld.long 0x00 1. "WKG_ENB_FOR_INTR1,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" newline bitfld.long 0x00 0. "WKG_ENB_FOR_INTR0,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" line.long 0x04 "WKG_ENB_B_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_32 to MPU_IRQ_63)" bitfld.long 0x04 31. "WKG_ENB_FOR_INTR63,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" newline bitfld.long 0x04 30. "WKG_ENB_FOR_INTR62,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" newline bitfld.long 0x04 29. "WKG_ENB_FOR_INTR61,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" newline bitfld.long 0x04 28. "WKG_ENB_FOR_INTR60,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" newline bitfld.long 0x04 27. "WKG_ENB_FOR_INTR59,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" newline bitfld.long 0x04 26. "WKG_ENB_FOR_INTR58,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" newline bitfld.long 0x04 25. "WKG_ENB_FOR_INTR57,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" newline bitfld.long 0x04 24. "WKG_ENB_FOR_INTR56,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" newline bitfld.long 0x04 23. "WKG_ENB_FOR_INTR55,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" newline bitfld.long 0x04 22. "WKG_ENB_FOR_INTR54,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" newline bitfld.long 0x04 21. "WKG_ENB_FOR_INTR53,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" newline bitfld.long 0x04 20. "WKG_ENB_FOR_INTR52,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" newline bitfld.long 0x04 19. "WKG_ENB_FOR_INTR51,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" newline bitfld.long 0x04 18. "WKG_ENB_FOR_INTR50,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" newline bitfld.long 0x04 17. "WKG_ENB_FOR_INTR49,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" newline bitfld.long 0x04 16. "WKG_ENB_FOR_INTR48,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" newline bitfld.long 0x04 15. "WKG_ENB_FOR_INTR47,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" newline bitfld.long 0x04 14. "WKG_ENB_FOR_INTR46,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" newline bitfld.long 0x04 13. "WKG_ENB_FOR_INTR45,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" newline bitfld.long 0x04 12. "WKG_ENB_FOR_INTR44,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" newline bitfld.long 0x04 11. "WKG_ENB_FOR_INTR43,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" newline bitfld.long 0x04 10. "WKG_ENB_FOR_INTR42,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" newline bitfld.long 0x04 9. "WKG_ENB_FOR_INTR41,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" newline bitfld.long 0x04 8. "WKG_ENB_FOR_INTR40,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" newline bitfld.long 0x04 7. "WKG_ENB_FOR_INTR39,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" newline bitfld.long 0x04 6. "WKG_ENB_FOR_INTR38,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" newline bitfld.long 0x04 5. "WKG_ENB_FOR_INTR37,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" newline bitfld.long 0x04 4. "WKG_ENB_FOR_INTR36,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" newline bitfld.long 0x04 3. "WKG_ENB_FOR_INTR35,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" newline bitfld.long 0x04 2. "WKG_ENB_FOR_INTR34,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" newline bitfld.long 0x04 1. "WKG_ENB_FOR_INTR33,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" newline bitfld.long 0x04 0. "WKG_ENB_FOR_INTR32,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" line.long 0x08 "WKG_ENB_C_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_64 to MPU_IRQ_95)" bitfld.long 0x08 31. "WKG_ENB_FOR_INTR95,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" newline bitfld.long 0x08 30. "WKG_ENB_FOR_INTR94,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" newline bitfld.long 0x08 29. "WKG_ENB_FOR_INTR93,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" newline bitfld.long 0x08 28. "WKG_ENB_FOR_INTR92,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" newline bitfld.long 0x08 27. "WKG_ENB_FOR_INTR91,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" newline bitfld.long 0x08 26. "WKG_ENB_FOR_INTR90,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" newline bitfld.long 0x08 25. "WKG_ENB_FOR_INTR89,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" newline bitfld.long 0x08 24. "WKG_ENB_FOR_INTR88,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" newline bitfld.long 0x08 23. "WKG_ENB_FOR_INTR87,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" newline bitfld.long 0x08 22. "WKG_ENB_FOR_INTR86,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" newline bitfld.long 0x08 21. "WKG_ENB_FOR_INTR85,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" newline bitfld.long 0x08 20. "WKG_ENB_FOR_INTR84,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" newline bitfld.long 0x08 19. "WKG_ENB_FOR_INTR83,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" newline bitfld.long 0x08 18. "WKG_ENB_FOR_INTR82,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" newline bitfld.long 0x08 17. "WKG_ENB_FOR_INTR81,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" newline bitfld.long 0x08 16. "WKG_ENB_FOR_INTR80,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" newline bitfld.long 0x08 15. "WKG_ENB_FOR_INTR79,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" newline bitfld.long 0x08 14. "WKG_ENB_FOR_INTR78,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" newline bitfld.long 0x08 13. "WKG_ENB_FOR_INTR77,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" newline bitfld.long 0x08 12. "WKG_ENB_FOR_INTR76,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" newline bitfld.long 0x08 11. "WKG_ENB_FOR_INTR75,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" newline bitfld.long 0x08 10. "WKG_ENB_FOR_INTR74,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" newline bitfld.long 0x08 9. "WKG_ENB_FOR_INTR73,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" newline bitfld.long 0x08 8. "WKG_ENB_FOR_INTR72,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" newline bitfld.long 0x08 7. "WKG_ENB_FOR_INTR71,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" newline bitfld.long 0x08 6. "WKG_ENB_FOR_INTR70,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" newline bitfld.long 0x08 5. "WKG_ENB_FOR_INTR69,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" newline bitfld.long 0x08 4. "WKG_ENB_FOR_INTR68,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" newline bitfld.long 0x08 3. "WKG_ENB_FOR_INTR67,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" newline bitfld.long 0x08 2. "WKG_ENB_FOR_INTR66,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" newline bitfld.long 0x08 1. "WKG_ENB_FOR_INTR65,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" newline bitfld.long 0x08 0. "WKG_ENB_FOR_INTR64,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" line.long 0x0C "WKG_ENB_D_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_96 to MPU_IRQ_127)" bitfld.long 0x0C 31. "WKG_ENB_FOR_INTR127,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" newline bitfld.long 0x0C 30. "WKG_ENB_FOR_INTR126,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" newline bitfld.long 0x0C 29. "WKG_ENB_FOR_INTR125,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" newline bitfld.long 0x0C 28. "WKG_ENB_FOR_INTR124,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" newline bitfld.long 0x0C 27. "WKG_ENB_FOR_INTR123,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" newline bitfld.long 0x0C 26. "WKG_ENB_FOR_INTR122,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" newline bitfld.long 0x0C 25. "WKG_ENB_FOR_INTR121,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" newline bitfld.long 0x0C 24. "WKG_ENB_FOR_INTR120,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" newline bitfld.long 0x0C 23. "WKG_ENB_FOR_INTR119,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" newline bitfld.long 0x0C 22. "WKG_ENB_FOR_INTR118,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" newline bitfld.long 0x0C 21. "WKG_ENB_FOR_INTR117,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" newline bitfld.long 0x0C 20. "WKG_ENB_FOR_INTR116,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" newline bitfld.long 0x0C 19. "WKG_ENB_FOR_INTR115,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" newline bitfld.long 0x0C 18. "WKG_ENB_FOR_INTR114,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" newline bitfld.long 0x0C 17. "WKG_ENB_FOR_INTR113,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" newline bitfld.long 0x0C 16. "WKG_ENB_FOR_INTR112,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" newline bitfld.long 0x0C 15. "WKG_ENB_FOR_INTR111,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" newline bitfld.long 0x0C 14. "WKG_ENB_FOR_INTR110,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" newline bitfld.long 0x0C 13. "WKG_ENB_FOR_INTR109,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" newline bitfld.long 0x0C 12. "WKG_ENB_FOR_INTR108,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" newline bitfld.long 0x0C 11. "WKG_ENB_FOR_INTR107,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" newline bitfld.long 0x0C 10. "WKG_ENB_FOR_INTR106,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" newline bitfld.long 0x0C 9. "WKG_ENB_FOR_INTR105,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" newline bitfld.long 0x0C 8. "WKG_ENB_FOR_INTR104,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" newline bitfld.long 0x0C 7. "WKG_ENB_FOR_INTR103,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" newline bitfld.long 0x0C 6. "WKG_ENB_FOR_INTR102,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" newline bitfld.long 0x0C 5. "WKG_ENB_FOR_INTR101,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" newline bitfld.long 0x0C 4. "WKG_ENB_FOR_INTR100,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" newline bitfld.long 0x0C 3. "WKG_ENB_FOR_INTR99,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" newline bitfld.long 0x0C 2. "WKG_ENB_FOR_INTR98,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" newline bitfld.long 0x0C 1. "WKG_ENB_FOR_INTR97,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" newline bitfld.long 0x0C 0. "WKG_ENB_FOR_INTR96,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" line.long 0x10 "WKG_ENB_E_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_128 to MPU_IRQ_159)" bitfld.long 0x10 31. "WKG_ENB_FOR_INTR159,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" newline bitfld.long 0x10 30. "WKG_ENB_FOR_INTR158,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" newline bitfld.long 0x10 29. "WKG_ENB_FOR_INTR157,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" newline bitfld.long 0x10 28. "WKG_ENB_FOR_INTR156,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" newline bitfld.long 0x10 27. "WKG_ENB_FOR_INTR155,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" newline bitfld.long 0x10 26. "WKG_ENB_FOR_INTR154,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" newline bitfld.long 0x10 25. "WKG_ENB_FOR_INTR153,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" newline bitfld.long 0x10 24. "WKG_ENB_FOR_INTR152,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" newline bitfld.long 0x10 23. "WKG_ENB_FOR_INTR151,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" newline bitfld.long 0x10 22. "WKG_ENB_FOR_INTR150,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" newline bitfld.long 0x10 21. "WKG_ENB_FOR_INTR149,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" newline bitfld.long 0x10 20. "WKG_ENB_FOR_INTR148,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" newline bitfld.long 0x10 19. "WKG_ENB_FOR_INTR147,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" newline bitfld.long 0x10 18. "WKG_ENB_FOR_INTR146,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" newline bitfld.long 0x10 17. "WKG_ENB_FOR_INTR145,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" newline bitfld.long 0x10 16. "WKG_ENB_FOR_INTR144,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" newline bitfld.long 0x10 15. "WKG_ENB_FOR_INTR143,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" newline bitfld.long 0x10 14. "WKG_ENB_FOR_INTR142,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" newline bitfld.long 0x10 13. "WKG_ENB_FOR_INTR141,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" newline bitfld.long 0x10 12. "WKG_ENB_FOR_INTR140,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" newline bitfld.long 0x10 11. "WKG_ENB_FOR_INTR139,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" newline bitfld.long 0x10 10. "WKG_ENB_FOR_INTR138,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" newline bitfld.long 0x10 9. "WKG_ENB_FOR_INTR137,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" newline bitfld.long 0x10 8. "WKG_ENB_FOR_INTR136,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" newline bitfld.long 0x10 7. "WKG_ENB_FOR_INTR135,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" newline bitfld.long 0x10 6. "WKG_ENB_FOR_INTR134,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" newline bitfld.long 0x10 5. "WKG_ENB_FOR_INTR133,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" newline bitfld.long 0x10 4. "WKG_ENB_FOR_INTR132,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" newline bitfld.long 0x10 3. "WKG_ENB_FOR_INTR131,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" newline bitfld.long 0x10 2. "WKG_ENB_FOR_INTR130,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" newline bitfld.long 0x10 1. "WKG_ENB_FOR_INTR129,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" newline bitfld.long 0x10 0. "WKG_ENB_FOR_INTR128,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" group.long 0x800++0x0F line.long 0x00 "AUX_CORE_BOOT_0,This register is used by the ROM code and OS during SMP boot" bitfld.long 0x00 4.--7. "MPU_C1_STATUS,MPU_C1 boot status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AUX_CORE_BOOT_1,This register is used by the ROM code and OS during SMP boot" line.long 0x08 "STM_HWEVENTS_INV,Gives programmable control of inverting or not inverting MPUHWDBGOUT[31:0] going to HWEVENTS[31:0] input of CS_STM" bitfld.long 0x08 31. "STM_HWEVENT_INV_ 31,Polarity inversion control for MPUHWDBGOUT31 signal" "0,1" newline bitfld.long 0x08 30. "STM_HWEVENT_INV_ 30,Polarity inversion control for MPUHWDBGOUT30 signal" "0,1" newline bitfld.long 0x08 29. "STM_HWEVENT_INV_ 29,Polarity inversion control for MPUHWDBGOUT29 signal" "0,1" newline bitfld.long 0x08 28. "STM_HWEVENT_INV_ 28,Polarity inversion control for MPUHWDBGOUT28 signal" "0,1" newline bitfld.long 0x08 27. "STM_HWEVENT_INV_ 27,Polarity inversion control for MPUHWDBGOUT27 signal" "0,1" newline bitfld.long 0x08 26. "STM_HWEVENT_INV_ 26,Polarity inversion control for MPUHWDBGOUT26 signal" "0,1" newline bitfld.long 0x08 25. "STM_HWEVENT_INV_ 25,Polarity inversion control for MPUHWDBGOUT25 signal" "0,1" newline bitfld.long 0x08 24. "STM_HWEVENT_INV_ 24,Polarity inversion control for MPUHWDBGOUT24 signal" "0,1" newline bitfld.long 0x08 23. "STM_HWEVENT_INV_ 23,Polarity inversion control for MPUHWDBGOUT23 signal" "0,1" newline bitfld.long 0x08 22. "STM_HWEVENT_INV_ 22,Polarity inversion control for MPUHWDBGOUT22 signal" "0,1" newline bitfld.long 0x08 21. "STM_HWEVENT_INV_ 21,Polarity inversion control for MPUHWDBGOUT21 signal" "0,1" newline bitfld.long 0x08 20. "STM_HWEVENT_INV_ 20,Polarity inversion control for MPUHWDBGOUT20 signal" "0,1" newline bitfld.long 0x08 19. "STM_HWEVENT_INV_ 19,Polarity inversion control for MPUHWDBGOUT19 signal" "0,1" newline bitfld.long 0x08 18. "STM_HWEVENT_INV_ 18,Polarity inversion control for MPUHWDBGOUT18 signal" "0,1" newline bitfld.long 0x08 17. "STM_HWEVENT_INV_ 17,Polarity inversion control for MPUHWDBGOUT17 signal" "0,1" newline bitfld.long 0x08 16. "STM_HWEVENT_INV_ 16,Polarity inversion control for MPUHWDBGOUT16 signal" "0,1" newline bitfld.long 0x08 15. "STM_HWEVENT_INV_ 15,Polarity inversion control for MPUHWDBGOUT15 signal" "0,1" newline bitfld.long 0x08 14. "STM_HWEVENT_INV_ 14,Polarity inversion control for MPUHWDBGOUT14 signal" "0,1" newline bitfld.long 0x08 13. "STM_HWEVENT_INV_ 13,Polarity inversion control for MPUHWDBGOUT13 signal" "0,1" newline bitfld.long 0x08 12. "STM_HWEVENT_INV_ 12,Polarity inversion control for MPUHWDBGOUT12 signal" "0,1" newline bitfld.long 0x08 11. "STM_HWEVENT_INV_ 11,Polarity inversion control for MPUHWDBGOUT11 signal" "0,1" newline bitfld.long 0x08 10. "STM_HWEVENT_INV_ 10,Polarity inversion control for MPUHWDBGOUT10 signal" "0,1" newline bitfld.long 0x08 9. "STM_HWEVENT_INV_ 9,Polarity inversion control for MPUHWDBGOUT9 signal" "0,1" newline bitfld.long 0x08 8. "STM_HWEVENT_INV_ 8,Polarity inversion control for MPUHWDBGOUT8 signal" "0,1" newline bitfld.long 0x08 7. "STM_HWEVENT_INV_ 7,Polarity inversion control for MPUHWDBGOUT7 signal" "0,1" newline bitfld.long 0x08 6. "STM_HWEVENT_INV_ 6,Polarity inversion control for MPUHWDBGOUT6 signal" "0,1" newline bitfld.long 0x08 5. "STM_HWEVENT_INV_ 5,Polarity inversion control for MPUHWDBGOUT5 signal" "0,1" newline bitfld.long 0x08 4. "STM_HWEVENT_INV_ 4,Polarity inversion control for MPUHWDBGOUT4 signal" "0,1" newline bitfld.long 0x08 3. "STM_HWEVENT_INV_ 3,Polarity inversion control for MPUHWDBGOUT3 signal" "0,1" newline bitfld.long 0x08 2. "STM_HWEVENT_INV_ 2,Polarity inversion control for MPUHWDBGOUT2 signal" "0,1" newline bitfld.long 0x08 1. "STM_HWEVENT_INV_ 1,Polarity inversion control for MPUHWDBGOUT1 signal" "0,1" newline bitfld.long 0x08 0. "STM_HWEVENT_INV_0,Polarity inversion control for MPUHWDBGOUT0 signal" "0,1" line.long 0x0C "AMBA_IF_MODE,This register controls the MPU core interface tie-off values for BI. BO. BCM and SBD" bitfld.long 0x0C 5. "ES2_PM_MODE,Enables OFF mode behavior" "OFF Mode 1 CPUs would enter and exit OFF mode..,OFF Mode 2 CPUs are allowed to enter/exit OFF.." newline bitfld.long 0x0C 4. "APB_FENCE_EN,Enables APB fencing logic" "0,1" newline bitfld.long 0x0C 3. "BI,BROADCASTINNER input of MPU core" "0,1" newline bitfld.long 0x0C 2. "BO,BROADCASTOUTER input of MPU core" "0,1" newline bitfld.long 0x0C 1. "BCM,BROADCASTMAINTENANCE input of MPU core" "0,1" newline bitfld.long 0x0C 0. "SBD,SYSBARDISABLE input of MPU core" "0,1" rgroup.long 0xC08++0x07 line.long 0x00 "TIMESTAMPCYCLELO,Lower 32 bits of the 48-bit timestamp counter value" line.long 0x04 "TIMESTAMPCYCLEHI,Higher 16 bits of the 48-bit timestamp counter value" hexmask.long.word 0x04 0.--15. 1. "COUNTER_47_32,Higher 16 bits of the timestamp counter value" width 0x0B tree.end tree.end tree "Dual_Cortex_M4_IPU_Subsystem" tree "IPU1_UNICACHE_CFG" base ad:0x58880000 group.long 0x04++0x1F line.long 0x00 "CACHE_CONFIG,Configuration Register" bitfld.long 0x00 4. "LOCK_MAIN,Lock access to maintenance registers" "LOCK_MAIN_0,LOCK_MAIN_1" bitfld.long 0x00 3. "LOCK_PORT,Lock access to interface registers" "LOCK_PORT_0,LOCK_PORT_1" bitfld.long 0x00 2. "LOCK_INT,Lock access to interrupt registers" "LOCK_INT_0,LOCK_INT_1" bitfld.long 0x00 1. "BYPASS,Bypass" "BYPASS_0,BYPASS_1" bitfld.long 0x00 0. "CACHE_LOCK,Unicache lock" "CACHE_LOCK_0,CACHE_LOCK_1" line.long 0x04 "CACHE_INT,Interrupt Register" bitfld.long 0x04 5.--8. "PORT,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. "READ,Interface read response error" "0,1" bitfld.long 0x04 3. "WRITE,Interface write response error" "0,1" bitfld.long 0x04 2. "MAINT,Maintenance is completed" "0,1" bitfld.long 0x04 1. "PAGEFAULT,Unicache MMU page fault" "0,1" newline bitfld.long 0x04 0. "CONFIG,Configuration error" "0,1" line.long 0x08 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x08 5. "CLEANBUF,Clean write and prefetch buffers in" "CLEANBUF_0,CLEANBUF_1" bitfld.long 0x08 4. "PREFETCH,Always prefetch data" "PREFETCH_0,PREFETCH_1" bitfld.long 0x08 3. "CACHED,Follow cacheable sideband signals" "CACHED_0,CACHED_1" bitfld.long 0x08 2. "WRALLOCATE,Follow write allocate sideband signals" "WRALLOCATE_0,WRALLOCATE_1" bitfld.long 0x08 1. "WRBUFFER,Write throughs and write back no allocate are buffered" "WRBUFFER_0,WRBUFFER_1" newline bitfld.long 0x08 0. "WRAP,OCP wrap mode (critical word first)" "WRAP_0,WRAP_1" line.long 0x0C "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0C 5. "INTERRUPT,Generate interrupt when maintenance operation is complete" "INTERRUPT_0,INTERRUPT_1" bitfld.long 0x0C 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x0C 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x0C 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x0C 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x0C 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x10 "CACHE_MTSTART,Maintenance Start Configuration Register" line.long 0x14 "CACHE_MTEND,Maintenance End Configuration Register" line.long 0x18 "CACHE_CTADDR,Cache Test Address Register" line.long 0x1C "CACHE_CTDATA,Cache Test Data Register" width 0x0B tree.end tree "IPU2_UNICACHE_CFG" base ad:0x55080000 group.long 0x04++0x1F line.long 0x00 "CACHE_CONFIG,Configuration Register" bitfld.long 0x00 4. "LOCK_MAIN,Lock access to maintenance registers" "LOCK_MAIN_0,LOCK_MAIN_1" bitfld.long 0x00 3. "LOCK_PORT,Lock access to interface registers" "LOCK_PORT_0,LOCK_PORT_1" bitfld.long 0x00 2. "LOCK_INT,Lock access to interrupt registers" "LOCK_INT_0,LOCK_INT_1" bitfld.long 0x00 1. "BYPASS,Bypass" "BYPASS_0,BYPASS_1" bitfld.long 0x00 0. "CACHE_LOCK,Unicache lock" "CACHE_LOCK_0,CACHE_LOCK_1" line.long 0x04 "CACHE_INT,Interrupt Register" bitfld.long 0x04 5.--8. "PORT,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. "READ,Interface read response error" "0,1" bitfld.long 0x04 3. "WRITE,Interface write response error" "0,1" bitfld.long 0x04 2. "MAINT,Maintenance is completed" "0,1" bitfld.long 0x04 1. "PAGEFAULT,Unicache MMU page fault" "0,1" newline bitfld.long 0x04 0. "CONFIG,Configuration error" "0,1" line.long 0x08 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x08 5. "CLEANBUF,Clean write and prefetch buffers in" "CLEANBUF_0,CLEANBUF_1" bitfld.long 0x08 4. "PREFETCH,Always prefetch data" "PREFETCH_0,PREFETCH_1" bitfld.long 0x08 3. "CACHED,Follow cacheable sideband signals" "CACHED_0,CACHED_1" bitfld.long 0x08 2. "WRALLOCATE,Follow write allocate sideband signals" "WRALLOCATE_0,WRALLOCATE_1" bitfld.long 0x08 1. "WRBUFFER,Write throughs and write back no allocate are buffered" "WRBUFFER_0,WRBUFFER_1" newline bitfld.long 0x08 0. "WRAP,OCP wrap mode (critical word first)" "WRAP_0,WRAP_1" line.long 0x0C "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0C 5. "INTERRUPT,Generate interrupt when maintenance operation is complete" "INTERRUPT_0,INTERRUPT_1" bitfld.long 0x0C 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x0C 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x0C 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x0C 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x0C 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" line.long 0x10 "CACHE_MTSTART,Maintenance Start Configuration Register" line.long 0x14 "CACHE_MTEND,Maintenance End Configuration Register" line.long 0x18 "CACHE_CTADDR,Cache Test Address Register" line.long 0x1C "CACHE_CTDATA,Cache Test Data Register" width 0x0B tree.end tree "IPU1_UNICACHE_MMU_AMMU" base ad:0x58880800 group.long 0x4A8++0x03 line.long 0x00 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x00 10. "G_FLUSH,Global flush bit" "G_FLUSH_0,G_FLUSH_1" bitfld.long 0x00 7. "L1_CACHE1,Do maintenance operation in L1" "L1_CACHE1_0,L1_CACHE1_1" bitfld.long 0x00 6. "CPU_INTERRUPT,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "CPU_INTERRUPT_0,CPU_INTERRUPT_1" bitfld.long 0x00 5. "HOST_INTERRUPT,Generate interrupt when maintenance operation is complete" "HOST_INTERRUPT_0,HOST_INTERRUPT_1" newline bitfld.long 0x00 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x00 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x00 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x00 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x00 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" rgroup.long 0x4B4++0x07 line.long 0x00 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x00 0. "STATUS,Status bit" "STATUS_0_r,STATUS_1_r" line.long 0x04 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x04 1. "PRIVILEGE,Privilege bit" "PRIVILEGE_0,PRIVILEGE_1" bitfld.long 0x04 0. "MMU_LOCK,MMU lock" "MMU_LOCK_0,MMU_LOCK_1" group.long 0x4B0++0x03 line.long 0x00 "CACHE_MMU_MTEND,Maintenance end configuration register" group.long 0x4AC++0x03 line.long 0x00 "CACHE_MMU_MTSTART,Maintenance start configuration register" tree "Channel_0" group.long 0x00++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x40++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x20++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x60++0x03 line.long 0x00 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" group.long 0xE0++0x03 line.long 0x00 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0xA0++0x03 line.long 0x00 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x120++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x220++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_1" group.long 0x04++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x44++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x24++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x64++0x03 line.long 0x00 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" group.long 0xE4++0x03 line.long 0x00 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0xA4++0x03 line.long 0x00 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x124++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x224++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_2" group.long 0x08++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x48++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x28++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x128++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A8++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x228++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A8++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_3" group.long 0x0C++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x4C++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x2C++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x12C++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2AC++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x22C++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1AC++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_4" group.long 0x130++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x230++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_5" group.long 0x134++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x234++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_6" group.long 0x138++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B8++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x238++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B8++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_7" group.long 0x13C++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2BC++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x23C++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1BC++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_8" group.long 0x140++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2C0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x240++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1C0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_9" group.long 0x144++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2C4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x244++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1C4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end width 0x0B tree.end tree "IPU2_UNICACHE_MMU_AMMU" base ad:0x55080800 group.long 0x4A8++0x03 line.long 0x00 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x00 10. "G_FLUSH,Global flush bit" "G_FLUSH_0,G_FLUSH_1" bitfld.long 0x00 7. "L1_CACHE1,Do maintenance operation in L1" "L1_CACHE1_0,L1_CACHE1_1" bitfld.long 0x00 6. "CPU_INTERRUPT,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "CPU_INTERRUPT_0,CPU_INTERRUPT_1" bitfld.long 0x00 5. "HOST_INTERRUPT,Generate interrupt when maintenance operation is complete" "HOST_INTERRUPT_0,HOST_INTERRUPT_1" newline bitfld.long 0x00 4. "INVALIDATE,Invalidate lines in region defined by maintenance start/end addresses" "INVALIDATE_0,INVALIDATE_1" bitfld.long 0x00 3. "CLEAN,Evict dirty lines in region defined by maintenance start/end addresses" "CLEAN_0,CLEAN_1" bitfld.long 0x00 2. "UNLOCK,Unlock region defined by maintenance start/end addresses" "UNLOCK_0,UNLOCK_1" bitfld.long 0x00 1. "LOCK,Lock region defined by maintenance start/end addresses" "LOCK_0,LOCK_1" newline bitfld.long 0x00 0. "PRELOAD,Preload region defined by maintenance start/end addresses" "PRELOAD_0,PRELOAD_1" rgroup.long 0x4B4++0x07 line.long 0x00 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x00 0. "STATUS,Status bit" "STATUS_0_r,STATUS_1_r" line.long 0x04 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x04 1. "PRIVILEGE,Privilege bit" "PRIVILEGE_0,PRIVILEGE_1" bitfld.long 0x04 0. "MMU_LOCK,MMU lock" "MMU_LOCK_0,MMU_LOCK_1" group.long 0x4B0++0x03 line.long 0x00 "CACHE_MMU_MTEND,Maintenance end configuration register" group.long 0x4AC++0x03 line.long 0x00 "CACHE_MMU_MTSTART,Maintenance start configuration register" tree "Channel_0" group.long 0x00++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x40++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x20++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x60++0x03 line.long 0x00 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" group.long 0xE0++0x03 line.long 0x00 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0xA0++0x03 line.long 0x00 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x120++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x220++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_1" group.long 0x04++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x44++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x24++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x64++0x03 line.long 0x00 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source address" group.long 0xE4++0x03 line.long 0x00 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0xA4++0x03 line.long 0x00 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" hexmask.long.word 0x00 17.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x124++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x224++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_2" group.long 0x08++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x48++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x28++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x128++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2A8++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x228++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1A8++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_3" group.long 0x0C++0x03 line.long 0x00 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source address" group.long 0x4C++0x03 line.long 0x00 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" newline bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x2C++0x03 line.long 0x00 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" hexmask.long.byte 0x00 25.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" group.long 0x12C++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2AC++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x22C++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1AC++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_4" group.long 0x130++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x230++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_5" group.long 0x134++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x234++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_6" group.long 0x138++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2B8++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x238++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1B8++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_7" group.long 0x13C++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2BC++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x23C++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1BC++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_8" group.long 0x140++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2C0++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x240++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1C0++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end tree "Channel_9" group.long 0x144++0x03 line.long 0x00 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source address" group.long 0x2C4++0x03 line.long 0x00 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x00 4. "INTERRUPT,Generate interrupt when maintenance operation is complete" "0,1" bitfld.long 0x00 3. "INVALIDATE,Invalidate page" "0,1" bitfld.long 0x00 2. "CLEAN,Evict page" "0,1" bitfld.long 0x00 1. "LOCK,Lock page" "0,1" newline bitfld.long 0x00 0. "PRELOAD,Preload page" "0,1" group.long 0x244++0x03 line.long 0x00 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x00 19. "L1_WR_POLICY,L1 write policy" "L1_WR_POLICY_0,L1_WR_POLICY_1" bitfld.long 0x00 18. "L1_ALLOCATE,L1 allocate policy" "L1_ALLOCATE_0,L1_ALLOCATE_1" bitfld.long 0x00 17. "L1_POSTED,L1 posted policy" "L1_POSTED_0,L1_POSTED_1" bitfld.long 0x00 16. "L1_CACHEABLE,L1 cache policy" "L1_CACHEABLE_0,L1_CACHEABLE_1" newline rbitfld.long 0x00 8. "COHERENCY,Coherency" "0,1" bitfld.long 0x00 7. "EXCLUSION,Cache exclusion" "EXCLUSION_0,EXCLUSION_1" bitfld.long 0x00 6. "PRELOAD,Preload region" "PRELOAD_0,PRELOAD_1" bitfld.long 0x00 5. "READ,Read only" "0,1" newline bitfld.long 0x00 4. "EXECUTE,Execute only" "0,1" bitfld.long 0x00 3. "VOLATILE,Volatile qualifier" "VOLATILE_0,VOLATILE_1" bitfld.long 0x00 1. "SIZE,Size of page" "SIZE_0,SIZE_1" bitfld.long 0x00 0. "ENABLE,Enable page" "ENABLE_0,ENABLE_1" group.long 0x1C4++0x03 line.long 0x00 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRESS,Logical source translated address" bitfld.long 0x00 0. "IGNORE,Do not use translated address" "0,1" tree.end width 0x0B tree.end tree "IPU1_UNICACHE_SCTM" base ad:0x58880400 group.long 0x00++0x03 line.long 0x00 "CACHE_SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVISION,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" rgroup.long 0x7C++0x03 line.long 0x00 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" tree "Channel_0" rgroup.long 0x180++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module" group.long 0x108++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" newline bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x100++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" newline bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x40++0x03 line.long 0x00 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_1" rgroup.long 0x184++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module" group.long 0x10C++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" newline bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x104++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" newline bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x44++0x03 line.long 0x00 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_2" rgroup.long 0x188++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module" group.long 0x110++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_3" rgroup.long 0x18C++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module" group.long 0x114++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_4" rgroup.long 0x190++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module" group.long 0x118++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_5" rgroup.long 0x194++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module" group.long 0x11C++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" rgroup.long 0x198++0x07 line.long 0x00 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module" line.long 0x04 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module" tree.end width 0x0B tree.end tree "IPU2_UNICACHE_SCTM" base ad:0x55080400 group.long 0x00++0x03 line.long 0x00 "CACHE_SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVISION,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "ENBL,SCTM global enable" "ENBL_0,ENBL_1" rgroup.long 0x7C++0x03 line.long 0x00 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" tree "Channel_0" rgroup.long 0x180++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module" group.long 0x108++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" newline bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x100++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" newline bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x40++0x03 line.long 0x00 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_1" rgroup.long 0x184++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module" group.long 0x10C++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" newline bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x104++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "RESTART_0,RESTART_1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "DBG_0,DBG_1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "INT_0,INT_1" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" newline bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" group.long 0x44++0x03 line.long 0x00 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_2" rgroup.long 0x188++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module" group.long 0x110++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_3" rgroup.long 0x18C++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module" group.long 0x114++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_4" rgroup.long 0x190++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module" group.long 0x118++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" tree.end tree "Channel_5" rgroup.long 0x194++0x03 line.long 0x00 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module" group.long 0x11C++0x03 line.long 0x00 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter input selection" "INPSEL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 7. "CHNSDW,Counter has a shadow register for chain reads" "CHNSDW_0,CHNSDW_1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last read" "OVRFLW_0,OVRFLW_1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "IDLE_0,IDLE_1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "FREE_0,FREE_1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "DURMODE_0,DURMODE_1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "CHAIN_0,CHAIN_1" newline bitfld.long 0x00 1. "RESET,Counter reset control" "RESET_0,RESET_1" bitfld.long 0x00 0. "ENBL,Counter enable control" "ENBL_0,ENBL_1" rgroup.long 0x198++0x07 line.long 0x00 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module" line.long 0x04 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module" tree.end width 0x0B tree.end tree "IPU1_WUGEN" base ad:0x58881000 group.long 0x00++0x13 line.long 0x00 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other. thus used as a handshake between the two CPUs" bitfld.long 0x00 16. "INT_CORTEX_2,Interrupt to IPUx_C1" "0,1" bitfld.long 0x00 0. "INT_CORTEX_1,Interrupt to IPUx_C0" "0,1" line.long 0x04 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x04 0.--1. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" line.long 0x08 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x08 0.--1. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request" bitfld.long 0x0C 31. "MIRQ31,Interrupt Mask bit 31" "0,1" bitfld.long 0x0C 30. "MIRQ30,Interrupt Mask bit 30" "0,1" bitfld.long 0x0C 29. "MIRQ29,Interrupt Mask bit 29" "0,1" bitfld.long 0x0C 28. "MIRQ28,Interrupt Mask bit 28" "0,1" bitfld.long 0x0C 27. "MIRQ27,Interrupt Mask bit 27" "0,1" bitfld.long 0x0C 26. "MIRQ26,Interrupt Mask bit 26" "0,1" bitfld.long 0x0C 25. "MIRQ25,Interrupt Mask bit 25" "0,1" newline bitfld.long 0x0C 24. "MIRQ24,Interrupt Mask bit 24" "0,1" bitfld.long 0x0C 23. "MIRQ23,Interrupt Mask bit 23" "0,1" bitfld.long 0x0C 22. "MIRQ22,Interrupt Mask bit 22" "0,1" bitfld.long 0x0C 21. "MIRQ21,Interrupt Mask bit 21" "0,1" bitfld.long 0x0C 20. "MIRQ20,Interrupt Mask bit 20" "0,1" bitfld.long 0x0C 19. "MIRQ19,Interrupt Mask bit 19" "0,1" bitfld.long 0x0C 18. "MIRQ18,Interrupt Mask bit 18" "0,1" newline bitfld.long 0x0C 17. "MIRQ17,Interrupt Mask bit 17" "0,1" bitfld.long 0x0C 16. "MIRQ16,Interrupt Mask bit 16" "0,1" bitfld.long 0x0C 15. "MIRQ15,Interrupt Mask bit 15" "0,1" bitfld.long 0x0C 14. "MIRQ14,Interrupt Mask bit 14" "0,1" bitfld.long 0x0C 13. "MIRQ13,Interrupt Mask bit 13" "0,1" bitfld.long 0x0C 12. "MIRQ12,Interrupt Mask bit 12" "0,1" bitfld.long 0x0C 11. "MIRQ11,Interrupt Mask bit 11" "0,1" newline bitfld.long 0x0C 10. "MIRQ10,Interrupt Mask bit 10" "0,1" bitfld.long 0x0C 9. "MIRQ9,Interrupt Mask bit 9" "0,1" bitfld.long 0x0C 8. "MIRQ8,Interrupt Mask bit 8" "0,1" bitfld.long 0x0C 7. "MIRQ7,Interrupt Mask bit 7" "0,1" bitfld.long 0x0C 6. "MIRQ6,Interrupt Mask bit 6" "0,1" bitfld.long 0x0C 5. "MIRQ5,Interrupt Mask bit 5" "0,1" bitfld.long 0x0C 4. "MIRQ4,Interrupt Mask bit 4" "0,1" newline bitfld.long 0x0C 3. "MIRQ3,Interrupt Mask bit 3" "0,1" bitfld.long 0x0C 2. "MIRQ2,Interrupt Mask bit 2" "0,1" bitfld.long 0x0C 1. "MIRQ1,Interrupt Mask bit 1" "0,1" bitfld.long 0x0C 0. "MIRQ0,Interrupt Mask bit 0" "0,1" line.long 0x10 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request" bitfld.long 0x10 31. "MIRQ63,Interrupt Mask bit 63" "0,1" bitfld.long 0x10 30. "MIRQ62,Interrupt Mask bit 62" "0,1" bitfld.long 0x10 29. "MIRQ61,Interrupt Mask bit 61" "0,1" bitfld.long 0x10 28. "MIRQ60,Interrupt Mask bit 60" "0,1" bitfld.long 0x10 27. "MIRQ59,Interrupt Mask bit 59" "0,1" bitfld.long 0x10 26. "MIRQ58,Interrupt Mask bit 58" "0,1" bitfld.long 0x10 25. "MIRQ57,Interrupt Mask bit 57" "0,1" newline bitfld.long 0x10 24. "MIRQ56,Interrupt Mask bit 56" "0,1" bitfld.long 0x10 23. "MIRQ55,Interrupt Mask bit 55" "0,1" bitfld.long 0x10 22. "MIRQ54,Interrupt Mask bit 54" "0,1" bitfld.long 0x10 21. "MIRQ53,Interrupt Mask bit 53" "0,1" bitfld.long 0x10 20. "MIRQ52,Interrupt Mask bit 52" "0,1" bitfld.long 0x10 19. "MIRQ51,Interrupt Mask bit 51" "0,1" bitfld.long 0x10 18. "MIRQ50,Interrupt Mask bit 50" "0,1" newline bitfld.long 0x10 17. "MIRQ49,Interrupt Mask bit 49" "0,1" bitfld.long 0x10 16. "MIRQ48,Interrupt Mask bit 48" "0,1" bitfld.long 0x10 15. "MIRQ47,Interrupt Mask bit 47" "0,1" bitfld.long 0x10 14. "MIRQ46,Interrupt Mask bit 46" "0,1" bitfld.long 0x10 13. "MIRQ45,Interrupt Mask bit 45" "0,1" bitfld.long 0x10 12. "MIRQ44,Interrupt Mask bit 44" "0,1" bitfld.long 0x10 11. "MIRQ43,Interrupt Mask bit 43" "0,1" newline bitfld.long 0x10 10. "MIRQ42,Interrupt Mask bit 42" "0,1" bitfld.long 0x10 9. "MIRQ41,Interrupt Mask bit 41" "0,1" bitfld.long 0x10 8. "MIRQ40,Interrupt Mask bit 40" "0,1" bitfld.long 0x10 7. "MIRQ39,Interrupt Mask bit 39" "0,1" bitfld.long 0x10 6. "MIRQ38,Interrupt Mask bit 38" "0,1" bitfld.long 0x10 5. "MIRQ37,Interrupt Mask bit 37" "0,1" bitfld.long 0x10 4. "MIRQ36,Interrupt Mask bit 36" "0,1" newline bitfld.long 0x10 3. "MIRQ35,Interrupt Mask bit 35" "0,1" bitfld.long 0x10 2. "MIRQ34,Interrupt Mask bit 34" "0,1" bitfld.long 0x10 1. "MIRQ33,Interrupt Mask bit 33" "0,1" bitfld.long 0x10 0. "MIRQ32,Interrupt Mask bit 32" "0,1" width 0x0B tree.end tree "IPU2_WUGEN" base ad:0x55081000 group.long 0x00++0x13 line.long 0x00 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other. thus used as a handshake between the two CPUs" bitfld.long 0x00 16. "INT_CORTEX_2,Interrupt to IPUx_C1" "0,1" bitfld.long 0x00 0. "INT_CORTEX_1,Interrupt to IPUx_C0" "0,1" line.long 0x04 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x04 0.--1. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" line.long 0x08 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x08 0.--1. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request" bitfld.long 0x0C 31. "MIRQ31,Interrupt Mask bit 31" "0,1" bitfld.long 0x0C 30. "MIRQ30,Interrupt Mask bit 30" "0,1" bitfld.long 0x0C 29. "MIRQ29,Interrupt Mask bit 29" "0,1" bitfld.long 0x0C 28. "MIRQ28,Interrupt Mask bit 28" "0,1" bitfld.long 0x0C 27. "MIRQ27,Interrupt Mask bit 27" "0,1" bitfld.long 0x0C 26. "MIRQ26,Interrupt Mask bit 26" "0,1" bitfld.long 0x0C 25. "MIRQ25,Interrupt Mask bit 25" "0,1" newline bitfld.long 0x0C 24. "MIRQ24,Interrupt Mask bit 24" "0,1" bitfld.long 0x0C 23. "MIRQ23,Interrupt Mask bit 23" "0,1" bitfld.long 0x0C 22. "MIRQ22,Interrupt Mask bit 22" "0,1" bitfld.long 0x0C 21. "MIRQ21,Interrupt Mask bit 21" "0,1" bitfld.long 0x0C 20. "MIRQ20,Interrupt Mask bit 20" "0,1" bitfld.long 0x0C 19. "MIRQ19,Interrupt Mask bit 19" "0,1" bitfld.long 0x0C 18. "MIRQ18,Interrupt Mask bit 18" "0,1" newline bitfld.long 0x0C 17. "MIRQ17,Interrupt Mask bit 17" "0,1" bitfld.long 0x0C 16. "MIRQ16,Interrupt Mask bit 16" "0,1" bitfld.long 0x0C 15. "MIRQ15,Interrupt Mask bit 15" "0,1" bitfld.long 0x0C 14. "MIRQ14,Interrupt Mask bit 14" "0,1" bitfld.long 0x0C 13. "MIRQ13,Interrupt Mask bit 13" "0,1" bitfld.long 0x0C 12. "MIRQ12,Interrupt Mask bit 12" "0,1" bitfld.long 0x0C 11. "MIRQ11,Interrupt Mask bit 11" "0,1" newline bitfld.long 0x0C 10. "MIRQ10,Interrupt Mask bit 10" "0,1" bitfld.long 0x0C 9. "MIRQ9,Interrupt Mask bit 9" "0,1" bitfld.long 0x0C 8. "MIRQ8,Interrupt Mask bit 8" "0,1" bitfld.long 0x0C 7. "MIRQ7,Interrupt Mask bit 7" "0,1" bitfld.long 0x0C 6. "MIRQ6,Interrupt Mask bit 6" "0,1" bitfld.long 0x0C 5. "MIRQ5,Interrupt Mask bit 5" "0,1" bitfld.long 0x0C 4. "MIRQ4,Interrupt Mask bit 4" "0,1" newline bitfld.long 0x0C 3. "MIRQ3,Interrupt Mask bit 3" "0,1" bitfld.long 0x0C 2. "MIRQ2,Interrupt Mask bit 2" "0,1" bitfld.long 0x0C 1. "MIRQ1,Interrupt Mask bit 1" "0,1" bitfld.long 0x0C 0. "MIRQ0,Interrupt Mask bit 0" "0,1" line.long 0x10 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request" bitfld.long 0x10 31. "MIRQ63,Interrupt Mask bit 63" "0,1" bitfld.long 0x10 30. "MIRQ62,Interrupt Mask bit 62" "0,1" bitfld.long 0x10 29. "MIRQ61,Interrupt Mask bit 61" "0,1" bitfld.long 0x10 28. "MIRQ60,Interrupt Mask bit 60" "0,1" bitfld.long 0x10 27. "MIRQ59,Interrupt Mask bit 59" "0,1" bitfld.long 0x10 26. "MIRQ58,Interrupt Mask bit 58" "0,1" bitfld.long 0x10 25. "MIRQ57,Interrupt Mask bit 57" "0,1" newline bitfld.long 0x10 24. "MIRQ56,Interrupt Mask bit 56" "0,1" bitfld.long 0x10 23. "MIRQ55,Interrupt Mask bit 55" "0,1" bitfld.long 0x10 22. "MIRQ54,Interrupt Mask bit 54" "0,1" bitfld.long 0x10 21. "MIRQ53,Interrupt Mask bit 53" "0,1" bitfld.long 0x10 20. "MIRQ52,Interrupt Mask bit 52" "0,1" bitfld.long 0x10 19. "MIRQ51,Interrupt Mask bit 51" "0,1" bitfld.long 0x10 18. "MIRQ50,Interrupt Mask bit 50" "0,1" newline bitfld.long 0x10 17. "MIRQ49,Interrupt Mask bit 49" "0,1" bitfld.long 0x10 16. "MIRQ48,Interrupt Mask bit 48" "0,1" bitfld.long 0x10 15. "MIRQ47,Interrupt Mask bit 47" "0,1" bitfld.long 0x10 14. "MIRQ46,Interrupt Mask bit 46" "0,1" bitfld.long 0x10 13. "MIRQ45,Interrupt Mask bit 45" "0,1" bitfld.long 0x10 12. "MIRQ44,Interrupt Mask bit 44" "0,1" bitfld.long 0x10 11. "MIRQ43,Interrupt Mask bit 43" "0,1" newline bitfld.long 0x10 10. "MIRQ42,Interrupt Mask bit 42" "0,1" bitfld.long 0x10 9. "MIRQ41,Interrupt Mask bit 41" "0,1" bitfld.long 0x10 8. "MIRQ40,Interrupt Mask bit 40" "0,1" bitfld.long 0x10 7. "MIRQ39,Interrupt Mask bit 39" "0,1" bitfld.long 0x10 6. "MIRQ38,Interrupt Mask bit 38" "0,1" bitfld.long 0x10 5. "MIRQ37,Interrupt Mask bit 37" "0,1" bitfld.long 0x10 4. "MIRQ36,Interrupt Mask bit 36" "0,1" newline bitfld.long 0x10 3. "MIRQ35,Interrupt Mask bit 35" "0,1" bitfld.long 0x10 2. "MIRQ34,Interrupt Mask bit 34" "0,1" bitfld.long 0x10 1. "MIRQ33,Interrupt Mask bit 33" "0,1" bitfld.long 0x10 0. "MIRQ32,Interrupt Mask bit 32" "0,1" width 0x0B tree.end tree.end tree "Dynamic_Memory_Manager" base ad:0x4E000000 tree "Channel_0" group.long 0x40++0x03 line.long 0x00 "DMM_LISA_MAP_i_0,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" newline bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "No interleaving,128-byte interleaving,256-byte interleaving,512-byte interleaving The 128-/256-/512-byte.." bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" newline bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "Unmapped,Mapped on EMIF1 only (not interleaved),Mapped on EMIF2 only (not interleaved),Mapped on EMIF1 and EMIF2 (interleaved) To.." hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x504++0x0B line.long 0x00 "DMM_PAT_AREA_i_0,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" newline hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_0,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" newline bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_0,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x500++0x03 line.long 0x00 "DMM_PAT_DESCR_i_0,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C0++0x03 line.long 0x00 "DMM_PAT_STATUS_i_0,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" newline bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" newline bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x440++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_0,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" group.long 0x620++0x03 line.long 0x00 "DMM_PEG_PRIO_k_0,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_1" group.long 0x44++0x03 line.long 0x00 "DMM_LISA_MAP_i_1,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" newline bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "No interleaving,128-byte interleaving,256-byte interleaving,512-byte interleaving The 128-/256-/512-byte.." bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" newline bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "Unmapped,Mapped on EMIF1 only (not interleaved),Mapped on EMIF2 only (not interleaved),Mapped on EMIF1 and EMIF2 (interleaved) To.." hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x514++0x0B line.long 0x00 "DMM_PAT_AREA_i_1,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" newline hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_1,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" newline bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_1,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x510++0x03 line.long 0x00 "DMM_PAT_DESCR_i_1,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C4++0x03 line.long 0x00 "DMM_PAT_STATUS_i_1,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" newline bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" newline bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x444++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_1,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" group.long 0x624++0x03 line.long 0x00 "DMM_PEG_PRIO_k_1,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" group.long 0x48++0x03 line.long 0x00 "DMM_LISA_MAP_i_2,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" newline bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "No interleaving,128-byte interleaving,256-byte interleaving,512-byte interleaving The 128-/256-/512-byte.." bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" newline bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "Unmapped,Mapped on EMIF1 only (not interleaved),Mapped on EMIF2 only (not interleaved),Mapped on EMIF1 and EMIF2 (interleaved) To.." hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x524++0x0B line.long 0x00 "DMM_PAT_AREA_i_2,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" newline hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_2,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" newline bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_2,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x520++0x03 line.long 0x00 "DMM_PAT_DESCR_i_2,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C8++0x03 line.long 0x00 "DMM_PAT_STATUS_i_2,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" newline bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" newline bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x448++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_2,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" group.long 0x628++0x03 line.long 0x00 "DMM_PEG_PRIO_k_2,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" group.long 0x4C++0x03 line.long 0x00 "DMM_LISA_MAP_i_3,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" newline bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "No interleaving,128-byte interleaving,256-byte interleaving,512-byte interleaving The 128-/256-/512-byte.." bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" newline bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "Unmapped,Mapped on EMIF1 only (not interleaved),Mapped on EMIF2 only (not interleaved),Mapped on EMIF1 and EMIF2 (interleaved) To.." hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x534++0x0B line.long 0x00 "DMM_PAT_AREA_i_3,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" newline hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_3,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" newline bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_3,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x530++0x03 line.long 0x00 "DMM_PAT_DESCR_i_3,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4CC++0x03 line.long 0x00 "DMM_PAT_STATUS_i_3,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" newline bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" newline bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x44C++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_3,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" group.long 0x62C++0x13 line.long 0x00 "DMM_PEG_PRIO_k_3,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" line.long 0x04 "DMM_PEG_PRIO_k_4,DMM PEG Priority register" bitfld.long 0x04 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x04 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x04 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x04 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x04 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x04 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x04 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x04 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x04 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" line.long 0x08 "DMM_PEG_PRIO_k_5,DMM PEG Priority register" bitfld.long 0x08 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x08 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x08 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x08 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x08 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x08 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x08 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x08 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x08 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" line.long 0x0C "DMM_PEG_PRIO_k_6,DMM PEG Priority register" bitfld.long 0x0C 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x0C 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x0C 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x0C 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x0C 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x0C 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x0C 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x0C 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x0C 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" line.long 0x10 "DMM_PEG_PRIO_k_7,DMM PEG Priority register" bitfld.long 0x10 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x10 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x10 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x10 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x10 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x10 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x10 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x10 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x10 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" tree.end group.long 0x20++0x03 line.long 0x00 "DMM_EMERGENCY,DMM memory mapping register" bitfld.long 0x00 16.--20. "WEIGHT,Weight for the LISA arbitration when any bit of the vector Mflag[63:0] is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 1.--15. 1. "Reserved,Reserved" bitfld.long 0x00 0. "ENABLE," "?,ENABLE_1" rgroup.long 0x04++0x07 line.long 0x00 "DMM_HWINFO,DMM hardware configuration" bitfld.long 0x00 8.--11. "SDRC_CNT,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. "SECTION_CNT,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMM_LISA_HWINFO,DMM hardware configuration for LISA" bitfld.long 0x04 8.--11. "SDRC_CNT,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--4. "SECTION_CNT,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x03 line.long 0x00 "DMM_LISA_LOCK,DMM memory mapping lock" bitfld.long 0x00 0. "LOCK,DMM lock map - UNLOCKED" "LOCK_0_r,LOCK_1_w" group.long 0x410++0x03 line.long 0x00 "DMM_PAT_CONFIG,This is the PAT configuration register aimed at defining the major PAT configuration of each refill engine" bitfld.long 0x00 3. "MODE3,Mode of refill engine" "MODE3_0,MODE3_1" bitfld.long 0x00 2. "MODE2,Mode of refill engine" "MODE2_0,MODE2_1" bitfld.long 0x00 1. "MODE1,Mode of refill engine" "MODE1_0,MODE1_1" bitfld.long 0x00 0. "MODE0,Mode of refill engine" "MODE0_0,MODE0_1" rgroup.long 0x40C++0x03 line.long 0x00 "DMM_PAT_GEOMETRY,PAT geometry-related settings" bitfld.long 0x00 24.--26. "CONT_HGHT,Container height in pages - 32" "?,CONT_HGHT_1_r,CONT_HGHT_2_r,?,CONT_HGHT_4_r,?,?,?" bitfld.long 0x00 16.--19. "CONT_WDTH,Container width in pages - 64" "?,?,CONT_WDTH_2_r,?,CONT_WDTH_4_r,?,?,?,CONT_WDTH_8_r,?,?,?,?,?,?,?" bitfld.long 0x00 8.--13. "ADDR_RANGE,PAT output physical address range - 128MB" "?,ADDR_RANGE_1_r,ADDR_RANGE_2_r,?,ADDR_RANGE_4_r,?,?,?,ADDR_RANGE_8_r,?,?,?,?,?,?,?,ADDR_RANGE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ADDR_RANGE_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--4. "PAGE_SZ,Page size in 4-kiB granularity - 4KB" "?,PAGE_SZ_1_r,?,?,PAGE_SZ_4_r,?,?,?,?,?,?,?,?,?,?,?,PAGE_SZ_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x408++0x03 line.long 0x00 "DMM_PAT_HWINFO,DMM hardware configuration for PAT" bitfld.long 0x00 24.--28. "ENGINE_CNT,Number of PAT refill engines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "LUT_CNT,Number of PAT LUT for page-grained physical address translation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. "VIEW_MAP_CNT,Number of internal PAT view mappings" "?,VIEW_MAP_CNT_1_r,VIEW_MAP_CNT_2_r,?,VIEW_MAP_CNT_4_r,?,?,?,VIEW_MAP_CNT_8_r,?,?,?,?,?,?,?" hexmask.long.byte 0x00 0.--6. 1. "VIEW_CNT,Number of PAT view entries - 1" group.long 0x478++0x03 line.long 0x00 "DMM_PAT_IRQ_EOI,PAT end of interrupt" bitfld.long 0x00 0. "EOI,End of PAT interrupt - ACK" "EOI_0,?" group.long 0x4B0++0x03 line.long 0x00 "DMM_PAT_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill interrupt source mask for the last descriptior in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill interrupt source mask for any descriptior in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill interrupt source mask for the last descriptior in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill interrupt source mask for any descriptior in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill interrupt source mask for the last descriptior in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill interrupt source mask for any descriptior in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill interrupt source mask for the last descriptior in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill interrupt source mask for any descriptior in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x4A0++0x03 line.long 0x00 "DMM_PAT_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill interrupt source mask for the last descriptior in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill interrupt source mask for any descriptior in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill interrupt source mask for the last descriptior in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill interrupt source mask for any descriptior in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill interrupt source mask for the last descriptior in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill interrupt source mask for any descriptior in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill interrupt source mask for the last descriptior in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill interrupt source mask for any descriptior in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x490++0x03 line.long 0x00 "DMM_PAT_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Data register update whilst refilling error event in area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Control register update whilst refilling error event in area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Area register update whilst refilling error event in area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer error event in area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer error event in area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill event for the last descriptor in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill event for any descriptor in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Data register update whilst refilling error event in area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Control register update whilst refilling error event in area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Area register update whilst refilling error event in area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer error event in area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer error event in area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill event for the last descriptor in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill event for any descriptor in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Data register update whilst refilling error event in area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Control register update whilst refilling error event in area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Area register update whilst refilling error event in area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer error event in area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer error event in area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill event for the last descriptor in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill event for any descriptor in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Data register update whilst refilling error event in area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Control register update whilst refilling error event in area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Area register update whilst refilling error event in area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer error event in area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer error event in area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill event for the last descriptor in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill event for any descriptor in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x480++0x03 line.long 0x00 "DMM_PAT_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Data register update whilst refilling error event in area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Control register update whilst refilling error event in area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Area register update whilst refilling error event in area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer error event in area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer error event in area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill event for the last descriptor in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill event for any descriptor in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Data register update whilst refilling error event in area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Control register update whilst refilling error event in area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Area register update whilst refilling error event in area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer error event in area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer error event in area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill event for the last descriptor in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill event for any descriptor in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Data register update whilst refilling error event in area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Control register update whilst refilling error event in area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Area register update whilst refilling error event in area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer error event in area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer error event in area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill event for the last descriptor in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill event for any descriptor in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Data register update whilst refilling error event in area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Control register update whilst refilling error event in area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Area register update whilst refilling error event in area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer error event in area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer error event in area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill event for the last descriptor in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill event for any descriptor in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x420++0x07 line.long 0x00 "DMM_PAT_VIEW0,DMM PAT View register (initiators 0 to 7)" bitfld.long 0x00 31. "W7,Write-enable for V7 bit field" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--29. "V7,PAT view for initiator 7" "0,1,2,3" bitfld.long 0x00 27. "W6,Write-enable for V6 bit field" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--25. "V6,PAT view for initiator 6" "0,1,2,3" newline bitfld.long 0x00 23. "W5,Write-enable for V5 bit field" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--21. "V5,PAT view for initiator 5" "0,1,2,3" bitfld.long 0x00 19. "W4,Write-enable for V4 bit field" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--17. "V4,PAT view for initiator 4" "0,1,2,3" newline bitfld.long 0x00 15. "W3,Write-enable for V3 bit field" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--13. "V3,PAT view for initiator 3" "0,1,2,3" bitfld.long 0x00 11. "W2,Write-enable for V2 bit field" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--9. "V2,PAT view for initiator 2" "0,1,2,3" newline bitfld.long 0x00 7. "W1,Write-enable for V1 bit field" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--5. "V1,PAT view for initiator 1" "0,1,2,3" bitfld.long 0x00 3. "W0,Write-enable for V0 bit field" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--1. "V0,PAT view for initiator 0" "0,1,2,3" line.long 0x04 "DMM_PAT_VIEW1,DMM PAT view register (initiators 8 to 15)" bitfld.long 0x04 31. "W15,Write-enable for V15 bit field" "W15_0_w,W15_1_w" bitfld.long 0x04 28.--29. "V15,PAT view for initiator 15" "0,1,2,3" bitfld.long 0x04 27. "W14,Write-enable for V14 bit field" "W14_0_w,W14_1_w" bitfld.long 0x04 24.--25. "V14,PAT view for initiator 14" "0,1,2,3" newline bitfld.long 0x04 23. "W13,Write-enable for V13 bit field" "W13_0_w,W13_1_w" bitfld.long 0x04 20.--21. "V13,PAT view for initiator 13" "0,1,2,3" bitfld.long 0x04 19. "W12,Write-enable for V12 bit field" "W12_0_w,W12_1_w" bitfld.long 0x04 16.--17. "V12,PAT view for initiator 12" "0,1,2,3" newline bitfld.long 0x04 15. "W11,Write-enable for V11 bit field" "W11_0_w,W11_1_w" bitfld.long 0x04 12.--13. "V11,PAT view for initiator 11" "0,1,2,3" bitfld.long 0x04 11. "W10,Write-enable for V10 bit field" "W10_0_w,W10_1_w" bitfld.long 0x04 8.--9. "V10,PAT view for initiator 10" "0,1,2,3" newline bitfld.long 0x04 7. "W9,Write-enable for V9 bit field" "W9_0_w,W9_1_w" bitfld.long 0x04 4.--5. "V9,PAT view for initiator 9" "0,1,2,3" bitfld.long 0x04 3. "W8,Write-enable for V8 bit field" "W8_0_w,W8_1_w" bitfld.long 0x04 0.--1. "V8,PAT view for initiator 8" "0,1,2,3" group.long 0x460++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_BASE,Base address of all view mappings" bitfld.long 0x00 31. "BASE_ADDR,MSB of the PAT view mapping base address" "0,1" rgroup.long 0x608++0x03 line.long 0x00 "DMM_PEG_HWINFO,DMM hardware configuration for PEG" hexmask.long.byte 0x00 0.--6. 1. "PRIO_CNT,Number of PEG priority entries - 1" group.long 0x640++0x03 line.long 0x00 "DMM_PEG_PRIO_PAT,DMM PEG priority register for the internal PAT engine" bitfld.long 0x00 3. "W_PAT,Write-enable for P_PAT bit field - UPDATE" "W_PAT_0_w,W_PAT_1_w" bitfld.long 0x00 0.--2. "P_PAT,Priority for PAT engine" "0,1,2,3,4,5,6,7" rgroup.long 0x00++0x03 line.long 0x00 "DMM_REVISION,DMM revision number" group.long 0x10++0x03 line.long 0x00 "DMM_SYSCONFIG,DMM clock management configuration" bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "IDLE_MODE_0,IDLE_MODE_1,IDLE_MODE_2,IDLE_MODE_3" rgroup.long 0x208++0x03 line.long 0x00 "DMM_TILER_HWINFO,DMM hardware configuration for TILER" hexmask.long.byte 0x00 0.--6. 1. "OR_CNT,Number of TILER orientation entries - 4" group.long 0x220++0x07 line.long 0x00 "DMM_TILER_OR0,DMM TILER orientation (initiators 0 to 7)" bitfld.long 0x00 31. "W7,Write-enable for OR7 bit field" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "OR7,Orientation for initiator 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. "W6,Write-enable for OR6 bit field" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "OR6,Orientation for initiator 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for OR5 bit field" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "OR5,Orientation for initiator 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. "W4,Write-enable for OR4 bit field" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "OR4,Orientation for initiator 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for OR3 bit field" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "OR3,Orientation for initiator 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. "W2,Write-enable for OR2 bit field" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "OR2,Orientation for initiator 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for OR1 bit field" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "OR1,Orientation for initiator 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "W0,Write-enable for OR0 bit field" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "OR0,Orientation for initiator 0" "0,1,2,3,4,5,6,7" line.long 0x04 "DMM_TILER_OR1,DMM TILER orientation (initiators 8 to 15)" bitfld.long 0x04 31. "W15,Write-enable for OR15 bit field" "W15_0_w,W15_1_w" bitfld.long 0x04 28.--30. "OR15,Orientation for initiator 15" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27. "W14,Write-enable for OR14 bit field" "W14_0_w,W14_1_w" bitfld.long 0x04 24.--26. "OR14,Orientation for initiator 14" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 23. "W13,Write-enable for OR13 bit field" "W13_0_w,W13_1_w" bitfld.long 0x04 20.--22. "OR13,Orientation for initiator 13" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. "W12,Write-enable for OR12 bit field" "W12_0_w,W12_1_w" bitfld.long 0x04 16.--18. "OR12,Orientation for initiator 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 15. "W11,Write-enable for OR11 bit field" "W11_0_w,W11_1_w" bitfld.long 0x04 12.--14. "OR11,Orientation for initiator 11" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "W10,Write-enable for OR10 bit field" "W10_0_w,W10_1_w" bitfld.long 0x04 8.--10. "OR10,Orientation for initiator 10" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "W9,Write-enable for OR9 bit field" "W9_0_w,W9_1_w" bitfld.long 0x04 4.--6. "OR9,Orientation for initiator 9" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "W8,Write-enable for OR8 bit field" "W8_0_w,W8_1_w" bitfld.long 0x04 0.--2. "OR8,Orientation for initiator 8" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "Embedded_Vision_Engine_EVE_Subsystem" repeat 2. (list 1. 2. )(list ad:0x42000000 ad:0x42100000 ) tree "EVE$1" base $2 group.long 0x8068C++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_CLR," group.long 0x80688++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_SET," group.long 0x80684++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS," rgroup.long 0x80680++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," group.long 0x8069C++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_CLR," group.long 0x80698++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_SET," group.long 0x80694++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS," rgroup.long 0x80690++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS_RAW," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" group.long 0x8020C++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_CLR," group.long 0x80208++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_SET," group.long 0x80204++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS," group.long 0x80200++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," tree "Channel_0" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end tree "Channel_1" group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80718++0x07 line.long 0x00 "EVE_GPOUTm_CLR_1," line.long 0x04 "EVE_GPOUTm_PULSE_1," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80424++0x03 line.long 0x00 "MISR2_Dk_1," group.long 0x80304++0x03 line.long 0x00 "MMR_LOCKi_1,MMR Lock/Unlock register" tree.end group.long 0x80014++0x03 line.long 0x00 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x00 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x00 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." group.long 0x80794++0x03 line.long 0x00 "EVE_CME_DONE_EN," abitfld.long 0x00 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" group.long 0x80780++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80788++0x07 line.long 0x00 "EVE_CME_DONE_GPOUT_CLR," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_PULSE," abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" group.long 0x80784++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT_SET," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80790++0x03 line.long 0x00 "EVE_CME_DONE_SEL," bitfld.long 0x00 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE1),driven by eve_cme_done_gpout[8+n] (from EVE2),?..." group.long 0x80FE8++0x03 line.long 0x00 "EVE_DBGOUT," hexmask.long.tbyte 0x00 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline bitfld.long 0x00 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80010++0x03 line.long 0x00 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x00 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline bitfld.long 0x00 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" group.long 0x80090++0x0F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" group.long 0x800F8++0x03 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8012C++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80128++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80124++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80120++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" group.long 0x800FC++0x03 line.long 0x00 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8051C++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_CLR," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80518++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_SET," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80514++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS," abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80510++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end rgroup.long 0x80004++0x03 line.long 0x00 "EVE_HWINFO," hexmask.long 0x00 4.--31. 1. "INFO," newline bitfld.long 0x00 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800B0++0x0F line.long 0x00 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x0C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80020++0x03 line.long 0x00 "EVE_MEMMAP," bitfld.long 0x00 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline bitfld.long 0x00 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" group.long 0x8001C++0x03 line.long 0x00 "EVE_MMU_CONFIG," bitfld.long 0x00 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x00 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" group.long 0x80024++0x07 line.long 0x00 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x00 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline bitfld.long 0x00 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline bitfld.long 0x00 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x00 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline bitfld.long 0x00 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x04 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x04 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" group.long 0x8011C++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." group.long 0x80118++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." group.long 0x80114++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." group.long 0x80110++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." rgroup.long 0x8002C++0x03 line.long 0x00 "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80050++0x07 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80058++0x0F line.long 0x00 "EVE_PC_ISAR,Invalidate single address register" line.long 0x04 "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x04 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x08 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x0C "EVE_PC_PBC," hexmask.long.word 0x0C 0.--15. 1. "BC,Preload Byte Count register" rgroup.long 0x80FE0++0x07 line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" rgroup.long 0x80000++0x03 line.long 0x00 "EVE_REVISION," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end rgroup.long 0x8000C++0x03 line.long 0x00 "EVE_STAT," bitfld.long 0x00 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x00 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline bitfld.long 0x00 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x00 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x00 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x00 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x00 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x00 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x00 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" group.long 0x80008++0x03 line.long 0x00 "EVE_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x00 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x00 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x00 0. "SOFTRESET,Reserved" "0,1" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," group.long 0x80018++0x03 line.long 0x00 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x00 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" newline bitfld.long 0x00 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x00 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" group.long 0x800A0++0x0F line.long 0x00 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x0C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" tree "IRQ_Line_10" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end tree "IRQ_Line_11" group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," tree.end tree "IRQ_Line_12" group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," tree.end tree "IRQ_Line_13" group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," tree.end tree "IRQ_Line_2" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end tree "IRQ_Line_3" group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x8042C++0x03 line.long 0x00 "MISR2_Dk_3," group.long 0x8030C++0x03 line.long 0x00 "MMR_LOCKi_3,MMR Lock/Unlock register" tree.end tree "IRQ_Line_4" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end tree "IRQ_Line_5" group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80314++0x03 line.long 0x00 "MMR_LOCKi_5,MMR Lock/Unlock register" tree.end tree "IRQ_Line_6" group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80318++0x03 line.long 0x00 "MMR_LOCKi_6,MMR Lock/Unlock register" tree.end tree "IRQ_Line_7" group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x8031C++0x03 line.long 0x00 "MMR_LOCKi_7,MMR Lock/Unlock register" tree.end tree "IRQ_Line_8" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end tree "IRQ_Line_9" group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," group.long 0x80324++0x03 line.long 0x00 "MMR_LOCKi_9,MMR Lock/Unlock register" tree.end group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80404++0x03 line.long 0x00 "MISR_CLEAR," bitfld.long 0x00 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80400++0x03 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." width 0x0B tree.end repeat.end tree "EVE1_DSP" base ad:0x2000000 group.long 0x8068C++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_CLR," group.long 0x80688++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_SET," group.long 0x80684++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS," rgroup.long 0x80680++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," group.long 0x8069C++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_CLR," group.long 0x80698++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_SET," group.long 0x80694++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS," rgroup.long 0x80690++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS_RAW," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" group.long 0x8020C++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_CLR," group.long 0x80208++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_SET," group.long 0x80204++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS," group.long 0x80200++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," tree "Channel_0" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end tree "Channel_1" group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80718++0x07 line.long 0x00 "EVE_GPOUTm_CLR_1," line.long 0x04 "EVE_GPOUTm_PULSE_1," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80424++0x03 line.long 0x00 "MISR2_Dk_1," group.long 0x80304++0x03 line.long 0x00 "MMR_LOCKi_1,MMR Lock/Unlock register" tree.end group.long 0x80014++0x03 line.long 0x00 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x00 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x00 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." group.long 0x80794++0x03 line.long 0x00 "EVE_CME_DONE_EN," abitfld.long 0x00 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" group.long 0x80780++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80788++0x07 line.long 0x00 "EVE_CME_DONE_GPOUT_CLR," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_PULSE," abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" group.long 0x80784++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT_SET," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80790++0x03 line.long 0x00 "EVE_CME_DONE_SEL," bitfld.long 0x00 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE1),driven by eve_cme_done_gpout[8+n] (from EVE2),?..." group.long 0x80FE8++0x03 line.long 0x00 "EVE_DBGOUT," hexmask.long.tbyte 0x00 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline bitfld.long 0x00 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80010++0x03 line.long 0x00 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x00 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline bitfld.long 0x00 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" group.long 0x80090++0x0F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" group.long 0x800F8++0x03 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8012C++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80128++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80124++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80120++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" group.long 0x800FC++0x03 line.long 0x00 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8051C++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_CLR," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80518++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_SET," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80514++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS," abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80510++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end rgroup.long 0x80004++0x03 line.long 0x00 "EVE_HWINFO," hexmask.long 0x00 4.--31. 1. "INFO," newline bitfld.long 0x00 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800B0++0x0F line.long 0x00 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x0C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80020++0x03 line.long 0x00 "EVE_MEMMAP," bitfld.long 0x00 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline bitfld.long 0x00 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" group.long 0x8001C++0x03 line.long 0x00 "EVE_MMU_CONFIG," bitfld.long 0x00 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x00 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" group.long 0x80024++0x07 line.long 0x00 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x00 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline bitfld.long 0x00 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline bitfld.long 0x00 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x00 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline bitfld.long 0x00 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x04 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x04 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" group.long 0x8011C++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." group.long 0x80118++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." group.long 0x80114++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." group.long 0x80110++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." rgroup.long 0x8002C++0x03 line.long 0x00 "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80050++0x07 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80058++0x0F line.long 0x00 "EVE_PC_ISAR,Invalidate single address register" line.long 0x04 "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x04 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x08 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x0C "EVE_PC_PBC," hexmask.long.word 0x0C 0.--15. 1. "BC,Preload Byte Count register" rgroup.long 0x80FE0++0x07 line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" rgroup.long 0x80000++0x03 line.long 0x00 "EVE_REVISION," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end rgroup.long 0x8000C++0x03 line.long 0x00 "EVE_STAT," bitfld.long 0x00 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x00 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline bitfld.long 0x00 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x00 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x00 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x00 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x00 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x00 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x00 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" group.long 0x80008++0x03 line.long 0x00 "EVE_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x00 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x00 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x00 0. "SOFTRESET,Reserved" "0,1" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," group.long 0x80018++0x03 line.long 0x00 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x00 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" newline bitfld.long 0x00 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x00 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" group.long 0x800A0++0x0F line.long 0x00 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x0C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" tree "IRQ_Line_10" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end tree "IRQ_Line_11" group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," tree.end tree "IRQ_Line_12" group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," tree.end tree "IRQ_Line_13" group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," tree.end tree "IRQ_Line_2" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end tree "IRQ_Line_3" group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x8042C++0x03 line.long 0x00 "MISR2_Dk_3," group.long 0x8030C++0x03 line.long 0x00 "MMR_LOCKi_3,MMR Lock/Unlock register" tree.end tree "IRQ_Line_4" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end tree "IRQ_Line_5" group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80314++0x03 line.long 0x00 "MMR_LOCKi_5,MMR Lock/Unlock register" tree.end tree "IRQ_Line_6" group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80318++0x03 line.long 0x00 "MMR_LOCKi_6,MMR Lock/Unlock register" tree.end tree "IRQ_Line_7" group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x8031C++0x03 line.long 0x00 "MMR_LOCKi_7,MMR Lock/Unlock register" tree.end tree "IRQ_Line_8" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end tree "IRQ_Line_9" group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," group.long 0x80324++0x03 line.long 0x00 "MMR_LOCKi_9,MMR Lock/Unlock register" tree.end group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80404++0x03 line.long 0x00 "MISR_CLEAR," bitfld.long 0x00 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80400++0x03 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." width 0x0B tree.end tree "EVE2_DSP" base ad:0x2100000 group.long 0x8068C++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_CLR," group.long 0x80688++0x03 line.long 0x00 "ARP32_INT14_IRQENABLE_SET," group.long 0x80684++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS," rgroup.long 0x80680++0x03 line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," group.long 0x8069C++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_CLR," group.long 0x80698++0x03 line.long 0x00 "ARP32_INT15_IRQENABLE_SET," group.long 0x80694++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS," rgroup.long 0x80690++0x03 line.long 0x00 "ARP32_INT15_IRQSTATUS_RAW," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" abitfld.long 0x00 0.--23. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" "0x000000=Interrupt #n disabled for wakeup,0x000001=Interrupt #n enabled for wakeup" group.long 0x8020C++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_CLR," group.long 0x80208++0x03 line.long 0x00 "ARP32_NMI_IRQENABLE_SET," group.long 0x80204++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS," group.long 0x80200++0x03 line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," tree "Channel_0" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end tree "Channel_1" group.long 0x80710++0x03 line.long 0x00 "EVE_GPOUTm_1," group.long 0x80718++0x07 line.long 0x00 "EVE_GPOUTm_CLR_1," line.long 0x04 "EVE_GPOUTm_PULSE_1," group.long 0x80714++0x03 line.long 0x00 "EVE_GPOUTm_SET_1," group.long 0x8053C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_1," group.long 0x80538++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_1," group.long 0x80534++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_1," group.long 0x80530++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_1," group.long 0x80424++0x03 line.long 0x00 "MISR2_Dk_1," group.long 0x80304++0x03 line.long 0x00 "MMR_LOCKi_1,MMR Lock/Unlock register" tree.end group.long 0x80014++0x03 line.long 0x00 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x00 12.--13. "TC1_DBS,TC1 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 8.--9. "TC0_DBS,TC0 default burst size" "16 byte,32 byte,64 byte,128 byte.." newline bitfld.long 0x00 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x00 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "Reserved,1 request in flight allowed,2 requests in flight allowed,?..." group.long 0x80794++0x03 line.long 0x00 "EVE_CME_DONE_EN," abitfld.long 0x00 0.--7. "EN,EVE CME Done EN #n" "0x00=EVE CME Done #n is disabled,0x01=EVE CME Done #n is enabled" group.long 0x80780++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done Output #n" "0x00=Drive Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80788++0x07 line.long 0x00 "EVE_CME_DONE_GPOUT_CLR," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" line.long 0x04 "EVE_CME_DONE_GPOUT_PULSE," abitfld.long 0x04 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done #n is high/1" group.long 0x80784++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT_SET," abitfld.long 0x00 0.--7. "EVENT,Internal CME Done #n" "0x00=Internal CME Done #n is low/0,0x01=Internal CME Done is high/1" group.long 0x80790++0x03 line.long 0x00 "EVE_CME_DONE_SEL," bitfld.long 0x00 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "Driven by EDMA cc_int0,Driven by EDMA cc_int1,Driven by EDMA cc_int2,Driven by EDMA cc_int3,Driven by EDMA cc_int4,Driven by EDMA cc_int5,Driven by EDMA cc_int6,Driven by EDMA cc_int7,Driven by EVE_CME_DONE_GPOUTn,driven by eve_cme_done_gpout[0+n] (from EVE1),driven by eve_cme_done_gpout[8+n] (from EVE2),?..." group.long 0x80FE8++0x03 line.long 0x00 "EVE_DBGOUT," hexmask.long.tbyte 0x00 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" newline bitfld.long 0x00 0.--3. "GROUP,Debug Group Output control : mux select" "disabled / all debug outputs driven to 0x0,select output group1,select output group2,?..." group.long 0x80010++0x03 line.long 0x00 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x00 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" newline bitfld.long 0x00 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" group.long 0x80090++0x0F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" group.long 0x800F8++0x03 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8012C++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80128++0x03 line.long 0x00 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80124++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80120++0x03 line.long 0x00 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" abitfld.long 0x00 0.--15. "EVENT,settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" group.long 0x800FC++0x03 line.long 0x00 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" abitfld.long 0x00 0.--15. "ENABLE,Disconnect Enable for Event #n" "0x0000=Disconnect disabled,0x0001=Disconnect enabled" group.long 0x8051C++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_CLR," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Disable interrupt (i.e. / clear ENABLEn.." group.long 0x80518++0x03 line.long 0x00 "EVE_ED_OUT_IRQENABLE_SET," abitfld.long 0x00 0.--15. "ENABLE,Enable for event #n" "0x0000=Interrupt disabled,0x0001=Enable interrupt" group.long 0x80514++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS," abitfld.long 0x00 0.--15. "EVENT,Clearable / enabled status for event #N" "0x0000=No (enabled) event pending,0x0001=Clear raw event" group.long 0x80510++0x03 line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," abitfld.long 0x00 0.--15. "EVENT,Settable raw status for event #n" "0x0000=No event pending,0x0001=Set event (for debug)" repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end rgroup.long 0x80004++0x03 line.long 0x00 "EVE_HWINFO," hexmask.long 0x00 4.--31. 1. "INFO," newline bitfld.long 0x00 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800B0++0x0F line.long 0x00 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x0C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80020++0x03 line.long 0x00 "EVE_MEMMAP," bitfld.long 0x00 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" newline bitfld.long 0x00 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" group.long 0x8001C++0x03 line.long 0x00 "EVE_MMU_CONFIG," bitfld.long 0x00 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" newline bitfld.long 0x00 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x00 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" group.long 0x80024++0x07 line.long 0x00 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x00 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" newline bitfld.long 0x00 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" newline bitfld.long 0x00 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x00 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" newline bitfld.long 0x00 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x04 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x04 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" group.long 0x8011C++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Disable interrupt (i.e. / clear ENABLEn bit),?..." group.long 0x80118++0x03 line.long 0x00 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x00 0.--3. "ENABLE,Enable for event #n" "Interrupt disabled,Enable interrupt,?..." group.long 0x80114++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,Clearable / enabled status for event #N" "No (enabled) event pending,Clear raw event,?..." group.long 0x80110++0x03 line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "No event pending,Set event (for debug),?..." rgroup.long 0x8002C++0x03 line.long 0x00 "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80050++0x07 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "Invalidate operation complete / or not in progress,Invalidate operation still in progress" group.long 0x80058++0x0F line.long 0x00 "EVE_PC_ISAR,Invalidate single address register" line.long 0x04 "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x04 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x08 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x0C "EVE_PC_PBC," hexmask.long.word 0x0C 0.--15. 1. "BC,Preload Byte Count register" rgroup.long 0x80FE0++0x07 line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" newline rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" rgroup.long 0x80000++0x03 line.long 0x00 "EVE_REVISION," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end rgroup.long 0x8000C++0x03 line.long 0x00 "EVE_STAT," bitfld.long 0x00 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,OCPI_DISC_STAT_2,?" newline bitfld.long 0x00 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,ARP32_DISC_STATUS_2,?" newline bitfld.long 0x00 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x00 7. "ARP32_INTC_STAT,Interrupt Controller Status" "ARP32_INTC_STAT_0,ARP32_INTC_STAT_1" newline bitfld.long 0x00 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" newline bitfld.long 0x00 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x00 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" newline bitfld.long 0x00 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" newline bitfld.long 0x00 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" group.long 0x80008++0x03 line.long 0x00 "EVE_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE," "?,No-Standby,Smart-Standby,Smart-Standby-Wkup" newline bitfld.long 0x00 2.--3. "IDLEMODE," "?,No-idle,Smart-idle,SmartIdleWkup" newline rbitfld.long 0x00 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x00 0. "SOFTRESET,Reserved" "0,1" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," group.long 0x80018++0x03 line.long 0x00 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x00 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" newline bitfld.long 0x00 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" newline bitfld.long 0x00 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" group.long 0x800A0++0x0F line.long 0x00 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x00 1. "INV," "Error detection logic is not inverted,Error detection logic is inverted" newline bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" newline bitfld.long 0x04 3. "SYSERR," "0,1" newline bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" newline bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x0C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" tree "IRQ_Line_10" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end tree "IRQ_Line_11" group.long 0x8063C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_11," group.long 0x80638++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_11," group.long 0x80634++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_11," rgroup.long 0x80630++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_11," tree.end tree "IRQ_Line_12" group.long 0x8064C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_12," group.long 0x80648++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_12," group.long 0x80644++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_12," rgroup.long 0x80640++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_12," tree.end tree "IRQ_Line_13" group.long 0x8065C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_13," group.long 0x80658++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_13," group.long 0x80654++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_13," rgroup.long 0x80650++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_13," tree.end tree "IRQ_Line_2" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end tree "IRQ_Line_3" group.long 0x8055C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_3," group.long 0x80558++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_3," group.long 0x80554++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_3," group.long 0x80550++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_3," group.long 0x8042C++0x03 line.long 0x00 "MISR2_Dk_3," group.long 0x8030C++0x03 line.long 0x00 "MMR_LOCKi_3,MMR Lock/Unlock register" tree.end tree "IRQ_Line_4" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end tree "IRQ_Line_5" group.long 0x8022C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_5," group.long 0x80228++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_5," group.long 0x80224++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_5," group.long 0x80220++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_5," group.long 0x80314++0x03 line.long 0x00 "MMR_LOCKi_5,MMR Lock/Unlock register" tree.end tree "IRQ_Line_6" group.long 0x8023C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_6," group.long 0x80238++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_6," group.long 0x80234++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_6," group.long 0x80230++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_6," group.long 0x80318++0x03 line.long 0x00 "MMR_LOCKi_6,MMR Lock/Unlock register" tree.end tree "IRQ_Line_7" group.long 0x8024C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_7," group.long 0x80248++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_7," group.long 0x80244++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_7," group.long 0x80240++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_7," group.long 0x8031C++0x03 line.long 0x00 "MMR_LOCKi_7,MMR Lock/Unlock register" tree.end tree "IRQ_Line_8" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end tree "IRQ_Line_9" group.long 0x8061C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_9," group.long 0x80618++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_9," group.long 0x80614++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_9," rgroup.long 0x80610++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_9," group.long 0x80324++0x03 line.long 0x00 "MMR_LOCKi_9,MMR Lock/Unlock register" tree.end group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80404++0x03 line.long 0x00 "MISR_CLEAR," bitfld.long 0x00 0.--2. "CLEAR,MISR Clear #N" "Previous MISR clear command has completed,MISR Clear in progress (this state may never..,?..." group.long 0x80400++0x03 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "ARP32 PMEM path Bit,ARP32 DMEM path Bit,INTC WBUF path,?..." width 0x0B tree.end tree "EVE1_SCTM" base ad:0x42085000 tree "Channel_0" rgroup.long 0x180++0x03 line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" group.long 0x108++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x100++0x03 line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x40++0x03 line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_1" rgroup.long 0x184++0x03 line.long 0x00 "SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the moduel" group.long 0x10C++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x104++0x03 line.long 0x00 "SCTM_CTCR_WT_m_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x44++0x03 line.long 0x00 "SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_2" rgroup.long 0x188++0x03 line.long 0x00 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" group.long 0x110++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x48++0x03 line.long 0x00 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_3" rgroup.long 0x18C++0x03 line.long 0x00 "SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the moduel" group.long 0x114++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_3,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x4C++0x03 line.long 0x00 "SCTM_TINTVLR_i_3,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_4" rgroup.long 0x190++0x03 line.long 0x00 "SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the moduel" group.long 0x118++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_4,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x50++0x03 line.long 0x00 "SCTM_TINTVLR_i_4,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_5" rgroup.long 0x194++0x03 line.long 0x00 "SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the moduel" group.long 0x11C++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_5,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x54++0x03 line.long 0x00 "SCTM_TINTVLR_i_5,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_6" rgroup.long 0x198++0x03 line.long 0x00 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" group.long 0x58++0x03 line.long 0x00 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_7" rgroup.long 0x19C++0x03 line.long 0x00 "SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the moduel" group.long 0x5C++0x03 line.long 0x00 "SCTM_TINTVLR_i_7,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "Force Idle mode,Ths SCTM will acknoledge the idle request but..,Ths SCTM uses the smart idle protocol,Since the SCTM does not support internal wakeup.." newline bitfld.long 0x00 0. "ENBL,SCTM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x80++0x03 line.long 0x00 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" rgroup.long 0x7C++0x03 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x20++0x03 line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" newline bitfld.long 0x00 0. "ENBL,STM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x28++0x03 line.long 0x00 "SCTM_CTSTMINTVL," hexmask.long.word 0x00 0.--15. 1. "INTERVAL,Periodic export interval" group.long 0x24++0x03 line.long 0x00 "SCTM_CTSTMMSTID," hexmask.long.byte 0x00 0.--6. 1. "MASTID,HW Master ID for this module" group.long 0x2C++0x03 line.long 0x00 "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" width 0x0B tree.end tree "EVE2_SCTM" base ad:0x42185000 tree "Channel_0" rgroup.long 0x180++0x03 line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" group.long 0x108++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x100++0x03 line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x40++0x03 line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_1" rgroup.long 0x184++0x03 line.long 0x00 "SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the moduel" group.long 0x10C++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x104++0x03 line.long 0x00 "SCTM_CTCR_WT_m_1,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x44++0x03 line.long 0x00 "SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_2" rgroup.long 0x188++0x03 line.long 0x00 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" group.long 0x110++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x48++0x03 line.long 0x00 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_3" rgroup.long 0x18C++0x03 line.long 0x00 "SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the moduel" group.long 0x114++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_3,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x4C++0x03 line.long 0x00 "SCTM_TINTVLR_i_3,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_4" rgroup.long 0x190++0x03 line.long 0x00 "SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the moduel" group.long 0x118++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_4,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x50++0x03 line.long 0x00 "SCTM_TINTVLR_i_4,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_5" rgroup.long 0x194++0x03 line.long 0x00 "SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the moduel" group.long 0x11C++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_5,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x54++0x03 line.long 0x00 "SCTM_TINTVLR_i_5,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_6" rgroup.long 0x198++0x03 line.long 0x00 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" group.long 0x58++0x03 line.long 0x00 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end tree "Channel_7" rgroup.long 0x19C++0x03 line.long 0x00 "SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the moduel" group.long 0x5C++0x03 line.long 0x00 "SCTM_TINTVLR_i_7,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "Force Idle mode,Ths SCTM will acknoledge the idle request but..,Ths SCTM uses the smart idle protocol,Since the SCTM does not support internal wakeup.." newline bitfld.long 0x00 0. "ENBL,SCTM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x80++0x03 line.long 0x00 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.byte 0x00 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" rgroup.long 0x7C++0x03 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" group.long 0x20++0x03 line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" newline bitfld.long 0x00 0. "ENBL,STM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x28++0x03 line.long 0x00 "SCTM_CTSTMINTVL," hexmask.long.word 0x00 0.--15. 1. "INTERVAL,Periodic export interval" group.long 0x24++0x03 line.long 0x00 "SCTM_CTSTMMSTID," hexmask.long.byte 0x00 0.--6. 1. "MASTID,HW Master ID for this module" group.long 0x2C++0x03 line.long 0x00 "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" width 0x0B tree.end tree "EVE1_SMSET" base ad:0x42088000 tree "Channel_1" group.long 0x30++0x1F line.long 0x00 "SMSET_SEDEN_i_1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x04 "SMSET_SEDEN_i_2,System Event Detection Enable register 1" bitfld.long 0x04 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x04 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x04 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x04 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x04 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x04 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x04 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x04 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x04 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x04 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x04 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x04 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x04 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x04 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x04 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x04 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x04 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x04 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x04 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x04 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x04 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x04 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x04 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x04 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x04 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x04 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x04 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x04 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x04 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x04 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x04 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x04 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x08 "SMSET_SEDEN_i_3,System Event Detection Enable register 1" bitfld.long 0x08 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x08 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x08 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x08 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x08 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x08 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x08 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x08 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x08 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x08 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x08 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x08 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x08 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x08 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x08 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x08 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x08 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x08 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x08 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x08 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x08 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x08 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x08 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x08 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x08 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x08 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x08 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x08 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x08 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x08 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x08 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x08 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x0C "SMSET_SEDEN_i_4,System Event Detection Enable register 1" bitfld.long 0x0C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x0C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x0C 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x0C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x0C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x0C 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x0C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x0C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x0C 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x0C 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x0C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x0C 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x0C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x0C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x0C 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x0C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x0C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x0C 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x0C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x0C 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x0C 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x0C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x0C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x0C 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x0C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x0C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x0C 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x0C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x0C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x0C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x0C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x0C 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x10 "SMSET_SEDEN_i_5,System Event Detection Enable register 1" bitfld.long 0x10 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x10 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x10 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x10 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x10 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x10 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x10 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x10 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x10 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x10 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x10 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x10 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x10 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x10 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x10 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x10 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x10 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x10 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x10 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x10 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x10 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x10 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x10 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x10 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x10 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x10 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x10 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x10 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x10 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x10 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x10 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x10 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x14 "SMSET_SEDEN_i_6,System Event Detection Enable register 1" bitfld.long 0x14 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x14 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x14 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x14 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x14 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x14 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x14 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x14 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x14 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x14 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x14 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x14 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x14 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x14 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x14 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x14 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x14 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x14 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x14 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x14 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x14 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x14 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x14 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x14 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x14 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x14 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x14 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x14 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x14 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x14 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x14 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x14 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x18 "SMSET_SEDEN_i_7,System Event Detection Enable register 1" bitfld.long 0x18 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x18 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x18 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x18 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x18 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x18 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x18 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x18 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x18 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x18 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x18 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x18 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x18 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x18 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x18 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x18 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x18 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x18 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x18 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x18 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x18 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x18 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x18 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x18 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x18 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x18 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x18 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x18 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x18 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x18 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x18 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x18 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x1C "SMSET_SEDEN_i_8,System Event Detection Enable register 1" bitfld.long 0x1C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x1C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x1C 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x1C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x1C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x1C 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x1C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x1C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x1C 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x1C 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x1C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x1C 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x1C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x1C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x1C 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x1C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x1C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x1C 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x1C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x1C 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x1C 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x1C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x1C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x1C 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x1C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x1C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x1C 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x1C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x1C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x1C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x1C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x1C 0. "EVENT1EN,Event 1 detection enable" "0,1" tree.end group.long 0x24++0x03 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "Release ownership,Claim ownership,Enable unit,No operation" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "DEBUGGEROVERRIDE_0,DEBUGGEROVERRIDE_1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "CURRENTOWNER_0,CURRENTOWNER_1" newline bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "CAPTUREEN_0,CAPTUREEN_1" bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "low level event detection,high level evnet detection" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "sampling window,event detection" newline bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "STOP_0,STOP_1" bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "START_0,START_1" rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x03 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x28++0x03 line.long 0x00 "SMSET_SESW,System Event Sampling Window register" hexmask.long.byte 0x00 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" rgroup.long 0x14++0x03 line.long 0x00 "SMSET_SR,SMSET Status Register" bitfld.long 0x00 9. "SWFIFOEMPTY,SW message FIFO empty" "SWFIFOEMPTY_0,SWFIFOEMPTY_1" bitfld.long 0x00 8. "HWFIFOEMPTY,System event trace FIFO empty" "HWFIFOEMPTY_0,HWFIFOEMPTY_1" bitfld.long 0x00 0. "RESETDONE,Reset completed" "RESETDONE_0,RESETDONE_1" width 0x0B tree.end tree "EVE2_SMSET" base ad:0x42188000 tree "Channel_1" group.long 0x30++0x1F line.long 0x00 "SMSET_SEDEN_i_1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x04 "SMSET_SEDEN_i_2,System Event Detection Enable register 1" bitfld.long 0x04 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x04 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x04 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x04 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x04 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x04 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x04 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x04 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x04 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x04 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x04 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x04 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x04 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x04 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x04 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x04 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x04 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x04 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x04 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x04 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x04 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x04 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x04 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x04 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x04 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x04 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x04 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x04 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x04 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x04 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x04 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x04 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x08 "SMSET_SEDEN_i_3,System Event Detection Enable register 1" bitfld.long 0x08 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x08 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x08 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x08 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x08 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x08 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x08 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x08 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x08 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x08 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x08 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x08 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x08 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x08 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x08 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x08 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x08 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x08 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x08 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x08 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x08 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x08 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x08 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x08 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x08 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x08 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x08 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x08 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x08 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x08 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x08 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x08 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x0C "SMSET_SEDEN_i_4,System Event Detection Enable register 1" bitfld.long 0x0C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x0C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x0C 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x0C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x0C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x0C 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x0C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x0C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x0C 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x0C 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x0C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x0C 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x0C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x0C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x0C 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x0C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x0C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x0C 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x0C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x0C 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x0C 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x0C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x0C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x0C 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x0C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x0C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x0C 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x0C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x0C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x0C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x0C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x0C 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x10 "SMSET_SEDEN_i_5,System Event Detection Enable register 1" bitfld.long 0x10 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x10 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x10 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x10 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x10 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x10 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x10 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x10 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x10 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x10 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x10 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x10 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x10 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x10 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x10 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x10 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x10 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x10 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x10 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x10 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x10 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x10 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x10 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x10 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x10 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x10 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x10 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x10 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x10 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x10 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x10 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x10 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x14 "SMSET_SEDEN_i_6,System Event Detection Enable register 1" bitfld.long 0x14 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x14 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x14 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x14 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x14 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x14 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x14 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x14 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x14 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x14 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x14 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x14 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x14 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x14 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x14 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x14 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x14 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x14 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x14 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x14 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x14 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x14 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x14 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x14 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x14 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x14 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x14 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x14 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x14 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x14 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x14 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x14 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x18 "SMSET_SEDEN_i_7,System Event Detection Enable register 1" bitfld.long 0x18 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x18 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x18 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x18 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x18 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x18 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x18 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x18 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x18 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x18 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x18 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x18 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x18 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x18 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x18 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x18 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x18 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x18 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x18 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x18 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x18 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x18 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x18 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x18 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x18 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x18 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x18 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x18 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x18 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x18 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x18 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x18 0. "EVENT1EN,Event 1 detection enable" "0,1" line.long 0x1C "SMSET_SEDEN_i_8,System Event Detection Enable register 1" bitfld.long 0x1C 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x1C 30. "EVENT31EN,Event 31 detection enable" "0,1" bitfld.long 0x1C 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x1C 28. "EVENT29EN,Event 29 detection enable" "0,1" bitfld.long 0x1C 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x1C 26. "EVENT27EN,Event 27 detection enable" "0,1" bitfld.long 0x1C 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x1C 24. "EVENT25EN,Event 25 detection enable" "0,1" bitfld.long 0x1C 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x1C 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x1C 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x1C 20. "EVENT21EN,Event 21 detection enable" "0,1" bitfld.long 0x1C 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x1C 18. "EVENT19EN,Event 19 detection enable" "0,1" bitfld.long 0x1C 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x1C 16. "EVENT17EN,Event 17 detection enable" "0,1" bitfld.long 0x1C 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x1C 14. "EVENT15EN,Event 15 detection enable" "0,1" bitfld.long 0x1C 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x1C 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x1C 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x1C 10. "EVENT11EN,Event 11 detection enable" "0,1" bitfld.long 0x1C 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x1C 8. "EVENT9EN,Event 9 detection enable" "0,1" bitfld.long 0x1C 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x1C 6. "EVENT7EN,Event 7 detection enable" "0,1" bitfld.long 0x1C 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x1C 4. "EVENT5EN,Event 5 detection enable" "0,1" bitfld.long 0x1C 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x1C 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x1C 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x1C 0. "EVENT1EN,Event 1 detection enable" "0,1" tree.end group.long 0x24++0x03 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "Release ownership,Claim ownership,Enable unit,No operation" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "DEBUGGEROVERRIDE_0,DEBUGGEROVERRIDE_1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "CURRENTOWNER_0,CURRENTOWNER_1" newline bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "CAPTUREEN_0,CAPTUREEN_1" bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "low level event detection,high level evnet detection" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "sampling window,event detection" newline bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "STOP_0,STOP_1" bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "START_0,START_1" rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x03 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x28++0x03 line.long 0x00 "SMSET_SESW,System Event Sampling Window register" hexmask.long.byte 0x00 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" rgroup.long 0x14++0x03 line.long 0x00 "SMSET_SR,SMSET Status Register" bitfld.long 0x00 9. "SWFIFOEMPTY,SW message FIFO empty" "SWFIFOEMPTY_0,SWFIFOEMPTY_1" bitfld.long 0x00 8. "HWFIFOEMPTY,System event trace FIFO empty" "HWFIFOEMPTY_0,HWFIFOEMPTY_1" bitfld.long 0x00 0. "RESETDONE,Reset completed" "RESETDONE_0,RESETDONE_1" width 0x0B tree.end tree.end tree "EMIF_Controller" base ad:0x4C000000 rgroup.long 0x00++0x2F line.long 0x00 "EMIF_REVISION,Revision number register" line.long 0x04 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x04 31. "BE,Big endian mode select for 8 and 16-bit devices set to 1 for big endian or 0 for little endian operation" "0,1" newline bitfld.long 0x04 30. "DUAL_CLK_MODE,Dual Clock mode" "0,1" newline bitfld.long 0x04 29. "FAST_INIT,Fast Init" "0,1" newline bitfld.long 0x04 6. "RDLVLGATETO,Read DQS Gate Training Timeout" "0,1" newline bitfld.long 0x04 5. "RDLVLTO,Read Data Eye Training Timeout" "0,1" newline bitfld.long 0x04 4. "WRLVLTO,Write Leveling Timeout" "0,1" newline bitfld.long 0x04 2. "PHY_DLL_READY,DDR PHY Ready" "0,1" line.long 0x08 "EMIF_SDRAM_CONFIG,SDRAM Config Register" bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM Type selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "DDR_TERM,DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "DDR2_DDQS,DDR2 differential DDQS enable" "0,1" newline bitfld.long 0x08 21.--22. "DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "SDRAM_DRIVE,SDRAM drive strength.For DDR3 set to 0 for RZQ/6 and set to 1 for RZQ/7" "0,1,2,3" newline bitfld.long 0x08 16.--17. "CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 14.--15. "NARROW_MODE,SDRAM data bus width" "0,1,2,3" newline bitfld.long 0x08 10.--13. "CL,CAS Latency (referred to as read latency (RL) in some SDRAM specs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--2. "PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" line.long 0x0C "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset" bitfld.long 0x0C 27. "EBANK_POS,External bank position" "0,1" line.long 0x10 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" bitfld.long 0x10 31. "INITREF_DIS,Initialization and Refresh disable" "0,1" newline bitfld.long 0x10 29. "SRT,DDR3 Self Refresh temperature range" "0,1" newline bitfld.long 0x10 28. "ASR,DDR3 Auto Self Refresh enable" "0,1" newline bitfld.long 0x10 24.--26. "PASR,Partial Array Self Refresh" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "REFRESH_RATE,Refresh Rate" line.long 0x14 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x14 0.--15. 1. "REFRESH_RATE_SHDW,Shadow field for REFRESH_RATE" line.long 0x18 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register" bitfld.long 0x18 29.--31. "T_RTW,Minimum number of DDR clock cycles between Read to Write data phases minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 25.--28. "T_RP,Minimum number of DDR clock cycles from Precharge to Activate or Refresh minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 21.--24. "T_RCD,Minimum number of DDR clock cycles from Activate to Read or Write minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 17.--20. "T_WR,Minimum number of DDR clock cycles from last Write transfer to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--16. "T_RAS,Minimum number of DDR clock cycles from Activate to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--11. "T_RC,Minimum number of DDR clock cycles from Activate to Activate minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 3.--5. "T_RRD,Minimum number of DDR clock cycles from Activate to Activate for a different bank minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "T_WTR,Minimum number of DDR clock cycles from last Write to Read minus one" "0,1,2,3,4,5,6,7" line.long 0x1C "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x1C 29.--31. "T_RTW_SHDW,Shadow field for T_RTW" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 25.--28. "T_RP_SHDW,Shadow field for T_RP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 21.--24. "T_RCD_SHDW,Shadow field for T_RCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 17.--20. "T_WR_SHDW,Shadow field for T_WR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--16. "T_RAS_SHDW,Shadow field for T_RAS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--11. "T_RC_SHDW,Shadow field for T_RC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 3.--5. "T_RRD_SHDW,Shadow field for T_RRD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "T_WTR_SHDW,Shadow field for T_WTR" "0,1,2,3,4,5,6,7" line.long 0x20 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register" bitfld.long 0x20 28.--30. "T_XP,Minimum number of DDR clock cycles from power-down exit to any command other than a read command minus one" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 16.--24. 1. "T_XSNR,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command minus one" newline hexmask.long.word 0x20 6.--15. 1. "T_XSRD,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command minus one" newline bitfld.long 0x20 3.--5. "T_RTP,Minimum number of DDR clock cycles for the last read command to a Precharge command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "T_CKE,Minimum number of DDR clock cycles between CKE pin changes minus one" "0,1,2,3,4,5,6,7" line.long 0x24 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" bitfld.long 0x24 28.--30. "T_XP_SHDW,Shadow field for T_XP" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 16.--24. 1. "T_XSNR_SHDW,Shadow field for T_XSNR" newline hexmask.long.word 0x24 6.--15. 1. "T_XSRD_SHDW,Shadow field for T_XSRD" newline bitfld.long 0x24 3.--5. "T_RTP_SHDW,Shadow field for T_RTP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--2. "T_CKE_SHDW,Shadow field for T_CKE" "0,1,2,3,4,5,6,7" line.long 0x28 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register" bitfld.long 0x28 28.--31. "T_PDLL_UL,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 21.--23. "T_CKESR,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--20. "ZQ_ZQCS,Number of DDR clock cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x28 4.--12. 1. "T_RFC,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one" newline bitfld.long 0x28 0.--3. "T_RAS_MAX,Maximum number of REFRESH_RATE intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x2C 28.--31. "T_PDLL_UL_SHDW,Shadow field for T_PDLL_UL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 21.--23. "T_CKESR_SHDW,Shadow field for T_CKESR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 15.--20. "ZQ_ZQCS_SHDW,Shadow field for ZQ_ZQCS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 4.--12. 1. "T_RFC_SHDW,Shadow field for T_RFC" newline bitfld.long 0x2C 0.--3. "T_RAS_MAX_SHDW,Shadow field for T_RAS_MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x30++0x07 hide.long 0x00 "EMIF_LPDDR2_NVM_TIMING,NOTE: This register is not supported" hide.long 0x04 "EMIF_LPDDR2_NVM_TIMING_SHADOW,NOTE: This register is not supported" group.long 0x38++0x07 line.long 0x00 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register" bitfld.long 0x00 12.--15. "PD_TIM,Power Management timer for Power-Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--10. "LP_MODE,Automatic Power Management enable" "Disable automatic power management,Reserved,Self Refresh mode,Disable automatic power management,Power-Down mode All other values disable..,?..." newline bitfld.long 0x00 4.--7. "SR_TIM,Power Management timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" bitfld.long 0x04 12.--15. "PD_TIM_SHDW,Shadow field for PD_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. "SR_TIM_SHDW,Shadow field for SR_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x0F line.long 0x00 "EMIF_OCP_CONFIG,OCP Config Register" bitfld.long 0x00 24.--27. "SYS_THRESH_MAX,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "MPU_THRESH_MAX,MPU Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" bitfld.long 0x04 30.--31. "SYS_BUS_WIDTH,System OCP data bus width" "32-bit wide,64-bit wide,128-bit wide,Reserved" newline hexmask.long.byte 0x04 8.--15. 1. "WR_FIFO_DEPTH,Write Data FIFO depth" newline hexmask.long.byte 0x04 0.--7. 1. "CMD_FIFO_DEPTH,Command FIFO depth" line.long 0x08 "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x08 16.--23. 1. "RREG_FIFO_DEPTH,Register Read Data FIFO depth" newline hexmask.long.byte 0x08 8.--15. 1. "RSD_FIFO_DEPTH,SDRAM Read Data FIFO depth" newline hexmask.long.byte 0x08 0.--7. 1. "RCMD_FIFO_DEPTH,Read Command FIFO depth" line.long 0x0C "EMIF_IODFT_TLGC," bitfld.long 0x0C 10. "RESET_PHY,Reset the DDR PHY" "0,1" rgroup.long 0x80++0x27 line.long 0x00 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" line.long 0x04 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" line.long 0x08 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x08 31. "CNTR2_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 30. "CNTR2_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 15. "CNTR1_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 14. "CNTR1_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Values table in . Interconnect" hexmask.long.byte 0x0C 24.--31. 1. "MCONNID2,MConnID forEMIF_PERFORMANCE_COUNTER_2 register" newline bitfld.long 0x0C 16.--17. "REGION_SEL2,MAddrSpace forEMIF_PERFORMANCE_COUNTER_2 register" "0,1,2,3" newline hexmask.long.byte 0x0C 8.--15. 1. "MCONNID1,MConnID forEMIF_PERFORMANCE_COUNTER_1 register" newline bitfld.long 0x0C 0.--1. "REGION_SEL1,MAddrSpace forEMIF_PERFORMANCE_COUNTER_1 register" "0,1,2,3" line.long 0x10 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register" line.long 0x14 "EMIF_MISC_REG," bitfld.long 0x14 0. "DLL_CALIB_OS,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse" "0,1" line.long 0x18 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps" bitfld.long 0x18 16.--19. "ACK_WAIT,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x18 0.--8. 1. "DLL_CALIB_INTERVAL,This field determines the interval between phy_dll_calib generation" line.long 0x1C "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" bitfld.long 0x1C 16.--19. "ACK_WAIT_SHDW,Shadow field for ACK_WAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x1C 0.--8. 1. "DLL_CALIB_INTERVAL_SHDW,Shadow field for DLL_CALIB_INTERVAL" line.long 0x20 "EMIF_END_OF_INTERRUPT," bitfld.long 0x20 0. "EOI,Software End Of Interrupt (EOI) control" "0,1" line.long 0x24 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" bitfld.long 0x24 5. "ONEBIT_ECC_ERR_SYS,Raw status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x24 4. "TWOBIT_ECC_ERR_SYS,Raw status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x24 3. "WR_ECC_ERR_SYS,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled" "0,1" newline bitfld.long 0x24 0. "ERR_SYS,Raw status of system OCP interrupt for command or address error" "0,1" group.long 0xAC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,Enabled status of system OCP interrupt interrupt for command or address error" "0,1" group.long 0xB4++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of sysem ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable set for system OCP interrupt for command or address error" "0,1" group.long 0xBC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location with RMW disabled" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable clear for system OCP interrupt for command or address error" "0,1" group.long 0xC8++0x23 line.long 0x00 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" bitfld.long 0x00 30. "ZQ_CS0EN,Writing a 1 enables ZQ calibration for CS0" "0,1" newline bitfld.long 0x00 28. "ZQ_SFEXITEN,Writing a 1 enables the issuing of ZQCL on Self-Refresh Active Power-Down and Precharge Power-Down exit" "0,1" newline bitfld.long 0x00 18.--19. "ZQ_ZQINIT_MULT,Indicates the number of ZQCL durations that make up a ZQINIT duration minus one" "0,1,2,3" newline bitfld.long 0x00 16.--17. "ZQ_ZQCL_MULT,Indicates the number of ZQCS intervals that make up a ZQCL duration minus one" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands" line.long 0x04 "EMIF_TEMP_ALERT_CONFIG,Temperature Alert Configuration Register.NOTE: This register is only applicable to LPDDR2 memories and cannot be used in this device" bitfld.long 0x04 31. "TA_CS1EN,Writing 1 enables temperature alert polling for CS1" "0,1" newline bitfld.long 0x04 30. "TA_CS0EN,Writing 1 enables temperature alert polling for CS0" "0,1" newline bitfld.long 0x04 28. "TA_SFEXITEN,Temperature Alert Poll on Self-Refresh Active Power-Down and Precharge Power-Down exit enable" "0,1" newline bitfld.long 0x04 26.--27. "TA_DEVWDT,This field indicates how wide a physical device is" "8-bit wide,16-bit wide,32-bit wide,?..." newline bitfld.long 0x04 24.--25. "TA_DEVCNT,This field indicates which external byte lanes contain a device for temperature monitoring" "one device,two devices,four devices,?..." newline hexmask.long.tbyte 0x04 0.--21. 1. "TA_REFINTERVAL,Number of refresh periods between temperature alert polls" line.long 0x08 "EMIF_OCP_ERROR_LOG,OCP Error Log Register" bitfld.long 0x08 14.--15. "MADDRSPACE,Address space of the first errored transaction" "SDRAM,reserved,reserved,internal registers" newline bitfld.long 0x08 11.--13. "MBURSTSEQ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--10. "MCMD,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 0.--7. 1. "MCONNID,Connection ID of the first errored transaction" line.long 0x0C "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.word 0x0C 0.--12. 1. "RDWRLVLINC_RMP_WIN,Incremental leveling ramp window in number of refresh periods" line.long 0x10 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" bitfld.long 0x10 31. "RDWRLVL_EN,Read-Write Leveling enable" "0,1" newline hexmask.long.byte 0x10 24.--30. 1. "RDWRLVLINC_RMP_PRE,Incremental leveling pre-scalar in number of refresh periods during ramp window" newline hexmask.long.byte 0x10 16.--23. 1. "RDLVLINC_RMP_INT,Incremental read data eye training interval during ramp window" newline hexmask.long.byte 0x10 8.--15. 1. "RDLVLGATEINC_RMP_INT,Incremental read DQS gate training interval during ramp window" newline hexmask.long.byte 0x10 0.--7. 1. "WRLVLINC_RMP_INT,Incremental write leveling interval during ramp window" line.long 0x14 "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" bitfld.long 0x14 31. "RDWRLVLFULL_START,Full leveling trigger" "0,1" newline hexmask.long.byte 0x14 24.--30. 1. "RDWRLVLINC_PRE,Incremental leveling pre-scalar in number of refresh periods" newline hexmask.long.byte 0x14 16.--23. 1. "RDLVLINC_INT,Incremental read data eye training interval" newline hexmask.long.byte 0x14 8.--15. 1. "RDLVLGATEINC_INT,Incremental read DQS gate training interval" newline hexmask.long.byte 0x14 0.--7. 1. "WRLVLINC_INT,Incremental write leveling interval" line.long 0x18 "EMIF_OCP_ERR_ADDR_LOG,OCP Error Address Log Register" line.long 0x1C "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x1C 27. "RDLVL_MASK,Writing a 1 to this field will mask read data eye training during full leveling command plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x1C 26. "RDLVLGATE_MASK,Writing a 1 to this field will mask dqs gate training during full leveling command plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x1C 25. "WRLVL_MASK,Writing a 1 to this field will mask write leveling training during full leveling command plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x1C 21. "PHY_HALF_DELAYS,Adjust slave delay line delays to support 2x mode" "1x mode (MDLL clock rate is same as PHY),2x mode (MDLL clock is half the rate of PHY)" newline bitfld.long 0x1C 20. "PHY_CLK_STALL_LEVEL,Enable variable idle value for delay lines" "0,1" newline bitfld.long 0x1C 19. "PHY_DIS_CALIB_RST,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs" "0,1" newline bitfld.long 0x1C 18. "PHY_INVERT_CLKOUT,Inverts the polarity of DRAM clock" "core clock is passed on to DRAM,inverted core clock is passed on to DRAM" newline hexmask.long.byte 0x1C 10.--17. 1. "PHY_DLL_LOCK_DIFF,The maximum number of delay line taps variation while maintaining the master DLL lock" newline bitfld.long 0x1C 9. "PHY_FAST_DLL_LOCK,Controls master DLL to lock fast or average logic must be part of locking process" "MDLL lock is asserted based on average of 16..,MDLL lock is asserted based on single sample" newline bitfld.long 0x1C 0.--4. "READ_LATENCY,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "EMIF_DDR_PHY_CONTROL_1_SHADOW," bitfld.long 0x20 27. "RDLVL_MASK_SHDW,Shadow field for RDLVL_MASK" "0,1" newline bitfld.long 0x20 26. "RDLVLGATE_MASK_SHDW,Shadow field for RDLVLGATE_MASK" "0,1" newline bitfld.long 0x20 25. "WRLVL_MASK_SHDW,Shadow field for WRLVL_MASK" "0,1" newline bitfld.long 0x20 21. "PHY_HALF_DELAYS_SHDW,Shadow field for PHY_HALF_DELAYS" "0,1" newline bitfld.long 0x20 20. "PHY_CLK_STALL_LEVEL_SHDW,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" newline bitfld.long 0x20 19. "PHY_DIS_CALIB_RST_SHDW,Shadow field for PHY_DIS_CALIB_RST" "0,1" newline bitfld.long 0x20 18. "PHY_INVERT_CLKOUT_SHDW,Shadow field for PHY_INVERT_CLKOUT" "0,1" newline hexmask.long.byte 0x20 10.--17. 1. "PHY_DLL_LOCK_DIFF_SHDW,Shadow field for PHY_DLL_LOCK_DIFF" newline bitfld.long 0x20 9. "PHY_FAST_DLL_SHDW,Shadow field for PHY_FAST_DLL" "0,1" newline bitfld.long 0x20 0.--4. "READ_LATENCY_SHDW,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hgroup.long 0xEC++0x03 hide.long 0x00 "EMIF_DDR_PHY_CONTROL_2," group.long 0x100++0x0B line.long 0x00 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING," bitfld.long 0x00 31. "PRI_COS_MAP_EN,Set 1 to enable priority to class of service mapping" "0,1" newline bitfld.long 0x00 14.--15. "PRI_7_COS,Class of service for commands with priority of 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_6_COS,Class of service for commands with priority of 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_5_COS,Class of service for commands with priority of 5" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_4_COS,Class of service for commands with priority of 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_3_COS,Class of service for commands with priority of 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_2_COS,Class of service for commands with priority of 2" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_1_COS,Class of service for commands with priority of 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_0_COS,Class of service for commands with priority of 0" "0,1,2,3" line.long 0x04 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING," bitfld.long 0x04 31. "CONNID_COS_1_MAP_EN,Set 1 to enable Connection ID to class of service 1 mapping" "0,1" newline hexmask.long.byte 0x04 23.--30. 1. "CONNID_1_COS_1,Connection ID value 1 for class of service 1" newline bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for Connection ID value 1 for class of service 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x04 12.--19. 1. "CONNID_2_COS_1,Connection ID value 2 for class of service 1" newline bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for Connection ID value 2 for class of service 1" "0,1,2,3" newline hexmask.long.byte 0x04 2.--9. 1. "CONNID_3_COS_1,Connection ID value 3 for class of service 1" newline bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for Connection ID value 3 for class of service 1" "0,1,2,3" line.long 0x08 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING," bitfld.long 0x08 31. "CONNID_COS_2_MAP_EN,Set 1 to enable Connection ID to class of service 2 mapping" "0,1" newline hexmask.long.byte 0x08 23.--30. 1. "CONNID_1_COS_2,Connection ID value 1 for class of service 2" newline bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for Connection ID value 1 for class of service 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 12.--19. 1. "CONNID_2_COS_2,Connection ID value 2 for class of service 2" newline bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for Connection ID value 2 for class of service 2" "0,1,2,3" newline hexmask.long.byte 0x08 2.--9. 1. "CONNID_3_COS_2,Connection ID value 3 for class of service 2" newline bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for Connection ID value 3 for class of service 2" "0,1,2,3" group.long 0x110++0x0B line.long 0x00 "EMIF_ECC_CTRL_REG," bitfld.long 0x00 31. "REG_ECC_EN,Set 1 to enable ECC" "0,1" newline bitfld.long 0x00 30. "REG_ECC_ADDR_RGN_PROT,Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges" "0,1" newline bitfld.long 0x00 29. "REG_ECC_VERIFY_DIS,When REG_ECC_EN =" "Enable ECC verification for read accesses,Disable ECC verification for read accesses The.." newline bitfld.long 0x00 28. "REG_RMW_EN,When REG_ECC_EN =" "Disable RMW functionality for sub-quanta accesses,Enable RMW functionality for sub-quanta accesses.." newline bitfld.long 0x00 1. "REG_ECC_ADDR_RGN_2_EN,Set 1 to enable ECC address range 2" "0,1" newline bitfld.long 0x00 0. "REG_ECC_ADDR_RGN_1_EN,Set 1 to enable ECC address range 1" "0,1" line.long 0x04 "EMIF_ECC_ADDRESS_RANGE_1," hexmask.long.word 0x04 16.--31. 1. "REG_ECC_END_ADDR_1,End address[31:16] for ECC address range 1" newline hexmask.long.word 0x04 0.--15. 1. "REG_ECC_STRT_ADDR_1,Start address[31:16] for ECC address range 1" line.long 0x08 "EMIF_ECC_ADDRESS_RANGE_2," hexmask.long.word 0x08 16.--31. 1. "REG_ECC_END_ADDR_2,End address[31:16] for ECC address range 2" newline hexmask.long.word 0x08 0.--15. 1. "REG_ECC_STRT_ADDR_2,Start address[31:16] for ECC address range 2" group.long 0x120++0x07 line.long 0x00 "EMIF_READ_WRITE_EXECUTION_THRESHOLD," bitfld.long 0x00 31. "MFLAG_OVERRIDE,Mflag override" "MFLAG_OVERRIDE_0,MFLAG_OVERRIDE_1" newline bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0.--4. "RD_THRSH,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_COS_CONFIG,Priority Raise Counter Register" hexmask.long.byte 0x04 16.--23. 1. "COS_COUNT_1,Priority Raise Counter for class of service 1" newline hexmask.long.byte 0x04 8.--15. 1. "COS_COUNT_2,Priority Raise Counter for class of service 2" newline hexmask.long.byte 0x04 0.--7. 1. "PR_OLD_COUNT,Priority Raise Old Counter" group.long 0x130++0x83 line.long 0x00 "EMIF_1B_ECC_ERR_CNT," line.long 0x04 "EMIF_1B_ECC_ERR_THRSH," hexmask.long.byte 0x04 24.--31. 1. "REG_1B_ECC_ERR_THRSH,1-bit ECC error threshold" newline hexmask.long.word 0x04 0.--15. 1. "REG_1B_ECC_ERR_WIN,1-bit ECC error window in number of refresh periods" line.long 0x08 "EMIF_1B_ECC_ERR_DIST_1," line.long 0x0C "EMIF_1B_ECC_ERR_ADDR_LOG," line.long 0x10 "EMIF_2B_ECC_ERR_ADDR_LOG," line.long 0x14 "EMIF_PHY_STATUS_1," hexmask.long.tbyte 0x14 12.--29. 1. "PHY_REG_PHY_CTRL_DLL_SLAVE_VALUE,DLL Slave Value" newline bitfld.long 0x14 4.--8. "PHY_REG_STATUS_DLL_LOCK,Lock Status for Data DLLs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--1. "PHY_REG_PHY_CTRL_DLL_LOCK,Lock Status for Command DLLs" "0,1,2,3" line.long 0x18 "EMIF_PHY_STATUS_2," line.long 0x1C "EMIF_PHY_STATUS_3," hexmask.long.word 0x1C 16.--30. 1. "PHY_REG_RDFIFO_RDPTR,Read FIFO Read Pointer" newline hexmask.long.word 0x1C 0.--12. 1. "PHY_REG_STATUS_DLL_SLAVE_VALUE_HI,Bits 44:32 of Phy_reg_status_dll_slave_value" line.long 0x20 "EMIF_PHY_STATUS_4," hexmask.long.word 0x20 16.--30. 1. "PHY_REG_GATELVL_FSM,Gate Leveling FSM" newline hexmask.long.word 0x20 0.--14. 1. "PHY_REG_RDFIFO_WRPTR,Read FIFO Write Pointer" line.long 0x24 "EMIF_PHY_STATUS_5," hexmask.long.tbyte 0x24 0.--19. 1. "PHY_REG_RD_LEVEL_FSM,Read Leveling FSM" line.long 0x28 "EMIF_PHY_STATUS_6," hexmask.long.word 0x28 0.--14. 1. "PHY_REG_WR_LEVEL_FSM,Write Leveling FSM" line.long 0x2C "EMIF_PHY_STATUS_7," hexmask.long.word 0x2C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO1,Read leveling DQS ratio1" newline hexmask.long.word 0x2C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO0,Read leveling DQS ratio0" line.long 0x30 "EMIF_PHY_STATUS_8," hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO3,Read leveling DQS ratio3" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO2,Read leveling DQS ratio2" line.long 0x34 "EMIF_PHY_STATUS_9," hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO5,Read Leveling DQS ratio5" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO4,Read Leveling DQS ratio4" line.long 0x38 "EMIF_PHY_STATUS_10," hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO7,Read leveling DQS ratio7" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO6,Read leveling DQS ratio6" line.long 0x3C "EMIF_PHY_STATUS_11," hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RDLVL_DQS_RATIO9,Read leveling DQS ratio9" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RDLVL_DQS_RATIO8,Read leveling DQS ratio8" line.long 0x40 "EMIF_PHY_STATUS_12," hexmask.long.word 0x40 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO1,Read leveling FIFO Write Enable Ratio1" newline hexmask.long.word 0x40 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO0,Read leveling FIFO Write Enable Ratio0" line.long 0x44 "EMIF_PHY_STATUS_13," hexmask.long.word 0x44 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO3,Read leveling FIFO Write Enable Ratio3" newline hexmask.long.word 0x44 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO2,Read leveling FIFO Write Enable Ratio2" line.long 0x48 "EMIF_PHY_STATUS_14," hexmask.long.word 0x48 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO5,Read leveling FIFO Write Enable Ratio5" newline hexmask.long.word 0x48 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO4,Read leveling FIFO Write Enable Ratio4" line.long 0x4C "EMIF_PHY_STATUS_15," hexmask.long.word 0x4C 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO7,Read leveling FIFO Wrie Enable Ratio7" newline hexmask.long.word 0x4C 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO6,Read leveling FIFO Wrie Enable Ratio6" line.long 0x50 "EMIF_PHY_STATUS_16," hexmask.long.word 0x50 16.--26. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO9,Read leveling FIFO Write Enable Ratio9" newline hexmask.long.word 0x50 0.--10. 1. "PHY_REG_RDLVL_FIFOWEIN_RATIO8,Read leveling FIFO Write Enable Ratio8" line.long 0x54 "EMIF_PHY_STATUS_17," hexmask.long.word 0x54 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO1,Write leveling DQ ratio1" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO0,Write leveling DQ ratio0" line.long 0x58 "EMIF_PHY_STATUS_18," hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO3,Write leveling DQ ratio3" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO2,Write leveling DQ ratio2" line.long 0x5C "EMIF_PHY_STATUS_19," hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO5,Write leveling DQ ratio5" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO4,Write leveling DQ ratio4" line.long 0x60 "EMIF_PHY_STATUS_20," hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO7,Write leveling DQ ratio7" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO6,Write leveling DQ ratio6" line.long 0x64 "EMIF_PHY_STATUS_21," hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WRLVL_DQ_RATIO9,Write leveling DQ ratio9" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WRLVL_DQ_RATIO8,Write leveling DQ ratio8" line.long 0x68 "EMIF_PHY_STATUS_22," hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO1,Write leveling DQS ratio 1" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO0,Write leveling DQS ratio 0" line.long 0x6C "EMIF_PHY_STATUS_23," hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO3,Write leveling DQS ratio3" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO2,Write leveling DQS ratio2" line.long 0x70 "EMIF_PHY_STATUS_24," hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO5,Write leveling DQS ratio5" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO4,Write leveling DQS ratio4" line.long 0x74 "EMIF_PHY_STATUS_25," hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO7,Write leveling DQS ratio7" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO6,Write leveling DQS ratio6" line.long 0x78 "EMIF_PHY_STATUS_26," hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WRLVL_DQS_RATIO9,Write leveling DQS ratio9" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WRLVL_DQS_RATIO8,Write leveling DQS ratio8" line.long 0x7C "EMIF_PHY_STATUS_27," bitfld.long 0x7C 28.--29. "PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKY,Phy control MDLL unlock sticky" "0,1,2,3" newline bitfld.long 0x7C 20.--24. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.tbyte 0x7C 0.--19. 1. "PHY_REG_RDC_FIFO_RST_ERR_CNT,RDC FIFO reset error count" line.long 0x80 "EMIF_PHY_STATUS_28," bitfld.long 0x80 24.--28. "PHY_REG_GATELVL_INC_FAIL,Gate leveling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 16.--20. "PHY_REG_WRLVL_INC_FAIL,Write leveling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 8.--12. "PHY_REG_RDLVL_INC_FAIL,Read leveling failure.NOTE: Incremental leveling is not supported on this device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x80 0.--4. "PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY,FIFO write enable in misaligned sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x11F line.long 0x00 "EMIF_EXT_PHY_CONTROL_1,Control DLL Slave Ratio Register" hexmask.long.word 0x00 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x00 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x04 "EMIF_EXT_PHY_CONTROL_1_SHADOW,Control DLL Slave Ratio Shadow Register" hexmask.long.word 0x04 20.--29. 1. "PHY_REG_CTRL_SLAVE_RATIO2,The user programmable ratio value for address/command launch timing in PHY control macro 2" newline hexmask.long.word 0x04 10.--19. 1. "PHY_REG_CTRL_SLAVE_RATIO1,The user programmable ratio value for address/command launch timing in PHY control macro 1" newline hexmask.long.word 0x04 0.--9. 1. "PHY_REG_CTRL_SLAVE_RATIO0,The user programmable ratio value for address/command launch timing in PHY control macro 0" line.long 0x08 "EMIF_EXT_PHY_CONTROL_2,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x08 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x08 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x0C "EMIF_EXT_PHY_CONTROL_2_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" hexmask.long.word 0x0C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO1,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x0C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO0,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0x10 "EMIF_EXT_PHY_CONTROL_3,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x10 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x10 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x14 "EMIF_EXT_PHY_CONTROL_3_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" hexmask.long.word 0x14 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO3,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x14 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO2,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0x18 "EMIF_EXT_PHY_CONTROL_4,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x18 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x18 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x1C "EMIF_EXT_PHY_CONTROL_4_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" hexmask.long.word 0x1C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO5,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x1C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO4,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0x20 "EMIF_EXT_PHY_CONTROL_5,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x20 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x20 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x24 "EMIF_EXT_PHY_CONTROL_5_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x24 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO7,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x24 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO6,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0x28 "EMIF_EXT_PHY_CONTROL_6,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x28 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x28 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x2C "EMIF_EXT_PHY_CONTROL_6_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register" hexmask.long.word 0x2C 16.--26. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO9,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x2C 0.--10. 1. "PHY_REG_FIFO_WE_SLAVE_RATIO8,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0x30 "EMIF_EXT_PHY_CONTROL_7,Data macro 0. read DQS DLL Slave Ratio Register" hexmask.long.word 0x30 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x30 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x34 "EMIF_EXT_PHY_CONTROL_7_SHADOW,Data macro 0. read DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x34 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO1,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x34 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO0,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x38 "EMIF_EXT_PHY_CONTROL_8,Data macro 1. read DQS DLL Slave Ratio Register" hexmask.long.word 0x38 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x38 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x3C "EMIF_EXT_PHY_CONTROL_8_SHADOW,Data macro 1. read DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x3C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO3,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO2,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x40 "EMIF_EXT_PHY_CONTROL_9,Data macro 2. read DQS DLL Slave Ratio Register" hexmask.long.word 0x40 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x40 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x44 "EMIF_EXT_PHY_CONTROL_9_SHADOW,Data macro 2. read DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x44 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO5,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x44 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO4,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x48 "EMIF_EXT_PHY_CONTROL_10,Data macro 3. read DQS DLL Slave Ratio Register" hexmask.long.word 0x48 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x48 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x4C "EMIF_EXT_PHY_CONTROL_10_SHADOW,Data macro 3. read DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x4C 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO7,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x4C 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO6,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x50 "EMIF_EXT_PHY_CONTROL_11,ECC Data macro. read DQS DLL Slave Ratio Register" hexmask.long.word 0x50 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x50 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x54 "EMIF_EXT_PHY_CONTROL_11_SHADOW,ECC Data macro. read DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x54 16.--25. 1. "PHY_REG_RD_DQS_SLAVE_RATIO9,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x54 0.--9. 1. "PHY_REG_RD_DQS_SLAVE_RATIO8,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x58 "EMIF_EXT_PHY_CONTROL_12,Data macro 0. write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x58 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x58 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x5C "EMIF_EXT_PHY_CONTROL_12_SHADOW,Data macro 0. write DQ (data) DLL Slave Ratio Shadow Register" hexmask.long.word 0x5C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO1,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x5C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO0,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0 chip select 0" line.long 0x60 "EMIF_EXT_PHY_CONTROL_13,Data macro 1. write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x60 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x60 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x64 "EMIF_EXT_PHY_CONTROL_13_SHADOW,Data macro 1. write DQ (data) DLL Slave Ratio Shadow Register" hexmask.long.word 0x64 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO3,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x64 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO2,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1 chip select 0" line.long 0x68 "EMIF_EXT_PHY_CONTROL_14,Data macro 2. write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x68 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x68 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x6C "EMIF_EXT_PHY_CONTROL_14_SHADOW,Data macro 2. write DQ (data) DLL Slave Ratio Shadow Register" hexmask.long.word 0x6C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO5,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x6C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO4,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2 chip select 0" line.long 0x70 "EMIF_EXT_PHY_CONTROL_15,Data macro 3. write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x70 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x70 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x74 "EMIF_EXT_PHY_CONTROL_15_SHADOW,Data macro 3. write DQ (data) DLL Slave Ratio Shadow Register" hexmask.long.word 0x74 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO7,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x74 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO6,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3 chip select 0" line.long 0x78 "EMIF_EXT_PHY_CONTROL_16,ECC Data macro. write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x78 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x78 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x7C "EMIF_EXT_PHY_CONTROL_16_SHADOW,ECC Data macro. write DQ (data) DLL Slave Ratio Shadow Register" hexmask.long.word 0x7C 16.--25. 1. "PHY_REG_WR_DATA_SLAVE_RATIO9,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x7C 0.--9. 1. "PHY_REG_WR_DATA_SLAVE_RATIO8,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro chip select 0" line.long 0x80 "EMIF_EXT_PHY_CONTROL_17,Data macro 0. write DQS DLL Slave Ratio Register" hexmask.long.word 0x80 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x80 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x84 "EMIF_EXT_PHY_CONTROL_17_SHADOW,Data macro 0. write DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x84 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO1,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0x84 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO0,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0x88 "EMIF_EXT_PHY_CONTROL_18,Data macro 1. write DQS DLL Slave Ratio Register" hexmask.long.word 0x88 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x88 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x8C "EMIF_EXT_PHY_CONTROL_18_SHADOW,Data macro 1. write DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x8C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO3,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0x8C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO2,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x90 "EMIF_EXT_PHY_CONTROL_19,Data macro 2. write DQS DLL Slave Ratio Register" hexmask.long.word 0x90 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x90 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x94 "EMIF_EXT_PHY_CONTROL_19_SHADOW,Data macro 2. write DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x94 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO5,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x94 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO4,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x98 "EMIF_EXT_PHY_CONTROL_20,Data macro 3. write DQS DLL Slave Ratio Register" hexmask.long.word 0x98 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x98 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x9C "EMIF_EXT_PHY_CONTROL_20_SHADOW,Data macro 3. write DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0x9C 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO7,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x9C 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO6,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0xA0 "EMIF_EXT_PHY_CONTROL_21,ECC Data macro. write DQS DLL Slave Ratio Register" hexmask.long.word 0xA0 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0xA0 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA4 "EMIF_EXT_PHY_CONTROL_21_SHADOW,ECC Data macro. write DQS DLL Slave Ratio Shadow Register" hexmask.long.word 0xA4 16.--25. 1. "PHY_REG_WR_DQS_SLAVE_RATIO9,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0xA4 0.--9. 1. "PHY_REG_WR_DQS_SLAVE_RATIO8,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0xA8 "EMIF_EXT_PHY_CONTROL_22," hexmask.long.word 0xA8 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.word 0xA8 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xAC "EMIF_EXT_PHY_CONTROL_22_SHADOW," hexmask.long.word 0xAC 16.--24. 1. "PHY_REG_FIFO_WE_IN_DELAY,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1" newline hexmask.long.word 0xAC 0.--8. 1. "PHY_REG_CTRL_SLAVE_DELAY,The user programmable command delay value used when DLL_OVERRIDE = 1" line.long 0xB0 "EMIF_EXT_PHY_CONTROL_23," hexmask.long.word 0xB0 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.word 0xB0 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB4 "EMIF_EXT_PHY_CONTROL_23_SHADOW," hexmask.long.word 0xB4 16.--24. 1. "PHY_REG_WR_DQS_SLAVE_DELAY,The user programmable write DQS delay value used when DLL_OVERRIDE = 1" newline hexmask.long.word 0xB4 0.--8. 1. "PHY_REG_RD_DQS_SLAVE_DELAY,The user programmable read DQS delay value used when DLL_OVERRIDE = 1" line.long 0xB8 "EMIF_EXT_PHY_CONTROL_24," hexmask.long.byte 0xB8 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline bitfld.long 0xB8 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline bitfld.long 0xB8 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline hexmask.long.word 0xB8 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xBC "EMIF_EXT_PHY_CONTROL_24_SHADOW," hexmask.long.byte 0xBC 24.--30. 1. "REG_PHY_DQ_OFFSET_HI,The user programmable offset ratio value from write DQS to write DQ" newline bitfld.long 0xBC 16. "REG_PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline bitfld.long 0xBC 12. "REG_PHY_USE_RANK0_DELAYS,Delay selection" "0,1" newline hexmask.long.word 0xBC 0.--8. 1. "REG_PHY_WR_DATA_SLAVE_DELAY,The user programmable write DQ delay value used when DLL_OVERRIDE = 1" line.long 0xC0 "EMIF_EXT_PHY_CONTROL_25,DQ DLL Slave Ratio Offset Register" hexmask.long.byte 0xC0 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC0 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC4 "EMIF_EXT_PHY_CONTROL_25_SHADOW,DQ DLL Slave Ratio Offset Shadow Register" hexmask.long.byte 0xC4 21.--27. 1. "REG_PHY_DQ_OFFSET3,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 14.--20. 1. "REG_PHY_DQ_OFFSET2,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 7.--13. 1. "REG_PHY_DQ_OFFSET1,The user programmable offset ratio value from write DQS to write DQ" newline hexmask.long.byte 0xC4 0.--6. 1. "REG_PHY_DQ_OFFSET0,The user programmable offset ratio value from write DQS to write DQ" line.long 0xC8 "EMIF_EXT_PHY_CONTROL_26,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0xC8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0xC8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xCC "EMIF_EXT_PHY_CONTROL_26_SHADOW,Data macro 0. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xCC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO1,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0xCC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO0,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0 chip select 0" line.long 0xD0 "EMIF_EXT_PHY_CONTROL_27,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0xD0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0xD0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD4 "EMIF_EXT_PHY_CONTROL_27_SHADOW,Data macro 1. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xD4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO3,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0xD4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO2,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1 chip select 0" line.long 0xD8 "EMIF_EXT_PHY_CONTROL_28,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0xD8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0xD8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xDC "EMIF_EXT_PHY_CONTROL_28_SHADOW,Data macro 2. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xDC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO5,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0xDC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO4,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2 chip select 0" line.long 0xE0 "EMIF_EXT_PHY_CONTROL_29,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0xE0 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0xE0 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE4 "EMIF_EXT_PHY_CONTROL_29_SHADOW,Data macro 3. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xE4 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO7,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0xE4 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO6,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3 chip select 0" line.long 0xE8 "EMIF_EXT_PHY_CONTROL_30,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0xE8 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0xE8 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xEC "EMIF_EXT_PHY_CONTROL_30_SHADOW,ECC Data macro. FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xEC 16.--26. 1. "REG_PHY_GATELVL_INIT_RATIO9,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0xEC 0.--10. 1. "REG_PHY_GATELVL_INIT_RATIO8,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro chip select 0" line.long 0xF0 "EMIF_EXT_PHY_CONTROL_31,Data macro 0. write DQS DLL Slave Init Ratio Register" hexmask.long.word 0xF0 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0xF0 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF4 "EMIF_EXT_PHY_CONTROL_31_SHADOW,Data macro 0. write DQS DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xF4 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO1,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 1" newline hexmask.long.word 0xF4 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO0,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0 chip select 0" line.long 0xF8 "EMIF_EXT_PHY_CONTROL_32,Data macro 1. write DQS DLL Slave Init Ratio Register" hexmask.long.word 0xF8 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0xF8 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0xFC "EMIF_EXT_PHY_CONTROL_32_SHADOW,Data macro 1. write DQS DLL Slave Init Ratio Shadow Register" hexmask.long.word 0xFC 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO3,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 1" newline hexmask.long.word 0xFC 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO2,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1 chip select 0" line.long 0x100 "EMIF_EXT_PHY_CONTROL_33,Data macro 2. write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x100 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x100 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x104 "EMIF_EXT_PHY_CONTROL_33_SHADOW,Data macro 2. write DQS DLL Slave Init Ratio Shadow Register" hexmask.long.word 0x104 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO5,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 1" newline hexmask.long.word 0x104 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO4,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2 chip select 0" line.long 0x108 "EMIF_EXT_PHY_CONTROL_34,Data macro 3. write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x108 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x108 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x10C "EMIF_EXT_PHY_CONTROL_34_SHADOW,Data macro 3. write DQS DLL Slave Init Ratio Shadow Register" hexmask.long.word 0x10C 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO7,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 1" newline hexmask.long.word 0x10C 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO6,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3 chip select 0" line.long 0x110 "EMIF_EXT_PHY_CONTROL_35,ECC Data macro. write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x110 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x110 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x114 "EMIF_EXT_PHY_CONTROL_35_SHADOW,ECC Data macro. write DQS DLL Slave Init Ratio Shadow Register" hexmask.long.word 0x114 16.--25. 1. "REG_PHY_WRLVL_INIT_RATIO9,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 1" newline hexmask.long.word 0x114 0.--9. 1. "REG_PHY_WRLVL_INIT_RATIO8,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro chip select 0" line.long 0x118 "EMIF_EXT_PHY_CONTROL_36," bitfld.long 0x118 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x118 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x118 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x118 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x118 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x11C "EMIF_EXT_PHY_CONTROL_36_SHADOW," bitfld.long 0x11C 10. "REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags" "0,1" newline bitfld.long 0x11C 9. "REG_PHY_MDLL_UNLOCK_CLR,Clears the phy_reg_status_mdll_unlock_sticky flag" "0,1" newline bitfld.long 0x11C 8. "REG_PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag" "0,1" newline bitfld.long 0x11C 4.--7. "REG_PHY_WRLVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x11C 0.--3. "REG_PHY_GATELVL_NUM_OF_DQ0,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "eMMC_SD_SDIO" repeat 2. (list 1. 2. )(list ad:0x4809C000 ad:0x480B4000 ) tree "MMC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "RETMODE_0_r,RETMODE_1_r" bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer: - MEM_1024" "?,MEM_SIZE_1_r,MEM_SIZE_2_r,?,MEM_SIZE_4_r,?,?,?,MEM_SIZE_8_r,?,?,?,?,?,?,?" newline bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture" "MERGE_MEM_0_r,MERGE_MEM_1_r" bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0_r,MADMA_EN_1_r" group.long 0x10++0x03 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x110++0x07 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface" bitfld.long 0x00 12.--13. "STANDBYMODE,Master interface power Management standby/wait control" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control - Disabled" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring Note: the debounce clock the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x13 line.long 0x00 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO" line.long 0x04 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification" rbitfld.long 0x04 16. "OBI,Out-Of-Band Interrupt (OBI) data value - HighLevel" "OBI_0_r,OBI_1_r" rbitfld.long 0x04 15. "SDCD,Card detect input signal (mmci_sdcd) data value - DrivenHigh" "SDCD_0_r,SDCD_1_r" newline rbitfld.long 0x04 14. "SDWP,Write protect input signal (mmci_sdwp) data value - DrivenHigh" "SDWP_0_r,SDWP_1_r" bitfld.long 0x04 13. "WAKD,Wake request output signal data value - DrivenLow_w" "WAKD_0_r,WAKD_1_r" newline bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)" "SSB_0_r,SSB_1_r" bitfld.long 0x04 11. "D7D,DAT7 input/output signal data value - DriveLow_w" "D7D_0_r,D7D_1_r" newline bitfld.long 0x04 10. "D6D,DAT6 input/output signal data value - DriveLow_w" "D6D_0_r,D6D_1_r" bitfld.long 0x04 9. "D5D,DAT5 input/output signal data value - DriveLow_w" "D5D_0_r,D5D_1_r" newline bitfld.long 0x04 8. "D4D,DAT4 input/output signal data value - DriveLow_w" "D4D_0_r,D4D_1_r" bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value - DriveLow_w" "D3D_0_r,D3D_1_r" newline bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value - DriveLow_w" "D2D_0_r,D2D_1_r" bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value - DriveLow_w" "D1D_0_r,D1D_1_r" newline bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value - Zero_w" "D0D_0_r,D0D_1_r" bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction" "DDIR_0_r,DDIR_1_r" newline bitfld.long 0x04 2. "CDAT,CMD input/output signal data value - DriveLow_w" "CDAT_0_r,CDAT_1_r" bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction" "CDIR_0_r,CDIR_1_r" newline bitfld.long 0x04 0. "MCKD,MMC clock output signal data value - DrivenLow_w" "MCKD_0_r,MCKD_1_r" line.long 0x08 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card" bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion request remains active until last allowed data written.." "SDMA_LNE_0,SDMA_LNE_1" bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available.." "DMA_MNS_0,DMA_MNS_1" newline bitfld.long 0x08 19. "DDR,Dual Data Rate mode: When this register is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1" bitfld.long 0x08 18. "BOOT_CF0,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence" "BOOT_CF0_0_r,BOOT_CF0_1_r" newline bitfld.long 0x08 17. "BOOT_ACK,Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued" "BOOT_ACK_0,BOOT_ACK_1" bitfld.long 0x08 16. "CLKEXTFREE,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1" newline bitfld.long 0x08 15. "PADEN,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1" bitfld.long 0x08 14. "OBIE,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin" "OBIE_0,OBIE_1" newline bitfld.long 0x08 13. "OBIP,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards" "OBIP_0,OBIP_1" bitfld.long 0x08 12. "CEATA,CE-ATA control mode MMC cards compliant with CE-ATA:By default this bit is set to 0" "CEATA_0,CEATA_1" newline bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line MMC and SD cards: By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current" "CTPL_0,CTPL_1" bitfld.long 0x08 9.--10. "DVAL,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd)" "DVAL_0,DVAL_1,DVAL_2,DVAL_3" newline bitfld.long 0x08 8. "WPP,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp)" "WPP_0,WPP_1" bitfld.long 0x08 7. "CDP,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd)" "CDP_0,CDP_1" newline bitfld.long 0x08 6. "MIT,MMC interrupt command Only for MMC cards" "MIT_0,MIT_1" bitfld.long 0x08 5. "DW8,8-bit mode MMC select For SD/SDIO cards this bit must be set to 0" "DW8_0,DW8_1" newline bitfld.long 0x08 4. "MODE,Mode select All cards This bit select between Functional mode and SYSTEST mode" "MODE_0,MODE_1" bitfld.long 0x08 3. "STR,Stream command Only for MMC cards" "STR_0,STR_1" newline bitfld.long 0x08 2. "HR,Broadcast host response Only for MMC cards" "HR_0,HR_1" bitfld.long 0x08 1. "INIT,Send initialization stream All cards" "INIT_0,INIT_1" newline bitfld.long 0x08 0. "OD,Card open drain mode" "OD_0,OD_1" line.long 0x0C "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage" hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register" line.long 0x10 "MMCHS_DLL,DLL control and status register This register is used for tuning procedure required for SDR104/HS200 speed mode" bitfld.long 0x10 31. "DLL_SOFT_RESET,Soft reset for DLL active HIGH" "DLL_SOFT_RESET_0_r,DLL_SOFT_RESET_1_r" bitfld.long 0x10 30. "LOCK_TIMER,Timer for the dll_lock signal to be asserted after reset" "LOCK_TIMER_0,LOCK_TIMER_1" newline hexmask.long.byte 0x10 22.--29. 1. "MAX_LOCK_DIFF,Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock" bitfld.long 0x10 21. "FORCE_SR_F,Forced fine delay value" "0,1" newline bitfld.long 0x10 20. "SWT,Software Tuning enable" "No software tuning sequence,Execute software tuning sequence" hexmask.long.byte 0x10 13.--19. 1. "FORCE_SR_C,Forced coarse delay value" newline bitfld.long 0x10 12. "FORCE_VALUE,Put forced values to slave DLL ignoring master DLL output and ratio value" "FORCE_VALUE_0,FORCE_VALUE_1" bitfld.long 0x10 6.--11. "SLAVE_RATIO,Fraction of a clock cycle for the shift to be implemented in units of 256ths of a clock cycle" "SLAVE_RATIO_0,?,SLAVE_RATIO_2,?,SLAVE_RATIO_4,?,SLAVE_RATIO_6,?,SLAVE_RATIO_8,?,SLAVE_RATIO_10,?,SLAVE_RATIO_12,?,SLAVE_RATIO_14,?,SLAVE_RATIO_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,SLAVE_RATIO_63" newline bitfld.long 0x10 3. "DLL_UNLOCK_CLEAR,Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL" "DLL_UNLOCK_CLEAR_0,DLL_UNLOCK_CLEAR_1" rbitfld.long 0x10 2. "DLL_UNLOCK_STICKY,Asserted when any single period measurement exceeds MAX_LOCK_DIFF" "0,1" newline bitfld.long 0x10 1. "DLL_CALIB,Enables Slave DLL to update new delay values" "DLL_CALIB_0,DLL_CALIB_1" rbitfld.long 0x10 0. "DLL_LOCK,Master DLL lock status" "DLL_LOCK_0_r,DLL_LOCK_1_r" group.long 0x200++0x4B line.long 0x00 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" line.long 0x04 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register" hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers" hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size" line.long 0x08 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register)" line.long 0x0C "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode" bitfld.long 0x0C 24.--29. "INDX,Command index - Binary encoded value from 0 to 63 specifying the command number send to card" "INDX_0,INDX_1,INDX_2,INDX_3,INDX_4,INDX_5,INDX_6,INDX_7,INDX_8,INDX_9,INDX_10,INDX_11,INDX_12,INDX_13,INDX_14,INDX_15,INDX_16,INDX_17,INDX_18,INDX_19,INDX_20,INDX_21,INDX_22,INDX_23,INDX_24,INDX_25,INDX_26,INDX_27,INDX_28,INDX_29,INDX_30,INDX_31,INDX_32,INDX_33,INDX_34,INDX_35,INDX_36,INDX_37,INDX_38,INDX_39,INDX_40,INDX_41,INDX_42,INDX_43,INDX_44,INDX_45,INDX_46,INDX_47,INDX_48,INDX_49,INDX_50,INDX_51,INDX_52,INDX_53,INDX_54,INDX_55,INDX_56,INDX_57,INDX_58,INDX_59,INDX_60,INDX_61,INDX_62,INDX_63" bitfld.long 0x0C 22.--23. "CMD_TYPE,Command typeThis register specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3" newline bitfld.long 0x0C 21. "DP,Data present select - This register indicates that data is present and DAT line shall be used" "DP_0,DP_1" bitfld.long 0x0C 20. "CICE,Command Index check enable - This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1" newline bitfld.long 0x0C 19. "CCCE,Command CRC check enable - This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1" bitfld.long 0x0C 16.--17. "RSP_TYPE,Response type - This bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3" newline bitfld.long 0x0C 5. "MSBS,Multi/Single block select - This bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1" bitfld.long 0x0C 4. "DDIR,Data transfer Direction Select - This bit defines either data transfer will be a read or a" "DDIR_0,DDIR_1" newline bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only" "ACEN_0,ACEN_1,ACEN_2,ACEN_3" bitfld.long 0x0C 1. "BCE,Block Count Enable - Multiple block transfers only" "BCE_0,BCE_1" newline bitfld.long 0x0C 0. "DE,DMA Enable - This bit is used to enable DMA mode for host data access" "DE_0,DE_1" line.long 0x10 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x10 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x10 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x14 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x14 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x14 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x18 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x18 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x18 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0x1C "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x1C 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0x1C 0.--15. 1. "RSP6,Command Response [111:96]" line.long 0x20 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers" line.long 0x24 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register" bitfld.long 0x24 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0_r,CLEV_1_r" bitfld.long 0x24 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors and for debugging" "DLEV_0,DLEV_1,DLEV_2,DLEV_3,DLEV_4,DLEV_5,DLEV_6,DLEV_7,DLEV_8,DLEV_9,DLEV_10,DLEV_11,DLEV_12,DLEV_13,DLEV_14,DLEV_15" newline bitfld.long 0x24 19. "WP,Write protect switch pin level For SDIO cards only" "WP_0_r,WP_1_r" bitfld.long 0x24 18. "CDPL,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd) debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1" "CDPL_0_r,CDPL_1_r" newline bitfld.long 0x24 17. "CSS,Card State Stable This bit is used for testing" "CSS_0_r,CSS_1_r" bitfld.long 0x24 16. "CINS,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd)" "CINS_0_r,CINS_1_r" newline bitfld.long 0x24 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0_r,BRE_1_r" bitfld.long 0x24 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0_r,BWE_1_r" newline bitfld.long 0x24 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0_r,RTA_1_r" bitfld.long 0x24 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0_r,WTA_1_r" newline bitfld.long 0x24 3. "RTR,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "RTR_0_r,RTR_1_r" bitfld.long 0x24 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0_r,DLA_1_r" newline bitfld.long 0x24 1. "DATI,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued" "DATI_0_r,DATI_1_r" bitfld.long 0x24 0. "CMDI,Command inhibit(CMD) This status bit indicates that the CMD line is in use" "CMDI_0_r,CMDI_1_r" line.long 0x28 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters" bitfld.long 0x28 27. "OBWE,Wakeup event enable for 'Out-of-Band' Interrupt" "OBWE_0,OBWE_1" bitfld.long 0x28 26. "REM,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion" "REM_0,REM_1" newline bitfld.long 0x28 25. "INS,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion" "INS_0,INS_1" bitfld.long 0x28 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1" newline bitfld.long 0x28 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1" bitfld.long 0x28 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1" newline bitfld.long 0x28 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR])" "CR_0,CR_1" bitfld.long 0x28 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1" newline bitfld.long 0x28 9.--11. "SDVS,SD bus voltage select All cards" "?,?,?,?,?,SDVS_5,SDVS_6,SDVS_7" bitfld.long 0x28 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS])" "SDBP_0,SDBP_1" newline bitfld.long 0x28 7. "CDSS,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in.." "CDSS_0,CDSS_1" bitfld.long 0x28 6. "CDTL,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not" "CDTL_0,CDTL_1" newline bitfld.long 0x28 3.--4. "DMAS,DMA Select Mode: One of supported DMA modes can be selected" "DMAS_0,DMAS_1,DMAS_2,DMAS_3" bitfld.long 0x28 2. "HSPE,Before setting this bit the Host Driver shall check theMMCHS_CAPA[21] HSS" "HSPE_0,HSPE_1" newline bitfld.long 0x28 1. "DTW,Data transfer width For MMC card this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument" "DTW_0,DTW_1" rbitfld.long 0x28 0. "LED,Reserved bit" "LED_0,LED_1" line.long 0x2C "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout" bitfld.long 0x2C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1" bitfld.long 0x2C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see CMD Line Reset Procedure" "SRC_0,SRC_1" newline bitfld.long 0x2C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1" bitfld.long 0x2C 16.--19. "DTO,Data timeout counter value and busy timeout" "DTO_0,DTO_1,?,?,?,?,?,?,?,?,?,?,?,?,DTO_14,DTO_15" newline hexmask.long.word 0x2C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC SD or SDIO)" rbitfld.long 0x2C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1" newline bitfld.long 0x2C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1" rbitfld.long 0x2C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0_r,ICS_1_r" newline bitfld.long 0x2C 0. "ICE,Internal clock enable This register controls the internal clock activity" "ICE_0,ICE_1" line.long 0x30 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x30 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit.." "BADA_0_r,BADA_1_r" bitfld.long 0x30 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0_r,CERR_1_r" newline bitfld.long 0x30 26. "TE,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select)" "TE_0,TE_1" bitfld.long 0x30 25. "ADMAE,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer" "ADMAE_0_r,ADMAE_1_r" newline bitfld.long 0x30 24. "ACE,Auto CMD error Auto CMD12 and Auto CMD23 use this error status" "ACE_0_r,ACE_1_r" bitfld.long 0x30 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode" "DEB_0_r,DEB_1_r" newline bitfld.long 0x30 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command" "DCRC_0_r,DCRC_1_r" bitfld.long 0x30 20. "DTO,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - St_un_w" "DTO_0_r,DTO_1_r" newline bitfld.long 0x30 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0_r,CIE_1_r" bitfld.long 0x30 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response" "CEB_0_r,CEB_1_r" newline bitfld.long 0x30 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register" "CCRC_0_r,CCRC_1_r" bitfld.long 0x30 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "CTO_0_r,CTO_1_r" newline rbitfld.long 0x30 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set then this bit is set to 1" "ERRI_0_r,ERRI_1_r" bitfld.long 0x30 10. "BSR,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line" "BSR_0_r,BSR_1_r" newline bitfld.long 0x30 9. "OBI,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin" "OBI_0_r,OBI_1_r" rbitfld.long 0x30 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards" "CIRQ_0_r,CIRQ_1_r" newline bitfld.long 0x30 7. "CREM,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0" "CREM_0_r,CREM_1_r" bitfld.long 0x30 6. "CINS,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1" "CINS_0_r,CINS_1_r" newline bitfld.long 0x30 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer" "BRR_0_r,BRR_1_r" bitfld.long 0x30 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]" "BWR_0_r,BWR_1_r" newline bitfld.long 0x30 3. "DMA,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion" "DMA_0_r,DMA_1_r" bitfld.long 0x30 2. "BGE,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]) this bit is automatically set when transaction is stopped at the block gap during a read or write operation" "BGE_0_r,BGE_1_r" newline bitfld.long 0x30 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR])" "TC_0_r,TC_1_r" bitfld.long 0x30 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command" "CC_0_r,CC_1_r" line.long 0x34 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis" bitfld.long 0x34 29. "BADA_ENABLE,Bad access to data space Status Enable - Masked" "BADA_ENABLE_0,BADA_ENABLE_1" bitfld.long 0x34 28. "CERR_ENABLE,Card Error Status Enable - Masked" "CERR_ENABLE_0,CERR_ENABLE_1" newline bitfld.long 0x34 26. "TE_ENABLE,Tuning Error Status Enable - Masked" "TE_ENABLE_0,TE_ENABLE_1" bitfld.long 0x34 25. "ADMAE_ENABLE,ADMA Error Status Enable - Masked" "ADMAE_ENABLE_0,ADMAE_ENABLE_1" newline bitfld.long 0x34 24. "ACE_ENABLE,Auto CMD Error Status Enable - Masked" "ACE_ENABLE_0,ACE_ENABLE_1" bitfld.long 0x34 22. "DEB_ENABLE,Data End Bit Error Status Enable - Masked" "DEB_ENABLE_0,DEB_ENABLE_1" newline bitfld.long 0x34 21. "DCRC_ENABLE,Data CRC Error Status Enable - Masked" "DCRC_ENABLE_0,DCRC_ENABLE_1" bitfld.long 0x34 20. "DTO_ENABLE,Data Timeout Error Status Enable - Masked" "DTO_ENABLE_0,DTO_ENABLE_1" newline bitfld.long 0x34 19. "CIE_ENABLE,Command Index Error Status Enable - Masked" "CIE_ENABLE_0,CIE_ENABLE_1" bitfld.long 0x34 18. "CEB_ENABLE,Command End Bit Error Status Enable - Masked" "CEB_ENABLE_0,CEB_ENABLE_1" newline bitfld.long 0x34 17. "CCRC_ENABLE,Command CRC Error Status Enable - Masked" "CCRC_ENABLE_0,CCRC_ENABLE_1" bitfld.long 0x34 16. "CTO_ENABLE,Command Timeout Error Status Enable - Masked" "CTO_ENABLE_0,CTO_ENABLE_1" newline rbitfld.long 0x34 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x34 10. "BSR_ENABLE,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_ENABLE_0,BSR_ENABLE_1" newline bitfld.long 0x34 9. "OBI_ENABLE,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_ENABLE_0,OBI_ENABLE_1" bitfld.long 0x34 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1" newline bitfld.long 0x34 7. "CREM_ENABLE,Card Removal Status Enable - Masked" "CREM_ENABLE_0,CREM_ENABLE_1" bitfld.long 0x34 6. "CINS_ENABLE,Card Insertion Status Enable - Masked" "CINS_ENABLE_0,CINS_ENABLE_1" newline bitfld.long 0x34 5. "BRR_ENABLE,Buffer Read Ready Status Enable - Masked" "BRR_ENABLE_0,BRR_ENABLE_1" bitfld.long 0x34 4. "BWR_ENABLE,Buffer Write Ready Status Enable - Masked" "BWR_ENABLE_0,BWR_ENABLE_1" newline bitfld.long 0x34 3. "DMA_ENABLE,DMA Status Enable - Masked" "DMA_ENABLE_0,DMA_ENABLE_1" bitfld.long 0x34 2. "BGE_ENABLE,Block Gap Event Status Enable - Masked" "BGE_ENABLE_0,BGE_ENABLE_1" newline bitfld.long 0x34 1. "TC_ENABLE,Transfer Complete Status Enable - Masked" "TC_ENABLE_0,TC_ENABLE_1" bitfld.long 0x34 0. "CC_ENABLE,Command Complete Status Enable - Masked" "CC_ENABLE_0,CC_ENABLE_1" line.long 0x38 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis" bitfld.long 0x38 29. "BADA_SIGEN,Bad access to data space Signal Enable - Masked" "BADA_SIGEN_0,BADA_SIGEN_1" bitfld.long 0x38 28. "CERR_SIGEN,Card Error Interrupt Signal Enable - Masked" "CERR_SIGEN_0,CERR_SIGEN_1" newline bitfld.long 0x38 26. "TE_SIGEN,Tuning Error Signal Enable - Masked" "TE_SIGEN_0,TE_SIGEN_1" bitfld.long 0x38 25. "ADMAE_SIGEN,ADMA Error Signal Enable - Masked" "ADMAE_SIGEN_0,ADMAE_SIGEN_1" newline bitfld.long 0x38 24. "ACE_SIGEN,Auto CMD Error Signal Enable - Masked" "ACE_SIGEN_0,ACE_SIGEN_1" bitfld.long 0x38 22. "DEB_SIGEN,Data End Bit Error Signal Enable - Masked" "DEB_SIGEN_0,DEB_SIGEN_1" newline bitfld.long 0x38 21. "DCRC_SIGEN,Data CRC Error Signal Enable - Masked" "DCRC_SIGEN_0,DCRC_SIGEN_1" bitfld.long 0x38 20. "DTO_SIGEN,Data Timeout Error Signal Enable - Masked" "DTO_SIGEN_0,DTO_SIGEN_1" newline bitfld.long 0x38 19. "CIE_SIGEN,Command Index Error Signal Enable - Masked" "CIE_SIGEN_0,CIE_SIGEN_1" bitfld.long 0x38 18. "CEB_SIGEN,Command End Bit Error Signal Enable - Masked" "CEB_SIGEN_0,CEB_SIGEN_1" newline bitfld.long 0x38 17. "CCRC_SIGEN,Command CRC Error Signal Enable - Masked" "CCRC_SIGEN_0,CCRC_SIGEN_1" bitfld.long 0x38 16. "CTO_SIGEN,Command timeout Error Signal Enable - Masked" "CTO_SIGEN_0,CTO_SIGEN_1" newline rbitfld.long 0x38 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x38 10. "BSR_SIGEN,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_SIGEN_0,BSR_SIGEN_1" newline bitfld.long 0x38 9. "OBI_SIGEN,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_SIGEN_0,OBI_SIGEN_1" bitfld.long 0x38 8. "CIRQ_SIGEN,Card Interrupt Signal Enable - Masked" "CIRQ_SIGEN_0,CIRQ_SIGEN_1" newline bitfld.long 0x38 7. "CREM_SIGEN,Card Removal Signal Enable - Masked" "CREM_SIGEN_0,CREM_SIGEN_1" bitfld.long 0x38 6. "CINS_SIGEN,Card Insertion Signal Enable - Masked" "CINS_SIGEN_0,CINS_SIGEN_1" newline bitfld.long 0x38 5. "BRR_SIGEN,Buffer Read Ready Signal Enable - Masked" "BRR_SIGEN_0,BRR_SIGEN_1" bitfld.long 0x38 4. "BWR_SIGEN,Buffer Write Ready Signal Enable - Masked" "BWR_SIGEN_0,BWR_SIGEN_1" newline bitfld.long 0x38 3. "DMA_SIGEN,DMA Interrupt Signal Enable - Masked" "DMA_SIGEN_0,DMA_SIGEN_1" bitfld.long 0x38 2. "BGE_SIGEN,Black Gap Event Signal Enable - Masked" "BGE_SIGEN_0,BGE_SIGEN_1" newline bitfld.long 0x38 1. "TC_SIGEN,Transfer Completed Status Enable - Masked" "TC_SIGEN_0,TC_SIGEN_1" bitfld.long 0x38 0. "CC_SIGEN,Command Complete Status Enable - Masked" "CC_SIGEN_0,CC_SIGEN_1" line.long 0x3C "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23" bitfld.long 0x3C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "PV_ENABLE_0,PV_ENABLE_1" bitfld.long 0x3C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1" "AI_ENABLE_0,AI_ENABLE_1" newline bitfld.long 0x3C 23. "SCLK_SEL,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT" "SCLK_SEL_0,SCLK_SEL_1" bitfld.long 0x3C 22. "ET,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "ET_0,ET_1" newline bitfld.long 0x3C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit" "DS_SEL_0,DS_SEL_1,DS_SEL_2,DS_SEL_3" bitfld.long 0x3C 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell" "V1V8_SIGEN_0,V1V8_SIGEN_1" newline bitfld.long 0x3C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1" "UHSMS_0,UHSMS_1,UHSMS_2,UHSMS_3,UHSMS_4,UHSMS_5,UHSMS_6,UHSMS_7" rbitfld.long 0x3C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "CNI_0_r,CNI_1_r" newline rbitfld.long 0x3C 4. "ACIE,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command" "ACIE_0_r,ACIE_1_r" rbitfld.long 0x3C 3. "ACEB,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0" "ACEB_0_r,ACEB_1_r" newline rbitfld.long 0x3C 2. "ACCE,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response" "ACCE_0_r,ACCE_1_r" rbitfld.long 0x3C 1. "ACTO,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0_r,ACTO_1_r" newline rbitfld.long 0x3C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0_r,ACNE_1_r" line.long 0x40 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller" rbitfld.long 0x40 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "AIS_0_r,AIS_1_r" rbitfld.long 0x40 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0_r,BIT64_1_r" newline bitfld.long 0x40 26. "VS18,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS18_0_r,VS18_1_r" bitfld.long 0x40 25. "VS30,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS30_0_r,VS30_1_r" newline bitfld.long 0x40 24. "VS33,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS33_0_r,VS33_1_r" rbitfld.long 0x40 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0_r,SRS_1_r" newline rbitfld.long 0x40 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0_r,DS_1_r" rbitfld.long 0x40 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0_r,HSS_1_r" newline rbitfld.long 0x40 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0_r,AD2S_1_r" rbitfld.long 0x40 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0_r,MBL_1_r,MBL_2_r,?" newline abitfld.long 0x40 8.--15. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock" "0x00=Get information via..,0x01=1MHz,0x02=2MHz,0xFF=255MHz" rbitfld.long 0x40 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCU_0_r,TCU_1_r" newline rbitfld.long 0x40 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCF_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation" abitfld.long 0x44 16.--23. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" "0x00=Clock Multiplier is Not Supported,0x01=Clock Multiplier M = 2,0x02=Clock Multiplier M = 3,0xFF=Clock Multiplier M = 256" bitfld.long 0x44 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "RTM_0_r,RTM_1_r,RTM_2_r,RTM_3_r" newline bitfld.long 0x44 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "TSDR50_0_r,TSDR50_1_r" bitfld.long 0x44 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "TCRT_0_r,TCRT_1_r,TCRT_2_r,TCRT_3_r,TCRT_4_r,TCRT_5_r,TCRT_6_r,TCRT_7_r,TCRT_8_r,TCRT_9_r,TCRT_10_r,TCRT_11_r,TCRT_12_r,TCRT_13_r,TCRT_14_r,TCRT_15_r" newline bitfld.long 0x44 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "DTD_0_r,DTD_1_r" bitfld.long 0x44 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "DTC_0_r,DTC_1_r" newline bitfld.long 0x44 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "DTA_0_r,DTA_1_r" bitfld.long 0x44 2. "DDR50,DDR50 Support - Supported" "DDR50_0_r,DDR50_1_r" newline bitfld.long 0x44 1. "SDR104,SDR104 Support SDR104 requires tuning" "SDR104_0_r,SDR104_1_r" bitfld.long 0x44 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "SDR50_0_r,SDR50_1_r" line.long 0x48 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x48 16.--23. 1. "CUR_1V8,Maximum current for" hexmask.long.byte 0x48 8.--15. 1. "CUR_3V0,Maximum current for" newline hexmask.long.byte 0x48 0.--7. 1. "CUR_3V3,Maximum current for" group.long 0x250++0x0B line.long 0x00 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register" bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space" "FE_BADA_0_w,FE_BADA_1_w" bitfld.long 0x00 28. "FE_CERR,Force Event Card error" "FE_CERR_0_w,FE_CERR_1_w" newline bitfld.long 0x00 25. "FE_ADMAE,Force Event ADMA Error" "FE_ADMAE_0_w,FE_ADMAE_1_w" bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACE_0_w,FE_ACE_1_w" newline bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error" "FE_DEB_0_w,FE_DEB_1_w" bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error" "FE_DCRC_0_w,FE_DCRC_1_w" newline bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error" "FE_DTO_0_w,FE_DTO_1_w" bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error" "FE_CIE_0_w,FE_CIE_1_w" newline bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error" "FE_CEB_0_w,FE_CEB_1_w" bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error" "FE_CCRC_0_w,FE_CCRC_1_w" newline bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0_w,FE_CTO_1_w" bitfld.long 0x00 7. "FE_CNI,Force Event Command not issue by Auto CMD12 error - NoAction" "FE_CNI_0_w,FE_CNI_1_w" newline bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACIE_0_w,FE_ACIE_1_w" bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error - NoAction" "FE_ACEB_0_w,FE_ACEB_1_w" newline bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error - NoAction" "FE_ACCE_0_w,FE_ACCE_1_w" bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error - NoAction" "FE_ACTO_0_w,FE_ACTO_1_w" newline bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed - NoAction" "FE_ACNE_0_w,FE_ACNE_1_w" line.long 0x04 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred. the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor" bitfld.long 0x04 2. "LME,ADMA Length Mismatch Error: (1) While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length" "LME_0,LME_1" bitfld.long 0x04 0.--1. "AES,ADMA Error StateThis field indicates the state of ADMA when error occurred during ADMA data transfer" "AES_0,AES_1,AES_2,AES_3" line.long 0x08 "MMCHS_ADMASAL,ADMA System address Low bits" rgroup.long 0x260++0x0F line.long 0x00 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "DSDS_SEL_0_r,DSDS_SEL_1_r,DSDS_SEL_2_r,DSDS_SEL_3_r" bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "DSCLKGEN_SEL_0_r,DSCLKGEN_SEL_1_r" newline hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes" "INITDS_SEL_0_r,INITDS_SEL_1_r,INITDS_SEL_2_r,INITDS_SEL_3_r" newline bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "INITCLKGEN_SEL_0_r,INITCLKGEN_SEL_1_r" hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x04 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR12DS_SEL_0_r,SDR12DS_SEL_1_r,SDR12DS_SEL_2_r,SDR12DS_SEL_3_r" bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "SDR12CLKGEN_SEL_0_r,SDR12CLKGEN_SEL_1_r" newline hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "HSDS_SEL_0_r,HSDS_SEL_1_r,HSDS_SEL_2_r,HSDS_SEL_3_r" newline bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "HSCLKGEN_SEL_0_r,HSCLKGEN_SEL_1_r" hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x08 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" bitfld.long 0x08 30.--31. "SDR50DS_SEL,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR50DS_SEL_0_r,SDR50DS_SEL_1_r,SDR50DS_SEL_2_r,SDR50DS_SEL_3_r" bitfld.long 0x08 26. "SDR50CLKGEN_SEL,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator" "SDR50CLKGEN_SEL_0_r,SDR50CLKGEN_SEL_1_r" newline hexmask.long.word 0x08 16.--25. 1. "SDR50SDCLK_SEL,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR25DS_SEL_0_r,SDR25DS_SEL_1_r,SDR25DS_SEL_2_r,SDR25DS_SEL_3_r" newline bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "SDR25CLKGEN_SEL_0_r,SDR25CLKGEN_SEL_1_r" hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x0C "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" bitfld.long 0x0C 30.--31. "DDR50DS_SEL,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "DDR50DS_SEL_0_r,DDR50DS_SEL_1_r,DDR50DS_SEL_2_r,DDR50DS_SEL_3_r" bitfld.long 0x0C 26. "DDR50CLKGEN_SEL,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator" "DDR50CLKGEN_SEL_0_r,DDR50CLKGEN_SEL_1_r" newline hexmask.long.word 0x0C 16.--25. 1. "DDR50SDCLK_SEL,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" bitfld.long 0x0C 14.--15. "SDR104DS_SEL,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR104DS_SEL_0_r,SDR104DS_SEL_1_r,SDR104DS_SEL_2_r,SDR104DS_SEL_3_r" newline bitfld.long 0x0C 10. "SDR104CLKGEN_SEL,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator" "SDR104CLKGEN_SEL_0_r,SDR104CLKGEN_SEL_1_r" hexmask.long.word 0x0C 0.--9. 1. "SDR104SDCLK_SEL,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" rgroup.long 0x2FC++0x03 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit" hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec" newline bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "SIS_0,SIS_1" width 0x0B tree.end repeat.end tree.end tree "Enhanced_DMA" tree "DSP1_EDMA_TPCC" base ad:0x40D10000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x400++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x440++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x404++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x444++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x428++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x42C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x46C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x430++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x470++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x434++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x474++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x438++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x478++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x43C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x47C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x140++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x144++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x148++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x14C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x408++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x150++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x154++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x158++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x15C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x160++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x164++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x168++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x16C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x170++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x174++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x40C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x44C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x178++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x17C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x180++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x184++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x188++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x18C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x190++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x194++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x198++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x19C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x410++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1AC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1BC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x414++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x454++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1CC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1DC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1EC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x418++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x458++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1FC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x41C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x45C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x420++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x460++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x424++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x464++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end tree "DSP2_EDMA_TPCC" base ad:0x41510000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x400++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x440++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x404++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x444++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x428++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x42C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x46C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x430++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x470++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x434++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x474++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x438++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x478++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x43C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x47C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x140++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x144++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x148++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x14C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x408++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x150++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x154++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x158++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x15C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x160++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x164++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x168++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x16C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x170++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x174++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x40C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x44C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x178++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x17C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x180++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x184++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x188++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x18C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x190++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x194++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x198++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x19C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x410++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1AC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1BC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x414++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x454++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1CC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1DC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1EC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x418++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x458++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1FC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x41C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x45C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x420++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x460++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x424++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x464++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end tree "DSP_EDMA_TPCC" base ad:0x1D10000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x400++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x440++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x404++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x444++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x428++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x42C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x46C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x430++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x470++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x434++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x474++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x438++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x478++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x43C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x47C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x140++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x144++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x148++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x14C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x408++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x150++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x154++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x158++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x15C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x160++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x164++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x168++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x16C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x170++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x174++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x40C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x44C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x178++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x17C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x180++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x184++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x188++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x18C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x190++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x194++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x198++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x19C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x410++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1AC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1BC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x414++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x454++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1CC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1DC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1EC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x418++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x458++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1FC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x41C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x45C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x420++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x460++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x424++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x464++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x43400000 ad:0x43500000 ) tree "SYS_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" rgroup.long 0x288++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" rgroup.long 0x284++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x24C++0x03 line.long 0x00 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x00 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization - FIFODEPTH_1" "DREGDEPTH_0,DREGDEPTH_1,DREGDEPTH_2,?" bitfld.long 0x00 4.--5. "BUSWIDTH,Bus Width Parameterization - BW_32BIT" "BUSWIDTH_0,BUSWIDTH_1,BUSWIDTH_2,?" bitfld.long 0x00 0.--2. "FIFOSIZE,Fifo Size Parameterization - FIFO_32_BYTE" "FIFOSIZE_0,FIFOSIZE_1,FIFOSIZE_2,FIFOSIZE_3,FIFOSIZE_4,?,?,?" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end repeat 2. (list 0. 1. )(list ad:0x41505000 ad:0x41506000 ) tree "DSP2_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" rgroup.long 0x288++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" rgroup.long 0x284++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x24C++0x03 line.long 0x00 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x00 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization - FIFODEPTH_1" "DREGDEPTH_0,DREGDEPTH_1,DREGDEPTH_2,?" bitfld.long 0x00 4.--5. "BUSWIDTH,Bus Width Parameterization - BW_32BIT" "BUSWIDTH_0,BUSWIDTH_1,BUSWIDTH_2,?" bitfld.long 0x00 0.--2. "FIFOSIZE,Fifo Size Parameterization - FIFO_32_BYTE" "FIFOSIZE_0,FIFOSIZE_1,FIFOSIZE_2,FIFOSIZE_3,FIFOSIZE_4,?,?,?" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end repeat 2. (list 0. 1. )(list ad:0x40D05000 ad:0x40D06000 ) tree "DSP1_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" rgroup.long 0x288++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" rgroup.long 0x284++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x24C++0x03 line.long 0x00 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x00 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization - FIFODEPTH_1" "DREGDEPTH_0,DREGDEPTH_1,DREGDEPTH_2,?" bitfld.long 0x00 4.--5. "BUSWIDTH,Bus Width Parameterization - BW_32BIT" "BUSWIDTH_0,BUSWIDTH_1,BUSWIDTH_2,?" bitfld.long 0x00 0.--2. "FIFOSIZE,Fifo Size Parameterization - FIFO_32_BYTE" "FIFOSIZE_0,FIFOSIZE_1,FIFOSIZE_2,FIFOSIZE_3,FIFOSIZE_4,?,?,?" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end repeat 2. (list 0. 1. )(list ad:0x1D05000 ad:0x1D06000 ) tree "DSP_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x03 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" rgroup.long 0x288++0x03 line.long 0x00 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" rgroup.long 0x284++0x03 line.long 0x00 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x24C++0x03 line.long 0x00 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x00 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization - FIFODEPTH_1" "DREGDEPTH_0,DREGDEPTH_1,DREGDEPTH_2,?" bitfld.long 0x00 4.--5. "BUSWIDTH,Bus Width Parameterization - BW_32BIT" "BUSWIDTH_0,BUSWIDTH_1,BUSWIDTH_2,?" bitfld.long 0x00 0.--2. "FIFOSIZE,Fifo Size Parameterization - FIFO_32_BYTE" "FIFOSIZE_0,FIFOSIZE_1,FIFOSIZE_2,FIFOSIZE_3,FIFOSIZE_4,?,?,?" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end tree "EVE1_EDMA_TPCC" base ad:0x420A0000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end tree "EVE2_EDMA_TPCC" base ad:0x421A0000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end repeat 2. (list 0. 1. )(list ad:0x42186000 ad:0x42187000 ) tree "EVE2_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end repeat 2. (list 0. 1. )(list ad:0x42086000 ad:0x42087000 ) tree "EVE1_EDMA_TPTC$1" base $2 tree "DMA_Channel_0" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end tree "DMA_Channel_1" rgroup.long 0x350++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x348++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" rgroup.long 0x354++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end rgroup.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" group.long 0x128++0x03 line.long 0x00 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x00 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x00 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x00 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" group.long 0x130++0x03 line.long 0x00 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x00 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x00 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" rgroup.long 0x12C++0x03 line.long 0x00 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x00 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x00 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x00 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x00 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" rgroup.long 0x120++0x03 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" group.long 0x10C++0x07 line.long 0x00 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x04 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x04 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x04 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" group.long 0x108++0x03 line.long 0x00 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" rgroup.long 0x104++0x03 line.long 0x00 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x00 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x00 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" group.long 0x210++0x03 line.long 0x00 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" group.long 0x208++0x07 line.long 0x00 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count" line.long 0x04 "EDMA_TPTCn_PDST,Program Set Destination Address" rgroup.long 0x214++0x03 line.long 0x00 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x07 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "Highest priority,Priority 1,?,?,?,?,?,Lowest priority" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" rgroup.long 0x250++0x03 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" rgroup.long 0x248++0x03 line.long 0x00 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x258++0x03 line.long 0x00 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" rgroup.long 0x260++0x03 line.long 0x00 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x254++0x03 line.long 0x00 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x07 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" rgroup.long 0x25C++0x03 line.long 0x00 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" rgroup.long 0x100++0x03 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 11.--12. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" width 0x0B tree.end repeat.end tree "SYS_EDMA_TPCC" base ad:0x43300000 tree "DMA_Channel_0" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x400++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x440++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end tree "DMA_Channel_1" group.long 0x4028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_1," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x403C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x221C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2218++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x104++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x244++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x34C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x348++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x402C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_1,Destination Address" group.long 0x220C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2208++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x222C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2228++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2224++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2220++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2234++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2230++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2204++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2200++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2214++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2210++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2274++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2270++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x225C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2258++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2254++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2250++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2264++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2260++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2278++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x226C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2268++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x814++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4020++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_1,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x404++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x444++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x204++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2288++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2284++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x228C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2280++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x384++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2294++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2290++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x604++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2244++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2240++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x223C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2238++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4024++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_1,Source Address" tree.end tree "DMA_Channel_10" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x428++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" tree.end tree "DMA_Channel_100" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end tree "DMA_Channel_101" group.long 0x4CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_101," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_101,Destination Address" group.long 0x4CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_101,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_101,Source Address" tree.end tree "DMA_Channel_102" group.long 0x4CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_102," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_102,Destination Address" group.long 0x4CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_102,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_102,Source Address" tree.end tree "DMA_Channel_103" group.long 0x4CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_103," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_103,Destination Address" group.long 0x4CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_103,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_103,Source Address" tree.end tree "DMA_Channel_104" group.long 0x4D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_104," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_104,Destination Address" group.long 0x4D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_104,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_104,Source Address" tree.end tree "DMA_Channel_105" group.long 0x4D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_105," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_105,Destination Address" group.long 0x4D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_105,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_105,Source Address" tree.end tree "DMA_Channel_106" group.long 0x4D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_106," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_106,Destination Address" group.long 0x4D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_106,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_106,Source Address" tree.end tree "DMA_Channel_107" group.long 0x4D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_107," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_107,Destination Address" group.long 0x4D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_107,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_107,Source Address" tree.end tree "DMA_Channel_108" group.long 0x4D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_108," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_108,Destination Address" group.long 0x4D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_108,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_108,Source Address" tree.end tree "DMA_Channel_109" group.long 0x4DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_109," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_109,Destination Address" group.long 0x4DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_109,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_109,Source Address" tree.end tree "DMA_Channel_11" group.long 0x4168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_11," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x417C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x12C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x416C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_11,Destination Address" group.long 0x4174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4160++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_11,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x42C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x46C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4164++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_11,Source Address" tree.end tree "DMA_Channel_110" group.long 0x4DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_110," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_110,Destination Address" group.long 0x4DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_110,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_110,Source Address" tree.end tree "DMA_Channel_111" group.long 0x4DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_111," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_111,Destination Address" group.long 0x4DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_111,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_111,Source Address" tree.end tree "DMA_Channel_112" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end tree "DMA_Channel_113" group.long 0x4E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_113," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_113,Destination Address" group.long 0x4E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_113,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_113,Source Address" tree.end tree "DMA_Channel_114" group.long 0x4E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_114," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_114,Destination Address" group.long 0x4E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_114,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_114,Source Address" tree.end tree "DMA_Channel_115" group.long 0x4E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_115," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_115,Destination Address" group.long 0x4E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_115,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_115,Source Address" tree.end tree "DMA_Channel_116" group.long 0x4E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_116," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_116,Destination Address" group.long 0x4E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_116,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_116,Source Address" tree.end tree "DMA_Channel_117" group.long 0x4EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_117," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_117,Destination Address" group.long 0x4EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_117,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_117,Source Address" tree.end tree "DMA_Channel_118" group.long 0x4EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_118," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_118,Destination Address" group.long 0x4ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_118,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_118,Source Address" tree.end tree "DMA_Channel_119" group.long 0x4EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_119," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_119,Destination Address" group.long 0x4EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_119,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_119,Source Address" tree.end tree "DMA_Channel_12" group.long 0x4188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_12," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x419C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x130++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x418C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_12,Destination Address" group.long 0x4194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4180++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_12,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x430++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x470++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4184++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_12,Source Address" tree.end tree "DMA_Channel_120" group.long 0x4F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_120," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_120,Destination Address" group.long 0x4F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_120,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_120,Source Address" tree.end tree "DMA_Channel_121" group.long 0x4F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_121," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_121,Destination Address" group.long 0x4F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_121,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_121,Source Address" tree.end tree "DMA_Channel_122" group.long 0x4F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_122," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_122,Destination Address" group.long 0x4F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_122,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_122,Source Address" tree.end tree "DMA_Channel_123" group.long 0x4F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_123," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_123,Destination Address" group.long 0x4F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_123,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_123,Source Address" tree.end tree "DMA_Channel_124" group.long 0x4F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_124," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_124,Destination Address" group.long 0x4F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_124,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_124,Source Address" tree.end tree "DMA_Channel_125" group.long 0x4FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_125," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_125,Destination Address" group.long 0x4FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_125,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_125,Source Address" tree.end tree "DMA_Channel_126" group.long 0x4FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_126," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_126,Destination Address" group.long 0x4FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_126,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_126,Source Address" tree.end tree "DMA_Channel_127" group.long 0x4FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_127," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_127,Destination Address" group.long 0x4FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_127,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_127,Source Address" tree.end tree "DMA_Channel_128" group.long 0x5008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_128,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_128," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x501C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_128,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_128,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x500C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_128,Destination Address" group.long 0x5014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_128,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5000++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_128,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_128,Source Address" tree.end tree "DMA_Channel_129" group.long 0x5028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_129,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_129," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x503C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_129,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_129,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x502C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_129,Destination Address" group.long 0x5034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_129,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5020++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_129,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_129,Source Address" tree.end tree "DMA_Channel_13" group.long 0x41A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_13," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x134++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_13,Destination Address" group.long 0x41B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_13,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x434++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x474++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_13,Source Address" tree.end tree "DMA_Channel_130" group.long 0x5048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_130,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_130," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x505C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_130,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_130,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x504C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_130,Destination Address" group.long 0x5054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_130,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5040++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_130,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_130,Source Address" tree.end tree "DMA_Channel_131" group.long 0x5068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_131,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_131," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x507C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_131,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_131,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x506C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_131,Destination Address" group.long 0x5074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_131,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5060++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_131,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_131,Source Address" tree.end tree "DMA_Channel_132" group.long 0x5088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_132,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_132," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x509C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_132,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_132,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x508C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_132,Destination Address" group.long 0x5094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_132,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5080++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_132,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_132,Source Address" tree.end tree "DMA_Channel_133" group.long 0x50A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_133,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x50B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_133," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x50BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_133,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x50B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_133,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x50AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_133,Destination Address" group.long 0x50B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_133,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x50A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_133,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_133,Source Address" tree.end tree "DMA_Channel_134" group.long 0x50C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_134,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x50D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_134," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x50DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_134,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x50D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_134,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x50CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_134,Destination Address" group.long 0x50D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_134,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x50C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_134,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_134,Source Address" tree.end tree "DMA_Channel_135" group.long 0x50E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_135,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x50F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_135," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x50FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_135,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x50F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_135,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x50EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_135,Destination Address" group.long 0x50F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_135,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x50E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_135,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_135,Source Address" tree.end tree "DMA_Channel_136" group.long 0x5108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_136,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_136," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x511C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_136,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_136,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x510C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_136,Destination Address" group.long 0x5114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_136,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5100++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_136,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_136,Source Address" tree.end tree "DMA_Channel_137" group.long 0x5128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_137,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_137," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x513C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_137,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_137,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x512C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_137,Destination Address" group.long 0x5134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_137,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5120++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_137,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_137,Source Address" tree.end tree "DMA_Channel_138" group.long 0x5148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_138,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_138," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x515C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_138,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_138,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x514C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_138,Destination Address" group.long 0x5154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_138,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_138,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_138,Source Address" tree.end tree "DMA_Channel_139" group.long 0x5168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_139,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_139," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x517C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_139,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_139,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x516C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_139,Destination Address" group.long 0x5174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_139,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5160++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_139,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_139,Source Address" tree.end tree "DMA_Channel_14" group.long 0x41C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_14," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x138++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_14,Destination Address" group.long 0x41D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_14,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x438++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x478++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_14,Source Address" tree.end tree "DMA_Channel_140" group.long 0x5188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_140,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_140," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x519C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_140,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_140,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x518C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_140,Destination Address" group.long 0x5194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_140,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5180++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_140,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_140,Source Address" tree.end tree "DMA_Channel_141" group.long 0x51A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_141,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x51B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_141," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x51BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_141,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x51B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_141,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x51AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_141,Destination Address" group.long 0x51B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_141,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x51A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_141,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_141,Source Address" tree.end tree "DMA_Channel_142" group.long 0x51C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_142,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x51D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_142," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x51DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_142,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x51D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_142,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x51CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_142,Destination Address" group.long 0x51D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_142,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x51C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_142,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_142,Source Address" tree.end tree "DMA_Channel_143" group.long 0x51E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_143,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x51F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_143," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x51FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_143,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x51F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_143,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x51EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_143,Destination Address" group.long 0x51F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_143,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x51E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_143,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_143,Source Address" tree.end tree "DMA_Channel_144" group.long 0x5208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_144,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_144," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x521C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_144,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_144,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x520C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_144,Destination Address" group.long 0x5214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_144,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_144,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_144,Source Address" tree.end tree "DMA_Channel_145" group.long 0x5228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_145,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_145," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x523C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_145,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_145,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x522C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_145,Destination Address" group.long 0x5234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_145,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_145,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_145,Source Address" tree.end tree "DMA_Channel_146" group.long 0x5248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_146,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_146," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x525C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_146,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_146,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x524C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_146,Destination Address" group.long 0x5254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_146,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_146,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_146,Source Address" tree.end tree "DMA_Channel_147" group.long 0x5268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_147,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_147," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x527C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_147,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_147,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x526C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_147,Destination Address" group.long 0x5274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_147,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_147,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_147,Source Address" tree.end tree "DMA_Channel_148" group.long 0x5288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_148,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_148," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x529C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_148,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_148,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x528C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_148,Destination Address" group.long 0x5294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_148,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_148,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_148,Source Address" tree.end tree "DMA_Channel_149" group.long 0x52A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_149,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x52B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_149," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x52BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_149,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x52B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_149,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x52AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_149,Destination Address" group.long 0x52B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_149,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x52A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_149,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_149,Source Address" tree.end tree "DMA_Channel_15" group.long 0x41E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x41F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_15," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x41FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x41F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x13C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x41EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_15,Destination Address" group.long 0x41F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x41E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_15,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x43C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x47C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x41E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_15,Source Address" tree.end tree "DMA_Channel_150" group.long 0x52C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_150,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x52D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_150," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x52DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_150,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x52D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_150,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x52CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_150,Destination Address" group.long 0x52D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_150,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x52C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_150,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_150,Source Address" tree.end tree "DMA_Channel_151" group.long 0x52E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_151,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x52F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_151," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x52FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_151,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x52F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_151,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x52EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_151,Destination Address" group.long 0x52F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_151,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x52E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_151,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_151,Source Address" tree.end tree "DMA_Channel_152" group.long 0x5308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_152,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_152," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x531C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_152,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_152,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x530C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_152,Destination Address" group.long 0x5314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_152,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_152,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_152,Source Address" tree.end tree "DMA_Channel_153" group.long 0x5328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_153,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_153," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x533C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_153,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_153,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x532C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_153,Destination Address" group.long 0x5334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_153,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_153,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_153,Source Address" tree.end tree "DMA_Channel_154" group.long 0x5348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_154,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_154," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x535C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_154,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_154,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x534C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_154,Destination Address" group.long 0x5354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_154,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_154,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_154,Source Address" tree.end tree "DMA_Channel_155" group.long 0x5368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_155,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_155," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x537C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_155,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_155,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x536C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_155,Destination Address" group.long 0x5374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_155,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_155,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_155,Source Address" tree.end tree "DMA_Channel_156" group.long 0x5388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_156,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_156," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x539C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_156,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_156,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x538C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_156,Destination Address" group.long 0x5394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_156,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_156,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_156,Source Address" tree.end tree "DMA_Channel_157" group.long 0x53A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_157,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x53B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_157," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x53BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_157,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x53B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_157,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x53AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_157,Destination Address" group.long 0x53B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_157,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x53A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_157,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_157,Source Address" tree.end tree "DMA_Channel_158" group.long 0x53C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_158,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x53D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_158," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x53DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_158,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x53D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_158,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x53CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_158,Destination Address" group.long 0x53D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_158,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x53C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_158,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_158,Source Address" tree.end tree "DMA_Channel_159" group.long 0x53E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_159,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x53F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_159," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x53FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_159,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x53F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_159,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x53EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_159,Destination Address" group.long 0x53F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_159,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x53E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_159,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_159,Source Address" tree.end tree "DMA_Channel_16" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x140++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end tree "DMA_Channel_160" group.long 0x5408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_160,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_160," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x541C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_160,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_160,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x540C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_160,Destination Address" group.long 0x5414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_160,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_160,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_160,Source Address" tree.end tree "DMA_Channel_161" group.long 0x5428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_161,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_161," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x543C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_161,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_161,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x542C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_161,Destination Address" group.long 0x5434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_161,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_161,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_161,Source Address" tree.end tree "DMA_Channel_162" group.long 0x5448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_162,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_162," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x545C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_162,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_162,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x544C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_162,Destination Address" group.long 0x5454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_162,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_162,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_162,Source Address" tree.end tree "DMA_Channel_163" group.long 0x5468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_163,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_163," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x547C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_163,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_163,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x546C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_163,Destination Address" group.long 0x5474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_163,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_163,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_163,Source Address" tree.end tree "DMA_Channel_164" group.long 0x5488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_164,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_164," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x549C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_164,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_164,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x548C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_164,Destination Address" group.long 0x5494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_164,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_164,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_164,Source Address" tree.end tree "DMA_Channel_165" group.long 0x54A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_165,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x54B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_165," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x54BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_165,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x54B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_165,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x54AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_165,Destination Address" group.long 0x54B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_165,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x54A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_165,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_165,Source Address" tree.end tree "DMA_Channel_166" group.long 0x54C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_166,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x54D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_166," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x54DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_166,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x54D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_166,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x54CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_166,Destination Address" group.long 0x54D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_166,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x54C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_166,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_166,Source Address" tree.end tree "DMA_Channel_167" group.long 0x54E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_167,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x54F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_167," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x54FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_167,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x54F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_167,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x54EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_167,Destination Address" group.long 0x54F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_167,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x54E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_167,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_167,Source Address" tree.end tree "DMA_Channel_168" group.long 0x5508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_168,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_168," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x551C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_168,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_168,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x550C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_168,Destination Address" group.long 0x5514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_168,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_168,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_168,Source Address" tree.end tree "DMA_Channel_169" group.long 0x5528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_169,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_169," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x553C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_169,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_169,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x552C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_169,Destination Address" group.long 0x5534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_169,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_169,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_169,Source Address" tree.end tree "DMA_Channel_17" group.long 0x4228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_17," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x423C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x144++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x422C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_17,Destination Address" group.long 0x4234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_17,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_17,Source Address" tree.end tree "DMA_Channel_170" group.long 0x5548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_170,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_170," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x555C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_170,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_170,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x554C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_170,Destination Address" group.long 0x5554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_170,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_170,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_170,Source Address" tree.end tree "DMA_Channel_171" group.long 0x5568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_171,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_171," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x557C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_171,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_171,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x556C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_171,Destination Address" group.long 0x5574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_171,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_171,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_171,Source Address" tree.end tree "DMA_Channel_172" group.long 0x5588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_172,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_172," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x559C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_172,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_172,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x558C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_172,Destination Address" group.long 0x5594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_172,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_172,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_172,Source Address" tree.end tree "DMA_Channel_173" group.long 0x55A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_173,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x55B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_173," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x55BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_173,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x55B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_173,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x55AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_173,Destination Address" group.long 0x55B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_173,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x55A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_173,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_173,Source Address" tree.end tree "DMA_Channel_174" group.long 0x55C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_174,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x55D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_174," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x55DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_174,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x55D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_174,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x55CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_174,Destination Address" group.long 0x55D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_174,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x55C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_174,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_174,Source Address" tree.end tree "DMA_Channel_175" group.long 0x55E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_175,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x55F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_175," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x55FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_175,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x55F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_175,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x55EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_175,Destination Address" group.long 0x55F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_175,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x55E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_175,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_175,Source Address" tree.end tree "DMA_Channel_176" group.long 0x5608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_176,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_176," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x561C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_176,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_176,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x560C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_176,Destination Address" group.long 0x5614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_176,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_176,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_176,Source Address" tree.end tree "DMA_Channel_177" group.long 0x5628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_177,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_177," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x563C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_177,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_177,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x562C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_177,Destination Address" group.long 0x5634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_177,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_177,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_177,Source Address" tree.end tree "DMA_Channel_178" group.long 0x5648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_178,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_178," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x565C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_178,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_178,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x564C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_178,Destination Address" group.long 0x5654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_178,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_178,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_178,Source Address" tree.end tree "DMA_Channel_179" group.long 0x5668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_179,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_179," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x567C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_179,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_179,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x566C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_179,Destination Address" group.long 0x5674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_179,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_179,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_179,Source Address" tree.end tree "DMA_Channel_18" group.long 0x4248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_18," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x425C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x148++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x424C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_18,Destination Address" group.long 0x4254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_18,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_18,Source Address" tree.end tree "DMA_Channel_180" group.long 0x5688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_180,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_180," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x569C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_180,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_180,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x568C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_180,Destination Address" group.long 0x5694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_180,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_180,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_180,Source Address" tree.end tree "DMA_Channel_181" group.long 0x56A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_181,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x56B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_181," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x56BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_181,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x56B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_181,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x56AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_181,Destination Address" group.long 0x56B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_181,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x56A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_181,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_181,Source Address" tree.end tree "DMA_Channel_182" group.long 0x56C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_182,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x56D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_182," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x56DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_182,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x56D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_182,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x56CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_182,Destination Address" group.long 0x56D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_182,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x56C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_182,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_182,Source Address" tree.end tree "DMA_Channel_183" group.long 0x56E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_183,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x56F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_183," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x56FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_183,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x56F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_183,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x56EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_183,Destination Address" group.long 0x56F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_183,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x56E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_183,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_183,Source Address" tree.end tree "DMA_Channel_184" group.long 0x5708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_184,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_184," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x571C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_184,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_184,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x570C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_184,Destination Address" group.long 0x5714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_184,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_184,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_184,Source Address" tree.end tree "DMA_Channel_185" group.long 0x5728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_185,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_185," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x573C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_185,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_185,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x572C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_185,Destination Address" group.long 0x5734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_185,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_185,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_185,Source Address" tree.end tree "DMA_Channel_186" group.long 0x5748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_186,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_186," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x575C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_186,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_186,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x574C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_186,Destination Address" group.long 0x5754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_186,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_186,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_186,Source Address" tree.end tree "DMA_Channel_187" group.long 0x5768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_187,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_187," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x577C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_187,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_187,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x576C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_187,Destination Address" group.long 0x5774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_187,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_187,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_187,Source Address" tree.end tree "DMA_Channel_188" group.long 0x5788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_188,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_188," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x579C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_188,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_188,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x578C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_188,Destination Address" group.long 0x5794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_188,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_188,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_188,Source Address" tree.end tree "DMA_Channel_189" group.long 0x57A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_189,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x57B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_189," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x57BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_189,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x57B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_189,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x57AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_189,Destination Address" group.long 0x57B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_189,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x57A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_189,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_189,Source Address" tree.end tree "DMA_Channel_19" group.long 0x4268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_19," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x427C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x14C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x426C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_19,Destination Address" group.long 0x4274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_19,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_19,Source Address" tree.end tree "DMA_Channel_190" group.long 0x57C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_190,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x57D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_190," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x57DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_190,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x57D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_190,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x57CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_190,Destination Address" group.long 0x57D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_190,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x57C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_190,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_190,Source Address" tree.end tree "DMA_Channel_191" group.long 0x57E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_191,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x57F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_191," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x57FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_191,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x57F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_191,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x57EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_191,Destination Address" group.long 0x57F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_191,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x57E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_191,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_191,Source Address" tree.end tree "DMA_Channel_192" group.long 0x5808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_192,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_192," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x581C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_192,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_192,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x580C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_192,Destination Address" group.long 0x5814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_192,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_192,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_192,Source Address" tree.end tree "DMA_Channel_193" group.long 0x5828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_193,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_193," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x583C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_193,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_193,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x582C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_193,Destination Address" group.long 0x5834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_193,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_193,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_193,Source Address" tree.end tree "DMA_Channel_194" group.long 0x5848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_194,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_194," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x585C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_194,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_194,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x584C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_194,Destination Address" group.long 0x5854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_194,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_194,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_194,Source Address" tree.end tree "DMA_Channel_195" group.long 0x5868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_195,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_195," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x587C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_195,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_195,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x586C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_195,Destination Address" group.long 0x5874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_195,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_195,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_195,Source Address" tree.end tree "DMA_Channel_196" group.long 0x5888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_196,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_196," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x589C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_196,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_196,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x588C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_196,Destination Address" group.long 0x5894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_196,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_196,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_196,Source Address" tree.end tree "DMA_Channel_197" group.long 0x58A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_197,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x58B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_197," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x58BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_197,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x58B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_197,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x58AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_197,Destination Address" group.long 0x58B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_197,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x58A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_197,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_197,Source Address" tree.end tree "DMA_Channel_198" group.long 0x58C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_198,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x58D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_198," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x58DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_198,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x58D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_198,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x58CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_198,Destination Address" group.long 0x58D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_198,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x58C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_198,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_198,Source Address" tree.end tree "DMA_Channel_199" group.long 0x58E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_199,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x58F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_199," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x58FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_199,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x58F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_199,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x58EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_199,Destination Address" group.long 0x58F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_199,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x58E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_199,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_199,Source Address" tree.end tree "DMA_Channel_2" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x408++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end tree "DMA_Channel_20" group.long 0x4288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_20," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x429C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x150++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x428C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_20,Destination Address" group.long 0x4294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_20,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_20,Source Address" tree.end tree "DMA_Channel_200" group.long 0x5908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_200,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_200," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x591C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_200,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_200,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x590C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_200,Destination Address" group.long 0x5914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_200,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_200,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_200,Source Address" tree.end tree "DMA_Channel_201" group.long 0x5928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_201,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_201," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x593C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_201,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_201,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x592C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_201,Destination Address" group.long 0x5934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_201,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_201,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_201,Source Address" tree.end tree "DMA_Channel_202" group.long 0x5948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_202,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_202," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x595C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_202,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_202,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x594C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_202,Destination Address" group.long 0x5954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_202,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_202,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_202,Source Address" tree.end tree "DMA_Channel_203" group.long 0x5968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_203,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_203," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x597C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_203,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_203,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x596C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_203,Destination Address" group.long 0x5974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_203,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_203,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_203,Source Address" tree.end tree "DMA_Channel_204" group.long 0x5988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_204,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_204," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x599C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_204,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_204,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x598C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_204,Destination Address" group.long 0x5994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_204,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_204,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_204,Source Address" tree.end tree "DMA_Channel_205" group.long 0x59A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_205,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x59B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_205," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x59BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_205,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x59B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_205,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x59AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_205,Destination Address" group.long 0x59B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_205,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x59A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_205,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_205,Source Address" tree.end tree "DMA_Channel_206" group.long 0x59C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_206,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x59D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_206," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x59DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_206,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x59D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_206,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x59CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_206,Destination Address" group.long 0x59D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_206,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x59C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_206,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_206,Source Address" tree.end tree "DMA_Channel_207" group.long 0x59E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_207,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x59F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_207," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x59FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_207,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x59F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_207,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x59EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_207,Destination Address" group.long 0x59F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_207,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x59E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_207,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_207,Source Address" tree.end tree "DMA_Channel_208" group.long 0x5A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_208,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_208," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_208,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_208,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_208,Destination Address" group.long 0x5A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_208,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_208,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_208,Source Address" tree.end tree "DMA_Channel_209" group.long 0x5A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_209,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_209," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_209,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_209,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_209,Destination Address" group.long 0x5A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_209,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_209,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_209,Source Address" tree.end tree "DMA_Channel_21" group.long 0x42A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_21," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x154++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_21,Destination Address" group.long 0x42B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_21,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_21,Source Address" tree.end tree "DMA_Channel_210" group.long 0x5A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_210,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_210," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_210,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_210,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_210,Destination Address" group.long 0x5A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_210,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_210,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_210,Source Address" tree.end tree "DMA_Channel_211" group.long 0x5A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_211,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_211," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_211,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_211,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_211,Destination Address" group.long 0x5A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_211,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_211,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_211,Source Address" tree.end tree "DMA_Channel_212" group.long 0x5A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_212,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_212," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_212,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_212,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_212,Destination Address" group.long 0x5A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_212,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_212,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_212,Source Address" tree.end tree "DMA_Channel_213" group.long 0x5AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_213,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_213," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_213,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_213,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_213,Destination Address" group.long 0x5AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_213,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_213,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_213,Source Address" tree.end tree "DMA_Channel_214" group.long 0x5AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_214,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_214," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_214,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_214,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_214,Destination Address" group.long 0x5AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_214,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_214,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_214,Source Address" tree.end tree "DMA_Channel_215" group.long 0x5AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_215,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_215," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_215,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_215,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_215,Destination Address" group.long 0x5AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_215,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_215,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_215,Source Address" tree.end tree "DMA_Channel_216" group.long 0x5B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_216,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_216," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_216,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_216,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_216,Destination Address" group.long 0x5B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_216,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_216,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_216,Source Address" tree.end tree "DMA_Channel_217" group.long 0x5B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_217,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_217," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_217,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_217,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_217,Destination Address" group.long 0x5B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_217,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_217,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_217,Source Address" tree.end tree "DMA_Channel_218" group.long 0x5B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_218,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_218," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_218,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_218,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_218,Destination Address" group.long 0x5B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_218,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_218,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_218,Source Address" tree.end tree "DMA_Channel_219" group.long 0x5B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_219,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_219," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_219,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_219,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_219,Destination Address" group.long 0x5B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_219,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_219,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_219,Source Address" tree.end tree "DMA_Channel_22" group.long 0x42C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_22," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x158++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_22,Destination Address" group.long 0x42D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_22,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_22,Source Address" tree.end tree "DMA_Channel_220" group.long 0x5B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_220,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_220," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_220,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_220,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_220,Destination Address" group.long 0x5B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_220,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_220,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_220,Source Address" tree.end tree "DMA_Channel_221" group.long 0x5BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_221,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_221," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_221,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_221,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_221,Destination Address" group.long 0x5BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_221,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_221,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_221,Source Address" tree.end tree "DMA_Channel_222" group.long 0x5BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_222,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_222," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_222,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_222,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_222,Destination Address" group.long 0x5BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_222,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_222,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_222,Source Address" tree.end tree "DMA_Channel_223" group.long 0x5BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_223,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_223," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_223,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_223,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_223,Destination Address" group.long 0x5BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_223,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_223,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_223,Source Address" tree.end tree "DMA_Channel_224" group.long 0x5C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_224,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_224," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_224,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_224,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_224,Destination Address" group.long 0x5C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_224,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_224,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_224,Source Address" tree.end tree "DMA_Channel_225" group.long 0x5C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_225,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_225," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_225,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_225,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_225,Destination Address" group.long 0x5C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_225,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_225,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_225,Source Address" tree.end tree "DMA_Channel_226" group.long 0x5C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_226,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_226," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_226,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_226,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_226,Destination Address" group.long 0x5C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_226,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_226,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_226,Source Address" tree.end tree "DMA_Channel_227" group.long 0x5C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_227,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_227," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_227,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_227,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_227,Destination Address" group.long 0x5C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_227,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_227,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_227,Source Address" tree.end tree "DMA_Channel_228" group.long 0x5C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_228,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_228," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_228,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_228,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_228,Destination Address" group.long 0x5C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_228,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_228,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_228,Source Address" tree.end tree "DMA_Channel_229" group.long 0x5CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_229,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_229," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_229,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_229,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_229,Destination Address" group.long 0x5CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_229,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_229,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_229,Source Address" tree.end tree "DMA_Channel_23" group.long 0x42E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x42F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_23," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x42FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x42F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x15C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x42EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_23,Destination Address" group.long 0x42F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x42E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_23,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_23,Source Address" tree.end tree "DMA_Channel_230" group.long 0x5CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_230,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_230," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_230,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_230,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_230,Destination Address" group.long 0x5CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_230,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_230,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_230,Source Address" tree.end tree "DMA_Channel_231" group.long 0x5CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_231,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_231," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_231,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_231,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_231,Destination Address" group.long 0x5CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_231,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_231,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_231,Source Address" tree.end tree "DMA_Channel_232" group.long 0x5D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_232,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_232," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_232,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_232,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_232,Destination Address" group.long 0x5D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_232,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_232,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_232,Source Address" tree.end tree "DMA_Channel_233" group.long 0x5D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_233,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_233," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_233,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_233,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_233,Destination Address" group.long 0x5D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_233,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_233,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_233,Source Address" tree.end tree "DMA_Channel_234" group.long 0x5D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_234,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_234," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_234,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_234,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_234,Destination Address" group.long 0x5D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_234,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_234,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_234,Source Address" tree.end tree "DMA_Channel_235" group.long 0x5D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_235,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_235," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_235,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_235,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_235,Destination Address" group.long 0x5D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_235,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_235,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_235,Source Address" tree.end tree "DMA_Channel_236" group.long 0x5D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_236,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_236," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_236,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_236,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_236,Destination Address" group.long 0x5D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_236,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_236,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_236,Source Address" tree.end tree "DMA_Channel_237" group.long 0x5DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_237,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_237," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_237,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_237,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_237,Destination Address" group.long 0x5DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_237,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_237,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_237,Source Address" tree.end tree "DMA_Channel_238" group.long 0x5DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_238,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_238," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_238,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_238,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_238,Destination Address" group.long 0x5DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_238,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_238,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_238,Source Address" tree.end tree "DMA_Channel_239" group.long 0x5DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_239,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_239," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_239,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_239,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_239,Destination Address" group.long 0x5DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_239,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_239,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_239,Source Address" tree.end tree "DMA_Channel_24" group.long 0x4308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_24," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x431C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x160++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x430C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_24,Destination Address" group.long 0x4314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_24,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_24,Source Address" tree.end tree "DMA_Channel_240" group.long 0x5E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_240,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_240," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_240,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_240,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_240,Destination Address" group.long 0x5E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_240,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_240,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_240,Source Address" tree.end tree "DMA_Channel_241" group.long 0x5E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_241,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_241," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_241,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_241,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_241,Destination Address" group.long 0x5E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_241,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_241,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_241,Source Address" tree.end tree "DMA_Channel_242" group.long 0x5E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_242,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_242," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_242,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_242,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_242,Destination Address" group.long 0x5E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_242,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_242,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_242,Source Address" tree.end tree "DMA_Channel_243" group.long 0x5E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_243,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_243," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_243,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_243,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_243,Destination Address" group.long 0x5E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_243,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_243,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_243,Source Address" tree.end tree "DMA_Channel_244" group.long 0x5E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_244,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_244," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_244,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_244,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_244,Destination Address" group.long 0x5E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_244,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_244,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_244,Source Address" tree.end tree "DMA_Channel_245" group.long 0x5EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_245,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_245," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_245,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_245,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_245,Destination Address" group.long 0x5EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_245,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_245,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_245,Source Address" tree.end tree "DMA_Channel_246" group.long 0x5EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_246,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_246," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_246,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_246,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_246,Destination Address" group.long 0x5ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_246,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_246,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_246,Source Address" tree.end tree "DMA_Channel_247" group.long 0x5EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_247,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_247," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_247,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_247,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_247,Destination Address" group.long 0x5EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_247,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_247,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_247,Source Address" tree.end tree "DMA_Channel_248" group.long 0x5F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_248,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_248," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_248,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_248,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_248,Destination Address" group.long 0x5F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_248,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_248,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_248,Source Address" tree.end tree "DMA_Channel_249" group.long 0x5F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_249,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_249," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_249,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_249,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_249,Destination Address" group.long 0x5F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_249,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_249,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_249,Source Address" tree.end tree "DMA_Channel_25" group.long 0x4328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_25," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x433C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x164++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x432C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_25,Destination Address" group.long 0x4334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_25,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_25,Source Address" tree.end tree "DMA_Channel_250" group.long 0x5F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_250,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_250," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_250,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_250,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_250,Destination Address" group.long 0x5F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_250,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_250,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_250,Source Address" tree.end tree "DMA_Channel_251" group.long 0x5F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_251,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_251," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_251,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_251,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_251,Destination Address" group.long 0x5F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_251,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_251,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_251,Source Address" tree.end tree "DMA_Channel_252" group.long 0x5F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_252,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_252," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_252,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_252,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_252,Destination Address" group.long 0x5F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_252,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_252,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_252,Source Address" tree.end tree "DMA_Channel_253" group.long 0x5FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_253,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_253," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_253,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_253,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_253,Destination Address" group.long 0x5FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_253,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_253,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_253,Source Address" tree.end tree "DMA_Channel_254" group.long 0x5FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_254,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_254," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_254,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_254,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_254,Destination Address" group.long 0x5FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_254,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_254,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_254,Source Address" tree.end tree "DMA_Channel_255" group.long 0x5FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_255,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x5FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_255," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x5FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_255,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x5FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_255,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x5FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_255,Destination Address" group.long 0x5FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_255,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x5FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_255,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_255,Source Address" tree.end tree "DMA_Channel_256" group.long 0x6008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_256,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_256," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x601C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_256,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_256,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x600C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_256,Destination Address" group.long 0x6014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_256,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6000++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_256,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_256,Source Address" tree.end tree "DMA_Channel_257" group.long 0x6028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_257,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_257," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x603C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_257,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_257,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x602C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_257,Destination Address" group.long 0x6034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_257,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6020++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_257,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_257,Source Address" tree.end tree "DMA_Channel_258" group.long 0x6048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_258,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_258," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x605C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_258,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_258,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x604C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_258,Destination Address" group.long 0x6054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_258,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6040++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_258,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_258,Source Address" tree.end tree "DMA_Channel_259" group.long 0x6068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_259,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_259," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x607C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_259,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_259,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x606C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_259,Destination Address" group.long 0x6074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_259,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6060++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_259,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_259,Source Address" tree.end tree "DMA_Channel_26" group.long 0x4348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_26," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x435C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x168++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x434C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_26,Destination Address" group.long 0x4354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_26,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_26,Source Address" tree.end tree "DMA_Channel_260" group.long 0x6088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_260,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_260," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x609C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_260,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_260,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x608C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_260,Destination Address" group.long 0x6094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_260,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6080++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_260,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_260,Source Address" tree.end tree "DMA_Channel_261" group.long 0x60A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_261,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x60B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_261," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x60BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_261,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x60B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_261,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x60AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_261,Destination Address" group.long 0x60B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_261,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x60A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_261,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_261,Source Address" tree.end tree "DMA_Channel_262" group.long 0x60C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_262,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x60D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_262," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x60DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_262,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x60D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_262,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x60CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_262,Destination Address" group.long 0x60D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_262,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x60C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_262,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_262,Source Address" tree.end tree "DMA_Channel_263" group.long 0x60E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_263,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x60F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_263," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x60FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_263,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x60F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_263,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x60EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_263,Destination Address" group.long 0x60F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_263,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x60E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_263,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_263,Source Address" tree.end tree "DMA_Channel_264" group.long 0x6108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_264,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_264," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x611C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_264,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_264,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x610C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_264,Destination Address" group.long 0x6114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_264,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6100++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_264,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_264,Source Address" tree.end tree "DMA_Channel_265" group.long 0x6128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_265,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_265," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x613C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_265,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_265,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x612C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_265,Destination Address" group.long 0x6134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_265,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6120++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_265,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_265,Source Address" tree.end tree "DMA_Channel_266" group.long 0x6148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_266,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_266," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x615C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_266,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_266,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x614C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_266,Destination Address" group.long 0x6154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_266,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_266,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_266,Source Address" tree.end tree "DMA_Channel_267" group.long 0x6168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_267,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_267," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x617C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_267,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_267,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x616C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_267,Destination Address" group.long 0x6174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_267,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6160++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_267,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_267,Source Address" tree.end tree "DMA_Channel_268" group.long 0x6188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_268,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_268," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x619C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_268,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_268,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x618C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_268,Destination Address" group.long 0x6194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_268,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6180++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_268,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_268,Source Address" tree.end tree "DMA_Channel_269" group.long 0x61A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_269,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x61B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_269," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x61BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_269,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x61B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_269,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x61AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_269,Destination Address" group.long 0x61B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_269,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x61A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_269,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_269,Source Address" tree.end tree "DMA_Channel_27" group.long 0x4368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_27," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x437C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x16C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x436C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_27,Destination Address" group.long 0x4374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_27,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_27,Source Address" tree.end tree "DMA_Channel_270" group.long 0x61C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_270,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x61D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_270," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x61DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_270,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x61D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_270,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x61CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_270,Destination Address" group.long 0x61D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_270,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x61C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_270,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_270,Source Address" tree.end tree "DMA_Channel_271" group.long 0x61E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_271,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x61F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_271," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x61FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_271,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x61F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_271,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x61EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_271,Destination Address" group.long 0x61F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_271,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x61E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_271,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_271,Source Address" tree.end tree "DMA_Channel_272" group.long 0x6208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_272,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_272," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x621C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_272,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_272,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x620C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_272,Destination Address" group.long 0x6214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_272,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_272,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_272,Source Address" tree.end tree "DMA_Channel_273" group.long 0x6228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_273,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_273," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x623C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_273,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_273,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x622C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_273,Destination Address" group.long 0x6234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_273,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_273,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_273,Source Address" tree.end tree "DMA_Channel_274" group.long 0x6248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_274,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_274," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x625C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_274,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_274,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x624C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_274,Destination Address" group.long 0x6254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_274,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_274,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_274,Source Address" tree.end tree "DMA_Channel_275" group.long 0x6268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_275,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_275," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x627C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_275,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_275,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x626C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_275,Destination Address" group.long 0x6274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_275,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_275,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_275,Source Address" tree.end tree "DMA_Channel_276" group.long 0x6288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_276,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_276," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x629C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_276,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_276,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x628C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_276,Destination Address" group.long 0x6294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_276,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_276,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_276,Source Address" tree.end tree "DMA_Channel_277" group.long 0x62A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_277,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x62B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_277," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x62BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_277,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x62B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_277,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x62AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_277,Destination Address" group.long 0x62B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_277,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x62A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_277,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_277,Source Address" tree.end tree "DMA_Channel_278" group.long 0x62C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_278,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x62D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_278," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x62DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_278,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x62D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_278,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x62CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_278,Destination Address" group.long 0x62D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_278,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x62C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_278,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_278,Source Address" tree.end tree "DMA_Channel_279" group.long 0x62E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_279,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x62F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_279," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x62FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_279,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x62F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_279,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x62EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_279,Destination Address" group.long 0x62F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_279,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x62E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_279,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_279,Source Address" tree.end tree "DMA_Channel_28" group.long 0x4388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_28," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x439C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x170++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x438C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_28,Destination Address" group.long 0x4394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_28,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_28,Source Address" tree.end tree "DMA_Channel_280" group.long 0x6308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_280,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_280," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x631C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_280,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_280,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x630C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_280,Destination Address" group.long 0x6314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_280,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_280,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_280,Source Address" tree.end tree "DMA_Channel_281" group.long 0x6328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_281,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_281," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x633C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_281,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_281,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x632C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_281,Destination Address" group.long 0x6334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_281,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_281,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_281,Source Address" tree.end tree "DMA_Channel_282" group.long 0x6348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_282,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_282," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x635C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_282,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_282,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x634C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_282,Destination Address" group.long 0x6354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_282,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_282,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_282,Source Address" tree.end tree "DMA_Channel_283" group.long 0x6368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_283,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_283," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x637C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_283,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_283,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x636C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_283,Destination Address" group.long 0x6374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_283,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_283,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_283,Source Address" tree.end tree "DMA_Channel_284" group.long 0x6388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_284,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_284," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x639C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_284,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_284,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x638C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_284,Destination Address" group.long 0x6394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_284,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_284,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_284,Source Address" tree.end tree "DMA_Channel_285" group.long 0x63A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_285,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x63B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_285," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x63BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_285,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x63B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_285,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x63AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_285,Destination Address" group.long 0x63B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_285,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x63A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_285,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_285,Source Address" tree.end tree "DMA_Channel_286" group.long 0x63C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_286,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x63D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_286," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x63DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_286,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x63D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_286,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x63CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_286,Destination Address" group.long 0x63D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_286,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x63C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_286,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_286,Source Address" tree.end tree "DMA_Channel_287" group.long 0x63E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_287,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x63F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_287," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x63FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_287,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x63F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_287,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x63EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_287,Destination Address" group.long 0x63F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_287,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x63E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_287,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_287,Source Address" tree.end tree "DMA_Channel_288" group.long 0x6408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_288,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_288," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x641C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_288,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_288,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x640C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_288,Destination Address" group.long 0x6414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_288,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_288,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_288,Source Address" tree.end tree "DMA_Channel_289" group.long 0x6428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_289,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_289," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x643C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_289,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_289,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x642C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_289,Destination Address" group.long 0x6434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_289,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_289,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_289,Source Address" tree.end tree "DMA_Channel_29" group.long 0x43A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_29," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x174++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_29,Destination Address" group.long 0x43B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_29,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_29,Source Address" tree.end tree "DMA_Channel_290" group.long 0x6448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_290,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_290," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x645C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_290,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_290,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x644C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_290,Destination Address" group.long 0x6454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_290,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_290,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_290,Source Address" tree.end tree "DMA_Channel_291" group.long 0x6468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_291,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_291," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x647C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_291,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_291,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x646C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_291,Destination Address" group.long 0x6474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_291,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_291,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_291,Source Address" tree.end tree "DMA_Channel_292" group.long 0x6488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_292,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_292," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x649C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_292,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_292,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x648C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_292,Destination Address" group.long 0x6494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_292,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_292,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_292,Source Address" tree.end tree "DMA_Channel_293" group.long 0x64A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_293,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x64B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_293," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x64BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_293,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x64B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_293,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x64AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_293,Destination Address" group.long 0x64B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_293,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x64A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_293,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_293,Source Address" tree.end tree "DMA_Channel_294" group.long 0x64C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_294,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x64D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_294," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x64DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_294,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x64D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_294,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x64CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_294,Destination Address" group.long 0x64D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_294,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x64C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_294,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_294,Source Address" tree.end tree "DMA_Channel_295" group.long 0x64E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_295,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x64F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_295," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x64FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_295,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x64F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_295,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x64EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_295,Destination Address" group.long 0x64F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_295,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x64E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_295,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_295,Source Address" tree.end tree "DMA_Channel_296" group.long 0x6508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_296,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_296," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x651C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_296,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_296,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x650C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_296,Destination Address" group.long 0x6514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_296,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_296,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_296,Source Address" tree.end tree "DMA_Channel_297" group.long 0x6528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_297,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_297," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x653C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_297,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_297,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x652C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_297,Destination Address" group.long 0x6534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_297,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_297,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_297,Source Address" tree.end tree "DMA_Channel_298" group.long 0x6548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_298,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_298," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x655C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_298,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_298,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x654C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_298,Destination Address" group.long 0x6554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_298,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_298,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_298,Source Address" tree.end tree "DMA_Channel_299" group.long 0x6568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_299,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_299," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x657C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_299,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_299,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x656C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_299,Destination Address" group.long 0x6574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_299,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_299,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_299,Source Address" tree.end tree "DMA_Channel_3" group.long 0x4068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_3," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x407C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x261C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2618++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x10C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x24C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x35C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x358++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x406C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_3,Destination Address" group.long 0x260C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2608++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x262C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2628++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2624++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2620++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2634++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2630++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2604++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2600++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2614++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2610++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2674++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2670++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x265C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2658++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2654++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2650++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2664++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2660++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2678++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x266C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2668++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x81C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4060++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_3,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x40C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x44C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2688++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2684++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x268C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2680++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x38C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2694++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2690++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2644++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2640++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x263C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2638++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4064++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_3,Source Address" tree.end tree "DMA_Channel_30" group.long 0x43C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_30," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x178++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_30,Destination Address" group.long 0x43D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_30,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_30,Source Address" tree.end tree "DMA_Channel_300" group.long 0x6588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_300,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_300," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x659C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_300,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_300,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x658C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_300,Destination Address" group.long 0x6594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_300,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_300,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_300,Source Address" tree.end tree "DMA_Channel_301" group.long 0x65A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_301,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x65B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_301," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x65BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_301,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x65B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_301,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x65AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_301,Destination Address" group.long 0x65B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_301,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x65A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_301,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_301,Source Address" tree.end tree "DMA_Channel_302" group.long 0x65C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_302,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x65D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_302," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x65DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_302,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x65D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_302,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x65CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_302,Destination Address" group.long 0x65D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_302,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x65C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_302,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_302,Source Address" tree.end tree "DMA_Channel_303" group.long 0x65E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_303,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x65F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_303," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x65FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_303,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x65F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_303,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x65EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_303,Destination Address" group.long 0x65F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_303,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x65E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_303,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_303,Source Address" tree.end tree "DMA_Channel_304" group.long 0x6608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_304,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_304," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x661C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_304,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_304,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x660C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_304,Destination Address" group.long 0x6614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_304,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_304,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_304,Source Address" tree.end tree "DMA_Channel_305" group.long 0x6628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_305,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_305," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x663C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_305,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_305,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x662C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_305,Destination Address" group.long 0x6634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_305,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_305,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_305,Source Address" tree.end tree "DMA_Channel_306" group.long 0x6648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_306,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_306," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x665C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_306,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_306,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x664C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_306,Destination Address" group.long 0x6654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_306,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_306,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_306,Source Address" tree.end tree "DMA_Channel_307" group.long 0x6668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_307,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_307," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x667C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_307,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_307,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x666C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_307,Destination Address" group.long 0x6674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_307,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_307,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_307,Source Address" tree.end tree "DMA_Channel_308" group.long 0x6688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_308,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_308," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x669C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_308,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_308,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x668C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_308,Destination Address" group.long 0x6694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_308,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_308,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_308,Source Address" tree.end tree "DMA_Channel_309" group.long 0x66A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_309,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x66B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_309," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x66BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_309,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x66B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_309,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x66AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_309,Destination Address" group.long 0x66B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_309,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x66A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_309,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_309,Source Address" tree.end tree "DMA_Channel_31" group.long 0x43E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x43F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_31," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x43FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x43F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x17C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x43EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_31,Destination Address" group.long 0x43F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x43E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_31,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_31,Source Address" tree.end tree "DMA_Channel_310" group.long 0x66C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_310,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x66D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_310," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x66DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_310,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x66D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_310,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x66CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_310,Destination Address" group.long 0x66D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_310,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x66C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_310,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_310,Source Address" tree.end tree "DMA_Channel_311" group.long 0x66E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_311,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x66F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_311," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x66FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_311,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x66F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_311,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x66EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_311,Destination Address" group.long 0x66F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_311,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x66E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_311,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_311,Source Address" tree.end tree "DMA_Channel_312" group.long 0x6708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_312,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_312," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x671C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_312,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_312,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x670C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_312,Destination Address" group.long 0x6714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_312,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_312,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_312,Source Address" tree.end tree "DMA_Channel_313" group.long 0x6728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_313,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_313," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x673C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_313,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_313,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x672C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_313,Destination Address" group.long 0x6734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_313,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_313,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_313,Source Address" tree.end tree "DMA_Channel_314" group.long 0x6748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_314,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_314," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x675C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_314,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_314,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x674C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_314,Destination Address" group.long 0x6754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_314,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_314,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_314,Source Address" tree.end tree "DMA_Channel_315" group.long 0x6768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_315,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_315," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x677C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_315,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_315,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x676C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_315,Destination Address" group.long 0x6774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_315,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_315,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_315,Source Address" tree.end tree "DMA_Channel_316" group.long 0x6788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_316,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_316," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x679C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_316,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_316,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x678C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_316,Destination Address" group.long 0x6794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_316,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_316,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_316,Source Address" tree.end tree "DMA_Channel_317" group.long 0x67A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_317,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x67B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_317," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x67BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_317,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x67B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_317,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x67AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_317,Destination Address" group.long 0x67B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_317,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x67A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_317,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_317,Source Address" tree.end tree "DMA_Channel_318" group.long 0x67C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_318,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x67D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_318," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x67DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_318,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x67D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_318,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x67CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_318,Destination Address" group.long 0x67D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_318,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x67C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_318,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_318,Source Address" tree.end tree "DMA_Channel_319" group.long 0x67E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_319,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x67F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_319," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x67FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_319,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x67F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_319,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x67EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_319,Destination Address" group.long 0x67F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_319,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x67E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_319,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_319,Source Address" tree.end tree "DMA_Channel_32" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x180++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end tree "DMA_Channel_320" group.long 0x6808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_320,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_320," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x681C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_320,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_320,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x680C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_320,Destination Address" group.long 0x6814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_320,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_320,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_320,Source Address" tree.end tree "DMA_Channel_321" group.long 0x6828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_321,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_321," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x683C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_321,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_321,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x682C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_321,Destination Address" group.long 0x6834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_321,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_321,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_321,Source Address" tree.end tree "DMA_Channel_322" group.long 0x6848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_322,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_322," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x685C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_322,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_322,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x684C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_322,Destination Address" group.long 0x6854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_322,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_322,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_322,Source Address" tree.end tree "DMA_Channel_323" group.long 0x6868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_323,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_323," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x687C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_323,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_323,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x686C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_323,Destination Address" group.long 0x6874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_323,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_323,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_323,Source Address" tree.end tree "DMA_Channel_324" group.long 0x6888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_324,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_324," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x689C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_324,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_324,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x688C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_324,Destination Address" group.long 0x6894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_324,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_324,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_324,Source Address" tree.end tree "DMA_Channel_325" group.long 0x68A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_325,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x68B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_325," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x68BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_325,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x68B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_325,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x68AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_325,Destination Address" group.long 0x68B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_325,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x68A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_325,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_325,Source Address" tree.end tree "DMA_Channel_326" group.long 0x68C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_326,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x68D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_326," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x68DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_326,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x68D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_326,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x68CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_326,Destination Address" group.long 0x68D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_326,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x68C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_326,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_326,Source Address" tree.end tree "DMA_Channel_327" group.long 0x68E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_327,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x68F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_327," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x68FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_327,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x68F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_327,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x68EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_327,Destination Address" group.long 0x68F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_327,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x68E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_327,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_327,Source Address" tree.end tree "DMA_Channel_328" group.long 0x6908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_328,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_328," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x691C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_328,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_328,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x690C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_328,Destination Address" group.long 0x6914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_328,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_328,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_328,Source Address" tree.end tree "DMA_Channel_329" group.long 0x6928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_329,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_329," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x693C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_329,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_329,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x692C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_329,Destination Address" group.long 0x6934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_329,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_329,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_329,Source Address" tree.end tree "DMA_Channel_33" group.long 0x4428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_33," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x443C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x184++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x442C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_33,Destination Address" group.long 0x4434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_33,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_33,Source Address" tree.end tree "DMA_Channel_330" group.long 0x6948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_330,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_330," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x695C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_330,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_330,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x694C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_330,Destination Address" group.long 0x6954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_330,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_330,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_330,Source Address" tree.end tree "DMA_Channel_331" group.long 0x6968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_331,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_331," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x697C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_331,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_331,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x696C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_331,Destination Address" group.long 0x6974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_331,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_331,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_331,Source Address" tree.end tree "DMA_Channel_332" group.long 0x6988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_332,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_332," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x699C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_332,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_332,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x698C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_332,Destination Address" group.long 0x6994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_332,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_332,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_332,Source Address" tree.end tree "DMA_Channel_333" group.long 0x69A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_333,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x69B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_333," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x69BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_333,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x69B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_333,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x69AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_333,Destination Address" group.long 0x69B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_333,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x69A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_333,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_333,Source Address" tree.end tree "DMA_Channel_334" group.long 0x69C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_334,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x69D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_334," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x69DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_334,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x69D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_334,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x69CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_334,Destination Address" group.long 0x69D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_334,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x69C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_334,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_334,Source Address" tree.end tree "DMA_Channel_335" group.long 0x69E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_335,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x69F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_335," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x69FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_335,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x69F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_335,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x69EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_335,Destination Address" group.long 0x69F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_335,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x69E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_335,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_335,Source Address" tree.end tree "DMA_Channel_336" group.long 0x6A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_336,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_336," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_336,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_336,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_336,Destination Address" group.long 0x6A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_336,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_336,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_336,Source Address" tree.end tree "DMA_Channel_337" group.long 0x6A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_337,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_337," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_337,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_337,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_337,Destination Address" group.long 0x6A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_337,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_337,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_337,Source Address" tree.end tree "DMA_Channel_338" group.long 0x6A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_338,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_338," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_338,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_338,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_338,Destination Address" group.long 0x6A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_338,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_338,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_338,Source Address" tree.end tree "DMA_Channel_339" group.long 0x6A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_339,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_339," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_339,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_339,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_339,Destination Address" group.long 0x6A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_339,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_339,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_339,Source Address" tree.end tree "DMA_Channel_34" group.long 0x4448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_34," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x445C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x188++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x444C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_34,Destination Address" group.long 0x4454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_34,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_34,Source Address" tree.end tree "DMA_Channel_340" group.long 0x6A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_340,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_340," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_340,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_340,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_340,Destination Address" group.long 0x6A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_340,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_340,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_340,Source Address" tree.end tree "DMA_Channel_341" group.long 0x6AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_341,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_341," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_341,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_341,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_341,Destination Address" group.long 0x6AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_341,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_341,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_341,Source Address" tree.end tree "DMA_Channel_342" group.long 0x6AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_342,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_342," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_342,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_342,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_342,Destination Address" group.long 0x6AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_342,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_342,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_342,Source Address" tree.end tree "DMA_Channel_343" group.long 0x6AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_343,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_343," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_343,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_343,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_343,Destination Address" group.long 0x6AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_343,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_343,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_343,Source Address" tree.end tree "DMA_Channel_344" group.long 0x6B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_344,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_344," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_344,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_344,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_344,Destination Address" group.long 0x6B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_344,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_344,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_344,Source Address" tree.end tree "DMA_Channel_345" group.long 0x6B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_345,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_345," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_345,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_345,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_345,Destination Address" group.long 0x6B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_345,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_345,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_345,Source Address" tree.end tree "DMA_Channel_346" group.long 0x6B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_346,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_346," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_346,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_346,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_346,Destination Address" group.long 0x6B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_346,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_346,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_346,Source Address" tree.end tree "DMA_Channel_347" group.long 0x6B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_347,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_347," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_347,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_347,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_347,Destination Address" group.long 0x6B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_347,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_347,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_347,Source Address" tree.end tree "DMA_Channel_348" group.long 0x6B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_348,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_348," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_348,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_348,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_348,Destination Address" group.long 0x6B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_348,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_348,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_348,Source Address" tree.end tree "DMA_Channel_349" group.long 0x6BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_349,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_349," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_349,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_349,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_349,Destination Address" group.long 0x6BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_349,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_349,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_349,Source Address" tree.end tree "DMA_Channel_35" group.long 0x4468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_35," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x447C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x18C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x446C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_35,Destination Address" group.long 0x4474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_35,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_35,Source Address" tree.end tree "DMA_Channel_350" group.long 0x6BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_350,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_350," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_350,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_350,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_350,Destination Address" group.long 0x6BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_350,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_350,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_350,Source Address" tree.end tree "DMA_Channel_351" group.long 0x6BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_351,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_351," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_351,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_351,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_351,Destination Address" group.long 0x6BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_351,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_351,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_351,Source Address" tree.end tree "DMA_Channel_352" group.long 0x6C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_352,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_352," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_352,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_352,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_352,Destination Address" group.long 0x6C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_352,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_352,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_352,Source Address" tree.end tree "DMA_Channel_353" group.long 0x6C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_353,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_353," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_353,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_353,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_353,Destination Address" group.long 0x6C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_353,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_353,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_353,Source Address" tree.end tree "DMA_Channel_354" group.long 0x6C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_354,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_354," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_354,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_354,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_354,Destination Address" group.long 0x6C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_354,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_354,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_354,Source Address" tree.end tree "DMA_Channel_355" group.long 0x6C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_355,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_355," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_355,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_355,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_355,Destination Address" group.long 0x6C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_355,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_355,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_355,Source Address" tree.end tree "DMA_Channel_356" group.long 0x6C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_356,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_356," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_356,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_356,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_356,Destination Address" group.long 0x6C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_356,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_356,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_356,Source Address" tree.end tree "DMA_Channel_357" group.long 0x6CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_357,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_357," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_357,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_357,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_357,Destination Address" group.long 0x6CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_357,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_357,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_357,Source Address" tree.end tree "DMA_Channel_358" group.long 0x6CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_358,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_358," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_358,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_358,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_358,Destination Address" group.long 0x6CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_358,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_358,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_358,Source Address" tree.end tree "DMA_Channel_359" group.long 0x6CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_359,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_359," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_359,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_359,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_359,Destination Address" group.long 0x6CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_359,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_359,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_359,Source Address" tree.end tree "DMA_Channel_36" group.long 0x4488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_36," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x449C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x190++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x448C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_36,Destination Address" group.long 0x4494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_36,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_36,Source Address" tree.end tree "DMA_Channel_360" group.long 0x6D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_360,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_360," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_360,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_360,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_360,Destination Address" group.long 0x6D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_360,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_360,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_360,Source Address" tree.end tree "DMA_Channel_361" group.long 0x6D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_361,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_361," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_361,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_361,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_361,Destination Address" group.long 0x6D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_361,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_361,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_361,Source Address" tree.end tree "DMA_Channel_362" group.long 0x6D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_362,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_362," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_362,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_362,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_362,Destination Address" group.long 0x6D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_362,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_362,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_362,Source Address" tree.end tree "DMA_Channel_363" group.long 0x6D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_363,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_363," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_363,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_363,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_363,Destination Address" group.long 0x6D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_363,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_363,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_363,Source Address" tree.end tree "DMA_Channel_364" group.long 0x6D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_364,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_364," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_364,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_364,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_364,Destination Address" group.long 0x6D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_364,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_364,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_364,Source Address" tree.end tree "DMA_Channel_365" group.long 0x6DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_365,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_365," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_365,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_365,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_365,Destination Address" group.long 0x6DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_365,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_365,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_365,Source Address" tree.end tree "DMA_Channel_366" group.long 0x6DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_366,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_366," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_366,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_366,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_366,Destination Address" group.long 0x6DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_366,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_366,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_366,Source Address" tree.end tree "DMA_Channel_367" group.long 0x6DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_367,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_367," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_367,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_367,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_367,Destination Address" group.long 0x6DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_367,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_367,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_367,Source Address" tree.end tree "DMA_Channel_368" group.long 0x6E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_368,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_368," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_368,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_368,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_368,Destination Address" group.long 0x6E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_368,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_368,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_368,Source Address" tree.end tree "DMA_Channel_369" group.long 0x6E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_369,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_369," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_369,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_369,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_369,Destination Address" group.long 0x6E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_369,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_369,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_369,Source Address" tree.end tree "DMA_Channel_37" group.long 0x44A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_37," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x194++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_37,Destination Address" group.long 0x44B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_37,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_37,Source Address" tree.end tree "DMA_Channel_370" group.long 0x6E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_370,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_370," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_370,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_370,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_370,Destination Address" group.long 0x6E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_370,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_370,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_370,Source Address" tree.end tree "DMA_Channel_371" group.long 0x6E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_371,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_371," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_371,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_371,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_371,Destination Address" group.long 0x6E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_371,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_371,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_371,Source Address" tree.end tree "DMA_Channel_372" group.long 0x6E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_372,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_372," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_372,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_372,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_372,Destination Address" group.long 0x6E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_372,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_372,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_372,Source Address" tree.end tree "DMA_Channel_373" group.long 0x6EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_373,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_373," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_373,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_373,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_373,Destination Address" group.long 0x6EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_373,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_373,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_373,Source Address" tree.end tree "DMA_Channel_374" group.long 0x6EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_374,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_374," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_374,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_374,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_374,Destination Address" group.long 0x6ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_374,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_374,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_374,Source Address" tree.end tree "DMA_Channel_375" group.long 0x6EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_375,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_375," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_375,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_375,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_375,Destination Address" group.long 0x6EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_375,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_375,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_375,Source Address" tree.end tree "DMA_Channel_376" group.long 0x6F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_376,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_376," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_376,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_376,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_376,Destination Address" group.long 0x6F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_376,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_376,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_376,Source Address" tree.end tree "DMA_Channel_377" group.long 0x6F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_377,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_377," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_377,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_377,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_377,Destination Address" group.long 0x6F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_377,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_377,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_377,Source Address" tree.end tree "DMA_Channel_378" group.long 0x6F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_378,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_378," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_378,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_378,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_378,Destination Address" group.long 0x6F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_378,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_378,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_378,Source Address" tree.end tree "DMA_Channel_379" group.long 0x6F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_379,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_379," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_379,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_379,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_379,Destination Address" group.long 0x6F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_379,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_379,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_379,Source Address" tree.end tree "DMA_Channel_38" group.long 0x44C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_38," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x198++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_38,Destination Address" group.long 0x44D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_38,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_38,Source Address" tree.end tree "DMA_Channel_380" group.long 0x6F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_380,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_380," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_380,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_380,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_380,Destination Address" group.long 0x6F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_380,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_380,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_380,Source Address" tree.end tree "DMA_Channel_381" group.long 0x6FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_381,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_381," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_381,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_381,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_381,Destination Address" group.long 0x6FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_381,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_381,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_381,Source Address" tree.end tree "DMA_Channel_382" group.long 0x6FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_382,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_382," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_382,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_382,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_382,Destination Address" group.long 0x6FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_382,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_382,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_382,Source Address" tree.end tree "DMA_Channel_383" group.long 0x6FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_383,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x6FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_383," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x6FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_383,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x6FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_383,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x6FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_383,Destination Address" group.long 0x6FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_383,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x6FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_383,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_383,Source Address" tree.end tree "DMA_Channel_384" group.long 0x7008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_384,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_384," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x701C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_384,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_384,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x700C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_384,Destination Address" group.long 0x7014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_384,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7000++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_384,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_384,Source Address" tree.end tree "DMA_Channel_385" group.long 0x7028++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_385,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7030++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_385," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x703C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_385,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7038++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_385,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x702C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_385,Destination Address" group.long 0x7034++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_385,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7020++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_385,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_385,Source Address" tree.end tree "DMA_Channel_386" group.long 0x7048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_386,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_386," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x705C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_386,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_386,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x704C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_386,Destination Address" group.long 0x7054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_386,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7040++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_386,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_386,Source Address" tree.end tree "DMA_Channel_387" group.long 0x7068++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_387,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7070++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_387," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x707C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_387,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7078++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_387,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x706C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_387,Destination Address" group.long 0x7074++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_387,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7060++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_387,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_387,Source Address" tree.end tree "DMA_Channel_388" group.long 0x7088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_388,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_388," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x709C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_388,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_388,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x708C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_388,Destination Address" group.long 0x7094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_388,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7080++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_388,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_388,Source Address" tree.end tree "DMA_Channel_389" group.long 0x70A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_389,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x70B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_389," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x70BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_389,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x70B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_389,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x70AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_389,Destination Address" group.long 0x70B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_389,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x70A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_389,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_389,Source Address" tree.end tree "DMA_Channel_39" group.long 0x44E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x44F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_39," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x44FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x44F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x19C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x44EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_39,Destination Address" group.long 0x44F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x44E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_39,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_39,Source Address" tree.end tree "DMA_Channel_390" group.long 0x70C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_390,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x70D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_390," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x70DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_390,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x70D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_390,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x70CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_390,Destination Address" group.long 0x70D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_390,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x70C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_390,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_390,Source Address" tree.end tree "DMA_Channel_391" group.long 0x70E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_391,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x70F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_391," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x70FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_391,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x70F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_391,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x70EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_391,Destination Address" group.long 0x70F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_391,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x70E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_391,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_391,Source Address" tree.end tree "DMA_Channel_392" group.long 0x7108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_392,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_392," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x711C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_392,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_392,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x710C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_392,Destination Address" group.long 0x7114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_392,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7100++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_392,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_392,Source Address" tree.end tree "DMA_Channel_393" group.long 0x7128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_393,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_393," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x713C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_393,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_393,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x712C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_393,Destination Address" group.long 0x7134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_393,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7120++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_393,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_393,Source Address" tree.end tree "DMA_Channel_394" group.long 0x7148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_394,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_394," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x715C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_394,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_394,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x714C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_394,Destination Address" group.long 0x7154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_394,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_394,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_394,Source Address" tree.end tree "DMA_Channel_395" group.long 0x7168++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_395,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7170++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_395," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x717C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_395,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7178++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_395,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x716C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_395,Destination Address" group.long 0x7174++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_395,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7160++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_395,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_395,Source Address" tree.end tree "DMA_Channel_396" group.long 0x7188++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_396,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7190++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_396," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x719C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_396,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7198++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_396,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x718C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_396,Destination Address" group.long 0x7194++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_396,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7180++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_396,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_396,Source Address" tree.end tree "DMA_Channel_397" group.long 0x71A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_397,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x71B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_397," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x71BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_397,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x71B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_397,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x71AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_397,Destination Address" group.long 0x71B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_397,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x71A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_397,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_397,Source Address" tree.end tree "DMA_Channel_398" group.long 0x71C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_398,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x71D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_398," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x71DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_398,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x71D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_398,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x71CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_398,Destination Address" group.long 0x71D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_398,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x71C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_398,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_398,Source Address" tree.end tree "DMA_Channel_399" group.long 0x71E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_399,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x71F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_399," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x71FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_399,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x71F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_399,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x71EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_399,Destination Address" group.long 0x71F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_399,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x71E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_399,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_399,Source Address" tree.end tree "DMA_Channel_4" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x410++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x210++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end tree "DMA_Channel_40" group.long 0x4508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_40," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x451C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x450C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_40,Destination Address" group.long 0x4514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_40,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_40,Source Address" tree.end tree "DMA_Channel_400" group.long 0x7208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_400,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_400," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x721C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_400,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_400,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x720C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_400,Destination Address" group.long 0x7214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_400,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_400,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_400,Source Address" tree.end tree "DMA_Channel_401" group.long 0x7228++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_401,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7230++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_401," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x723C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_401,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7238++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_401,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x722C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_401,Destination Address" group.long 0x7234++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_401,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7220++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_401,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_401,Source Address" tree.end tree "DMA_Channel_402" group.long 0x7248++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_402,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7250++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_402," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x725C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_402,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7258++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_402,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x724C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_402,Destination Address" group.long 0x7254++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_402,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7240++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_402,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_402,Source Address" tree.end tree "DMA_Channel_403" group.long 0x7268++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_403,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7270++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_403," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x727C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_403,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7278++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_403,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x726C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_403,Destination Address" group.long 0x7274++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_403,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7260++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_403,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_403,Source Address" tree.end tree "DMA_Channel_404" group.long 0x7288++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_404,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7290++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_404," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x729C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_404,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7298++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_404,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x728C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_404,Destination Address" group.long 0x7294++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_404,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7280++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_404,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_404,Source Address" tree.end tree "DMA_Channel_405" group.long 0x72A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_405,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x72B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_405," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x72BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_405,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x72B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_405,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x72AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_405,Destination Address" group.long 0x72B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_405,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x72A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_405,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_405,Source Address" tree.end tree "DMA_Channel_406" group.long 0x72C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_406,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x72D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_406," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x72DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_406,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x72D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_406,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x72CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_406,Destination Address" group.long 0x72D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_406,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x72C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_406,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_406,Source Address" tree.end tree "DMA_Channel_407" group.long 0x72E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_407,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x72F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_407," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x72FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_407,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x72F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_407,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x72EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_407,Destination Address" group.long 0x72F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_407,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x72E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_407,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_407,Source Address" tree.end tree "DMA_Channel_408" group.long 0x7308++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_408,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7310++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_408," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x731C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_408,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7318++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_408,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x730C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_408,Destination Address" group.long 0x7314++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_408,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7300++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_408,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_408,Source Address" tree.end tree "DMA_Channel_409" group.long 0x7328++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_409,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7330++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_409," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x733C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_409,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7338++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_409,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x732C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_409,Destination Address" group.long 0x7334++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_409,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7320++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_409,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_409,Source Address" tree.end tree "DMA_Channel_41" group.long 0x4528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_41," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x453C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x452C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_41,Destination Address" group.long 0x4534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_41,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_41,Source Address" tree.end tree "DMA_Channel_410" group.long 0x7348++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_410,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7350++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_410," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x735C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_410,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7358++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_410,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x734C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_410,Destination Address" group.long 0x7354++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_410,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7340++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_410,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_410,Source Address" tree.end tree "DMA_Channel_411" group.long 0x7368++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_411,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7370++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_411," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x737C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_411,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7378++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_411,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x736C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_411,Destination Address" group.long 0x7374++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_411,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7360++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_411,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_411,Source Address" tree.end tree "DMA_Channel_412" group.long 0x7388++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_412,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7390++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_412," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x739C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_412,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7398++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_412,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x738C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_412,Destination Address" group.long 0x7394++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_412,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7380++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_412,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_412,Source Address" tree.end tree "DMA_Channel_413" group.long 0x73A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_413,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x73B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_413," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x73BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_413,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x73B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_413,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x73AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_413,Destination Address" group.long 0x73B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_413,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x73A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_413,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_413,Source Address" tree.end tree "DMA_Channel_414" group.long 0x73C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_414,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x73D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_414," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x73DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_414,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x73D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_414,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x73CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_414,Destination Address" group.long 0x73D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_414,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x73C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_414,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_414,Source Address" tree.end tree "DMA_Channel_415" group.long 0x73E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_415,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x73F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_415," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x73FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_415,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x73F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_415,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x73EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_415,Destination Address" group.long 0x73F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_415,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x73E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_415,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_415,Source Address" tree.end tree "DMA_Channel_416" group.long 0x7408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_416,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_416," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x741C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_416,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_416,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x740C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_416,Destination Address" group.long 0x7414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_416,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_416,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_416,Source Address" tree.end tree "DMA_Channel_417" group.long 0x7428++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_417,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7430++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_417," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x743C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_417,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7438++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_417,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x742C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_417,Destination Address" group.long 0x7434++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_417,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7420++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_417,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_417,Source Address" tree.end tree "DMA_Channel_418" group.long 0x7448++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_418,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7450++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_418," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x745C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_418,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7458++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_418,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x744C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_418,Destination Address" group.long 0x7454++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_418,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7440++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_418,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_418,Source Address" tree.end tree "DMA_Channel_419" group.long 0x7468++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_419,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7470++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_419," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x747C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_419,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7478++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_419,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x746C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_419,Destination Address" group.long 0x7474++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_419,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7460++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_419,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_419,Source Address" tree.end tree "DMA_Channel_42" group.long 0x4548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_42," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x455C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1A8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x454C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_42,Destination Address" group.long 0x4554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_42,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_42,Source Address" tree.end tree "DMA_Channel_420" group.long 0x7488++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_420,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7490++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_420," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x749C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_420,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7498++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_420,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x748C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_420,Destination Address" group.long 0x7494++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_420,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7480++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_420,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_420,Source Address" tree.end tree "DMA_Channel_421" group.long 0x74A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_421,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x74B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_421," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x74BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_421,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x74B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_421,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x74AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_421,Destination Address" group.long 0x74B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_421,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x74A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_421,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_421,Source Address" tree.end tree "DMA_Channel_422" group.long 0x74C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_422,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x74D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_422," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x74DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_422,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x74D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_422,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x74CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_422,Destination Address" group.long 0x74D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_422,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x74C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_422,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_422,Source Address" tree.end tree "DMA_Channel_423" group.long 0x74E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_423,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x74F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_423," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x74FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_423,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x74F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_423,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x74EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_423,Destination Address" group.long 0x74F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_423,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x74E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_423,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_423,Source Address" tree.end tree "DMA_Channel_424" group.long 0x7508++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_424,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7510++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_424," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x751C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_424,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7518++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_424,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x750C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_424,Destination Address" group.long 0x7514++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_424,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7500++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_424,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_424,Source Address" tree.end tree "DMA_Channel_425" group.long 0x7528++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_425,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7530++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_425," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x753C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_425,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7538++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_425,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x752C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_425,Destination Address" group.long 0x7534++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_425,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7520++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_425,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_425,Source Address" tree.end tree "DMA_Channel_426" group.long 0x7548++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_426,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7550++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_426," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x755C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_426,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7558++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_426,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x754C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_426,Destination Address" group.long 0x7554++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_426,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7540++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_426,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_426,Source Address" tree.end tree "DMA_Channel_427" group.long 0x7568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_427,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_427," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x757C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_427,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_427,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x756C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_427,Destination Address" group.long 0x7574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_427,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_427,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_427,Source Address" tree.end tree "DMA_Channel_428" group.long 0x7588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_428,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_428," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x759C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_428,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_428,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x758C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_428,Destination Address" group.long 0x7594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_428,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_428,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_428,Source Address" tree.end tree "DMA_Channel_429" group.long 0x75A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_429,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x75B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_429," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x75BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_429,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x75B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_429,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x75AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_429,Destination Address" group.long 0x75B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_429,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x75A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_429,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_429,Source Address" tree.end tree "DMA_Channel_43" group.long 0x4568++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4570++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_43," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x457C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4578++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1AC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x456C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_43,Destination Address" group.long 0x4574++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4560++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_43,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_43,Source Address" tree.end tree "DMA_Channel_430" group.long 0x75C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_430,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x75D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_430," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x75DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_430,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x75D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_430,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x75CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_430,Destination Address" group.long 0x75D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_430,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x75C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_430,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_430,Source Address" tree.end tree "DMA_Channel_431" group.long 0x75E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_431,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x75F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_431," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x75FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_431,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x75F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_431,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x75EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_431,Destination Address" group.long 0x75F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_431,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x75E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_431,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_431,Source Address" tree.end tree "DMA_Channel_432" group.long 0x7608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_432,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_432," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x761C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_432,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_432,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x760C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_432,Destination Address" group.long 0x7614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_432,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_432,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_432,Source Address" tree.end tree "DMA_Channel_433" group.long 0x7628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_433,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_433," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x763C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_433,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_433,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x762C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_433,Destination Address" group.long 0x7634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_433,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_433,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_433,Source Address" tree.end tree "DMA_Channel_434" group.long 0x7648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_434,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_434," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x765C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_434,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_434,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x764C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_434,Destination Address" group.long 0x7654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_434,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_434,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_434,Source Address" tree.end tree "DMA_Channel_435" group.long 0x7668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_435,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_435," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x767C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_435,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_435,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x766C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_435,Destination Address" group.long 0x7674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_435,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_435,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_435,Source Address" tree.end tree "DMA_Channel_436" group.long 0x7688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_436,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_436," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x769C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_436,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_436,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x768C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_436,Destination Address" group.long 0x7694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_436,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_436,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_436,Source Address" tree.end tree "DMA_Channel_437" group.long 0x76A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_437,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x76B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_437," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x76BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_437,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x76B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_437,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x76AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_437,Destination Address" group.long 0x76B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_437,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x76A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_437,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_437,Source Address" tree.end tree "DMA_Channel_438" group.long 0x76C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_438,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x76D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_438," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x76DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_438,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x76D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_438,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x76CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_438,Destination Address" group.long 0x76D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_438,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x76C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_438,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_438,Source Address" tree.end tree "DMA_Channel_439" group.long 0x76E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_439,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x76F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_439," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x76FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_439,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x76F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_439,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x76EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_439,Destination Address" group.long 0x76F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_439,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x76E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_439,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_439,Source Address" tree.end tree "DMA_Channel_44" group.long 0x4588++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4590++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_44," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x459C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4598++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x458C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_44,Destination Address" group.long 0x4594++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4580++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_44,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_44,Source Address" tree.end tree "DMA_Channel_440" group.long 0x7708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_440,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_440," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x771C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_440,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_440,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x770C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_440,Destination Address" group.long 0x7714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_440,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_440,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_440,Source Address" tree.end tree "DMA_Channel_441" group.long 0x7728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_441,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_441," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x773C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_441,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_441,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x772C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_441,Destination Address" group.long 0x7734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_441,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_441,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_441,Source Address" tree.end tree "DMA_Channel_442" group.long 0x7748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_442,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_442," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x775C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_442,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_442,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x774C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_442,Destination Address" group.long 0x7754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_442,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_442,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_442,Source Address" tree.end tree "DMA_Channel_443" group.long 0x7768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_443,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_443," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x777C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_443,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_443,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x776C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_443,Destination Address" group.long 0x7774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_443,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_443,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_443,Source Address" tree.end tree "DMA_Channel_444" group.long 0x7788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_444,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_444," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x779C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_444,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_444,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x778C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_444,Destination Address" group.long 0x7794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_444,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_444,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_444,Source Address" tree.end tree "DMA_Channel_445" group.long 0x77A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_445,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x77B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_445," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x77BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_445,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x77B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_445,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x77AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_445,Destination Address" group.long 0x77B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_445,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x77A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_445,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_445,Source Address" tree.end tree "DMA_Channel_446" group.long 0x77C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_446,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x77D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_446," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x77DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_446,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x77D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_446,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x77CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_446,Destination Address" group.long 0x77D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_446,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x77C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_446,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_446,Source Address" tree.end tree "DMA_Channel_447" group.long 0x77E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_447,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x77F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_447," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x77FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_447,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x77F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_447,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x77EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_447,Destination Address" group.long 0x77F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_447,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x77E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_447,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_447,Source Address" tree.end tree "DMA_Channel_448" group.long 0x7808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_448,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_448," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x781C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_448,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_448,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x780C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_448,Destination Address" group.long 0x7814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_448,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_448,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_448,Source Address" tree.end tree "DMA_Channel_449" group.long 0x7828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_449,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_449," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x783C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_449,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_449,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x782C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_449,Destination Address" group.long 0x7834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_449,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_449,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_449,Source Address" tree.end tree "DMA_Channel_45" group.long 0x45A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_45," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_45,Destination Address" group.long 0x45B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_45,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_45,Source Address" tree.end tree "DMA_Channel_450" group.long 0x7848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_450,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_450," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x785C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_450,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_450,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x784C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_450,Destination Address" group.long 0x7854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_450,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_450,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_450,Source Address" tree.end tree "DMA_Channel_451" group.long 0x7868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_451,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_451," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x787C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_451,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_451,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x786C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_451,Destination Address" group.long 0x7874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_451,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_451,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_451,Source Address" tree.end tree "DMA_Channel_452" group.long 0x7888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_452,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_452," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x789C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_452,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_452,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x788C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_452,Destination Address" group.long 0x7894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_452,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_452,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_452,Source Address" tree.end tree "DMA_Channel_453" group.long 0x78A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_453,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x78B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_453," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x78BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_453,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x78B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_453,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x78AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_453,Destination Address" group.long 0x78B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_453,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x78A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_453,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_453,Source Address" tree.end tree "DMA_Channel_454" group.long 0x78C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_454,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x78D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_454," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x78DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_454,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x78D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_454,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x78CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_454,Destination Address" group.long 0x78D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_454,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x78C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_454,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_454,Source Address" tree.end tree "DMA_Channel_455" group.long 0x78E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_455,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x78F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_455," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x78FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_455,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x78F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_455,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x78EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_455,Destination Address" group.long 0x78F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_455,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x78E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_455,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_455,Source Address" tree.end tree "DMA_Channel_456" group.long 0x7908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_456,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_456," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x791C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_456,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_456,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x790C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_456,Destination Address" group.long 0x7914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_456,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_456,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_456,Source Address" tree.end tree "DMA_Channel_457" group.long 0x7928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_457,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_457," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x793C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_457,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_457,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x792C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_457,Destination Address" group.long 0x7934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_457,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_457,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_457,Source Address" tree.end tree "DMA_Channel_458" group.long 0x7948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_458,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_458," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x795C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_458,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_458,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x794C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_458,Destination Address" group.long 0x7954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_458,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_458,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_458,Source Address" tree.end tree "DMA_Channel_459" group.long 0x7968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_459,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_459," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x797C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_459,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_459,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x796C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_459,Destination Address" group.long 0x7974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_459,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_459,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_459,Source Address" tree.end tree "DMA_Channel_46" group.long 0x45C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_46," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1B8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_46,Destination Address" group.long 0x45D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_46,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_46,Source Address" tree.end tree "DMA_Channel_460" group.long 0x7988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_460,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_460," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x799C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_460,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_460,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x798C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_460,Destination Address" group.long 0x7994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_460,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_460,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_460,Source Address" tree.end tree "DMA_Channel_461" group.long 0x79A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_461,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x79B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_461," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x79BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_461,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x79B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_461,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x79AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_461,Destination Address" group.long 0x79B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_461,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x79A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_461,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_461,Source Address" tree.end tree "DMA_Channel_462" group.long 0x79C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_462,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x79D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_462," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x79DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_462,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x79D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_462,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x79CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_462,Destination Address" group.long 0x79D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_462,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x79C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_462,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_462,Source Address" tree.end tree "DMA_Channel_463" group.long 0x79E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_463,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x79F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_463," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x79FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_463,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x79F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_463,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x79EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_463,Destination Address" group.long 0x79F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_463,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x79E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_463,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_463,Source Address" tree.end tree "DMA_Channel_464" group.long 0x7A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_464,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_464," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_464,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_464,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_464,Destination Address" group.long 0x7A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_464,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_464,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_464,Source Address" tree.end tree "DMA_Channel_465" group.long 0x7A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_465,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_465," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_465,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_465,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_465,Destination Address" group.long 0x7A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_465,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_465,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_465,Source Address" tree.end tree "DMA_Channel_466" group.long 0x7A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_466,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_466," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_466,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_466,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_466,Destination Address" group.long 0x7A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_466,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_466,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_466,Source Address" tree.end tree "DMA_Channel_467" group.long 0x7A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_467,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_467," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_467,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_467,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_467,Destination Address" group.long 0x7A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_467,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_467,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_467,Source Address" tree.end tree "DMA_Channel_468" group.long 0x7A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_468,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_468," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_468,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_468,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_468,Destination Address" group.long 0x7A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_468,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_468,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_468,Source Address" tree.end tree "DMA_Channel_469" group.long 0x7AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_469,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_469," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_469,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_469,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_469,Destination Address" group.long 0x7AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_469,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_469,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_469,Source Address" tree.end tree "DMA_Channel_47" group.long 0x45E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x45F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_47," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x45FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x45F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1BC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x45EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_47,Destination Address" group.long 0x45F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x45E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_47,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_47,Source Address" tree.end tree "DMA_Channel_470" group.long 0x7AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_470,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_470," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_470,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_470,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_470,Destination Address" group.long 0x7AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_470,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_470,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_470,Source Address" tree.end tree "DMA_Channel_471" group.long 0x7AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_471,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_471," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_471,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_471,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_471,Destination Address" group.long 0x7AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_471,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_471,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_471,Source Address" tree.end tree "DMA_Channel_472" group.long 0x7B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_472,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_472," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_472,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_472,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_472,Destination Address" group.long 0x7B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_472,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_472,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_472,Source Address" tree.end tree "DMA_Channel_473" group.long 0x7B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_473,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_473," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_473,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_473,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_473,Destination Address" group.long 0x7B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_473,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_473,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_473,Source Address" tree.end tree "DMA_Channel_474" group.long 0x7B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_474,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_474," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_474,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_474,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_474,Destination Address" group.long 0x7B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_474,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_474,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_474,Source Address" tree.end tree "DMA_Channel_475" group.long 0x7B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_475,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_475," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_475,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_475,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_475,Destination Address" group.long 0x7B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_475,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_475,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_475,Source Address" tree.end tree "DMA_Channel_476" group.long 0x7B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_476,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_476," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_476,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_476,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_476,Destination Address" group.long 0x7B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_476,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_476,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_476,Source Address" tree.end tree "DMA_Channel_477" group.long 0x7BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_477,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_477," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_477,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_477,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_477,Destination Address" group.long 0x7BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_477,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_477,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_477,Source Address" tree.end tree "DMA_Channel_478" group.long 0x7BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_478,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_478," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_478,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_478,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_478,Destination Address" group.long 0x7BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_478,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_478,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_478,Source Address" tree.end tree "DMA_Channel_479" group.long 0x7BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_479,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_479," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_479,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_479,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_479,Destination Address" group.long 0x7BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_479,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_479,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_479,Source Address" tree.end tree "DMA_Channel_48" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end tree "DMA_Channel_480" group.long 0x7C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_480,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_480," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_480,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_480,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_480,Destination Address" group.long 0x7C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_480,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_480,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_480,Source Address" tree.end tree "DMA_Channel_481" group.long 0x7C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_481,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_481," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_481,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_481,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_481,Destination Address" group.long 0x7C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_481,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_481,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_481,Source Address" tree.end tree "DMA_Channel_482" group.long 0x7C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_482,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_482," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_482,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_482,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_482,Destination Address" group.long 0x7C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_482,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_482,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_482,Source Address" tree.end tree "DMA_Channel_483" group.long 0x7C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_483,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_483," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_483,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_483,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_483,Destination Address" group.long 0x7C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_483,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_483,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_483,Source Address" tree.end tree "DMA_Channel_484" group.long 0x7C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_484,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_484," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_484,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_484,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_484,Destination Address" group.long 0x7C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_484,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_484,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_484,Source Address" tree.end tree "DMA_Channel_485" group.long 0x7CA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_485,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7CB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_485," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7CBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_485,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7CB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_485,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7CAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_485,Destination Address" group.long 0x7CB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_485,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7CA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_485,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_485,Source Address" tree.end tree "DMA_Channel_486" group.long 0x7CC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_486,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7CD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_486," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7CDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_486,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7CD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_486,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7CCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_486,Destination Address" group.long 0x7CD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_486,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7CC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_486,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_486,Source Address" tree.end tree "DMA_Channel_487" group.long 0x7CE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_487,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7CF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_487," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7CFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_487,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7CF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_487,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7CEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_487,Destination Address" group.long 0x7CF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_487,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7CE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_487,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_487,Source Address" tree.end tree "DMA_Channel_488" group.long 0x7D08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_488,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7D10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_488," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7D1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_488,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7D18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_488,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7D0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_488,Destination Address" group.long 0x7D14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_488,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7D00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_488,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_488,Source Address" tree.end tree "DMA_Channel_489" group.long 0x7D28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_489,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7D30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_489," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7D3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_489,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7D38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_489,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7D2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_489,Destination Address" group.long 0x7D34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_489,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7D20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_489,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_489,Source Address" tree.end tree "DMA_Channel_49" group.long 0x4628++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4630++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_49," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x463C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4638++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x462C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_49,Destination Address" group.long 0x4634++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4620++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_49,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_49,Source Address" tree.end tree "DMA_Channel_490" group.long 0x7D48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_490,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7D50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_490," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7D5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_490,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7D58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_490,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7D4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_490,Destination Address" group.long 0x7D54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_490,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7D40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_490,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_490,Source Address" tree.end tree "DMA_Channel_491" group.long 0x7D68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_491,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7D70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_491," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7D7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_491,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7D78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_491,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7D6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_491,Destination Address" group.long 0x7D74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_491,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7D60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_491,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_491,Source Address" tree.end tree "DMA_Channel_492" group.long 0x7D88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_492,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7D90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_492," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7D9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_492,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7D98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_492,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7D8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_492,Destination Address" group.long 0x7D94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_492,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7D80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_492,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_492,Source Address" tree.end tree "DMA_Channel_493" group.long 0x7DA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_493,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7DB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_493," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7DBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_493,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7DB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_493,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7DAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_493,Destination Address" group.long 0x7DB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_493,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7DA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_493,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_493,Source Address" tree.end tree "DMA_Channel_494" group.long 0x7DC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_494,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7DD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_494," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7DDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_494,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7DD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_494,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7DCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_494,Destination Address" group.long 0x7DD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_494,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7DC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_494,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_494,Source Address" tree.end tree "DMA_Channel_495" group.long 0x7DE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_495,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7DF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_495," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7DFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_495,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7DF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_495,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7DEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_495,Destination Address" group.long 0x7DF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_495,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7DE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_495,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_495,Source Address" tree.end tree "DMA_Channel_496" group.long 0x7E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_496,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_496," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_496,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_496,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_496,Destination Address" group.long 0x7E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_496,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_496,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_496,Source Address" tree.end tree "DMA_Channel_497" group.long 0x7E28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_497,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7E30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_497," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7E3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_497,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7E38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_497,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7E2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_497,Destination Address" group.long 0x7E34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_497,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7E20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_497,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_497,Source Address" tree.end tree "DMA_Channel_498" group.long 0x7E48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_498,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7E50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_498," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7E5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_498,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7E58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_498,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7E4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_498,Destination Address" group.long 0x7E54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_498,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7E40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_498,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_498,Source Address" tree.end tree "DMA_Channel_499" group.long 0x7E68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_499,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7E70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_499," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7E7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_499,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7E78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_499,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7E6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_499,Destination Address" group.long 0x7E74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_499,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7E60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_499,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_499,Source Address" tree.end tree "DMA_Channel_5" group.long 0x40A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_5," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2A1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x114++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x254++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x36C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x368++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_5,Destination Address" group.long 0x2A0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2A54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2A60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2A78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2A6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2A68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x824++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40A0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_5,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x414++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x454++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x214++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2A88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x394++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2A94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2A44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2A40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2A3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2A38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40A4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_5,Source Address" tree.end tree "DMA_Channel_50" group.long 0x4648++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4650++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_50," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x465C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4658++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x464C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_50,Destination Address" group.long 0x4654++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4640++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_50,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_50,Source Address" tree.end tree "DMA_Channel_500" group.long 0x7E88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_500,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7E90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_500," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7E9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_500,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7E98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_500,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7E8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_500,Destination Address" group.long 0x7E94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_500,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7E80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_500,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_500,Source Address" tree.end tree "DMA_Channel_501" group.long 0x7EA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_501,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7EB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_501," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7EBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_501,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7EB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_501,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7EAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_501,Destination Address" group.long 0x7EB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_501,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7EA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_501,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_501,Source Address" tree.end tree "DMA_Channel_502" group.long 0x7EC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_502,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7ED0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_502," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7EDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_502,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7ED8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_502,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7ECC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_502,Destination Address" group.long 0x7ED4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_502,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7EC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_502,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_502,Source Address" tree.end tree "DMA_Channel_503" group.long 0x7EE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_503,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7EF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_503," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7EFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_503,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7EF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_503,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7EEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_503,Destination Address" group.long 0x7EF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_503,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7EE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_503,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_503,Source Address" tree.end tree "DMA_Channel_504" group.long 0x7F08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_504,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7F10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_504," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7F1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_504,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7F18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_504,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7F0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_504,Destination Address" group.long 0x7F14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_504,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7F00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_504,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_504,Source Address" tree.end tree "DMA_Channel_505" group.long 0x7F28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_505,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7F30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_505," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7F3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_505,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7F38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_505,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7F2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_505,Destination Address" group.long 0x7F34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_505,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7F20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_505,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_505,Source Address" tree.end tree "DMA_Channel_506" group.long 0x7F48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_506,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7F50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_506," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7F5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_506,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7F58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_506,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7F4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_506,Destination Address" group.long 0x7F54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_506,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7F40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_506,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_506,Source Address" tree.end tree "DMA_Channel_507" group.long 0x7F68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_507,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7F70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_507," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7F7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_507,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7F78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_507,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7F6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_507,Destination Address" group.long 0x7F74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_507,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7F60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_507,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_507,Source Address" tree.end tree "DMA_Channel_508" group.long 0x7F88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_508,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7F90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_508," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7F9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_508,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7F98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_508,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7F8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_508,Destination Address" group.long 0x7F94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_508,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7F80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_508,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_508,Source Address" tree.end tree "DMA_Channel_509" group.long 0x7FA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_509,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7FB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_509," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7FBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_509,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7FB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_509,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7FAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_509,Destination Address" group.long 0x7FB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_509,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7FA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_509,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_509,Source Address" tree.end tree "DMA_Channel_51" group.long 0x4668++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4670++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_51," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x467C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4678++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1CC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x466C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_51,Destination Address" group.long 0x4674++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4660++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_51,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_51,Source Address" tree.end tree "DMA_Channel_510" group.long 0x7FC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_510,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7FD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_510," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7FDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_510,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7FD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_510,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7FCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_510,Destination Address" group.long 0x7FD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_510,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7FC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_510,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_510,Source Address" tree.end tree "DMA_Channel_511" group.long 0x7FE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_511,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x7FF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_511," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x7FFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_511,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x7FF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_511,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x7FEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_511,Destination Address" group.long 0x7FF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_511,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x7FE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_511,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_511,Source Address" tree.end tree "DMA_Channel_512" group.long 0x8008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_512,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x8010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_512," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x801C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_512,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x8018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_512,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x800C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_512,Destination Address" group.long 0x8014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_512,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x8000++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_512,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_512,Source Address" tree.end tree "DMA_Channel_52" group.long 0x4688++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4690++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_52," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x469C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4698++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x468C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_52,Destination Address" group.long 0x4694++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4680++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_52,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_52,Source Address" tree.end tree "DMA_Channel_53" group.long 0x46A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_53," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_53,Destination Address" group.long 0x46B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_53,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_53,Source Address" tree.end tree "DMA_Channel_54" group.long 0x46C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_54," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1D8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_54,Destination Address" group.long 0x46D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_54,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_54,Source Address" tree.end tree "DMA_Channel_55" group.long 0x46E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x46F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_55," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x46FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x46F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1DC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x46EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_55,Destination Address" group.long 0x46F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x46E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_55,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_55,Source Address" tree.end tree "DMA_Channel_56" group.long 0x4708++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4710++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_56," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x471C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4718++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x470C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_56,Destination Address" group.long 0x4714++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4700++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_56,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_56,Source Address" tree.end tree "DMA_Channel_57" group.long 0x4728++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4730++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_57," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x473C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4738++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x472C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_57,Destination Address" group.long 0x4734++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4720++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_57,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_57,Source Address" tree.end tree "DMA_Channel_58" group.long 0x4748++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4750++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_58," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x475C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4758++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1E8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x474C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_58,Destination Address" group.long 0x4754++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4740++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_58,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_58,Source Address" tree.end tree "DMA_Channel_59" group.long 0x4768++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4770++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_59," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x477C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4778++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1EC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x476C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_59,Destination Address" group.long 0x4774++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4760++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_59,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_59,Source Address" tree.end tree "DMA_Channel_6" group.long 0x40C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_6," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2C1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x118++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x258++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x374++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x370++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_6,Destination Address" group.long 0x2C0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2C54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2C60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2C78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2C6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2C68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x828++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40C0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_6,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x418++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x458++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x218++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2C88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x398++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2C94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2C44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2C40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2C3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2C38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40C4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_6,Source Address" tree.end tree "DMA_Channel_60" group.long 0x4788++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4790++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_60," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x479C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4798++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x478C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_60,Destination Address" group.long 0x4794++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4780++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_60,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_60,Source Address" tree.end tree "DMA_Channel_61" group.long 0x47A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_61," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F4++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_61,Destination Address" group.long 0x47B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_61,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_61,Source Address" tree.end tree "DMA_Channel_62" group.long 0x47C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_62," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1F8++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_62,Destination Address" group.long 0x47D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_62,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_62,Source Address" tree.end tree "DMA_Channel_63" group.long 0x47E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x47F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_63," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x47FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x47F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1FC++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x47EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_63,Destination Address" group.long 0x47F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x47E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_63,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_63,Source Address" tree.end tree "DMA_Channel_64" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end tree "DMA_Channel_65" group.long 0x4828++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4830++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_65," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x483C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4838++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x482C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_65,Destination Address" group.long 0x4834++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4820++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_65,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_65,Source Address" tree.end tree "DMA_Channel_66" group.long 0x4848++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4850++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_66," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x485C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4858++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x484C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_66,Destination Address" group.long 0x4854++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4840++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_66,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_66,Source Address" tree.end tree "DMA_Channel_67" group.long 0x4868++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4870++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_67," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x487C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4878++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x486C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_67,Destination Address" group.long 0x4874++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4860++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_67,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_67,Source Address" tree.end tree "DMA_Channel_68" group.long 0x4888++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4890++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_68," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x489C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4898++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x488C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_68,Destination Address" group.long 0x4894++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4880++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_68,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_68,Source Address" tree.end tree "DMA_Channel_69" group.long 0x48A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_69," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_69,Destination Address" group.long 0x48B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_69,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_69,Source Address" tree.end tree "DMA_Channel_7" group.long 0x40E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x40F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_7," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x40FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x2E1C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E18++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x11C++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x25C++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x378++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x40EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_7,Destination Address" group.long 0x2E0C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E08++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E2C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E28++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E24++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E20++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E34++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E30++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E04++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E00++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E14++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E10++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E74++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E70++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E5C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E58++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2E54++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E50++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E64++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2E60++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2E78++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x2E6C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2E68++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x40F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x82C++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" newline bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "VBus requests with PrivID == '0' are not allowed..,VBus requests with PrivID == '0' are permitted.." bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" newline bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x40E0++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_7,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" newline bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x41C++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x45C++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x21C++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2E88++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E84++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E8C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E80++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x39C++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2E94++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E90++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2E44++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2E40++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2E3C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" newline bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" newline bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" newline bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" newline bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" newline bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2E38++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" newline bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" newline bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" newline bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" newline bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x40E4++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_7,Source Address" tree.end tree "DMA_Channel_70" group.long 0x48C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_70," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_70,Destination Address" group.long 0x48D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_70,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_70,Source Address" tree.end tree "DMA_Channel_71" group.long 0x48E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x48F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_71," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x48FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x48F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x48EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_71,Destination Address" group.long 0x48F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x48E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_71,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_71,Source Address" tree.end tree "DMA_Channel_72" group.long 0x4908++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4910++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_72," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x491C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4918++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x490C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_72,Destination Address" group.long 0x4914++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4900++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_72,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_72,Source Address" tree.end tree "DMA_Channel_73" group.long 0x4928++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4930++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_73," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x493C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4938++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x492C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_73,Destination Address" group.long 0x4934++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4920++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_73,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_73,Source Address" tree.end tree "DMA_Channel_74" group.long 0x4948++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4950++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_74," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x495C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4958++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x494C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_74,Destination Address" group.long 0x4954++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4940++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_74,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_74,Source Address" tree.end tree "DMA_Channel_75" group.long 0x4968++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4970++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_75," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x497C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4978++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x496C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_75,Destination Address" group.long 0x4974++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4960++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_75,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_75,Source Address" tree.end tree "DMA_Channel_76" group.long 0x4988++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4990++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_76," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x499C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4998++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x498C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_76,Destination Address" group.long 0x4994++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4980++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_76,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_76,Source Address" tree.end tree "DMA_Channel_77" group.long 0x49A8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49B0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_77," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49BC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49B8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49AC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_77,Destination Address" group.long 0x49B4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49A0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_77,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_77,Source Address" tree.end tree "DMA_Channel_78" group.long 0x49C8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49D0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_78," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49DC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49D8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49CC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_78,Destination Address" group.long 0x49D4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49C0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_78,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_78,Source Address" tree.end tree "DMA_Channel_79" group.long 0x49E8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x49F0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_79," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x49FC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x49F8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x49EC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_79,Destination Address" group.long 0x49F4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x49E0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_79,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_79,Source Address" tree.end tree "DMA_Channel_8" group.long 0x4108++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4110++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_8," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x411C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4118++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x120++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x410C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_8,Destination Address" group.long 0x4114++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4100++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_8,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x420++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x460++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4104++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_8,Source Address" tree.end tree "DMA_Channel_80" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end tree "DMA_Channel_81" group.long 0x4A28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_81," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_81,Destination Address" group.long 0x4A34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_81,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_81,Source Address" tree.end tree "DMA_Channel_82" group.long 0x4A48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_82," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_82,Destination Address" group.long 0x4A54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_82,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_82,Source Address" tree.end tree "DMA_Channel_83" group.long 0x4A68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_83," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_83,Destination Address" group.long 0x4A74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_83,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_83,Source Address" tree.end tree "DMA_Channel_84" group.long 0x4A88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_84," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_84,Destination Address" group.long 0x4A94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_84,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_84,Source Address" tree.end tree "DMA_Channel_85" group.long 0x4AA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_85," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ABC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_85,Destination Address" group.long 0x4AB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_85,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_85,Source Address" tree.end tree "DMA_Channel_86" group.long 0x4AC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_86," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4ADC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4ACC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_86,Destination Address" group.long 0x4AD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_86,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_86,Source Address" tree.end tree "DMA_Channel_87" group.long 0x4AE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4AF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_87," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4AFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4AF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4AEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_87,Destination Address" group.long 0x4AF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4AE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_87,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_87,Source Address" tree.end tree "DMA_Channel_88" group.long 0x4B08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_88," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_88,Destination Address" group.long 0x4B14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_88,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_88,Source Address" tree.end tree "DMA_Channel_89" group.long 0x4B28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_89," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_89,Destination Address" group.long 0x4B34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_89,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_89,Source Address" tree.end tree "DMA_Channel_9" group.long 0x4128++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4130++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_9," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x413C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4138++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x124++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x412C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_9,Destination Address" group.long 0x4134++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4120++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_9,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x424++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x464++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4124++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_9,Source Address" tree.end tree "DMA_Channel_90" group.long 0x4B48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_90," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_90,Destination Address" group.long 0x4B54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_90,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_90,Source Address" tree.end tree "DMA_Channel_91" group.long 0x4B68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_91," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_91,Destination Address" group.long 0x4B74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_91,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_91,Source Address" tree.end tree "DMA_Channel_92" group.long 0x4B88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4B90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_92," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4B9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4B98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4B8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_92,Destination Address" group.long 0x4B94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4B80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_92,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_92,Source Address" tree.end tree "DMA_Channel_93" group.long 0x4BA8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BB0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_93," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BBC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BB8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BAC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_93,Destination Address" group.long 0x4BB4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BA0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_93,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_93,Source Address" tree.end tree "DMA_Channel_94" group.long 0x4BC8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BD0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_94," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BDC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BD8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BCC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_94,Destination Address" group.long 0x4BD4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BC0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_94,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_94,Source Address" tree.end tree "DMA_Channel_95" group.long 0x4BE8++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4BF0++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_95," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4BFC++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4BF8++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4BEC++0x03 line.long 0x00 "EDMA_TPCC_DST_n_95,Destination Address" group.long 0x4BF4++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4BE0++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_95,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_95,Source Address" tree.end tree "DMA_Channel_96" group.long 0x4C08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_96," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_96,Destination Address" group.long 0x4C14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_96,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_96,Source Address" tree.end tree "DMA_Channel_97" group.long 0x4C28++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C30++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_97," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C3C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C38++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C2C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_97,Destination Address" group.long 0x4C34++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C20++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_97,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_97,Source Address" tree.end tree "DMA_Channel_98" group.long 0x4C48++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C50++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_98," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C5C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C58++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C4C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_98,Destination Address" group.long 0x4C54++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C40++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_98,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_98,Source Address" tree.end tree "DMA_Channel_99" group.long 0x4C68++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C70++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_99," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C7C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C78++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C6C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_99,Destination Address" group.long 0x4C74++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C60++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_99,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_99,Source Address" tree.end group.long 0x708++0x03 line.long 0x00 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x00 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" group.long 0x700++0x07 line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" newline bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" rgroup.long 0x04++0x03 line.long 0x00 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x00 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x00 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x00 20.--21. "NUMREGN,Number of MP and Shadow regions - NUMREG0" "NUMREGN_0,NUMREGN_1,NUMREGN_2,NUMREGN_3" newline bitfld.long 0x00 16.--18. "NUMTC,Number of Queues/Number of TCs - NUMTC7" "NUMTC_0,NUMTC_1,NUMTC_2,NUMTC_3,NUMTC_4,NUMTC_5,NUMTC_6,NUMTC_7" bitfld.long 0x00 12.--14. "NUMPAENTRY,Number of PaRAM entries - NUMPARAMENTRIES32" "NUMPAENTRY_0,NUMPAENTRY_1,NUMPAENTRY_2,NUMPAENTRY_3,NUMPAENTRY_4,NUMPAENTRY_5,?,?" bitfld.long 0x00 8.--10. "NUMINTCH,Number of Interrupt" "?,NUMINTCH_1,NUMINTCH_2,NUMINTCH_3,NUMINTCH_4,?,?,?" newline bitfld.long 0x00 4.--6. "NUMQDMACH,Number of QDMA" "NUMQDMACH_0,NUMQDMACH_1,NUMQDMACH_2,NUMQDMACH_3,NUMQDMACH_4,?,?,?" bitfld.long 0x00 0.--2. "NUMDMACH,Number of DMA" "NUMDMACH_0,NUMDMACH_1,NUMDMACH_2,NUMDMACH_3,NUMDMACH_4,NUMDMACH_5,?,?" rgroup.long 0x318++0x07 line.long 0x00 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x00 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x00 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x00 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" newline bitfld.long 0x00 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x00 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" bitfld.long 0x00 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" newline bitfld.long 0x00 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x00 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x00 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x04 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x04 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x04 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" newline bitfld.long 0x04 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" bitfld.long 0x04 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" newline bitfld.long 0x04 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x04 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x04 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" newline bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2" newline bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" newline bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.." bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" newline bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" rgroup.long 0x1018++0x07 line.long 0x00 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x1008++0x07 line.long 0x00 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1028++0x07 line.long 0x00 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1020++0x07 line.long 0x00 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1030++0x07 line.long 0x00 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x320++0x03 line.long 0x00 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x00 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x308++0x07 line.long 0x00 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed Clear #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed Clear #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed Clear #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed Clear #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed Clear #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" line.long 0x04 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x04 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed Clear #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed Clear #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed Clear #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed Clear #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed Clear #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed Clear #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" newline bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" newline bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" newline bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" newline bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" newline bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" newline bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" newline bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" rgroup.long 0x1000++0x07 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1010++0x07 line.long 0x00 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" group.long 0x1070++0x07 line.long 0x00 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1058++0x07 line.long 0x00 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1050++0x07 line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1060++0x07 line.long 0x00 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1068++0x07 line.long 0x00 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" newline bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" newline bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" newline bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" newline bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" newline bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" newline bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" newline bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" newline bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x800++0x03 line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" group.long 0x808++0x03 line.long 0x00 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" rgroup.long 0x804++0x03 line.long 0x00 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x00 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" newline bitfld.long 0x00 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x00 2. "URE,User Read Error" "URE_0,URE_1" bitfld.long 0x00 1. "UWE,User Write Error" "UWE_0,UWE_1" newline bitfld.long 0x00 0. "UXE,User Execute Error" "UXE_0,UXE_1" group.long 0x80C++0x03 line.long 0x00 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" newline bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" newline bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x00++0x03 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x1088++0x03 line.long 0x00 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1084++0x03 line.long 0x00 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x108C++0x03 line.long 0x00 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x314++0x03 line.long 0x00 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x00 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" rgroup.long 0x1080++0x03 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x1094++0x03 line.long 0x00 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x03 line.long 0x00 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x284++0x03 line.long 0x00 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x00 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" group.long 0x280++0x03 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1040++0x07 line.long 0x00 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x07 line.long 0x00 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" newline bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" newline bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" newline bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" newline bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" newline bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" bitfld.long 0x04 26. "E58,Event #58" "0,1" newline bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" newline bitfld.long 0x04 22. "E54,Event #54" "0,1" bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" newline bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" newline bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" bitfld.long 0x04 11. "E43,Event #43" "0,1" newline bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" newline bitfld.long 0x04 7. "E39,Event #39" "0,1" bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" newline bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" width 0x0B tree.end tree.end tree "Error_Location_Module" base ad:0x48078000 tree "Channel_0" rgroup.long 0x880++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x884++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x800++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x400++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_1" rgroup.long 0x980++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x9A8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_1,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_1,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_1,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_1,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_1,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x984++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_1,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_1,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_1,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_1,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_1,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_1,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_1,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_1,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_1,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x900++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_1,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x440++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_1,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_1,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_1,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_1,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_1,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_1,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_1,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_2" rgroup.long 0xA80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xAA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_2,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_2,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_2,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_2,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_2,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_2,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_2,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_2,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_2,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_2,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_2,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_2,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_2,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_2,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xA00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_2,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x480++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_2,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_2,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_2,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_2,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_2,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_2,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_2,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_3" rgroup.long 0xB80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xBA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_3,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_3,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_3,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_3,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_3,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_3,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_3,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_3,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_3,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_3,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_3,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_3,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_3,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_3,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xB00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_3,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C0++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_3,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_3,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_3,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_3,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_3,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_3,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_3,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_4" rgroup.long 0xC80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xCA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_4,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_4,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_4,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_4,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_4,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_4,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_4,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_4,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_4,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_4,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_4,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_4,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_4,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_4,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xC00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_4,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x500++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_4,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_4,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_4,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_4,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_4,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_4,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_4,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_5" rgroup.long 0xD80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xDA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_5,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_5,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_5,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_5,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_5,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_5,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_5,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_5,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_5,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_5,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_5,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_5,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_5,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_5,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xD00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_5,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x540++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_5,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_5,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_5,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_5,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_5,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_5,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_5,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_6" rgroup.long 0xE80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xEA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_6,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_6,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_6,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_6,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_6,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_6,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_6,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_6,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_6,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_6,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_6,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_6,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_6,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_6,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xE00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_6,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x580++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_6,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_6,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_6,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_6,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_6,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_6,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_6,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end tree "Channel_7" rgroup.long 0xF80++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xFA8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_7,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_7,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_7,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_7,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_7,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF84++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_7,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_7,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_7,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_7,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_7,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_7,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_7,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_7,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_7,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0xF00++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_7,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "ECC error-location process failed,All errors were successfully located" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C0++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_7,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_7,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_7,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_7,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_7,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_7,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_7,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "This syndrome polynomial must not be processed,This syndrome polynomial must be processed" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end group.long 0x1C++0x03 line.long 0x00 "ELM_IRQENABLE,Interrupt enable" bitfld.long 0x00 8. "PAGE_MASK,Page interrupt mask bit" "Disable interrupt,Enable interrupt" bitfld.long 0x00 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "LOCATION_MASK_7_0,LOCATION_MASK_7_1" bitfld.long 0x00 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "LOCATION_MASK_6_0,LOCATION_MASK_6_1" newline bitfld.long 0x00 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "LOCATION_MASK_5_0,LOCATION_MASK_5_1" bitfld.long 0x00 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "LOCATION_MASK_4_0,LOCATION_MASK_4_1" bitfld.long 0x00 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "LOCATION_MASK_3_0,LOCATION_MASK_3_1" newline bitfld.long 0x00 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "LOCATION_MASK_2_0,LOCATION_MASK_2_1" bitfld.long 0x00 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "LOCATION_MASK_1_0,LOCATION_MASK_1_1" bitfld.long 0x00 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "Disable interrupt,Enable interrupt" group.long 0x18++0x03 line.long 0x00 "ELM_IRQSTATUS,Interrupt status" bitfld.long 0x00 8. "PAGE_VALID,Error-location status for a full page based on the mask definition Read" "No effect,Clear interrupt" bitfld.long 0x00 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "No effect,Clear interrupt" bitfld.long 0x00 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "LOC_VALID_6_0,LOC_VALID_6_1" newline bitfld.long 0x00 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "LOC_VALID_5_0,LOC_VALID_5_1" bitfld.long 0x00 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "LOC_VALID_4_0,LOC_VALID_4_1" bitfld.long 0x00 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "LOC_VALID_3_0,LOC_VALID_3_1" newline bitfld.long 0x00 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "LOC_VALID_2_0,LOC_VALID_2_1" bitfld.long 0x00 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "LOC_VALID_1_0,LOC_VALID_1_1" bitfld.long 0x00 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "LOC_VALID_0_0,LOC_VALID_0_1" group.long 0x20++0x03 line.long 0x00 "ELM_LOCATION_CONFIG,ECC algorithm parameters" hexmask.long.word 0x00 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)" bitfld.long 0x00 0.--1. "ECC_BCH_LEVEL,Error correction level" "4 bits,8 bits,16 bits,Reserved" group.long 0x80++0x03 line.long 0x00 "ELM_PAGE_CTRL,Page definition" bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "SECTOR_7_0,SECTOR_7_1" bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "SECTOR_6_0,SECTOR_6_1" bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "SECTOR_5_0,SECTOR_5_1" newline bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "SECTOR_4_0,SECTOR_4_1" bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "SECTOR_3_0,SECTOR_3_1" bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "SECTOR_2_0,SECTOR_2_1" newline bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "SECTOR_1_0,SECTOR_1_1" bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "SECTOR_0_0,SECTOR_0_1" rgroup.long 0x00++0x03 line.long 0x00 "ELM_REVISION,This register contains the IP revision code" group.long 0x10++0x07 line.long 0x00 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP clock activity when module is in IDLE mode (during wake-up mode period) - OCP_OFF" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1" bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE req/ack control) - FORCE_IDLE" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Module software reset This bit is automatically reset by hardware (during reads it always returns 0)" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy (no module visible effect other than saving power) - OCP_FREE" "AUTOGATING_0,AUTOGATING_1" line.long 0x04 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective. the reset state is 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective the reset state is 0" "RESETDONE_0_r,RESETDONE_1_r" width 0x0B tree.end tree "General_Purpose_Interface" repeat 8. (list 7. 8. 2. 3. 4. 5. 6. 1. )(list ad:0x48051000 ad:0x48053000 ad:0x48055000 ad:0x48057000 ad:0x48059000 ad:0x4805B000 ad:0x4805D000 ad:0x4AE10000 ) tree "GPIO$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x20++0x2B line.long 0x00 "GPIO_EOI,Software end of interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to first line of interrupt)" line.long 0x08 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. showing all active events (enabled and not enabled). (corresponding to second line of interrupt)" line.long 0x0C "GPIO_IRQSTATUS_0,Per-event interrupt status vector. showing all active and enabled events (corresponding to first line of interrupt)" line.long 0x10 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector. showing all active and enabled events (corresponding to second line of interrupt)" line.long 0x14 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" line.long 0x18 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" line.long 0x1C "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" line.long 0x20 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" line.long 0x24 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" line.long 0x28 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. "RESETDONE,- InProgress" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x130++0x27 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. "GATINGRATIO,Clock gating ratio for event detection - N_1" "GATINGRATIO_0,GATINGRATIO_1,GATINGRATIO_2,GATINGRATIO_3" bitfld.long 0x00 0. "DISABLEMODULE,- Enabled" "DISABLEMODULE_0,DISABLEMODULE_1" line.long 0x04 "GPIO_OE,Output enable register" line.long 0x08 "GPIO_DATAIN,Data input register (with sampled input data)" line.long 0x0C "GPIO_DATAOUT,Data-output register (data to set on output pins)" line.long 0x10 "GPIO_LEVELDETECT0,Detect low-level register" line.long 0x14 "GPIO_LEVELDETECT1,Detect high-level register" line.long 0x18 "GPIO_RISINGDETECT,Detect rising edge register" line.long 0x1C "GPIO_FALLINGDETECT,Detect falling edge register" line.long 0x20 "GPIO_DEBOUNCENABLE,Debouncing enable register" line.long 0x24 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x24 0.--7. 1. "DEBOUNCETIME,8-bit values specifying the debouncing time" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data-output register" line.long 0x04 "GPIO_SETDATAOUT,Set data-output register" width 0x0B tree.end repeat.end tree.end tree "General_Purpose_Memory_Controller" base ad:0x50000000 tree "Channel_0" group.long 0x240++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" group.long 0x300++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x60++0x1B line.long 0x00 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_0,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_0,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x200++0x03 line.long 0x00 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x80++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_0,This register is not a true register. only an address location" group.long 0x7C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_0,This register is not a true register. only an address location" group.long 0x84++0x03 line.long 0x00 "GPMC_NAND_DATA_i_0,This register is not a true register.only an address location" tree.end tree "Channel_1" group.long 0x250++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_1,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_1,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_1,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_1,BCH ECC result (bits 96 to 127)" group.long 0x310++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_1,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_1,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_1,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x90++0x1B line.long 0x00 "GPMC_CONFIG1_i_1,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_1,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_1,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_1,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_1,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_1,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_1,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x204++0x03 line.long 0x00 "GPMC_ECCj_RESULT_1,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0xB0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_1,This register is not a true register. only an address location" group.long 0xAC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_1,This register is not a true register. only an address location" group.long 0xB4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_1,This register is not a true register.only an address location" tree.end tree "Channel_2" group.long 0x260++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_2,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_2,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_2,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_2,BCH ECC result (bits 96 to 127)" group.long 0x320++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_2,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_2,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_2,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0xC0++0x1B line.long 0x00 "GPMC_CONFIG1_i_2,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_2,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_2,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_2,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_2,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_2,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_2,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x208++0x03 line.long 0x00 "GPMC_ECCj_RESULT_2,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0xE0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_2,This register is not a true register. only an address location" group.long 0xDC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_2,This register is not a true register. only an address location" group.long 0xE4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_2,This register is not a true register.only an address location" tree.end tree "Channel_3" group.long 0x270++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_3,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_3,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_3,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_3,BCH ECC result (bits 96 to 127)" group.long 0x330++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_3,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_3,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_3,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0xF0++0x1B line.long 0x00 "GPMC_CONFIG1_i_3,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_3,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_3,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_3,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_3,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_3,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_3,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x20C++0x03 line.long 0x00 "GPMC_ECCj_RESULT_3,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x110++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_3,This register is not a true register. only an address location" group.long 0x10C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_3,This register is not a true register. only an address location" group.long 0x114++0x03 line.long 0x00 "GPMC_NAND_DATA_i_3,This register is not a true register.only an address location" tree.end tree "Channel_4" group.long 0x280++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_4,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_4,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_4,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_4,BCH ECC result (bits 96 to 127)" group.long 0x340++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_4,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_4,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_4,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x120++0x1B line.long 0x00 "GPMC_CONFIG1_i_4,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_4,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_4,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_4,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_4,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_4,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_4,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x210++0x03 line.long 0x00 "GPMC_ECCj_RESULT_4,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x140++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_4,This register is not a true register. only an address location" group.long 0x13C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_4,This register is not a true register. only an address location" group.long 0x144++0x03 line.long 0x00 "GPMC_NAND_DATA_i_4,This register is not a true register.only an address location" tree.end tree "Channel_5" group.long 0x290++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_5,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_5,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_5,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_5,BCH ECC result (bits 96 to 127)" group.long 0x350++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_5,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_5,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_5,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x150++0x1B line.long 0x00 "GPMC_CONFIG1_i_5,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_5,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_5,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_5,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_5,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_5,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_5,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x214++0x03 line.long 0x00 "GPMC_ECCj_RESULT_5,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x170++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_5,This register is not a true register. only an address location" group.long 0x16C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_5,This register is not a true register. only an address location" group.long 0x174++0x03 line.long 0x00 "GPMC_NAND_DATA_i_5,This register is not a true register.only an address location" tree.end tree "Channel_6" group.long 0x2A0++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_6,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_6,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_6,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_6,BCH ECC result (bits 96 to 127)" group.long 0x360++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_6,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_6,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_6,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x180++0x1B line.long 0x00 "GPMC_CONFIG1_i_6,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_6,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_6,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_6,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_6,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_6,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x218++0x03 line.long 0x00 "GPMC_ECCj_RESULT_6,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x1A0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_6,This register is not a true register. only an address location" group.long 0x19C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_6,This register is not a true register. only an address location" group.long 0x1A4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_6,This register is not a true register.only an address location" tree.end tree "Channel_7" group.long 0x2B0++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" group.long 0x370++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x1B0++0x1B line.long 0x00 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x08 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x0C "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x10 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" line.long 0x14 "GPMC_CONFIG6_i_7,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31 GPMC_FCLK cycles" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,?,?,?,?,?,?,?,?,15 GPMC_FCLK cycles" line.long 0x18 "GPMC_CONFIG7_i_7,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x21C++0x03 line.long 0x00 "GPMC_ECCj_RESULT_7,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x1D0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_7,This register is not a true register. only an address location" group.long 0x1CC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_7,This register is not a true register. only an address location" group.long 0x1D4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_7,This register is not a true register.only an address location" rgroup.long 0x220++0x03 line.long 0x00 "GPMC_ECCj_RESULT_8,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" tree.end group.long 0x2D0++0x03 line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface" hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation Only bits 0 to 7 are considered if the calculator is configured to use 8-bit data (GPMC_ECC_CONFIG[7] ECC16B = 0)" group.long 0x50++0x03 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC" bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1 - W1ActiveL" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1" newline bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0 - W0ActiveL" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1" newline bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location - NoForcePWr" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1" group.long 0x1F4++0x0B line.long 0x00 "GPMC_ECC_CONFIG,ECC configuration" bitfld.long 0x00 16. "ECCALGORITHM,ECC algorithm used" "ECCALGORITHM_0,ECCALGORITHM_1" newline bitfld.long 0x00 12.--13. "ECCBCHTSEL,Error correction capability used for BCH" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3" newline bitfld.long 0x00 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "ECCWRAPMODE_0,ECCWRAPMODE_1,ECCWRAPMODE_2,ECCWRAPMODE_3,ECCWRAPMODE_4,ECCWRAPMODE_5,ECCWRAPMODE_6,ECCWRAPMODE_7,ECCWRAPMODE_8,ECCWRAPMODE_9,ECCWRAPMODE_10,ECCWRAPMODE_11,ECCWRAPMODE_12,ECCWRAPMODE_13,ECCWRAPMODE_14,ECCWRAPMODE_15" newline bitfld.long 0x00 7. "ECC16B,Selects an ECC calculated on 16 columns - EightCol" "ECC16B_0,ECC16B_1" newline bitfld.long 0x00 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "1 sector (512-kB page),2 sectors,?,4 sectors (2-kB page),?,?,?,8 sectors (4-kB page)" newline bitfld.long 0x00 1.--3. "ECCCS,Selects the CS where ECC is computed - CS0" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,?,?,?,?" newline bitfld.long 0x00 0. "ECCENABLE,Enables the ECC feature - ECCDisabled" "ECCENABLE_0,ECCENABLE_1" line.long 0x04 "GPMC_ECC_CONTROL,ECC control" bitfld.long 0x04 8. "ECCCLEAR,Clear all ECC result registers Reads return 0" "ECCCLEAR_0,ECCCLEAR_1" newline bitfld.long 0x04 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Other enums: writing other values disables.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,?,?,?,?,?,?" line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC size" abitfld.long 0x08 22.--29. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline abitfld.long 0x08 12.--19. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes" "0x00=2 bytes,0x01=4 bytes,0x02=6 bytes,0x03=8 bytes,0xFF=512 bytes For BCH.." newline bitfld.long 0x08 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register - Size0Sel" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1" newline bitfld.long 0x08 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register - Size0Sel" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1" newline bitfld.long 0x08 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register - Size0Sel" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1" newline bitfld.long 0x08 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register - Size0Sel" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1" newline bitfld.long 0x08 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register - Size0Sel" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1" newline bitfld.long 0x08 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register - Size0Sel" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1" newline bitfld.long 0x08 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register - Size0Sel" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1" newline bitfld.long 0x08 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register - Size0Sel" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1" newline bitfld.long 0x08 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register - Size0Sel" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1" rgroup.long 0x44++0x07 line.long 0x00 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs" hexmask.long 0x00 0.--30. 1. "ILLEGALADD,Address of illegal access A30: 0 for memory region 1 for GPMC register region A29-A0: 1 GiB maximum" line.long 0x04 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs" rbitfld.long 0x04 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "ILLEGALMCMD_0,ILLEGALMCMD_1,ILLEGALMCMD_2,ILLEGALMCMD_3,ILLEGALMCMD_4,ILLEGALMCMD_5,ILLEGALMCMD_6,ILLEGALMCMD_7" newline rbitfld.long 0x04 4. "ERRORNOTSUPPADD,Not supported address error - NoErr" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1" newline rbitfld.long 0x04 3. "ERRORNOTSUPPMCMD,Not supported command error - NoErr" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1" newline rbitfld.long 0x04 2. "ERRORTIMEOUT,Time-out error - NoErr" "ERRORTIMEOUT_0,ERRORTIMEOUT_1" newline bitfld.long 0x04 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction - NotValid" "ERRORVALID_0,ERRORVALID_1" group.long 0x1C++0x03 line.long 0x00 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x00 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt - W1Masked" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1" newline bitfld.long 0x00 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt - W0Masked" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1" newline bitfld.long 0x00 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode - TCMasked" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1" newline bitfld.long 0x00 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt - FIFOMasked" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1" group.long 0x18++0x03 line.long 0x00 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt - W1Det0_R" "WAIT1EDGEDETECTIONSTATUS_0_w,WAIT1EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x00 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt - W0Det0_R" "WAIT0EDGEDETECTIONSTATUS_0_w,WAIT0EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x00 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt - TCStat0_R" "TERMINALCOUNTSTATUS_0_w,TERMINALCOUNTSTATUS_1_w" newline bitfld.long 0x00 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt - FIFOStat0_R" "FIFOEVENTSTATUS_0_w,FIFOEVENTSTATUS_1_w" group.long 0x1E0++0x07 line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "0 GPMC_FCLK cycle,1 GPMC_FCLK cycle,?,?,?,?,?,7 GPMC_FCLK cycles" newline bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization - OptDisabled" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1" newline bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7" newline bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration - RRDisabled" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1" newline bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "The next access is granted to the PFPW engine,The next two accesses are granted to the PFPW..,?,?,?,?,?,?,?,?,?,?,?,?,?,The next 16 accesses are granted to the PFPW.." newline abitfld.long 0x00 8.--14. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request" "0x00=0 byte,0x01=1 byte,0x40=64 bytes" newline bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine - PPDisabled" "ENABLEENGINE_0,ENABLEENGINE_1" newline bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode - W0" "WAITPINSELECTOR_0,WAITPINSELECTOR_1,?,?" newline bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to" "SYNCHROMODE_0,SYNCHROMODE_1" newline bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization - InterruptSync" "DMAMODE_0,DMAMODE_1" newline bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses - PrefetchRead" "ACCESSMODE_0,ACCESSMODE_1" line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" abitfld.long 0x04 0.--13. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select" "0x0000=0 byte,0x0001=1 byte,0x2000=8 Kbytes" group.long 0x1EC++0x07 line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control" bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine - Stop" "STARTENGINE_0_w,STARTENGINE_1_w" line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch engine status" abitfld.long 0x04 24.--30. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written" "0x00=0 byte available to be read or 0 free empty..,0x40=64 bytes available to be read or 64 empty.." newline bitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value - SmallerThanThres" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1" newline abitfld.long 0x04 0.--13. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" "0x0000=0 byte remaining to be read or to be..,0x0001=1 byte remaining to be read or to be..,0x2000=8 KiB remaining to be read or to be written" rgroup.long 0x00++0x03 line.long 0x00 "GPMC_REVISION,This register contains the IP revision code" rgroup.long 0x54++0x03 line.long 0x00 "GPMC_STATUS,The status register provides global status bits of the GPMC" bitfld.long 0x00 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1" newline bitfld.long 0x00 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1" newline bitfld.long 0x00 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer - b0" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1" group.long 0x10++0x07 line.long 0x00 "GPMC_SYSCONFIG,This register controls the various parameters of the interconnect" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy - FreeRun" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RstOnGoing" "RESETDONE_0,RESETDONE_1" group.long 0x40++0x03 line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter" abitfld.long 0x00 4.--12. "TIMEOUTSTARTVALUE,Start value of the time-out counter" "0x000=Zero GPMC_FCLK cycle,0x001=One GPMC_FCLK cycle,0x1FF=511 GPMC_FCLK cycles" newline bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature - TODisabled" "TIMEOUTENABLE_0,TIMEOUTENABLE_1" width 0x0B tree.end tree "General_Purpose_Timers" tree "TIMER10_L4_PER1Interconnect" base ad:0x48086000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" newline bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" width 0x0B tree.end tree "TIMER1_L4_WKUPInterconnect" base ad:0x4AE18000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" newline bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" width 0x0B tree.end tree "TIMER2_L4_PER1Interconnect" base ad:0x48032000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" newline bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" newline bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" newline bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" newline bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" newline bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" newline bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" width 0x0B tree.end tree "TIMER11_L4_PER1Interconnect" base ad:0x48088000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER12_L4_WKUPInterconnect" base ad:0x4AE20000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER13_L4_PER3Interconnect" base ad:0x48828000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER14_L4_PER3Interconnect" base ad:0x4882A000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER15_L4_PER3Interconnect" base ad:0x4882C000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER16_L4_PER3Interconnect" base ad:0x4882E000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER3_L4_PER1Interconnect" base ad:0x48034000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER4_L4_PER1Interconnect" base ad:0x48036000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER5_L4_PER3Interconnect" base ad:0x48820000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER6_L4_PER3Interconnect" base ad:0x48822000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER7_L4_PER3Interconnect" base ad:0x48824000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER8_L4_PER3Interconnect" base ad:0x48826000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree "TIMER9_L4_PER1Interconnect" base ad:0x4803E000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI on interrupt line,No action" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Trigger IRQ event by software" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "No action Read,Clear any pending event" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "No action Read,Clear any pending event" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "No action Read,Clear any pending event" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Set IRQ enable" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Set IRQ enable" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "No action Read,Clear IRQ enable" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "No action Read,Clear IRQ enable" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" width 0x0B tree.end tree.end tree "Gigabit_Ethernet_Switch_GMAC_SW_" tree "ALE" base ad:0x48484D00 rgroup.long 0x00++0x03 line.long 0x00 "ALE_IDVER,ADDRESS LOOKUP ENGINE revision register" group.long 0x08++0x03 line.long 0x00 "ALE_CONTROL,Address lookup engine control register" bitfld.long 0x00 31. "ENABLE_ALE,Enable ALE" "Drop all packets,Enable ALE packet processing" newline bitfld.long 0x00 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1" newline bitfld.long 0x00 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1" newline bitfld.long 0x00 8. "EN_P0_UNI_FLOOD,Enable Port 0 (Host Port) unicast flood" "do not flood unknown unicast packets to host..,flood unknown unicast packets to host port (p0)" newline bitfld.long 0x00 7. "LEARN_NO_VID,Learn No VID" "VID is learned with the source address,VID is not learned with the source address.." newline bitfld.long 0x00 6. "EN_VID0_MODE,Enable VLAN ID = 0 Mode" "Process the packet with VID = PORT_VLAN[11:0],Process the packet with VID = 0" newline bitfld.long 0x00 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set this bit indicates that a packet with a non OUI table entry matching source address will be dropped to the host unless the destination address matches a multicast table entry with the super bit set" "0,1" newline bitfld.long 0x00 4. "BYPASS,ALE Bypass - When set all packets received on ports 0 and 1 are sent to the host (only to the host)" "0,1" newline bitfld.long 0x00 3. "RATE_LIMIT_TX,Rate Limit Transmit mode" "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.." newline bitfld.long 0x00 2. "VLAN_AWARE,ALE VLAN Aware - Determines what is done if VLAN not found" "Flood if VLAN not found,Drop packet if VLAN not found" newline bitfld.long 0x00 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode" newline bitfld.long 0x00 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.." group.long 0x10++0x03 line.long 0x00 "ALE_PRESCALE,Address lookup engine prescale register" hexmask.long.tbyte 0x00 0.--19. 1. "PRESCALE,ALE Prescale Register - The input clock is divided by this value for use in the multicast/broadcast rate limiters" group.long 0x18++0x03 line.long 0x00 "ALE_UNKNOWN_VLAN,Address lookup engine unknown vlan register" bitfld.long 0x00 24.--29. "UNKNOWN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. "UNKNOWN_REG_MCAST_FLOOD_MASK,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. "UNKNOWN_MCAST_FLOOD_MASK,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "UNKNOWN_VLAN_MEMBER_LIST,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "ALE_TBLCTL,Address lookup engine table control" bitfld.long 0x00 31. "WRITE_RDZ,Write Bit - This bit is always read as zero" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "ENTRY_POINTER,Table Entry Pointer - The entry_pointer contains the table entry value that will be read/written with accesses to the table word registers" group.long 0x34++0x23 line.long 0x00 "ALE_TBLW2,Address lookup engine table word 2 register" hexmask.long.byte 0x00 0.--7. 1. "ENTRY71_64,Table entry bits 71:64" line.long 0x04 "ALE_TBLW1,Address lookup engine table word 1 register" line.long 0x08 "ALE_TBLW0,Address lookup engine table word 0 register" line.long 0x0C "ALE_PORTCTL0,Address lookup engine port 0 control register" hexmask.long.byte 0x0C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x0C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x0C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x0C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x0C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x0C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x0C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x10 "ALE_PORTCTL1,Address lookup engine port 1 control register" hexmask.long.byte 0x10 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x10 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x10 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x10 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x10 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x10 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x10 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x14 "ALE_PORTCTL2,Address lookup engine port 2 control register" hexmask.long.byte 0x14 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x14 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x14 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x14 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x14 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x14 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x14 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x18 "ALE_PORTCTL3,Address lookup engine port 3 control register" hexmask.long.byte 0x18 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x18 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x18 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x18 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x18 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x18 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x18 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x1C "ALE_PORTCTL4,Address lookup engine port 4 control register" hexmask.long.byte 0x1C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x1C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x1C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x1C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x1C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x1C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x1C 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x20 "ALE_PORTCTL5,Address lookup engine port 5 control register" hexmask.long.byte 0x20 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" newline hexmask.long.byte 0x20 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" newline bitfld.long 0x20 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x20 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" newline bitfld.long 0x20 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" newline bitfld.long 0x20 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x20 0.--1. "PORT_STATE,Port State" "Disabled,Blocked,Learn,Forward" width 0x0B tree.end tree "CPDMA" base ad:0x48484800 rgroup.long 0x00++0x0B line.long 0x00 "CPDMA_TX_IDVER,CPDMA_REGS TX revision register" line.long 0x04 "CPDMA_TX_CONTROL,CPDMA_REGS TX control register" bitfld.long 0x04 0. "TX_EN,TX Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_TX_TEARDOWN,CPDMA_REGS TX teardown register" rbitfld.long 0x08 31. "TX_TDN_RDY,Tx Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline bitfld.long 0x08 0.--2. "TX_TDN_CH,Tx Teardown" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3F line.long 0x00 "CPDMA_RX_IDVER,CPDMA_REGS RX revision register" line.long 0x04 "CPDMA_RX_CONTROL,CPDMA_REGS RX control register" bitfld.long 0x04 0. "RX_EN,RX DMA Enable" "Disabled,Enabled" line.long 0x08 "CPDMA_RX_TEARDOWN,CPDMA_REGS RX teardown register" rbitfld.long 0x08 31. "RX_TDN_RDY,Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" newline bitfld.long 0x08 0.--2. "RX_TDN_CH,Rx Teardown Channel -Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down" "0,1,2,3,4,5,6,7" line.long 0x0C "CPDMA_SOFT_RESET,CPDMA_REGS soft reset register" bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPDMA logic to be reset" "0,1" line.long 0x10 "CPDMA_DMACONTROL,CPDMA_REGS CPDMA control register" abitfld.long 0x10 8.--15. "TX_RLIM,Transmit Rate Limit Channel Bus" "0x00=no rate-limited channels,0x80=channel 7 is rate-limited,0xC0=channels 7 downto 6 are rate-limited,0xE0=channels 7 downto 5 are rate-limited,0xF0=channels 7 downto 4 are rate-limited,0xF8=channels 7 downto 3 are rate-limited,0xFC=channels 7 downto 2 are rate-limited,0xFE=channels 7 downto 1 are rate-limited,0xFF=channels 7 downto 0 are rate-limited all.." newline bitfld.long 0x10 4. "RX_CEF,RX Copy Error Frames Enable - Enables DMA overrun frames to be transferred to memory (up to the point of overrun)" "Frames containing overrun errors are filtered,Frames containing overrun errors are transferred.." newline bitfld.long 0x10 3. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in CPDMA_DMASTATUS)" newline bitfld.long 0x10 2. "RX_OFFLEN_BLOCK,Receive Offset/Length word write block" "Do not block the DMA writes to the receive..,Block all CPDMA DMA controller writes to the.." newline bitfld.long 0x10 1. "RX_OWNERSHIP,Receive Ownership Write Bit Value" "The CPDMA writes the receive ownership bit to..,The CPDMA writes the receive ownership bit to.." newline bitfld.long 0x10 0. "TX_PTYPE,Transmit Queue Priority Type" "The queue uses a round robin scheme to select..,The queue uses a fixed (channel 7 highest.." line.long 0x14 "CPDMA_DMASTATUS,CPDMA_REGS CPDMA status register" bitfld.long 0x14 31. "IDLE,Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet on transmit or receive" "0,1" newline bitfld.long 0x14 20.--23. "TX_HOST_ERR_CODE,TX Host Error Code - This field is set to indicate CPDMA detected TX DMA related host errors" "No error,SOP error,Ownership bit not set in SOP buffer,Zero Next Buffer Descriptor Pointer Without EOP,Zero Buffer Pointer,Zero Buffer Length,Packet Length Error (sum of buffers is less than..,?..." newline bitfld.long 0x14 16.--18. "TX_ERR_CH,TX Host Error" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--15. "RX_HOST_ERR_CODE,RX Host Error Code - This field is set to indicate CPDMA detected RX DMA related host errors" "No error,reserved,Ownership bit not set in input buffer,reserved,Zero Buffer Pointer,Zero buffer length on non-SOP descriptor,SOP buffer length not greater than offset 0x7 -..,?..." newline bitfld.long 0x14 8.--10. "RX_ERR_CH,RX Host Error" "0,1,2,3,4,5,6,7" line.long 0x18 "CPDMA_RX_BUFFER_OFFSET,CPDMA_REGS receive buffer offset" hexmask.long.word 0x18 0.--15. 1. "RX_BUFFER_OFFSET,Receive Buffer Offset Value - The RX_BUFFER_OFFSET will be written by the port into each frame SOP buffer descriptor buffer_offset field" line.long 0x1C "CPDMA_EMCONTROL,CPDMA_REGS emulation control" bitfld.long 0x1C 1. "SOFT,Emulation Soft Bit" "0,1" newline bitfld.long 0x1C 0. "FREE,Emulation Free Bit" "0,1" line.long 0x20 "CPDMA_TX_PRI0_RATE,CPDMA_REGS transmit (ingress) priority 0 rate" hexmask.long.word 0x20 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x20 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x24 "CPDMA_TX_PRI1_RATE,CPDMA_REGS transmit (ingress) priority 1 rate" hexmask.long.word 0x24 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x24 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x28 "CPDMA_TX_PRI2_RATE,CPDMA_REGS transmit (ingress) priority 2 rate" hexmask.long.word 0x28 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x28 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x2C "CPDMA_TX_PRI3_RATE,CPDMA_REGS transmit (ingress) priority 3 rate" hexmask.long.word 0x2C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x2C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x30 "CPDMA_TX_PRI4_RATE,CPDMA_REGS transmit (ingress) priority 4 rate" hexmask.long.word 0x30 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x30 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x34 "CPDMA_TX_PRI5_RATE,CPDMA_REGS transmit (ingress) priority 5 rate" hexmask.long.word 0x34 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x34 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x38 "CPDMA_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" hexmask.long.word 0x38 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x38 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x3C "CPDMA_TX_PRI7_RATE,CPDMA_REGS transmit (ingress) priority 7 rate" hexmask.long.word 0x3C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" newline hexmask.long.word 0x3C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" rgroup.long 0x80++0x17 line.long 0x00 "CPDMA_TX_INTSTAT_RAW,CPDMA_INT TX interrupt status register (raw value)" bitfld.long 0x00 7. "TX7_PEND,TX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "TX6_PEND,TX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "TX5_PEND,TX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "TX4_PEND,TX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "TX3_PEND,TX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "TX2_PEND,TX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "TX1_PEND,TX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "TX0_PEND,TX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_TX_INTSTAT_MASKED,CPDMA_INT TX interrupt status register (masked value)" bitfld.long 0x04 7. "TX7_PEND,TX7_PEND masked interrupt" "0,1" newline bitfld.long 0x04 6. "TX6_PEND,TX6_PEND masked interrupt" "0,1" newline bitfld.long 0x04 5. "TX5_PEND,TX5_PEND masked interrupt" "0,1" newline bitfld.long 0x04 4. "TX4_PEND,TX4_PEND masked interrupt" "0,1" newline bitfld.long 0x04 3. "TX3_PEND,TX3_PEND masked interrupt" "0,1" newline bitfld.long 0x04 2. "TX2_PEND,TX2_PEND masked interrupt" "0,1" newline bitfld.long 0x04 1. "TX1_PEND,TX1_PEND masked interrupt" "0,1" newline bitfld.long 0x04 0. "TX0_PEND,TX0_PEND masked interrupt" "0,1" line.long 0x08 "CPDMA_TX_INTMASK_SET,CPDMA_INT TX interrupt mask set register" bitfld.long 0x08 7. "TX7_MASK,TX Channel 7 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 6. "TX6_MASK,TX Channel 6 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 5. "TX5_MASK,TX Channel 5 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 4. "TX4_MASK,TX Channel 4 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 3. "TX3_MASK,TX Channel 3 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 2. "TX2_MASK,TX Channel 2 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 1. "TX1_MASK,TX Channel 1 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 0. "TX0_MASK,TX Channel 0 Mask - Write one to enable interrupt" "0,1" line.long 0x0C "CPDMA_TX_INTMASK_CLEAR,CPDMA_INT TX Interrupt mask clear register" bitfld.long 0x0C 7. "TX7_MASK,TX Channel 7 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 6. "TX6_MASK,TX Channel 6 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 5. "TX5_MASK,TX Channel 5 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 4. "TX4_MASK,TX Channel 4 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 3. "TX3_MASK,TX Channel 3 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 2. "TX2_MASK,TX Channel 2 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 1. "TX1_MASK,TX Channel 1 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 0. "TX0_MASK,TX Channel 0 Mask - Write one to disable interrupt" "0,1" line.long 0x10 "CPDMA_IN_VECTOR,CPDMA_INT input vector (read only)" line.long 0x14 "CPDMA_EOI_VECTOR,CPDMA_INT end of interrupt vector" bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,DMA End of Interrupt Vector - The EOI_VECTOR( 4:0) pins reflect the value written to this location one MAIN_CLK cycle after a write to this location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x5F line.long 0x00 "CPDMA_RX_INTSTAT_RAW,CPDMA_INT RX Interrupt status register (raw value)" bitfld.long 0x00 15. "RX7_THRESH_PEND,RX7_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 14. "RX6_THRESH_PEND,RX6_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 13. "RX5_THRESH_PEND,RX5_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 12. "RX4_THRESH_PEND,RX4_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 11. "RX3_THRESH_PEND,RX3_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 10. "RX2_THRESH_PEND,RX2_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 9. "RX1_THRESH_PEND,RX1_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 8. "RX0_THRESH_PEND,RX0_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 7. "RX7_PEND,RX7_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 6. "RX6_PEND,RX6_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 5. "RX5_PEND,RX5_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 4. "RX4_PEND,RX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "RX3_PEND,RX3_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 2. "RX2_PEND,RX2_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 1. "RX1_PEND,RX1_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 0. "RX0_PEND,RX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_RX_INTSTAT_MASKED,CPDMA_INT RX interrupt status register (masked value)" bitfld.long 0x04 15. "RX7_THRESH_PEND,RX7_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 14. "RX6_THRESH_PEND,RX6_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 13. "RX5_THRESH_PEND,RX5_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 12. "RX4_THRESH_PEND,RX4_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 11. "RX3_THRESH_PEND,RX3_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 10. "RX2_THRESH_PEND,RX2_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 9. "RX1_THRESH_PEND,RX1_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 8. "RX0_THRESH_PEND,RX0_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 7. "RX7_PEND,RX7_PEND masked int" "0,1" newline bitfld.long 0x04 6. "RX6_PEND,RX6_PEND masked int" "0,1" newline bitfld.long 0x04 5. "RX5_PEND,RX5_PEND masked int" "0,1" newline bitfld.long 0x04 4. "RX4_PEND,RX4_PEND masked int" "0,1" newline bitfld.long 0x04 3. "RX3_PEND,RX3_PEND masked int" "0,1" newline bitfld.long 0x04 2. "RX2_PEND,RX2_PEND masked int" "0,1" newline bitfld.long 0x04 1. "RX1_PEND,RX1_PEND masked int" "0,1" newline bitfld.long 0x04 0. "RX0_PEND,RX0_PEND masked int" "0,1" line.long 0x08 "CPDMA_RX_INTMASK_SET,CPDMA_INT RX interrupt mask set register" bitfld.long 0x08 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x08 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x08 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x08 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x08 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x08 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x08 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x08 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x08 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x08 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x08 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x08 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x08 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x08 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x08 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x08 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x0C "CPDMA_RX_INTMASK_CLEAR,CPDMA_INT RX interrupt mask clear register" bitfld.long 0x0C 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" newline bitfld.long 0x0C 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" newline bitfld.long 0x0C 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" newline bitfld.long 0x0C 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x0C 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" newline bitfld.long 0x0C 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" newline bitfld.long 0x0C 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" newline bitfld.long 0x0C 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x10 "CPDMA_DMA_INTSTAT_RAW,CPDMA_INT DMA interrupt status register (raw value)" bitfld.long 0x10 1. "HOST_PEND,Host Pending Interrupt - raw int read (before mask)" "0,1" newline bitfld.long 0x10 0. "STAT_PEND,Statistics Pending Interrupt - raw int read (before mask)" "0,1" line.long 0x14 "CPDMA_DMA_INTSTAT_MASKED,CPDMA_INT DMA interrupt status register (masked value)" bitfld.long 0x14 1. "HOST_PEND,Host Pending Interrupt - masked interrupt" "0,1" newline bitfld.long 0x14 0. "STAT_PEND,Statistics Pending Interrupt - masked interrupt" "0,1" line.long 0x18 "CPDMA_DMA_INTMASK_SET,CPDMA_INT DMA interrupt mask set register" bitfld.long 0x18 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to enable interrupt" "0,1" newline rbitfld.long 0x18 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to enable interrupt" "0,1" line.long 0x1C "CPDMA_DMA_INTMASK_CLEAR,CPDMA_INT DMA interrupt mask clear register" bitfld.long 0x1C 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x1C 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to disable interrupt" "0,1" line.long 0x20 "CPDMA_RX0_PENDTHRESH,CPDMA_INT receive threshold pending register channel 0" hexmask.long.byte 0x20 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x24 "CPDMA_RX1_PENDTHRESH,CPDMA_INT receive threshold pending register channel 1" hexmask.long.byte 0x24 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x28 "CPDMA_RX2_PENDTHRESH,CPDMA_INT receive threshold pending register channel 2" hexmask.long.byte 0x28 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x2C "CPDMA_RX3_PENDTHRESH,CPDMA_INT receive threshold pending register channel 3" hexmask.long.byte 0x2C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x30 "CPDMA_RX4_PENDTHRESH,CPDMA_INT receive threshold pending register channel 4" hexmask.long.byte 0x30 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x34 "CPDMA_RX5_PENDTHRESH,CPDMA_INT receive threshold pending register channel 5" hexmask.long.byte 0x34 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x38 "CPDMA_RX6_PENDTHRESH,CPDMA_INT receive threshold pending register channel 6" hexmask.long.byte 0x38 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x3C "CPDMA_RX7_PENDTHRESH,CPDMA_INT receive threshold pending register channel 7" hexmask.long.byte 0x3C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x40 "CPDMA_RX0_FREEBUFFER,CPDMA_INT receive free buffer register channel 0" hexmask.long.word 0x40 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x44 "CPDMA_RX1_FREEBUFFER,CPDMA_INT receive free buffer register channel 1" hexmask.long.word 0x44 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x48 "CPDMA_RX2_FREEBUFFER,CPDMA_INT receive free buffer register channel 2" hexmask.long.word 0x48 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x4C "CPDMA_RX3_FREEBUFFER,CPDMA_INT receive free buffer register channel 3" hexmask.long.word 0x4C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x50 "CPDMA_RX4_FREEBUFFER,CPDMA_INT receive free buffer register channel 4" hexmask.long.word 0x50 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x54 "CPDMA_RX5_FREEBUFFER,CPDMA_INT receive free buffer register channel 5" hexmask.long.word 0x54 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x58 "CPDMA_RX6_FREEBUFFER,CPDMA_INT receive free buffer register channel 6" hexmask.long.word 0x58 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x5C "CPDMA_RX7_FREEBUFFER,CPDMA_INT receive free buffer register channel 7" hexmask.long.word 0x5C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" width 0x0B tree.end tree "CPTS" base ad:0x48484C00 rgroup.long 0x00++0x07 line.long 0x00 "CPTS_IDVER,CPTS revision" line.long 0x04 "CPTS_CONTROL,Time sync control register" bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" newline bitfld.long 0x04 1. "INT_TEST,Interrupt Test - When set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1" bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable - When disabled (cleared to zero) the RCLK domain is held in reset" "Time Sync Disabled,Time Sync Enabled" group.long 0x0C++0x0B line.long 0x00 "CPTS_TS_PUSH,Time stamp event push register" bitfld.long 0x00 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1" line.long 0x04 "CPTS_TS_LOAD_VAL,Time stamp load value register" line.long 0x08 "CPTS_TS_LOAD_EN,Time stamp load enable register" bitfld.long 0x08 0. "TS_LOAD_EN,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written via theCPTS_TS_LOAD_VAL register" "0,1" group.long 0x20++0x0B line.long 0x00 "CPTS_INTSTAT_RAW,Time sync interrupt status raw register" bitfld.long 0x00 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" line.long 0x04 "CPTS_INTSTAT_MASKED,Time sync interrupt status masked register" bitfld.long 0x04 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" line.long 0x08 "CPTS_INT_ENABLE,Time sync interrupt enable register" bitfld.long 0x08 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" group.long 0x30++0x0B line.long 0x00 "CPTS_EVENT_POP,Event interrupt pop register" bitfld.long 0x00 0. "EVENT_POP,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO" "0,1" line.long 0x04 "CPTS_EVENT_LOW,Lower 32-bits of the event value" line.long 0x08 "CPTS_EVENT_HIGH,Upper 32-bits of the event value" bitfld.long 0x08 24.--28. "PORT_NUMBER,Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. "EVENT_TYPE,Time Sync Event Type" "Time Stamp Push Event,Time Stamp Rollover Event,Time Stamp Half Rollover Event,Hardware Time Stamp Push Event,Ethernet Receive Event,Ethernet Transmit Event,?..." bitfld.long 0x08 16.--19. "MESSAGE_TYPE,Message type - The message type value that was contained in an ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet" width 0x0B tree.end tree "MDIO" base ad:0x48485000 group.long 0x00++0x17 line.long 0x00 "MDIO_VER,MDIO Revision" line.long 0x04 "MDIO_CONTROL,MDIO Control register" bitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "State machine is not in idle state,State machine is in idle state" newline bitfld.long 0x04 30. "ENABLE,Enable control" "Disables the MDIO state machine,Enable the MDIO state machine" newline rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "Standard MDIO preamble is used,Disables this device from sending MDIO frame.." newline bitfld.long 0x04 19. "FAULT,Fault indicator" "No failure,Physical layer fault; the.." newline bitfld.long 0x04 18. "FAULTENB,Fault detect enable" "Disables the physical layer fault detection,Enables the physical layer fault detection" newline bitfld.long 0x04 17. "INTTESTENB,Interrupt test enable" "Interrupt bits are not set,Enables the host to set the USERINT and LINKINT.." newline hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider" line.long 0x08 "MDIO_ALIVE,PHY Alive Status Register" line.long 0x0C "MDIO_LINK,PHY Link Status" line.long 0x10 "MDIO_LINKINTRAW," bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x14 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" group.long 0x20++0x0F line.long 0x00 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt" bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x04 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt" bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x08 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set" bitfld.long 0x08 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3" line.long 0x0C "MDIO_USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear" bitfld.long 0x0C 0.--1. "USERINTMASKCLEAR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3" group.long 0x80++0x0F line.long 0x00 "MDIO_USERACCESS0,MDIO_User_Access" bitfld.long 0x00 31. "GO,Go" "0,1" newline bitfld.long 0x00 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x00 29. "ACK,Acknowledge" "0,1" newline bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--15. 1. "DATA,User data" line.long 0x04 "MDIO_USERPHYSEL0,MDIO User PHY Select" bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x04 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline bitfld.long 0x04 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "MDIO_USERACCESS1,MDIO User Access" bitfld.long 0x08 31. "GO,Go" "0,1" newline bitfld.long 0x08 30. "WRITE,Write enable" "0,1" newline bitfld.long 0x08 29. "ACK,Acknowledge" "0,1" newline bitfld.long 0x08 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x08 0.--15. 1. "DATA,User data" line.long 0x0C "MDIO_USERPHYSEL1,MDIO User PHY Select" bitfld.long 0x0C 7. "LINKSEL,Link status determination select" "0,1" newline bitfld.long 0x0C 6. "LINKINTENB,Link change interrupt enable" "Link change interrupts are disabled,Link change status interrupts for PHY address.." newline bitfld.long 0x0C 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PORT" base ad:0x48484100 group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 control register" bitfld.long 0x00 28.--30. "P0_DLR_CPDMA_CH,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline bitfld.long 0x00 21. "P0_VLAN_LTYPE2_EN,Port 0 VLAN LTYPE 2 enable" "disabled,enabled" bitfld.long 0x00 20. "P0_VLAN_LTYPE1_EN,Port 0 VLAN LTYPE 1 enable" "disabled,enabled" newline bitfld.long 0x00 16. "P0_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" group.long 0x08++0x1B line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P0_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P0_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P0_BLK_CNT,CPSW PORT 0 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P0_TX_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P0_RX_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P0_TX_IN_CTL,CPSW PORT 0 transmit FIFO control" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,Dual MAC mode,Rate Limit mode,reserved Note that Dual MAC mode is not.." newline bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual MAC mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P0_PORT_VLAN,CPSW PORT 0 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P0_TX_PRI_MAP,CPSW PORT 0 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) packet priority to header priority" bitfld.long 0x14 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) switch priority to DMA channel" bitfld.long 0x18 28.--30. "P2_PRI3,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "P2_PRI2,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "P2_PRI1,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "P2_PRI0,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "P1_PRI3,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "P1_PRI2,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "P1_PRI1,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "P1_PRI0,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x30++0x27 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P0_IDLE2LPI,Port 0 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P0_IDLE2LPI,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle" line.long 0x24 "P0_LPI2WAKE,Port 0 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P0_LPI2WAKE,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter" group.long 0x100++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 control register" bitfld.long 0x00 25. "P1_TX_CLKSTOP_EN,Port 1 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" bitfld.long 0x00 24. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline bitfld.long 0x00 21. "P1_VLAN_LTYPE2_EN,Port 1 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." bitfld.long 0x00 20. "P1_VLAN_LTYPE1_EN,Port 1 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline bitfld.long 0x00 16. "P1_DSCP_PRI_EN,Port 1 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" bitfld.long 0x00 15. "P1_TS_107,Port 1 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P1_TS_320,Port 1 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 13. "P1_TS_319,Port 1 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P1_TS_132,Port 1 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 11. "P1_TS_131,Port 1 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P1_TS_130,Port 1 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 9. "P1_TS_129,Port 1 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P1_TS_TTL_NONZERO,Port 1 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" bitfld.long 0x00 7. "P1_TS_UNI_EN,Port 1 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P1_TS_ANNEX_F_EN,Port 1 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" bitfld.long 0x00 5. "P1_TS_ANNEX_E_EN,Port 1 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P1_TS_ANNEX_D_EN,Port 1 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" bitfld.long 0x00 3. "P1_TS_LTYPE2_EN,Port 1 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P1_TS_LTYPE1_EN,Port 1 Time Sync LTYPE 1 enable" "disabled,enabled" bitfld.long 0x00 1. "P1_TS_TX_EN,Port 1 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P1_TS_RX_EN,Port 1 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x108++0x23 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P1_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P1_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P1_BLK_CNT,CPSW PORT 1 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P1_TX_BLK_CNT,Port 1 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P1_RX_BLK_CNT,Port 1 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P1_TX_IN_CTL,CPSW PORT 1 transmit FIFO control" bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P1_PORT_VLAN,CPSW PORT 1 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P1_TX_PRI_MAP,CPSW PORT 1 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P1_TS_SEQ_MTYPE,CPSW PORT 1 time sync sequence ID offset and message type" bitfld.long 0x14 16.--21. "P1_TS_SEQ_ID_OFFSET,Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x14 0.--15. 1. "P1_TS_MSG_TYPE_EN,Port 1 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P1_SA_LO,CPSW CPGMAC_SL1 source address low register" hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P1_SA_HI,CPSW CPGMAC_SL1 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P1_SEND_PERCENT,CPSW PORT 1 transmit queue send percentages" hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) whenCPSW_PTYPE[18] P1_PRI3_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) whenCPSW_PTYPE[17] P1_PRI2_SHAPE_EN is set (queue shaping enabled)" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[16] P1_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x130++0x27 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P1_IDLE2LPI,Port 1 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P1_IDLE2LPI,Port 1 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 1 idle to LPI counter on each clock that the port 1 transmit is not idle" line.long 0x24 "P1_LPI2WAKE,Port 1 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P1_LPI2WAKE,Port 1 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 1 LPI to wake counter" group.long 0x200++0x03 line.long 0x00 "P2_CONTROL,CPSW_3GF PORT 2 control register" bitfld.long 0x00 25. "P2_TX_CLKSTOP_EN,Port 2 Transmit clockstop enable 0 - RGMII transmit clockstop not enabled 1 - RGMII transmit clockstop enabled" "0,1" bitfld.long 0x00 24. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "Priority tagged packets have the zero VID..,Priority tagged packets are processed unchanged" newline bitfld.long 0x00 21. "P2_VLAN_LTYPE2_EN,Port 2 VLAN LTYPE 2 enable" "disabled,VLAN LTYPE2 enabled on.." bitfld.long 0x00 20. "P2_VLAN_LTYPE1_EN,Port 2 VLAN LTYPE 1 enable" "disabled,VLAN LTYPE1 enabled on.." newline bitfld.long 0x00 16. "P2_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "DSCP priority disabled,DSCP priority enabled" bitfld.long 0x00 15. "P2_TS_107,Port 2 Time Sync Destination IP Address 107 enable 0 - disabled 1 - destination IP address (dec) 224.0.0.107 is enabled" "0,1" newline bitfld.long 0x00 14. "P2_TS_320,Port 2 Time Sync Destination Port Number 320 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 13. "P2_TS_319,Port 2 Time Sync Destination Port Number 319 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 12. "P2_TS_132,Port 2 Time Sync Destination IP Address 132 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 11. "P2_TS_131,Port 2 Time Sync Destination IP Address 131 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 10. "P2_TS_130,Port 2 Time Sync Destination IP Address 130 enable" "disabled,Annex D (UDP/IPv4).." bitfld.long 0x00 9. "P2_TS_129,Port 2 Time Sync Destination IP Address 129 enable" "disabled,Annex D (UDP/IPv4).." newline bitfld.long 0x00 8. "P2_TS_TTL_NONZERO,Port 2 Time Sync Time To Live Non-zero enable" "TTL must be zero,TTL may be any value" bitfld.long 0x00 7. "P2_TS_UNI_EN,Port 2 Time Sync Unicast Enable 0 - Unicast disabled 1 - Unicast enabled" "0,1" newline bitfld.long 0x00 6. "P2_TS_ANNEX_F_EN,Port 2 Time Sync Annex F enable 0 - Annex F disabled 1 - Annex F enabled" "0,1" bitfld.long 0x00 5. "P2_TS_ANNEX_E_EN,Port 2 Time Sync Annex E enable 0 - Annex E disabled 1 - Annex E enabled" "0,1" newline bitfld.long 0x00 4. "P2_TS_ANNEX_D_EN,Port 2 Time Sync Annex D enable" "Annex D disabled,Annex D enabled" bitfld.long 0x00 3. "P2_TS_LTYPE2_EN,Port 2 Time Sync LTYPE 2 enable" "disabled,enabled" newline bitfld.long 0x00 2. "P2_TS_LTYPE1_EN,Port 2 Time Sync LTYPE 1 enable" "disabled,enabled" bitfld.long 0x00 1. "P2_TS_TX_EN,Port 2 Time Sync Transmit Enable" "disabled,enabled" newline bitfld.long 0x00 0. "P2_TS_RX_EN,Port 2 Time Sync Receive Enable" "Port 1 Receive Time Sync disabled,Port 1 Receive Time Sync enabled" group.long 0x208++0x23 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P2_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P2_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P2_BLK_CNT,CPSW PORT 2 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P2_TX_BLK_CNT,Port 2 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P2_RX_BLK_CNT,Port 2 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P2_TX_IN_CTL,CPSW PORT 2 transmit FIFO control" bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "Normal priority mode,reserved,Rate Limit mode,reserved" bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P2_PORT_VLAN,CPSW PORT 2 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" newline hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P2_TX_PRI_MAP,CPSW PORT 2 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" newline bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" newline bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 time sync sequence ID offset and message type" bitfld.long 0x14 16.--21. "P2_TS_SEQ_ID_OFFSET,Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x14 0.--15. 1. "P2_TS_MSG_TYPE_EN,Port 2 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P2_SA_LO,CPSW CPGMAC_SL2 source address low register" hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P2_SA_HI,CPSW CPGMAC_SL2 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_23,Source Address bits 31:23 (byte 3)" newline hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P2_SEND_PERCENT,CPSW PORT 2 transmit queue send percentages" hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) when theCPSW_PTYPE[21] P2_PRI3_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) when theCPSW_PTYPE[20] P2_PRI2_SHAPE_EN is set (queue shaping enabled)" newline hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[19] P2_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x230++0x27 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P2_IDLE2LPI,Port 2 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P2_IDLE2LPI,Port 2 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 2 idle to LPI counter on each clock that the port 2 transmit is not idle" line.long 0x24 "P2_LPI2WAKE,Port 2 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P2_LPI2WAKE,Port 2 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 2 LPI to wake counter" width 0x0B tree.end repeat 2. (list 1. 2. )(list ad:0x48484D80 ad:0x48484DC0 ) tree "SL$1" base $2 rgroup.long 0x00++0x2B line.long 0x00 "SL_IDVER,CPGMAC_SL revision register" line.long 0x04 "SL_MACCONTROL,CPGMAC_SL MAC control register" bitfld.long 0x04 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory" "MAC control frames are filtered (but acted upon..,MAC control frames are transferred to memory" bitfld.long 0x04 23. "RX_CSF_EN,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory" "Short frames are filtered,Short frames are transferred to memory" newline bitfld.long 0x04 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory" "Frames containing errors are filtered,Frames containing errors are transferred to memory" bitfld.long 0x04 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm" "0,1" newline bitfld.long 0x04 18. "EXT_EN,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register" "Use this setting for RMII/GMII mode,Use this setting for RGMII mode" bitfld.long 0x04 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY" "0,1" newline bitfld.long 0x04 16. "IFCTL_B,Interface Control B (NOT FUNCTIONAL)" "0,1" bitfld.long 0x04 15. "IFCTL_A,Interface Control A" "0,1" newline bitfld.long 0x04 11. "CMD_IDLE,Command Idle" "Idle not commanded,Idle Commanded (read IDLE in SL_MACSTATUS)" bitfld.long 0x04 10. "TX_SHORT_GAP_EN,Transmit Short Gap Enable" "Transmit with a short IPG is disabled,Transmit with a short IPG (when TX_SHORT_GAP.." newline bitfld.long 0x04 7. "GIG,Gigabit Mode" "0,1" bitfld.long 0x04 6. "TX_PACE,Transmit Pacing Enable" "Transmit Pacing Disabled,Transmit Pacing Enabled" newline bitfld.long 0x04 5. "GMII_EN,GMII Enable" "GMII RX and TX held in reset,GMII RX and TX released from reset" bitfld.long 0x04 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode" "Transmit Flow Control Disabled,Transmit Flow Control Enabled" newline bitfld.long 0x04 3. "RX_FLOW_EN,Receive Flow Control Enable" "Receive Flow Control Disabled Half-duplex mode -..,Receive Flow Control Enabled Half-duplex mode -.." bitfld.long 0x04 2. "MTEST,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers" "0,1" newline bitfld.long 0x04 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "Not looped back,Loop Back Mode enabled" bitfld.long 0x04 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "half duplex mode,full duplex mode" line.long 0x08 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x08 31. "IDLE,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command)" "The CPGMAC_SL is not in the idle state,The CPGMAC_SL is in the idle state" bitfld.long 0x08 4. "EXT_GIG,External GIG - This is the value of the EXT_GIG input bit" "0,1" newline bitfld.long 0x08 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit" "0,1" bitfld.long 0x08 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered" "0,1" newline bitfld.long 0x08 0. "TX_FLOW_ACT,Transmit Flow Control Active - When asserted this bit indicates that the pause time period is being observed for a received pause frame" "0,1" line.long 0x0C "SL_SOFT_RESET,CPGMAC_SL soft reset register" bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset" "0,1" line.long 0x10 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length - This field determines the maximum length of a received frame" line.long 0x14 "SL_BOFFTEST,CPGMAC_SL backoff test register" bitfld.long 0x14 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x14 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only)" newline rbitfld.long 0x14 12.--15. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes" line.long 0x18 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x18 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode)" line.long 0x1C "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x1C 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode)" line.long 0x20 "SL_EMCONTROL,CPGMAC_SL emulation control register" bitfld.long 0x20 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x20 0. "FREE,Emulation Free Bit" "0,1" line.long 0x24 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" bitfld.long 0x24 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x28 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.word 0x28 0.--8. 1. "TX_GAP,Transmit Inter-Packet Gap" width 0x0B tree.end repeat.end repeat 2. (list 1. 2. )(list ad:0x48485C00 ad:0x48485E00 ) tree "SPF$1" base $2 tree "Channel_0" group.long 0x1C++0x03 line.long 0x00 "SPF_CONSTj_0,Constant Register" group.long 0x78++0x03 line.long 0x00 "SPF_LOG_THRESHk_0,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" group.long 0x18++0x03 line.long 0x00 "SPF_RATELIMi_0,Rate Limit Register" hexmask.long.byte 0x00 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" tree.end tree "Channel_1" group.long 0x20++0x03 line.long 0x00 "SPF_CONSTj_1,Constant Register" group.long 0x7C++0x03 line.long 0x00 "SPF_LOG_THRESHk_1,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" group.long 0x1C++0x03 line.long 0x00 "SPF_RATELIMi_1,Rate Limit Register" hexmask.long.byte 0x00 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" tree.end tree "Channel_2" group.long 0x24++0x03 line.long 0x00 "SPF_CONSTj_2,Constant Register" group.long 0x80++0x03 line.long 0x00 "SPF_LOG_THRESHk_2,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" group.long 0x20++0x03 line.long 0x00 "SPF_RATELIMi_2,Rate Limit Register" hexmask.long.byte 0x00 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" tree.end tree "Channel_3" group.long 0x28++0x03 line.long 0x00 "SPF_CONSTj_3,Constant Register" group.long 0x84++0x03 line.long 0x00 "SPF_LOG_THRESHk_3,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" group.long 0x24++0x03 line.long 0x00 "SPF_RATELIMi_3,Rate Limit Register" hexmask.long.byte 0x00 0.--7. 1. "SPF_RATELIM,SPF Rate Limit Register" tree.end tree "Channel_4" group.long 0x2C++0x03 line.long 0x00 "SPF_CONSTj_4,Constant Register" group.long 0x88++0x03 line.long 0x00 "SPF_LOG_THRESHk_4,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" tree.end tree "Channel_5" group.long 0x30++0x03 line.long 0x00 "SPF_CONSTj_5,Constant Register" group.long 0x8C++0x03 line.long 0x00 "SPF_LOG_THRESHk_5,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" tree.end tree "Channel_6" group.long 0x34++0x03 line.long 0x00 "SPF_CONSTj_6,Constant Register" group.long 0x90++0x03 line.long 0x00 "SPF_LOG_THRESHk_6,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" tree.end tree "Channel_7" group.long 0x38++0x03 line.long 0x00 "SPF_CONSTj_7,Constant Register" group.long 0x94++0x07 line.long 0x00 "SPF_LOG_THRESHk_7,Log Threshold and Count Register" hexmask.long.word 0x00 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x00 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" line.long 0x04 "SPF_LOG_THRESHk_8,Log Threshold and Count Register" hexmask.long.word 0x04 16.--31. 1. "SPF_COUNT,Number of packets dropped for drop code k (8 is default)" hexmask.long.word 0x04 0.--15. 1. "SPF_THRESH,Number of packets to be dropped before logging starts" tree.end group.long 0x08++0x07 line.long 0x00 "SPF_CONTROL,SPF control register" bitfld.long 0x00 9. "SPF_LOGOW_EN,SPF Log Overwrite Enable" "0,1" bitfld.long 0x00 8. "SPF_LOG_EN,SPF Log Enable" "0,1" bitfld.long 0x00 3. "SPF_RULE_LOG,SPF Rule Engine Log Enable" "0,1" bitfld.long 0x00 2. "SPF_EXT_BYPASS,SPF Extractor Bypass Enable" "0,1" bitfld.long 0x00 1. "SPF_DROP,SPF Drop Enable" "0,1" bitfld.long 0x00 0. "SPF_ENABLE,SPF Enable" "0,1" line.long 0x04 "SPF_DROPCOUNT,Drop Count Register" hexmask.long.tbyte 0x04 0.--23. 1. "SPF_DROPCNT,SPF Drop counter indicates the number of packets dropped so far" rgroup.long 0x00++0x03 line.long 0x00 "SPF_IDVER,SPF revision register" group.long 0x5C++0x03 line.long 0x00 "SPF_INSTR_CTL,Instruction Control Register" bitfld.long 0x00 31. "SPF_INSTR_WEN,SPF Write enable bit specifies whether a write operation is to be performed" "0,1" bitfld.long 0x00 30. "SPF_INSTR_REN,SPF Read enable bit specifies whether a read operation is to be performed" "0,1" bitfld.long 0x00 0.--5. "SPF_INSTR_PTR,The address in the instruction memory that is to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x58++0x03 line.long 0x00 "SPF_INSTRW0,Instruction Word 0 Register" group.long 0x54++0x03 line.long 0x00 "SPF_INSTRW1,Instruction Word 1 Register" group.long 0x50++0x03 line.long 0x00 "SPF_INSTRW2,Instruction Word 2 Register" hexmask.long.word 0x00 0.--13. 1. "SPF_INSTR_W2,SPF Rule Engine Instruction Word [75:64] is read from or written to this field" group.long 0xA4++0x03 line.long 0x00 "SPF_INT_MASKED,Interrupt Status register" bitfld.long 0x00 0. "SPF_INT_MASKED,Status of interrupt signal with mask" "0,1" group.long 0xA0++0x03 line.long 0x00 "SPF_INT_RAW,Raw Interrupt Status register" bitfld.long 0x00 0. "SPF_INT_RAW,Status of Raw interrupt signal" "0,1" group.long 0x9C++0x03 line.long 0x00 "SPF_INTCNT,Interrupt Frequency Control Register" bitfld.long 0x00 0.--4. "SPF_INTCNT,Number of time thresholds must be met before a drop interrupt is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x60++0x0B line.long 0x00 "SPF_LOG_BEGIN,Log Begin Address Register" line.long 0x04 "SPF_LOG_END,Log End Address Register" line.long 0x08 "SPF_LOG_HWPTR,Log Hardware Pointer Register" group.long 0x70++0x07 line.long 0x00 "SPF_LOG_MAP0,Filter Code Map Register 0" hexmask.long.byte 0x00 24.--31. 1. "SPF_LOGMAP3,Mapping of drop code 3 to log threshold 3" hexmask.long.byte 0x00 16.--23. 1. "SPF_LOGMAP2,Mapping of drop code 2 to log threshold 2" hexmask.long.byte 0x00 8.--15. 1. "SPF_LOGMAP1,Mapping of drop code 1 to log threshold 1" hexmask.long.byte 0x00 0.--7. 1. "SPF_LOGMAP0,Mapping of drop code 0 to log threshold 0" line.long 0x04 "SPF_LOG_MAP1,Filter Code Map Register 1" hexmask.long.byte 0x04 24.--31. 1. "SPF_LOGMAP7,Mapping of drop code 7 to log threshold 7" hexmask.long.byte 0x04 16.--23. 1. "SPF_LOGMAP6,Mapping of drop code 6 to log threshold 6" hexmask.long.byte 0x04 8.--15. 1. "SPF_LOGMAP5,Mapping of drop code 5 to log threshold 5" hexmask.long.byte 0x04 0.--7. 1. "SPF_LOGMAP4,Mapping of drop code 4 to log threshold 4" group.long 0x6C++0x03 line.long 0x00 "SPF_LOG_SWPTR,Log Software Pointer Register" group.long 0xAC++0x03 line.long 0x00 "SPF_MASK_CLR,Interrupt Mask Clear Register" bitfld.long 0x00 0. "SPF_MASKCLR,Write a 1 to this bit to disable the interrupt" "0,1" group.long 0xA8++0x03 line.long 0x00 "SPF_MASK_SET,Interrupt Mask Set Register" bitfld.long 0x00 0. "SPF_MASKSET,Write a 1 to this bit to enable the interrupt" "0,1" group.long 0x14++0x03 line.long 0x00 "SPF_PRESCALE,Rate Limit Prescale Register" hexmask.long.tbyte 0x00 0.--19. 1. "SPF_PRESCALE,The MAIN clock is divided by this value for use in Rate Limiters" group.long 0x04++0x03 line.long 0x00 "SPF_STATUS,Status register" bitfld.long 0x00 0. "SPF_BUSY,SPF is Busy/Idle Busy Packet processing or logging in progress" "0,1" group.long 0x10++0x03 line.long 0x00 "SPF_SWRESET,Software Reset Register" bitfld.long 0x00 0. "SPF_SWRST,SPF Software reset bit can be set to initiate a software reset" "0,1" width 0x0B tree.end repeat.end tree "SS" base ad:0x48484000 rgroup.long 0x00++0x37 line.long 0x00 "CPSW_ID_VER,CPSW_3G ID version register" line.long 0x04 "CPSW_CONTROL,Switch control register" bitfld.long 0x04 4. "EEE_EN,EEE (Energy Efficient Ethernet) enable 0 - EEE is disabled" "0,1" bitfld.long 0x04 3. "DLR_EN,DLR enable" "DLR is disabled,DLR is disabled" newline bitfld.long 0x04 2. "RX_VLAN_ENCAP,Port 0 VLAN Encapsulation (egress)" "Port 0 receive packets (from CPSW_3G) are not..,Port 0 receive packets (from CPSW_3G) are VLAN.." bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "CPSW_3G is in the VLAN unaware mode,CPSW_3G is in the VLAN aware mode" newline bitfld.long 0x04 0. "FIFO_LOOPBACK,FIFO Loopback Mode" "Loopback is disabled,FIFO Loopback mode enabled" line.long 0x08 "CPSW_SOFT_RESET,Soft reset register" bitfld.long 0x08 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the 3G logic (INT REGS CPPI and SPF modules) to be reset" "0,1" line.long 0x0C "CPSW_STAT_PORT_EN,Statistics port enable register" bitfld.long 0x0C 2. "P2_STAT_EN,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "Port 2 statistics are not enabled,Port 2 statistics are enabled" bitfld.long 0x0C 1. "P1_STAT_EN,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "Port 1 statistics are not enabled,Port 1 statistics are enabled" newline bitfld.long 0x0C 0. "P0_STAT_EN,Port 0 Statistics Enable" "Port 0 statistics are not enabled,Port 0 statistics are enabled" line.long 0x10 "CPSW_PTYPE,Transmit priority type register" bitfld.long 0x10 21. "P2_PRI3_SHAPE_EN,Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" bitfld.long 0x10 20. "P2_PRI2_SHAPE_EN,Port 2 Queue Priority 2 Transmit Shape Enable - If there are two shaping queues then they must be priorities 3 and 2" "0,1" newline bitfld.long 0x10 19. "P2_PRI1_SHAPE_EN,Port 2 Queue Priority 1 Transmit Shape Enable - If there are three shaping queues all three bits should be set" "0,1" bitfld.long 0x10 18. "P1_PRI3_SHAPE_EN,Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" newline bitfld.long 0x10 17. "P1_PRI2_SHAPE_EN,Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping queues then they must be priorities 3 and 2" "0,1" bitfld.long 0x10 16. "P1_PRI1_SHAPE_EN,Port 1 Queue Priority 1 Transmit Shape Enable- If there are three shaping queues all three bits should be set" "0,1" newline bitfld.long 0x10 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "Port 2 priority type fixed,Port 2 priority type escalate Escalate should.." bitfld.long 0x10 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "Port 1 priority type fixed,Port 1 priority type escalate Escalate should.." newline bitfld.long 0x10 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "Port 0 priority type fixed,Port 0 priority type escalate Escalate should.." bitfld.long 0x10 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value When a port is in escalate priority this is the number of higher priority packets sent before the next lower priority is allowed to send a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CPSW_SOFT_IDLE,Software idle" bitfld.long 0x14 0. "SOFT_IDLE,Software Idle - Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet" "0,1" line.long 0x18 "CPSW_THRU_RATE,Throughput rate" bitfld.long 0x18 12.--15. "SL_RX_THRU_RATE,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. "CPDMA_THRU_RATE,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "CPSW_GAP_THRESH,CPGMAC_SL short gap threshold" bitfld.long 0x1C 0.--4. "GAP_THRESH,CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CPSW_TX_START_WDS,Transmit start words" hexmask.long.word 0x20 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words" line.long 0x24 "CPSW_FLOW_CONTROL,Flow control" bitfld.long 0x24 2. "P2_FLOW_EN,Port 2 Receive flow control enable" "0,1" bitfld.long 0x24 1. "P1_FLOW_EN,Port 1 Receive flow control enable" "0,1" newline bitfld.long 0x24 0. "P0_FLOW_EN,Port 0 Receive flow control enable" "0,1" line.long 0x28 "CPSW_VLAN_LTYPE,LTYPE1 and LTYPE 2 Register" hexmask.long.word 0x28 16.--31. 1. "VLAN_LTYPE2,Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx" hexmask.long.word 0x28 0.--15. 1. "VLAN_LTYPE1,Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx" line.long 0x2C "CPSW_TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 Register" hexmask.long.word 0x2C 16.--31. 1. "TS_LTYPE2,Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets" hexmask.long.word 0x2C 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync packets" line.long 0x30 "CPSW_DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x30 0.--15. 1. "DLR_LTYPE,DLR LTYPE" line.long 0x34 "CPSW_EEE_PRESCALE,EEE Pre-scale Counter Load Value Register" hexmask.long.word 0x34 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero" width 0x0B tree.end tree "STATERAM" base ad:0x48484A00 group.long 0x00++0x7F line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX channel 0 head descriptor pointer" line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX channel 1 head descriptor pointer" line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX channel 2 head descriptor pointer" line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX channel 3 head descriptor pointer" line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX channel 4 head descriptor pointer" line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX channel 5 head descriptor pointer" line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX channel 6 head descriptor pointer" line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX channel 7 head descriptor pointer" line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 channel 0 head descriptor pointer" line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 channel 1 head descriptor pointer" line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 channel 2 head descriptor pointer" line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 channel 3 head descriptor pointer" line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 channel 4 head descriptor pointer" line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 channel 5 head descriptor pointer" line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 channel 6 head desc pointer" line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 channel 7 head desc pointer" line.long 0x40 "TX0_CP,CPDMA_STATERAM TX channel 0 completion pointer register" line.long 0x44 "TX1_CP,CPDMA_STATERAM TX channel 1 completion pointer register" line.long 0x48 "TX2_CP,CPDMA_STATERAM TX channel 2 completion pointer register" line.long 0x4C "TX3_CP,CPDMA_STATERAM TX channel 3 completion pointer register" line.long 0x50 "TX4_CP,CPDMA_STATERAM TX channel 4 completion pointer register" line.long 0x54 "TX5_CP,CPDMA_STATERAM TX channel 5 completion pointer register" line.long 0x58 "TX6_CP,CPDMA_STATERAM TX channel 6 completion pointer register" line.long 0x5C "TX7_CP,CPDMA_STATERAM TX channel 7 completion pointer register" line.long 0x60 "RX0_CP,CPDMA_STATERAM RX channel 0 completion pointer register" line.long 0x64 "RX1_CP,CPDMA_STATERAM RX channel 1 completion pointer register" line.long 0x68 "RX2_CP,CPDMA_STATERAM RX channel 2 completion pointer register" line.long 0x6C "RX3_CP,CPDMA_STATERAM RX channel 3 completion pointer register" line.long 0x70 "RX4_CP,CPDMA_STATERAM RX channel 4 completion pointer register" line.long 0x74 "RX5_CP,CPDMA_STATERAM RX channel 5 completion pointer register" line.long 0x78 "RX6_CP,CPDMA_STATERAM RX channel 6 completion pointer register" line.long 0x7C "RX7_CP,CPDMA_STATERAM RX channel 7 completion pointer register" width 0x0B tree.end tree "STATS" base ad:0x48484900 group.long 0x00++0x27 line.long 0x00 "GOOD_RX_FRAMES,The total number of good frames received on the port" line.long 0x04 "BROADCAST_RX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x08 "MULTICAST_RX_FRAMES,The total number of good multicast frames received on the port" line.long 0x0C "PAUSE_RX_FRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not)" line.long 0x10 "RX_CRC_ERRORS,The total number of frames received on the port that experienced a CRC error" line.long 0x14 "RX_ALIGN_CODE_ERRORS,The total number of frames received on the port that experienced an alignment error or code error" line.long 0x18 "OVERSIZE_RX_FRAMES,The total number of oversized frames received on the port" line.long 0x1C "RX_JABBERS,The total number of jabber frames received on the port" line.long 0x20 "UNDERSIZE_RX_FRAMES,The total number of undersized frames received on the port" line.long 0x24 "RX_FRAGMENTS,The total number of frame fragments received on the port" group.long 0x30++0x5F line.long 0x00 "RX_OCTETS,The total number of bytes in all good frames received on the port" line.long 0x04 "GOOD_TX_FRAMES,The total number of good frames received on the port" line.long 0x08 "BROADCAST_TX_FRAMES,The total number of good broadcast frames received on the port" line.long 0x0C "MULTICAST_TX_FRAMES,The total number of good multicast frames received on the port" line.long 0x10 "PAUSE_TX_FRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port" line.long 0x14 "DEFERRED_TX_FRAMES,The total number of frames transmitted on the port that first experienced deferment" line.long 0x18 "COLLISIONS,This statistic records the total number of times that the port experienced a collision" line.long 0x1C "SINGLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced exactly one collision" line.long 0x20 "MULTIPLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced multiple collisions" line.long 0x24 "EXCESSIVE_COLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions" line.long 0x28 "LATE_COLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision" line.long 0x2C "TX_UNDERRUN,There should be no transmitted frames that experience underrun" line.long 0x30 "CARRIER_SENSE_ERRORS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x34 "TX_OCTETS,The total number of bytes in all good frames transmitted on the port" line.long 0x38 "RX_TX_64_OCTET_FRAMES,The total number of 64-byte frames received and transmitted on the port" line.long 0x3C "RX_TX_65_127_OCTET_FRAMES,The total number of frames of size 65 to 127 bytes received and transmitted on the port" line.long 0x40 "RX_TX_128_255_OCTET_FRAMES,The total number of frames of size 128 to 255 bytes received and transmitted on the port" line.long 0x44 "RX_TX_256_511_OCTET_FRAMES,The total number of frames of size 256 to 511 bytes received and transmitted on the port" line.long 0x48 "RX_TX_512_1023_OCTET_FRAMES,The total number of frames of size 512 to 1023 bytes received and transmitted on the port" line.long 0x4C "RX_TX_1024_UP_OCTET_FRAMES,The total number of frames of size 1024 to[13:0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port" line.long 0x50 "NET_OCTETS,The total number of bytes of frame data received and transmitted on the port" line.long 0x54 "RX_START_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA start of frame (SOF) overrun or were dropped by due to FIFO resource limitations. or were dropped by the SPF" line.long 0x58 "RX_MIDDLE_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun" line.long 0x5C "RX_DMA_OVERRUNS,The total number of frames received on the port that had either a DMA start of frame (SOF) overrun or a DMA MOF overrun" width 0x0B tree.end tree "WR" base ad:0x48485200 rgroup.long 0x00++0x1F line.long 0x00 "WR_IDVER,Subsystem wrapper revision register" line.long 0x04 "WR_SOFT_RESET,Subsystem soft reset register" bitfld.long 0x04 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT REGS CPPI)" "0,1" line.long 0x08 "WR_CONTROL,Subsystem control register" bitfld.long 0x08 8. "SS_EEE_EN,Subsystem Energy Efficient Ethernet enable" "EEE disabled,EEE enabled" bitfld.long 0x08 2.--3. "MMR_STDBYMODE,Configuration of the local initiator state management mode" "MMR_STDBYMODE_0,MMR_STDBYMODE_1,MMR_STDBYMODE_2,MMR_STDBYMODE_3" bitfld.long 0x08 0.--1. "MMR_IDLEMODE,Configuration of the local initiator state management mode" "MMR_IDLEMODE_0,MMR_IDLEMODE_1,MMR_IDLEMODE_2,MMR_IDLEMODE_3" line.long 0x0C "WR_INT_CONTROL,Subsystem interrupt control" bitfld.long 0x0C 31. "INT_TEST,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" bitfld.long 0x0C 16.--21. "INT_PACE_EN,Interrupt Pacing Enable INT_PACE_EN[0] - Enables RX_PULSE Pacing (0 is pacing bypass) INT_PACE_EN[1] - Enables TX_PULSE Pacing (0 is pacing bypass)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0C 0.--11. 1. "INT_PRESCALE,Interrupt Counter Prescaler - The number of MAIN_CLK periods in 4us" line.long 0x10 "WR_C0_RX_THRESH_EN,Subsystem core 0 receive threshold int enable register" hexmask.long.byte 0x10 0.--7. 1. "C0_RX_THRESH_EN,Core 0 Receive Threshold Enable - Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on RX_THRESH_PULSE" line.long 0x14 "WR_C0_RX_EN,Subsystem core 0 receive interrupt enable register" hexmask.long.byte 0x14 0.--7. 1. "C0_RX_EN,Core 0 Receive Enable - Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on RX_PULSE" line.long 0x18 "WR_C0_TX_EN,Subsystem core 0 transmit interrupt enable register" hexmask.long.byte 0x18 0.--7. 1. "C0_TX_EN,Core 0 Transmit Enable - Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on TX_PULSE" line.long 0x1C "WR_C0_MISC_EN,Subsystem core 0 misc interrupt enable register" bitfld.long 0x1C 0.--4. "C0_MISC_EN,Core 0 Misc Enable - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled to generate an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x40++0x0F line.long 0x00 "WR_C0_RX_THRESH_STAT,Subsystem core 0 rx threshold masked int status register" hexmask.long.byte 0x00 0.--7. 1. "C0_RX_THRESH_STAT,Core 0 Receive Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on RX_THRESH_PULSE" line.long 0x04 "WR_C0_RX_STAT,Subsystem core 0 rx interrupt masked int status register" hexmask.long.byte 0x04 0.--7. 1. "C0_RX_STAT,Core 0 Receive Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on RX_PULSE" line.long 0x08 "WR_C0_TX_STAT,Subsystem core 0 tx interrupt masked int status register" hexmask.long.byte 0x08 0.--7. 1. "C0_TX_STAT,Core 0 Transmit Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on TX_PULSE" line.long 0x0C "WR_C0_MISC_STAT,Subsystem core 0 misc interrupt masked int status register" bitfld.long 0x0C 0.--4. "C0_MISC_STAT,Core 0 Misc Masked Interrupt Status - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND SPF1_PEND EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled and generating an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x07 line.long 0x00 "WR_C0_RX_IMAX,Subsystem core 0 receive interrupts per millisecond" bitfld.long 0x00 0.--5. "C0_RX_IMAX,Core 0 Receive Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "WR_C0_TX_IMAX,Subsystem core 0 transmit interrupts per millisecond" bitfld.long 0x04 0.--5. "C0_TX_IMAX,Core 0 Transmit Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on TX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x88++0x07 line.long 0x00 "WR_RGMII_CTL,RGMII control signal register" bitfld.long 0x00 7. "RGMII2_FULLDUPLEX,RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 5.--6. "RGMII2_SPEED,RGMII2 Speed - This is the CPRGMII speed output signal" "0,1,2,3" bitfld.long 0x00 4. "RGMII2_LINK,RGMII2 Link Indicator - This is the CPRGMII link output signal" "RGMII2 link is down,RGMII2 link is up" newline bitfld.long 0x00 3. "RGMII1_FULLDUPLEX,RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal" "Half-duplex mode,Full-duplex mode" bitfld.long 0x00 1.--2. "RGMII1_SPEED,RGMII1 Speed - This is the CPRGMII speed output signal" "0,1,2,3" bitfld.long 0x00 0. "RGMII1_LINK,RGMII1 Link Indicator - This is the CPRGMII link output signal" "RGMII1 link is down,RGMII1 link is up" line.long 0x04 "WR_STATUS,Subsystem Status register" bitfld.long 0x04 2. "SPF2_CLKSTOP_ACK,SPF2 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF2" "0,1" bitfld.long 0x04 1. "SPF1_CLKSTOP_ACK,SPF1 Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to SPF1" "0,1" bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,CPSW_3G Clockstop Acknowledge - When asserted the subsystem gated clock is not turned on due to the CPSW_3G" "0,1" width 0x0B tree.end tree.end tree "GPU" base ad:0x5600FE00 rgroup.long 0x00++0x07 line.long 0x00 "REVISION,Revision register" line.long 0x04 "HWINFO,Hardware implementation information" bitfld.long 0x04 2. "MEM_BUS_WIDTH,Memory bus width" "64 bits,128 bits" bitfld.long 0x04 0.--1. "SYS_BUS_WIDTH,System bus width" "32 bits,64 bits,128 bits,Reserved" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,System configuration register" bitfld.long 0x00 4.--5. "STANDBY_MODE,Clock standby mode" "Force-standby,No-standby,Smart-standby,Reserved" bitfld.long 0x00 2.--3. "IDLE_MODE,Clock idle mode" "Force-standby,No-standby,Smart-standby,Reserved" group.long 0x24++0x2F line.long 0x00 "IRQSTATUS_RAW_0,Raw IRQ 0 status" bitfld.long 0x00 0. "INIT_MINTERRUPT_RAW,Interrupt 0 raw event: Write" "No event pending,Event pending" line.long 0x04 "IRQSTATUS_RAW_1,Raw IRQ 1 status" bitfld.long 0x04 0. "TARGET_SINTERRUPT_RAW,Interrupt 1 raw event: Write" "No event pending,Event pending" line.long 0x08 "IRQSTATUS_RAW_2,Raw IRQ 2 status" bitfld.long 0x08 0. "THALIA_IRQ_RAW,Interrupt 0 raw event: Write" "No event pending,Event pending" line.long 0x0C "IRQSTATUS_0,Interrupt 0 status event" bitfld.long 0x0C 0. "INIT_MINTERRUPT_STATUS,Interrupt 0 raw event: Write" "No event pending,Event pending and interrupt enabled" line.long 0x10 "IRQSTATUS_1,Interrupt" bitfld.long 0x10 0. "TARGET_SINTERRUPT_STATUS,Interrupt 0 raw event: Write" "No event pending,Event pending and interrupt enabled" line.long 0x14 "IRQSTATUS_2,Interrupt" bitfld.long 0x14 0. "THALIA_IRQ_STATUS,Interrupt 0 raw event: Write" "No event pending,Event pending and interrupt enabled" line.long 0x18 "IRQENABLE_SET_0,Enable Interrupt" bitfld.long 0x18 0. "INIT_MINTERRUPT_ENABLE,To enable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" line.long 0x1C "IRQENABLE_SET_1,Enable Interrupt 1" bitfld.long 0x1C 0. "TARGET_SINTERRUPT_ENABLE,To enable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" line.long 0x20 "IRQENABLE_SET_2,Enable Interrupt 2" bitfld.long 0x20 0. "THALIA_IRQ_ENABLE,To enable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" line.long 0x24 "IRQENABLE_CLR_0,Disable Interrupt" bitfld.long 0x24 0. "INIT_MINTERRUPT_DISABLE,To disable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" line.long 0x28 "IRQENABLE_CLR_1,Disable Interrupt" bitfld.long 0x28 0. "TARGET_SINTERRUPT_DISABLE,To disable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" line.long 0x2C "IRQENABLE_CLR_2,Disable Interrupt" bitfld.long 0x2C 0. "THALIA_IRQ_DISABLE,To disable interrupt: Write" "Interrupt is disabled,Interrupt is enabled" group.long 0x100++0x13 line.long 0x00 "PAGE_CONFIG,Configure memory pages" bitfld.long 0x00 31. "THALIA_INT_BYPASS,Bypass OCP IPG interrupt logic" "0,1" bitfld.long 0x00 3.--4. "OCP_PAGE_SIZE,Defines the page size on OCP memory interface" "4 KiB,2 KiB,1 KiB,512B" newline bitfld.long 0x00 2. "MEM_PAGE_CHECK_EN,To enable page boundary" "Disabled,Enabled" bitfld.long 0x00 0.--1. "MEM_PAGE_SIZE,Defines the page size on internal memory interface" "4 KiB,2 KiB,1 KiB,512B" line.long 0x04 "INTERRUPT_EVENT,Interrupt events" bitfld.long 0x04 18. "TARGET_INVALID_OCP_CMD,Invalid command from OCP: Write" "No event pending,Event pending" bitfld.long 0x04 17. "TARGET_CMD_FIFO_FULL,Command FIFO full: Write" "No event pending,Event pending" newline bitfld.long 0x04 16. "TARGET_RESP_FIFO_FULL,Response FIFO full: Write" "No event pending,Event pending" bitfld.long 0x04 13. "INT_MEM_REQ_FIFO_OVERRUN_1,Memory request FIFO overrun: Write" "No event pending,Event pending" newline bitfld.long 0x04 12. "INIT_READ_TAG_FIFO_OVERRUN_1,Read tag FIFO overrun: Write" "No event pending,Event pending" bitfld.long 0x04 11. "INIT_PAGE_CROSS_ERROR_1,Memory page had been crossed during a burst: Write" "No event pending,Event pending" newline bitfld.long 0x04 10. "INIT_RESP_ERROR_1,Receiving error response: Write" "No event pending,Event pending" bitfld.long 0x04 9. "INIT_RESP_UNUSED_TAG_1,Receiving response on an unused OCP TAG: Write" "No event pending,Event pending" newline bitfld.long 0x04 8. "INIT_RESP_UNEXPECTED_1,Receiving response when not expected: Write" "No event pending,Event pending" bitfld.long 0x04 5. "INIT_MEM_REQ_FIFO_OVERRUN_0,Memory request FIFO overrun;" "No event pending,Event pending" newline bitfld.long 0x04 4. "INIT_READ_TAG_FIFO_OVERRUN_0,Read tag FIFO overrun: Write" "No event pending,Event pending" bitfld.long 0x04 3. "INIT_PAGE_CROSS_ERROR_0,Memory page had been crossed during a burst" "No event pending,Event pending" newline bitfld.long 0x04 2. "INIT_RESP_ERROR_0,Receiving error response: Write" "No event pending,Event pending" bitfld.long 0x04 1. "INIT_RESP_UNUSED_TAG_0,Receiving response on an unused OCP TAG: Write" "No event pending,Event pending" newline bitfld.long 0x04 0. "INIT_RESP_UNEXPECTED_0,Receiving response when not expected: Write" "No event pending,Event pending" line.long 0x08 "DEBUG_CONFIG,Configuration of debug modes" bitfld.long 0x08 5. "SELECT_INT_IDLE,To select which idle the disconnect protocol should act on" "Whole SGX idle,OCP initiator idle" bitfld.long 0x08 4. "FORCE_PASS_DATA,Forces the initiator to pass data independent of disconnect protocol" "Do not force normal operation,Never fence request to OCP" newline bitfld.long 0x08 2.--3. "FORCE_INIT_IDLE,Forces initiator idle: 0x0 " "?,Always idle,Never idle,Do not force normal operation" bitfld.long 0x08 0.--1. "FORCE_TARGET_IDLE,Forces target idle: 0x0 " "?,Always idle,Never idle,Do not force normal operation" line.long 0x0C "DEBUG_STATUS_0,Port0 debug status register" bitfld.long 0x0C 31. "CMD_DEBUG_STATE,Target command state-machine" "IDLE,Accept.." bitfld.long 0x0C 30. "CMD_RESP_DEBUG_STATE,Target response state-machine" "Send accept,Wait accept" newline bitfld.long 0x0C 29. "TARGET_IDLE,Target idle" "0,1" bitfld.long 0x0C 28. "RESP_FIFO_FULL,Target response FIFO full" "0,1" newline bitfld.long 0x0C 27. "CMD_FIFO_FULL,Target command FIFO full" "0,1" bitfld.long 0x0C 26. "RESP_ERROR,Respond to OCP with error which could be caused by either address misalignment or invalid byte enable" "0,1" newline bitfld.long 0x0C 21.--25. "WHICH_TARGET_REGISTER,Indicates which OCP target registers to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 18.--20. "TARGET_CMD_OUT,Command received from OCP" "CMD_WRSYS,CMD_RDSYS,CMD_WR_ERROR,CMD_RD_ERROR,CMD_CHK_WRADDR_PAGE (not used),CMD_CHK_RDADDR_PAGE (not used),CMD_TARGET_REG_,CMD_TARGET_REG_READ" newline bitfld.long 0x0C 17. "INIT_MSTANDBY,Status of init_MStandby signal" "0,1" bitfld.long 0x0C 16. "INIT_MWAIT,Status of init_MWait signal" "0,1" newline bitfld.long 0x0C 15. "INIT_MDISCREQ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x0C 13.--14. "INIT_MDISCACK,Disconnect status of the OCP interface" "FUNCT,TRANS,Reserved,IDLE" newline bitfld.long 0x0C 12. "INIT_SCONNECT_2,Defines whether to wait in M_WAIT state for MConnect FSM" "Skip M_WAIT state,Wait in M_WAIT state" bitfld.long 0x0C 11. "INIT_SCONNECT_1,Defines the busy-ness state of the slave" "Slave is drained,Slave is loaded" newline bitfld.long 0x0C 10. "INIT_SCONNECT_0,Disconnect from slave" "Disconnect request from slave,Connect request from slave" bitfld.long 0x0C 8.--9. "INIT_MCONNECT,Initiator MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON" newline bitfld.long 0x0C 6.--7. "TARGET_SIDLEACK,Acknowledge the SIdleAck state-machine" "FUNCT,SLEEP TRANS,Reserved,IDLE" bitfld.long 0x0C 4.--5. "TARGET_SDISCACK,Acknowledge the SDiscAck state-machine" "FUNCT,TRANS,Reserved,IDLE" newline bitfld.long 0x0C 3. "TARGET_SIDLEREQ,Request the target to go idle: 0 Do not go idle or go active 1 Go idle" "0,1" bitfld.long 0x0C 2. "TARGET_SCONNECT,Target SConnect bit 0 state" "Disconnect interface,Connect OCP interface" newline bitfld.long 0x0C 0.--1. "TARGET_MCONNECT,Target MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON" line.long 0x10 "DEBUG_STATUS_1,Port1 debug status register" bitfld.long 0x10 31. "CMD_DEBUG_STATE,Target command state-machine" "IDLE,Accept.." bitfld.long 0x10 30. "CMD_RESP_DEBUG_STATE,Target response state-machine" "Send accept,Wait accept" newline bitfld.long 0x10 29. "TARGET_IDLE,Target idle" "0,1" bitfld.long 0x10 28. "RESP_FIFO_FULL,Target response FIFO full" "0,1" newline bitfld.long 0x10 27. "CMD_FIFO_FULL,Target command FIFO full" "0,1" bitfld.long 0x10 26. "RESP_ERROR,Respond to OCP with error which could be caused by either address misalignment or invalid byte enable" "0,1" newline bitfld.long 0x10 21.--25. "WHICH_TARGET_REGISTER,Indicates which OCP target registers to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 18.--20. "TARGET_CMD_OUT,Command received from OCP" "CMD_WRSYS,CMD_RDSYS,CMD_WR_ERROR,CMD_RD_ERROR,CMD_CHK_WRADDR_PAGE (not used),CMD_CHK_RDADDR_PAGE (not used),CMD_TARGET_REG_,CMD_TARGET_REG_READ" newline bitfld.long 0x10 17. "INIT_MSTANDBY,Status of init_MStandby signal" "0,1" bitfld.long 0x10 16. "INIT_MWAIT,Status of init_MWait signal" "0,1" newline bitfld.long 0x10 15. "INIT_MDISCREQ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x10 13.--14. "INIT_MDISCACK,Disconnect status of the OCP interface" "FUNCT,SLEEP TRANS,Reserved,IDLE" newline bitfld.long 0x10 12. "INIT_SCONNECT_2,Defines whether to wait in M_WAIT state for MConnect FSM" "Skip M_WAIT state,Wait in M_WAIT state" bitfld.long 0x10 11. "INIT_SCONNECT_1,Defines the busy-ness state of the slave" "Slave is drained,Slave is loaded" newline bitfld.long 0x10 10. "INIT_SCONNECT_0,Disconnect from slave" "Disconnect request from slave,Connect request from slave" bitfld.long 0x10 8.--9. "INIT_MCONNECT,Initiator MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON" newline bitfld.long 0x10 6.--7. "TARGET_SIDLEACK,Acknowledge the SIdleAck state-machine" "FUNCT,SLEEP TRANS,Reserved,IDLE" bitfld.long 0x10 4.--5. "TARGET_SDISCACK,Acknowledge the SDiscAck state-machine" "FUNCT,TRANS,Reserved,IDLE" newline bitfld.long 0x10 3. "TARGET_SIDLEREQ,Request the target to go idle" "Do not go idle or..,Go idle" bitfld.long 0x10 2. "TARGET_SCONNECT,Target SConnect bit 0 state" "Disconnect interface,Connect OCP interface" newline bitfld.long 0x10 0.--1. "TARGET_MCONNECT,Target MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON" width 0x0B tree.end tree "Introduction" base ad:0x54160000 group.long 0x294++0x03 line.long 0x00 "DRM_SUSPEND_CTRL37,susp" bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL" "SUSPEND_SEL field will select which suspend..,SUSPEND_SEL field ignored" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat 5. (list 32. 33. 34. 35. 36. )(list 0x00 0x04 0x08 0x0C 0x10 ) group.long ($2+0x280)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL" "SUSPEND_SEL field will select which suspend..,SUSPEND_SEL field ignored" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL" "SUSPEND_SEL field will select which suspend..,SUSPEND_SEL field ignored" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "DRM_SUSPEND_CTRL$1," bitfld.long 0x00 4.--8. "SUSPEND_SEL,Suspend signal selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. "SUSPEND_DEFAULT_OVERRIDE,Enable or disable the override value in SUSPEND_SEL" "SUSPEND_SEL field will select which suspend..,SUSPEND_SEL field ignored" newline bitfld.long 0x00 0. "SENSCTRL,Sensitivity Control for suspend signals" "Suspend signal will not reach the peripheral,Suspend signal will reach the peripheral" repeat.end width 0x0B tree.end tree "IODELAYCONFIG_Module" base ad:0x4844A000 group.long 0x0C++0x03 line.long 0x00 "CONFIG_REG_0,Calibration Control Register" bitfld.long 0x00 1. "ROM_READ,Triggers complete ROM read when '1' is written" "0,1" bitfld.long 0x00 0. "CALIBRATION_START,Triggers hardware calibration when '1' is written" "0,1" group.long 0x14++0x0B line.long 0x00 "CONFIG_REG_2,Reference Clock Period Register" hexmask.long.word 0x00 0.--15. 1. "REFCLK_PERIOD,15:0 stores the binary equivalent of reference clock period in units of 10ps" line.long 0x04 "CONFIG_REG_3,coarse calibration results register" hexmask.long.word 0x04 16.--31. 1. "COARSE_DELAY_COUNT,Results of 16 bit counter clocked by 'delay line oscillator' clock during calibration" hexmask.long.word 0x04 0.--15. 1. "COARSE_REF_COUNT,Results of 16 bit counter clocked by 'reference' clock during coarse calibration" line.long 0x08 "CONFIG_REG_4,fine calibration results register" hexmask.long.word 0x08 16.--31. 1. "FINE_DELAY_COUNT,Results of 16 bit counter clocked by 'delay line oscillator' clock during fine calibration" hexmask.long.word 0x08 0.--15. 1. "FINE_REF_COUNT,Results of 16 bit counter clocked by 'reference' clock during fine calibration" group.long 0x2C++0xCF3 line.long 0x00 "CONFIG_REG_8,Global Lock Register" bitfld.long 0x00 0. "GLOBAL_LOCK_BIT,Global Lock Bit Register" "0,1" line.long 0x04 "CFG_RMII_MHZ_50_CLK_IN,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_in interface" bitfld.long 0x04 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x04 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x08 "CFG_RMII_MHZ_50_CLK_OEN,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_oen interface" bitfld.long 0x08 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x08 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x0C "CFG_RMII_MHZ_50_CLK_OUT,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_out interface" bitfld.long 0x0C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x0C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x10 "CFG_WAKEUP0_IN,Delay Select Value in binary coded form for cfg_Wakeup0_in interface" bitfld.long 0x10 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x10 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x14 "CFG_WAKEUP0_OEN,Delay Select Value in binary coded form for cfg_Wakeup0_oen interface" bitfld.long 0x14 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x14 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x18 "CFG_WAKEUP0_OUT,Delay Select Value in binary coded form for cfg_Wakeup0_out interface" bitfld.long 0x18 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x18 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1C "CFG_WAKEUP1_IN,Delay Select Value in binary coded form for cfg_Wakeup1_in interface" bitfld.long 0x1C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x20 "CFG_WAKEUP1_OEN,Delay Select Value in binary coded form for cfg_Wakeup1_oen interface" bitfld.long 0x20 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x20 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x24 "CFG_WAKEUP1_OUT,Delay Select Value in binary coded form for cfg_Wakeup1_out interface" bitfld.long 0x24 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x24 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x28 "CFG_WAKEUP2_IN,Delay Select Value in binary coded form for cfg_Wakeup2_in interface" bitfld.long 0x28 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x28 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2C "CFG_WAKEUP2_OEN,Delay Select Value in binary coded form for cfg_Wakeup2_oen interface" bitfld.long 0x2C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x30 "CFG_WAKEUP2_OUT,Delay Select Value in binary coded form for cfg_Wakeup2_out interface" bitfld.long 0x30 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x30 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x34 "CFG_WAKEUP3_IN,Delay Select Value in binary coded form for cfg_Wakeup3_in interface" bitfld.long 0x34 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x34 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x38 "CFG_WAKEUP3_OEN,Delay Select Value in binary coded form for cfg_Wakeup3_oen interface" bitfld.long 0x38 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x38 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3C "CFG_WAKEUP3_OUT,Delay Select Value in binary coded form for cfg_Wakeup3_out interface" bitfld.long 0x3C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x40 "CFG_DCAN1_RX_IN,Delay Select Value in binary coded form for cfg_dcan1_rx_in interface" bitfld.long 0x40 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x40 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x44 "CFG_DCAN1_RX_OEN,Delay Select Value in binary coded form for cfg_dcan1_rx_oen interface" bitfld.long 0x44 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x44 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x48 "CFG_DCAN1_RX_OUT,Delay Select Value in binary coded form for cfg_dcan1_rx_out interface" bitfld.long 0x48 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x48 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4C "CFG_DCAN1_TX_IN,Delay Select Value in binary coded form for cfg_dcan1_tx_in interface" bitfld.long 0x4C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x50 "CFG_DCAN1_TX_OEN,Delay Select Value in binary coded form for cfg_dcan1_tx_oen interface" bitfld.long 0x50 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x50 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x54 "CFG_DCAN1_TX_OUT,Delay Select Value in binary coded form for cfg_dcan1_tx_out interface" bitfld.long 0x54 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x54 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x58 "CFG_DCAN2_RX_IN,Delay Select Value in binary coded form for cfg_dcan2_rx_in interface" bitfld.long 0x58 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x58 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5C "CFG_DCAN2_RX_OEN,Delay Select Value in binary coded form for cfg_dcan2_rx_oen interface" bitfld.long 0x5C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x60 "CFG_DCAN2_RX_OUT,Delay Select Value in binary coded form for cfg_dcan2_rx_out interface" bitfld.long 0x60 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x60 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x64 "CFG_DCAN2_TX_IN,Delay Select Value in binary coded form for cfg_dcan2_tx_in interface" bitfld.long 0x64 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x64 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x68 "CFG_DCAN2_TX_OEN,Delay Select Value in binary coded form for cfg_dcan2_tx_oen interface" bitfld.long 0x68 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x68 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6C "CFG_DCAN2_TX_OUT,Delay Select Value in binary coded form for cfg_dcan2_tx_out interface" bitfld.long 0x6C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x70 "CFG_EMU0_IN,Delay Select Value in binary coded form for cfg_emu0_in interface" bitfld.long 0x70 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x70 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x74 "CFG_EMU0_OEN,Delay Select Value in binary coded form for cfg_emu0_oen interface" bitfld.long 0x74 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x74 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x78 "CFG_EMU0_OUT,Delay Select Value in binary coded form for cfg_emu0_out interface" bitfld.long 0x78 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x78 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7C "CFG_EMU1_IN,Delay Select Value in binary coded form for cfg_emu1_in interface" bitfld.long 0x7C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x80 "CFG_EMU1_OEN,Delay Select Value in binary coded form for cfg_emu1_oen interface" bitfld.long 0x80 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x80 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x84 "CFG_EMU1_OUT,Delay Select Value in binary coded form for cfg_emu1_out interface" bitfld.long 0x84 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x84 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x88 "CFG_EMU2_IN,Delay Select Value in binary coded form for cfg_emu2_in interface" bitfld.long 0x88 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x88 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8C "CFG_EMU2_OEN,Delay Select Value in binary coded form for cfg_emu2_oen interface" bitfld.long 0x8C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x90 "CFG_EMU2_OUT,Delay Select Value in binary coded form for cfg_emu2_out interface" bitfld.long 0x90 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x90 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x94 "CFG_EMU3_IN,Delay Select Value in binary coded form for cfg_emu3_in interface" bitfld.long 0x94 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x94 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x98 "CFG_EMU3_OEN,Delay Select Value in binary coded form for cfg_emu3_oen interface" bitfld.long 0x98 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x98 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9C "CFG_EMU3_OUT,Delay Select Value in binary coded form for cfg_emu3_out interface" bitfld.long 0x9C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA0 "CFG_EMU4_IN,Delay Select Value in binary coded form for cfg_emu4_in interface" bitfld.long 0xA0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA4 "CFG_EMU4_OEN,Delay Select Value in binary coded form for cfg_emu4_oen interface" bitfld.long 0xA4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA8 "CFG_EMU4_OUT,Delay Select Value in binary coded form for cfg_emu4_out interface" bitfld.long 0xA8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAC "CFG_GPIO6_10_IN,Delay Select Value in binary coded form for cfg_gpio6_10_in interface" bitfld.long 0xAC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB0 "CFG_GPIO6_10_OEN,Delay Select Value in binary coded form for cfg_gpio6_10_oen interface" bitfld.long 0xB0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB4 "CFG_GPIO6_10_OUT,Delay Select Value in binary coded form for cfg_gpio6_10_out interface" bitfld.long 0xB4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB8 "CFG_GPIO6_11_IN,Delay Select Value in binary coded form for cfg_gpio6_11_in interface" bitfld.long 0xB8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBC "CFG_GPIO6_11_OEN,Delay Select Value in binary coded form for cfg_gpio6_11_oen interface" bitfld.long 0xBC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC0 "CFG_GPIO6_11_OUT,Delay Select Value in binary coded form for cfg_gpio6_11_out interface" bitfld.long 0xC0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC4 "CFG_GPIO6_14_IN,Delay Select Value in binary coded form for cfg_gpio6_14_in interface" bitfld.long 0xC4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC8 "CFG_GPIO6_14_OEN,Delay Select Value in binary coded form for cfg_gpio6_14_oen interface" bitfld.long 0xC8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCC "CFG_GPIO6_14_OUT,Delay Select Value in binary coded form for cfg_gpio6_14_out interface" bitfld.long 0xCC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xD0 "CFG_GPIO6_15_IN,Delay Select Value in binary coded form for cfg_gpio6_15_in interface" bitfld.long 0xD0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xD0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xD4 "CFG_GPIO6_15_OEN,Delay Select Value in binary coded form for cfg_gpio6_15_oen interface" bitfld.long 0xD4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xD4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xD8 "CFG_GPIO6_15_OUT,Delay Select Value in binary coded form for cfg_gpio6_15_out interface" bitfld.long 0xD8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xD8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xD8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xDC "CFG_GPIO6_16_IN,Delay Select Value in binary coded form for cfg_gpio6_16_in interface" bitfld.long 0xDC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xDC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xDC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xE0 "CFG_GPIO6_16_OEN,Delay Select Value in binary coded form for cfg_gpio6_16_oen interface" bitfld.long 0xE0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xE0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xE4 "CFG_GPIO6_16_OUT,Delay Select Value in binary coded form for cfg_gpio6_16_out interface" bitfld.long 0xE4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xE4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xE8 "CFG_GPMC_A0_IN,Delay Select Value in binary coded form for cfg_gpmc_a0_in interface" bitfld.long 0xE8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xE8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xEC "CFG_GPMC_A0_OEN,Delay Select Value in binary coded form for cfg_gpmc_a0_oen interface" bitfld.long 0xEC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xEC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xEC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xF0 "CFG_GPMC_A0_OUT,Delay Select Value in binary coded form for cfg_gpmc_a0_out interface" bitfld.long 0xF0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xF0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xF4 "CFG_GPMC_A10_IN,Delay Select Value in binary coded form for cfg_gpmc_a10_in interface" bitfld.long 0xF4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xF4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xF8 "CFG_GPMC_A10_OEN,Delay Select Value in binary coded form for cfg_gpmc_a10_oen interface" bitfld.long 0xF8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xF8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xFC "CFG_GPMC_A10_OUT,Delay Select Value in binary coded form for cfg_gpmc_a10_out interface" bitfld.long 0xFC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xFC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xFC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x100 "CFG_GPMC_A11_IN,Delay Select Value in binary coded form for cfg_gpmc_a11_in interface" bitfld.long 0x100 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x100 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x100 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x104 "CFG_GPMC_A11_OEN,Delay Select Value in binary coded form for cfg_gpmc_a11_oen interface" bitfld.long 0x104 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x104 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x104 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x108 "CFG_GPMC_A11_OUT,Delay Select Value in binary coded form for cfg_gpmc_a11_out interface" bitfld.long 0x108 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x108 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x108 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x10C "CFG_GPMC_A12_IN,Delay Select Value in binary coded form for cfg_gpmc_a12_in interface" bitfld.long 0x10C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x10C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x110 "CFG_GPMC_A12_OEN,Delay Select Value in binary coded form for cfg_gpmc_a12_oen interface" bitfld.long 0x110 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x110 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x110 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x114 "CFG_GPMC_A12_OUT,Delay Select Value in binary coded form for cfg_gpmc_a12_out interface" bitfld.long 0x114 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x114 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x114 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x118 "CFG_GPMC_A13_IN,Delay Select Value in binary coded form for cfg_gpmc_a13_in interface" bitfld.long 0x118 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x118 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x118 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x11C "CFG_GPMC_A13_OEN,Delay Select Value in binary coded form for cfg_gpmc_a13_oen interface" bitfld.long 0x11C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x11C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x11C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x120 "CFG_GPMC_A13_OUT,Delay Select Value in binary coded form for cfg_gpmc_a13_out interface" bitfld.long 0x120 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x120 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x120 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x124 "CFG_GPMC_A14_IN,Delay Select Value in binary coded form for cfg_gpmc_a14_in interface" bitfld.long 0x124 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x124 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x124 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x128 "CFG_GPMC_A14_OEN,Delay Select Value in binary coded form for cfg_gpmc_a14_oen interface" bitfld.long 0x128 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x128 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x128 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x12C "CFG_GPMC_A14_OUT,Delay Select Value in binary coded form for cfg_gpmc_a14_out interface" bitfld.long 0x12C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x12C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x12C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x130 "CFG_GPMC_A15_IN,Delay Select Value in binary coded form for cfg_gpmc_a15_in interface" bitfld.long 0x130 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x130 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x130 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x134 "CFG_GPMC_A15_OEN,Delay Select Value in binary coded form for cfg_gpmc_a15_oen interface" bitfld.long 0x134 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x134 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x134 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x138 "CFG_GPMC_A15_OUT,Delay Select Value in binary coded form for cfg_gpmc_a15_out interface" bitfld.long 0x138 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x138 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x138 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x13C "CFG_GPMC_A16_IN,Delay Select Value in binary coded form for cfg_gpmc_a16_in interface" bitfld.long 0x13C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x13C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x13C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x140 "CFG_GPMC_A16_OEN,Delay Select Value in binary coded form for cfg_gpmc_a16_oen interface" bitfld.long 0x140 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x140 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x140 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x144 "CFG_GPMC_A16_OUT,Delay Select Value in binary coded form for cfg_gpmc_a16_out interface" bitfld.long 0x144 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x144 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x144 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x148 "CFG_GPMC_A17_IN,Delay Select Value in binary coded form for cfg_gpmc_a17_in interface" bitfld.long 0x148 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x148 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x148 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x14C "CFG_GPMC_A17_OEN,Delay Select Value in binary coded form for cfg_gpmc_a17_oen interface" bitfld.long 0x14C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x14C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x14C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x150 "CFG_GPMC_A17_OUT,Delay Select Value in binary coded form for cfg_gpmc_a17_out interface" bitfld.long 0x150 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x150 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x150 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x154 "CFG_GPMC_A18_IN,Delay Select Value in binary coded form for cfg_gpmc_a18_in interface" bitfld.long 0x154 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x154 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x154 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x158 "CFG_GPMC_A18_OEN,Delay Select Value in binary coded form for cfg_gpmc_a18_oen interface" bitfld.long 0x158 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x158 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x158 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x15C "CFG_GPMC_A18_OUT,Delay Select Value in binary coded form for cfg_gpmc_a18_out interface" bitfld.long 0x15C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x15C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x15C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x160 "CFG_GPMC_A19_IN,Delay Select Value in binary coded form for cfg_gpmc_a19_in interface" bitfld.long 0x160 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x160 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x160 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x164 "CFG_GPMC_A19_OEN,Delay Select Value in binary coded form for cfg_gpmc_a19_oen interface" bitfld.long 0x164 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x164 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x164 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x168 "CFG_GPMC_A19_OUT,Delay Select Value in binary coded form for cfg_gpmc_a19_out interface" bitfld.long 0x168 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x168 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x168 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x16C "CFG_GPMC_A1_IN,Delay Select Value in binary coded form for cfg_gpmc_a1_in interface" bitfld.long 0x16C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x16C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x16C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x170 "CFG_GPMC_A1_OEN,Delay Select Value in binary coded form for cfg_gpmc_a1_oen interface" bitfld.long 0x170 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x170 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x170 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x174 "CFG_GPMC_A1_OUT,Delay Select Value in binary coded form for cfg_gpmc_a1_out interface" bitfld.long 0x174 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x174 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x174 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x178 "CFG_GPMC_A20_IN,Delay Select Value in binary coded form for cfg_gpmc_a20_in interface" bitfld.long 0x178 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x178 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x178 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x17C "CFG_GPMC_A20_OEN,Delay Select Value in binary coded form for cfg_gpmc_a20_oen interface" bitfld.long 0x17C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x17C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x17C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x180 "CFG_GPMC_A20_OUT,Delay Select Value in binary coded form for cfg_gpmc_a20_out interface" bitfld.long 0x180 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x180 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x180 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x184 "CFG_GPMC_A21_IN,Delay Select Value in binary coded form for cfg_gpmc_a21_in interface" bitfld.long 0x184 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x184 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x184 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x188 "CFG_GPMC_A21_OEN,Delay Select Value in binary coded form for cfg_gpmc_a21_oen interface" bitfld.long 0x188 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x188 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x188 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x18C "CFG_GPMC_A21_OUT,Delay Select Value in binary coded form for cfg_gpmc_a21_out interface" bitfld.long 0x18C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x18C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x18C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x190 "CFG_GPMC_A22_IN,Delay Select Value in binary coded form for cfg_gpmc_a22_in interface" bitfld.long 0x190 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x190 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x190 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x194 "CFG_GPMC_A22_OEN,Delay Select Value in binary coded form for cfg_gpmc_a22_oen interface" bitfld.long 0x194 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x194 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x194 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x198 "CFG_GPMC_A22_OUT,Delay Select Value in binary coded form for cfg_gpmc_a22_out interface" bitfld.long 0x198 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x198 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x198 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x19C "CFG_GPMC_A23_IN,Delay Select Value in binary coded form for cfg_gpmc_a23_in interface" bitfld.long 0x19C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x19C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x19C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1A0 "CFG_GPMC_A23_OEN,Delay Select Value in binary coded form for cfg_gpmc_a23_oen interface" bitfld.long 0x1A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1A4 "CFG_GPMC_A23_OUT,Delay Select Value in binary coded form for cfg_gpmc_a23_out interface" bitfld.long 0x1A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1A8 "CFG_GPMC_A24_IN,Delay Select Value in binary coded form for cfg_gpmc_a24_in interface" bitfld.long 0x1A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1AC "CFG_GPMC_A24_OEN,Delay Select Value in binary coded form for cfg_gpmc_a24_oen interface" bitfld.long 0x1AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1B0 "CFG_GPMC_A24_OUT,Delay Select Value in binary coded form for cfg_gpmc_a24_out interface" bitfld.long 0x1B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1B4 "CFG_GPMC_A25_IN,Delay Select Value in binary coded form for cfg_gpmc_a25_in interface" bitfld.long 0x1B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1B8 "CFG_GPMC_A25_OEN,Delay Select Value in binary coded form for cfg_gpmc_a25_oen interface" bitfld.long 0x1B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1BC "CFG_GPMC_A25_OUT,Delay Select Value in binary coded form for cfg_gpmc_a25_out interface" bitfld.long 0x1BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1C0 "CFG_GPMC_A26_IN,Delay Select Value in binary coded form for cfg_gpmc_a26_in interface" bitfld.long 0x1C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1C4 "CFG_GPMC_A26_OEN,Delay Select Value in binary coded form for cfg_gpmc_a26_oen interface" bitfld.long 0x1C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1C8 "CFG_GPMC_A26_OUT,Delay Select Value in binary coded form for cfg_gpmc_a26_out interface" bitfld.long 0x1C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1CC "CFG_GPMC_A27_IN,Delay Select Value in binary coded form for cfg_gpmc_a27_in interface" bitfld.long 0x1CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1D0 "CFG_GPMC_A27_OEN,Delay Select Value in binary coded form for cfg_gpmc_a27_oen interface" bitfld.long 0x1D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1D4 "CFG_GPMC_A27_OUT,Delay Select Value in binary coded form for cfg_gpmc_a27_out interface" bitfld.long 0x1D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1D8 "CFG_GPMC_A2_IN,Delay Select Value in binary coded form for cfg_gpmc_a2_in interface" bitfld.long 0x1D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1DC "CFG_GPMC_A2_OEN,Delay Select Value in binary coded form for cfg_gpmc_a2_oen interface" bitfld.long 0x1DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1E0 "CFG_GPMC_A2_OUT,Delay Select Value in binary coded form for cfg_gpmc_a2_out interface" bitfld.long 0x1E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1E4 "CFG_GPMC_A3_IN,Delay Select Value in binary coded form for cfg_gpmc_a3_in interface" bitfld.long 0x1E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1E8 "CFG_GPMC_A3_OEN,Delay Select Value in binary coded form for cfg_gpmc_a3_oen interface" bitfld.long 0x1E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1EC "CFG_GPMC_A3_OUT,Delay Select Value in binary coded form for cfg_gpmc_a3_out interface" bitfld.long 0x1EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1F0 "CFG_GPMC_A4_IN,Delay Select Value in binary coded form for cfg_gpmc_a4_in interface" bitfld.long 0x1F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1F4 "CFG_GPMC_A4_OEN,Delay Select Value in binary coded form for cfg_gpmc_a4_oen interface" bitfld.long 0x1F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1F8 "CFG_GPMC_A4_OUT,Delay Select Value in binary coded form for cfg_gpmc_a4_out interface" bitfld.long 0x1F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x1FC "CFG_GPMC_A5_IN,Delay Select Value in binary coded form for cfg_gpmc_a5_in interface" bitfld.long 0x1FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x1FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x1FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x200 "CFG_GPMC_A5_OEN,Delay Select Value in binary coded form for cfg_gpmc_a5_oen interface" bitfld.long 0x200 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x200 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x200 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x204 "CFG_GPMC_A5_OUT,Delay Select Value in binary coded form for cfg_gpmc_a5_out interface" bitfld.long 0x204 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x204 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x204 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x208 "CFG_GPMC_A6_IN,Delay Select Value in binary coded form for cfg_gpmc_a6_in interface" bitfld.long 0x208 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x208 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x208 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x20C "CFG_GPMC_A6_OEN,Delay Select Value in binary coded form for cfg_gpmc_a6_oen interface" bitfld.long 0x20C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x20C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x210 "CFG_GPMC_A6_OUT,Delay Select Value in binary coded form for cfg_gpmc_a6_out interface" bitfld.long 0x210 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x210 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x210 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x214 "CFG_GPMC_A7_IN,Delay Select Value in binary coded form for cfg_gpmc_a7_in interface" bitfld.long 0x214 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x214 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x214 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x218 "CFG_GPMC_A7_OEN,Delay Select Value in binary coded form for cfg_gpmc_a7_oen interface" bitfld.long 0x218 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x218 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x218 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x21C "CFG_GPMC_A7_OUT,Delay Select Value in binary coded form for cfg_gpmc_a7_out interface" bitfld.long 0x21C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x21C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x21C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x220 "CFG_GPMC_A8_IN,Delay Select Value in binary coded form for cfg_gpmc_a8_in interface" bitfld.long 0x220 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x220 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x220 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x224 "CFG_GPMC_A8_OEN,Delay Select Value in binary coded form for cfg_gpmc_a8_oen interface" bitfld.long 0x224 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x224 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x224 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x228 "CFG_GPMC_A8_OUT,Delay Select Value in binary coded form for cfg_gpmc_a8_out interface" bitfld.long 0x228 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x228 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x228 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x22C "CFG_GPMC_A9_IN,Delay Select Value in binary coded form for cfg_gpmc_a9_in interface" bitfld.long 0x22C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x22C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x22C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x230 "CFG_GPMC_A9_OEN,Delay Select Value in binary coded form for cfg_gpmc_a9_oen interface" bitfld.long 0x230 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x230 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x230 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x234 "CFG_GPMC_A9_OUT,Delay Select Value in binary coded form for cfg_gpmc_a9_out interface" bitfld.long 0x234 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x234 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x234 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x238 "CFG_GPMC_AD0_IN,Delay Select Value in binary coded form for cfg_gpmc_ad0_in interface" bitfld.long 0x238 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x238 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x238 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x23C "CFG_GPMC_AD0_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad0_oen interface" bitfld.long 0x23C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x23C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x23C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x240 "CFG_GPMC_AD0_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad0_out interface" bitfld.long 0x240 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x240 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x240 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x244 "CFG_GPMC_AD10_IN,Delay Select Value in binary coded form for cfg_gpmc_ad10_in interface" bitfld.long 0x244 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x244 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x244 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x248 "CFG_GPMC_AD10_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad10_oen interface" bitfld.long 0x248 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x248 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x248 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x24C "CFG_GPMC_AD10_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad10_out interface" bitfld.long 0x24C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x24C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x24C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x250 "CFG_GPMC_AD11_IN,Delay Select Value in binary coded form for cfg_gpmc_ad11_in interface" bitfld.long 0x250 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x250 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x250 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x254 "CFG_GPMC_AD11_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad11_oen interface" bitfld.long 0x254 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x254 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x254 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x258 "CFG_GPMC_AD11_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad11_out interface" bitfld.long 0x258 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x258 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x258 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x25C "CFG_GPMC_AD12_IN,Delay Select Value in binary coded form for cfg_gpmc_ad12_in interface" bitfld.long 0x25C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x25C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x25C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x260 "CFG_GPMC_AD12_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad12_oen interface" bitfld.long 0x260 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x260 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x260 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x264 "CFG_GPMC_AD12_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad12_out interface" bitfld.long 0x264 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x264 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x264 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x268 "CFG_GPMC_AD13_IN,Delay Select Value in binary coded form for cfg_gpmc_ad13_in interface" bitfld.long 0x268 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x268 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x268 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x26C "CFG_GPMC_AD13_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad13_oen interface" bitfld.long 0x26C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x26C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x26C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x270 "CFG_GPMC_AD13_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad13_out interface" bitfld.long 0x270 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x270 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x270 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x274 "CFG_GPMC_AD14_IN,Delay Select Value in binary coded form for cfg_gpmc_ad14_in interface" bitfld.long 0x274 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x274 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x274 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x278 "CFG_GPMC_AD14_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad14_oen interface" bitfld.long 0x278 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x278 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x278 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x27C "CFG_GPMC_AD14_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad14_out interface" bitfld.long 0x27C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x27C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x27C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x280 "CFG_GPMC_AD15_IN,Delay Select Value in binary coded form for cfg_gpmc_ad15_in interface" bitfld.long 0x280 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x280 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x280 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x284 "CFG_GPMC_AD15_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad15_oen interface" bitfld.long 0x284 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x284 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x284 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x288 "CFG_GPMC_AD15_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad15_out interface" bitfld.long 0x288 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x288 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x288 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x28C "CFG_GPMC_AD1_IN,Delay Select Value in binary coded form for cfg_gpmc_ad1_in interface" bitfld.long 0x28C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x28C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x28C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x290 "CFG_GPMC_AD1_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad1_oen interface" bitfld.long 0x290 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x290 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x290 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x294 "CFG_GPMC_AD1_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad1_out interface" bitfld.long 0x294 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x294 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x294 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x298 "CFG_GPMC_AD2_IN,Delay Select Value in binary coded form for cfg_gpmc_ad2_in interface" bitfld.long 0x298 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x298 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x298 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x29C "CFG_GPMC_AD2_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad2_oen interface" bitfld.long 0x29C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x29C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x29C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2A0 "CFG_GPMC_AD2_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad2_out interface" bitfld.long 0x2A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2A4 "CFG_GPMC_AD3_IN,Delay Select Value in binary coded form for cfg_gpmc_ad3_in interface" bitfld.long 0x2A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2A8 "CFG_GPMC_AD3_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad3_oen interface" bitfld.long 0x2A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2AC "CFG_GPMC_AD3_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad3_out interface" bitfld.long 0x2AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2B0 "CFG_GPMC_AD4_IN,Delay Select Value in binary coded form for cfg_gpmc_ad4_in interface" bitfld.long 0x2B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2B4 "CFG_GPMC_AD4_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad4_oen interface" bitfld.long 0x2B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2B8 "CFG_GPMC_AD4_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad4_out interface" bitfld.long 0x2B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2BC "CFG_GPMC_AD5_IN,Delay Select Value in binary coded form for cfg_gpmc_ad5_in interface" bitfld.long 0x2BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2C0 "CFG_GPMC_AD5_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad5_oen interface" bitfld.long 0x2C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2C4 "CFG_GPMC_AD5_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad5_out interface" bitfld.long 0x2C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2C8 "CFG_GPMC_AD6_IN,Delay Select Value in binary coded form for cfg_gpmc_ad6_in interface" bitfld.long 0x2C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2CC "CFG_GPMC_AD6_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad6_oen interface" bitfld.long 0x2CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2D0 "CFG_GPMC_AD6_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad6_out interface" bitfld.long 0x2D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2D4 "CFG_GPMC_AD7_IN,Delay Select Value in binary coded form for cfg_gpmc_ad7_in interface" bitfld.long 0x2D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2D8 "CFG_GPMC_AD7_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad7_oen interface" bitfld.long 0x2D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2DC "CFG_GPMC_AD7_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad7_out interface" bitfld.long 0x2DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2E0 "CFG_GPMC_AD8_IN,Delay Select Value in binary coded form for cfg_gpmc_ad8_in interface" bitfld.long 0x2E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2E4 "CFG_GPMC_AD8_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad8_oen interface" bitfld.long 0x2E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2E8 "CFG_GPMC_AD8_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad8_out interface" bitfld.long 0x2E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2EC "CFG_GPMC_AD9_IN,Delay Select Value in binary coded form for cfg_gpmc_ad9_in interface" bitfld.long 0x2EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2F0 "CFG_GPMC_AD9_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad9_oen interface" bitfld.long 0x2F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2F4 "CFG_GPMC_AD9_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad9_out interface" bitfld.long 0x2F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2F8 "CFG_GPMC_ADVN_ALE_IN,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_in interface" bitfld.long 0x2F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x2FC "CFG_GPMC_ADVN_ALE_OEN,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_oen interface" bitfld.long 0x2FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x2FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x2FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x300 "CFG_GPMC_ADVN_ALE_OUT,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_out interface" bitfld.long 0x300 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x300 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x300 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x304 "CFG_GPMC_BEN0_IN,Delay Select Value in binary coded form for cfg_gpmc_ben0_in interface" bitfld.long 0x304 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x304 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x304 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x308 "CFG_GPMC_BEN0_OEN,Delay Select Value in binary coded form for cfg_gpmc_ben0_oen interface" bitfld.long 0x308 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x308 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x308 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x30C "CFG_GPMC_BEN0_OUT,Delay Select Value in binary coded form for cfg_gpmc_ben0_out interface" bitfld.long 0x30C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x30C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x30C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x310 "CFG_GPMC_BEN1_IN,Delay Select Value in binary coded form for cfg_gpmc_ben1_in interface" bitfld.long 0x310 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x310 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x310 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x314 "CFG_GPMC_BEN1_OEN,Delay Select Value in binary coded form for cfg_gpmc_ben1_oen interface" bitfld.long 0x314 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x314 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x314 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x318 "CFG_GPMC_BEN1_OUT,Delay Select Value in binary coded form for cfg_gpmc_ben1_out interface" bitfld.long 0x318 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x318 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x318 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x31C "CFG_GPMC_CLK_IN,Delay Select Value in binary coded form for cfg_gpmc_clk_in interface" bitfld.long 0x31C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x31C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x31C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x320 "CFG_GPMC_CLK_OEN,Delay Select Value in binary coded form for cfg_gpmc_clk_oen interface" bitfld.long 0x320 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x320 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x320 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x324 "CFG_GPMC_CLK_OUT,Delay Select Value in binary coded form for cfg_gpmc_clk_out interface" bitfld.long 0x324 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x324 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x324 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x328 "CFG_GPMC_CS0_IN,Delay Select Value in binary coded form for cfg_gpmc_cs0_in interface" bitfld.long 0x328 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x328 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x328 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x32C "CFG_GPMC_CS0_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs0_oen interface" bitfld.long 0x32C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x32C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x32C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x330 "CFG_GPMC_CS0_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs0_out interface" bitfld.long 0x330 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x330 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x330 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x334 "CFG_GPMC_CS1_IN,Delay Select Value in binary coded form for cfg_gpmc_cs1_in interface" bitfld.long 0x334 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x334 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x334 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x338 "CFG_GPMC_CS1_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs1_oen interface" bitfld.long 0x338 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x338 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x338 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x33C "CFG_GPMC_CS1_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs1_out interface" bitfld.long 0x33C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x33C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x33C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x340 "CFG_GPMC_CS2_IN,Delay Select Value in binary coded form for cfg_gpmc_cs2_in interface" bitfld.long 0x340 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x340 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x340 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x344 "CFG_GPMC_CS2_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs2_oen interface" bitfld.long 0x344 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x344 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x344 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x348 "CFG_GPMC_CS2_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs2_out interface" bitfld.long 0x348 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x348 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x348 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x34C "CFG_GPMC_CS3_IN,Delay Select Value in binary coded form for cfg_gpmc_cs3_in interface" bitfld.long 0x34C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x34C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x34C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x350 "CFG_GPMC_CS3_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs3_oen interface" bitfld.long 0x350 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x350 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x350 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x354 "CFG_GPMC_CS3_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs3_out interface" bitfld.long 0x354 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x354 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x354 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x358 "CFG_GPMC_OEN_REN_IN,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_in interface" bitfld.long 0x358 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x358 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x358 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x35C "CFG_GPMC_OEN_REN_OEN,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_oen interface" bitfld.long 0x35C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x35C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x35C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x360 "CFG_GPMC_OEN_REN_OUT,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_out interface" bitfld.long 0x360 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x360 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x360 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x364 "CFG_GPMC_WAIT0_IN,Delay Select Value in binary coded form for cfg_gpmc_wait0_in interface" bitfld.long 0x364 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x364 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x364 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x368 "CFG_GPMC_WAIT0_OEN,Delay Select Value in binary coded form for cfg_gpmc_wait0_oen interface" bitfld.long 0x368 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x368 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x368 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x36C "CFG_GPMC_WAIT0_OUT,Delay Select Value in binary coded form for cfg_gpmc_wait0_out interface" bitfld.long 0x36C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x36C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x36C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x370 "CFG_GPMC_WEN_IN,Delay Select Value in binary coded form for cfg_gpmc_wen_in interface" bitfld.long 0x370 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x370 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x370 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x374 "CFG_GPMC_WEN_OEN,Delay Select Value in binary coded form for cfg_gpmc_wen_oen interface" bitfld.long 0x374 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x374 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x374 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x378 "CFG_GPMC_WEN_OUT,Delay Select Value in binary coded form for cfg_gpmc_wen_out interface" bitfld.long 0x378 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x378 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x378 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x37C "CFG_MCASP1_ACLKR_IN,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_in interface" bitfld.long 0x37C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x37C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x37C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x380 "CFG_MCASP1_ACLKR_OEN,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_oen interface" bitfld.long 0x380 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x380 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x380 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x384 "CFG_MCASP1_ACLKR_OUT,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_out interface" bitfld.long 0x384 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x384 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x384 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x388 "CFG_MCASP1_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_in interface" bitfld.long 0x388 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x388 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x388 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x38C "CFG_MCASP1_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_oen interface" bitfld.long 0x38C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x38C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x38C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x390 "CFG_MCASP1_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_out interface" bitfld.long 0x390 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x390 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x390 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x394 "CFG_MCASP1_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr0_in interface" bitfld.long 0x394 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x394 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x394 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x398 "CFG_MCASP1_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr0_oen interface" bitfld.long 0x398 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x398 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x398 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x39C "CFG_MCASP1_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr0_out interface" bitfld.long 0x39C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x39C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x39C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3A0 "CFG_MCASP1_AXR10_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr10_in interface" bitfld.long 0x3A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3A4 "CFG_MCASP1_AXR10_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr10_oen interface" bitfld.long 0x3A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3A8 "CFG_MCASP1_AXR10_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr10_out interface" bitfld.long 0x3A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3AC "CFG_MCASP1_AXR11_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr11_in interface" bitfld.long 0x3AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3B0 "CFG_MCASP1_AXR11_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr11_oen interface" bitfld.long 0x3B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3B4 "CFG_MCASP1_AXR11_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr11_out interface" bitfld.long 0x3B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3B8 "CFG_MCASP1_AXR12_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr12_in interface" bitfld.long 0x3B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3BC "CFG_MCASP1_AXR12_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr12_oen interface" bitfld.long 0x3BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3C0 "CFG_MCASP1_AXR12_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr12_out interface" bitfld.long 0x3C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3C4 "CFG_MCASP1_AXR13_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr13_in interface" bitfld.long 0x3C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3C8 "CFG_MCASP1_AXR13_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr13_oen interface" bitfld.long 0x3C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3CC "CFG_MCASP1_AXR13_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr13_out interface" bitfld.long 0x3CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3D0 "CFG_MCASP1_AXR14_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr14_in interface" bitfld.long 0x3D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3D4 "CFG_MCASP1_AXR14_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr14_oen interface" bitfld.long 0x3D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3D8 "CFG_MCASP1_AXR14_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr14_out interface" bitfld.long 0x3D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3DC "CFG_MCASP1_AXR15_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr15_in interface" bitfld.long 0x3DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3E0 "CFG_MCASP1_AXR15_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr15_oen interface" bitfld.long 0x3E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3E4 "CFG_MCASP1_AXR15_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr15_out interface" bitfld.long 0x3E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3E8 "CFG_MCASP1_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr1_in interface" bitfld.long 0x3E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3EC "CFG_MCASP1_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr1_oen interface" bitfld.long 0x3EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3F0 "CFG_MCASP1_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr1_out interface" bitfld.long 0x3F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3F4 "CFG_MCASP1_AXR2_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr2_in interface" bitfld.long 0x3F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3F8 "CFG_MCASP1_AXR2_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr2_oen interface" bitfld.long 0x3F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x3FC "CFG_MCASP1_AXR2_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr2_out interface" bitfld.long 0x3FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x3FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x3FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x400 "CFG_MCASP1_AXR3_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr3_in interface" bitfld.long 0x400 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x400 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x400 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x404 "CFG_MCASP1_AXR3_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr3_oen interface" bitfld.long 0x404 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x404 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x404 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x408 "CFG_MCASP1_AXR3_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr3_out interface" bitfld.long 0x408 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x408 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x408 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x40C "CFG_MCASP1_AXR4_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr4_in interface" bitfld.long 0x40C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x40C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x40C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x410 "CFG_MCASP1_AXR4_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr4_oen interface" bitfld.long 0x410 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x410 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x410 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x414 "CFG_MCASP1_AXR4_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr4_out interface" bitfld.long 0x414 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x414 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x414 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x418 "CFG_MCASP1_AXR5_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr5_in interface" bitfld.long 0x418 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x418 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x418 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x41C "CFG_MCASP1_AXR5_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr5_oen interface" bitfld.long 0x41C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x41C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x41C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x420 "CFG_MCASP1_AXR5_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr5_out interface" bitfld.long 0x420 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x420 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x420 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x424 "CFG_MCASP1_AXR6_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr6_in interface" bitfld.long 0x424 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x424 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x424 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x428 "CFG_MCASP1_AXR6_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr6_oen interface" bitfld.long 0x428 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x428 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x428 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x42C "CFG_MCASP1_AXR6_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr6_out interface" bitfld.long 0x42C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x42C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x42C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x430 "CFG_MCASP1_AXR7_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr7_in interface" bitfld.long 0x430 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x430 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x430 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x434 "CFG_MCASP1_AXR7_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr7_oen interface" bitfld.long 0x434 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x434 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x434 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x438 "CFG_MCASP1_AXR7_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr7_out interface" bitfld.long 0x438 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x438 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x438 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x43C "CFG_MCASP1_AXR8_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr8_in interface" bitfld.long 0x43C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x43C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x43C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x440 "CFG_MCASP1_AXR8_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr8_oen interface" bitfld.long 0x440 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x440 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x440 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x444 "CFG_MCASP1_AXR8_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr8_out interface" bitfld.long 0x444 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x444 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x444 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x448 "CFG_MCASP1_AXR9_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr9_in interface" bitfld.long 0x448 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x448 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x448 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x44C "CFG_MCASP1_AXR9_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr9_oen interface" bitfld.long 0x44C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x44C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x44C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x450 "CFG_MCASP1_AXR9_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr9_out interface" bitfld.long 0x450 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x450 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x450 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x454 "CFG_MCASP1_FSR_IN,Delay Select Value in binary coded form for cfg_mcasp1_fsr_in interface" bitfld.long 0x454 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x454 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x454 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x458 "CFG_MCASP1_FSR_OEN,Delay Select Value in binary coded form for cfg_mcasp1_fsr_oen interface" bitfld.long 0x458 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x458 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x458 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x45C "CFG_MCASP1_FSR_OUT,Delay Select Value in binary coded form for cfg_mcasp1_fsr_out interface" bitfld.long 0x45C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x45C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x45C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x460 "CFG_MCASP1_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp1_fsx_in interface" bitfld.long 0x460 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x460 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x460 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x464 "CFG_MCASP1_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp1_fsx_oen interface" bitfld.long 0x464 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x464 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x464 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x468 "CFG_MCASP1_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp1_fsx_out interface" bitfld.long 0x468 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x468 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x468 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x46C "CFG_MCASP2_ACLKR_IN,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_in interface" bitfld.long 0x46C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x46C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x46C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x470 "CFG_MCASP2_ACLKR_OEN,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_oen interface" bitfld.long 0x470 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x470 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x470 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x474 "CFG_MCASP2_ACLKR_OUT,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_out interface" bitfld.long 0x474 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x474 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x474 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x478 "CFG_MCASP2_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_in interface" bitfld.long 0x478 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x478 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x478 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x47C "CFG_MCASP2_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_oen interface" bitfld.long 0x47C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x47C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x47C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x480 "CFG_MCASP2_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_out interface" bitfld.long 0x480 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x480 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x480 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x484 "CFG_MCASP2_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr0_in interface" bitfld.long 0x484 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x484 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x484 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x488 "CFG_MCASP2_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr0_oen interface" bitfld.long 0x488 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x488 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x488 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x48C "CFG_MCASP2_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr0_out interface" bitfld.long 0x48C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x48C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x48C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x490 "CFG_MCASP2_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr1_in interface" bitfld.long 0x490 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x490 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x490 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x494 "CFG_MCASP2_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr1_oen interface" bitfld.long 0x494 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x494 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x494 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x498 "CFG_MCASP2_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr1_out interface" bitfld.long 0x498 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x498 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x498 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x49C "CFG_MCASP2_AXR2_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr2_in interface" bitfld.long 0x49C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x49C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x49C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4A0 "CFG_MCASP2_AXR2_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr2_oen interface" bitfld.long 0x4A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4A4 "CFG_MCASP2_AXR2_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr2_out interface" bitfld.long 0x4A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4A8 "CFG_MCASP2_AXR3_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr3_in interface" bitfld.long 0x4A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4AC "CFG_MCASP2_AXR3_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr3_oen interface" bitfld.long 0x4AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4B0 "CFG_MCASP2_AXR3_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr3_out interface" bitfld.long 0x4B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4B4 "CFG_MCASP2_AXR4_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr4_in interface" bitfld.long 0x4B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4B8 "CFG_MCASP2_AXR4_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr4_oen interface" bitfld.long 0x4B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4BC "CFG_MCASP2_AXR4_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr4_out interface" bitfld.long 0x4BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4C0 "CFG_MCASP2_AXR5_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr5_in interface" bitfld.long 0x4C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4C4 "CFG_MCASP2_AXR5_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr5_oen interface" bitfld.long 0x4C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4C8 "CFG_MCASP2_AXR5_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr5_out interface" bitfld.long 0x4C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4CC "CFG_MCASP2_AXR6_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr6_in interface" bitfld.long 0x4CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4D0 "CFG_MCASP2_AXR6_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr6_oen interface" bitfld.long 0x4D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4D4 "CFG_MCASP2_AXR6_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr6_out interface" bitfld.long 0x4D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4D8 "CFG_MCASP2_AXR7_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr7_in interface" bitfld.long 0x4D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4DC "CFG_MCASP2_AXR7_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr7_oen interface" bitfld.long 0x4DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4E0 "CFG_MCASP2_AXR7_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr7_out interface" bitfld.long 0x4E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4E4 "CFG_MCASP2_FSR_IN,Delay Select Value in binary coded form for cfg_mcasp2_fsr_in interface" bitfld.long 0x4E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4E8 "CFG_MCASP2_FSR_OEN,Delay Select Value in binary coded form for cfg_mcasp2_fsr_oen interface" bitfld.long 0x4E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4EC "CFG_MCASP2_FSR_OUT,Delay Select Value in binary coded form for cfg_mcasp2_fsr_out interface" bitfld.long 0x4EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4F0 "CFG_MCASP2_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp2_fsx_in interface" bitfld.long 0x4F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4F4 "CFG_MCASP2_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp2_fsx_oen interface" bitfld.long 0x4F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4F8 "CFG_MCASP2_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp2_fsx_out interface" bitfld.long 0x4F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x4FC "CFG_MCASP3_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_in interface" bitfld.long 0x4FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x4FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x500 "CFG_MCASP3_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_oen interface" bitfld.long 0x500 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x500 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x500 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x504 "CFG_MCASP3_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_out interface" bitfld.long 0x504 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x504 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x504 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x508 "CFG_MCASP3_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp3_axr0_in interface" bitfld.long 0x508 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x508 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x508 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x50C "CFG_MCASP3_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp3_axr0_oen interface" bitfld.long 0x50C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x50C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x510 "CFG_MCASP3_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp3_axr0_out interface" bitfld.long 0x510 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x510 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x510 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x514 "CFG_MCASP3_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp3_axr1_in interface" bitfld.long 0x514 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x514 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x514 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x518 "CFG_MCASP3_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp3_axr1_oen interface" bitfld.long 0x518 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x518 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x518 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x51C "CFG_MCASP3_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp3_axr1_out interface" bitfld.long 0x51C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x51C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x51C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x520 "CFG_MCASP3_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp3_fsx_in interface" bitfld.long 0x520 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x520 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x520 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x524 "CFG_MCASP3_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp3_fsx_oen interface" bitfld.long 0x524 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x524 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x524 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x528 "CFG_MCASP3_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp3_fsx_out interface" bitfld.long 0x528 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x528 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x528 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x52C "CFG_MCASP4_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_in interface" bitfld.long 0x52C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x52C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x52C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x530 "CFG_MCASP4_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_oen interface" bitfld.long 0x530 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x530 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x530 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x534 "CFG_MCASP4_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_out interface" bitfld.long 0x534 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x534 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x534 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x538 "CFG_MCASP4_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp4_axr0_in interface" bitfld.long 0x538 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x538 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x538 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x53C "CFG_MCASP4_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp4_axr0_oen interface" bitfld.long 0x53C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x53C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x53C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x540 "CFG_MCASP4_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp4_axr0_out interface" bitfld.long 0x540 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x540 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x540 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x544 "CFG_MCASP4_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp4_axr1_in interface" bitfld.long 0x544 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x544 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x544 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x548 "CFG_MCASP4_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp4_axr1_oen interface" bitfld.long 0x548 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x548 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x548 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x54C "CFG_MCASP4_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp4_axr1_out interface" bitfld.long 0x54C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x54C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x54C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x550 "CFG_MCASP4_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp4_fsx_in interface" bitfld.long 0x550 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x550 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x550 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x554 "CFG_MCASP4_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp4_fsx_oen interface" bitfld.long 0x554 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x554 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x554 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x558 "CFG_MCASP4_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp4_fsx_out interface" bitfld.long 0x558 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x558 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x558 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x55C "CFG_MCASP5_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_in interface" bitfld.long 0x55C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x55C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x55C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x560 "CFG_MCASP5_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_oen interface" bitfld.long 0x560 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x560 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x560 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x564 "CFG_MCASP5_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_out interface" bitfld.long 0x564 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x564 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x564 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x568 "CFG_MCASP5_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp5_axr0_in interface" bitfld.long 0x568 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x568 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x568 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x56C "CFG_MCASP5_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp5_axr0_oen interface" bitfld.long 0x56C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x56C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x56C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x570 "CFG_MCASP5_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp5_axr0_out interface" bitfld.long 0x570 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x570 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x570 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x574 "CFG_MCASP5_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp5_axr1_in interface" bitfld.long 0x574 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x574 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x574 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x578 "CFG_MCASP5_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp5_axr1_oen interface" bitfld.long 0x578 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x578 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x578 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x57C "CFG_MCASP5_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp5_axr1_out interface" bitfld.long 0x57C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x57C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x57C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x580 "CFG_MCASP5_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp5_fsx_in interface" bitfld.long 0x580 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x580 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x580 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x584 "CFG_MCASP5_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp5_fsx_oen interface" bitfld.long 0x584 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x584 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x584 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x588 "CFG_MCASP5_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp5_fsx_out interface" bitfld.long 0x588 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x588 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x588 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x58C "CFG_MDIO_D_IN,Delay Select Value in binary coded form for cfg_mdio_d_in interface" bitfld.long 0x58C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x58C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x58C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x590 "CFG_MDIO_D_OEN,Delay Select Value in binary coded form for cfg_mdio_d_oen interface" bitfld.long 0x590 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x590 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x590 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x594 "CFG_MDIO_D_OUT,Delay Select Value in binary coded form for cfg_mdio_d_out interface" bitfld.long 0x594 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x594 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x594 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x598 "CFG_MDIO_MCLK_IN,Delay Select Value in binary coded form for cfg_mdio_mclk_in interface" bitfld.long 0x598 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x598 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x598 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x59C "CFG_MDIO_MCLK_OEN,Delay Select Value in binary coded form for cfg_mdio_mclk_oen interface" bitfld.long 0x59C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x59C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x59C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5A0 "CFG_MDIO_MCLK_OUT,Delay Select Value in binary coded form for cfg_mdio_mclk_out interface" bitfld.long 0x5A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5A4 "CFG_MLBP_CLK_N_IN,Delay Select Value in binary coded form for cfg_mlbp_clk_n_in interface" bitfld.long 0x5A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5A8 "CFG_MLBP_CLK_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_clk_n_oen interface" bitfld.long 0x5A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5AC "CFG_MLBP_CLK_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_clk_n_out interface" bitfld.long 0x5AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5B0 "CFG_MLBP_CLK_P_IN,Delay Select Value in binary coded form for cfg_mlbp_clk_p_in interface" bitfld.long 0x5B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5B4 "CFG_MLBP_CLK_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_clk_p_oen interface" bitfld.long 0x5B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5B8 "CFG_MLBP_CLK_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_clk_p_out interface" bitfld.long 0x5B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5BC "CFG_MLBP_DAT_N_IN,Delay Select Value in binary coded form for cfg_mlbp_dat_n_in interface" bitfld.long 0x5BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5C0 "CFG_MLBP_DAT_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_dat_n_oen interface" bitfld.long 0x5C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5C4 "CFG_MLBP_DAT_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_dat_n_out interface" bitfld.long 0x5C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5C8 "CFG_MLBP_DAT_P_IN,Delay Select Value in binary coded form for cfg_mlbp_dat_p_in interface" bitfld.long 0x5C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5CC "CFG_MLBP_DAT_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_dat_p_oen interface" bitfld.long 0x5CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5D0 "CFG_MLBP_DAT_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_dat_p_out interface" bitfld.long 0x5D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5D4 "CFG_MLBP_SIG_N_IN,Delay Select Value in binary coded form for cfg_mlbp_sig_n_in interface" bitfld.long 0x5D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5D8 "CFG_MLBP_SIG_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_sig_n_oen interface" bitfld.long 0x5D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5DC "CFG_MLBP_SIG_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_sig_n_out interface" bitfld.long 0x5DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5E0 "CFG_MLBP_SIG_P_IN,Delay Select Value in binary coded form for cfg_mlbp_sig_p_in interface" bitfld.long 0x5E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5E4 "CFG_MLBP_SIG_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_sig_p_oen interface" bitfld.long 0x5E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5E8 "CFG_MLBP_SIG_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_sig_p_out interface" bitfld.long 0x5E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5EC "CFG_MMC1_CLK_IN,Delay Select Value in binary coded form for cfg_mmc1_clk_in interface" bitfld.long 0x5EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5F0 "CFG_MMC1_CLK_OEN,Delay Select Value in binary coded form for cfg_mmc1_clk_oen interface" bitfld.long 0x5F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5F4 "CFG_MMC1_CLK_OUT,Delay Select Value in binary coded form for cfg_mmc1_clk_out interface" bitfld.long 0x5F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5F8 "CFG_MMC1_CMD_IN,Delay Select Value in binary coded form for cfg_mmc1_cmd_in interface" bitfld.long 0x5F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x5FC "CFG_MMC1_CMD_OEN,Delay Select Value in binary coded form for cfg_mmc1_cmd_oen interface" bitfld.long 0x5FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x5FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x5FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x600 "CFG_MMC1_CMD_OUT,Delay Select Value in binary coded form for cfg_mmc1_cmd_out interface" bitfld.long 0x600 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x600 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x600 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x604 "CFG_MMC1_DAT0_IN,Delay Select Value in binary coded form for cfg_mmc1_dat0_in interface" bitfld.long 0x604 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x604 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x604 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x608 "CFG_MMC1_DAT0_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat0_oen interface" bitfld.long 0x608 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x608 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x608 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x60C "CFG_MMC1_DAT0_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat0_out interface" bitfld.long 0x60C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x60C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x610 "CFG_MMC1_DAT1_IN,Delay Select Value in binary coded form for cfg_mmc1_dat1_in interface" bitfld.long 0x610 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x610 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x610 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x614 "CFG_MMC1_DAT1_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat1_oen interface" bitfld.long 0x614 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x614 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x614 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x618 "CFG_MMC1_DAT1_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat1_out interface" bitfld.long 0x618 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x618 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x618 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x61C "CFG_MMC1_DAT2_IN,Delay Select Value in binary coded form for cfg_mmc1_dat2_in interface" bitfld.long 0x61C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x61C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x61C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x620 "CFG_MMC1_DAT2_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat2_oen interface" bitfld.long 0x620 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x620 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x620 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x624 "CFG_MMC1_DAT2_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat2_out interface" bitfld.long 0x624 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x624 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x624 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x628 "CFG_MMC1_DAT3_IN,Delay Select Value in binary coded form for cfg_mmc1_dat3_in interface" bitfld.long 0x628 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x628 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x628 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x62C "CFG_MMC1_DAT3_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat3_oen interface" bitfld.long 0x62C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x62C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x62C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x630 "CFG_MMC1_DAT3_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat3_out interface" bitfld.long 0x630 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x630 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x630 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x634 "CFG_MMC1_SDCD_IN,Delay Select Value in binary coded form for cfg_mmc1_sdcd_in interface" bitfld.long 0x634 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x634 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x634 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x638 "CFG_MMC1_SDCD_OEN,Delay Select Value in binary coded form for cfg_mmc1_sdcd_oen interface" bitfld.long 0x638 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x638 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x638 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x63C "CFG_MMC1_SDCD_OUT,Delay Select Value in binary coded form for cfg_mmc1_sdcd_out interface" bitfld.long 0x63C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x63C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x63C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x640 "CFG_MMC1_SDWP_IN,Delay Select Value in binary coded form for cfg_mmc1_sdwp_in interface" bitfld.long 0x640 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x640 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x640 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x644 "CFG_MMC1_SDWP_OEN,Delay Select Value in binary coded form for cfg_mmc1_sdwp_oen interface" bitfld.long 0x644 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x644 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x644 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x648 "CFG_MMC1_SDWP_OUT,Delay Select Value in binary coded form for cfg_mmc1_sdwp_out interface" bitfld.long 0x648 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x648 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x648 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x64C "CFG_MMC3_CLK_IN,Delay Select Value in binary coded form for cfg_mmc3_clk_in interface" bitfld.long 0x64C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x64C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x650 "CFG_MMC3_CLK_OEN,Delay Select Value in binary coded form for cfg_mmc3_clk_oen interface" bitfld.long 0x650 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x650 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x650 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x654 "CFG_MMC3_CLK_OUT,Delay Select Value in binary coded form for cfg_mmc3_clk_out interface" bitfld.long 0x654 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x654 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x654 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x658 "CFG_MMC3_CMD_IN,Delay Select Value in binary coded form for cfg_mmc3_cmd_in interface" bitfld.long 0x658 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x658 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x658 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x65C "CFG_MMC3_CMD_OEN,Delay Select Value in binary coded form for cfg_mmc3_cmd_oen interface" bitfld.long 0x65C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x65C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x65C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x660 "CFG_MMC3_CMD_OUT,Delay Select Value in binary coded form for cfg_mmc3_cmd_out interface" bitfld.long 0x660 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x660 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x660 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x664 "CFG_MMC3_DAT0_IN,Delay Select Value in binary coded form for cfg_mmc3_dat0_in interface" bitfld.long 0x664 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x664 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x664 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x668 "CFG_MMC3_DAT0_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat0_oen interface" bitfld.long 0x668 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x668 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x668 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x66C "CFG_MMC3_DAT0_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat0_out interface" bitfld.long 0x66C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x66C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x66C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x670 "CFG_MMC3_DAT1_IN,Delay Select Value in binary coded form for cfg_mmc3_dat1_in interface" bitfld.long 0x670 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x670 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x670 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x674 "CFG_MMC3_DAT1_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat1_oen interface" bitfld.long 0x674 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x674 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x674 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x678 "CFG_MMC3_DAT1_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat1_out interface" bitfld.long 0x678 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x678 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x678 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x67C "CFG_MMC3_DAT2_IN,Delay Select Value in binary coded form for cfg_mmc3_dat2_in interface" bitfld.long 0x67C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x67C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x67C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x680 "CFG_MMC3_DAT2_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat2_oen interface" bitfld.long 0x680 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x680 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x680 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x684 "CFG_MMC3_DAT2_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat2_out interface" bitfld.long 0x684 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x684 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x684 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x688 "CFG_MMC3_DAT3_IN,Delay Select Value in binary coded form for cfg_mmc3_dat3_in interface" bitfld.long 0x688 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x688 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x688 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x68C "CFG_MMC3_DAT3_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat3_oen interface" bitfld.long 0x68C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x68C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x690 "CFG_MMC3_DAT3_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat3_out interface" bitfld.long 0x690 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x690 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x690 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x694 "CFG_MMC3_DAT4_IN,Delay Select Value in binary coded form for cfg_mmc3_dat4_in interface" bitfld.long 0x694 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x694 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x694 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x698 "CFG_MMC3_DAT4_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat4_oen interface" bitfld.long 0x698 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x698 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x698 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x69C "CFG_MMC3_DAT4_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat4_out interface" bitfld.long 0x69C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x69C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x69C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6A0 "CFG_MMC3_DAT5_IN,Delay Select Value in binary coded form for cfg_mmc3_dat5_in interface" bitfld.long 0x6A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6A4 "CFG_MMC3_DAT5_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat5_oen interface" bitfld.long 0x6A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6A8 "CFG_MMC3_DAT5_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat5_out interface" bitfld.long 0x6A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6AC "CFG_MMC3_DAT6_IN,Delay Select Value in binary coded form for cfg_mmc3_dat6_in interface" bitfld.long 0x6AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6B0 "CFG_MMC3_DAT6_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat6_oen interface" bitfld.long 0x6B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6B4 "CFG_MMC3_DAT6_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat6_out interface" bitfld.long 0x6B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6B8 "CFG_MMC3_DAT7_IN,Delay Select Value in binary coded form for cfg_mmc3_dat7_in interface" bitfld.long 0x6B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6BC "CFG_MMC3_DAT7_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat7_oen interface" bitfld.long 0x6BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6C0 "CFG_MMC3_DAT7_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat7_out interface" bitfld.long 0x6C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6C4 "CFG_RGMII0_RXC_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxc_in interface" bitfld.long 0x6C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6C8 "CFG_RGMII0_RXC_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxc_oen interface" bitfld.long 0x6C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6CC "CFG_RGMII0_RXC_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxc_out interface" bitfld.long 0x6CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6D0 "CFG_RGMII0_RXCTL_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_in interface" bitfld.long 0x6D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6D4 "CFG_RGMII0_RXCTL_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_oen interface" bitfld.long 0x6D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6D8 "CFG_RGMII0_RXCTL_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_out interface" bitfld.long 0x6D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6DC "CFG_RGMII0_RXD0_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_in interface" bitfld.long 0x6DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6E0 "CFG_RGMII0_RXD0_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_oen interface" bitfld.long 0x6E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6E4 "CFG_RGMII0_RXD0_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_out interface" bitfld.long 0x6E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6E8 "CFG_RGMII0_RXD1_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_in interface" bitfld.long 0x6E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6EC "CFG_RGMII0_RXD1_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_oen interface" bitfld.long 0x6EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6F0 "CFG_RGMII0_RXD1_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_out interface" bitfld.long 0x6F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6F4 "CFG_RGMII0_RXD2_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_in interface" bitfld.long 0x6F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6F8 "CFG_RGMII0_RXD2_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_oen interface" bitfld.long 0x6F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x6FC "CFG_RGMII0_RXD2_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_out interface" bitfld.long 0x6FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x6FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x700 "CFG_RGMII0_RXD3_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_in interface" bitfld.long 0x700 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x700 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x700 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x704 "CFG_RGMII0_RXD3_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_oen interface" bitfld.long 0x704 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x704 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x704 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x708 "CFG_RGMII0_RXD3_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_out interface" bitfld.long 0x708 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x708 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x708 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x70C "CFG_RGMII0_TXC_IN,Delay Select Value in binary coded form for cfg_rgmii0_txc_in interface" bitfld.long 0x70C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x70C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x70C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x710 "CFG_RGMII0_TXC_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txc_oen interface" bitfld.long 0x710 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x710 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x710 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x714 "CFG_RGMII0_TXC_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txc_out interface" bitfld.long 0x714 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x714 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x714 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x718 "CFG_RGMII0_TXCTL_IN,Delay Select Value in binary coded form for cfg_rgmii0_txctl_in interface" bitfld.long 0x718 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x718 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x718 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x71C "CFG_RGMII0_TXCTL_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txctl_oen interface" bitfld.long 0x71C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x71C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x71C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x720 "CFG_RGMII0_TXCTL_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txctl_out interface" bitfld.long 0x720 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x720 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x720 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x724 "CFG_RGMII0_TXD0_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd0_in interface" bitfld.long 0x724 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x724 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x724 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x728 "CFG_RGMII0_TXD0_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd0_oen interface" bitfld.long 0x728 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x728 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x728 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x72C "CFG_RGMII0_TXD0_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd0_out interface" bitfld.long 0x72C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x72C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x72C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x730 "CFG_RGMII0_TXD1_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd1_in interface" bitfld.long 0x730 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x730 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x730 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x734 "CFG_RGMII0_TXD1_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd1_oen interface" bitfld.long 0x734 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x734 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x734 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x738 "CFG_RGMII0_TXD1_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd1_out interface" bitfld.long 0x738 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x738 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x738 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x73C "CFG_RGMII0_TXD2_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd2_in interface" bitfld.long 0x73C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x73C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x73C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x740 "CFG_RGMII0_TXD2_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd2_oen interface" bitfld.long 0x740 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x740 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x740 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x744 "CFG_RGMII0_TXD2_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd2_out interface" bitfld.long 0x744 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x744 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x744 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x748 "CFG_RGMII0_TXD3_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd3_in interface" bitfld.long 0x748 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x748 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x748 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x74C "CFG_RGMII0_TXD3_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd3_oen interface" bitfld.long 0x74C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x74C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x74C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x750 "CFG_RGMII0_TXD3_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd3_out interface" bitfld.long 0x750 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x750 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x750 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x754 "CFG_RTCK_IN,Delay Select Value in binary coded form for cfg_rtck_in interface" bitfld.long 0x754 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x754 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x754 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x758 "CFG_RTCK_OEN,Delay Select Value in binary coded form for cfg_rtck_oen interface" bitfld.long 0x758 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x758 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x758 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x75C "CFG_RTCK_OUT,Delay Select Value in binary coded form for cfg_rtck_out interface" bitfld.long 0x75C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x75C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x75C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x760 "CFG_SPI1_CS0_IN,Delay Select Value in binary coded form for cfg_spi1_cs0_in interface" bitfld.long 0x760 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x760 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x760 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x764 "CFG_SPI1_CS0_OEN,Delay Select Value in binary coded form for cfg_spi1_cs0_oen interface" bitfld.long 0x764 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x764 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x764 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x768 "CFG_SPI1_CS0_OUT,Delay Select Value in binary coded form for cfg_spi1_cs0_out interface" bitfld.long 0x768 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x768 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x768 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x76C "CFG_SPI1_CS1_IN,Delay Select Value in binary coded form for cfg_spi1_cs1_in interface" bitfld.long 0x76C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x76C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x76C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x770 "CFG_SPI1_CS1_OEN,Delay Select Value in binary coded form for cfg_spi1_cs1_oen interface" bitfld.long 0x770 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x770 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x770 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x774 "CFG_SPI1_CS1_OUT,Delay Select Value in binary coded form for cfg_spi1_cs1_out interface" bitfld.long 0x774 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x774 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x774 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x778 "CFG_SPI1_CS2_IN,Delay Select Value in binary coded form for cfg_spi1_cs2_in interface" bitfld.long 0x778 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x778 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x778 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x77C "CFG_SPI1_CS2_OEN,Delay Select Value in binary coded form for cfg_spi1_cs2_oen interface" bitfld.long 0x77C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x77C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x77C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x780 "CFG_SPI1_CS2_OUT,Delay Select Value in binary coded form for cfg_spi1_cs2_out interface" bitfld.long 0x780 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x780 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x780 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x784 "CFG_SPI1_CS3_IN,Delay Select Value in binary coded form for cfg_spi1_cs3_in interface" bitfld.long 0x784 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x784 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x784 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x788 "CFG_SPI1_CS3_OEN,Delay Select Value in binary coded form for cfg_spi1_cs3_oen interface" bitfld.long 0x788 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x788 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x788 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x78C "CFG_SPI1_CS3_OUT,Delay Select Value in binary coded form for cfg_spi1_cs3_out interface" bitfld.long 0x78C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x78C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x78C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x790 "CFG_SPI1_D0_IN,Delay Select Value in binary coded form for cfg_spi1_d0_in interface" bitfld.long 0x790 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x790 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x790 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x794 "CFG_SPI1_D0_OEN,Delay Select Value in binary coded form for cfg_spi1_d0_oen interface" bitfld.long 0x794 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x794 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x794 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x798 "CFG_SPI1_D0_OUT,Delay Select Value in binary coded form for cfg_spi1_d0_out interface" bitfld.long 0x798 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x798 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x798 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x79C "CFG_SPI1_D1_IN,Delay Select Value in binary coded form for cfg_spi1_d1_in interface" bitfld.long 0x79C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x79C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x79C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7A0 "CFG_SPI1_D1_OEN,Delay Select Value in binary coded form for cfg_spi1_d1_oen interface" bitfld.long 0x7A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7A4 "CFG_SPI1_D1_OUT,Delay Select Value in binary coded form for cfg_spi1_d1_out interface" bitfld.long 0x7A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7A8 "CFG_SPI1_SCLK_IN,Delay Select Value in binary coded form for cfg_spi1_sclk_in interface" bitfld.long 0x7A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7AC "CFG_SPI1_SCLK_OEN,Delay Select Value in binary coded form for cfg_spi1_sclk_oen interface" bitfld.long 0x7AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7B0 "CFG_SPI1_SCLK_OUT,Delay Select Value in binary coded form for cfg_spi1_sclk_out interface" bitfld.long 0x7B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7B4 "CFG_SPI2_CS0_IN,Delay Select Value in binary coded form for cfg_spi2_cs0_in interface" bitfld.long 0x7B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7B8 "CFG_SPI2_CS0_OEN,Delay Select Value in binary coded form for cfg_spi2_cs0_oen interface" bitfld.long 0x7B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7BC "CFG_SPI2_CS0_OUT,Delay Select Value in binary coded form for cfg_spi2_cs0_out interface" bitfld.long 0x7BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7C0 "CFG_SPI2_D0_IN,Delay Select Value in binary coded form for cfg_spi2_d0_in interface" bitfld.long 0x7C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7C4 "CFG_SPI2_D0_OEN,Delay Select Value in binary coded form for cfg_spi2_d0_oen interface" bitfld.long 0x7C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7C8 "CFG_SPI2_D0_OUT,Delay Select Value in binary coded form for cfg_spi2_d0_out interface" bitfld.long 0x7C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7CC "CFG_SPI2_D1_IN,Delay Select Value in binary coded form for cfg_spi2_d1_in interface" bitfld.long 0x7CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7D0 "CFG_SPI2_D1_OEN,Delay Select Value in binary coded form for cfg_spi2_d1_oen interface" bitfld.long 0x7D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7D4 "CFG_SPI2_D1_OUT,Delay Select Value in binary coded form for cfg_spi2_d1_out interface" bitfld.long 0x7D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7D8 "CFG_SPI2_SCLK_IN,Delay Select Value in binary coded form for cfg_spi2_sclk_in interface" bitfld.long 0x7D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7DC "CFG_SPI2_SCLK_OEN,Delay Select Value in binary coded form for cfg_spi2_sclk_oen interface" bitfld.long 0x7DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7E0 "CFG_SPI2_SCLK_OUT,Delay Select Value in binary coded form for cfg_spi2_sclk_out interface" bitfld.long 0x7E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7E4 "CFG_TDI_IN,Delay Select Value in binary coded form for cfg_tdi_in interface" bitfld.long 0x7E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7E8 "CFG_TDI_OEN,Delay Select Value in binary coded form for cfg_tdi_oen interface" bitfld.long 0x7E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7EC "CFG_TDI_OUT,Delay Select Value in binary coded form for cfg_tdi_out interface" bitfld.long 0x7EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7F0 "CFG_TDO_IN,Delay Select Value in binary coded form for cfg_tdo_in interface" bitfld.long 0x7F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7F4 "CFG_TDO_OEN,Delay Select Value in binary coded form for cfg_tdo_oen interface" bitfld.long 0x7F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7F8 "CFG_TDO_OUT,Delay Select Value in binary coded form for cfg_tdo_out interface" bitfld.long 0x7F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x7FC "CFG_TMS_IN,Delay Select Value in binary coded form for cfg_tms_in interface" bitfld.long 0x7FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x7FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x7FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x800 "CFG_TMS_OEN,Delay Select Value in binary coded form for cfg_tms_oen interface" bitfld.long 0x800 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x800 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x800 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x804 "CFG_TMS_OUT,Delay Select Value in binary coded form for cfg_tms_out interface" bitfld.long 0x804 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x804 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x804 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x808 "CFG_TRSTN_IN,Delay Select Value in binary coded form for cfg_trstn_in interface" bitfld.long 0x808 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x808 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x808 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x80C "CFG_TRSTN_OEN,Delay Select Value in binary coded form for cfg_trstn_oen interface" bitfld.long 0x80C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x80C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x80C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x810 "CFG_TRSTN_OUT,Delay Select Value in binary coded form for cfg_trstn_out interface" bitfld.long 0x810 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x810 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x810 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x814 "CFG_UART1_CTSN_IN,Delay Select Value in binary coded form for cfg_uart1_ctsn_in interface" bitfld.long 0x814 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x814 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x814 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x818 "CFG_UART1_CTSN_OEN,Delay Select Value in binary coded form for cfg_uart1_ctsn_oen interface" bitfld.long 0x818 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x818 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x818 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x81C "CFG_UART1_CTSN_OUT,Delay Select Value in binary coded form for cfg_uart1_ctsn_out interface" bitfld.long 0x81C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x81C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x81C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x820 "CFG_UART1_RTSN_IN,Delay Select Value in binary coded form for cfg_uart1_rtsn_in interface" bitfld.long 0x820 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x820 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x820 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x824 "CFG_UART1_RTSN_OEN,Delay Select Value in binary coded form for cfg_uart1_rtsn_oen interface" bitfld.long 0x824 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x824 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x824 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x828 "CFG_UART1_RTSN_OUT,Delay Select Value in binary coded form for cfg_uart1_rtsn_out interface" bitfld.long 0x828 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x828 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x828 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x82C "CFG_UART1_RXD_IN,Delay Select Value in binary coded form for cfg_uart1_rxd_in interface" bitfld.long 0x82C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x82C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x82C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x830 "CFG_UART1_RXD_OEN,Delay Select Value in binary coded form for cfg_uart1_rxd_oen interface" bitfld.long 0x830 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x830 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x830 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x834 "CFG_UART1_RXD_OUT,Delay Select Value in binary coded form for cfg_uart1_rxd_out interface" bitfld.long 0x834 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x834 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x834 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x838 "CFG_UART1_TXD_IN,Delay Select Value in binary coded form for cfg_uart1_txd_in interface" bitfld.long 0x838 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x838 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x838 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x83C "CFG_UART1_TXD_OEN,Delay Select Value in binary coded form for cfg_uart1_txd_oen interface" bitfld.long 0x83C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x83C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x83C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x840 "CFG_UART1_TXD_OUT,Delay Select Value in binary coded form for cfg_uart1_txd_out interface" bitfld.long 0x840 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x840 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x840 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x844 "CFG_UART2_CTSN_IN,Delay Select Value in binary coded form for cfg_uart2_ctsn_in interface" bitfld.long 0x844 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x844 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x844 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x848 "CFG_UART2_CTSN_OEN,Delay Select Value in binary coded form for cfg_uart2_ctsn_oen interface" bitfld.long 0x848 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x848 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x848 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x84C "CFG_UART2_CTSN_OUT,Delay Select Value in binary coded form for cfg_uart2_ctsn_out interface" bitfld.long 0x84C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x84C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x84C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x850 "CFG_UART2_RTSN_IN,Delay Select Value in binary coded form for cfg_uart2_rtsn_in interface" bitfld.long 0x850 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x850 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x850 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x854 "CFG_UART2_RTSN_OEN,Delay Select Value in binary coded form for cfg_uart2_rtsn_oen interface" bitfld.long 0x854 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x854 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x854 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x858 "CFG_UART2_RTSN_OUT,Delay Select Value in binary coded form for cfg_uart2_rtsn_out interface" bitfld.long 0x858 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x858 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x858 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x85C "CFG_UART2_RXD_IN,Delay Select Value in binary coded form for cfg_uart2_rxd_in interface" bitfld.long 0x85C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x85C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x85C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x860 "CFG_UART2_RXD_OEN,Delay Select Value in binary coded form for cfg_uart2_rxd_oen interface" bitfld.long 0x860 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x860 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x860 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x864 "CFG_UART2_RXD_OUT,Delay Select Value in binary coded form for cfg_uart2_rxd_out interface" bitfld.long 0x864 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x864 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x864 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x868 "CFG_UART2_TXD_IN,Delay Select Value in binary coded form for cfg_uart2_txd_in interface" bitfld.long 0x868 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x868 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x868 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x86C "CFG_UART2_TXD_OEN,Delay Select Value in binary coded form for cfg_uart2_txd_oen interface" bitfld.long 0x86C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x86C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x86C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x870 "CFG_UART2_TXD_OUT,Delay Select Value in binary coded form for cfg_uart2_txd_out interface" bitfld.long 0x870 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x870 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x870 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x874 "CFG_UART3_RXD_IN,Delay Select Value in binary coded form for cfg_uart3_rxd_in interface" bitfld.long 0x874 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x874 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x874 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x878 "CFG_UART3_RXD_OEN,Delay Select Value in binary coded form for cfg_uart3_rxd_oen interface" bitfld.long 0x878 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x878 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x878 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x87C "CFG_UART3_RXD_OUT,Delay Select Value in binary coded form for cfg_uart3_rxd_out interface" bitfld.long 0x87C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x87C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x87C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x880 "CFG_UART3_TXD_IN,Delay Select Value in binary coded form for cfg_uart3_txd_in interface" bitfld.long 0x880 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x880 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x880 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x884 "CFG_UART3_TXD_OEN,Delay Select Value in binary coded form for cfg_uart3_txd_oen interface" bitfld.long 0x884 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x884 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x884 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x888 "CFG_UART3_TXD_OUT,Delay Select Value in binary coded form for cfg_uart3_txd_out interface" bitfld.long 0x888 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x888 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x888 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x88C "CFG_USB1_DRVVBUS_IN,Delay Select Value in binary coded form for cfg_usb1_drvvbus_in interface" bitfld.long 0x88C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x88C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x88C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x890 "CFG_USB1_DRVVBUS_OEN,Delay Select Value in binary coded form for cfg_usb1_drvvbus_oen interface" bitfld.long 0x890 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x890 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x890 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x894 "CFG_USB1_DRVVBUS_OUT,Delay Select Value in binary coded form for cfg_usb1_drvvbus_out interface" bitfld.long 0x894 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x894 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x894 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x898 "CFG_USB2_DRVVBUS_IN,Delay Select Value in binary coded form for cfg_usb2_drvvbus_in interface" bitfld.long 0x898 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x898 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x898 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x89C "CFG_USB2_DRVVBUS_OEN,Delay Select Value in binary coded form for cfg_usb2_drvvbus_oen interface" bitfld.long 0x89C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x89C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x89C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8A0 "CFG_USB2_DRVVBUS_OUT,Delay Select Value in binary coded form for cfg_usb2_drvvbus_out interface" bitfld.long 0x8A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8A4 "CFG_VIN1A_CLK0_IN,Delay Select Value in binary coded form for cfg_vin1a_clk0_in interface" bitfld.long 0x8A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8A8 "CFG_VIN1A_CLK0_OEN,Delay Select Value in binary coded form for cfg_vin1a_clk0_oen interface" bitfld.long 0x8A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8AC "CFG_VIN1A_CLK0_OUT,Delay Select Value in binary coded form for cfg_vin1a_clk0_out interface" bitfld.long 0x8AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8B0 "CFG_VIN1A_D0_IN,Delay Select Value in binary coded form for cfg_vin1a_d0_in interface" bitfld.long 0x8B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8B4 "CFG_VIN1A_D0_OEN,Delay Select Value in binary coded form for cfg_vin1a_d0_oen interface" bitfld.long 0x8B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8B8 "CFG_VIN1A_D0_OUT,Delay Select Value in binary coded form for cfg_vin1a_d0_out interface" bitfld.long 0x8B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8BC "CFG_VIN1A_D10_IN,Delay Select Value in binary coded form for cfg_vin1a_d10_in interface" bitfld.long 0x8BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8C0 "CFG_VIN1A_D10_OEN,Delay Select Value in binary coded form for cfg_vin1a_d10_oen interface" bitfld.long 0x8C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8C4 "CFG_VIN1A_D10_OUT,Delay Select Value in binary coded form for cfg_vin1a_d10_out interface" bitfld.long 0x8C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8C8 "CFG_VIN1A_D11_IN,Delay Select Value in binary coded form for cfg_vin1a_d11_in interface" bitfld.long 0x8C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8CC "CFG_VIN1A_D11_OEN,Delay Select Value in binary coded form for cfg_vin1a_d11_oen interface" bitfld.long 0x8CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8D0 "CFG_VIN1A_D11_OUT,Delay Select Value in binary coded form for cfg_vin1a_d11_out interface" bitfld.long 0x8D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8D4 "CFG_VIN1A_D12_IN,Delay Select Value in binary coded form for cfg_vin1a_d12_in interface" bitfld.long 0x8D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8D8 "CFG_VIN1A_D12_OEN,Delay Select Value in binary coded form for cfg_vin1a_d12_oen interface" bitfld.long 0x8D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8DC "CFG_VIN1A_D12_OUT,Delay Select Value in binary coded form for cfg_vin1a_d12_out interface" bitfld.long 0x8DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8E0 "CFG_VIN1A_D13_IN,Delay Select Value in binary coded form for cfg_vin1a_d13_in interface" bitfld.long 0x8E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8E4 "CFG_VIN1A_D13_OEN,Delay Select Value in binary coded form for cfg_vin1a_d13_oen interface" bitfld.long 0x8E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8E8 "CFG_VIN1A_D13_OUT,Delay Select Value in binary coded form for cfg_vin1a_d13_out interface" bitfld.long 0x8E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8EC "CFG_VIN1A_D14_IN,Delay Select Value in binary coded form for cfg_vin1a_d14_in interface" bitfld.long 0x8EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8F0 "CFG_VIN1A_D14_OEN,Delay Select Value in binary coded form for cfg_vin1a_d14_oen interface" bitfld.long 0x8F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8F4 "CFG_VIN1A_D14_OUT,Delay Select Value in binary coded form for cfg_vin1a_d14_out interface" bitfld.long 0x8F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8F8 "CFG_VIN1A_D15_IN,Delay Select Value in binary coded form for cfg_vin1a_d15_in interface" bitfld.long 0x8F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x8FC "CFG_VIN1A_D15_OEN,Delay Select Value in binary coded form for cfg_vin1a_d15_oen interface" bitfld.long 0x8FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x8FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x900 "CFG_VIN1A_D15_OUT,Delay Select Value in binary coded form for cfg_vin1a_d15_out interface" bitfld.long 0x900 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x900 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x900 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x904 "CFG_VIN1A_D16_IN,Delay Select Value in binary coded form for cfg_vin1a_d16_in interface" bitfld.long 0x904 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x904 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x904 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x908 "CFG_VIN1A_D16_OEN,Delay Select Value in binary coded form for cfg_vin1a_d16_oen interface" bitfld.long 0x908 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x908 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x908 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x90C "CFG_VIN1A_D16_OUT,Delay Select Value in binary coded form for cfg_vin1a_d16_out interface" bitfld.long 0x90C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x90C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x90C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x910 "CFG_VIN1A_D17_IN,Delay Select Value in binary coded form for cfg_vin1a_d17_in interface" bitfld.long 0x910 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x910 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x910 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x914 "CFG_VIN1A_D17_OEN,Delay Select Value in binary coded form for cfg_vin1a_d17_oen interface" bitfld.long 0x914 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x914 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x914 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x918 "CFG_VIN1A_D17_OUT,Delay Select Value in binary coded form for cfg_vin1a_d17_out interface" bitfld.long 0x918 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x918 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x918 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x91C "CFG_VIN1A_D18_IN,Delay Select Value in binary coded form for cfg_vin1a_d18_in interface" bitfld.long 0x91C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x91C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x91C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x920 "CFG_VIN1A_D18_OEN,Delay Select Value in binary coded form for cfg_vin1a_d18_oen interface" bitfld.long 0x920 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x920 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x920 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x924 "CFG_VIN1A_D18_OUT,Delay Select Value in binary coded form for cfg_vin1a_d18_out interface" bitfld.long 0x924 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x924 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x924 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x928 "CFG_VIN1A_D19_IN,Delay Select Value in binary coded form for cfg_vin1a_d19_in interface" bitfld.long 0x928 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x928 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x928 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x92C "CFG_VIN1A_D19_OEN,Delay Select Value in binary coded form for cfg_vin1a_d19_oen interface" bitfld.long 0x92C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x92C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x92C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x930 "CFG_VIN1A_D19_OUT,Delay Select Value in binary coded form for cfg_vin1a_d19_out interface" bitfld.long 0x930 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x930 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x930 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x934 "CFG_VIN1A_D1_IN,Delay Select Value in binary coded form for cfg_vin1a_d1_in interface" bitfld.long 0x934 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x934 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x934 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x938 "CFG_VIN1A_D1_OEN,Delay Select Value in binary coded form for cfg_vin1a_d1_oen interface" bitfld.long 0x938 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x938 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x938 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x93C "CFG_VIN1A_D1_OUT,Delay Select Value in binary coded form for cfg_vin1a_d1_out interface" bitfld.long 0x93C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x93C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x93C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x940 "CFG_VIN1A_D20_IN,Delay Select Value in binary coded form for cfg_vin1a_d20_in interface" bitfld.long 0x940 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x940 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x940 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x944 "CFG_VIN1A_D20_OEN,Delay Select Value in binary coded form for cfg_vin1a_d20_oen interface" bitfld.long 0x944 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x944 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x944 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x948 "CFG_VIN1A_D20_OUT,Delay Select Value in binary coded form for cfg_vin1a_d20_out interface" bitfld.long 0x948 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x948 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x948 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x94C "CFG_VIN1A_D21_IN,Delay Select Value in binary coded form for cfg_vin1a_d21_in interface" bitfld.long 0x94C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x94C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x94C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x950 "CFG_VIN1A_D21_OEN,Delay Select Value in binary coded form for cfg_vin1a_d21_oen interface" bitfld.long 0x950 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x950 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x950 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x954 "CFG_VIN1A_D21_OUT,Delay Select Value in binary coded form for cfg_vin1a_d21_out interface" bitfld.long 0x954 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x954 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x954 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x958 "CFG_VIN1A_D22_IN,Delay Select Value in binary coded form for cfg_vin1a_d22_in interface" bitfld.long 0x958 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x958 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x958 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x95C "CFG_VIN1A_D22_OEN,Delay Select Value in binary coded form for cfg_vin1a_d22_oen interface" bitfld.long 0x95C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x95C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x95C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x960 "CFG_VIN1A_D22_OUT,Delay Select Value in binary coded form for cfg_vin1a_d22_out interface" bitfld.long 0x960 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x960 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x960 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x964 "CFG_VIN1A_D23_IN,Delay Select Value in binary coded form for cfg_vin1a_d23_in interface" bitfld.long 0x964 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x964 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x964 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x968 "CFG_VIN1A_D23_OEN,Delay Select Value in binary coded form for cfg_vin1a_d23_oen interface" bitfld.long 0x968 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x968 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x968 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x96C "CFG_VIN1A_D23_OUT,Delay Select Value in binary coded form for cfg_vin1a_d23_out interface" bitfld.long 0x96C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x96C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x96C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x970 "CFG_VIN1A_D2_IN,Delay Select Value in binary coded form for cfg_vin1a_d2_in interface" bitfld.long 0x970 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x970 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x970 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x974 "CFG_VIN1A_D2_OEN,Delay Select Value in binary coded form for cfg_vin1a_d2_oen interface" bitfld.long 0x974 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x974 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x974 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x978 "CFG_VIN1A_D2_OUT,Delay Select Value in binary coded form for cfg_vin1a_d2_out interface" bitfld.long 0x978 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x978 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x978 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x97C "CFG_VIN1A_D3_IN,Delay Select Value in binary coded form for cfg_vin1a_d3_in interface" bitfld.long 0x97C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x97C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x97C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x980 "CFG_VIN1A_D3_OEN,Delay Select Value in binary coded form for cfg_vin1a_d3_oen interface" bitfld.long 0x980 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x980 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x980 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x984 "CFG_VIN1A_D3_OUT,Delay Select Value in binary coded form for cfg_vin1a_d3_out interface" bitfld.long 0x984 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x984 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x984 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x988 "CFG_VIN1A_D4_IN,Delay Select Value in binary coded form for cfg_vin1a_d4_in interface" bitfld.long 0x988 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x988 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x988 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x98C "CFG_VIN1A_D4_OEN,Delay Select Value in binary coded form for cfg_vin1a_d4_oen interface" bitfld.long 0x98C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x98C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x98C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x990 "CFG_VIN1A_D4_OUT,Delay Select Value in binary coded form for cfg_vin1a_d4_out interface" bitfld.long 0x990 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x990 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x990 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x994 "CFG_VIN1A_D5_IN,Delay Select Value in binary coded form for cfg_vin1a_d5_in interface" bitfld.long 0x994 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x994 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x994 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x998 "CFG_VIN1A_D5_OEN,Delay Select Value in binary coded form for cfg_vin1a_d5_oen interface" bitfld.long 0x998 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x998 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x998 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x99C "CFG_VIN1A_D5_OUT,Delay Select Value in binary coded form for cfg_vin1a_d5_out interface" bitfld.long 0x99C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x99C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x99C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9A0 "CFG_VIN1A_D6_IN,Delay Select Value in binary coded form for cfg_vin1a_d6_in interface" bitfld.long 0x9A0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9A0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9A0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9A4 "CFG_VIN1A_D6_OEN,Delay Select Value in binary coded form for cfg_vin1a_d6_oen interface" bitfld.long 0x9A4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9A4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9A4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9A8 "CFG_VIN1A_D6_OUT,Delay Select Value in binary coded form for cfg_vin1a_d6_out interface" bitfld.long 0x9A8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9A8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9A8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9AC "CFG_VIN1A_D7_IN,Delay Select Value in binary coded form for cfg_vin1a_d7_in interface" bitfld.long 0x9AC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9AC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9AC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9B0 "CFG_VIN1A_D7_OEN,Delay Select Value in binary coded form for cfg_vin1a_d7_oen interface" bitfld.long 0x9B0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9B0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9B0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9B4 "CFG_VIN1A_D7_OUT,Delay Select Value in binary coded form for cfg_vin1a_d7_out interface" bitfld.long 0x9B4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9B4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9B4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9B8 "CFG_VIN1A_D8_IN,Delay Select Value in binary coded form for cfg_vin1a_d8_in interface" bitfld.long 0x9B8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9B8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9B8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9BC "CFG_VIN1A_D8_OEN,Delay Select Value in binary coded form for cfg_vin1a_d8_oen interface" bitfld.long 0x9BC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9BC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9BC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9C0 "CFG_VIN1A_D8_OUT,Delay Select Value in binary coded form for cfg_vin1a_d8_out interface" bitfld.long 0x9C0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9C0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9C4 "CFG_VIN1A_D9_IN,Delay Select Value in binary coded form for cfg_vin1a_d9_in interface" bitfld.long 0x9C4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9C4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9C8 "CFG_VIN1A_D9_OEN,Delay Select Value in binary coded form for cfg_vin1a_d9_oen interface" bitfld.long 0x9C8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9C8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9C8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9CC "CFG_VIN1A_D9_OUT,Delay Select Value in binary coded form for cfg_vin1a_d9_out interface" bitfld.long 0x9CC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9CC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9CC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9D0 "CFG_VIN1A_DE0_IN,Delay Select Value in binary coded form for cfg_vin1a_de0_in interface" bitfld.long 0x9D0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9D0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9D0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9D4 "CFG_VIN1A_DE0_OEN,Delay Select Value in binary coded form for cfg_vin1a_de0_oen interface" bitfld.long 0x9D4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9D4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9D4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9D8 "CFG_VIN1A_DE0_OUT,Delay Select Value in binary coded form for cfg_vin1a_de0_out interface" bitfld.long 0x9D8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9D8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9D8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9DC "CFG_VIN1A_FLD0_IN,Delay Select Value in binary coded form for cfg_vin1a_fld0_in interface" bitfld.long 0x9DC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9DC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9DC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9E0 "CFG_VIN1A_FLD0_OEN,Delay Select Value in binary coded form for cfg_vin1a_fld0_oen interface" bitfld.long 0x9E0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9E0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9E0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9E4 "CFG_VIN1A_FLD0_OUT,Delay Select Value in binary coded form for cfg_vin1a_fld0_out interface" bitfld.long 0x9E4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9E4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9E4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9E8 "CFG_VIN1A_HSYNC0_IN,Delay Select Value in binary coded form for cfg_vin1a_hsync0_in interface" bitfld.long 0x9E8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9E8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9E8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9EC "CFG_VIN1A_HSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin1a_hsync0_oen interface" bitfld.long 0x9EC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9EC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9EC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9F0 "CFG_VIN1A_HSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin1a_hsync0_out interface" bitfld.long 0x9F0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9F0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9F0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9F4 "CFG_VIN1A_VSYNC0_IN,Delay Select Value in binary coded form for cfg_vin1a_vsync0_in interface" bitfld.long 0x9F4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9F4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9F4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9F8 "CFG_VIN1A_VSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin1a_vsync0_oen interface" bitfld.long 0x9F8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9F8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9F8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0x9FC "CFG_VIN1A_VSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin1a_vsync0_out interface" bitfld.long 0x9FC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x9FC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0x9FC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA00 "CFG_VIN1B_CLK1_IN,Delay Select Value in binary coded form for cfg_vin1b_clk1_in interface" bitfld.long 0xA00 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA00 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA00 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA04 "CFG_VIN1B_CLK1_OEN,Delay Select Value in binary coded form for cfg_vin1b_clk1_oen interface" bitfld.long 0xA04 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA04 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA04 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA08 "CFG_VIN1B_CLK1_OUT,Delay Select Value in binary coded form for cfg_vin1b_clk1_out interface" bitfld.long 0xA08 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA08 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA08 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA0C "CFG_VIN2A_CLK0_IN,Delay Select Value in binary coded form for cfg_vin2a_clk0_in interface" bitfld.long 0xA0C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA0C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA0C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA10 "CFG_VIN2A_CLK0_OEN,Delay Select Value in binary coded form for cfg_vin2a_clk0_oen interface" bitfld.long 0xA10 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA10 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA10 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA14 "CFG_VIN2A_CLK0_OUT,Delay Select Value in binary coded form for cfg_vin2a_clk0_out interface" bitfld.long 0xA14 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA14 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA14 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA18 "CFG_VIN2A_D0_IN,Delay Select Value in binary coded form for cfg_vin2a_d0_in interface" bitfld.long 0xA18 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA18 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA18 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA1C "CFG_VIN2A_D0_OEN,Delay Select Value in binary coded form for cfg_vin2a_d0_oen interface" bitfld.long 0xA1C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA1C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA1C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA20 "CFG_VIN2A_D0_OUT,Delay Select Value in binary coded form for cfg_vin2a_d0_out interface" bitfld.long 0xA20 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA20 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA20 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA24 "CFG_VIN2A_D10_IN,Delay Select Value in binary coded form for cfg_vin2a_d10_in interface" bitfld.long 0xA24 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA24 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA24 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA28 "CFG_VIN2A_D10_OEN,Delay Select Value in binary coded form for cfg_vin2a_d10_oen interface" bitfld.long 0xA28 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA28 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA28 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA2C "CFG_VIN2A_D10_OUT,Delay Select Value in binary coded form for cfg_vin2a_d10_out interface" bitfld.long 0xA2C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA2C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA2C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA30 "CFG_VIN2A_D11_IN,Delay Select Value in binary coded form for cfg_vin2a_d11_in interface" bitfld.long 0xA30 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA30 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA30 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA34 "CFG_VIN2A_D11_OEN,Delay Select Value in binary coded form for cfg_vin2a_d11_oen interface" bitfld.long 0xA34 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA34 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA34 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA38 "CFG_VIN2A_D11_OUT,Delay Select Value in binary coded form for cfg_vin2a_d11_out interface" bitfld.long 0xA38 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA38 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA38 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA3C "CFG_VIN2A_D12_IN,Delay Select Value in binary coded form for cfg_vin2a_d12_in interface" bitfld.long 0xA3C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA3C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA3C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA40 "CFG_VIN2A_D12_OEN,Delay Select Value in binary coded form for cfg_vin2a_d12_oen interface" bitfld.long 0xA40 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA40 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA40 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA44 "CFG_VIN2A_D12_OUT,Delay Select Value in binary coded form for cfg_vin2a_d12_out interface" bitfld.long 0xA44 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA44 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA44 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA48 "CFG_VIN2A_D13_IN,Delay Select Value in binary coded form for cfg_vin2a_d13_in interface" bitfld.long 0xA48 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA48 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA48 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA4C "CFG_VIN2A_D13_OEN,Delay Select Value in binary coded form for cfg_vin2a_d13_oen interface" bitfld.long 0xA4C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA4C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA4C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA50 "CFG_VIN2A_D13_OUT,Delay Select Value in binary coded form for cfg_vin2a_d13_out interface" bitfld.long 0xA50 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA50 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA50 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA54 "CFG_VIN2A_D14_IN,Delay Select Value in binary coded form for cfg_vin2a_d14_in interface" bitfld.long 0xA54 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA54 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA54 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA58 "CFG_VIN2A_D14_OEN,Delay Select Value in binary coded form for cfg_vin2a_d14_oen interface" bitfld.long 0xA58 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA58 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA58 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA5C "CFG_VIN2A_D14_OUT,Delay Select Value in binary coded form for cfg_vin2a_d14_out interface" bitfld.long 0xA5C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA5C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA5C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA60 "CFG_VIN2A_D15_IN,Delay Select Value in binary coded form for cfg_vin2a_d15_in interface" bitfld.long 0xA60 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA60 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA60 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA64 "CFG_VIN2A_D15_OEN,Delay Select Value in binary coded form for cfg_vin2a_d15_oen interface" bitfld.long 0xA64 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA64 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA64 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA68 "CFG_VIN2A_D15_OUT,Delay Select Value in binary coded form for cfg_vin2a_d15_out interface" bitfld.long 0xA68 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA68 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA68 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA6C "CFG_VIN2A_D16_IN,Delay Select Value in binary coded form for cfg_vin2a_d16_in interface" bitfld.long 0xA6C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA6C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA6C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA70 "CFG_VIN2A_D16_OEN,Delay Select Value in binary coded form for cfg_vin2a_d16_oen interface" bitfld.long 0xA70 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA70 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA70 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA74 "CFG_VIN2A_D16_OUT,Delay Select Value in binary coded form for cfg_vin2a_d16_out interface" bitfld.long 0xA74 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA74 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA74 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA78 "CFG_VIN2A_D17_IN,Delay Select Value in binary coded form for cfg_vin2a_d17_in interface" bitfld.long 0xA78 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA78 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA78 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA7C "CFG_VIN2A_D17_OEN,Delay Select Value in binary coded form for cfg_vin2a_d17_oen interface" bitfld.long 0xA7C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA7C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA7C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA80 "CFG_VIN2A_D17_OUT,Delay Select Value in binary coded form for cfg_vin2a_d17_out interface" bitfld.long 0xA80 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA80 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA80 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA84 "CFG_VIN2A_D18_IN,Delay Select Value in binary coded form for cfg_vin2a_d18_in interface" bitfld.long 0xA84 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA84 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA84 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA88 "CFG_VIN2A_D18_OEN,Delay Select Value in binary coded form for cfg_vin2a_d18_oen interface" bitfld.long 0xA88 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA88 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA88 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA8C "CFG_VIN2A_D18_OUT,Delay Select Value in binary coded form for cfg_vin2a_d18_out interface" bitfld.long 0xA8C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA8C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA8C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA90 "CFG_VIN2A_D19_IN,Delay Select Value in binary coded form for cfg_vin2a_d19_in interface" bitfld.long 0xA90 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA90 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA90 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA94 "CFG_VIN2A_D19_OEN,Delay Select Value in binary coded form for cfg_vin2a_d19_oen interface" bitfld.long 0xA94 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA94 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA94 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA98 "CFG_VIN2A_D19_OUT,Delay Select Value in binary coded form for cfg_vin2a_d19_out interface" bitfld.long 0xA98 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA98 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA98 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xA9C "CFG_VIN2A_D1_IN,Delay Select Value in binary coded form for cfg_vin2a_d1_in interface" bitfld.long 0xA9C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xA9C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xA9C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAA0 "CFG_VIN2A_D1_OEN,Delay Select Value in binary coded form for cfg_vin2a_d1_oen interface" bitfld.long 0xAA0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAA0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAA0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAA4 "CFG_VIN2A_D1_OUT,Delay Select Value in binary coded form for cfg_vin2a_d1_out interface" bitfld.long 0xAA4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAA4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAA4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAA8 "CFG_VIN2A_D20_IN,Delay Select Value in binary coded form for cfg_vin2a_d20_in interface" bitfld.long 0xAA8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAA8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAA8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAAC "CFG_VIN2A_D20_OEN,Delay Select Value in binary coded form for cfg_vin2a_d20_oen interface" bitfld.long 0xAAC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAAC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAAC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAB0 "CFG_VIN2A_D20_OUT,Delay Select Value in binary coded form for cfg_vin2a_d20_out interface" bitfld.long 0xAB0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAB0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAB0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAB4 "CFG_VIN2A_D21_IN,Delay Select Value in binary coded form for cfg_vin2a_d21_in interface" bitfld.long 0xAB4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAB4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAB4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAB8 "CFG_VIN2A_D21_OEN,Delay Select Value in binary coded form for cfg_vin2a_d21_oen interface" bitfld.long 0xAB8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAB8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAB8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xABC "CFG_VIN2A_D21_OUT,Delay Select Value in binary coded form for cfg_vin2a_d21_out interface" bitfld.long 0xABC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xABC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xABC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAC0 "CFG_VIN2A_D22_IN,Delay Select Value in binary coded form for cfg_vin2a_d22_in interface" bitfld.long 0xAC0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAC0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAC4 "CFG_VIN2A_D22_OEN,Delay Select Value in binary coded form for cfg_vin2a_d22_oen interface" bitfld.long 0xAC4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAC4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAC8 "CFG_VIN2A_D22_OUT,Delay Select Value in binary coded form for cfg_vin2a_d22_out interface" bitfld.long 0xAC8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAC8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAC8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xACC "CFG_VIN2A_D23_IN,Delay Select Value in binary coded form for cfg_vin2a_d23_in interface" bitfld.long 0xACC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xACC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xACC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAD0 "CFG_VIN2A_D23_OEN,Delay Select Value in binary coded form for cfg_vin2a_d23_oen interface" bitfld.long 0xAD0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAD0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAD0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAD4 "CFG_VIN2A_D23_OUT,Delay Select Value in binary coded form for cfg_vin2a_d23_out interface" bitfld.long 0xAD4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAD4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAD4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAD8 "CFG_VIN2A_D2_IN,Delay Select Value in binary coded form for cfg_vin2a_d2_in interface" bitfld.long 0xAD8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAD8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAD8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xADC "CFG_VIN2A_D2_OEN,Delay Select Value in binary coded form for cfg_vin2a_d2_oen interface" bitfld.long 0xADC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xADC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xADC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAE0 "CFG_VIN2A_D2_OUT,Delay Select Value in binary coded form for cfg_vin2a_d2_out interface" bitfld.long 0xAE0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAE0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAE0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAE4 "CFG_VIN2A_D3_IN,Delay Select Value in binary coded form for cfg_vin2a_d3_in interface" bitfld.long 0xAE4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAE4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAE4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAE8 "CFG_VIN2A_D3_OEN,Delay Select Value in binary coded form for cfg_vin2a_d3_oen interface" bitfld.long 0xAE8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAE8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAE8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAEC "CFG_VIN2A_D3_OUT,Delay Select Value in binary coded form for cfg_vin2a_d3_out interface" bitfld.long 0xAEC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAEC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAEC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAF0 "CFG_VIN2A_D4_IN,Delay Select Value in binary coded form for cfg_vin2a_d4_in interface" bitfld.long 0xAF0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAF0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAF0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAF4 "CFG_VIN2A_D4_OEN,Delay Select Value in binary coded form for cfg_vin2a_d4_oen interface" bitfld.long 0xAF4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAF4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAF4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAF8 "CFG_VIN2A_D4_OUT,Delay Select Value in binary coded form for cfg_vin2a_d4_out interface" bitfld.long 0xAF8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAF8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAF8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xAFC "CFG_VIN2A_D5_IN,Delay Select Value in binary coded form for cfg_vin2a_d5_in interface" bitfld.long 0xAFC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xAFC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xAFC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB00 "CFG_VIN2A_D5_OEN,Delay Select Value in binary coded form for cfg_vin2a_d5_oen interface" bitfld.long 0xB00 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB00 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB00 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB04 "CFG_VIN2A_D5_OUT,Delay Select Value in binary coded form for cfg_vin2a_d5_out interface" bitfld.long 0xB04 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB04 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB04 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB08 "CFG_VIN2A_D6_IN,Delay Select Value in binary coded form for cfg_vin2a_d6_in interface" bitfld.long 0xB08 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB08 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB08 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB0C "CFG_VIN2A_D6_OEN,Delay Select Value in binary coded form for cfg_vin2a_d6_oen interface" bitfld.long 0xB0C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB0C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB0C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB10 "CFG_VIN2A_D6_OUT,Delay Select Value in binary coded form for cfg_vin2a_d6_out interface" bitfld.long 0xB10 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB10 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB10 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB14 "CFG_VIN2A_D7_IN,Delay Select Value in binary coded form for cfg_vin2a_d7_in interface" bitfld.long 0xB14 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB14 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB14 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB18 "CFG_VIN2A_D7_OEN,Delay Select Value in binary coded form for cfg_vin2a_d7_oen interface" bitfld.long 0xB18 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB18 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB18 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB1C "CFG_VIN2A_D7_OUT,Delay Select Value in binary coded form for cfg_vin2a_d7_out interface" bitfld.long 0xB1C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB1C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB1C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB20 "CFG_VIN2A_D8_IN,Delay Select Value in binary coded form for cfg_vin2a_d8_in interface" bitfld.long 0xB20 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB20 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB20 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB24 "CFG_VIN2A_D8_OEN,Delay Select Value in binary coded form for cfg_vin2a_d8_oen interface" bitfld.long 0xB24 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB24 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB24 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB28 "CFG_VIN2A_D8_OUT,Delay Select Value in binary coded form for cfg_vin2a_d8_out interface" bitfld.long 0xB28 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB28 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB28 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB2C "CFG_VIN2A_D9_IN,Delay Select Value in binary coded form for cfg_vin2a_d9_in interface" bitfld.long 0xB2C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB2C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB2C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB30 "CFG_VIN2A_D9_OEN,Delay Select Value in binary coded form for cfg_vin2a_d9_oen interface" bitfld.long 0xB30 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB30 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB30 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB34 "CFG_VIN2A_D9_OUT,Delay Select Value in binary coded form for cfg_vin2a_d9_out interface" bitfld.long 0xB34 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB34 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB34 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB38 "CFG_VIN2A_DE0_IN,Delay Select Value in binary coded form for cfg_vin2a_de0_in interface" bitfld.long 0xB38 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB38 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB38 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB3C "CFG_VIN2A_DE0_OEN,Delay Select Value in binary coded form for cfg_vin2a_de0_oen interface" bitfld.long 0xB3C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB3C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB3C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB40 "CFG_VIN2A_DE0_OUT,Delay Select Value in binary coded form for cfg_vin2a_de0_out interface" bitfld.long 0xB40 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB40 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB40 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB44 "CFG_VIN2A_FLD0_IN,Delay Select Value in binary coded form for cfg_vin2a_fld0_in interface" bitfld.long 0xB44 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB44 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB44 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB48 "CFG_VIN2A_FLD0_OEN,Delay Select Value in binary coded form for cfg_vin2a_fld0_oen interface" bitfld.long 0xB48 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB48 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB48 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB4C "CFG_VIN2A_FLD0_OUT,Delay Select Value in binary coded form for cfg_vin2a_fld0_out interface" bitfld.long 0xB4C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB4C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB4C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB50 "CFG_VIN2A_HSYNC0_IN,Delay Select Value in binary coded form for cfg_vin2a_hsync0_in interface" bitfld.long 0xB50 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB50 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB50 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB54 "CFG_VIN2A_HSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin2a_hsync0_oen interface" bitfld.long 0xB54 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB54 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB54 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB58 "CFG_VIN2A_HSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin2a_hsync0_out interface" bitfld.long 0xB58 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB58 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB58 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB5C "CFG_VIN2A_VSYNC0_IN,Delay Select Value in binary coded form for cfg_vin2a_vsync0_in interface" bitfld.long 0xB5C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB5C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB5C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB60 "CFG_VIN2A_VSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin2a_vsync0_oen interface" bitfld.long 0xB60 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB60 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB60 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB64 "CFG_VIN2A_VSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin2a_vsync0_out interface" bitfld.long 0xB64 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB64 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB64 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB68 "CFG_VOUT1_CLK_IN,Delay Select Value in binary coded form for cfg_vout1_clk_in interface" bitfld.long 0xB68 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB68 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB68 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB6C "CFG_VOUT1_CLK_OEN,Delay Select Value in binary coded form for cfg_vout1_clk_oen interface" bitfld.long 0xB6C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB6C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB6C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB70 "CFG_VOUT1_CLK_OUT,Delay Select Value in binary coded form for cfg_vout1_clk_out interface" bitfld.long 0xB70 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB70 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB70 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB74 "CFG_VOUT1_D0_IN,Delay Select Value in binary coded form for cfg_vout1_d0_in interface" bitfld.long 0xB74 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB74 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB74 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB78 "CFG_VOUT1_D0_OEN,Delay Select Value in binary coded form for cfg_vout1_d0_oen interface" bitfld.long 0xB78 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB78 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB78 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB7C "CFG_VOUT1_D0_OUT,Delay Select Value in binary coded form for cfg_vout1_d0_out interface" bitfld.long 0xB7C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB7C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB7C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB80 "CFG_VOUT1_D10_IN,Delay Select Value in binary coded form for cfg_vout1_d10_in interface" bitfld.long 0xB80 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB80 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB80 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB84 "CFG_VOUT1_D10_OEN,Delay Select Value in binary coded form for cfg_vout1_d10_oen interface" bitfld.long 0xB84 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB84 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB84 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB88 "CFG_VOUT1_D10_OUT,Delay Select Value in binary coded form for cfg_vout1_d10_out interface" bitfld.long 0xB88 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB88 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB88 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB8C "CFG_VOUT1_D11_IN,Delay Select Value in binary coded form for cfg_vout1_d11_in interface" bitfld.long 0xB8C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB8C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB8C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB90 "CFG_VOUT1_D11_OEN,Delay Select Value in binary coded form for cfg_vout1_d11_oen interface" bitfld.long 0xB90 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB90 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB90 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB94 "CFG_VOUT1_D11_OUT,Delay Select Value in binary coded form for cfg_vout1_d11_out interface" bitfld.long 0xB94 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB94 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB94 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB98 "CFG_VOUT1_D12_IN,Delay Select Value in binary coded form for cfg_vout1_d12_in interface" bitfld.long 0xB98 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB98 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB98 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xB9C "CFG_VOUT1_D12_OEN,Delay Select Value in binary coded form for cfg_vout1_d12_oen interface" bitfld.long 0xB9C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xB9C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xB9C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBA0 "CFG_VOUT1_D12_OUT,Delay Select Value in binary coded form for cfg_vout1_d12_out interface" bitfld.long 0xBA0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBA0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBA0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBA4 "CFG_VOUT1_D13_IN,Delay Select Value in binary coded form for cfg_vout1_d13_in interface" bitfld.long 0xBA4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBA4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBA4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBA8 "CFG_VOUT1_D13_OEN,Delay Select Value in binary coded form for cfg_vout1_d13_oen interface" bitfld.long 0xBA8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBA8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBA8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBAC "CFG_VOUT1_D13_OUT,Delay Select Value in binary coded form for cfg_vout1_d13_out interface" bitfld.long 0xBAC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBAC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBAC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBB0 "CFG_VOUT1_D14_IN,Delay Select Value in binary coded form for cfg_vout1_d14_in interface" bitfld.long 0xBB0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBB0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBB0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBB4 "CFG_VOUT1_D14_OEN,Delay Select Value in binary coded form for cfg_vout1_d14_oen interface" bitfld.long 0xBB4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBB4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBB4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBB8 "CFG_VOUT1_D14_OUT,Delay Select Value in binary coded form for cfg_vout1_d14_out interface" bitfld.long 0xBB8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBB8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBB8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBBC "CFG_VOUT1_D15_IN,Delay Select Value in binary coded form for cfg_vout1_d15_in interface" bitfld.long 0xBBC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBBC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBBC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBC0 "CFG_VOUT1_D15_OEN,Delay Select Value in binary coded form for cfg_vout1_d15_oen interface" bitfld.long 0xBC0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBC0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBC4 "CFG_VOUT1_D15_OUT,Delay Select Value in binary coded form for cfg_vout1_d15_out interface" bitfld.long 0xBC4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBC4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBC8 "CFG_VOUT1_D16_IN,Delay Select Value in binary coded form for cfg_vout1_d16_in interface" bitfld.long 0xBC8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBC8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBC8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBCC "CFG_VOUT1_D16_OEN,Delay Select Value in binary coded form for cfg_vout1_d16_oen interface" bitfld.long 0xBCC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBCC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBCC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBD0 "CFG_VOUT1_D16_OUT,Delay Select Value in binary coded form for cfg_vout1_d16_out interface" bitfld.long 0xBD0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBD0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBD0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBD4 "CFG_VOUT1_D17_IN,Delay Select Value in binary coded form for cfg_vout1_d17_in interface" bitfld.long 0xBD4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBD4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBD4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBD8 "CFG_VOUT1_D17_OEN,Delay Select Value in binary coded form for cfg_vout1_d17_oen interface" bitfld.long 0xBD8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBD8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBD8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBDC "CFG_VOUT1_D17_OUT,Delay Select Value in binary coded form for cfg_vout1_d17_out interface" bitfld.long 0xBDC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBDC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBDC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBE0 "CFG_VOUT1_D18_IN,Delay Select Value in binary coded form for cfg_vout1_d18_in interface" bitfld.long 0xBE0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBE0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBE0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBE4 "CFG_VOUT1_D18_OEN,Delay Select Value in binary coded form for cfg_vout1_d18_oen interface" bitfld.long 0xBE4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBE4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBE4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBE8 "CFG_VOUT1_D18_OUT,Delay Select Value in binary coded form for cfg_vout1_d18_out interface" bitfld.long 0xBE8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBE8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBE8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBEC "CFG_VOUT1_D19_IN,Delay Select Value in binary coded form for cfg_vout1_d19_in interface" bitfld.long 0xBEC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBEC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBEC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBF0 "CFG_VOUT1_D19_OEN,Delay Select Value in binary coded form for cfg_vout1_d19_oen interface" bitfld.long 0xBF0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBF0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBF0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBF4 "CFG_VOUT1_D19_OUT,Delay Select Value in binary coded form for cfg_vout1_d19_out interface" bitfld.long 0xBF4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBF4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBF4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBF8 "CFG_VOUT1_D1_IN,Delay Select Value in binary coded form for cfg_vout1_d1_in interface" bitfld.long 0xBF8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBF8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBF8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xBFC "CFG_VOUT1_D1_OEN,Delay Select Value in binary coded form for cfg_vout1_d1_oen interface" bitfld.long 0xBFC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xBFC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xBFC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC00 "CFG_VOUT1_D1_OUT,Delay Select Value in binary coded form for cfg_vout1_d1_out interface" bitfld.long 0xC00 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC00 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC00 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC04 "CFG_VOUT1_D20_IN,Delay Select Value in binary coded form for cfg_vout1_d20_in interface" bitfld.long 0xC04 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC04 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC04 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC08 "CFG_VOUT1_D20_OEN,Delay Select Value in binary coded form for cfg_vout1_d20_oen interface" bitfld.long 0xC08 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC08 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC08 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC0C "CFG_VOUT1_D20_OUT,Delay Select Value in binary coded form for cfg_vout1_d20_out interface" bitfld.long 0xC0C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC0C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC0C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC10 "CFG_VOUT1_D21_IN,Delay Select Value in binary coded form for cfg_vout1_d21_in interface" bitfld.long 0xC10 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC10 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC10 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC14 "CFG_VOUT1_D21_OEN,Delay Select Value in binary coded form for cfg_vout1_d21_oen interface" bitfld.long 0xC14 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC14 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC14 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC18 "CFG_VOUT1_D21_OUT,Delay Select Value in binary coded form for cfg_vout1_d21_out interface" bitfld.long 0xC18 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC18 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC18 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC1C "CFG_VOUT1_D22_IN,Delay Select Value in binary coded form for cfg_vout1_d22_in interface" bitfld.long 0xC1C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC1C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC1C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC20 "CFG_VOUT1_D22_OEN,Delay Select Value in binary coded form for cfg_vout1_d22_oen interface" bitfld.long 0xC20 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC20 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC20 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC24 "CFG_VOUT1_D22_OUT,Delay Select Value in binary coded form for cfg_vout1_d22_out interface" bitfld.long 0xC24 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC24 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC24 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC28 "CFG_VOUT1_D23_IN,Delay Select Value in binary coded form for cfg_vout1_d23_in interface" bitfld.long 0xC28 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC28 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC28 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC2C "CFG_VOUT1_D23_OEN,Delay Select Value in binary coded form for cfg_vout1_d23_oen interface" bitfld.long 0xC2C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC2C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC2C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC30 "CFG_VOUT1_D23_OUT,Delay Select Value in binary coded form for cfg_vout1_d23_out interface" bitfld.long 0xC30 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC30 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC30 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC34 "CFG_VOUT1_D2_IN,Delay Select Value in binary coded form for cfg_vout1_d2_in interface" bitfld.long 0xC34 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC34 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC34 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC38 "CFG_VOUT1_D2_OEN,Delay Select Value in binary coded form for cfg_vout1_d2_oen interface" bitfld.long 0xC38 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC38 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC38 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC3C "CFG_VOUT1_D2_OUT,Delay Select Value in binary coded form for cfg_vout1_d2_out interface" bitfld.long 0xC3C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC3C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC3C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC40 "CFG_VOUT1_D3_IN,Delay Select Value in binary coded form for cfg_vout1_d3_in interface" bitfld.long 0xC40 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC40 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC40 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC44 "CFG_VOUT1_D3_OEN,Delay Select Value in binary coded form for cfg_vout1_d3_oen interface" bitfld.long 0xC44 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC44 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC44 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC48 "CFG_VOUT1_D3_OUT,Delay Select Value in binary coded form for cfg_vout1_d3_out interface" bitfld.long 0xC48 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC48 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC48 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC4C "CFG_VOUT1_D4_IN,Delay Select Value in binary coded form for cfg_vout1_d4_in interface" bitfld.long 0xC4C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC4C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC4C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC50 "CFG_VOUT1_D4_OEN,Delay Select Value in binary coded form for cfg_vout1_d4_oen interface" bitfld.long 0xC50 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC50 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC50 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC54 "CFG_VOUT1_D4_OUT,Delay Select Value in binary coded form for cfg_vout1_d4_out interface" bitfld.long 0xC54 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC54 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC54 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC58 "CFG_VOUT1_D5_IN,Delay Select Value in binary coded form for cfg_vout1_d5_in interface" bitfld.long 0xC58 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC58 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC58 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC5C "CFG_VOUT1_D5_OEN,Delay Select Value in binary coded form for cfg_vout1_d5_oen interface" bitfld.long 0xC5C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC5C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC5C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC60 "CFG_VOUT1_D5_OUT,Delay Select Value in binary coded form for cfg_vout1_d5_out interface" bitfld.long 0xC60 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC60 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC60 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC64 "CFG_VOUT1_D6_IN,Delay Select Value in binary coded form for cfg_vout1_d6_in interface" bitfld.long 0xC64 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC64 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC64 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC68 "CFG_VOUT1_D6_OEN,Delay Select Value in binary coded form for cfg_vout1_d6_oen interface" bitfld.long 0xC68 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC68 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC68 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC6C "CFG_VOUT1_D6_OUT,Delay Select Value in binary coded form for cfg_vout1_d6_out interface" bitfld.long 0xC6C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC6C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC6C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC70 "CFG_VOUT1_D7_IN,Delay Select Value in binary coded form for cfg_vout1_d7_in interface" bitfld.long 0xC70 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC70 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC70 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC74 "CFG_VOUT1_D7_OEN,Delay Select Value in binary coded form for cfg_vout1_d7_oen interface" bitfld.long 0xC74 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC74 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC74 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC78 "CFG_VOUT1_D7_OUT,Delay Select Value in binary coded form for cfg_vout1_d7_out interface" bitfld.long 0xC78 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC78 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC78 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC7C "CFG_VOUT1_D8_IN,Delay Select Value in binary coded form for cfg_vout1_d8_in interface" bitfld.long 0xC7C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC7C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC7C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC80 "CFG_VOUT1_D8_OEN,Delay Select Value in binary coded form for cfg_vout1_d8_oen interface" bitfld.long 0xC80 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC80 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC80 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC84 "CFG_VOUT1_D8_OUT,Delay Select Value in binary coded form for cfg_vout1_d8_out interface" bitfld.long 0xC84 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC84 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC84 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC88 "CFG_VOUT1_D9_IN,Delay Select Value in binary coded form for cfg_vout1_d9_in interface" bitfld.long 0xC88 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC88 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC88 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC8C "CFG_VOUT1_D9_OEN,Delay Select Value in binary coded form for cfg_vout1_d9_oen interface" bitfld.long 0xC8C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC8C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC90 "CFG_VOUT1_D9_OUT,Delay Select Value in binary coded form for cfg_vout1_d9_out interface" bitfld.long 0xC90 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC90 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC90 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC94 "CFG_VOUT1_DE_IN,Delay Select Value in binary coded form for cfg_vout1_de_in interface" bitfld.long 0xC94 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC94 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC94 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC98 "CFG_VOUT1_DE_OEN,Delay Select Value in binary coded form for cfg_vout1_de_oen interface" bitfld.long 0xC98 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC98 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC98 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xC9C "CFG_VOUT1_DE_OUT,Delay Select Value in binary coded form for cfg_vout1_de_out interface" bitfld.long 0xC9C 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC9C 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xC9C 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCA0 "CFG_VOUT1_FLD_IN,Delay Select Value in binary coded form for cfg_vout1_fld_in interface" bitfld.long 0xCA0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCA0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCA0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCA4 "CFG_VOUT1_FLD_OEN,Delay Select Value in binary coded form for cfg_vout1_fld_oen interface" bitfld.long 0xCA4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCA4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCA4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCA8 "CFG_VOUT1_FLD_OUT,Delay Select Value in binary coded form for cfg_vout1_fld_out interface" bitfld.long 0xCA8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCA8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCA8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCAC "CFG_VOUT1_HSYNC_IN,Delay Select Value in binary coded form for cfg_vout1_hsync_in interface" bitfld.long 0xCAC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCAC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCAC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCB0 "CFG_VOUT1_HSYNC_OEN,Delay Select Value in binary coded form for cfg_vout1_hsync_oen interface" bitfld.long 0xCB0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCB0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCB0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCB4 "CFG_VOUT1_HSYNC_OUT,Delay Select Value in binary coded form for cfg_vout1_hsync_out interface" bitfld.long 0xCB4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCB4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCB4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCB8 "CFG_VOUT1_VSYNC_IN,Delay Select Value in binary coded form for cfg_vout1_vsync_in interface" bitfld.long 0xCB8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCB8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCB8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCBC "CFG_VOUT1_VSYNC_OEN,Delay Select Value in binary coded form for cfg_vout1_vsync_oen interface" bitfld.long 0xCBC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCBC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCBC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCC0 "CFG_VOUT1_VSYNC_OUT,Delay Select Value in binary coded form for cfg_vout1_vsync_out interface" bitfld.long 0xCC0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCC0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCC4 "CFG_XREF_CLK0_IN,Delay Select Value in binary coded form for cfg_xref_clk0_in interface" bitfld.long 0xCC4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCC4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCC8 "CFG_XREF_CLK0_OEN,Delay Select Value in binary coded form for cfg_xref_clk0_oen interface" bitfld.long 0xCC8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCC8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCC8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCCC "CFG_XREF_CLK0_OUT,Delay Select Value in binary coded form for cfg_xref_clk0_out interface" bitfld.long 0xCCC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCCC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCCC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCD0 "CFG_XREF_CLK1_IN,Delay Select Value in binary coded form for cfg_xref_clk1_in interface" bitfld.long 0xCD0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCD0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCD0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCD4 "CFG_XREF_CLK1_OEN,Delay Select Value in binary coded form for cfg_xref_clk1_oen interface" bitfld.long 0xCD4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCD4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCD4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCD8 "CFG_XREF_CLK1_OUT,Delay Select Value in binary coded form for cfg_xref_clk1_out interface" bitfld.long 0xCD8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCD8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCD8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCDC "CFG_XREF_CLK2_IN,Delay Select Value in binary coded form for cfg_xref_clk2_in interface" bitfld.long 0xCDC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCDC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCDC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCE0 "CFG_XREF_CLK2_OEN,Delay Select Value in binary coded form for cfg_xref_clk2_oen interface" bitfld.long 0xCE0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCE0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCE0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCE4 "CFG_XREF_CLK2_OUT,Delay Select Value in binary coded form for cfg_xref_clk2_out interface" bitfld.long 0xCE4 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCE4 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCE4 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCE8 "CFG_XREF_CLK3_IN,Delay Select Value in binary coded form for cfg_xref_clk3_in interface" bitfld.long 0xCE8 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCE8 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCE8 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCEC "CFG_XREF_CLK3_OEN,Delay Select Value in binary coded form for cfg_xref_clk3_oen interface" bitfld.long 0xCEC 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCEC 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCEC 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" line.long 0xCF0 "CFG_XREF_CLK3_OUT,Delay Select Value in binary coded form for cfg_xref_clk3_out interface" bitfld.long 0xCF0 12.--17. "SIGNATURE,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xCF0 10. "LOCK_BIT,When '1' prevents HW update to this MMR" "0,1" hexmask.long.word 0xCF0 0.--9. 1. "BINARY_DELAY,Delay Select Value in binary coded form" width 0x0B tree.end tree "ISS_Image_Signal_Processor" tree "ISP6P5_GLBCE" base ad:0x52051000 group.long 0x00++0x0B line.long 0x00 "GLBCE_CFG,GLBCE Configuration Registers" bitfld.long 0x00 0. "SWRST,This bit initiate software reset process - OFF" "SWRST_0,SWRST_1" line.long 0x04 "GLBCE_MODE," bitfld.long 0x04 0. "OST,One shot mode or continuous mode" "OST_0,OST_1" line.long 0x08 "GLBCE_CONTROL0,GLBCE Configuration Port GLBCE Control Register 0 (control_0)" bitfld.long 0x08 4. "CCTL,Color Control (CCTL) - Enabling this processing will result in more accurate colors processing" "Disable color correction,Enable color correction" newline bitfld.long 0x08 3. "MB,Max Bayer Type- Use this bit to select the algorithm used for calculating intensity" "Algorithm 1,Algorithm 2 (Recommended) -.." newline bitfld.long 0x08 0. "ONOFF,GLBCE On/Off - This bit turns GLBCE processing ON and OFF" "Disable GLBCE processing,Enable GLBCE processing - OFF" hgroup.long 0x0C++0x03 hide.long 0x00 "GLBCE_CONTROL1,GLBCE Configuration Port" group.long 0x10++0x6CB line.long 0x00 "GLBCE_BLACK_LEVEL,GLBCE Configuration Port Black Level Register (black_level)" hexmask.long.word 0x00 0.--15. 1. "VAL,The value stored in Black Level Port will be used as zero level for GLBCE processing in all unsigned data channels" line.long 0x04 "GLBCE_WHITE_LEVEL,GLBCE Configuration Port White Level Register (white_level)" hexmask.long.word 0x04 0.--15. 1. "VAL,The value stored in White Level Port will be used as white level for GLBCE processing in all unsigned data channels" line.long 0x08 "GLBCE_VARIANCE,GLBCE Configuration Port Affects the sensitivity of the transform to different areas of the image. and can be increased in order to emphasize small regions (e.g. faces)" bitfld.long 0x08 4.--7. "VARIANCEINTENSITY,Variance Intensity - Sets the degree of sensitivity in the luminance domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "VARIANCESPACE,Variance Space - Sets the degree of spatial sensitivity of the algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "GLBCE_LIMIT_AMPL,GLBCE Configuration Port The parameters ? dark amplification limit ? bright amplification limit are used to restrict the luminance space in which GLBCE can adaptively generate tone curves for each pixel" bitfld.long 0x0C 4.--7. "BRIGHTAMPLIFICATIONLIMIT,Bright amplification limit - The resultant tone curve cannot be lower than bright amplification limit line controlled by the bright amplification limit parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "DARKAMPLIFICATIONLIMIT,Dark amplification limit - The resultant tone curve cannot be higher than dark amplification limit line controlled by the dark amplification limit parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "GLBCE_DITHER,GLBCE Configuration Port Dithering Register (dither)" bitfld.long 0x10 0.--2. "DITHER," "?,One least significant bit of the output signal..,Two bits are dithered,Three bits are dithered,Four bits are dithered All other values,?..." line.long 0x14 "GLBCE_SLOPE_MAX,GLBCE Configuration Port Slope Max Limit Register (slope_max)" hexmask.long.byte 0x14 0.--7. 1. "SLOPEMAXLIMIT,Slope Max Limit - Slope Max Limit is used to restrict the slope of the tone-curve generated by GLBCE" line.long 0x18 "GLBCE_SLOPE_MIN,GLBCE Configuration Port Slope Min Limit Register (slope_min)" hexmask.long.byte 0x18 0.--7. 1. "SLOPEMINLIMIT,Slope Min Limit - Slope Min Limit is used to restrict the slope of the tone-curve generated by GLBCE" line.long 0x1C "GLBCE_LUT_FI_00,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x1C 0.--15. 1. "VAL," line.long 0x20 "GLBCE_LUT_FI_01,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x20 0.--15. 1. "VAL," line.long 0x24 "GLBCE_LUT_FI_02,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x24 0.--15. 1. "VAL," line.long 0x28 "GLBCE_LUT_FI_03,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x28 0.--15. 1. "VAL," line.long 0x2C "GLBCE_LUT_FI_04,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x2C 0.--15. 1. "VAL," line.long 0x30 "GLBCE_LUT_FI_05,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x30 0.--15. 1. "VAL," line.long 0x34 "GLBCE_LUT_FI_06,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x34 0.--15. 1. "VAL," line.long 0x38 "GLBCE_LUT_FI_07,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x38 0.--15. 1. "VAL," line.long 0x3C "GLBCE_LUT_FI_08,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x3C 0.--15. 1. "VAL," line.long 0x40 "GLBCE_LUT_FI_09,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x40 0.--15. 1. "VAL," line.long 0x44 "GLBCE_LUT_FI_10,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x44 0.--15. 1. "VAL," line.long 0x48 "GLBCE_LUT_FI_11,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x48 0.--15. 1. "VAL," line.long 0x4C "GLBCE_LUT_FI_12,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x4C 0.--15. 1. "VAL," line.long 0x50 "GLBCE_LUT_FI_13,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x50 0.--15. 1. "VAL," line.long 0x54 "GLBCE_LUT_FI_14,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x54 0.--15. 1. "VAL," line.long 0x58 "GLBCE_LUT_FI_15,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x58 0.--15. 1. "VAL," line.long 0x5C "GLBCE_LUT_FI_16,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x5C 0.--15. 1. "VAL," line.long 0x60 "GLBCE_LUT_FI_17,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x60 0.--15. 1. "VAL," line.long 0x64 "GLBCE_LUT_FI_18,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x64 0.--15. 1. "VAL," line.long 0x68 "GLBCE_LUT_FI_19,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x68 0.--15. 1. "VAL," line.long 0x6C "GLBCE_LUT_FI_20,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x6C 0.--15. 1. "VAL," line.long 0x70 "GLBCE_LUT_FI_21,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x70 0.--15. 1. "VAL," line.long 0x74 "GLBCE_LUT_FI_22,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x74 0.--15. 1. "VAL," line.long 0x78 "GLBCE_LUT_FI_23,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x78 0.--15. 1. "VAL," line.long 0x7C "GLBCE_LUT_FI_24,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x7C 0.--15. 1. "VAL," line.long 0x80 "GLBCE_LUT_FI_25,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x80 0.--15. 1. "VAL," line.long 0x84 "GLBCE_LUT_FI_26,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x84 0.--15. 1. "VAL," line.long 0x88 "GLBCE_LUT_FI_27,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x88 0.--15. 1. "VAL," line.long 0x8C "GLBCE_LUT_FI_28,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x8C 0.--15. 1. "VAL," line.long 0x90 "GLBCE_LUT_FI_29,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x90 0.--15. 1. "VAL," line.long 0x94 "GLBCE_LUT_FI_30,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x94 0.--15. 1. "VAL," line.long 0x98 "GLBCE_LUT_FI_31,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x98 0.--15. 1. "VAL," line.long 0x9C "GLBCE_LUT_FI_32,GLBCE Configuration Port Asymmetry Function LUT The Asymmetry Function Lookup Table port geometry is 33 words. each of which is 16 bits" hexmask.long.word 0x9C 0.--15. 1. "VAL," line.long 0xA0 "GLBCE_FORMAT_CONTROL_REG0,GLBCE Configuration Port The Data format port specifies the input data format so that the GLBCE core can process the different input data formats This register is reserved for ISS6" bitfld.long 0xA0 0.--1. "DATAFORMAT,This value is reserved" "0,1,2,3" line.long 0xA4 "GLBCE_FORMAT_CONTROL_REG1,GLBCE Configuration Port Control Reg1" bitfld.long 0xA4 7. "AUTOSIZE,This value is read only" "AUTOSIZE_0,AUTOSIZE_1" newline bitfld.long 0xA4 6. "AUTOPOS,This value is read only" "AUTOPOS_0,AUTOPOS_1" newline bitfld.long 0xA4 4.--5. "FCMODE,Field Correction Mode - INTERNAL" "FCMODE_0,FCMODE_1,FCMODE_2,?" newline bitfld.long 0xA4 1. "VSPOL,Vertical Sync Polarity This value is read only" "VSPOL_0,VSPOL_1" newline bitfld.long 0xA4 0. "HSPOL,Horizontal Sync Polarity This value is read only" "HSPOL_0,HSPOL_1" line.long 0xA8 "GLBCE_FRAME_WIDTH,GLBCE Configuration Port Frame Width is the number of pixels in an active line" hexmask.long.word 0xA8 0.--15. 1. "VAL," line.long 0xAC "GLBCE_FRAME_HEIGHT,GLBCE Configuration Port Frame Height is the number of active lines in one field" hexmask.long.word 0xAC 0.--15. 1. "VAL," line.long 0xB0 "GLBCE_STRENGTH_IR,GLBCE Configuration Port Strength (Strength of GLBCE) - This Port sets processing Strength" hexmask.long.byte 0xB0 0.--7. 1. "VAL," line.long 0xB4 "GLBCE_PERCEPT_EN," bitfld.long 0xB4 1. "FWD_EN,- DISABLE" "FWD_EN_0,FWD_EN_1" newline bitfld.long 0xB4 0. "REV_EN,Reverse Perceptual LUT enable[ - DISABLE. - ENABLE" "REV_EN_0,REV_EN_1" line.long 0xB8 "GLBCE_REV_PERCEPT_LUT_00,Reverse Perceptual LUT" hexmask.long.word 0xB8 0.--15. 1. "VAL," line.long 0xBC "GLBCE_REV_PERCEPT_LUT_01,Reverse Perceptual LUT" hexmask.long.word 0xBC 0.--15. 1. "VAL," line.long 0xC0 "GLBCE_REV_PERCEPT_LUT_02,Reverse Perceptual LUT" hexmask.long.word 0xC0 0.--15. 1. "VAL," line.long 0xC4 "GLBCE_REV_PERCEPT_LUT_03,Reverse Perceptual LUT" hexmask.long.word 0xC4 0.--15. 1. "VAL," line.long 0xC8 "GLBCE_REV_PERCEPT_LUT_04,Reverse Perceptual LUT" hexmask.long.word 0xC8 0.--15. 1. "VAL," line.long 0xCC "GLBCE_REV_PERCEPT_LUT_05,Reverse Perceptual LUT" hexmask.long.word 0xCC 0.--15. 1. "VAL," line.long 0xD0 "GLBCE_REV_PERCEPT_LUT_06,Reverse Perceptual LUT" hexmask.long.word 0xD0 0.--15. 1. "VAL," line.long 0xD4 "GLBCE_REV_PERCEPT_LUT_07,Reverse Perceptual LUT" hexmask.long.word 0xD4 0.--15. 1. "VAL," line.long 0xD8 "GLBCE_REV_PERCEPT_LUT_08,Reverse Perceptual LUT" hexmask.long.word 0xD8 0.--15. 1. "VAL," line.long 0xDC "GLBCE_REV_PERCEPT_LUT_09,Reverse Perceptual LUT" hexmask.long.word 0xDC 0.--15. 1. "VAL," line.long 0xE0 "GLBCE_REV_PERCEPT_LUT_10,Reverse Perceptual LUT" hexmask.long.word 0xE0 0.--15. 1. "VAL," line.long 0xE4 "GLBCE_REV_PERCEPT_LUT_11,Reverse Perceptual LUT" hexmask.long.word 0xE4 0.--15. 1. "VAL," line.long 0xE8 "GLBCE_REV_PERCEPT_LUT_12,Reverse Perceptual LUT" hexmask.long.word 0xE8 0.--15. 1. "VAL," line.long 0xEC "GLBCE_REV_PERCEPT_LUT_13,Reverse Perceptual LUT" hexmask.long.word 0xEC 0.--15. 1. "VAL," line.long 0xF0 "GLBCE_REV_PERCEPT_LUT_14,Reverse Perceptual LUT" hexmask.long.word 0xF0 0.--15. 1. "VAL," line.long 0xF4 "GLBCE_REV_PERCEPT_LUT_15,Reverse Perceptual LUT" hexmask.long.word 0xF4 0.--15. 1. "VAL," line.long 0xF8 "GLBCE_REV_PERCEPT_LUT_16,Reverse Perceptual LUT" hexmask.long.word 0xF8 0.--15. 1. "VAL," line.long 0xFC "GLBCE_REV_PERCEPT_LUT_17,Reverse Perceptual LUT" hexmask.long.word 0xFC 0.--15. 1. "VAL," line.long 0x100 "GLBCE_REV_PERCEPT_LUT_18,Reverse Perceptual LUT" hexmask.long.word 0x100 0.--15. 1. "VAL," line.long 0x104 "GLBCE_REV_PERCEPT_LUT_19,Reverse Perceptual LUT" hexmask.long.word 0x104 0.--15. 1. "VAL," line.long 0x108 "GLBCE_REV_PERCEPT_LUT_20,Reverse Perceptual LUT" hexmask.long.word 0x108 0.--15. 1. "VAL," line.long 0x10C "GLBCE_REV_PERCEPT_LUT_21,Reverse Perceptual LUT" hexmask.long.word 0x10C 0.--15. 1. "VAL," line.long 0x110 "GLBCE_REV_PERCEPT_LUT_22,Reverse Perceptual LUT" hexmask.long.word 0x110 0.--15. 1. "VAL," line.long 0x114 "GLBCE_REV_PERCEPT_LUT_23,Reverse Perceptual LUT" hexmask.long.word 0x114 0.--15. 1. "VAL," line.long 0x118 "GLBCE_REV_PERCEPT_LUT_24,Reverse Perceptual LUT" hexmask.long.word 0x118 0.--15. 1. "VAL," line.long 0x11C "GLBCE_REV_PERCEPT_LUT_25,Reverse Perceptual LUT" hexmask.long.word 0x11C 0.--15. 1. "VAL," line.long 0x120 "GLBCE_REV_PERCEPT_LUT_26,Reverse Perceptual LUT" hexmask.long.word 0x120 0.--15. 1. "VAL," line.long 0x124 "GLBCE_REV_PERCEPT_LUT_27,Reverse Perceptual LUT" hexmask.long.word 0x124 0.--15. 1. "VAL," line.long 0x128 "GLBCE_REV_PERCEPT_LUT_28,Reverse Perceptual LUT" hexmask.long.word 0x128 0.--15. 1. "VAL," line.long 0x12C "GLBCE_REV_PERCEPT_LUT_29,Reverse Perceptual LUT" hexmask.long.word 0x12C 0.--15. 1. "VAL," line.long 0x130 "GLBCE_REV_PERCEPT_LUT_30,Reverse Perceptual LUT" hexmask.long.word 0x130 0.--15. 1. "VAL," line.long 0x134 "GLBCE_REV_PERCEPT_LUT_31,Reverse Perceptual LUT" hexmask.long.word 0x134 0.--15. 1. "VAL," line.long 0x138 "GLBCE_REV_PERCEPT_LUT_32,Reverse Perceptual LUT" hexmask.long.word 0x138 0.--15. 1. "VAL," line.long 0x13C "GLBCE_REV_PERCEPT_LUT_33,Reverse Perceptual LUT" hexmask.long.word 0x13C 0.--15. 1. "VAL," line.long 0x140 "GLBCE_REV_PERCEPT_LUT_34,Reverse Perceptual LUT" hexmask.long.word 0x140 0.--15. 1. "VAL," line.long 0x144 "GLBCE_REV_PERCEPT_LUT_35,Reverse Perceptual LUT" hexmask.long.word 0x144 0.--15. 1. "VAL," line.long 0x148 "GLBCE_REV_PERCEPT_LUT_36,Reverse Perceptual LUT" hexmask.long.word 0x148 0.--15. 1. "VAL," line.long 0x14C "GLBCE_REV_PERCEPT_LUT_37,Reverse Perceptual LUT" hexmask.long.word 0x14C 0.--15. 1. "VAL," line.long 0x150 "GLBCE_REV_PERCEPT_LUT_38,Reverse Perceptual LUT" hexmask.long.word 0x150 0.--15. 1. "VAL," line.long 0x154 "GLBCE_REV_PERCEPT_LUT_39,Reverse Perceptual LUT" hexmask.long.word 0x154 0.--15. 1. "VAL," line.long 0x158 "GLBCE_REV_PERCEPT_LUT_40,Reverse Perceptual LUT" hexmask.long.word 0x158 0.--15. 1. "VAL," line.long 0x15C "GLBCE_REV_PERCEPT_LUT_41,Reverse Perceptual LUT" hexmask.long.word 0x15C 0.--15. 1. "VAL," line.long 0x160 "GLBCE_REV_PERCEPT_LUT_42,Reverse Perceptual LUT" hexmask.long.word 0x160 0.--15. 1. "VAL," line.long 0x164 "GLBCE_REV_PERCEPT_LUT_43,Reverse Perceptual LUT" hexmask.long.word 0x164 0.--15. 1. "VAL," line.long 0x168 "GLBCE_REV_PERCEPT_LUT_44,Reverse Perceptual LUT" hexmask.long.word 0x168 0.--15. 1. "VAL," line.long 0x16C "GLBCE_REV_PERCEPT_LUT_45,Reverse Perceptual LUT" hexmask.long.word 0x16C 0.--15. 1. "VAL," line.long 0x170 "GLBCE_REV_PERCEPT_LUT_46,Reverse Perceptual LUT" hexmask.long.word 0x170 0.--15. 1. "VAL," line.long 0x174 "GLBCE_REV_PERCEPT_LUT_47,Reverse Perceptual LUT" hexmask.long.word 0x174 0.--15. 1. "VAL," line.long 0x178 "GLBCE_REV_PERCEPT_LUT_48,Reverse Perceptual LUT" hexmask.long.word 0x178 0.--15. 1. "VAL," line.long 0x17C "GLBCE_REV_PERCEPT_LUT_49,Reverse Perceptual LUT" hexmask.long.word 0x17C 0.--15. 1. "VAL," line.long 0x180 "GLBCE_REV_PERCEPT_LUT_50,Reverse Perceptual LUT" hexmask.long.word 0x180 0.--15. 1. "VAL," line.long 0x184 "GLBCE_REV_PERCEPT_LUT_51,Reverse Perceptual LUT" hexmask.long.word 0x184 0.--15. 1. "VAL," line.long 0x188 "GLBCE_REV_PERCEPT_LUT_52,Reverse Perceptual LUT" hexmask.long.word 0x188 0.--15. 1. "VAL," line.long 0x18C "GLBCE_REV_PERCEPT_LUT_53,Reverse Perceptual LUT" hexmask.long.word 0x18C 0.--15. 1. "VAL," line.long 0x190 "GLBCE_REV_PERCEPT_LUT_54,Reverse Perceptual LUT" hexmask.long.word 0x190 0.--15. 1. "VAL," line.long 0x194 "GLBCE_REV_PERCEPT_LUT_55,Reverse Perceptual LUT" hexmask.long.word 0x194 0.--15. 1. "VAL," line.long 0x198 "GLBCE_REV_PERCEPT_LUT_56,Reverse Perceptual LUT" hexmask.long.word 0x198 0.--15. 1. "VAL," line.long 0x19C "GLBCE_REV_PERCEPT_LUT_57,Reverse Perceptual LUT" hexmask.long.word 0x19C 0.--15. 1. "VAL," line.long 0x1A0 "GLBCE_REV_PERCEPT_LUT_58,Reverse Perceptual LUT" hexmask.long.word 0x1A0 0.--15. 1. "VAL," line.long 0x1A4 "GLBCE_REV_PERCEPT_LUT_59,Reverse Perceptual LUT" hexmask.long.word 0x1A4 0.--15. 1. "VAL," line.long 0x1A8 "GLBCE_REV_PERCEPT_LUT_60,Reverse Perceptual LUT" hexmask.long.word 0x1A8 0.--15. 1. "VAL," line.long 0x1AC "GLBCE_REV_PERCEPT_LUT_61,Reverse Perceptual LUT" hexmask.long.word 0x1AC 0.--15. 1. "VAL," line.long 0x1B0 "GLBCE_REV_PERCEPT_LUT_62,Reverse Perceptual LUT" hexmask.long.word 0x1B0 0.--15. 1. "VAL," line.long 0x1B4 "GLBCE_REV_PERCEPT_LUT_63,Reverse Perceptual LUT" hexmask.long.word 0x1B4 0.--15. 1. "VAL," line.long 0x1B8 "GLBCE_REV_PERCEPT_LUT_64,Reverse Perceptual LUT" hexmask.long.word 0x1B8 0.--15. 1. "VAL," line.long 0x1BC "GLBCE_FWD_PERCEPT_LUT_00," hexmask.long.word 0x1BC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1C0 "GLBCE_FWD_PERCEPT_LUT_01," hexmask.long.word 0x1C0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1C4 "GLBCE_FWD_PERCEPT_LUT_02," hexmask.long.word 0x1C4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1C8 "GLBCE_FWD_PERCEPT_LUT_03," hexmask.long.word 0x1C8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1CC "GLBCE_FWD_PERCEPT_LUT_04," hexmask.long.word 0x1CC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D0 "GLBCE_FWD_PERCEPT_LUT_05," hexmask.long.word 0x1D0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D4 "GLBCE_FWD_PERCEPT_LUT_06," hexmask.long.word 0x1D4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1D8 "GLBCE_FWD_PERCEPT_LUT_07," hexmask.long.word 0x1D8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1DC "GLBCE_FWD_PERCEPT_LUT_08," hexmask.long.word 0x1DC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E0 "GLBCE_FWD_PERCEPT_LUT_09," hexmask.long.word 0x1E0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E4 "GLBCE_FWD_PERCEPT_LUT_10," hexmask.long.word 0x1E4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1E8 "GLBCE_FWD_PERCEPT_LUT_11," hexmask.long.word 0x1E8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1EC "GLBCE_FWD_PERCEPT_LUT_12," hexmask.long.word 0x1EC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F0 "GLBCE_FWD_PERCEPT_LUT_13," hexmask.long.word 0x1F0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F4 "GLBCE_FWD_PERCEPT_LUT_14," hexmask.long.word 0x1F4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1F8 "GLBCE_FWD_PERCEPT_LUT_15," hexmask.long.word 0x1F8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x1FC "GLBCE_FWD_PERCEPT_LUT_16," hexmask.long.word 0x1FC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x200 "GLBCE_FWD_PERCEPT_LUT_17," hexmask.long.word 0x200 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x204 "GLBCE_FWD_PERCEPT_LUT_18," hexmask.long.word 0x204 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x208 "GLBCE_FWD_PERCEPT_LUT_19," hexmask.long.word 0x208 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x20C "GLBCE_FWD_PERCEPT_LUT_20," hexmask.long.word 0x20C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x210 "GLBCE_FWD_PERCEPT_LUT_21," hexmask.long.word 0x210 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x214 "GLBCE_FWD_PERCEPT_LUT_22," hexmask.long.word 0x214 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x218 "GLBCE_FWD_PERCEPT_LUT_23," hexmask.long.word 0x218 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x21C "GLBCE_FWD_PERCEPT_LUT_24," hexmask.long.word 0x21C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x220 "GLBCE_FWD_PERCEPT_LUT_25," hexmask.long.word 0x220 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x224 "GLBCE_FWD_PERCEPT_LUT_26," hexmask.long.word 0x224 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x228 "GLBCE_FWD_PERCEPT_LUT_27," hexmask.long.word 0x228 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x22C "GLBCE_FWD_PERCEPT_LUT_28," hexmask.long.word 0x22C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x230 "GLBCE_FWD_PERCEPT_LUT_29," hexmask.long.word 0x230 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x234 "GLBCE_FWD_PERCEPT_LUT_30," hexmask.long.word 0x234 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x238 "GLBCE_FWD_PERCEPT_LUT_31," hexmask.long.word 0x238 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x23C "GLBCE_FWD_PERCEPT_LUT_32," hexmask.long.word 0x23C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x240 "GLBCE_FWD_PERCEPT_LUT_33," hexmask.long.word 0x240 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x244 "GLBCE_FWD_PERCEPT_LUT_34," hexmask.long.word 0x244 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x248 "GLBCE_FWD_PERCEPT_LUT_35," hexmask.long.word 0x248 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x24C "GLBCE_FWD_PERCEPT_LUT_36," hexmask.long.word 0x24C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x250 "GLBCE_FWD_PERCEPT_LUT_37," hexmask.long.word 0x250 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x254 "GLBCE_FWD_PERCEPT_LUT_38," hexmask.long.word 0x254 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x258 "GLBCE_FWD_PERCEPT_LUT_39," hexmask.long.word 0x258 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x25C "GLBCE_FWD_PERCEPT_LUT_40," hexmask.long.word 0x25C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x260 "GLBCE_FWD_PERCEPT_LUT_41," hexmask.long.word 0x260 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x264 "GLBCE_FWD_PERCEPT_LUT_42," hexmask.long.word 0x264 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x268 "GLBCE_FWD_PERCEPT_LUT_43," hexmask.long.word 0x268 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x26C "GLBCE_FWD_PERCEPT_LUT_44," hexmask.long.word 0x26C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x270 "GLBCE_FWD_PERCEPT_LUT_45," hexmask.long.word 0x270 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x274 "GLBCE_FWD_PERCEPT_LUT_46," hexmask.long.word 0x274 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x278 "GLBCE_FWD_PERCEPT_LUT_47," hexmask.long.word 0x278 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x27C "GLBCE_FWD_PERCEPT_LUT_48," hexmask.long.word 0x27C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x280 "GLBCE_FWD_PERCEPT_LUT_49," hexmask.long.word 0x280 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x284 "GLBCE_FWD_PERCEPT_LUT_50," hexmask.long.word 0x284 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x288 "GLBCE_FWD_PERCEPT_LUT_51," hexmask.long.word 0x288 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x28C "GLBCE_FWD_PERCEPT_LUT_52," hexmask.long.word 0x28C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x290 "GLBCE_FWD_PERCEPT_LUT_53," hexmask.long.word 0x290 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x294 "GLBCE_FWD_PERCEPT_LUT_54," hexmask.long.word 0x294 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x298 "GLBCE_FWD_PERCEPT_LUT_55," hexmask.long.word 0x298 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x29C "GLBCE_FWD_PERCEPT_LUT_56," hexmask.long.word 0x29C 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A0 "GLBCE_FWD_PERCEPT_LUT_57," hexmask.long.word 0x2A0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A4 "GLBCE_FWD_PERCEPT_LUT_58," hexmask.long.word 0x2A4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2A8 "GLBCE_FWD_PERCEPT_LUT_59," hexmask.long.word 0x2A8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2AC "GLBCE_FWD_PERCEPT_LUT_60," hexmask.long.word 0x2AC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B0 "GLBCE_FWD_PERCEPT_LUT_61," hexmask.long.word 0x2B0 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B4 "GLBCE_FWD_PERCEPT_LUT_62," hexmask.long.word 0x2B4 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2B8 "GLBCE_FWD_PERCEPT_LUT_63," hexmask.long.word 0x2B8 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2BC "GLBCE_FWD_PERCEPT_LUT_64," hexmask.long.word 0x2BC 0.--15. 1. "VAL,Forward Perceptual LUT enable" line.long 0x2C0 "GLBCE_WDR_GAMMA_EN," bitfld.long 0x2C0 0. "EN,Frontend WDR LUT enable - DISABLE" "EN_0,EN_1" line.long 0x2C4 "GLBCE_WDR_GAMMA_LUT_00,Frontend WDR LUT" hexmask.long.word 0x2C4 0.--15. 1. "VAL," line.long 0x2C8 "GLBCE_WDR_GAMMA_LUT_01,Frontend WDR LUT" hexmask.long.word 0x2C8 0.--15. 1. "VAL," line.long 0x2CC "GLBCE_WDR_GAMMA_LUT_02,Frontend WDR LUT" hexmask.long.word 0x2CC 0.--15. 1. "VAL," line.long 0x2D0 "GLBCE_WDR_GAMMA_LUT_03,Frontend WDR LUT" hexmask.long.word 0x2D0 0.--15. 1. "VAL," line.long 0x2D4 "GLBCE_WDR_GAMMA_LUT_04,Frontend WDR LUT" hexmask.long.word 0x2D4 0.--15. 1. "VAL," line.long 0x2D8 "GLBCE_WDR_GAMMA_LUT_05,Frontend WDR LUT" hexmask.long.word 0x2D8 0.--15. 1. "VAL," line.long 0x2DC "GLBCE_WDR_GAMMA_LUT_06,Frontend WDR LUT" hexmask.long.word 0x2DC 0.--15. 1. "VAL," line.long 0x2E0 "GLBCE_WDR_GAMMA_LUT_07,Frontend WDR LUT" hexmask.long.word 0x2E0 0.--15. 1. "VAL," line.long 0x2E4 "GLBCE_WDR_GAMMA_LUT_08,Frontend WDR LUT" hexmask.long.word 0x2E4 0.--15. 1. "VAL," line.long 0x2E8 "GLBCE_WDR_GAMMA_LUT_09,Frontend WDR LUT" hexmask.long.word 0x2E8 0.--15. 1. "VAL," line.long 0x2EC "GLBCE_WDR_GAMMA_LUT_10,Frontend WDR LUT" hexmask.long.word 0x2EC 0.--15. 1. "VAL," line.long 0x2F0 "GLBCE_WDR_GAMMA_LUT_11,Frontend WDR LUT" hexmask.long.word 0x2F0 0.--15. 1. "VAL," line.long 0x2F4 "GLBCE_WDR_GAMMA_LUT_12,Frontend WDR LUT" hexmask.long.word 0x2F4 0.--15. 1. "VAL," line.long 0x2F8 "GLBCE_WDR_GAMMA_LUT_13,Frontend WDR LUT" hexmask.long.word 0x2F8 0.--15. 1. "VAL," line.long 0x2FC "GLBCE_WDR_GAMMA_LUT_14,Frontend WDR LUT" hexmask.long.word 0x2FC 0.--15. 1. "VAL," line.long 0x300 "GLBCE_WDR_GAMMA_LUT_15,Frontend WDR LUT" hexmask.long.word 0x300 0.--15. 1. "VAL," line.long 0x304 "GLBCE_WDR_GAMMA_LUT_16,Frontend WDR LUT" hexmask.long.word 0x304 0.--15. 1. "VAL," line.long 0x308 "GLBCE_WDR_GAMMA_LUT_17,Frontend WDR LUT" hexmask.long.word 0x308 0.--15. 1. "VAL," line.long 0x30C "GLBCE_WDR_GAMMA_LUT_18,Frontend WDR LUT" hexmask.long.word 0x30C 0.--15. 1. "VAL," line.long 0x310 "GLBCE_WDR_GAMMA_LUT_19,Frontend WDR LUT" hexmask.long.word 0x310 0.--15. 1. "VAL," line.long 0x314 "GLBCE_WDR_GAMMA_LUT_20,Frontend WDR LUT" hexmask.long.word 0x314 0.--15. 1. "VAL," line.long 0x318 "GLBCE_WDR_GAMMA_LUT_21,Frontend WDR LUT" hexmask.long.word 0x318 0.--15. 1. "VAL," line.long 0x31C "GLBCE_WDR_GAMMA_LUT_22,Frontend WDR LUT" hexmask.long.word 0x31C 0.--15. 1. "VAL," line.long 0x320 "GLBCE_WDR_GAMMA_LUT_23,Frontend WDR LUT" hexmask.long.word 0x320 0.--15. 1. "VAL," line.long 0x324 "GLBCE_WDR_GAMMA_LUT_24,Frontend WDR LUT" hexmask.long.word 0x324 0.--15. 1. "VAL," line.long 0x328 "GLBCE_WDR_GAMMA_LUT_25,Frontend WDR LUT" hexmask.long.word 0x328 0.--15. 1. "VAL," line.long 0x32C "GLBCE_WDR_GAMMA_LUT_26,Frontend WDR LUT" hexmask.long.word 0x32C 0.--15. 1. "VAL," line.long 0x330 "GLBCE_WDR_GAMMA_LUT_27,Frontend WDR LUT" hexmask.long.word 0x330 0.--15. 1. "VAL," line.long 0x334 "GLBCE_WDR_GAMMA_LUT_28,Frontend WDR LUT" hexmask.long.word 0x334 0.--15. 1. "VAL," line.long 0x338 "GLBCE_WDR_GAMMA_LUT_29,Frontend WDR LUT" hexmask.long.word 0x338 0.--15. 1. "VAL," line.long 0x33C "GLBCE_WDR_GAMMA_LUT_30,Frontend WDR LUT" hexmask.long.word 0x33C 0.--15. 1. "VAL," line.long 0x340 "GLBCE_WDR_GAMMA_LUT_31,Frontend WDR LUT" hexmask.long.word 0x340 0.--15. 1. "VAL," line.long 0x344 "GLBCE_WDR_GAMMA_LUT_32,Frontend WDR LUT" hexmask.long.word 0x344 0.--15. 1. "VAL," line.long 0x348 "GLBCE_WDR_GAMMA_LUT_33,Frontend WDR LUT" hexmask.long.word 0x348 0.--15. 1. "VAL," line.long 0x34C "GLBCE_WDR_GAMMA_LUT_34,Frontend WDR LUT" hexmask.long.word 0x34C 0.--15. 1. "VAL," line.long 0x350 "GLBCE_WDR_GAMMA_LUT_35,Frontend WDR LUT" hexmask.long.word 0x350 0.--15. 1. "VAL," line.long 0x354 "GLBCE_WDR_GAMMA_LUT_36,Frontend WDR LUT" hexmask.long.word 0x354 0.--15. 1. "VAL," line.long 0x358 "GLBCE_WDR_GAMMA_LUT_37,Frontend WDR LUT" hexmask.long.word 0x358 0.--15. 1. "VAL," line.long 0x35C "GLBCE_WDR_GAMMA_LUT_38,Frontend WDR LUT" hexmask.long.word 0x35C 0.--15. 1. "VAL," line.long 0x360 "GLBCE_WDR_GAMMA_LUT_39,Frontend WDR LUT" hexmask.long.word 0x360 0.--15. 1. "VAL," line.long 0x364 "GLBCE_WDR_GAMMA_LUT_40,Frontend WDR LUT" hexmask.long.word 0x364 0.--15. 1. "VAL," line.long 0x368 "GLBCE_WDR_GAMMA_LUT_41,Frontend WDR LUT" hexmask.long.word 0x368 0.--15. 1. "VAL," line.long 0x36C "GLBCE_WDR_GAMMA_LUT_42,Frontend WDR LUT" hexmask.long.word 0x36C 0.--15. 1. "VAL," line.long 0x370 "GLBCE_WDR_GAMMA_LUT_43,Frontend WDR LUT" hexmask.long.word 0x370 0.--15. 1. "VAL," line.long 0x374 "GLBCE_WDR_GAMMA_LUT_44,Frontend WDR LUT" hexmask.long.word 0x374 0.--15. 1. "VAL," line.long 0x378 "GLBCE_WDR_GAMMA_LUT_45,Frontend WDR LUT" hexmask.long.word 0x378 0.--15. 1. "VAL," line.long 0x37C "GLBCE_WDR_GAMMA_LUT_46,Frontend WDR LUT" hexmask.long.word 0x37C 0.--15. 1. "VAL," line.long 0x380 "GLBCE_WDR_GAMMA_LUT_47,Frontend WDR LUT" hexmask.long.word 0x380 0.--15. 1. "VAL," line.long 0x384 "GLBCE_WDR_GAMMA_LUT_48,Frontend WDR LUT" hexmask.long.word 0x384 0.--15. 1. "VAL," line.long 0x388 "GLBCE_WDR_GAMMA_LUT_49,Frontend WDR LUT" hexmask.long.word 0x388 0.--15. 1. "VAL," line.long 0x38C "GLBCE_WDR_GAMMA_LUT_50,Frontend WDR LUT" hexmask.long.word 0x38C 0.--15. 1. "VAL," line.long 0x390 "GLBCE_WDR_GAMMA_LUT_51,Frontend WDR LUT" hexmask.long.word 0x390 0.--15. 1. "VAL," line.long 0x394 "GLBCE_WDR_GAMMA_LUT_52,Frontend WDR LUT" hexmask.long.word 0x394 0.--15. 1. "VAL," line.long 0x398 "GLBCE_WDR_GAMMA_LUT_53,Frontend WDR LUT" hexmask.long.word 0x398 0.--15. 1. "VAL," line.long 0x39C "GLBCE_WDR_GAMMA_LUT_54,Frontend WDR LUT" hexmask.long.word 0x39C 0.--15. 1. "VAL," line.long 0x3A0 "GLBCE_WDR_GAMMA_LUT_55,Frontend WDR LUT" hexmask.long.word 0x3A0 0.--15. 1. "VAL," line.long 0x3A4 "GLBCE_WDR_GAMMA_LUT_56,Frontend WDR LUT" hexmask.long.word 0x3A4 0.--15. 1. "VAL," line.long 0x3A8 "GLBCE_WDR_GAMMA_LUT_57,Frontend WDR LUT" hexmask.long.word 0x3A8 0.--15. 1. "VAL," line.long 0x3AC "GLBCE_WDR_GAMMA_LUT_58,Frontend WDR LUT" hexmask.long.word 0x3AC 0.--15. 1. "VAL," line.long 0x3B0 "GLBCE_WDR_GAMMA_LUT_59,Frontend WDR LUT" hexmask.long.word 0x3B0 0.--15. 1. "VAL," line.long 0x3B4 "GLBCE_WDR_GAMMA_LUT_60,Frontend WDR LUT" hexmask.long.word 0x3B4 0.--15. 1. "VAL," line.long 0x3B8 "GLBCE_WDR_GAMMA_LUT_61,Frontend WDR LUT" hexmask.long.word 0x3B8 0.--15. 1. "VAL," line.long 0x3BC "GLBCE_WDR_GAMMA_LUT_62,Frontend WDR LUT" hexmask.long.word 0x3BC 0.--15. 1. "VAL," line.long 0x3C0 "GLBCE_WDR_GAMMA_LUT_63,Frontend WDR LUT" hexmask.long.word 0x3C0 0.--15. 1. "VAL," line.long 0x3C4 "GLBCE_WDR_GAMMA_LUT_64,Frontend WDR LUT" hexmask.long.word 0x3C4 0.--15. 1. "VAL," line.long 0x3C8 "GLBCE_WDR_GAMMA_LUT_65,Frontend WDR LUT" hexmask.long.word 0x3C8 0.--15. 1. "VAL," line.long 0x3CC "GLBCE_WDR_GAMMA_LUT_66,Frontend WDR LUT" hexmask.long.word 0x3CC 0.--15. 1. "VAL," line.long 0x3D0 "GLBCE_WDR_GAMMA_LUT_67,Frontend WDR LUT" hexmask.long.word 0x3D0 0.--15. 1. "VAL," line.long 0x3D4 "GLBCE_WDR_GAMMA_LUT_68,Frontend WDR LUT" hexmask.long.word 0x3D4 0.--15. 1. "VAL," line.long 0x3D8 "GLBCE_WDR_GAMMA_LUT_69,Frontend WDR LUT" hexmask.long.word 0x3D8 0.--15. 1. "VAL," line.long 0x3DC "GLBCE_WDR_GAMMA_LUT_70,Frontend WDR LUT" hexmask.long.word 0x3DC 0.--15. 1. "VAL," line.long 0x3E0 "GLBCE_WDR_GAMMA_LUT_71,Frontend WDR LUT" hexmask.long.word 0x3E0 0.--15. 1. "VAL," line.long 0x3E4 "GLBCE_WDR_GAMMA_LUT_72,Frontend WDR LUT" hexmask.long.word 0x3E4 0.--15. 1. "VAL," line.long 0x3E8 "GLBCE_WDR_GAMMA_LUT_73,Frontend WDR LUT" hexmask.long.word 0x3E8 0.--15. 1. "VAL," line.long 0x3EC "GLBCE_WDR_GAMMA_LUT_74,Frontend WDR LUT" hexmask.long.word 0x3EC 0.--15. 1. "VAL," line.long 0x3F0 "GLBCE_WDR_GAMMA_LUT_75,Frontend WDR LUT" hexmask.long.word 0x3F0 0.--15. 1. "VAL," line.long 0x3F4 "GLBCE_WDR_GAMMA_LUT_76,Frontend WDR LUT" hexmask.long.word 0x3F4 0.--15. 1. "VAL," line.long 0x3F8 "GLBCE_WDR_GAMMA_LUT_77,Frontend WDR LUT" hexmask.long.word 0x3F8 0.--15. 1. "VAL," line.long 0x3FC "GLBCE_WDR_GAMMA_LUT_78,Frontend WDR LUT" hexmask.long.word 0x3FC 0.--15. 1. "VAL," line.long 0x400 "GLBCE_WDR_GAMMA_LUT_79,Frontend WDR LUT" hexmask.long.word 0x400 0.--15. 1. "VAL," line.long 0x404 "GLBCE_WDR_GAMMA_LUT_80,Frontend WDR LUT" hexmask.long.word 0x404 0.--15. 1. "VAL," line.long 0x408 "GLBCE_WDR_GAMMA_LUT_81,Frontend WDR LUT" hexmask.long.word 0x408 0.--15. 1. "VAL," line.long 0x40C "GLBCE_WDR_GAMMA_LUT_82,Frontend WDR LUT" hexmask.long.word 0x40C 0.--15. 1. "VAL," line.long 0x410 "GLBCE_WDR_GAMMA_LUT_83,Frontend WDR LUT" hexmask.long.word 0x410 0.--15. 1. "VAL," line.long 0x414 "GLBCE_WDR_GAMMA_LUT_84,Frontend WDR LUT" hexmask.long.word 0x414 0.--15. 1. "VAL," line.long 0x418 "GLBCE_WDR_GAMMA_LUT_85,Frontend WDR LUT" hexmask.long.word 0x418 0.--15. 1. "VAL," line.long 0x41C "GLBCE_WDR_GAMMA_LUT_86,Frontend WDR LUT" hexmask.long.word 0x41C 0.--15. 1. "VAL," line.long 0x420 "GLBCE_WDR_GAMMA_LUT_87,Frontend WDR LUT" hexmask.long.word 0x420 0.--15. 1. "VAL," line.long 0x424 "GLBCE_WDR_GAMMA_LUT_88,Frontend WDR LUT" hexmask.long.word 0x424 0.--15. 1. "VAL," line.long 0x428 "GLBCE_WDR_GAMMA_LUT_89,Frontend WDR LUT" hexmask.long.word 0x428 0.--15. 1. "VAL," line.long 0x42C "GLBCE_WDR_GAMMA_LUT_90,Frontend WDR LUT" hexmask.long.word 0x42C 0.--15. 1. "VAL," line.long 0x430 "GLBCE_WDR_GAMMA_LUT_91,Frontend WDR LUT" hexmask.long.word 0x430 0.--15. 1. "VAL," line.long 0x434 "GLBCE_WDR_GAMMA_LUT_92,Frontend WDR LUT" hexmask.long.word 0x434 0.--15. 1. "VAL," line.long 0x438 "GLBCE_WDR_GAMMA_LUT_93,Frontend WDR LUT" hexmask.long.word 0x438 0.--15. 1. "VAL," line.long 0x43C "GLBCE_WDR_GAMMA_LUT_94,Frontend WDR LUT" hexmask.long.word 0x43C 0.--15. 1. "VAL," line.long 0x440 "GLBCE_WDR_GAMMA_LUT_95,Frontend WDR LUT" hexmask.long.word 0x440 0.--15. 1. "VAL," line.long 0x444 "GLBCE_WDR_GAMMA_LUT_96,Frontend WDR LUT" hexmask.long.word 0x444 0.--15. 1. "VAL," line.long 0x448 "GLBCE_WDR_GAMMA_LUT_97,Frontend WDR LUT" hexmask.long.word 0x448 0.--15. 1. "VAL," line.long 0x44C "GLBCE_WDR_GAMMA_LUT_98,Frontend WDR LUT" hexmask.long.word 0x44C 0.--15. 1. "VAL," line.long 0x450 "GLBCE_WDR_GAMMA_LUT_99,Frontend WDR LUT" hexmask.long.word 0x450 0.--15. 1. "VAL," line.long 0x454 "GLBCE_WDR_GAMMA_LUT_100,Frontend WDR LUT" hexmask.long.word 0x454 0.--15. 1. "VAL," line.long 0x458 "GLBCE_WDR_GAMMA_LUT_101,Frontend WDR LUT" hexmask.long.word 0x458 0.--15. 1. "VAL," line.long 0x45C "GLBCE_WDR_GAMMA_LUT_102,Frontend WDR LUT" hexmask.long.word 0x45C 0.--15. 1. "VAL," line.long 0x460 "GLBCE_WDR_GAMMA_LUT_103,Frontend WDR LUT" hexmask.long.word 0x460 0.--15. 1. "VAL," line.long 0x464 "GLBCE_WDR_GAMMA_LUT_104,Frontend WDR LUT" hexmask.long.word 0x464 0.--15. 1. "VAL," line.long 0x468 "GLBCE_WDR_GAMMA_LUT_105,Frontend WDR LUT" hexmask.long.word 0x468 0.--15. 1. "VAL," line.long 0x46C "GLBCE_WDR_GAMMA_LUT_106,Frontend WDR LUT" hexmask.long.word 0x46C 0.--15. 1. "VAL," line.long 0x470 "GLBCE_WDR_GAMMA_LUT_107,Frontend WDR LUT" hexmask.long.word 0x470 0.--15. 1. "VAL," line.long 0x474 "GLBCE_WDR_GAMMA_LUT_108,Frontend WDR LUT" hexmask.long.word 0x474 0.--15. 1. "VAL," line.long 0x478 "GLBCE_WDR_GAMMA_LUT_109,Frontend WDR LUT" hexmask.long.word 0x478 0.--15. 1. "VAL," line.long 0x47C "GLBCE_WDR_GAMMA_LUT_110,Frontend WDR LUT" hexmask.long.word 0x47C 0.--15. 1. "VAL," line.long 0x480 "GLBCE_WDR_GAMMA_LUT_111,Frontend WDR LUT" hexmask.long.word 0x480 0.--15. 1. "VAL," line.long 0x484 "GLBCE_WDR_GAMMA_LUT_112,Frontend WDR LUT" hexmask.long.word 0x484 0.--15. 1. "VAL," line.long 0x488 "GLBCE_WDR_GAMMA_LUT_113,Frontend WDR LUT" hexmask.long.word 0x488 0.--15. 1. "VAL," line.long 0x48C "GLBCE_WDR_GAMMA_LUT_114,Frontend WDR LUT" hexmask.long.word 0x48C 0.--15. 1. "VAL," line.long 0x490 "GLBCE_WDR_GAMMA_LUT_115,Frontend WDR LUT" hexmask.long.word 0x490 0.--15. 1. "VAL," line.long 0x494 "GLBCE_WDR_GAMMA_LUT_116,Frontend WDR LUT" hexmask.long.word 0x494 0.--15. 1. "VAL," line.long 0x498 "GLBCE_WDR_GAMMA_LUT_117,Frontend WDR LUT" hexmask.long.word 0x498 0.--15. 1. "VAL," line.long 0x49C "GLBCE_WDR_GAMMA_LUT_118,Frontend WDR LUT" hexmask.long.word 0x49C 0.--15. 1. "VAL," line.long 0x4A0 "GLBCE_WDR_GAMMA_LUT_119,Frontend WDR LUT" hexmask.long.word 0x4A0 0.--15. 1. "VAL," line.long 0x4A4 "GLBCE_WDR_GAMMA_LUT_120,Frontend WDR LUT" hexmask.long.word 0x4A4 0.--15. 1. "VAL," line.long 0x4A8 "GLBCE_WDR_GAMMA_LUT_121,Frontend WDR LUT" hexmask.long.word 0x4A8 0.--15. 1. "VAL," line.long 0x4AC "GLBCE_WDR_GAMMA_LUT_122,Frontend WDR LUT" hexmask.long.word 0x4AC 0.--15. 1. "VAL," line.long 0x4B0 "GLBCE_WDR_GAMMA_LUT_123,Frontend WDR LUT" hexmask.long.word 0x4B0 0.--15. 1. "VAL," line.long 0x4B4 "GLBCE_WDR_GAMMA_LUT_124,Frontend WDR LUT" hexmask.long.word 0x4B4 0.--15. 1. "VAL," line.long 0x4B8 "GLBCE_WDR_GAMMA_LUT_125,Frontend WDR LUT" hexmask.long.word 0x4B8 0.--15. 1. "VAL," line.long 0x4BC "GLBCE_WDR_GAMMA_LUT_126,Frontend WDR LUT" hexmask.long.word 0x4BC 0.--15. 1. "VAL," line.long 0x4C0 "GLBCE_WDR_GAMMA_LUT_127,Frontend WDR LUT" hexmask.long.word 0x4C0 0.--15. 1. "VAL," line.long 0x4C4 "GLBCE_WDR_GAMMA_LUT_128,Frontend WDR LUT" hexmask.long.word 0x4C4 0.--15. 1. "VAL," line.long 0x4C8 "GLBCE_WDR_GAMMA_LUT_129,Frontend WDR LUT" hexmask.long.word 0x4C8 0.--15. 1. "VAL," line.long 0x4CC "GLBCE_WDR_GAMMA_LUT_130,Frontend WDR LUT" hexmask.long.word 0x4CC 0.--15. 1. "VAL," line.long 0x4D0 "GLBCE_WDR_GAMMA_LUT_131,Frontend WDR LUT" hexmask.long.word 0x4D0 0.--15. 1. "VAL," line.long 0x4D4 "GLBCE_WDR_GAMMA_LUT_132,Frontend WDR LUT" hexmask.long.word 0x4D4 0.--15. 1. "VAL," line.long 0x4D8 "GLBCE_WDR_GAMMA_LUT_133,Frontend WDR LUT" hexmask.long.word 0x4D8 0.--15. 1. "VAL," line.long 0x4DC "GLBCE_WDR_GAMMA_LUT_134,Frontend WDR LUT" hexmask.long.word 0x4DC 0.--15. 1. "VAL," line.long 0x4E0 "GLBCE_WDR_GAMMA_LUT_135,Frontend WDR LUT" hexmask.long.word 0x4E0 0.--15. 1. "VAL," line.long 0x4E4 "GLBCE_WDR_GAMMA_LUT_136,Frontend WDR LUT" hexmask.long.word 0x4E4 0.--15. 1. "VAL," line.long 0x4E8 "GLBCE_WDR_GAMMA_LUT_137,Frontend WDR LUT" hexmask.long.word 0x4E8 0.--15. 1. "VAL," line.long 0x4EC "GLBCE_WDR_GAMMA_LUT_138,Frontend WDR LUT" hexmask.long.word 0x4EC 0.--15. 1. "VAL," line.long 0x4F0 "GLBCE_WDR_GAMMA_LUT_139,Frontend WDR LUT" hexmask.long.word 0x4F0 0.--15. 1. "VAL," line.long 0x4F4 "GLBCE_WDR_GAMMA_LUT_140,Frontend WDR LUT" hexmask.long.word 0x4F4 0.--15. 1. "VAL," line.long 0x4F8 "GLBCE_WDR_GAMMA_LUT_141,Frontend WDR LUT" hexmask.long.word 0x4F8 0.--15. 1. "VAL," line.long 0x4FC "GLBCE_WDR_GAMMA_LUT_142,Frontend WDR LUT" hexmask.long.word 0x4FC 0.--15. 1. "VAL," line.long 0x500 "GLBCE_WDR_GAMMA_LUT_143,Frontend WDR LUT" hexmask.long.word 0x500 0.--15. 1. "VAL," line.long 0x504 "GLBCE_WDR_GAMMA_LUT_144,Frontend WDR LUT" hexmask.long.word 0x504 0.--15. 1. "VAL," line.long 0x508 "GLBCE_WDR_GAMMA_LUT_145,Frontend WDR LUT" hexmask.long.word 0x508 0.--15. 1. "VAL," line.long 0x50C "GLBCE_WDR_GAMMA_LUT_146,Frontend WDR LUT" hexmask.long.word 0x50C 0.--15. 1. "VAL," line.long 0x510 "GLBCE_WDR_GAMMA_LUT_147,Frontend WDR LUT" hexmask.long.word 0x510 0.--15. 1. "VAL," line.long 0x514 "GLBCE_WDR_GAMMA_LUT_148,Frontend WDR LUT" hexmask.long.word 0x514 0.--15. 1. "VAL," line.long 0x518 "GLBCE_WDR_GAMMA_LUT_149,Frontend WDR LUT" hexmask.long.word 0x518 0.--15. 1. "VAL," line.long 0x51C "GLBCE_WDR_GAMMA_LUT_150,Frontend WDR LUT" hexmask.long.word 0x51C 0.--15. 1. "VAL," line.long 0x520 "GLBCE_WDR_GAMMA_LUT_151,Frontend WDR LUT" hexmask.long.word 0x520 0.--15. 1. "VAL," line.long 0x524 "GLBCE_WDR_GAMMA_LUT_152,Frontend WDR LUT" hexmask.long.word 0x524 0.--15. 1. "VAL," line.long 0x528 "GLBCE_WDR_GAMMA_LUT_153,Frontend WDR LUT" hexmask.long.word 0x528 0.--15. 1. "VAL," line.long 0x52C "GLBCE_WDR_GAMMA_LUT_154,Frontend WDR LUT" hexmask.long.word 0x52C 0.--15. 1. "VAL," line.long 0x530 "GLBCE_WDR_GAMMA_LUT_155,Frontend WDR LUT" hexmask.long.word 0x530 0.--15. 1. "VAL," line.long 0x534 "GLBCE_WDR_GAMMA_LUT_156,Frontend WDR LUT" hexmask.long.word 0x534 0.--15. 1. "VAL," line.long 0x538 "GLBCE_WDR_GAMMA_LUT_157,Frontend WDR LUT" hexmask.long.word 0x538 0.--15. 1. "VAL," line.long 0x53C "GLBCE_WDR_GAMMA_LUT_158,Frontend WDR LUT" hexmask.long.word 0x53C 0.--15. 1. "VAL," line.long 0x540 "GLBCE_WDR_GAMMA_LUT_159,Frontend WDR LUT" hexmask.long.word 0x540 0.--15. 1. "VAL," line.long 0x544 "GLBCE_WDR_GAMMA_LUT_160,Frontend WDR LUT" hexmask.long.word 0x544 0.--15. 1. "VAL," line.long 0x548 "GLBCE_WDR_GAMMA_LUT_161,Frontend WDR LUT" hexmask.long.word 0x548 0.--15. 1. "VAL," line.long 0x54C "GLBCE_WDR_GAMMA_LUT_162,Frontend WDR LUT" hexmask.long.word 0x54C 0.--15. 1. "VAL," line.long 0x550 "GLBCE_WDR_GAMMA_LUT_163,Frontend WDR LUT" hexmask.long.word 0x550 0.--15. 1. "VAL," line.long 0x554 "GLBCE_WDR_GAMMA_LUT_164,Frontend WDR LUT" hexmask.long.word 0x554 0.--15. 1. "VAL," line.long 0x558 "GLBCE_WDR_GAMMA_LUT_165,Frontend WDR LUT" hexmask.long.word 0x558 0.--15. 1. "VAL," line.long 0x55C "GLBCE_WDR_GAMMA_LUT_166,Frontend WDR LUT" hexmask.long.word 0x55C 0.--15. 1. "VAL," line.long 0x560 "GLBCE_WDR_GAMMA_LUT_167,Frontend WDR LUT" hexmask.long.word 0x560 0.--15. 1. "VAL," line.long 0x564 "GLBCE_WDR_GAMMA_LUT_168,Frontend WDR LUT" hexmask.long.word 0x564 0.--15. 1. "VAL," line.long 0x568 "GLBCE_WDR_GAMMA_LUT_169,Frontend WDR LUT" hexmask.long.word 0x568 0.--15. 1. "VAL," line.long 0x56C "GLBCE_WDR_GAMMA_LUT_170,Frontend WDR LUT" hexmask.long.word 0x56C 0.--15. 1. "VAL," line.long 0x570 "GLBCE_WDR_GAMMA_LUT_171,Frontend WDR LUT" hexmask.long.word 0x570 0.--15. 1. "VAL," line.long 0x574 "GLBCE_WDR_GAMMA_LUT_172,Frontend WDR LUT" hexmask.long.word 0x574 0.--15. 1. "VAL," line.long 0x578 "GLBCE_WDR_GAMMA_LUT_173,Frontend WDR LUT" hexmask.long.word 0x578 0.--15. 1. "VAL," line.long 0x57C "GLBCE_WDR_GAMMA_LUT_174,Frontend WDR LUT" hexmask.long.word 0x57C 0.--15. 1. "VAL," line.long 0x580 "GLBCE_WDR_GAMMA_LUT_175,Frontend WDR LUT" hexmask.long.word 0x580 0.--15. 1. "VAL," line.long 0x584 "GLBCE_WDR_GAMMA_LUT_176,Frontend WDR LUT" hexmask.long.word 0x584 0.--15. 1. "VAL," line.long 0x588 "GLBCE_WDR_GAMMA_LUT_177,Frontend WDR LUT" hexmask.long.word 0x588 0.--15. 1. "VAL," line.long 0x58C "GLBCE_WDR_GAMMA_LUT_178,Frontend WDR LUT" hexmask.long.word 0x58C 0.--15. 1. "VAL," line.long 0x590 "GLBCE_WDR_GAMMA_LUT_179,Frontend WDR LUT" hexmask.long.word 0x590 0.--15. 1. "VAL," line.long 0x594 "GLBCE_WDR_GAMMA_LUT_180,Frontend WDR LUT" hexmask.long.word 0x594 0.--15. 1. "VAL," line.long 0x598 "GLBCE_WDR_GAMMA_LUT_181,Frontend WDR LUT" hexmask.long.word 0x598 0.--15. 1. "VAL," line.long 0x59C "GLBCE_WDR_GAMMA_LUT_182,Frontend WDR LUT" hexmask.long.word 0x59C 0.--15. 1. "VAL," line.long 0x5A0 "GLBCE_WDR_GAMMA_LUT_183,Frontend WDR LUT" hexmask.long.word 0x5A0 0.--15. 1. "VAL," line.long 0x5A4 "GLBCE_WDR_GAMMA_LUT_184,Frontend WDR LUT" hexmask.long.word 0x5A4 0.--15. 1. "VAL," line.long 0x5A8 "GLBCE_WDR_GAMMA_LUT_185,Frontend WDR LUT" hexmask.long.word 0x5A8 0.--15. 1. "VAL," line.long 0x5AC "GLBCE_WDR_GAMMA_LUT_186,Frontend WDR LUT" hexmask.long.word 0x5AC 0.--15. 1. "VAL," line.long 0x5B0 "GLBCE_WDR_GAMMA_LUT_187,Frontend WDR LUT" hexmask.long.word 0x5B0 0.--15. 1. "VAL," line.long 0x5B4 "GLBCE_WDR_GAMMA_LUT_188,Frontend WDR LUT" hexmask.long.word 0x5B4 0.--15. 1. "VAL," line.long 0x5B8 "GLBCE_WDR_GAMMA_LUT_189,Frontend WDR LUT" hexmask.long.word 0x5B8 0.--15. 1. "VAL," line.long 0x5BC "GLBCE_WDR_GAMMA_LUT_190,Frontend WDR LUT" hexmask.long.word 0x5BC 0.--15. 1. "VAL," line.long 0x5C0 "GLBCE_WDR_GAMMA_LUT_191,Frontend WDR LUT" hexmask.long.word 0x5C0 0.--15. 1. "VAL," line.long 0x5C4 "GLBCE_WDR_GAMMA_LUT_192,Frontend WDR LUT" hexmask.long.word 0x5C4 0.--15. 1. "VAL," line.long 0x5C8 "GLBCE_WDR_GAMMA_LUT_193,Frontend WDR LUT" hexmask.long.word 0x5C8 0.--15. 1. "VAL," line.long 0x5CC "GLBCE_WDR_GAMMA_LUT_194,Frontend WDR LUT" hexmask.long.word 0x5CC 0.--15. 1. "VAL," line.long 0x5D0 "GLBCE_WDR_GAMMA_LUT_195,Frontend WDR LUT" hexmask.long.word 0x5D0 0.--15. 1. "VAL," line.long 0x5D4 "GLBCE_WDR_GAMMA_LUT_196,Frontend WDR LUT" hexmask.long.word 0x5D4 0.--15. 1. "VAL," line.long 0x5D8 "GLBCE_WDR_GAMMA_LUT_197,Frontend WDR LUT" hexmask.long.word 0x5D8 0.--15. 1. "VAL," line.long 0x5DC "GLBCE_WDR_GAMMA_LUT_198,Frontend WDR LUT" hexmask.long.word 0x5DC 0.--15. 1. "VAL," line.long 0x5E0 "GLBCE_WDR_GAMMA_LUT_199,Frontend WDR LUT" hexmask.long.word 0x5E0 0.--15. 1. "VAL," line.long 0x5E4 "GLBCE_WDR_GAMMA_LUT_200,Frontend WDR LUT" hexmask.long.word 0x5E4 0.--15. 1. "VAL," line.long 0x5E8 "GLBCE_WDR_GAMMA_LUT_201,Frontend WDR LUT" hexmask.long.word 0x5E8 0.--15. 1. "VAL," line.long 0x5EC "GLBCE_WDR_GAMMA_LUT_202,Frontend WDR LUT" hexmask.long.word 0x5EC 0.--15. 1. "VAL," line.long 0x5F0 "GLBCE_WDR_GAMMA_LUT_203,Frontend WDR LUT" hexmask.long.word 0x5F0 0.--15. 1. "VAL," line.long 0x5F4 "GLBCE_WDR_GAMMA_LUT_204,Frontend WDR LUT" hexmask.long.word 0x5F4 0.--15. 1. "VAL," line.long 0x5F8 "GLBCE_WDR_GAMMA_LUT_205,Frontend WDR LUT" hexmask.long.word 0x5F8 0.--15. 1. "VAL," line.long 0x5FC "GLBCE_WDR_GAMMA_LUT_206,Frontend WDR LUT" hexmask.long.word 0x5FC 0.--15. 1. "VAL," line.long 0x600 "GLBCE_WDR_GAMMA_LUT_207,Frontend WDR LUT" hexmask.long.word 0x600 0.--15. 1. "VAL," line.long 0x604 "GLBCE_WDR_GAMMA_LUT_208,Frontend WDR LUT" hexmask.long.word 0x604 0.--15. 1. "VAL," line.long 0x608 "GLBCE_WDR_GAMMA_LUT_209,Frontend WDR LUT" hexmask.long.word 0x608 0.--15. 1. "VAL," line.long 0x60C "GLBCE_WDR_GAMMA_LUT_210,Frontend WDR LUT" hexmask.long.word 0x60C 0.--15. 1. "VAL," line.long 0x610 "GLBCE_WDR_GAMMA_LUT_211,Frontend WDR LUT" hexmask.long.word 0x610 0.--15. 1. "VAL," line.long 0x614 "GLBCE_WDR_GAMMA_LUT_212,Frontend WDR LUT" hexmask.long.word 0x614 0.--15. 1. "VAL," line.long 0x618 "GLBCE_WDR_GAMMA_LUT_213,Frontend WDR LUT" hexmask.long.word 0x618 0.--15. 1. "VAL," line.long 0x61C "GLBCE_WDR_GAMMA_LUT_214,Frontend WDR LUT" hexmask.long.word 0x61C 0.--15. 1. "VAL," line.long 0x620 "GLBCE_WDR_GAMMA_LUT_215,Frontend WDR LUT" hexmask.long.word 0x620 0.--15. 1. "VAL," line.long 0x624 "GLBCE_WDR_GAMMA_LUT_216,Frontend WDR LUT" hexmask.long.word 0x624 0.--15. 1. "VAL," line.long 0x628 "GLBCE_WDR_GAMMA_LUT_217,Frontend WDR LUT" hexmask.long.word 0x628 0.--15. 1. "VAL," line.long 0x62C "GLBCE_WDR_GAMMA_LUT_218,Frontend WDR LUT" hexmask.long.word 0x62C 0.--15. 1. "VAL," line.long 0x630 "GLBCE_WDR_GAMMA_LUT_219,Frontend WDR LUT" hexmask.long.word 0x630 0.--15. 1. "VAL," line.long 0x634 "GLBCE_WDR_GAMMA_LUT_220,Frontend WDR LUT" hexmask.long.word 0x634 0.--15. 1. "VAL," line.long 0x638 "GLBCE_WDR_GAMMA_LUT_221,Frontend WDR LUT" hexmask.long.word 0x638 0.--15. 1. "VAL," line.long 0x63C "GLBCE_WDR_GAMMA_LUT_222,Frontend WDR LUT" hexmask.long.word 0x63C 0.--15. 1. "VAL," line.long 0x640 "GLBCE_WDR_GAMMA_LUT_223,Frontend WDR LUT" hexmask.long.word 0x640 0.--15. 1. "VAL," line.long 0x644 "GLBCE_WDR_GAMMA_LUT_224,Frontend WDR LUT" hexmask.long.word 0x644 0.--15. 1. "VAL," line.long 0x648 "GLBCE_WDR_GAMMA_LUT_225,Frontend WDR LUT" hexmask.long.word 0x648 0.--15. 1. "VAL," line.long 0x64C "GLBCE_WDR_GAMMA_LUT_226,Frontend WDR LUT" hexmask.long.word 0x64C 0.--15. 1. "VAL," line.long 0x650 "GLBCE_WDR_GAMMA_LUT_227,Frontend WDR LUT" hexmask.long.word 0x650 0.--15. 1. "VAL," line.long 0x654 "GLBCE_WDR_GAMMA_LUT_228,Frontend WDR LUT" hexmask.long.word 0x654 0.--15. 1. "VAL," line.long 0x658 "GLBCE_WDR_GAMMA_LUT_229,Frontend WDR LUT" hexmask.long.word 0x658 0.--15. 1. "VAL," line.long 0x65C "GLBCE_WDR_GAMMA_LUT_230,Frontend WDR LUT" hexmask.long.word 0x65C 0.--15. 1. "VAL," line.long 0x660 "GLBCE_WDR_GAMMA_LUT_231,Frontend WDR LUT" hexmask.long.word 0x660 0.--15. 1. "VAL," line.long 0x664 "GLBCE_WDR_GAMMA_LUT_232,Frontend WDR LUT" hexmask.long.word 0x664 0.--15. 1. "VAL," line.long 0x668 "GLBCE_WDR_GAMMA_LUT_233,Frontend WDR LUT" hexmask.long.word 0x668 0.--15. 1. "VAL," line.long 0x66C "GLBCE_WDR_GAMMA_LUT_234,Frontend WDR LUT" hexmask.long.word 0x66C 0.--15. 1. "VAL," line.long 0x670 "GLBCE_WDR_GAMMA_LUT_235,Frontend WDR LUT" hexmask.long.word 0x670 0.--15. 1. "VAL," line.long 0x674 "GLBCE_WDR_GAMMA_LUT_236,Frontend WDR LUT" hexmask.long.word 0x674 0.--15. 1. "VAL," line.long 0x678 "GLBCE_WDR_GAMMA_LUT_237,Frontend WDR LUT" hexmask.long.word 0x678 0.--15. 1. "VAL," line.long 0x67C "GLBCE_WDR_GAMMA_LUT_238,Frontend WDR LUT" hexmask.long.word 0x67C 0.--15. 1. "VAL," line.long 0x680 "GLBCE_WDR_GAMMA_LUT_239,Frontend WDR LUT" hexmask.long.word 0x680 0.--15. 1. "VAL," line.long 0x684 "GLBCE_WDR_GAMMA_LUT_240,Frontend WDR LUT" hexmask.long.word 0x684 0.--15. 1. "VAL," line.long 0x688 "GLBCE_WDR_GAMMA_LUT_241,Frontend WDR LUT" hexmask.long.word 0x688 0.--15. 1. "VAL," line.long 0x68C "GLBCE_WDR_GAMMA_LUT_242,Frontend WDR LUT" hexmask.long.word 0x68C 0.--15. 1. "VAL," line.long 0x690 "GLBCE_WDR_GAMMA_LUT_243,Frontend WDR LUT" hexmask.long.word 0x690 0.--15. 1. "VAL," line.long 0x694 "GLBCE_WDR_GAMMA_LUT_244,Frontend WDR LUT" hexmask.long.word 0x694 0.--15. 1. "VAL," line.long 0x698 "GLBCE_WDR_GAMMA_LUT_245,Frontend WDR LUT" hexmask.long.word 0x698 0.--15. 1. "VAL," line.long 0x69C "GLBCE_WDR_GAMMA_LUT_246,Frontend WDR LUT" hexmask.long.word 0x69C 0.--15. 1. "VAL," line.long 0x6A0 "GLBCE_WDR_GAMMA_LUT_247,Frontend WDR LUT" hexmask.long.word 0x6A0 0.--15. 1. "VAL," line.long 0x6A4 "GLBCE_WDR_GAMMA_LUT_248,Frontend WDR LUT" hexmask.long.word 0x6A4 0.--15. 1. "VAL," line.long 0x6A8 "GLBCE_WDR_GAMMA_LUT_249,Frontend WDR LUT" hexmask.long.word 0x6A8 0.--15. 1. "VAL," line.long 0x6AC "GLBCE_WDR_GAMMA_LUT_250,Frontend WDR LUT" hexmask.long.word 0x6AC 0.--15. 1. "VAL," line.long 0x6B0 "GLBCE_WDR_GAMMA_LUT_251,Frontend WDR LUT" hexmask.long.word 0x6B0 0.--15. 1. "VAL," line.long 0x6B4 "GLBCE_WDR_GAMMA_LUT_252,Frontend WDR LUT" hexmask.long.word 0x6B4 0.--15. 1. "VAL," line.long 0x6B8 "GLBCE_WDR_GAMMA_LUT_253,Frontend WDR LUT" hexmask.long.word 0x6B8 0.--15. 1. "VAL," line.long 0x6BC "GLBCE_WDR_GAMMA_LUT_254,Frontend WDR LUT" hexmask.long.word 0x6BC 0.--15. 1. "VAL," line.long 0x6C0 "GLBCE_WDR_GAMMA_LUT_255,Frontend WDR LUT" hexmask.long.word 0x6C0 0.--15. 1. "VAL," line.long 0x6C4 "GLBCE_WDR_GAMMA_LUT_256,Frontend WDR LUT" hexmask.long.word 0x6C4 0.--15. 1. "VAL," line.long 0x6C8 "GLBCE_TILE_OUT_POS,Tile processing signals [TBD]" hexmask.long.word 0x6C8 16.--31. 1. "TOP," newline hexmask.long.word 0x6C8 0.--15. 1. "LEFT," group.long 0x6E0++0x03 line.long 0x00 "GLBCE_TILE_OUT_SIZE,Tile processing signals [TBD]" hexmask.long.word 0x00 16.--31. 1. "HEIGHT," newline hexmask.long.word 0x00 0.--15. 1. "WIDTH," group.long 0x6E8++0x07 line.long 0x00 "GLBCE_TILE_CONTROL,TBD" bitfld.long 0x00 4. "LAST,Last time" "0,1" newline bitfld.long 0x00 3. "COLLECTION_DISABLE,Statistics collection disable" "0,1" newline bitfld.long 0x00 2. "UPDATE_DSABLE,Statistics update disable" "0,1" newline bitfld.long 0x00 0. "ENABLE,Tile processing Enable" "0,1" line.long 0x04 "GLBCE_OUTPUT_FLAGS,TBD" hexmask.long.word 0x04 0.--15. 1. "TILE_STATUS,Tile Status" width 0x0B tree.end tree "ISP6P5_H3A" base ad:0x52041400 rgroup.long 0x00++0x7F line.long 0x00 "H3A_PID,Peripheral Revision and Class Information" line.long 0x04 "H3A_PCR,Peripheral Control Register" hexmask.long.word 0x04 22.--31. 1. "AVE2LMT,AE/AWB Saturation Limit This is the value that all sub sampled pixels in the AE/AWB engine are compared to" bitfld.long 0x04 21. "OVF,H3A module overflow status bit" "OVF_0,OVF_1" bitfld.long 0x04 20. "AF_VF_EN,AF Vertical Focus Enable - NEWENUM1" "AF_VF_EN_0,AF_VF_EN_1" bitfld.long 0x04 19. "AEW_MED_EN,AE/AWB Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not filtered" "AEW_MED_EN_0,AEW_MED_EN_1" newline rbitfld.long 0x04 18. "BUSYAEAWB,Busy bit for AE/AWB" "BUSYAEAWB_0,BUSYAEAWB_1" bitfld.long 0x04 17. "AEW_ALAW_EN,AE/AWB A-law Enable - NEWENUM1" "AEW_ALAW_EN_0,AEW_ALAW_EN_1" bitfld.long 0x04 16. "AEW_EN,AE/AWB enable - NEWENUM1" "AEW_EN_0,AEW_EN_1" rbitfld.long 0x04 15. "BUSYAF,Busy bit for AF" "BUSYAF_0,BUSYAF_1" newline bitfld.long 0x04 14. "FVMODE,Focus Value Accumulation Mode - NEWENUM1" "FVMODE_0,FVMODE_1" bitfld.long 0x04 11.--13. "RGBPOS,Red Green and blue pixel location in the AF windows RGBPOS(0): GR and GB as Bayer pattern RGBPOS(1): RG and GB as Bayer pattern RGBPOS(2): GR and BG as Bayer pattern RGBPOS(3): RG and BG as Bayer pattern RGBPOS(4): GG and RB as custom pattern.." "RGBPOS_0,RGBPOS_1,RGBPOS_2,RGBPOS_3,RGBPOS_4,RGBPOS_5,RGBPOS_6,RGBPOS_7" hexmask.long.byte 0x04 3.--10. 1. "MED_TH,Median filter threshold" bitfld.long 0x04 2. "AF_MED_EN,Auto Focus Median filter Enable If the median filter is enabled then the 1st 2 and last 2 pixels in the frame are not in the valid region" "AF_MED_EN_0,AF_MED_EN_1" newline bitfld.long 0x04 1. "AF_ALAW_EN,AF A-law table enable - NEWENUM1" "AF_ALAW_EN_0,AF_ALAW_EN_1" bitfld.long 0x04 0. "AF_EN,AF enable - NEWENUM1" "AF_EN_0,AF_EN_1" line.long 0x08 "H3A_AFPAX1,Setup for the AF Engine Paxel Configuration" hexmask.long.byte 0x08 16.--23. 1. "PAXW,AF Engine Paxel Width The width of the paxel is the value of this register plus 1 multiplied by 2" hexmask.long.byte 0x08 0.--7. 1. "PAXH,AF Engine Paxel Height The height of the paxel is the value of this register plus 1 multiplied by 2 with a final value of 2-256 (even) * This value is shadowed and latched on the rising edge of VSYNC" line.long 0x0C "H3A_AFPAX2,Setup for the AF Engine Paxel Configuration" bitfld.long 0x0C 17.--20. "AFINCH,AF Engine Column Increments Number of columns to increment in a paxel plus 1 multiplied by 2" "AFINCH_0,AFINCH_1,AFINCH_2,AFINCH_3,AFINCH_4,AFINCH_5,AFINCH_6,AFINCH_7,AFINCH_8,AFINCH_9,AFINCH_10,AFINCH_11,AFINCH_12,AFINCH_13,AFINCH_14,AFINCH_15" bitfld.long 0x0C 13.--16. "AFINCV,AF Engine Line Increments Number of lines to increment in a Paxel plus 1 multiplied by 2" "AFINCV_0,AFINCV_1,AFINCV_2,AFINCV_3,AFINCV_4,AFINCV_5,AFINCV_6,AFINCV_7,AFINCV_8,AFINCV_9,AFINCV_10,AFINCV_11,AFINCV_12,AFINCV_13,AFINCV_14,AFINCV_15" hexmask.long.byte 0x0C 6.--12. 1. "PAXVC,AF Engine Vertical Paxel Count The number of paxels in the vertical direction plus 1" bitfld.long 0x0C 0.--5. "PAXHC,AF Engine Horizontal Paxel Count The number of paxels in the horizontal direction plus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "H3A_AFPAXSTART,Start Position for AF Engine Paxels" hexmask.long.word 0x10 16.--27. 1. "PAXSH,AF Engine Paxel Horizontal start position Range: 2-4094 PAXSH must be equal to or greater than (IIRSH + 2) This value must be even if Vertical mode is not enabled" hexmask.long.word 0x10 0.--11. 1. "PAXSV,AF Engine Paxel Vertical start position Range: 0-4095 Sets the vertical line for the first paxel" line.long 0x14 "H3A_AFIIRSH,Start Position for IIRSH" hexmask.long.word 0x14 0.--11. 1. "IIRSH,AF Engine IIR Horizontal Start Position Range from 0-4094" line.long 0x18 "H3A_AFBUFST,SDRAM destination address for AF engine statistics" hexmask.long 0x18 5.--31. 1. "AFBUFST,SDRAM destination address for AF engine statistics The SDRAM destination address for the AF statistics" line.long 0x1C "H3A_AFCOEF010,IIR filter coefficient data for SET 0" hexmask.long.word 0x1C 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 (Set 0) The range is signed" hexmask.long.word 0x1C 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 (Set 0) The range is signed" line.long 0x20 "H3A_AFCOEF032,IIR filter coefficient data for SET 0" hexmask.long.word 0x20 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 (Set 0) The range is signed" hexmask.long.word 0x20 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 (Set 0) The range is signed" line.long 0x24 "H3A_AFCOEF054,IIR filter coefficient data for SET 0" hexmask.long.word 0x24 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 (Set 0) The range is signed" hexmask.long.word 0x24 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 (Set 0) The range is signed" line.long 0x28 "H3A_AFCOEF076,IIR filter coefficient data for SET 0" hexmask.long.word 0x28 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 (Set 0) The range is signed" hexmask.long.word 0x28 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 (Set 0) The range is signed" line.long 0x2C "H3A_AFCOEF098,IIR filter coefficient data for SET 0" hexmask.long.word 0x2C 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 (Set 0) The range is signed" hexmask.long.word 0x2C 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 (Set 0) The range is signed" line.long 0x30 "H3A_AFCOEF0010,IIR filter coefficient data for SET 0" hexmask.long.word 0x30 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 (Set 0) The range is signed" line.long 0x34 "H3A_AFCOEF110,IIR filter coefficient data for SET 1" hexmask.long.word 0x34 16.--27. 1. "COEFF1,AF Engine IIR filter Coefficient #1 (Set 1) The range is signed" hexmask.long.word 0x34 0.--11. 1. "COEFF0,AF Engine IIR filter Coefficient #0 (Set 1) The range is signed" line.long 0x38 "H3A_AFCOEF132,IIR filter coefficient data for SET 1" hexmask.long.word 0x38 16.--27. 1. "COEFF3,AF Engine IIR filter Coefficient #3 (Set 1) The range is signed" hexmask.long.word 0x38 0.--11. 1. "COEFF2,AF Engine IIR filter Coefficient #2 (Set 1) The range is signed" line.long 0x3C "H3A_AFCOEF154,IIR filter coefficient data for SET 1" hexmask.long.word 0x3C 16.--27. 1. "COEFF5,AF Engine IIR filter Coefficient #5 (Set 1) The range is signed" hexmask.long.word 0x3C 0.--11. 1. "COEFF4,AF Engine IIR filter Coefficient #4 (Set 1) The range is signed" line.long 0x40 "H3A_AFCOEF176,IIR filter coefficient data for SET 1" hexmask.long.word 0x40 16.--27. 1. "COEFF7,AF Engine IIR filter Coefficient #7 (Set 1) The range is signed" hexmask.long.word 0x40 0.--11. 1. "COEFF6,AF Engine IIR filter Coefficient #6 (Set 1) The range is signed" line.long 0x44 "H3A_AFCOEF198,IIR filter coefficient data for SET 1" hexmask.long.word 0x44 16.--27. 1. "COEFF9,AF Engine IIR filter Coefficient #9 (Set 1) The range is signed" hexmask.long.word 0x44 0.--11. 1. "COEFF8,AF Engine IIR filter Coefficient #8 (Set 1) The range is signed" line.long 0x48 "H3A_AFCOEF1010,IIR filter coefficient data for SET 1" hexmask.long.word 0x48 0.--11. 1. "COEFF10,AF Engine IIR filter Coefficient #10 (Set 1) The range is signed" line.long 0x4C "H3A_AEWWIN1,Configuration for AE/AWB Windows" hexmask.long.byte 0x4C 24.--31. 1. "WINH,AE/AWB Engine Window Height This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2" hexmask.long.byte 0x4C 13.--20. 1. "WINW,AE/AWB Engine Window Width This specifies the window width in an even number of pixels the window width is the value plus 1 multiplied by 2" hexmask.long.byte 0x4C 6.--12. 1. "WINVC,AE/AWB Engine Vertical Window Count The number of windows in the vertical direction plus 1" bitfld.long 0x4C 0.--5. "WINHC,AE/AWB Engine Horizontal Window Count The number of horizontal windows plus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "H3A_AEWINSTART,Start position for AE/AWB Windows" hexmask.long.word 0x50 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position Sets the first line for the first window" hexmask.long.word 0x50 0.--11. 1. "WINSH,AE/AWB Engine Horizontal Window Start Position Sets the horizontal position for the first window on each line" line.long 0x54 "H3A_AEWINBLK,Start position and height for black line of AE/AWB Windows" hexmask.long.word 0x54 16.--27. 1. "WINSV,AE/AWB Engine Vertical Window Start Position for single black line of windows Sets the first line for the single black line of windows" hexmask.long.byte 0x54 0.--6. 1. "WINH,AE/AWB Engine Window Height for the single black line of windows This specifies the window height in an even number of pixels the window height is the value plus 1 multiplied by 2" line.long 0x58 "H3A_AEWSUBWIN,Configuration for subsample data in AE/AWB window" bitfld.long 0x58 8.--11. "AEWINCV,AE/AWB Engine Vertical Sampling Point Increment Sets vertical distance between sub-samples within a window plus 1 multiplied by 2" "AEWINCV_0,AEWINCV_1,AEWINCV_2,AEWINCV_3,AEWINCV_4,AEWINCV_5,AEWINCV_6,AEWINCV_7,AEWINCV_8,AEWINCV_9,AEWINCV_10,AEWINCV_11,AEWINCV_12,AEWINCV_13,AEWINCV_14,AEWINCV_15" bitfld.long 0x58 0.--3. "AEWINCH,AE/AWB Engine Horizontal Sampling Point Increment Sets horizontal distance between sub-samples within a window plus 1 multiplied by 2" "AEWINCH_0,AEWINCH_1,AEWINCH_2,AEWINCH_3,AEWINCH_4,AEWINCH_5,AEWINCH_6,AEWINCH_7,AEWINCH_8,AEWINCH_9,AEWINCH_10,AEWINCH_11,AEWINCH_12,AEWINCH_13,AEWINCH_14,AEWINCH_15" line.long 0x5C "H3A_AEWBUFST,SDRAM destination address for AE/AWB engine statistics" hexmask.long 0x5C 5.--31. 1. "AEWBUFST,SDRAM destination address for AE/AWB engine statistics The start location in SDRAM for the AE/AWB statistics" line.long 0x60 "H3A_AEWCFG,Configuration for AE/AWB" bitfld.long 0x60 8.--9. "AEFMT,AE/AWB output format" "sum of squares,min/max,sum only; no sum of squares..,?..." bitfld.long 0x60 0.--3. "SUMSHFT,AE/AWB engine shift value for the accumulation of pixel values This bitfield sets the right shift value which is applied on the result of the pixel accumulation before it is stored in the packet" "SUMSHFT_0,SUMSHFT_1,SUMSHFT_2,SUMSHFT_3,SUMSHFT_4,SUMSHFT_5,SUMSHFT_6,SUMSHFT_7,SUMSHFT_8,SUMSHFT_9,SUMSHFT_10,SUMSHFT_11,SUMSHFT_12,SUMSHFT_13,SUMSHFT_14,SUMSHFT_15" line.long 0x64 "H3A_LINE_START,Line Framing Logic Register In certain cases the number of clock cycles between HD pulses will be greater than the line buffer included in the H3A module" hexmask.long.word 0x64 16.--31. 1. "SLV,Start Line Vertical Specifies how many lines after the VD rising edge the real frame starts" hexmask.long.word 0x64 0.--15. 1. "LINE_START,Line Start The framing module uses the LINE_START bitfield to find the position of the first pixel to place into the line buffer" line.long 0x68 "H3A_VFV_CFG1,Vertical focus value configuration 1" hexmask.long.byte 0x68 24.--31. 1. "VCOEF1_3,Vertical FV FIR 1 coefficient 3" hexmask.long.byte 0x68 16.--23. 1. "VCOEF1_2,Vertical FV FIR 1 coefficient 2" hexmask.long.byte 0x68 8.--15. 1. "VCOEF1_1,Vertical FV FIR 1 coefficient 1" hexmask.long.byte 0x68 0.--7. 1. "VCOEF1_0,Vertical FV FIR 1 coefficient 0" line.long 0x6C "H3A_VFV_CFG2,Vertical focus value configuration 2" hexmask.long.word 0x6C 16.--31. 1. "VTHR1,Threshold for vertical FV FIR 1" hexmask.long.byte 0x6C 0.--7. 1. "VCOEF1_4,Vertical FV FIR 1 coefficient 4" line.long 0x70 "H3A_VFV_CFG3,Vertical focus value configuration 4" hexmask.long.byte 0x70 24.--31. 1. "VCOEF2_3,Vertical FV FIR 2 coefficient 3" hexmask.long.byte 0x70 16.--23. 1. "VCOEF2_2,Vertical FV FIR 2 coefficient 2" hexmask.long.byte 0x70 8.--15. 1. "VCOEF2_1,Vertical FV FIR 2 coefficient 1" hexmask.long.byte 0x70 0.--7. 1. "VCOEF2_0,Vertical FV FIR 2 coefficient 0" line.long 0x74 "H3A_VFV_CFG4,Vertical focus value configuration 4" hexmask.long.word 0x74 16.--31. 1. "VTHR2,Threshold for vertical FV FIR 2" hexmask.long.byte 0x74 0.--7. 1. "VCOEF2_4,Vertical FV FIR 2 coefficient 4" line.long 0x78 "H3A_HVF_THR,Horizontal Focus Value Threshold" hexmask.long.word 0x78 16.--31. 1. "HTHR2,Threshold for horizontal FV IIR 2" hexmask.long.word 0x78 0.--15. 1. "HTHR1,Threshold for horizontal FV IIR 1" line.long 0x7C "H3A_ADVANCED," hexmask.long.word 0x7C 16.--31. 1. "ID,To access the other bitfields (AF_MODE/AEW_MODE) certain value should be written to this ID field first" bitfld.long 0x7C 4. "AEW_MODE,This bit is accesible only if ID is set to 0xDC00 AE/AWB engine custom mode (AVE2 mode) select" "AEW_MODE_0,AEW_MODE_1" bitfld.long 0x7C 0. "AF_MODE,AF engine mode" "AF_MODE_0,AF_MODE_1" width 0x0B tree.end tree "ISP6P5_IPIPE" base ad:0x52040800 group.long 0x00++0x2F line.long 0x00 "IPIPE_SRC_EN,This register is not shadowed" bitfld.long 0x00 0. "EN,The start flag of the IPIPE module" "EN_0,EN_1" line.long 0x04 "IPIPE_SRC_MODE," bitfld.long 0x04 1. "WRT,The mode selection of the ipipeif_wrt which is an input port of the IPIPE module" "WRT_0,WRT_1" bitfld.long 0x04 0. "OST,The processing mode selection of the IPIPE module" "OST_0,OST_1" line.long 0x08 "IPIPE_SRC_FMT," bitfld.long 0x08 4. "FMT3,Chroma sumpling postion in YUV422 to 444 This field is only valide if FMT=3 and FT2=2 - COSITED" "FMT3_0,FMT3_1" bitfld.long 0x08 2.--3. "FMT2,YUV processing mode This field is valid only when FMT=3 (YUV input YUV output) - YUV_PROCESS" "FMT2_0,FMT2_1,FMT2_2,FMT2_3" bitfld.long 0x08 0.--1. "FMT,IPIPE module datapath selection - NEWENUM1" "FMT_0,FMT_1,FMT_2,FMT_3" line.long 0x0C "IPIPE_SRC_COL," bitfld.long 0x0C 6.--7. "OO,The color pattern of the odd line and odd pixel" "OO_0,OO_1,OO_2,OO_3" bitfld.long 0x0C 4.--5. "OE,The color pattern of the odd line and even pixel" "OE_0,OE_1,OE_2,OE_3" bitfld.long 0x0C 2.--3. "EO,The color pattern of the even line and odd pixel" "EO_0,EO_1,EO_2,EO_3" bitfld.long 0x0C 0.--1. "EE,The color pattern of the even line and even pixel" "EE_0,EE_1,EE_2,EE_3" line.long 0x10 "IPIPE_SRC_VPS," hexmask.long.word 0x10 0.--15. 1. "VAL,The vertical position of the global frame from the rising edge of the VD" line.long 0x14 "IPIPE_SRC_VSZ," hexmask.long.word 0x14 0.--12. 1. "VAL,The vertical size of the processing area" line.long 0x18 "IPIPE_SRC_HPS," hexmask.long.word 0x18 0.--15. 1. "VAL,The horizontal position of the global frame from the rising edge of the HD" line.long 0x1C "IPIPE_SRC_HSZ," hexmask.long.word 0x1C 1.--12. 1. "VAL,The horizontal size of the processing area" rbitfld.long 0x1C 0. "VAL_0,This is the LSB of the VAL[12:0]" "0,1" line.long 0x20 "IPIPE_SEL_SBU," bitfld.long 0x20 0. "EDOF,EDOF port selection - INT" "EDOF_0,EDOF_1" line.long 0x24 "IPIPE_SRC_STA,IPIPE STATUS REGISTER" bitfld.long 0x24 4. "VAL4,Status of Histogram Process (busy status)" "VAL4_0,VAL4_1" bitfld.long 0x24 3. "VAL3,Status of Histogram bank select" "VAL3_0,VAL3_1" bitfld.long 0x24 2. "VAL2,Status of BSC process (busy status)" "VAL2_0,VAL2_1" bitfld.long 0x24 1. "VAL1,Status of Boxcar process (busy status)" "VAL1_0,VAL1_1" newline bitfld.long 0x24 0. "VAL0,Status of Boxcar process (error status)" "VAL0_0,VAL0_1" line.long 0x28 "IPIPE_GCK_MMR," bitfld.long 0x28 0. "REG,The on/off selection of the clk_arm_g0 which is used for some ARM register access" "REG_0,REG_1" line.long 0x2C "IPIPE_GCK_PIX,This register is not shadowed" bitfld.long 0x2C 3. "G3,The on/off selection of the clk_pix_g3 which is use for the IPIPE processes of ?EE? and 'CAR'" "G3_0,G3_1" bitfld.long 0x2C 2. "G2,The on/off selection of the clk_pix_g2 which is use for the IPIPE processes of ?CFA? to '422' 'Histogram(YCbCr input)' and 'Boundary Signal Calculator'" "G2_0,G2_1" bitfld.long 0x2C 1. "G1,The on/off selection of the clk_pix_g1 which is used for the IPIPE processes of 'DefectCorrection' to 'WhiteBalance' and 'Histogram(RAW input)'" "G1_0,G1_1" bitfld.long 0x2C 0. "G0,The on/off selection of the clk_pix_g0 which is used for the IPIPE processing of 'Boxcar'" "G0_0,G0_1" group.long 0x34++0x5F line.long 0x00 "IPIPE_DPC_LUT_EN," bitfld.long 0x00 0. "EN,Enable of LUT defect pixel correction" "EN_0,EN_1" line.long 0x04 "IPIPE_DPC_LUT_SEL," bitfld.long 0x04 1. "TBL,LUT table type selection" "TBL_0,TBL_1" bitfld.long 0x04 0. "DOT,Replace dot selection on processing method 0" "DOT_0,DOT_1" line.long 0x08 "IPIPE_DPC_LUT_ADR," hexmask.long.word 0x08 0.--9. 1. "ADR,The address of the first valid data in look-up-table" line.long 0x0C "IPIPE_DPC_LUT_SIZ," hexmask.long.word 0x0C 0.--9. 1. "SIZ,The number of valid data in look-up-table" line.long 0x10 "IPIPE_DPC_OTF_EN,Enable of adaptive defect pixel correction module" bitfld.long 0x10 0. "EN,- NEWENUM1" "EN_0,EN_1" line.long 0x14 "IPIPE_DPC_OTF_TYP,To select MinMax Algorithm following values are set ALG: 0 TYP: 0 IPIPE_DPC_OTF_2_D_THR_x: 0 IPIPE_DPC_OTF_2_C_THR_x: maximum value" bitfld.long 0x14 1. "TYP,- NEWENUM1" "TYP_0,TYP_1" bitfld.long 0x14 0. "ALG,- NEWENUM1" "ALG_0,ALG_1" line.long 0x18 "IPIPE_DPC_OTF_2_D_THR_R,D_THR for R" hexmask.long.word 0x18 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x1C "IPIPE_DPC_OTF_2_D_THR_GR,D_THR for Gr" hexmask.long.word 0x1C 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x20 "IPIPE_DPC_OTF_2_D_THR_GB,D_THR for Gb" hexmask.long.word 0x20 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x24 "IPIPE_DPC_OTF_2_D_THR_B,D_THR for B" hexmask.long.word 0x24 0.--11. 1. "VAL,Defect detection threshold value for each color (DPC2.0)" line.long 0x28 "IPIPE_DPC_OTF_2_C_THR_R,C_THR for R" hexmask.long.word 0x28 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x2C "IPIPE_DPC_OTF_2_C_THR_GR,C_THR for Gr" hexmask.long.word 0x2C 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x30 "IPIPE_DPC_OTF_2_C_THR_GB,C_THR for Gb" hexmask.long.word 0x30 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x34 "IPIPE_DPC_OTF_2_C_THR_B,C_THR for B" hexmask.long.word 0x34 0.--11. 1. "VAL,Defect correction threshold value for each color (DPC2.0)" line.long 0x38 "IPIPE_DPC_OTF_3_SHF," bitfld.long 0x38 0.--1. "SHF," "SHF_0,SHF_1,SHF_2,SHF_3" line.long 0x3C "IPIPE_DPC_OTF_3_D_THR," bitfld.long 0x3C 6.--11. "VAL,DPC3 Defect detection threshold 12-bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x3C 0.--5. "VAL_RESERVED,DPC3 Defect detection threshold 12-bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x40 "IPIPE_DPC_OTF_3_D_SPL," bitfld.long 0x40 0.--5. "VAL,Defect detection threshold slope for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x44 "IPIPE_DPC_OTF_3_D_MIN," hexmask.long.word 0x44 0.--11. 1. "VAL," line.long 0x48 "IPIPE_DPC_OTF_3_D_MAX," hexmask.long.word 0x48 0.--11. 1. "VAL,Defect detection threshold MAX for DPC3.0" line.long 0x4C "IPIPE_DPC_OTF_3_C_THR," bitfld.long 0x4C 6.--11. "VAL,Defect correction threshold for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x4C 0.--5. "VAL_RESERVED,Defect correction threshold for DPC3.0 Bits VAL[5-0] cannot be written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "IPIPE_DPC_OTF_3_C_SLP," rbitfld.long 0x50 6.--11. "VAL_RESERVED,Defect correction threshold slope for DPC3.0 VAL[11-6] cannot be written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 0.--5. "VAL,Defect correction threshold slope for DPC3.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "IPIPE_DPC_OTF_3_C_MIN," hexmask.long.word 0x54 0.--11. 1. "VAL,Defect correction threshold MIN for DPC3.0" line.long 0x58 "IPIPE_DPC_OTF_3_C_MAX," hexmask.long.word 0x58 0.--11. 1. "VAL,Defect correction threshold MAX for DPC3.0" line.long 0x5C "IPIPE_LSC_VOFT,LSC VOFT" hexmask.long.word 0x5C 0.--12. 1. "LSC_VOFT," group.long 0x9C++0x07 line.long 0x00 "IPIPE_LSC_VS," bitfld.long 0x00 4.--7. "VS2,LSC VS1" "VS2_0,VS2_1,VS2_2,VS2_3,VS2_4,VS2_5,VS2_6,VS2_7,VS2_8,VS2_9,VS2_10,VS2_11,VS2_12,VS2_13,VS2_14,VS2_15" bitfld.long 0x00 0.--3. "VS1,LSC VS1" "VS1_0,VS1_1,VS1_2,VS1_3,VS1_4,VS1_5,VS1_6,VS1_7,VS1_8,VS1_9,VS1_10,VS1_11,VS1_12,VS1_13,VS1_14,VS1_15" line.long 0x04 "IPIPE_LSC_HOFT," hexmask.long.word 0x04 0.--12. 1. "VAL,LSC HOFT" group.long 0xAC++0xA3 line.long 0x00 "IPIPE_LSC_HS," bitfld.long 0x00 4.--7. "HS2,LSC HS1" "HS2_0,HS2_1,HS2_2,HS2_3,HS2_4,HS2_5,HS2_6,HS2_7,HS2_8,HS2_9,HS2_10,HS2_11,HS2_12,HS2_13,HS2_14,HS2_15" bitfld.long 0x00 0.--3. "HS1,LSC HS1" "HS1_0,HS1_1,HS1_2,HS1_3,HS1_4,HS1_5,HS1_6,HS1_7,HS1_8,HS1_9,HS1_10,HS1_11,HS1_12,HS1_13,HS1_14,HS1_15" line.long 0x04 "IPIPE_LSC_GAN_R," hexmask.long.byte 0x04 0.--7. 1. "VAL,GAN R" line.long 0x08 "IPIPE_LSC_GAN_GR," hexmask.long.byte 0x08 0.--7. 1. "VAL,GAN GR" line.long 0x0C "IPIPE_LSC_GAN_GB," hexmask.long.byte 0x0C 0.--7. 1. "VAL,GAN GB" line.long 0x10 "IPIPE_LSC_GAN_B," hexmask.long.byte 0x10 0.--7. 1. "VAL,GAN B" line.long 0x14 "IPIPE_LSC_OFT_R," hexmask.long.byte 0x14 0.--7. 1. "VAL,LSC OFT R" line.long 0x18 "IPIPE_LSC_OFT_GR," hexmask.long.byte 0x18 0.--7. 1. "VAL,LSC OFT GR" line.long 0x1C "IPIPE_LSC_OFT_GB," hexmask.long.byte 0x1C 0.--7. 1. "VAL,LSC OFT GB" line.long 0x20 "IPIPE_LSC_OFT_B," hexmask.long.byte 0x20 0.--7. 1. "VAL,LSC OFT B" line.long 0x24 "IPIPE_LSC_SHF," bitfld.long 0x24 0.--3. "VAL,LSC SHV" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15" line.long 0x28 "IPIPE_LSC_MAX," hexmask.long.word 0x28 0.--8. 1. "VAL,LSC MAX" line.long 0x2C "IPIPE_D2F_1ST_EN,Noise Filter 1 Register" bitfld.long 0x2C 0. "EN,Enable of noise filter-1 module" "EN_0,EN_1" line.long 0x30 "IPIPE_D2F_1ST_TYP,Noise Filter 1 Register" bitfld.long 0x30 9. "SEL,Select SPR value source - NEWENUM1" "SEL_0,SEL_1" bitfld.long 0x30 8. "LSC,Apply LSC gain to threshold values - NEWENUM1" "LSC_0,LSC_1" bitfld.long 0x30 7. "TYP,The sampling method of green pixels" "TYP_0,TYP_1" bitfld.long 0x30 5.--6. "SHF,The d value (down shift value) in look-up-table reference address" "SHF_0,SHF_1,SHF_2,SHF_3" newline bitfld.long 0x30 0.--4. "SPR,The SP value ('spread' value) in noise filter-1 algorithm" "SPR_0,SPR_1,SPR_2,SPR_3,SPR_4,SPR_5,SPR_6,SPR_7,SPR_8,SPR_9,SPR_10,SPR_11,SPR_12,SPR_13,SPR_14,SPR_15,SPR_16,SPR_17,SPR_18,SPR_19,SPR_20,SPR_21,SPR_22,SPR_23,SPR_24,SPR_25,SPR_26,SPR_27,SPR_28,SPR_29,SPR_30,SPR_31" line.long 0x34 "IPIPE_D2F_1ST_THR_00,Noise Filter 1 Register" hexmask.long.word 0x34 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x38 "IPIPE_D2F_1ST_THR_01,Noise Filter 1 Register" hexmask.long.word 0x38 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x3C "IPIPE_D2F_1ST_THR_02,Noise Filter 1 Register" hexmask.long.word 0x3C 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x40 "IPIPE_D2F_1ST_THR_03,Noise Filter 1 Register" hexmask.long.word 0x40 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x44 "IPIPE_D2F_1ST_THR_04,Noise Filter 1 Register" hexmask.long.word 0x44 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x48 "IPIPE_D2F_1ST_THR_05,Noise Filter 1 Register" hexmask.long.word 0x48 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x4C "IPIPE_D2F_1ST_THR_06,Noise Filter 1 Register" hexmask.long.word 0x4C 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x50 "IPIPE_D2F_1ST_THR_07,Noise Filter 1 Register" hexmask.long.word 0x50 0.--9. 1. "VAL,Threshold values in noise filter-1 algorithm" line.long 0x54 "IPIPE_D2F_1ST_STR_00,Noise Filter 1 Register" bitfld.long 0x54 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x58 "IPIPE_D2F_1ST_STR_01,Noise Filter 1 Register" bitfld.long 0x58 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x5C "IPIPE_D2F_1ST_STR_02,Noise Filter 1 Register" bitfld.long 0x5C 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x60 "IPIPE_D2F_1ST_STR_03,Noise Filter 1 Register" bitfld.long 0x60 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x64 "IPIPE_D2F_1ST_STR_04,Noise Filter 1 Register" bitfld.long 0x64 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x68 "IPIPE_D2F_1ST_STR_05,Noise Filter 1 Register" bitfld.long 0x68 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x6C "IPIPE_D2F_1ST_STR_06,Noise Filter 1 Register" bitfld.long 0x6C 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x70 "IPIPE_D2F_1ST_STR_07,Noise Filter 1 Register" bitfld.long 0x70 0.--4. "VAL,Noise filter-1 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x74 "IPIPE_D2F_1ST_SPR_00,Noise Filter 1 Register" bitfld.long 0x74 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x78 "IPIPE_D2F_1ST_SPR_01,Noise Filter 1 Register" bitfld.long 0x78 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x7C "IPIPE_D2F_1ST_SPR_02,Noise Filter 1 Register" bitfld.long 0x7C 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x80 "IPIPE_D2F_1ST_SPR_03,Noise Filter 1 Register" bitfld.long 0x80 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x84 "IPIPE_D2F_1ST_SPR_04,Noise Filter 1 Register" bitfld.long 0x84 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x88 "IPIPE_D2F_1ST_SPR_05,Noise Filter 1 Register" bitfld.long 0x88 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x8C "IPIPE_D2F_1ST_SPR_06,Noise Filter 1 Register" bitfld.long 0x8C 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x90 "IPIPE_D2F_1ST_SPR_07,Noise Filter 1 Register" bitfld.long 0x90 0.--4. "VAL,Noise filter-1 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x94 "IPIPE_D2F_1ST_EDG_MIN,Noise Filter 1 Register" hexmask.long.word 0x94 0.--10. 1. "VAL,Noise filter-1 edge detection MIN" line.long 0x98 "IPIPE_D2F_1ST_EDG_MAX,Noise Filter 1 Register" hexmask.long.word 0x98 0.--10. 1. "VAL,Noise filter-1 edge detection MAX" line.long 0x9C "IPIPE_D2F_2ND_EN,Noise Filter 2 Register" bitfld.long 0x9C 0. "EN,Enable of noise filter-2 module" "EN_0,EN_1" line.long 0xA0 "IPIPE_D2F_2ND_TYP,Noise Filter 2 Register" bitfld.long 0xA0 9. "SEL,Select SPR value source - NEWENUM1" "SEL_0,SEL_1" bitfld.long 0xA0 8. "LSC,Apply LSC gain to threshold values - NEWENUM1" "LSC_0,LSC_1" bitfld.long 0xA0 7. "TYP,The sampling method of green pixels" "TYP_0,TYP_1" bitfld.long 0xA0 5.--6. "SHF,The d value (down shift value) in look-up-table reference address" "SHF_0,SHF_1,SHF_2,SHF_3" newline bitfld.long 0xA0 0.--4. "SPR,The SP value ('spread' value) in noise filter-2 algorithm" "SPR_0,SPR_1,SPR_2,SPR_3,SPR_4,SPR_5,SPR_6,SPR_7,SPR_8,SPR_9,SPR_10,SPR_11,SPR_12,SPR_13,SPR_14,SPR_15,SPR_16,SPR_17,SPR_18,SPR_19,SPR_20,SPR_21,SPR_22,SPR_23,SPR_24,SPR_25,SPR_26,SPR_27,SPR_28,SPR_29,SPR_30,SPR_31" group.long 0x170++0x227 line.long 0x00 "IPIPE_D2F_2ND_STR_00,Noise Filter 2 Register" bitfld.long 0x00 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x04 "IPIPE_D2F_2ND_STR_01,Noise Filter 2 Register" bitfld.long 0x04 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x08 "IPIPE_D2F_2ND_STR_02,Noise Filter 2 Register" bitfld.long 0x08 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x0C "IPIPE_D2F_2ND_STR_03,Noise Filter 2 Register" bitfld.long 0x0C 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x10 "IPIPE_D2F_2ND_STR_04,Noise Filter 2 Register" bitfld.long 0x10 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x14 "IPIPE_D2F_2ND_STR_05,Noise Filter 2 Register" bitfld.long 0x14 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x18 "IPIPE_D2F_2ND_STR_06,Noise Filter 2 Register" bitfld.long 0x18 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x1C "IPIPE_D2F_2ND_STR_07,Noise Filter 2 Register" bitfld.long 0x1C 0.--4. "VAL,Noise filter-2 intensity values (STR)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x20 "IPIPE_D2F_2ND_SPR_00,Noise Filter 2 Register" bitfld.long 0x20 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x24 "IPIPE_D2F_2ND_SPR_01,Noise Filter 2 Register" bitfld.long 0x24 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x28 "IPIPE_D2F_2ND_SPR_02,Noise Filter 2 Register" bitfld.long 0x28 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x2C "IPIPE_D2F_2ND_SPR_03,Noise Filter 2 Register" bitfld.long 0x2C 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x30 "IPIPE_D2F_2ND_SPR_04,Noise Filter 2 Register" bitfld.long 0x30 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x34 "IPIPE_D2F_2ND_SPR_05,Noise Filter 2 Register" bitfld.long 0x34 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x38 "IPIPE_D2F_2ND_SPR_06,Noise Filter 2 Register" bitfld.long 0x38 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x3C "IPIPE_D2F_2ND_SPR_07,Noise Filter 2 Register" bitfld.long 0x3C 0.--4. "VAL,Noise filter-2 intensity values (SP)" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x40 "IPIPE_D2F_2ND_EDG_MIN,Noise Filter 2 Register" hexmask.long.word 0x40 0.--10. 1. "VAL,Noise filter-2 edge detection MIN" line.long 0x44 "IPIPE_D2F_2ND_EDG_MAX,Noise Filter 2 Register" hexmask.long.word 0x44 0.--10. 1. "VAL,Noise filter-2 edge detection MAX" line.long 0x48 "IPIPE_GIC_EN,Green Imbalance Correction Register" bitfld.long 0x48 0. "EN,Enable signal of PreFilter module - NEWENUM1" "EN_0,EN_1" line.long 0x4C "IPIPE_GIC_TYP,Green Imbalance Correction Register" bitfld.long 0x4C 2. "LSC,Applies LSC gain to threshold value - NEWENUM1" "LSC_0,LSC_1" bitfld.long 0x4C 1. "SEL,Threshold Selection This bit selects the threshold either from the register value (GIC_THR) or threshold table of NF-2 - NEWENUM1" "SEL_0,SEL_1" bitfld.long 0x4C 0. "TYP,Algorithm select - NEWENUM1" "TYP_0,TYP_1" line.long 0x50 "IPIPE_GIC_GAN,Green Imbalance Correction Register" hexmask.long.byte 0x50 0.--7. 1. "VAL,VAL specifies the PreFilter gain" line.long 0x54 "IPIPE_GIC_NFGAIN," hexmask.long.byte 0x54 0.--7. 1. "VAL," line.long 0x58 "IPIPE_GIC_THR,Green Imbalance Correction Register" hexmask.long.word 0x58 0.--11. 1. "VAL,Threshold-1 in the adaptive GIC algorithm" line.long 0x5C "IPIPE_GIC_SLP,Green Imbalance Correction Register" hexmask.long.word 0x5C 0.--11. 1. "VAL,Slope (THR2-THR1) of GIC algorithm" line.long 0x60 "IPIPE_WB2_OFT_R,White Balance Register" hexmask.long.word 0x60 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x64 "IPIPE_WB2_OFT_GR,White Balance Register" hexmask.long.word 0x64 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x68 "IPIPE_WB2_OFT_GB,White Balance Register" hexmask.long.word 0x68 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x6C "IPIPE_WB2_OFT_B,White Balance Register" hexmask.long.word 0x6C 0.--11. 1. "VAL,Offset before white balance (S12) -2048 to +2047" line.long 0x70 "IPIPE_WB2_WGN_R,White Balance Register" hexmask.long.word 0x70 0.--12. 1. "VAL,White balance gain for R in U4.9 format 0 to +15.998" line.long 0x74 "IPIPE_WB2_WGN_GR,White Balance Register" hexmask.long.word 0x74 0.--12. 1. "VAL,White balance gain for Gr in U4.9 format 0 to +15.998" line.long 0x78 "IPIPE_WB2_WGN_GB,White Balance Register" hexmask.long.word 0x78 0.--12. 1. "VAL,White balance gain for Gb in U4.9 format 0 to +15.998" line.long 0x7C "IPIPE_WB2_WGN_B,White Balance Register" hexmask.long.word 0x7C 0.--12. 1. "VAL,White balance gain for B in U4.9 format 0 to +15.998" line.long 0x80 "IPIPE_CFA_MODE,CFA Register" bitfld.long 0x80 0.--1. "MODE,Algorithm selection - NEWENUM1" "MODE_0,MODE_1,MODE_2,MODE_3" line.long 0x84 "IPIPE_CFA_2DIR_HPF_THR,CFA: HP Value Low Threshold" hexmask.long.word 0x84 0.--12. 1. "VAL,HPF_THR 2DirCFA HP Value Low Threshold" line.long 0x88 "IPIPE_CFA_2DIR_HPF_SLP,CFA: HP Value Slope" hexmask.long.word 0x88 0.--9. 1. "VAL,HPF_SLP 2DirCFA HP Value Slope" line.long 0x8C "IPIPE_CFA_2DIR_MIX_THR,CFA: HP Mix Threshold" hexmask.long.word 0x8C 0.--12. 1. "VAL,MIX_THR 2DirCFA HP Mix Threshold" line.long 0x90 "IPIPE_CFA_2DIR_MIX_SLP,CFA Register" hexmask.long.word 0x90 0.--9. 1. "VAL,MIX_SLP 2DirCFA HP Mix Slope" line.long 0x94 "IPIPE_CFA_2DIR_DIR_TRH,CFA: Direction Threshold" hexmask.long.word 0x94 0.--9. 1. "VAL,DIR_THR 2DirCFA Direction Threshold" line.long 0x98 "IPIPE_CFA_2DIR_DIR_SLP,CFA: Direction Slope" hexmask.long.byte 0x98 0.--6. 1. "VAL,DIR_SLP 2DirCFA Direction Slope" line.long 0x9C "IPIPE_CFA_2DIR_NDWT," bitfld.long 0x9C 0.--5. "VAL,ND Weight 2DirCFA NonDirectional Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xA0 "IPIPE_CFA_MONO_HUE_FRA,Mono CFA Register" bitfld.long 0xA0 0.--5. "VAL,HUE_FRA DAA Hue Fraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xA4 "IPIPE_CFA_MONO_EDG_THR,monoCFA THR SLP" hexmask.long.byte 0xA4 0.--7. 1. "VAL,EDGE_THR DAA Edge Threshold" line.long 0xA8 "IPIPE_CFA_MONO_THR_MIN,Mono CFA Register" hexmask.long.word 0xA8 0.--9. 1. "VAL,THR_MIN DAA Threshold Minimum" line.long 0xAC "IPIPE_CFA_MONO_THR_SLP,CFA: Threshold Slope" hexmask.long.word 0xAC 0.--9. 1. "VAL,THR_SLP DAA Threshold Slope" line.long 0xB0 "IPIPE_CFA_MONO_SLP_MIN,CFA: Threshold Minimum" hexmask.long.word 0xB0 0.--9. 1. "VAL,SLP_MIN DAA Slope Minimum" line.long 0xB4 "IPIPE_CFA_MONO_SLP_SLP,CFA: Threshold Slope" hexmask.long.word 0xB4 0.--9. 1. "VAL,SLP_SLP DAA Slope Slope" line.long 0xB8 "IPIPE_CFA_MONO_LPWT,CFA: LP Weight" bitfld.long 0xB8 0.--5. "VAL,LPWT DAA LP Weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xBC "IPIPE_RGB1_MUL_RR,RGB to RGB Conversion Register" abitfld.long 0xBC 0.--11. "VAL,The matrix coefficient" "0xFFFFFFFFFFFFFFFF=-2048/256 = -8,0x000=0/256 = 0,0x001=1/256,0x0FF=255/256,0x100=256/256 = 1,0x101=257/256 [...],0x7FE=2046/256 [...],0x7FF=2047/256 = 7.99609375" line.long 0xC0 "IPIPE_RGB1_MUL_GR,RGB to RGB Conversion Register" hexmask.long.word 0xC0 0.--11. 1. "VAL,The matrix coefficient" line.long 0xC4 "IPIPE_RGB1_MUL_BR,RGB to RGB Conversion Register" hexmask.long.word 0xC4 0.--11. 1. "VAL,The matrix coefficient" line.long 0xC8 "IPIPE_RGB1_MUL_RG,RGB to RGB Conversion Register" hexmask.long.word 0xC8 0.--11. 1. "VAL,The matrix coefficient" line.long 0xCC "IPIPE_RGB1_MUL_GG,RGB to RGB Conversion Register" hexmask.long.word 0xCC 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD0 "IPIPE_RGB1_MUL_BG,RGB to RGB Conversion Register" hexmask.long.word 0xD0 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD4 "IPIPE_RGB1_MUL_RB,RGB to RGB Conversion Register" hexmask.long.word 0xD4 0.--11. 1. "VAL,The matrix coefficient" line.long 0xD8 "IPIPE_RGB1_MUL_GB,RGB to RGB Conversion Register" hexmask.long.word 0xD8 0.--11. 1. "VAL,The matrix coefficient" line.long 0xDC "IPIPE_RGB1_MUL_BB,RGB to RGB Conversion Register" hexmask.long.word 0xDC 0.--11. 1. "VAL,The matrix coefficient" line.long 0xE0 "IPIPE_RGB1_OFT_OR,RGB to RGB Conversion Register" hexmask.long.word 0xE0 0.--12. 1. "VAL,The output offset value for R" line.long 0xE4 "IPIPE_RGB1_OFT_OG,RGB to RGB Conversion Register" hexmask.long.word 0xE4 0.--12. 1. "VAL,The output offset value for G" line.long 0xE8 "IPIPE_RGB1_OFT_OB,RGB to RGB Conversion Register" hexmask.long.word 0xE8 0.--12. 1. "VAL,The output offset value for B" line.long 0xEC "IPIPE_GMM_CFG,RGB to RGB Conversion Register" bitfld.long 0xEC 5.--6. "SIZ,The size of the gamma table" "SIZ_0,SIZ_1,SIZ_2,SIZ_3" bitfld.long 0xEC 4. "TBL,Selection of Gamma table" "TBL_0,TBL_1" bitfld.long 0xEC 2. "BYPB,Gamma correction mode for B - NEWENUM1" "BYPB_0,BYPB_1" bitfld.long 0xEC 1. "BYPG,Gamma correction mode for G - NEWENUM1" "BYPG_0,BYPG_1" newline bitfld.long 0xEC 0. "BYPR,Gamma correction mode for R - NEWENUM1" "BYPR_0,BYPR_1" line.long 0xF0 "IPIPE_RGB2_MUL_RR,RGB to RGB conversion after gamma" abitfld.long 0xF0 0.--10. "VAL,The matrix coefficient" "0xFFFFFFFFFFFFFFFF=-2048/256 = -8,0x000=0/256 = 0,0x001=1/256,0x0FF=255/256,0x100=256/256 = 1,0x101=257/256,0x7FE=2046/256,0x7FF=2047/256 = 7.99609375" line.long 0xF4 "IPIPE_RGB2_MUL_GR,RGB to RGB conversion after gamma" hexmask.long.word 0xF4 0.--10. 1. "VAL,The matrix coefficient" line.long 0xF8 "IPIPE_RGB2_MUL_BR,RGB to RGB conversion after gamma" hexmask.long.word 0xF8 0.--10. 1. "VAL,The matrix coefficient" line.long 0xFC "IPIPE_RGB2_MUL_RG,RGB to RGB conversion after gamma" hexmask.long.word 0xFC 0.--10. 1. "VAL,The matrix coefficient" line.long 0x100 "IPIPE_RGB2_MUL_GG,RGB to RGB conversion after gamma" hexmask.long.word 0x100 0.--10. 1. "VAL,The matrix coefficient" line.long 0x104 "IPIPE_RGB2_MUL_BG,RGB to RGB conversion after gamma" hexmask.long.word 0x104 0.--10. 1. "VAL,The matrix coefficient" line.long 0x108 "IPIPE_RGB2_MUL_RB,RGB to RGB conversion after gamma" hexmask.long.word 0x108 0.--10. 1. "VAL,The matrix coefficient" line.long 0x10C "IPIPE_RGB2_MUL_GB,RGB to RGB conversion after gamma" hexmask.long.word 0x10C 0.--10. 1. "VAL,The matrix coefficient" line.long 0x110 "IPIPE_RGB2_MUL_BB,RGB to RGB conversion after gamma" hexmask.long.word 0x110 0.--10. 1. "VAL,The matrix coefficient" line.long 0x114 "IPIPE_RGB2_OFT_OR,RGB to RGB conversion after gamma" hexmask.long.word 0x114 0.--10. 1. "VAL,The output offset value for R S10 number: -1024 to + 1023" line.long 0x118 "IPIPE_RGB2_OFT_OG,RGB to RGB conversion after gamma" hexmask.long.word 0x118 0.--10. 1. "VAL,The output offset value for G S10 number: -1024 to + 1023" line.long 0x11C "IPIPE_RGB2_OFT_OB,RGB to RGB conversion after gamma" hexmask.long.word 0x11C 0.--10. 1. "VAL,The output offset value for B S10 number: -1024 to + 1023" line.long 0x120 "IPIPE_3DLUT_EN,3D-LUT" bitfld.long 0x120 0. "EN,Enables or disable the 3D-LUT function" "EN_0,EN_1" line.long 0x124 "IPIPE_YUV_ADJ,RGB to YUV Conversion Register" hexmask.long.byte 0x124 8.--15. 1. "BRT,The offset value for brightness control" abitfld.long 0x124 0.--7. "CRT,The multiplier coefficient value for contrast control" "0x00=0/16 = 0,0x01=1/16,0x0F=15/16,0x10=16/16 = 1,0x11=17/16,0xFE=254/16,0xFF=255/16 = 15.9375" line.long 0x128 "IPIPE_YUV_MUL_RY,RGB to YUV Conversion Register" hexmask.long.word 0x128 0.--11. 1. "VAL,Matrix Coefficient for RY (S4.8 = -8 - +7.996)" line.long 0x12C "IPIPE_YUV_MUL_GY,RGB to YUV Conversion Register" hexmask.long.word 0x12C 0.--11. 1. "VAL,Matrix Coefficient for GY (S4.8 = -8 - +7.996)" line.long 0x130 "IPIPE_YUV_MUL_BY,RGB to YUV Conversion Register" hexmask.long.word 0x130 0.--11. 1. "VAL,Matrix Coefficient for BY (S4.8 = -8 - +7.996)" line.long 0x134 "IPIPE_YUV_MUL_RCB,RGB to YUV Conversion Register" hexmask.long.word 0x134 0.--11. 1. "VAL,The matrix coefficient" line.long 0x138 "IPIPE_YUV_MUL_GCB,RGB to YUV Conversion Register" hexmask.long.word 0x138 0.--11. 1. "VAL,The matrix coefficient" line.long 0x13C "IPIPE_YUV_MUL_BCB,RGB to YUV Conversion Register" hexmask.long.word 0x13C 0.--11. 1. "VAL,The matrix coefficient" line.long 0x140 "IPIPE_YUV_MUL_RCR,RGB to YUV Conversion Register" hexmask.long.word 0x140 0.--11. 1. "VAL,The matrix coefficient" line.long 0x144 "IPIPE_YUV_MUL_GCR,RGB to YUV Conversion Register" hexmask.long.word 0x144 0.--11. 1. "VAL,The matrix coefficient" line.long 0x148 "IPIPE_YUV_MUL_BCR,RGB to YUV Conversion Register" hexmask.long.word 0x148 0.--11. 1. "VAL,The matrix coefficient" line.long 0x14C "IPIPE_YUV_OFT_Y,RGB to YUV Conversion Register" hexmask.long.word 0x14C 0.--10. 1. "VAL,The output offset value for Y" line.long 0x150 "IPIPE_YUV_OFT_CB,RGB to YUV Conversion Register" hexmask.long.word 0x150 0.--10. 1. "VAL,The output offset value for Cb For Cb/Cr set (0x80 + offset value) here" line.long 0x154 "IPIPE_YUV_OFT_CR,RGB to YUV Conversion Register" hexmask.long.word 0x154 0.--10. 1. "VAL,The output offset value for Cr For Cb/Cr set (0x80 + offset value) here" line.long 0x158 "IPIPE_YUV_PHS,YUV422 down sampling register" bitfld.long 0x158 1. "LPF,121-LPF enable for chrominance samples" "LPF_0,LPF_1" bitfld.long 0x158 0. "POS,This bit sets the output position of the chrominance sample with regards to the luma sample positions" "POS_0,POS_1" line.long 0x15C "IPIPE_GBCE_EN,Global brightness contrast enhancement" bitfld.long 0x15C 0. "EN,Enable of GBCE module" "EN_0,EN_1" line.long 0x160 "IPIPE_GBCE_TYP,Global brightness contrast enhancement" bitfld.long 0x160 0. "TYP,GBCE method selection - NEWENUM1" "TYP_0,TYP_1" line.long 0x164 "IPIPE_YEE_EN,Edge Enhancer Register" bitfld.long 0x164 0. "EN,The on/off selection of the ?Edge enhancer?" "EN_0,EN_1" line.long 0x168 "IPIPE_YEE_TYP,Edge Enhancer Register" bitfld.long 0x168 1. "HAL,Halo reduction in Edge Sharpener module" "HAL_0,HAL_1" bitfld.long 0x168 0. "SEL,Merging method between Edge Enhancer and Edge Sharpener - NEWENUM2" "SEL_0,SEL_1" line.long 0x16C "IPIPE_YEE_SHF,Edge Enhancer Register" bitfld.long 0x16C 0.--3. "SHF,Down shift length of high pass filter (HPF) in edge enhancer" "SHF_0,SHF_1,SHF_2,SHF_3,SHF_4,SHF_5,SHF_6,SHF_7,SHF_8,SHF_9,SHF_10,SHF_11,SHF_12,SHF_13,SHF_14,SHF_15" line.long 0x170 "IPIPE_YEE_MUL_00,Edge Enhancer Register" abitfld.long 0x170 0.--9. "VAL,Multiplier coefficient in HPF" "0x000=0,0x001=1,0x1FE=510,0x1FF=511,0x200=-512,0x201=-511,0x3FF=-1" line.long 0x174 "IPIPE_YEE_MUL_01,Edge Enhancer Register" hexmask.long.word 0x174 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x178 "IPIPE_YEE_MUL_02,Edge Enhancer Register" hexmask.long.word 0x178 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x17C "IPIPE_YEE_MUL_10,Edge Enhancer Register" hexmask.long.word 0x17C 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x180 "IPIPE_YEE_MUL_11,Edge Enhancer Register" hexmask.long.word 0x180 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x184 "IPIPE_YEE_MUL_12,Edge Enhancer Register" hexmask.long.word 0x184 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x188 "IPIPE_YEE_MUL_20,Edge Enhancer Register" hexmask.long.word 0x188 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x18C "IPIPE_YEE_MUL_21,Edge Enhancer Register" hexmask.long.word 0x18C 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x190 "IPIPE_YEE_MUL_22,Edge Enhancer Register" hexmask.long.word 0x190 0.--9. 1. "VAL,Multiplier coefficient in HPF" line.long 0x194 "IPIPE_YEE_THR,Edge Enhancer Register" bitfld.long 0x194 0.--5. "VAL,Edge Enhancer lower threshold before referring to LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x198 "IPIPE_YEE_E_GAN,Edge Enhancer Register" hexmask.long.word 0x198 0.--11. 1. "VAL,Edge sharpener gain" line.long 0x19C "IPIPE_YEE_E_THR_1,Edge Enhancer Register" hexmask.long.word 0x19C 0.--11. 1. "VAL,Edge sharpener HPF value lower limit" line.long 0x1A0 "IPIPE_YEE_E_THR_2,Edge Enhancer Register" bitfld.long 0x1A0 0.--5. "VAL,Edge sharpener HPF value upper limit (after 6 bit right shift)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1A4 "IPIPE_YEE_G_GAN,Edge Enhancer Register" hexmask.long.byte 0x1A4 0.--7. 1. "VAL,Edge sharpener gain value on gradient" line.long 0x1A8 "IPIPE_YEE_G_OFT,Edge Enhancer Register" bitfld.long 0x1A8 0.--5. "VAL,Edge sharpener offset value on gradient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1AC "IPIPE_CAR_EN,Chroma Artifact Reduction Register" bitfld.long 0x1AC 0. "EN,The on/off selection of the ?fault color suppression?" "EN_0,EN_1" line.long 0x1B0 "IPIPE_CAR_TYP,Chroma Artifact Reduction Register" bitfld.long 0x1B0 1. "CHR,To specify the order of chroma in dynamic switching" "Normal Cb/Cr order (default),Flipped order (Cr/Cb) - NEWENUM1" bitfld.long 0x1B0 0. "TYP,The mode selection of the 'fault color suppression'" "TYP_0,TYP_1" line.long 0x1B4 "IPIPE_CAR_SW,Chroma Artifact Reduction Register" hexmask.long.byte 0x1B4 8.--15. 1. "SW1,Threshold-2 for switching function (Select gain control)" hexmask.long.byte 0x1B4 0.--7. 1. "SW0,Threshold-1 for switching function (Select median filter)" line.long 0x1B8 "IPIPE_CAR_HPF_TYP,Chroma Artifact Reduction Register" bitfld.long 0x1B8 0.--2. "TYP,- NEWENUM7" "TYP_0,TYP_1,TYP_2,TYP_3,TYP_4,TYP_5,TYP_6,TYP_7" line.long 0x1BC "IPIPE_CAR_HPF_SHF,Chroma Artifact Reduction Register" bitfld.long 0x1BC 0.--1. "VAL,Down shift value for HPF" "VAL_0,VAL_1,VAL_2,VAL_3" line.long 0x1C0 "IPIPE_CAR_HPF_THR,Chroma Artifact Reduction Register" hexmask.long.byte 0x1C0 0.--7. 1. "VAL,The threshold of the gain function for HPF value" line.long 0x1C4 "IPIPE_CAR_GN1_GAN,Chroma Artifact Reduction Register" hexmask.long.byte 0x1C4 0.--7. 1. "VAL,The intensity of the gain function for HPF value" line.long 0x1C8 "IPIPE_CAR_GN1_SHF,Chroma Artifact Reduction Register" bitfld.long 0x1C8 0.--2. "VAL,The down shift value of the gain function on HPF value" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x1CC "IPIPE_CAR_GN1_MIN,Chroma Artifact Reduction Register" hexmask.long.word 0x1CC 0.--8. 1. "VAL,The lower limit of the gain function on HPF value" line.long 0x1D0 "IPIPE_CAR_GN2_GAN,Chroma Artifact Reduction Register" hexmask.long.byte 0x1D0 0.--7. 1. "VAL,The intensity of the gain function for chroma value" line.long 0x1D4 "IPIPE_CAR_GN2_SHF,Chroma Artifact Reduction Register" bitfld.long 0x1D4 0.--3. "VAL,The down shift value of the gain function on chroma value" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,?,?,?,?,?,?,?,?" line.long 0x1D8 "IPIPE_CAR_GN2_MIN,Chroma Artifact Reduction Register" hexmask.long.word 0x1D8 0.--8. 1. "VAL,The lower limit of the gain function on chroma value" line.long 0x1DC "IPIPE_CGS_EN,Chroma Gain Suppression" bitfld.long 0x1DC 0. "EN,Enables or disables chroma gain suppression - NEWENUM1" "EN_0,EN_1" line.long 0x1E0 "IPIPE_CGS_GN1_L_THR,Chroma Gain Suppression" hexmask.long.byte 0x1E0 0.--7. 1. "VAL," line.long 0x1E4 "IPIPE_CGS_GN1_L_GAIN,Chroma Gain Suppression" hexmask.long.byte 0x1E4 0.--7. 1. "VAL," line.long 0x1E8 "IPIPE_CGS_GN1_L_SHF,Chroma Gain Suppression" bitfld.long 0x1E8 0.--2. "VAL," "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x1EC "IPIPE_CGS_GN1_L_MIN,Chroma Gain Suppression" hexmask.long.byte 0x1EC 0.--7. 1. "VAL,The lower limit 1 of the gain function 1" line.long 0x1F0 "IPIPE_CGS_GN1_H_THR,Chroma Gain Suppression" hexmask.long.byte 0x1F0 0.--7. 1. "VAL,The threshold 2 of the gain function for Y value" line.long 0x1F4 "IPIPE_CGS_GN1_H_GAIN,Chroma Gain Suppression" hexmask.long.byte 0x1F4 0.--7. 1. "VAL,The slope 2 of the gain function for Y value" line.long 0x1F8 "IPIPE_CGS_GN1_H_SHF,Chroma Gain Suppression" bitfld.long 0x1F8 0.--2. "VAL,The down shift value of the gain function on Y" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x1FC "IPIPE_CGS_GN1_H_MIN,Chroma Gain Suppression" hexmask.long.byte 0x1FC 0.--7. 1. "VAL,The lower limit 2 of the gain function" line.long 0x200 "IPIPE_CGS_GN2_L_THR,Chroma Gain Suppression" hexmask.long.byte 0x200 0.--7. 1. "VAL,The slope 2 of the gain function for Y value" line.long 0x204 "IPIPE_CGS_GN2_L_GAIN,Chroma Gain Suppression" hexmask.long.byte 0x204 0.--7. 1. "VAL,The down shift value 3 of the gain function on Y" line.long 0x208 "IPIPE_CGS_GN2_L_SHF," bitfld.long 0x208 0.--2. "VAL," "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x20C "IPIPE_CGS_GN2_L_MIN,Chroma Gain Suppression" hexmask.long.byte 0x20C 0.--7. 1. "VAL,The lower limit 3 of the gain function" line.long 0x210 "IPIPE_BOX_EN,Boxcar Register" bitfld.long 0x210 0. "EN,This bit enables ordisables the BOXCAR functionality" "EN_0,EN_1" line.long 0x214 "IPIPE_BOX_MODE,Boxcar Register" bitfld.long 0x214 0. "OST,The processing mode selection of the Boxcar function" "OST_0,OST_1" line.long 0x218 "IPIPE_BOX_TYP,Boxcar Register" bitfld.long 0x218 0. "SEL,Block size in boxcar sampling - NEWENUM1" "SEL_0,SEL_1" line.long 0x21C "IPIPE_BOX_SHF,Boxcar Register" bitfld.long 0x21C 0.--2. "VAL,The down shift value applied to the boxcar compuation result" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x220 "IPIPE_BOX_SDR_SAD_H,Boxcar Register" hexmask.long.word 0x220 0.--15. 1. "VAL,The higher 11 bits of the first address of output in memory" line.long 0x224 "IPIPE_BOX_SDR_SAD_L,Boxcar Register" hexmask.long.word 0x224 5.--15. 1. "VAL,The lower 16 bits of the first address of output in memory" rbitfld.long 0x224 0.--4. "VAL_RESERVED,Ensures 32-byte alignment" "VAL_RESERVED_0,VAL_RESERVED_1,VAL_RESERVED_2,VAL_RESERVED_3,VAL_RESERVED_4,VAL_RESERVED_5,VAL_RESERVED_6,VAL_RESERVED_7,VAL_RESERVED_8,VAL_RESERVED_9,VAL_RESERVED_10,VAL_RESERVED_11,VAL_RESERVED_12,VAL_RESERVED_13,VAL_RESERVED_14,VAL_RESERVED_15,VAL_RESERVED_16,VAL_RESERVED_17,VAL_RESERVED_18,VAL_RESERVED_19,VAL_RESERVED_20,VAL_RESERVED_21,VAL_RESERVED_22,VAL_RESERVED_23,VAL_RESERVED_24,VAL_RESERVED_25,VAL_RESERVED_26,VAL_RESERVED_27,VAL_RESERVED_28,VAL_RESERVED_29,VAL_RESERVED_30,VAL_RESERVED_31" group.long 0x39C++0xBB line.long 0x00 "IPIPE_HST_EN,Histogram" bitfld.long 0x00 0. "EN,This bit enables or disables the HISTOGRAM functionality" "EN_0,EN_1" line.long 0x04 "IPIPE_HST_MODE,Histogram" bitfld.long 0x04 0. "OST,The processing mode selection of the Histogram module" "OST_0,OST_1" line.long 0x08 "IPIPE_HST_SEL,Histogram" bitfld.long 0x08 2. "SEL,Input selection" "SEL_0,SEL_1" bitfld.long 0x08 0.--1. "TYP,G selection in Bayer mode (SEL0=0) - NEWENUM1" "TYP_0,TYP_1,TYP_2,TYP_3" line.long 0x0C "IPIPE_HST_PARA,Histogram COL0. COL1. COL2. and COL3 should be set to ?1?" bitfld.long 0x0C 12.--13. "BIN,The number of the bins" "BIN_0,BIN_1,BIN_2,BIN_3" bitfld.long 0x0C 8.--11. "SHF,The shift length of the input data" "SHF_0,SHF_1,SHF_2,SHF_3,SHF_4,SHF_5,SHF_6,SHF_7,SHF_8,SHF_9,SHF_10,SHF_11,SHF_12,SHF_13,SHF_14,SHF_15" bitfld.long 0x0C 7. "COL3,The on/off selection of the color pattern 3 (Y)" "COL3_0,COL3_1" bitfld.long 0x0C 6. "COL2,The on/off selection of the color pattern 2 (B)" "COL2_0,COL2_1" newline bitfld.long 0x0C 5. "COL1,The on/off selection of the color pattern 1 (G)" "COL1_0,COL1_1" bitfld.long 0x0C 4. "COL0,The on/off selection of the color pattern 0 (R)" "COL0_0,COL0_1" bitfld.long 0x0C 3. "RGN3,The on/off selection of the region 3" "RGN3_0,RGN3_1" bitfld.long 0x0C 2. "RGN2,The on/off selection of the region 2" "RGN2_0,RGN2_1" newline bitfld.long 0x0C 1. "RGN1,The on/off selection of the region 1" "RGN1_0,RGN1_1" bitfld.long 0x0C 0. "RGN0,The on/off selection of the region 0" "RGN0_0,RGN0_1" line.long 0x10 "IPIPE_HST_0_VPS,Histogram" hexmask.long.word 0x10 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x10 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x14 "IPIPE_HST_0_VSZ,Histogram" hexmask.long.word 0x14 1.--12. 1. "VAL,The vertical size of the region 0" rbitfld.long 0x14 0. "VAL_RESERVED,The vertical size of the region 0" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x18 "IPIPE_HST_0_HPS,Histogram" hexmask.long.word 0x18 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x18 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x1C "IPIPE_HST_0_HSZ,Histogram" hexmask.long.word 0x1C 1.--12. 1. "VAL,The horizontal size of the region 0" rbitfld.long 0x1C 0. "VAL_RESERVED,The horizontal size of the region 0" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x20 "IPIPE_HST_1_VPS,Histogram" hexmask.long.word 0x20 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x20 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x24 "IPIPE_HST_1_VSZ,Histogram" hexmask.long.word 0x24 1.--12. 1. "VAL,The vertical size of the region 1" rbitfld.long 0x24 0. "VAL_RESERVED,The vertical size of the region 1" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x28 "IPIPE_HST_1_HPS,Histogram" hexmask.long.word 0x28 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x28 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x2C "IPIPE_HST_1_HSZ,Histogram" hexmask.long.word 0x2C 1.--12. 1. "VAL,The horizontal size of the region 1" rbitfld.long 0x2C 0. "VAL_RESERVED,The horizontal size of the region 1" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x30 "IPIPE_HST_2_VPS,Histogram" hexmask.long.word 0x30 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x30 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x34 "IPIPE_HST_2_VSZ,Histogram" hexmask.long.word 0x34 1.--12. 1. "VAL,The vertical size of the region 2" rbitfld.long 0x34 0. "VAL_RESERVED,The vertical size of the region 2" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x38 "IPIPE_HST_2_HPS,Histogram" hexmask.long.word 0x38 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x38 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x3C "IPIPE_HST_2_HSZ,Histogram" hexmask.long.word 0x3C 1.--12. 1. "VAL,The horizontal size of the region 2" rbitfld.long 0x3C 0. "VAL_RESERVED,The horizontal size of the region 2" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x40 "IPIPE_HST_3_VPS,Histogram" hexmask.long.word 0x40 1.--12. 1. "VAL,The vertical position of the region 0 from theIPIPE_SRC_VPS" rbitfld.long 0x40 0. "VAL_RESERVED,The vertical position of the region 0 from theIPIPE_SRC_VPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x44 "IPIPE_HST_3_VSZ,Histogram" hexmask.long.word 0x44 1.--12. 1. "VAL,The vertical size of the region 3" rbitfld.long 0x44 0. "VAL_RESERVED,The vertical size of the region 3" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x48 "IPIPE_HST_3_HPS,Histogram" hexmask.long.word 0x48 1.--12. 1. "VAL,The horizontal position of the region 0 from theIPIPE_SRC_HPS" rbitfld.long 0x48 0. "VAL_RESERVED,The horizontal position of the region 0 from theIPIPE_SRC_HPS" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x4C "IPIPE_HST_3_HSZ,Histogram" hexmask.long.word 0x4C 1.--12. 1. "VAL,The horizontal size of the region 3" rbitfld.long 0x4C 0. "VAL_RESERVED,The horizontal size of the region 3" "VAL_RESERVED_0,VAL_RESERVED_1" line.long 0x50 "IPIPE_HST_TBL,Histogram" bitfld.long 0x50 1. "CLR,Histogram memory clear" "CLR_0,CLR_1" bitfld.long 0x50 0. "SEL,This bit shall be used to select which memory is used to store the histogram data" "SEL_0,SEL_1" line.long 0x54 "IPIPE_HST_MUL_R,Histogram" hexmask.long.byte 0x54 0.--7. 1. "GAIN,Gain" line.long 0x58 "IPIPE_HST_MUL_GR,Histogram" hexmask.long.byte 0x58 0.--7. 1. "GAIN,Gain" line.long 0x5C "IPIPE_HST_MUL_GB,Histogram" hexmask.long.byte 0x5C 0.--7. 1. "GAIN,Gain" line.long 0x60 "IPIPE_HST_MUL_B,Histogram" hexmask.long.byte 0x60 0.--7. 1. "GAIN,Gain" line.long 0x64 "IPIPE_BSC_EN,Boundary Signal Calculator" bitfld.long 0x64 0. "EN,The start flag of the ?Boundary Signal Calculator?" "EN_0,EN_1" line.long 0x68 "IPIPE_BSC_MODE,Boundary Signal Calculator" bitfld.long 0x68 0. "OST,The processing mode selection of the BSC module" "OST_0,OST_1" line.long 0x6C "IPIPE_BSC_TYP,Boundary Signal Calculator" bitfld.long 0x6C 3. "CEN,Enable of column sampling" "CEN_0,CEN_1" bitfld.long 0x6C 2. "REN,Enable of row sampling - NEWENUM1" "REN_0,REN_1" bitfld.long 0x6C 0.--1. "COL,Selects the element to be summed" "COL_0,COL_1,COL_2,COL_3" line.long 0x70 "IPIPE_BSC_ROW_VCT,Boundary Signal Calculator" bitfld.long 0x70 0.--1. "VAL,The number of row sum vectors" "VAL_0,VAL_1,VAL_2,VAL_3" line.long 0x74 "IPIPE_BSC_ROW_SHF,Boundary Signal Calculator" bitfld.long 0x74 0.--2. "VAL,The down shift value for row sum vectors" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x78 "IPIPE_BSC_ROW_VPOS,Boundary Signal Calculator" hexmask.long.word 0x78 0.--12. 1. "VAL,The vertical position of the first sampling pixel; the first row to be summed" line.long 0x7C "IPIPE_BSC_ROW_VNUM,Boundary Signal Calculator" hexmask.long.word 0x7C 1.--12. 1. "VAL,The height of the area covered by a row sum vector" rbitfld.long 0x7C 0. "VAL_0,The LSB must be odd" "0,1" line.long 0x80 "IPIPE_BSC_ROW_VSKIP,Boundary Signal Calculator" bitfld.long 0x80 0.--4. "VAL,The interval of the rows" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x84 "IPIPE_BSC_ROW_HPOS,Boundary Signal Calculator" hexmask.long.word 0x84 0.--12. 1. "VAL,The horizontal position of the first sampling pixel; the first pixel in a row to be summed" line.long 0x88 "IPIPE_BSC_ROW_HNUM,Boundary Signal Calculator" hexmask.long.word 0x88 0.--12. 1. "VAL,The horizontal number of samples in the area covered by a row sum vector" line.long 0x8C "IPIPE_BSC_ROW_HSKIP,Boundary Signal Calculator" bitfld.long 0x8C 0.--4. "VAL,The interval of the pixels in a row to be summed" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0x90 "IPIPE_BSC_COL_VCT,Boundary Signal Calculator" bitfld.long 0x90 0.--1. "VAL,The number of column sum vectors" "VAL_0,VAL_1,VAL_2,VAL_3" line.long 0x94 "IPIPE_BSC_COL_SHF,Boundary Signal Calculator" bitfld.long 0x94 0.--2. "VAL,The down shift value for column sum vectors" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7" line.long 0x98 "IPIPE_BSC_COL_VPOS,Boundary Signal Calculator" hexmask.long.word 0x98 0.--12. 1. "VAL,The vertical position of the first sampling pixel; the first pixel in a column to be summed" line.long 0x9C "IPIPE_BSC_COL_VNUM,Boundary Signal Calculator" hexmask.long.word 0x9C 0.--12. 1. "VAL,The vertical number of samples in the area covered by a column sum vector" line.long 0xA0 "IPIPE_BSC_COL_VSKIP,Boundary Signal Calculator" bitfld.long 0xA0 0.--4. "VAL,The interval of the pixels in a column to be summed" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0xA4 "IPIPE_BSC_COL_HPOS,Boundary Signal Calculator" hexmask.long.word 0xA4 0.--12. 1. "VAL,The horizontal position of the first sampling pixel; the first column to be summed" line.long 0xA8 "IPIPE_BSC_COL_HNUM,Boundary Signal Calculator" hexmask.long.word 0xA8 1.--12. 1. "VAL,The width of the area covered by a column sum vector" rbitfld.long 0xA8 0. "VAL_0,The LSB must be odd" "0,1" line.long 0xAC "IPIPE_BSC_COL_HSKIP,Boundary Signal Calculator" bitfld.long 0xAC 0.--4. "VAL,The interval of the columns" "VAL_0,VAL_1,VAL_2,VAL_3,VAL_4,VAL_5,VAL_6,VAL_7,VAL_8,VAL_9,VAL_10,VAL_11,VAL_12,VAL_13,VAL_14,VAL_15,VAL_16,VAL_17,VAL_18,VAL_19,VAL_20,VAL_21,VAL_22,VAL_23,VAL_24,VAL_25,VAL_26,VAL_27,VAL_28,VAL_29,VAL_30,VAL_31" line.long 0xB0 "IPIPE_YUV_INP_OFST_Y,Offset value applied to Y input becore YUVtoRGB matrix" hexmask.long.word 0xB0 0.--8. 1. "Y_OFST,Y offset value (s9) Usually zero" line.long 0xB4 "IPIPE_YUV_INP_OFST_CB,Offset value applied to CB input becore YUVtoRGB matrix" hexmask.long.word 0xB4 0.--8. 1. "CB_OFST,Cb offset value (s9) Usually -128" line.long 0xB8 "IPIPE_YUV_INP_OFST_CR,Offset value applied to CR input becore YUVtoRGB matrix" hexmask.long.word 0xB8 0.--8. 1. "CR_OFST,Cr offset value (s9) Usually -128" repeat 8. (list 00. 01. 02. 03. 04. 05. 06. 07. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x150)++0x03 line.long 0x00 "IPIPE_D2F_2ND_THR$1,Noise Filter 2 Register" hexmask.long.word 0x00 0.--9. 1. "VAL,Threshold values in noise filter-2 algorithm" repeat.end repeat 2. (list 2. 1. )(list 0x00 0x04 ) group.long ($2+0xA4)++0x03 line.long 0x00 "IPIPE_LSC_HA$1," hexmask.long.word 0x00 0.--12. 1. "VAL,LSC HA2" repeat.end repeat 2. (list 2. 1. )(list 0x00 0x04 ) group.long ($2+0x94)++0x03 line.long 0x00 "IPIPE_LSC_VA$1," hexmask.long.word 0x00 0.--12. 1. "VAL,LSC VA2" repeat.end width 0x0B tree.end tree "ISP6P5_IPIPEIF" base ad:0x52041200 group.long 0x00++0x73 line.long 0x00 "IPIPEIF_ENABLE,IPIPEIF Enable" bitfld.long 0x00 1. "SYNCOFF,VD output mask This register masks the VD output to the IPIPE module" "SYNCOFF_0,SYNCOFF_1" bitfld.long 0x00 0. "ENABLE,IPIPE I/F Enable This register is used to start the operation of SDRAM buffer memory read and generates SYNC signals" "ENABLE_0,ENABLE_1" line.long 0x04 "IPIPEIF_CFG1,IPIPEIF Configuration #1" bitfld.long 0x04 14.--15. "INPSRC1,Selects the source for the mux (VPORT / ISIF / SDRAM) as well as the data format type" "INPSRC1_0,INPSRC1_1,INPSRC1_2,INPSRC1_3" bitfld.long 0x04 11.--13. "DATASFT,SDRAM read data shift This register is available when INPSRC1 or INPSRC2 = 1 or 2 i.e. when data are read from SDRAM" "DATASFT_0,DATASFT_1,DATASFT_2,DATASFT_3,DATASFT_4,DATASFT_5,DATASFT_6,DATASFT_7" bitfld.long 0x04 10. "CLKSEL,IPIPEIF IPIPE module pixel clock selection" "CLKSEL_0,CLKSEL_1" bitfld.long 0x04 8.--9. "UNPACK,8-Bit 12-bit Packed Mode When sensor raw data are stored in 8-bit packed mode or 12-bit packed mode this register should code 1 or 3" "UNPACK_0,UNPACK_1,UNPACK_2,UNPACK_3" bitfld.long 0x04 7. "AVGFILT,Averaging Filter It applies (1 2 1) filter for the RGB/YCbCr data" "AVGFILT_0,AVGFILT_1" newline bitfld.long 0x04 4. "RAW16_SDRAM,RAW16/12 format of SDRAM This affect how DATASFT works" "0,1" bitfld.long 0x04 2.--3. "INPSRC2,Selects the source for the mux (ISIF / SDRAM) as well as the data format type" "INPSRC2_0,INPSRC2_1,INPSRC2_2,INPSRC2_3" bitfld.long 0x04 1. "DECIM,Pixel Decimation The decimation rate defined by RSZ register" "DECIM_0,DECIM_1" bitfld.long 0x04 0. "ONESHOT,One Shot Mode This register is available when INPSRC = 1 or 3" "ONESHOT_0,ONESHOT_1" line.long 0x08 "IPIPEIF_PPLN,IPIPEIF Interval of HD / Start pixel in HD" hexmask.long.word 0x08 0.--12. 1. "PPLN,Case-1: Interval of Horizontal Sync (HD) Specifies the interval of horizontal sync" line.long 0x0C "IPIPEIF_LPFR,IPIPEIF Interval of VD / Start line in VD" hexmask.long.word 0x0C 0.--12. 1. "LPFR,Case-1: Interval of Vertical Sync (VD) Specifies the interval of vertical sync" line.long 0x10 "IPIPEIF_HNUM,IPIPEIF Number of valid pixels per line" hexmask.long.word 0x10 0.--12. 1. "HNUM,The Number of Valid Pixels in a Line Specifies the number of valid pixels in a horizontal line" line.long 0x14 "IPIPEIF_VNUM,IPIPEIF Number of valid lines per frame" hexmask.long.word 0x14 0.--12. 1. "VNUM,The Number of Valid Line in a Vertical Specifies the number of valid line in a vertical" line.long 0x18 "IPIPEIF_ADDRU,IPIPEIF Memory Address (Upper)" hexmask.long.word 0x18 0.--10. 1. "ADDRU,Memory Address ? Upper Memory address upper 11-bits are specified in units of 32-bytes This register is available when INPSRC = 1 2 or 3" line.long 0x1C "IPIPEIF_ADDRL,IPIPEIF Memory Address (Lower)" hexmask.long.word 0x1C 0.--15. 1. "ADDRL,Memory Address - Lower Memory address lower 16-bits are specified in units of 32-bytes" line.long 0x20 "IPIPEIF_ADOFS,IPIPEIF Address offset" hexmask.long.word 0x20 0.--11. 1. "ADOFS,Specifies the SDRAM stride for each line in units of 32-bytes" line.long 0x24 "IPIPEIF_RSZ,IPIPEIF Horizontal Resizing Parameter on IPIPE datapath" hexmask.long.byte 0x24 0.--6. 1. "RSZ,Horizontal Resizing Parameter for IPIPE datapath Specifies the horizontal resizing parameter" line.long 0x28 "IPIPEIF_GAIN,IPIPEIF Gain Parameter" hexmask.long.word 0x28 0.--9. 1. "GAIN,Gain Parameter Specifies the gain applied to RAW data before it is forwarded to the IPIPE module" line.long 0x2C "IPIPEIF_DPCM,IPIPEIF DPCM configuration This register applies only if.UNPACK = 1. i.e.. RAW8 data is read from SDRAM" bitfld.long 0x2C 2. "BITS,DPCM bit mode for SDRAM data This register access is enabled by the Nokia Custom key - _8TO10" "BITS_0,BITS_1" bitfld.long 0x2C 1. "PRED,DPCM prediction mode for SDRAM data This register access is enabled by the Nokia Custom key - SIMPLE" "PRED_0,PRED_1" bitfld.long 0x2C 0. "ENA,DPCM decompression enable for SDRAM data" "ENA_0,ENA_1" line.long 0x30 "IPIPEIF_CFG2,IPIPEIF Configuration #2" bitfld.long 0x30 7. "YUV8P,8-bit YUV data unpacking to 16 bits WhenIPIPEIF_CFG1.INPSRC2 = 0 and IPIPEIF_CFG2.YUV16 = 1 the 8-bit YUV data are transformed into 16-bit YUV data" "YUV8P_0,YUV8P_1" bitfld.long 0x30 6. "YUV8,YUV 8bit mode When ISIF_CFG1.INPSRC2 = 0 and YUV16 = 1 setting this bit to 1 enables the conversion from 8bit YUV input to 16bit YUV" "YUV8_0,YUV8_1" bitfld.long 0x30 5. "DFSDIR,DFS direction Selects the direction of dark frame subtraction" "DFSDIR_0,DFSDIR_1" bitfld.long 0x30 4. "WENE,External WEN signal selection" "WENE_0,WENE_1" bitfld.long 0x30 3. "YUV16,Data type selection" "YUV16_0,YUV16_1" newline bitfld.long 0x30 2. "VDPOL,VD Sync Polarity When input VD is active low SYNC pulse this bit needs to be set to ?1?" "VDPOL_0,VDPOL_1" bitfld.long 0x30 1. "HDPOL,HD Sync Polarity When input HD is active low SYNC pulse this bit needs to be set to ?1?" "HDPOL_0,HDPOL_1" bitfld.long 0x30 0. "INTSW,IPIPEIF interrupt source selection" "INTSW_0,INTSW_1" line.long 0x34 "IPIPEIF_INIRSZ,IPIPEIF resize initial position - IPIPE data path" bitfld.long 0x34 13. "ALNSYNC,Align the HSYNC VSYNC to initial position defined by INIRSZ" "ALNSYNC_0,ALNSYNC_1" hexmask.long.word 0x34 0.--12. 1. "INIRSZ,Offset used to re-initialize the HD/VD position after resizer" line.long 0x38 "IPIPEIF_OCLIP,IPIPEIF output clipping value" hexmask.long.word 0x38 0.--15. 1. "OCLIP,Output clipping value after gain control on IPIPE data path" line.long 0x3C "IPIPEIF_DTUDF,IPIPEIF data underflow detection" bitfld.long 0x3C 2.--5. "FIFOWMRKLVL,To guarantee that the FIFO does not overflow the stall request is deasserted only when a certain number of locations in the FIFO are free" "FIFOWMRKLVL_0,FIFOWMRKLVL_1,FIFOWMRKLVL_2,FIFOWMRKLVL_3,FIFOWMRKLVL_4,FIFOWMRKLVL_5,FIFOWMRKLVL_6,FIFOWMRKLVL_7,FIFOWMRKLVL_8,FIFOWMRKLVL_9,FIFOWMRKLVL_10,FIFOWMRKLVL_11,FIFOWMRKLVL_12,FIFOWMRKLVL_13,FIFOWMRKLVL_14,FIFOWMRKLVL_15" bitfld.long 0x3C 1. "ENM2MSTALL,Enable memory-to-memory stall mechanism - DISABLE" "ENM2MSTALL_0,ENM2MSTALL_1" bitfld.long 0x3C 0. "DTUDF,Data under flow error status register" "DTUDF_0,DTUDF_1" line.long 0x40 "IPIPEIF_CLKDIV,IPIPEIF CLOCK DIVIDER" hexmask.long.word 0x40 0.--15. 1. "CLKDIV,IPIPEIF clock rate configuration IPIPE/IPIPEIF clock frequency = M/N x clk_vpss clock frequency" line.long 0x44 "IPIPEIF_DPC1,IPIPEIF defect pixel correction #1" bitfld.long 0x44 12. "ENA,DPC enable" "ENA_0,ENA_1" hexmask.long.word 0x44 0.--11. 1. "TH,DPC threshold value" line.long 0x48 "IPIPEIF_DPC2,IPIPEIF defect pixel correction #2" bitfld.long 0x48 12. "ENA,DPC enable" "ENA_0,ENA_1" hexmask.long.word 0x48 0.--11. 1. "TH,DPC threshold value" line.long 0x4C "IPIPEIF_DFSGVL,IPIPEIF DARK FRAME GAIN CONTROL - GAIN VALUE" bitfld.long 0x4C 10. "DFSGEN,DFS gain control enable" "DFSGEN_0,DFSGEN_1" hexmask.long.word 0x4C 0.--9. 1. "DFSGVL,DFS gain value" line.long 0x50 "IPIPEIF_DFSGTH,IPIPEIF DARK FRAME GAIN CONTROL - THRESHOLD VALUE" hexmask.long.word 0x50 0.--11. 1. "DFSGTH,DFS gain threshold value" line.long 0x54 "IPIPEIF_RSZ3A,IPIPEIF HORIZONTAL RESIZING PARAMETER FOR H3A" bitfld.long 0x54 9. "DECIM,Pixel Decimation Enable The decimation rate defined by the RSZ bitfield" "DECIM_0,DECIM_1" bitfld.long 0x54 8. "AVGFILT,Averaging Filter It applies a (1 2 1) filter for the RGB/YCbCr data" "AVGFILT_0,AVGFILT_1" hexmask.long.byte 0x54 0.--6. 1. "RSZ,Horizontal Resizing Parameter for H3A datapath Specifies the horizontal resizing parameter" line.long 0x58 "IPIPEIF_INIRSZ3A,IPIPEIF resize initial position - H3A data path" bitfld.long 0x58 13. "ALNSYNC,Align the HD VD to initial position defined by the INIRSZ bit field" "ALNSYNC_0,ALNSYNC_1" hexmask.long.word 0x58 0.--12. 1. "INIRSZ,Offset used to re-initialize the HD/VD position after resizer" line.long 0x5C "IPIPEIF_CFG3,Parameters for Circular buffering" bitfld.long 0x5C 29. "HSK_EOF,Issue C_DONE at the end of frame" "HSK_EOF_0,HSK_EOF_1" bitfld.long 0x5C 28. "HSK_EN,Handshake with ICM is enabled Note: If ICM handshake is on in DFS/WDR mode (INPSRC1=2 or INPSRC2=2) memory-to-memory stall mechanism must be on (IPIPEIF_DTUDF.ENM2MSTALL=1) *This bit field is latched by VD" "HSK_EN_0,HSK_EN_1" hexmask.long.word 0x5C 16.--27. 1. "CYN,ICM Handshake cycle U12 *This bit field is latched by VD" bitfld.long 0x5C 12. "CIR_EN,Enable circular buffering *This bit field is latched by VD" "CIR_EN_0,CIR_EN_1" hexmask.long.word 0x5C 0.--11. 1. "CBN,Circular buffer cycle U12 *This bit field is latched by VD" line.long 0x60 "IPIPEIF_CFG4,IPIPEIF WDR configuration for WDR merging" bitfld.long 0x60 16.--20. "DST,Down shift value after WDR merge *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x60 8.--11. "SBIT,Shift up value for short exposure pixel Usually set (16- (bit width of long exposure pixels))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 4.--7. "LBIT,Shift up value for long exposure pixel Usually set (16- (bit width of long exposure pixels))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x60 1. "WGT_SEL,Select the source for weight calculation in WDR merge *This bit field is latched by VD" "WGT_SEL_0,WGT_SEL_1" bitfld.long 0x60 0. "WDR_EN,Enable WDR merge (Two frame/single frame) When this function is enabled WDR is used instead of DFS" "WDR_EN_0,WDR_EN_1" line.long 0x64 "IPIPEIF_WDRAF,WDR Merge parameter AF_M" bitfld.long 0x64 20.--24. "AFE,WDR Merge parameter AFE Exponential part of a value in weight calculation Unsigned 5bit *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x64 0.--15. 1. "AFM,WDR Merge parameter AF_M Coefficient (mantissa) part of a value in weight calculation Signed 16bit *This bit field is latched by VD" line.long 0x68 "IPIPEIF_WDRBF,WDR Merge parameter BF" hexmask.long.word 0x68 0.--15. 1. "BF,WDR Merge parameter BF Q0.15) The actual value is BF x 2^-16 x 2^-5 *This bit field is latched by VD" line.long 0x6C "IPIPEIF_WDRGAIN,Gain difference between long exposure and short exposure" hexmask.long.word 0x6C 16.--31. 1. "GSHORT,The gain applied to short exposure pixels" hexmask.long.word 0x6C 0.--15. 1. "GLONG,The gain applied to long exposure pixels" line.long 0x70 "IPIPEIF_WDRTHR,Threshold value in WDR merging" hexmask.long.word 0x70 0.--15. 1. "THR,T (Threshold value) U16 *This bit field is latched by VD" hgroup.long 0x74++0x07 hide.long 0x00 "IPIPEIF_RSVD1,White Balance used in weight calculation" hide.long 0x04 "IPIPEIF_RSVD2," group.long 0x7C++0x3F line.long 0x00 "IPIPEIF_WDRLBK1,Black level for Long exposure input" hexmask.long.word 0x00 16.--27. 1. "LBK01,Black level for long exposure pixel at [0 1] (Odd pixel at even line) U12 *This bit field is latched by VD" hexmask.long.word 0x00 0.--11. 1. "LBK00,Black level for long exposure pixel at [0 0] (Even pixel at even line) U12 *This bit field is latched by VD" line.long 0x04 "IPIPEIF_WDRLBK2,Black level for Long exposure input" hexmask.long.word 0x04 16.--27. 1. "LBK11,Black level for long exposure pixel at [1 1] (Odd pixel at odd line) U12 *This bit field is latched by VD" hexmask.long.word 0x04 0.--11. 1. "LBK10,1lack level for long exposure pixel at [1 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD" line.long 0x08 "IPIPEIF_WDRSBK1,Black level for short exposure input" hexmask.long.word 0x08 16.--27. 1. "SBK01,Black level for short exposure pixel at [0 1] (Odd pixel at even line) U12 *This bit field is latched by VD" hexmask.long.word 0x08 0.--11. 1. "SBK00,Black level for short exposure pixel at [0 0] (Even pixel at even line) U12 *This bit field is latched by VD" line.long 0x0C "IPIPEIF_WDRSBK2,Black level for short exposure input" hexmask.long.word 0x0C 16.--27. 1. "SBK11,Black level for short exposure pixel at [1 1] (Odd pixel at odd line) U12 *This bit field is latched by VD" hexmask.long.word 0x0C 0.--11. 1. "SBK10,1lack level for short exposure pixel at [1 0 ] (Even pixel at odd line) U12 *This bit field is latched by VD" line.long 0x10 "IPIPEIF_WDRMA,Threshold value in motion adaptive filter" hexmask.long.word 0x10 16.--31. 1. "MAS,Slope in motion adaptive filter MAS = 32768/(D2-D1) U16 *This bit field is latched by VD" hexmask.long.word 0x10 0.--15. 1. "MAD,Threshold (D1) in motion adaptive filter U16 To disable MA filtering put the maximum value (65535: default) *This bit field is latched by VD" line.long 0x14 "IPIPEIF_WDRSAT_VP,Saturation parameters for VPORT input" hexmask.long.tbyte 0x14 0.--19. 1. "VP_SAT,Saturation value for VPORT input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0x18 "IPIPEIF_WDRSAT_VP2,Saturation parameters for VPORT input" hexmask.long.byte 0x18 8.--15. 1. "VP_DCCLMP,DC Clamp addition value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0x18 3.--7. "VP_DSF,Down shift value for VPORT input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 0. "VP_SATEN,Enable saturation function on VPort *This bit field is latched by VD" "VP_SATEN_0,VP_SATEN_1" line.long 0x1C "IPIPEIF_WDRSAT_ISIF,Saturation parameters for ISIF input" hexmask.long.tbyte 0x1C 0.--19. 1. "ISIF_SAT,Saturation value for ISIF input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0x20 "IPIPEIF_WDRSAT_ISIF2,Saturation value for ISIF input" hexmask.long.byte 0x20 8.--15. 1. "ISIF_DCCLMP,DC Clamp addition value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0x20 3.--7. "ISIF_DSF,Down shift value for ISIF input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x20 0. "ISIF_SATEN,Enable saturation function on ISIF port *This bit field is latched by VD" "ISIF_SATEN_0,ISIF_SATEN_1" line.long 0x24 "IPIPEIF_WDRSAT_SD,Saturation parameters for SDRAM input" hexmask.long.tbyte 0x24 0.--19. 1. "SD_SAT,Saturation value for SDRAM input used in WDR split function for pseudo-long-exposure image Do disable set maximum value (1048575: default) *This bit field is latched by VD" line.long 0x28 "IPIPEIF_WDRSAT_SD2,Saturation params for SDRAM input" hexmask.long.byte 0x28 8.--15. 1. "SD_DCCLMP,DC Clamp addition value for SD Port input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" bitfld.long 0x28 3.--7. "SD_DSF,Down shift value for SDRAM input (Used in WDR split function for pseudo-short-exposure) *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x28 0. "SD_SATEN,Enable saturation function on SDRAM *This bit field is latched by VD" "SD_SATEN_0,SD_SATEN_1" line.long 0x2C "IPIPEIF_WDRLWB1,White Balance used in weight calculation" hexmask.long.word 0x2C 16.--28. 1. "LWB01,White balance for pixels at [0 1] (Odd pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" hexmask.long.word 0x2C 0.--12. 1. "LWB00,White balance for pixels at [0 0] (Even pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0x30 "IPIPEIF_WDRLWB2,White Balance used in weight calculation" hexmask.long.word 0x30 16.--28. 1. "LWB11,White balance for pixels at [0 1] (Odd pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" hexmask.long.word 0x30 0.--12. 1. "LWB10,White balance for pixels at [1 0] (Even pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0x34 "IPIPEIF_WDRSWB1,White Balance used in weight calculation" hexmask.long.word 0x34 16.--28. 1. "SWB01,White balance for pixels at [0 1] (Odd pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" hexmask.long.word 0x34 0.--12. 1. "SWB00,White balance for pixels at [0 0] (Even pixel at even line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0x38 "IPIPEIF_WDRSWB2,White Balance used in weight calculation" hexmask.long.word 0x38 16.--28. 1. "SWB11,White balance for pixels at [0 1] (Odd pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" hexmask.long.word 0x38 0.--12. 1. "SWB10,White balance for pixels at [1 0] (Even pixel at odd line) U4.9 (for gain=1.0 set 512) *This bit field is latched by VD" line.long 0x3C "IPIPEIF_VPDCMPXTHR1,Threshold value in VP Decomanding" hexmask.long.word 0x3C 0.--15. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" group.long 0xC4++0x23 line.long 0x00 "IPIPEIF_VPDCMPYTHR1,Threshold value in VP Decomanding" hexmask.long.tbyte 0x00 0.--19. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x04 "IPIPEIF_VPDCMPYTHR2,Threshold value in VP Decomanding" hexmask.long.tbyte 0x04 0.--19. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x08 "IPIPEIF_VPDCMPYTHR3,Threshold value in VP Decomanding" hexmask.long.tbyte 0x08 0.--19. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" line.long 0x0C "IPIPEIF_VPDCMPSLOPE1,Slope value in VP Decomanding" hexmask.long.word 0x0C 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" line.long 0x10 "IPIPEIF_VPDCMPSLOPE2,Slope value in VP Decomanding" hexmask.long.word 0x10 0.--15. 1. "SLOPE2,SLOPE_2 (Slope value) U16 *This bit field is latched by VD" line.long 0x14 "IPIPEIF_VPDCMPSLOPE3,Slope value in VP Decomanding" hexmask.long.word 0x14 0.--15. 1. "SLOPE3,SLOPE_3 (Slope value) U16 *This bit field is latched by VD" line.long 0x18 "IPIPEIF_VPDCMPSLOPE4,Slope value in VP Decomanding" hexmask.long.word 0x18 0.--15. 1. "SLOPE4,SLOPE_4 (Slope value) U16 *This bit field is latched by VD" line.long 0x1C "IPIPEIF_VPDCMPCFG,Configuration register for VP Decomanding" bitfld.long 0x1C 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x1C 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x20 "IPIPEIF_SDDCMPXTHR1,Threshold value in SD Decomanding" hexmask.long.word 0x20 0.--15. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" group.long 0xF0++0x37 line.long 0x00 "IPIPEIF_SDDCMPYTHR1,Threshold value in SD Decomanding" hexmask.long.tbyte 0x00 0.--19. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x04 "IPIPEIF_SDDCMPYTHR2,Threshold value in SD Decomanding" hexmask.long.tbyte 0x04 0.--19. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x08 "IPIPEIF_SDDCMPYTHR3,Threshold value in SD Decomanding" hexmask.long.tbyte 0x08 0.--19. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" line.long 0x0C "IPIPEIF_SDDCMPSLOPE1,Slope value in SD Decomanding" hexmask.long.word 0x0C 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" line.long 0x10 "IPIPEIF_SDDCMPSLOPE2,Slope value in SD Decomanding" hexmask.long.word 0x10 0.--15. 1. "SLOPE2,SLOPE_2 (Slope value) U16 *This bit field is latched by VD" line.long 0x14 "IPIPEIF_SDDCMPSLOPE3,Slope value in SD Decomanding" hexmask.long.word 0x14 0.--15. 1. "SLOPE3,SLOPE_3 (Slope value) U16 *This bit field is latched by VD" line.long 0x18 "IPIPEIF_SDDCMPSLOPE4,Slope value in SD Decomanding" hexmask.long.word 0x18 0.--15. 1. "SLOPE4,SLOPE_4 (Slope value) U16 *This bit field is latched by VD" line.long 0x1C "IPIPEIF_SDDCMPCFG,Configuration register for SD Decomanding" bitfld.long 0x1C 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x1C 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x1C 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x20 "IPIPEIF_WDRCMPXTHR1,Threshold value in SD WDR Companding" hexmask.long.tbyte 0x20 0.--19. 1. "XTHR1,X_THR_1 (Threshold value) U16 *This bit field is latched by VD" line.long 0x24 "IPIPEIF_WDRCMPXTHR2,Threshold value in WDR Companding" hexmask.long.tbyte 0x24 0.--19. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" line.long 0x28 "IPIPEIF_WDRCMPXTHR3,Threshold value in WDR Decompanding" hexmask.long.tbyte 0x28 0.--19. 1. "XTHR3,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" line.long 0x2C "IPIPEIF_WDRCMPYTHR1,Threshold value in WDR Companding" hexmask.long.word 0x2C 0.--15. 1. "YTHR1,Y_THR_1 (Threshold value) U20 *This bit field is latched by VD" line.long 0x30 "IPIPEIF_WDRCMPYTHR2,Threshold value in WDR Decompanding" hexmask.long.word 0x30 0.--15. 1. "YTHR2,Y_THR_2 (Threshold value) U20 *This bit field is latched by VD" line.long 0x34 "IPIPEIF_WDRCMPYTHR3,Threshold value in WDR Companding" hexmask.long.word 0x34 0.--15. 1. "YTHR3,Y_THR_3 (Threshold value) U20 *This bit field is latched by VD" group.long 0x138++0x07 line.long 0x00 "IPIPEIF_WDRCMPCFG,Configuration register for WDR Decompanding" bitfld.long 0x00 24.--28. "SHIFT,Shift value for PWL U5 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. "LUTBITSEL,LUTBITSEL (For selecting address to LUT) U4 *This bit field is latched by VD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "LUTSET,Select Bit '0' : Choose PWL '1' : Choose LUT *This bit field is latched by VD" "0,1" bitfld.long 0x00 0. "ENABLE,Enable for VP Decompanding *This bit field is latched by VD" "0,1" line.long 0x04 "IPIPEIF_WDRMRGCFG,Configuration register for WDR Merge" bitfld.long 0x04 24.--26. "MRGWTSFT,Shift value for Weight black U3 *This bit field is latched by VD" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x04 0.--19. 1. "WDRCLIP,Clip value after WDR Merge *This bit field is latched by VD" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x128)++0x03 line.long 0x00 "IPIPEIF_WDRCMPSLOPE$1,Slope value in WDR Decompanding" hexmask.long.word 0x00 0.--15. 1. "SLOPE1,SLOPE_1 (Slope value) U16 *This bit field is latched by VD" repeat.end repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0xE8)++0x03 line.long 0x00 "IPIPEIF_SDDCMPXTHR$1,Threshold value in SD Decompanding" hexmask.long.word 0x00 0.--15. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" repeat.end repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0xBC)++0x03 line.long 0x00 "IPIPEIF_VPDCMPXTHR$1,Threshold value in VP Decompanding" hexmask.long.word 0x00 0.--15. 1. "XTHR2,X_THR_2 (Threshold value) U16 *This bit field is latched by VD" repeat.end width 0x0B tree.end tree "ISP6P5_ISIF" base ad:0x52041000 group.long 0x00++0x1C7 line.long 0x00 "ISIF_SYNCEN," bitfld.long 0x00 1. "DWEN,Controls the storage of image sensor RAW data in memory" "DWEN_0,DWEN_1" bitfld.long 0x00 0. "SYEN,Controls ON/OFF of VD/HD output" "SYEN_0,SYEN_1" line.long 0x04 "ISIF_MODESET," rbitfld.long 0x04 15. "MDFS,Field Status This bit indicates the status of the current FLD signal when the ISIF module is in interlaced mode" "MDFS_0,MDFS_1" bitfld.long 0x04 14. "HLPF,Low pass filter enable" "HLPF_0,HLPF_1" newline bitfld.long 0x04 12.--13. "INPMOD,Data input mode: - NEWENUM1" "INPMOD_0,INPMOD_1,INPMOD_2,INPMOD_3" bitfld.long 0x04 11. "OVF,ISIF module write port overflow status bit" "OVF_0,OVF_1" newline bitfld.long 0x04 8.--10. "CCDW,This bit enables to shift right (divide) the up-to-12-bit RAW data value when writing out to SDRAM" "CCDW_0,CCDW_1,CCDW_2,CCDW_3,CCDW_4,CCDW_5,CCDW_6,CCDW_7" bitfld.long 0x04 7. "CCDMD,Field mode: This bit selects the type of image sensor: interlaced or progressive - NEWENUM1" "CCDMD_0,CCDMD_1" newline bitfld.long 0x04 6. "DPOL,Image sensor input data polarity - NEWENUM1" "DPOL_0,DPOL_1" bitfld.long 0x04 5. "SWEN,External WEN selection In case this bit and SYNCEN.DWEN are set to 1 the external WEN signal is used to store image sensor data to memory" "SWEN_0,SWEN_1" newline bitfld.long 0x04 4. "FIPOL,FLD Signal Polarity - NEWENUM1" "FIPOL_0,FIPOL_1" bitfld.long 0x04 3. "HDPOL,HD Sync Signal Polarity - NEWENUM1" "HDPOL_0,HDPOL_1" newline bitfld.long 0x04 2. "VDPOL,VD Sync Signal Polarity - NEWENUM1" "VDPOL_0,VDPOL_1" bitfld.long 0x04 1. "FIDD,FLD Signal Direction There shall be at least three clock cycles between the time this bit is modified and the HD/VD pulse for start of frame comes" "FIDD_0,FIDD_1" newline bitfld.long 0x04 0. "HDVDD,VD HD Sync Signal Direction There shall be at least three clock cycles between the time this bit is modified and the HD/VD pulse for start of frame comes" "HDVDD_0,HDVDD_1" line.long 0x08 "ISIF_HDW," hexmask.long.word 0x08 0.--11. 1. "HDW,HD width: Sets width of HD" line.long 0x0C "ISIF_VDW," hexmask.long.word 0x0C 0.--11. 1. "VDW,VD width : Sets width of VD" line.long 0x10 "ISIF_PPLN," hexmask.long.word 0x10 0.--15. 1. "PPLN,Pixels per line Number of pixel clock periods in one line HD period = PPLN+1 pixel clocks" line.long 0x14 "ISIF_LPFR,Line per Frame/Field" hexmask.long.word 0x14 0.--15. 1. "LPFR,Half lines per filed or frame Sets number of half lines per frame or field" line.long 0x18 "ISIF_SPH,Start Pixel Horizontal" hexmask.long.word 0x18 0.--14. 1. "SPH,The first pixel in a line to be stored to memory" line.long 0x1C "ISIF_LNH," hexmask.long.word 0x1C 0.--14. 1. "LNH,Number of pixels in an line to be stored to memory" line.long 0x20 "ISIF_SLV0," hexmask.long.word 0x20 0.--14. 1. "SLV0,Start Line Vertical (Field 0) Sets line at which data output to SDRAM will begin measured from the start of VD *This bit field is latched by VD" line.long 0x24 "ISIF_SLV1," hexmask.long.word 0x24 0.--14. 1. "SLV1,Start Line Vertical (Field 1) Sets line at which data output to SDRAM will begin measured from the start of VD *This bit field is latched by VD" line.long 0x28 "ISIF_LNV," hexmask.long.word 0x28 0.--14. 1. "LNV,The number of lines to be stored to memory" line.long 0x2C "ISIF_CULH,This register specifies horizontal culling" hexmask.long.byte 0x2C 8.--15. 1. "CLHE,Culling Pattern in EVEN Line: Sets culling pattern when data is loaded into memory (even lines)" hexmask.long.byte 0x2C 0.--7. 1. "CLHO,Culling Pattern in ODD Line: Sets culling pattern when data is loaded into memory (odd lines)" line.long 0x30 "ISIF_CULV," hexmask.long.byte 0x30 0.--7. 1. "CULV,Culling Pattern in Vertical Line Note: CULV[0] must be 1 for proper operation" line.long 0x34 "ISIF_HSIZE,SDRAM OUTPUT CTRL REGISTER" bitfld.long 0x34 12. "ADCR,SDRAM address decrement" "ADCR_0,ADCR_1" hexmask.long.word 0x34 0.--11. 1. "HSIZE,Memory address offset between the lines" line.long 0x38 "ISIF_SDOFST,SDRAM OUTPUT CTRL REGISTER" bitfld.long 0x38 14. "FIINV,FID polarity: This bit inverse a FID polarity" "FIINV_0,FIINV_1" bitfld.long 0x38 12.--13. "FOFST,Field line offset value in odd (FID = 1) field - NEWENUM1" "FOFST_0,FOFST_1,FOFST_2,FOFST_3" newline bitfld.long 0x38 9.--11. "LOFSTEE,Field line offset value applied after even line even field (This value affects the first address of odd lines) - NEWENUM7" "LOFSTEE_0,LOFSTEE_1,LOFSTEE_2,LOFSTEE_3,LOFSTEE_4,LOFSTEE_5,LOFSTEE_6,LOFSTEE_7" bitfld.long 0x38 6.--8. "LOFSTOE,Field line offset value applied after odd line even field (This value affects the even lines) - NEWENUM7" "LOFSTOE_0,LOFSTOE_1,LOFSTOE_2,LOFSTOE_3,LOFSTOE_4,LOFSTOE_5,LOFSTOE_6,LOFSTOE_7" newline bitfld.long 0x38 3.--5. "LOFSTEO,Field line offset value applied after even line odd field (This value affects the first address of off lines) - NEWENUM7" "LOFSTEO_0,LOFSTEO_1,LOFSTEO_2,LOFSTEO_3,LOFSTEO_4,LOFSTEO_5,LOFSTEO_6,LOFSTEO_7" bitfld.long 0x38 0.--2. "LOFSTOO,Field line offset value applied after odd line odd field (This value affects the first address of even lines) - NEWENUM7" "LOFSTOO_0,LOFSTOO_1,LOFSTOO_2,LOFSTOO_3,LOFSTOO_4,LOFSTOO_5,LOFSTOO_6,LOFSTOO_7" line.long 0x3C "ISIF_CADU,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x3C 0.--10. 1. "CADU,Memory Address (Upper" line.long 0x40 "ISIF_CADL,SDRAM OUTPUT CTRL REGISTER" hexmask.long.word 0x40 0.--15. 1. "CADL,Memory Address (Lower" line.long 0x44 "ISIF_LINCFG0,INPUT LINEARIZATION CTRL REGISTER" bitfld.long 0x44 4.--6. "CORRSFT,Shift up value for the correction value (S10)" "CORRSFT_0,CORRSFT_1,CORRSFT_2,CORRSFT_3,CORRSFT_4,CORRSFT_5,CORRSFT_6,CORRSFT_7" bitfld.long 0x44 1. "LINMD,Linearization Mode: - NEWENUM1" "LINMD_0,LINMD_1" newline bitfld.long 0x44 0. "LINEN,Linearization Enable: - NEWENUM1" "LINEN_0,LINEN_1" line.long 0x48 "ISIF_LINCFG1,INPUT LINEARIZATION CTRL REGISTER" hexmask.long.word 0x48 0.--10. 1. "LUTSCL,Scale factor (U11Q10) for LUT input" line.long 0x4C "ISIF_CCOLP," bitfld.long 0x4C 14.--15. "CP0_F1,Specifies color pattern for pixel position 0 (Field 1) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP=?0? and to pixel count=0 in case of CFAP=?1?" "CP0_F1_0,CP0_F1_1,CP0_F1_2,CP0_F1_3" bitfld.long 0x4C 12.--13. "CP1_F1,Specifies color pattern for pixel position 1 (Field 1) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP=?0? and to pixel count=1 in case of CFAP=?1?" "CP1_F1_0,CP1_F1_1,CP1_F1_2,CP1_F1_3" newline bitfld.long 0x4C 10.--11. "CP2_F1,Specifies color pattern for pixel position 2 (Field 1) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP=?0? and to pixel count=2 in case of CFAP=?1?" "CP2_F1_0,CP2_F1_1,CP2_F1_2,CP2_F1_3" bitfld.long 0x4C 8.--9. "CP3_F1,Specifies color pattern for pixel position 3 (Field 1) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP=?0?" "CP3_F1_0,CP3_F1_1,CP3_F1_2,CP3_F1_3" newline bitfld.long 0x4C 6.--7. "CP0_F0,Specifies color pattern for pixel position 0 (Field 0) Pixel position 0 corresponds to pixel count=0 at even line in case of CFAP=?0? and to pixel count=0 in case of CFAP=?1?" "CP0_F0_0,CP0_F0_1,CP0_F0_2,CP0_F0_3" bitfld.long 0x4C 4.--5. "CP1_F0,Specifies color pattern for pixel position 1 (Field 0) Pixel position 1 corresponds to pixel count=1 at even line in case of CFAP=?0? and to pixel count=1 in case of CFAP=?1?" "CP1_F0_0,CP1_F0_1,CP1_F0_2,CP1_F0_3" newline bitfld.long 0x4C 2.--3. "CP2_F0,Specifies color pattern for pixel position 2 (Field 0) Pixel position 2 corresponds to pixel count=0 at odd line in case of CFAP=?0? and to pixel count=2 in case of CFAP=?1?" "CP2_F0_0,CP2_F0_1,CP2_F0_2,CP2_F0_3" bitfld.long 0x4C 0.--1. "CP3_F0,Specifies color pattern for pixel position 3 (Field 0) Pixel position 3 corresponds to pixel count=1 at odd line in case of CFAP=?0?" "CP3_F0_0,CP3_F0_1,CP3_F0_2,CP3_F0_3" line.long 0x50 "ISIF_CRGAIN," hexmask.long.word 0x50 0.--11. 1. "CGR,R/Ye gain: Performs gain adjustment on image sensor data" line.long 0x54 "ISIF_CGRGAIN," hexmask.long.word 0x54 0.--11. 1. "CGGR,Gr/Cy gain: Performs gain adjustment on image sensor data" line.long 0x58 "ISIF_CGBGAIN," hexmask.long.word 0x58 0.--11. 1. "CGGB,Gb/Cy gain: Performs gain adjustment on image sensor data" line.long 0x5C "ISIF_CBGAIN," hexmask.long.word 0x5C 0.--11. 1. "CGB,B/Mg gain: Performs gain adjustment on image sensor data" line.long 0x60 "ISIF_COFSTA," hexmask.long.word 0x60 0.--11. 1. "COFT,Image sensor offset: Performs offset value adjustment on image sensor data (0~4095)" line.long 0x64 "ISIF_FLSHCFG0," bitfld.long 0x64 0. "FLSHEN,Flash timing signal enable This bit is automatically cleared to '0' at VD timing" "FLSHEN_0,FLSHEN_1" line.long 0x68 "ISIF_FLSHCFG1," hexmask.long.word 0x68 0.--14. 1. "SFLSH,Start line to set the FLASH timing signal" line.long 0x6C "ISIF_FLSHCFG2," hexmask.long.word 0x6C 0.--15. 1. "VFLSH,Valid width of the FLASH timing signal" line.long 0x70 "ISIF_VDINT0," hexmask.long.word 0x70 0.--14. 1. "CVD0,VD0 Interrupt timing in a field (line number)" line.long 0x74 "ISIF_VDINT1," hexmask.long.word 0x74 0.--14. 1. "CVD1,VD1 Interrupt timing in a field (line number)" line.long 0x78 "ISIF_VDINT2," hexmask.long.word 0x78 0.--14. 1. "CVD2,VD2 Interrupt timing in a field (line number)" line.long 0x7C "ISIF_MISC," bitfld.long 0x7C 13. "DPCMPRE,Selects Predictor for DPCM Encoder (12-8) - NEWENUM1" "DPCMPRE_0,DPCMPRE_1" bitfld.long 0x7C 12. "DPCMEN,Enables DPCM Encoding (12-8) - NEWENUM1" "DPCMEN_0,DPCMEN_1" line.long 0x80 "ISIF_CGAMMAWD," bitfld.long 0x80 14. "WBEN2,White Balance Enable for H3A - NEWENUM1" "WBEN2_0,WBEN2_1" bitfld.long 0x80 13. "WBEN1,White Balance Enable for IPIPE - NEWENUM1" "WBEN1_0,WBEN1_1" newline bitfld.long 0x80 12. "WBEN0,White Balance Enable for memory capture - NEWENUM1" "WBEN0_0,WBEN0_1" bitfld.long 0x80 10. "OFSTEN2,Offset control Enable for H3A - NEWENUM1" "OFSTEN2_0,OFSTEN2_1" newline bitfld.long 0x80 9. "OFSTEN1,Offset control Enable for IPIPE - NEWENUM1" "OFSTEN1_0,OFSTEN1_1" bitfld.long 0x80 8. "OFSTEN0,Offset control Enable for SDRAM capture - NEWENUM1" "OFSTEN0_0,OFSTEN0_1" newline bitfld.long 0x80 5. "CFAP,Selects CFA pattern - NEWENUM1" "CFAP_0,CFAP_1" bitfld.long 0x80 1.--4. "GWDI,Selects MSB position of Input Data - NEWENUM14" "GWDI_0,GWDI_1,GWDI_2,GWDI_3,GWDI_4,GWDI_5,GWDI_6,GWDI_7,GWDI_8,GWDI_9,GWDI_10,GWDI_11,GWDI_12,GWDI_13,GWDI_14,GWDI_15" newline bitfld.long 0x80 0. "CCDTBL,On/Off control of A-law table for SDRAM capture - NEWENUM1" "CCDTBL_0,CCDTBL_1" line.long 0x84 "ISIF_REC656IF,INPUT CONFIG REGISTER" bitfld.long 0x84 1. "R656ON,CCIR Rec.656 interface mode - NEWENUM1" "R656ON_0,R656ON_1" bitfld.long 0x84 0. "ECCFVH,Error correction of FVH code - NEWENUM1" "ECCFVH_0,ECCFVH_1" line.long 0x88 "ISIF_CCDCFG," bitfld.long 0x88 15. "VLDC,On/off control of CPU registers re-synchronize function by VSYNC" "VLDC_0,VLDC_1" bitfld.long 0x88 13. "MSBINVI,MSB inverse of CIN port when the data are captured to SDRAM" "MSBINVI_0,MSBINVI_1" newline bitfld.long 0x88 12. "BSWD,On/off control of Byte SWAP function when SDRAM capturing" "BSWD_0,BSWD_1" bitfld.long 0x88 11. "Y8POS,Selects Y signal position when in 8bit input mode - NEWENUM1" "Y8POS_0,Y8POS_1" newline bitfld.long 0x88 10. "EXTRG,Setting ?1? to this register the SDRAM address is initialized at the rising edge of FID input signal or DWEN register" "EXTRG_0,EXTRG_1" bitfld.long 0x88 9. "TRGSEL,Select trigger source signal of SDRAM address initializing in case EXTRG=1" "TRGSEL_0,TRGSEL_1" newline bitfld.long 0x88 8. "WENLOG,Specifies the CCD valid area" "WENLOG_0,WENLOG_1" bitfld.long 0x88 6.--7. "FIDMD,Specifies FID detection mode - NEWENUM1" "FIDMD_0,FIDMD_1,FIDMD_2,FIDMD_3" newline bitfld.long 0x88 5. "BT656,Selects bit width of CCIR656" "BT656_0,BT656_1" bitfld.long 0x88 4. "YCINSWP,The ISIF module has a 16-bit interface" "YCINSWP_0,YCINSWP_1" newline bitfld.long 0x88 0.--1. "SDRPACK,This bit field selects how the data are stored to SDRAM" "SDRPACK_0,SDRPACK_1,SDRPACK_2,SDRPACK_3" line.long 0x8C "ISIF_DFCCTL,VERTICAL LINE DEFCT CTRL REGISTER" bitfld.long 0x8C 8.--10. "VDFLSFT,Vertical line Defect level shift value Defect Level (value to be subtracted from the data) is 8bit width but can be up-shifted up to 6bits by VDFLSFT" "VDFLSFT_0,VDFLSFT_1,VDFLSFT_2,VDFLSFT_3,VDFLSFT_4,VDFLSFT_5,VDFLSFT_6,VDFLSFT_7" bitfld.long 0x8C 7. "VDFCUDA,Vertical line Defect Correction upper pixels disable" "VDFCUDA_0,VDFCUDA_1" newline bitfld.long 0x8C 5.--6. "VDFCSL,Vertical line Defect Correction mode select" "VDFCSL_0,VDFCSL_1,VDFCSL_2,VDFCSL_3" bitfld.long 0x8C 4. "VDFCEN,Vertical line Defect Correction enable" "VDFCEN_0,VDFCEN_1" line.long 0x90 "ISIF_VDFSATLV,VERTICAL LINE DEFCT CTRL REGISTER" hexmask.long.word 0x90 0.--11. 1. "VDFSLV,Vertical line Defect Correction saturation level" line.long 0x94 "ISIF_DFCMEMCTL,VERTICAL LINE DEFCT CTRL REGISTER" bitfld.long 0x94 4. "DFCMCLR,Defect correction" "DFCMCLR_0,DFCMCLR_1" bitfld.long 0x94 2. "DFCMARST,Defect correction" "DFCMARST_0,DFCMARST_1" newline bitfld.long 0x94 1. "DFCMRD,Defect correction" "DFCMRD_0,DFCMRD_1" bitfld.long 0x94 0. "DFCMWR,Defect correction" "DFCMWR_0,DFCMWR_1" line.long 0x98 "ISIF_DFCMEM0,Defect correction memory" hexmask.long.word 0x98 0.--12. 1. "DFCMEM0,Defect correction memory 0 Sets V position of the defects" line.long 0x9C "ISIF_DFCMEM1,Defect correction memory" hexmask.long.word 0x9C 0.--12. 1. "DFCMEM1,Defect correction memory 1 Sets H position of the defects" line.long 0xA0 "ISIF_DFCMEM2,Defect correction memory" hexmask.long.byte 0xA0 0.--7. 1. "DFCMEM2,Defect correction Memory 2 Set SUB1: Defect level of the Vertical line defect position (V = Vdefect)" line.long 0xA4 "ISIF_DFCMEM3,Defect correction memory" hexmask.long.byte 0xA4 0.--7. 1. "DFCMEM3,Defect correction Memory 3 Set SUB2: Defect level of the pixels upper than the Vertical line defect (V Vdefect)" line.long 0xA8 "ISIF_DFCMEM4,Defect correction memory" hexmask.long.byte 0xA8 0.--7. 1. "DFCMEM4,Memory 4 Set SUB3: Defect level of the pixels lower than the Vertical line defect (V Vdefect)" line.long 0xAC "ISIF_CLAMPCFG,BLACK CLAMP CTRL REGISTER" bitfld.long 0xAC 4. "CLMD,Black clamp mode Clamp value can be calculated regardless of the color or can be calculated separately for each 4 colors" "CLMD_0,CLMD_1" bitfld.long 0xAC 1.--2. "CLHMD,Horizontal Clamp mode - NEWENUM1" "CLHMD_0,CLHMD_1,CLHMD_2,CLHMD_3" newline bitfld.long 0xAC 0. "CLEN,Black Clamp Enable Enables clamp value to be subtracted from Image data" "CLEN_0,CLEN_1" line.long 0xB0 "ISIF_CLDCOFST,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xB0 0.--12. 1. "CLDC,DC offset for black clamp This value is added to the incoming pixels regardless whether optical black clamp is enabled (ISIF_CLAMPCFG.CLEN)" line.long 0xB4 "ISIF_CLSV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xB4 0.--12. 1. "CLSV,Black Clamp Start position (V)" line.long 0xB8 "ISIF_CLHWIN0,BLACK CLAMP CTRL REGISTER" bitfld.long 0xB8 12.--13. "CLHWN,Horizontal Black clamp - Vertical dimension of a Window (2^N)" "CLHWN_0,CLHWN_1,CLHWN_2,CLHWN_3" bitfld.long 0xB8 8.--9. "CLHWM,Horizontal Black clamp - Horizontal dimension of a Window (2^M)" "CLHWM_0,CLHWM_1,CLHWM_2,CLHWM_3" newline bitfld.long 0xB8 6. "CLHLMT,Horizontal Black clamp - Pixel value limitation for the Horizontal clamp value calculation" "CLHLMT_0,CLHLMT_1" bitfld.long 0xB8 5. "CLHWBS,Horizontal Black clamp - Base Window select - NEWENUM1" "CLHWBS_0,CLHWBS_1" newline bitfld.long 0xB8 0.--4. "CLHWC,Horizontal Black clamp - Window count per color Window count = CLHWC+1 Range" "CLHWC_0,CLHWC_1,CLHWC_2,CLHWC_3,CLHWC_4,CLHWC_5,CLHWC_6,CLHWC_7,CLHWC_8,CLHWC_9,CLHWC_10,CLHWC_11,CLHWC_12,CLHWC_13,CLHWC_14,CLHWC_15,CLHWC_16,CLHWC_17,CLHWC_18,CLHWC_19,CLHWC_20,CLHWC_21,CLHWC_22,CLHWC_23,CLHWC_24,CLHWC_25,CLHWC_26,CLHWC_27,CLHWC_28,CLHWC_29,CLHWC_30,CLHWC_31" line.long 0xBC "ISIF_CLHWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xBC 0.--12. 1. "CLHSH,Horizontal black clamp" line.long 0xC0 "ISIF_CLHWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xC0 0.--12. 1. "CLHSV,Horizontal black clamp" line.long 0xC4 "ISIF_CLVRV,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xC4 0.--11. 1. "CLVRV,Vertical black clamp reset value" line.long 0xC8 "ISIF_CLVWIN0,BLACK CLAMP CTRL REGISTER" hexmask.long.byte 0xC8 8.--15. 1. "CLVCOEF,Vertical Black clamp - Line average coefficient (k)" bitfld.long 0xC8 4.--5. "CLVRVSL,Vertical Black clamp - reset value selection Select the reset value for the clamp value of the previous line - NEWENUM1" "CLVRVSL_0,CLVRVSL_1,CLVRVSL_2,CLVRVSL_3" newline bitfld.long 0xC8 0.--2. "CLVOBH,Vertical Black clamp - Optical Black H valid (2^L)" "CLVOBH_0,CLVOBH_1,CLVOBH_2,CLVOBH_3,CLVOBH_4,CLVOBH_5,CLVOBH_6,CLVOBH_7" line.long 0xCC "ISIF_CLVWIN1,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xCC 0.--12. 1. "CLVSH,Vertical black clamp" line.long 0xD0 "ISIF_CLVWIN2,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xD0 0.--12. 1. "CLVSV,Vertical black clamp" line.long 0xD4 "ISIF_CLVWIN3,BLACK CLAMP CTRL REGISTER" hexmask.long.word 0xD4 0.--12. 1. "CLVOBV,Vertical black clamp" line.long 0xD8 "ISIF_LSCHOFST,2D Lens Shading Correction Register" hexmask.long.word 0xD8 0.--13. 1. "HOFST,H direction Data offset for Lens Shading Correction" line.long 0xDC "ISIF_LSCVOFST,2D Lens Shading Correction Register" hexmask.long.word 0xDC 0.--13. 1. "VOFST,V direction Data offset for Lens Shading Correction" line.long 0xE0 "ISIF_LSCHVAL,2D Lens Shading Correction Register" hexmask.long.word 0xE0 0.--13. 1. "HVAL,Number of valid pixels in H direction" line.long 0xE4 "ISIF_LSCVVAL,2D Lens Shading Correction Register" hexmask.long.word 0xE4 0.--13. 1. "VVAL,Number of valid lines in V direction" line.long 0xE8 "ISIF_2DLSCCFG,2D Lens Shading Correction Register" bitfld.long 0xE8 12.--14. "GAIN_MODE_M,Define the horizontal dimension of a paxel" "GAIN_MODE_M_0,GAIN_MODE_M_1,GAIN_MODE_M_2,GAIN_MODE_M_3,GAIN_MODE_M_4,GAIN_MODE_M_5,GAIN_MODE_M_6,GAIN_MODE_M_7" bitfld.long 0xE8 8.--10. "GAIN_MODE_N,Define the vertical dimension of a paxel" "GAIN_MODE_N_0,GAIN_MODE_N_1,GAIN_MODE_N_2,GAIN_MODE_N_3,GAIN_MODE_N_4,GAIN_MODE_N_5,GAIN_MODE_N_6,GAIN_MODE_N_7" newline rbitfld.long 0xE8 7. "BUSY,Busy bit - NEWENUM1" "BUSY_0,BUSY_1" bitfld.long 0xE8 6. "GAIN_RANGE,Define the range of gain table values" "8-bit gain mode GAIN table represents unsigned..,16-bit gain mode" newline bitfld.long 0xE8 1.--4. "GAIN_FORMAT,Sets gain table format 16-bit mode - NEWENUM14" "GAIN_FORMAT_0,GAIN_FORMAT_1,GAIN_FORMAT_2,GAIN_FORMAT_3,GAIN_FORMAT_4,GAIN_FORMAT_5,GAIN_FORMAT_6,GAIN_FORMAT_7,GAIN_FORMAT_8,GAIN_FORMAT_9,GAIN_FORMAT_10,GAIN_FORMAT_11,GAIN_FORMAT_12,GAIN_FORMAT_13,GAIN_FORMAT_14,GAIN_FORMAT_15" bitfld.long 0xE8 0. "ENABLE,Enables/disables LSC - NEWENUM1" "ENABLE_0,ENABLE_1" line.long 0xEC "ISIF_2DLSCOFST,2D Lens Shading Correction Register" hexmask.long.byte 0xEC 8.--15. 1. "OFSTSF,Scaling factor for Offsets (U8Q7) Range: 0 to 1+127/128" bitfld.long 0xEC 4.--6. "OFSTSFT,Shift up value for Offsets (S8Q0) - NEWENUM7" "OFSTSFT_0,OFSTSFT_1,OFSTSFT_2,OFSTSFT_3,OFSTSFT_4,OFSTSFT_5,OFSTSFT_6,OFSTSFT_7" newline bitfld.long 0xEC 0. "OFSTEN,Enables/disables Offset control in LSC This bit is ignored (treated as zero) in 16-bit gain mode (ISIF_2DLSCCFG.GAIN_RANGE=1)" "OFSTEN_0,OFSTEN_1" line.long 0xF0 "ISIF_2DLSCINI,2D Lens Shading Correction Register" hexmask.long.byte 0xF0 8.--14. 1. "Y,Initial Y Y position in pixels of the first active pixel in reference to the first active paxel" hexmask.long.byte 0xF0 0.--6. 1. "X,Initial X X position in pixels of the first active pixel in reference to the first active paxel" line.long 0xF4 "ISIF_2DLSCGRBU,2D Lens Shading Correction Register" hexmask.long.word 0xF4 0.--15. 1. "BASE31_16,Gain Table address base (Upper 16-bits) This bit field sets the address of the gain table in memory" line.long 0xF8 "ISIF_2DLSCGRBL,2D Lens Shading Correction Register" hexmask.long.word 0xF8 0.--15. 1. "BASE15_0,Gain Table address base (Lower 16-bits) Table address in bytes" line.long 0xFC "ISIF_2DLSCGROF,2D Lens Shading Correction Register" hexmask.long.word 0xFC 0.--15. 1. "OFFSET,Gain Table offset Defines the length in bytes of one row of the table" line.long 0x100 "ISIF_2DLSCORBU,2D Lens Shading Correction Register" hexmask.long.word 0x100 0.--15. 1. "BASE,Offset Table address base (Upper 16-bits) Table address in bytes" line.long 0x104 "ISIF_2DLSCORBL,2D Lens Shading Correction Register" hexmask.long.word 0x104 0.--15. 1. "BASE,Offset Table address base (Lower 16-bits) Table address in bytes" line.long 0x108 "ISIF_2DLSCOROF,2D Lens Shading Correction Register" hexmask.long.word 0x108 0.--15. 1. "OFFSET,Offset Table offset Defines the length in bytes of one row of the table" line.long 0x10C "ISIF_2DLSCIRQEN," bitfld.long 0x10C 3. "SOF,Interrupt status for LSC SOF Indicates the start of the LSC valid region" "SOF_0,SOF_1" bitfld.long 0x10C 2. "PREFETCH_COMPLETED,Interrupt enable for Prefetch Complete Indicates current state of the prefetch buffer" "PREFETCH_COMPLETED_0,PREFETCH_COMPLETED_1" newline bitfld.long 0x10C 1. "PREFETCH_ERROR,Interrupt enable for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM" "PREFETCH_ERROR_0,PREFETCH_ERROR_1" bitfld.long 0x10C 0. "DONE,Interrupt enable for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "DONE_0,DONE_1" line.long 0x110 "ISIF_2DLSCIRQST,2D Lens Shading Correction Register" bitfld.long 0x110 3. "SOF,Interrupt status for LSC SOF Indicates the start of the LSC valid region" "SOF_0,SOF_1" bitfld.long 0x110 2. "PREFETCH_COMPLETED,Interrupt status for Prefetch Complete Indicates current state of the prefetch buffer" "PREFETCH_COMPLETED_0,PREFETCH_COMPLETED_1" newline bitfld.long 0x110 1. "PREFETCH_ERROR,Interrupt status for Prefetch Error The prefetch error indicates when the gain table was read to slowly from SDRAM" "PREFETCH_ERROR_0,PREFETCH_ERROR_1" bitfld.long 0x110 0. "DONE,Interrupt status for LSC Done The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "DONE_0,DONE_1" line.long 0x114 "ISIF_FMTCFG,Input Data Formatter Register" bitfld.long 0x114 8.--11. "FMTAINC,Address increment Address increment = (FMTAINC + 1) Range (1-16) *This bit is latched by VD" "FMTAINC_0,FMTAINC_1,FMTAINC_2,FMTAINC_3,FMTAINC_4,FMTAINC_5,FMTAINC_6,FMTAINC_7,FMTAINC_8,FMTAINC_9,FMTAINC_10,FMTAINC_11,FMTAINC_12,FMTAINC_13,FMTAINC_14,FMTAINC_15" bitfld.long 0x114 4.--5. "LNUM,Split/Combine number of lines *This bit is latched by VD" "LNUM_0,LNUM_1,LNUM_2,LNUM_3" newline bitfld.long 0x114 2. "LNALT,Line alternating *This bit is latched by VD" "LNALT_0,LNALT_1" bitfld.long 0x114 1. "FMTCBL,Combine Input lines *This bit is latched by VD" "FMTCBL_0,FMTCBL_1" newline bitfld.long 0x114 0. "FMTEN,CCD Formatter enable *This bit is latched by VD" "FMTEN_0,FMTEN_1" line.long 0x118 "ISIF_FMTPLEN,Input Data Formatter Register" bitfld.long 0x118 12.--14. "FMTPLEN3,Number of program entries for SET3 Number of entries = (FMTPLEN3 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD" "FMTPLEN3_0,FMTPLEN3_1,FMTPLEN3_2,FMTPLEN3_3,FMTPLEN3_4,FMTPLEN3_5,FMTPLEN3_6,FMTPLEN3_7" bitfld.long 0x118 8.--10. "FMTPLEN2,Number of program entries for SET2 Number of entries = (FMTPLEN2 + 1) Range: 1-8 Valid only if FMTCBL is set *This bit is latched by VD" "FMTPLEN2_0,FMTPLEN2_1,FMTPLEN2_2,FMTPLEN2_3,FMTPLEN2_4,FMTPLEN2_5,FMTPLEN2_6,FMTPLEN2_7" newline bitfld.long 0x118 4.--7. "FMTPLEN1,Number of program entries for SET1 Number of entries = (FMTPLEN1 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD" "FMTPLEN1_0,FMTPLEN1_1,FMTPLEN1_2,FMTPLEN1_3,FMTPLEN1_4,FMTPLEN1_5,FMTPLEN1_6,FMTPLEN1_7,FMTPLEN1_8,FMTPLEN1_9,FMTPLEN1_10,FMTPLEN1_11,FMTPLEN1_12,FMTPLEN1_13,FMTPLEN1_14,FMTPLEN1_15" bitfld.long 0x118 0.--3. "FMTPLEN0,Number of program entries for SET0 Number of entries = (PLEN0 + 1) Range: 1-16 (FMTCBL = 0) 1-8 (FMTCBL = 1) Setting a value greater than 7 to FMTPLEN1 is not allowed if FMTCBL is set *This bit is latched by VD" "FMTPLEN0_0,FMTPLEN0_1,FMTPLEN0_2,FMTPLEN0_3,FMTPLEN0_4,FMTPLEN0_5,FMTPLEN0_6,FMTPLEN0_7,FMTPLEN0_8,FMTPLEN0_9,FMTPLEN0_10,FMTPLEN0_11,FMTPLEN0_12,FMTPLEN0_13,FMTPLEN0_14,FMTPLEN0_15" line.long 0x11C "ISIF_FMTSPH,Input Data Formatter Register" hexmask.long.word 0x11C 0.--12. 1. "FMTSPH,The first pixel in a line fed into the formatter" line.long 0x120 "ISIF_FMTLNH,Input Data Formatter Register" hexmask.long.word 0x120 0.--12. 1. "FMTLNH,Number of pixels in a line fed to the formatterNumber of pixels = FMTLNH + 1" line.long 0x124 "ISIF_FMTLSV,Input Data Formatter Register" hexmask.long.word 0x124 0.--12. 1. "FMTSLV,Start line vertical" line.long 0x128 "ISIF_FMTLNV,Input Data Formatter Register" hexmask.long.word 0x128 0.--14. 1. "FMTLNV,Number of lines in vertical Number of lines = FMTLNV + 1" line.long 0x12C "ISIF_FMTRLEN,Input Data Formatter Register" hexmask.long.word 0x12C 0.--12. 1. "FMTRLEN,Number of pixels in an output line Maximum value = 4480" line.long 0x130 "ISIF_FMTHCNT,Input Data Formatter Register" hexmask.long.word 0x130 0.--12. 1. "FMTHCNT,HD interval for output lines Set all '0' to this register if combining multiple lines into a single line" line.long 0x134 "ISIF_FMTAPTR0,Input Data Formatter Register" bitfld.long 0x134 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x134 0.--12. 1. "INIT,Initial address value for address pointer 0 This address can not exceed FMTRLEN - 1" line.long 0x138 "ISIF_FMTAPTR1,Input Data Formatter Register" bitfld.long 0x138 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x138 0.--12. 1. "INIT,Initial address value for address pointer 1 This address can not exceed FMTRLEN - 1" line.long 0x13C "ISIF_FMTAPTR2,Input Data Formatter Register" bitfld.long 0x13C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x13C 0.--12. 1. "INIT,Initial address value for address pointer 2 This address can not exceed FMTRLEN - 1" line.long 0x140 "ISIF_FMTAPTR3,Input Data Formatter Register" bitfld.long 0x140 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x140 0.--12. 1. "INIT,Initial address value for address pointer 3 This address can not exceed FMTRLEN - 1" line.long 0x144 "ISIF_FMTAPTR4,Input Data Formatter Register" bitfld.long 0x144 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x144 0.--12. 1. "INIT,Initial address value for address pointer 4 This address can not exceed FMTRLEN - 1" line.long 0x148 "ISIF_FMTAPTR5,Input Data Formatter Register" bitfld.long 0x148 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x148 0.--12. 1. "INIT,Initial address value for address pointer 5 This address can not exceed FMTRLEN - 1" line.long 0x14C "ISIF_FMTAPTR6,Input Data Formatter Register" bitfld.long 0x14C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x14C 0.--12. 1. "INIT,Initial address value for address pointer 6 This address can not exceed FMTRLEN - 1" line.long 0x150 "ISIF_FMTAPTR7,Input Data Formatter Register" bitfld.long 0x150 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x150 0.--12. 1. "INIT,Initial address value for address pointer 7 This address can not exceed FMTRLEN - 1" line.long 0x154 "ISIF_FMTAPTR8,Input Data Formatter Register" bitfld.long 0x154 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x154 0.--12. 1. "INIT,Initial address value for address pointer 8 This address can not exceed FMTRLEN - 1" line.long 0x158 "ISIF_FMTAPTR9,Input Data Formatter Register" bitfld.long 0x158 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x158 0.--12. 1. "INIT,Initial address value for address pointer 9 This address can not exceed FMTRLEN - 1" line.long 0x15C "ISIF_FMTAPTR10,Input Data Formatter Register" bitfld.long 0x15C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x15C 0.--12. 1. "INIT,Initial address value for address pointer 10 This address can not exceed FMTRLEN - 1" line.long 0x160 "ISIF_FMTAPTR11,Input Data Formatter Register" bitfld.long 0x160 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x160 0.--12. 1. "INIT,Initial address value for address pointer 11 This address can not exceed FMTRLEN - 1" line.long 0x164 "ISIF_FMTAPTR12,Input Data Formatter Register" bitfld.long 0x164 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x164 0.--12. 1. "INIT,Initial address value for address pointer 12 This address can not exceed FMTRLEN - 1" line.long 0x168 "ISIF_FMTAPTR13,Input Data Formatter Register" bitfld.long 0x168 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x168 0.--12. 1. "INIT,Initial address value for address pointer 13 This address can not exceed FMTRLEN - 1" line.long 0x16C "ISIF_FMTAPTR14,Input Data Formatter Register" bitfld.long 0x16C 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x16C 0.--12. 1. "INIT,Initial address value for address pointer 14 This address can not exceed FMTRLEN - 1" line.long 0x170 "ISIF_FMTAPTR15,Input Data Formatter Register" bitfld.long 0x170 13.--14. "LINE,The output line the address belongs to Valid only if FMTCBL is cleared - NEWENUM1" "LINE_0,LINE_1,LINE_2,LINE_3" hexmask.long.word 0x170 0.--12. 1. "INIT,Initial address value for address pointer 15 This address can not exceed FMTRLEN - 1" line.long 0x174 "ISIF_FMTPGMVF0,Input Data Formatter Register" bitfld.long 0x174 15. "PGM15EN,Program 15 Valid Flag - NEWENUM1" "PGM15EN_0,PGM15EN_1" bitfld.long 0x174 14. "PGM14EN,Program 14 Valid Flag - NEWENUM1" "PGM14EN_0,PGM14EN_1" newline bitfld.long 0x174 13. "PGM13EN,Program 13 Valid Flag - NEWENUM1" "PGM13EN_0,PGM13EN_1" bitfld.long 0x174 12. "PGM12EN,Program 12 Valid Flag - NEWENUM1" "PGM12EN_0,PGM12EN_1" newline bitfld.long 0x174 11. "PGM11EN,Program 11 Valid Flag - NEWENUM1" "PGM11EN_0,PGM11EN_1" bitfld.long 0x174 10. "PGM10EN,Program 10 Valid Flag - NEWENUM1" "PGM10EN_0,PGM10EN_1" newline bitfld.long 0x174 9. "PGM09EN,Program 9 Valid Flag - NEWENUM1" "PGM09EN_0,PGM09EN_1" bitfld.long 0x174 8. "PGM08EN,Program 8 Valid Flag - NEWENUM1" "PGM08EN_0,PGM08EN_1" newline bitfld.long 0x174 7. "PGM07EN,Program 7 Valid Flag - NEWENUM1" "PGM07EN_0,PGM07EN_1" bitfld.long 0x174 6. "PGM06EN,Program 6 Valid Flag - NEWENUM1" "PGM06EN_0,PGM06EN_1" newline bitfld.long 0x174 5. "PGM05EN,Program 5 Valid Flag - NEWENUM1" "PGM05EN_0,PGM05EN_1" bitfld.long 0x174 4. "PGM04EN,Program 4 Valid Flag - NEWENUM1" "PGM04EN_0,PGM04EN_1" newline bitfld.long 0x174 3. "PGM03EN,Program 3 Valid Flag - NEWENUM1" "PGM03EN_0,PGM03EN_1" bitfld.long 0x174 2. "PGM02EN,Program 2 Valid Flag - NEWENUM1" "PGM02EN_0,PGM02EN_1" newline bitfld.long 0x174 1. "PGM01EN,Program 1 Valid Flag - NEWENUM1" "PGM01EN_0,PGM01EN_1" bitfld.long 0x174 0. "PGM00EN,Program 0 Valid Flag - NEWENUM1" "PGM00EN_0,PGM00EN_1" line.long 0x178 "ISIF_FMTPGMVF1,Input Data Formatter Register" bitfld.long 0x178 15. "PGM31EN,Program 31 Valid Flag - NEWENUM1" "PGM31EN_0,PGM31EN_1" bitfld.long 0x178 14. "PGM30EN,Program 30 Valid Flag - NEWENUM1" "PGM30EN_0,PGM30EN_1" newline bitfld.long 0x178 13. "PGM29EN,Program 29 Valid Flag - NEWENUM1" "PGM29EN_0,PGM29EN_1" bitfld.long 0x178 12. "PGM28EN,Program 28 Valid Flag - NEWENUM1" "PGM28EN_0,PGM28EN_1" newline bitfld.long 0x178 11. "PGM27EN,Program 27 Valid Flag - NEWENUM1" "PGM27EN_0,PGM27EN_1" bitfld.long 0x178 10. "PGM26EN,Program 26 Valid Flag - NEWENUM1" "PGM26EN_0,PGM26EN_1" newline bitfld.long 0x178 9. "PGM25EN,Program 25 Valid Flag - NEWENUM1" "PGM25EN_0,PGM25EN_1" bitfld.long 0x178 8. "PGM24EN,Program 24 Valid Flag - NEWENUM1" "PGM24EN_0,PGM24EN_1" newline bitfld.long 0x178 7. "PGM23EN,Program 23 Valid Flag - NEWENUM1" "PGM23EN_0,PGM23EN_1" bitfld.long 0x178 6. "PGM22EN,Program 22 Valid Flag - NEWENUM1" "PGM22EN_0,PGM22EN_1" newline bitfld.long 0x178 5. "PGM21EN,Program 21 Valid Flag - NEWENUM1" "PGM21EN_0,PGM21EN_1" bitfld.long 0x178 4. "PGM20EN,Program 20 Valid Flag - NEWENUM1" "PGM20EN_0,PGM20EN_1" newline bitfld.long 0x178 3. "PGM19EN,Program 19 Valid Flag - NEWENUM1" "PGM19EN_0,PGM19EN_1" bitfld.long 0x178 2. "PGM18EN,Program 18 Valid Flag - NEWENUM1" "PGM18EN_0,PGM18EN_1" newline bitfld.long 0x178 1. "PGM17EN,Program 17 Valid Flag - NEWENUM1" "PGM17EN_0,PGM17EN_1" bitfld.long 0x178 0. "PGM16EN,Program 16 Valid Flag - NEWENUM1" "PGM16EN_0,PGM16EN_1" line.long 0x17C "ISIF_FMTPGMAPU0,Input Data Formatter Register" bitfld.long 0x17C 15. "PGM15UPDT,Program 15 Address Pointer Update - NEWENUM1" "PGM15UPDT_0,PGM15UPDT_1" bitfld.long 0x17C 14. "PGM14UPDT,Program 14 Address Pointer Update - NEWENUM1" "PGM14UPDT_0,PGM14UPDT_1" newline bitfld.long 0x17C 13. "PGM13UPDT,Program 13 Address Pointer Update - NEWENUM1" "PGM13UPDT_0,PGM13UPDT_1" bitfld.long 0x17C 12. "PGM12UPDT,Program 12 Address Pointer Update - NEWENUM1" "PGM12UPDT_0,PGM12UPDT_1" newline bitfld.long 0x17C 11. "PGM11UPDT,Program 11 Address Pointer Update - NEWENUM1" "PGM11UPDT_0,PGM11UPDT_1" bitfld.long 0x17C 10. "PGM10UPDT,Program 10 Address Pointer Update - NEWENUM1" "PGM10UPDT_0,PGM10UPDT_1" newline bitfld.long 0x17C 9. "PGM9UPDT,Program 9 Address Pointer Update - NEWENUM1" "PGM9UPDT_0,PGM9UPDT_1" bitfld.long 0x17C 8. "PGM8UPDT,Program 8 Address Pointer Update - NEWENUM1" "PGM8UPDT_0,PGM8UPDT_1" newline bitfld.long 0x17C 7. "PGM7UPDT,Program 7 Address Pointer Update - NEWENUM1" "PGM7UPDT_0,PGM7UPDT_1" bitfld.long 0x17C 6. "PGM6UPDT,Program 6 Address Pointer Update - NEWENUM1" "PGM6UPDT_0,PGM6UPDT_1" newline bitfld.long 0x17C 5. "PGM5UPDT,Program 5 Address Pointer Update - NEWENUM1" "PGM5UPDT_0,PGM5UPDT_1" bitfld.long 0x17C 4. "PGM4UPDT,Program 4 Address Pointer Update - NEWENUM1" "PGM4UPDT_0,PGM4UPDT_1" newline bitfld.long 0x17C 3. "PGM3UPDT,Program 3 Address Pointer Update - NEWENUM1" "PGM3UPDT_0,PGM3UPDT_1" bitfld.long 0x17C 2. "PGM2UPDT,Program 2 Address Pointer Update - NEWENUM1" "PGM2UPDT_0,PGM2UPDT_1" newline bitfld.long 0x17C 1. "PGM1UPDT,Program 1 Address Pointer Update - NEWENUM1" "PGM1UPDT_0,PGM1UPDT_1" bitfld.long 0x17C 0. "PGM0UPDT,Program 0 Address Pointer Update - NEWENUM1" "PGM0UPDT_0,PGM0UPDT_1" line.long 0x180 "ISIF_FMTPGMAPU1,Input Data Formatter Register" bitfld.long 0x180 15. "PGM31UPDT,Program 31 Address Pointer Update - NEWENUM1" "PGM31UPDT_0,PGM31UPDT_1" bitfld.long 0x180 14. "PGM30UPDT,Program 30 Address Pointer Update - NEWENUM1" "PGM30UPDT_0,PGM30UPDT_1" newline bitfld.long 0x180 13. "PGM29UPDT,Program 29 Address Pointer Update - NEWENUM1" "PGM29UPDT_0,PGM29UPDT_1" bitfld.long 0x180 12. "PGM28UPDT,Program 28 Address Pointer Update - NEWENUM1" "PGM28UPDT_0,PGM28UPDT_1" newline bitfld.long 0x180 11. "PGM27UPDT,Program 27 Address Pointer Update - NEWENUM1" "PGM27UPDT_0,PGM27UPDT_1" bitfld.long 0x180 10. "PGM26UPDT,Program 26 Address Pointer Update - NEWENUM1" "PGM26UPDT_0,PGM26UPDT_1" newline bitfld.long 0x180 9. "PGM25UPDT,Program 25 Address Pointer Update - NEWENUM1" "PGM25UPDT_0,PGM25UPDT_1" bitfld.long 0x180 8. "PGM24UPDT,Program 24 Address Pointer Update - NEWENUM1" "PGM24UPDT_0,PGM24UPDT_1" newline bitfld.long 0x180 7. "PGM23UPDT,Program 23 Address Pointer Update - NEWENUM1" "PGM23UPDT_0,PGM23UPDT_1" bitfld.long 0x180 6. "PGM22UPDT,Program 22 Address Pointer Update - NEWENUM1" "PGM22UPDT_0,PGM22UPDT_1" newline bitfld.long 0x180 5. "PGM21UPDT,Program 21 Address Pointer Update - NEWENUM1" "PGM21UPDT_0,PGM21UPDT_1" bitfld.long 0x180 4. "PGM20UPDT,Program 20 Address Pointer Update - NEWENUM1" "PGM20UPDT_0,PGM20UPDT_1" newline bitfld.long 0x180 3. "PGM19UPDT,Program 19 Address Pointer Update - NEWENUM1" "PGM19UPDT_0,PGM19UPDT_1" bitfld.long 0x180 2. "PGM18UPDT,Program 18 Address Pointer Update - NEWENUM1" "PGM18UPDT_0,PGM18UPDT_1" newline bitfld.long 0x180 1. "PGM17UPDT,Program 17 Address Pointer Update - NEWENUM1" "PGM17UPDT_0,PGM17UPDT_1" bitfld.long 0x180 0. "PGM16UPDT,Program 16 Address Pointer Update - NEWENUM1" "PGM16UPDT_0,PGM16UPDT_1" line.long 0x184 "ISIF_FMTPGMAPS0,Input Data Formatter Register" bitfld.long 0x184 12.--15. "PGM3APTR,Program 3 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM3APTR_0,PGM3APTR_1,PGM3APTR_2,PGM3APTR_3,PGM3APTR_4,PGM3APTR_5,PGM3APTR_6,PGM3APTR_7,PGM3APTR_8,PGM3APTR_9,PGM3APTR_10,PGM3APTR_11,PGM3APTR_12,PGM3APTR_13,PGM3APTR_14,PGM3APTR_15" bitfld.long 0x184 8.--11. "PGM2APTR,Program 2 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM2APTR_0,PGM2APTR_1,PGM2APTR_2,PGM2APTR_3,PGM2APTR_4,PGM2APTR_5,PGM2APTR_6,PGM2APTR_7,PGM2APTR_8,PGM2APTR_9,PGM2APTR_10,PGM2APTR_11,PGM2APTR_12,PGM2APTR_13,PGM2APTR_14,PGM2APTR_15" newline bitfld.long 0x184 4.--7. "PGM1APTR,Program 1 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM1APTR_0,PGM1APTR_1,PGM1APTR_2,PGM1APTR_3,PGM1APTR_4,PGM1APTR_5,PGM1APTR_6,PGM1APTR_7,PGM1APTR_8,PGM1APTR_9,PGM1APTR_10,PGM1APTR_11,PGM1APTR_12,PGM1APTR_13,PGM1APTR_14,PGM1APTR_15" bitfld.long 0x184 0.--3. "PGM0APTR,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM0APTR_0,PGM0APTR_1,PGM0APTR_2,PGM0APTR_3,PGM0APTR_4,PGM0APTR_5,PGM0APTR_6,PGM0APTR_7,PGM0APTR_8,PGM0APTR_9,PGM0APTR_10,PGM0APTR_11,PGM0APTR_12,PGM0APTR_13,PGM0APTR_14,PGM0APTR_15" line.long 0x188 "ISIF_FMTPGMAPS1,Input Data Formatter Register" bitfld.long 0x188 12.--15. "PGM7APTR,Program 7 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM7APTR_0,PGM7APTR_1,PGM7APTR_2,PGM7APTR_3,PGM7APTR_4,PGM7APTR_5,PGM7APTR_6,PGM7APTR_7,PGM7APTR_8,PGM7APTR_9,PGM7APTR_10,PGM7APTR_11,PGM7APTR_12,PGM7APTR_13,PGM7APTR_14,PGM7APTR_15" bitfld.long 0x188 8.--11. "PGM6APTR,Program 6 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM6APTR_0,PGM6APTR_1,PGM6APTR_2,PGM6APTR_3,PGM6APTR_4,PGM6APTR_5,PGM6APTR_6,PGM6APTR_7,PGM6APTR_8,PGM6APTR_9,PGM6APTR_10,PGM6APTR_11,PGM6APTR_12,PGM6APTR_13,PGM6APTR_14,PGM6APTR_15" newline bitfld.long 0x188 4.--7. "PGM5APTR,Program 5 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM5APTR_0,PGM5APTR_1,PGM5APTR_2,PGM5APTR_3,PGM5APTR_4,PGM5APTR_5,PGM5APTR_6,PGM5APTR_7,PGM5APTR_8,PGM5APTR_9,PGM5APTR_10,PGM5APTR_11,PGM5APTR_12,PGM5APTR_13,PGM5APTR_14,PGM5APTR_15" bitfld.long 0x188 0.--3. "PGM4APTR,Program 0 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM4APTR_0,PGM4APTR_1,PGM4APTR_2,PGM4APTR_3,PGM4APTR_4,PGM4APTR_5,PGM4APTR_6,PGM4APTR_7,PGM4APTR_8,PGM4APTR_9,PGM4APTR_10,PGM4APTR_11,PGM4APTR_12,PGM4APTR_13,PGM4APTR_14,PGM4APTR_15" line.long 0x18C "ISIF_FMTPGMAPS2,Input Data Formatter Register" bitfld.long 0x18C 12.--15. "PGM11APTR,Program 11 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM11APTR_0,PGM11APTR_1,PGM11APTR_2,PGM11APTR_3,PGM11APTR_4,PGM11APTR_5,PGM11APTR_6,PGM11APTR_7,PGM11APTR_8,PGM11APTR_9,PGM11APTR_10,PGM11APTR_11,PGM11APTR_12,PGM11APTR_13,PGM11APTR_14,PGM11APTR_15" bitfld.long 0x18C 8.--11. "PGM10APTR,Program 10 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM10APTR_0,PGM10APTR_1,PGM10APTR_2,PGM10APTR_3,PGM10APTR_4,PGM10APTR_5,PGM10APTR_6,PGM10APTR_7,PGM10APTR_8,PGM10APTR_9,PGM10APTR_10,PGM10APTR_11,PGM10APTR_12,PGM10APTR_13,PGM10APTR_14,PGM10APTR_15" newline bitfld.long 0x18C 4.--7. "PGM9APTR,Program 9 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM9APTR_0,PGM9APTR_1,PGM9APTR_2,PGM9APTR_3,PGM9APTR_4,PGM9APTR_5,PGM9APTR_6,PGM9APTR_7,PGM9APTR_8,PGM9APTR_9,PGM9APTR_10,PGM9APTR_11,PGM9APTR_12,PGM9APTR_13,PGM9APTR_14,PGM9APTR_15" bitfld.long 0x18C 0.--3. "PGM8APTR,Program 8 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM8APTR_0,PGM8APTR_1,PGM8APTR_2,PGM8APTR_3,PGM8APTR_4,PGM8APTR_5,PGM8APTR_6,PGM8APTR_7,PGM8APTR_8,PGM8APTR_9,PGM8APTR_10,PGM8APTR_11,PGM8APTR_12,PGM8APTR_13,PGM8APTR_14,PGM8APTR_15" line.long 0x190 "ISIF_FMTPGMAPS3,Input Data Formatter Register" bitfld.long 0x190 12.--15. "PGM15APTR,Program 15 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM15APTR_0,PGM15APTR_1,PGM15APTR_2,PGM15APTR_3,PGM15APTR_4,PGM15APTR_5,PGM15APTR_6,PGM15APTR_7,PGM15APTR_8,PGM15APTR_9,PGM15APTR_10,PGM15APTR_11,PGM15APTR_12,PGM15APTR_13,PGM15APTR_14,PGM15APTR_15" bitfld.long 0x190 8.--11. "PGM14APTR,Program 14 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM14APTR_0,PGM14APTR_1,PGM14APTR_2,PGM14APTR_3,PGM14APTR_4,PGM14APTR_5,PGM14APTR_6,PGM14APTR_7,PGM14APTR_8,PGM14APTR_9,PGM14APTR_10,PGM14APTR_11,PGM14APTR_12,PGM14APTR_13,PGM14APTR_14,PGM14APTR_15" newline bitfld.long 0x190 4.--7. "PGM13APTR,Program 13 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM13APTR_0,PGM13APTR_1,PGM13APTR_2,PGM13APTR_3,PGM13APTR_4,PGM13APTR_5,PGM13APTR_6,PGM13APTR_7,PGM13APTR_8,PGM13APTR_9,PGM13APTR_10,PGM13APTR_11,PGM13APTR_12,PGM13APTR_13,PGM13APTR_14,PGM13APTR_15" bitfld.long 0x190 0.--3. "PGM12APTR,Program 12 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM12APTR_0,PGM12APTR_1,PGM12APTR_2,PGM12APTR_3,PGM12APTR_4,PGM12APTR_5,PGM12APTR_6,PGM12APTR_7,PGM12APTR_8,PGM12APTR_9,PGM12APTR_10,PGM12APTR_11,PGM12APTR_12,PGM12APTR_13,PGM12APTR_14,PGM12APTR_15" line.long 0x194 "ISIF_FMTPGMAPS4,Input Data Formatter Register" bitfld.long 0x194 12.--15. "PGM19APTR,Program 19 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM19APTR_0,PGM19APTR_1,PGM19APTR_2,PGM19APTR_3,PGM19APTR_4,PGM19APTR_5,PGM19APTR_6,PGM19APTR_7,PGM19APTR_8,PGM19APTR_9,PGM19APTR_10,PGM19APTR_11,PGM19APTR_12,PGM19APTR_13,PGM19APTR_14,PGM19APTR_15" bitfld.long 0x194 8.--11. "PGM18APTR,Program 18 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM18APTR_0,PGM18APTR_1,PGM18APTR_2,PGM18APTR_3,PGM18APTR_4,PGM18APTR_5,PGM18APTR_6,PGM18APTR_7,PGM18APTR_8,PGM18APTR_9,PGM18APTR_10,PGM18APTR_11,PGM18APTR_12,PGM18APTR_13,PGM18APTR_14,PGM18APTR_15" newline bitfld.long 0x194 4.--7. "PGM17APTR,Program 17 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM17APTR_0,PGM17APTR_1,PGM17APTR_2,PGM17APTR_3,PGM17APTR_4,PGM17APTR_5,PGM17APTR_6,PGM17APTR_7,PGM17APTR_8,PGM17APTR_9,PGM17APTR_10,PGM17APTR_11,PGM17APTR_12,PGM17APTR_13,PGM17APTR_14,PGM17APTR_15" bitfld.long 0x194 0.--3. "PGM16APTR,Program 16 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM16APTR_0,PGM16APTR_1,PGM16APTR_2,PGM16APTR_3,PGM16APTR_4,PGM16APTR_5,PGM16APTR_6,PGM16APTR_7,PGM16APTR_8,PGM16APTR_9,PGM16APTR_10,PGM16APTR_11,PGM16APTR_12,PGM16APTR_13,PGM16APTR_14,PGM16APTR_15" line.long 0x198 "ISIF_FMTPGMAPS5,Input Data Formatter Register" bitfld.long 0x198 12.--15. "PGM23APTR,Program 23 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM23APTR_0,PGM23APTR_1,PGM23APTR_2,PGM23APTR_3,PGM23APTR_4,PGM23APTR_5,PGM23APTR_6,PGM23APTR_7,PGM23APTR_8,PGM23APTR_9,PGM23APTR_10,PGM23APTR_11,PGM23APTR_12,PGM23APTR_13,PGM23APTR_14,PGM23APTR_15" bitfld.long 0x198 8.--11. "PGM22APTR,Program 22 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM22APTR_0,PGM22APTR_1,PGM22APTR_2,PGM22APTR_3,PGM22APTR_4,PGM22APTR_5,PGM22APTR_6,PGM22APTR_7,PGM22APTR_8,PGM22APTR_9,PGM22APTR_10,PGM22APTR_11,PGM22APTR_12,PGM22APTR_13,PGM22APTR_14,PGM22APTR_15" newline bitfld.long 0x198 4.--7. "PGM21APTR,Program 21 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM21APTR_0,PGM21APTR_1,PGM21APTR_2,PGM21APTR_3,PGM21APTR_4,PGM21APTR_5,PGM21APTR_6,PGM21APTR_7,PGM21APTR_8,PGM21APTR_9,PGM21APTR_10,PGM21APTR_11,PGM21APTR_12,PGM21APTR_13,PGM21APTR_14,PGM21APTR_15" bitfld.long 0x198 0.--3. "PGM20APTR,Program 20 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM20APTR_0,PGM20APTR_1,PGM20APTR_2,PGM20APTR_3,PGM20APTR_4,PGM20APTR_5,PGM20APTR_6,PGM20APTR_7,PGM20APTR_8,PGM20APTR_9,PGM20APTR_10,PGM20APTR_11,PGM20APTR_12,PGM20APTR_13,PGM20APTR_14,PGM20APTR_15" line.long 0x19C "ISIF_FMTPGMAPS6,Input Data Formatter Register" bitfld.long 0x19C 12.--15. "PGM27APTR,Program 27 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM27APTR_0,PGM27APTR_1,PGM27APTR_2,PGM27APTR_3,PGM27APTR_4,PGM27APTR_5,PGM27APTR_6,PGM27APTR_7,PGM27APTR_8,PGM27APTR_9,PGM27APTR_10,PGM27APTR_11,PGM27APTR_12,PGM27APTR_13,PGM27APTR_14,PGM27APTR_15" bitfld.long 0x19C 8.--11. "PGM26APTR,Program 26 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM26APTR_0,PGM26APTR_1,PGM26APTR_2,PGM26APTR_3,PGM26APTR_4,PGM26APTR_5,PGM26APTR_6,PGM26APTR_7,PGM26APTR_8,PGM26APTR_9,PGM26APTR_10,PGM26APTR_11,PGM26APTR_12,PGM26APTR_13,PGM26APTR_14,PGM26APTR_15" newline bitfld.long 0x19C 4.--7. "PGM25APTR,Program 25 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM25APTR_0,PGM25APTR_1,PGM25APTR_2,PGM25APTR_3,PGM25APTR_4,PGM25APTR_5,PGM25APTR_6,PGM25APTR_7,PGM25APTR_8,PGM25APTR_9,PGM25APTR_10,PGM25APTR_11,PGM25APTR_12,PGM25APTR_13,PGM25APTR_14,PGM25APTR_15" bitfld.long 0x19C 0.--3. "PGM24APTR,Program 24 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM24APTR_0,PGM24APTR_1,PGM24APTR_2,PGM24APTR_3,PGM24APTR_4,PGM24APTR_5,PGM24APTR_6,PGM24APTR_7,PGM24APTR_8,PGM24APTR_9,PGM24APTR_10,PGM24APTR_11,PGM24APTR_12,PGM24APTR_13,PGM24APTR_14,PGM24APTR_15" line.long 0x1A0 "ISIF_FMTPGMAPS7,Input Data Formatter Register" bitfld.long 0x1A0 12.--15. "PGM31APTR,Program 31 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM31APTR_0,PGM31APTR_1,PGM31APTR_2,PGM31APTR_3,PGM31APTR_4,PGM31APTR_5,PGM31APTR_6,PGM31APTR_7,PGM31APTR_8,PGM31APTR_9,PGM31APTR_10,PGM31APTR_11,PGM31APTR_12,PGM31APTR_13,PGM31APTR_14,PGM31APTR_15" bitfld.long 0x1A0 8.--11. "PGM30APTR,Program 30 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM30APTR_0,PGM30APTR_1,PGM30APTR_2,PGM30APTR_3,PGM30APTR_4,PGM30APTR_5,PGM30APTR_6,PGM30APTR_7,PGM30APTR_8,PGM30APTR_9,PGM30APTR_10,PGM30APTR_11,PGM30APTR_12,PGM30APTR_13,PGM30APTR_14,PGM30APTR_15" newline bitfld.long 0x1A0 4.--7. "PGM29APTR,Program 29 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM29APTR_0,PGM29APTR_1,PGM29APTR_2,PGM29APTR_3,PGM29APTR_4,PGM29APTR_5,PGM29APTR_6,PGM29APTR_7,PGM29APTR_8,PGM29APTR_9,PGM29APTR_10,PGM29APTR_11,PGM29APTR_12,PGM29APTR_13,PGM29APTR_14,PGM29APTR_15" bitfld.long 0x1A0 0.--3. "PGM28APTR,Program 28 Address Pointer Select n: APTRn n:0-15 (APTR0 - APR15)" "PGM28APTR_0,PGM28APTR_1,PGM28APTR_2,PGM28APTR_3,PGM28APTR_4,PGM28APTR_5,PGM28APTR_6,PGM28APTR_7,PGM28APTR_8,PGM28APTR_9,PGM28APTR_10,PGM28APTR_11,PGM28APTR_12,PGM28APTR_13,PGM28APTR_14,PGM28APTR_15" line.long 0x1A4 "ISIF_CSCCTL,Color Space Converter Register" bitfld.long 0x1A4 0. "CSCEN,Controls ON/OFF of Color Space converter" "CSCEN_0,CSCEN_1" line.long 0x1A8 "ISIF_CSCM0,Color Space Converter Register" hexmask.long.byte 0x1A8 8.--15. 1. "CSCM01,Color Space convert coefficient value M01: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1A8 0.--7. 1. "CSCM00,Color Space convert coefficient value M00: This value is signed 8-bit with the 5-bits decimal" line.long 0x1AC "ISIF_CSCM1,Color Space Converter Register" hexmask.long.byte 0x1AC 8.--15. 1. "CSCM03,Color Space convert coefficient value M03: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1AC 0.--7. 1. "CSCM02,Color Space convert coefficient value M02: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B0 "ISIF_CSCM2,Color Space Converter Register" hexmask.long.byte 0x1B0 8.--15. 1. "CSCM11,Color Space convert coefficient value M11: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1B0 0.--7. 1. "CSCM10,Color Space convert coefficient value M10: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B4 "ISIF_CSCM3,Color Space Converter Register" hexmask.long.byte 0x1B4 8.--15. 1. "CSCM13,Color Space convert coefficient value M13: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1B4 0.--7. 1. "CSCM12,Color Space convert coefficient value M12: This value is signed 8-bit with the 5-bits decimal" line.long 0x1B8 "ISIF_CSCM4,Color Space Converter Register" hexmask.long.byte 0x1B8 8.--15. 1. "CSCM21,Color Space convert coefficient value M21: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1B8 0.--7. 1. "CSCM20,Color Space convert coefficient value M20: This value is signed 8-bit with the 5-bits decimal" line.long 0x1BC "ISIF_CSCM5,Color Space Converter Register" hexmask.long.byte 0x1BC 8.--15. 1. "CSCM23,Color Space convert coefficient value M23: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1BC 0.--7. 1. "CSCM22,Color Space convert coefficient value M22: This value is signed 8-bit with the 5-bits decimal" line.long 0x1C0 "ISIF_CSCM6,Color Space Converter Register" hexmask.long.byte 0x1C0 8.--15. 1. "CSCM31,Color Space convert coefficient value M31: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1C0 0.--7. 1. "CSCM30,Color Space convert coefficient value M30: This value is signed 8-bit with the 5-bits decimal" line.long 0x1C4 "ISIF_CSCM7,Color Space Converter Register" hexmask.long.byte 0x1C4 8.--15. 1. "CSCM33,Color Space convert coefficient value M33: This value is signed 8-bit with the 5-bits decimal" hexmask.long.byte 0x1C4 0.--7. 1. "CSCM32,Color Space convert coefficient value M32: This value is signed 8-bit with the 5-bits decimal" group.long 0x1F8++0x07 line.long 0x00 "ISIF_CLKCTL," bitfld.long 0x00 1. "CLKEN1,Forces isif_clken1 to be active" "CLKEN1_0,CLKEN1_1" bitfld.long 0x00 0. "CLKEN2,Forces isif_clken2 to be active" "CLKEN2_0,CLKEN2_1" line.long 0x04 "ISIF_CBN,Circular bufferr parameters" hexmask.long.word 0x04 16.--30. 1. "CYN,Cicular Buffer Interrupt timing (line number)" hexmask.long.word 0x04 0.--14. 1. "CBN,Circular buffer size" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) hgroup.long ($2+0x1D8)++0x03 hide.long 0x00 "ISIF_OBVAL$1,Reserved" repeat.end repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) hgroup.long ($2+0x1C8)++0x03 hide.long 0x00 "ISIF_OBWIN$1,Reserved" repeat.end width 0x0B tree.end tree "ISP6P5_CNF1" base ad:0x52050C10 group.long 0x00++0x03 line.long 0x00 "NSF3V_SYSCONFIG,OCP interface" bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Reset (software or other) ongoing" group.long 0x08++0xE7 line.long 0x00 "NSF3V_CTRL,Control" bitfld.long 0x00 0. "EN,Enable NSF3V operation for either single frame or video depending onNSF3V_CFG.ONESHOT" "0,1" line.long 0x04 "NSF3V_CFG,Configuration" bitfld.long 0x04 17. "FORCE_CLKON,Force clock to be on disabling clock autogating" "0,1" bitfld.long 0x04 16. "SUPPRS_ALL,Suppress all subband signals (debug mode)" "0,1" bitfld.long 0x04 15. "BYPASS_W_DELAY,Bypass all processing so that output = input but maintain the same latency" "0,1" bitfld.long 0x04 14. "BBORDER_REP,Replicate top border to not lose 7 lines per color on the bottom" "0,1" newline bitfld.long 0x04 13. "TBORDER_REP,Replicate top border to not lose 7 lines per color on the top" "0,1" bitfld.long 0x04 12. "RBORDER_REP,Replicate right border to not lose 8 data points per color on the right" "0,1" bitfld.long 0x04 11. "LBORDER_REP,Replicate left border to not lose 8 data points per color on the left" "0,1" bitfld.long 0x04 10. "DESAT_EN,enable chroma desaturation" "0,1" newline bitfld.long 0x04 9. "SHD_EN,enable shading gain" "0,1" bitfld.long 0x04 8. "EE_EN,enable edge enhancement" "0,1" bitfld.long 0x04 7. "ONESHOT,Video (continuous operation) or one shot (single-frame)" "video,one-shot" bitfld.long 0x04 6. "HARD_THR_EN_422UV,Hard thresholding enable applicable to YUV422 (normal and interleaved) UV path" "0,1" newline bitfld.long 0x04 0.--3. "MODE,Mode of operation" "Bayer,Bayer interleaved 2x2,Bayer interleaved 3x3,YUV422,YUV420 Y plane,YuV420 UV plane,YUV422 interleaved,YUV420 Y interleaved,YUV420 UV interleaved 9 ~,?,?,?,?,?,?,reserved" line.long 0x08 "NSF3V_DIM,Image block dimension" hexmask.long.word 0x08 16.--29. 1. "IH,Image height in lines" hexmask.long.word 0x08 0.--13. 1. "IW,Image width in pixels" line.long 0x0C "NSF3V_VPOUT_CTRL,Video port output control" hexmask.long.word 0x0C 0.--15. 1. "PCLK,Video port output data rate indicate that VPOUT EN signal should be sent functional clock * PCLK / 65536" line.long 0x10 "NSF3V_SHD_ST,Shading gain starting coordinate" hexmask.long.word 0x10 16.--29. 1. "Y,shading gain starting Y coordinate" hexmask.long.word 0x10 0.--13. 1. "X,shading gain starting X coordinate" line.long 0x14 "NSF3V_SHD_HA,Shading gain HA1/HA2" hexmask.long.word 0x14 16.--28. 1. "HA2,shading gain HA2 coefficient" hexmask.long.word 0x14 0.--12. 1. "HA1,shading gain HA1 coefficient" line.long 0x18 "NSF3V_SHD_VA,Shading gain VA1/VA2" hexmask.long.word 0x18 16.--28. 1. "VA2,shading gain VA2 coefficient" hexmask.long.word 0x18 0.--12. 1. "VA1,shading gain VA1 coefficient" line.long 0x1C "NSF3V_SHD_HSVS,Shading gain shift counts" bitfld.long 0x1C 28.--29. "VCS,Vshading gain VCS shift count only 1 or 2 allowed" "0,1,2,3" bitfld.long 0x1C 24.--27. "VS2,shading gain VS2 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 20.--23. "VS1,shading gain VS1 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--13. "HCS,shading gain HCS shift count only 1 or 2 allowed" "0,1,2,3" newline bitfld.long 0x1C 8.--11. "HS2,shading gain HS2 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. "HS1,shading gain HS1 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. "S0,shading gain S0 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "NSF3V_SHD_ADJ,Shading gain adjustment" hexmask.long.word 0x20 16.--28. 1. "OADJ,shading gain offset adjustment" hexmask.long.byte 0x20 0.--7. 1. "GADJ,shading gain gain adjustment unsigned" line.long 0x24 "NSF3V_SHD_MAXG,Max shading gain" hexmask.long.word 0x24 0.--8. 1. "MAXG,Max shading gain" line.long 0x28 "NSF3V_TN_C00,Color 0 noise threshold" hexmask.long.word 0x28 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x28 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x2C "NSF3V_TN_C01,Color 0 noise threshold" hexmask.long.word 0x2C 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x2C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x30 "NSF3V_TN_C02,Color 0 noise threshold" hexmask.long.word 0x30 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x30 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x34 "NSF3V_TN_C03,Color 0 noise threshold" hexmask.long.word 0x34 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x34 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x38 "NSF3V_TN_C04,Color 0 noise threshold" hexmask.long.word 0x38 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x38 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x3C "NSF3V_TN_C05,Color 0 noise threshold" hexmask.long.word 0x3C 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x3C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x40 "NSF3V_TN_C10,Color 1 noise threshold" hexmask.long.word 0x40 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x40 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x44 "NSF3V_TN_C11,Color 1 noise threshold" hexmask.long.word 0x44 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x44 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x48 "NSF3V_TN_C12,Color 1 noise threshold" hexmask.long.word 0x48 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x48 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x4C "NSF3V_TN_C13,Color 1 noise threshold" hexmask.long.word 0x4C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x4C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x50 "NSF3V_TN_C14,Color 1 noise threshold" hexmask.long.word 0x50 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x50 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x54 "NSF3V_TN_C15,Color 1 noise threshold" hexmask.long.word 0x54 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x54 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x58 "NSF3V_TN_C20,Color 2 noise threshold" hexmask.long.word 0x58 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x58 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x5C "NSF3V_TN_C21,Color 2 noise threshold" hexmask.long.word 0x5C 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x5C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x60 "NSF3V_TN_C22,Color 2 noise threshold" hexmask.long.word 0x60 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x60 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x64 "NSF3V_TN_C23,Color 2 noise threshold" hexmask.long.word 0x64 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x64 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x68 "NSF3V_TN_C24,Color 2 noise threshold" hexmask.long.word 0x68 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x68 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x6C "NSF3V_TN_C25,Color 2 noise threshold" hexmask.long.word 0x6C 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x6C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x70 "NSF3V_TN_C30,Color 3 noise threshold" hexmask.long.word 0x70 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x70 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x74 "NSF3V_TN_C31,Color 3 noise threshold" hexmask.long.word 0x74 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x74 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x78 "NSF3V_TN_C32,Color 3 noise threshold" hexmask.long.word 0x78 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x78 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x7C "NSF3V_TN_C33,Color 3 noise threshold" hexmask.long.word 0x7C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x7C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x80 "NSF3V_TN_C34,Color 3 noise threshold" hexmask.long.word 0x80 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x80 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x84 "NSF3V_TN_C35,Color 3 noise threshold" hexmask.long.word 0x84 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x84 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x88 "NSF3V_TN_SCALE," hexmask.long.byte 0x88 16.--23. 1. "TN3_TO_TN2,Scaling factor to get TN3 noise threshold for level 3 subbands U3.5" hexmask.long.byte 0x88 0.--7. 1. "TN1_TO_TN2,Scaling factor to get TN1 noise threshold for level 1 subbands U3.5" line.long 0x8C "NSF3V_THR_KNEE,Thresholding knee points" hexmask.long.byte 0x8C 16.--23. 1. "U3,Knee point u3 above which ee = ee_max" hexmask.long.byte 0x8C 8.--15. 1. "U2,Knee point u2 below which ee = 0" hexmask.long.byte 0x8C 0.--7. 1. "U1,Knee point u1 below which suppression = suppression_max" line.long 0x90 "NSF3V_SUP_C00,Color 0 suppression max" hexmask.long.byte 0x90 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x90 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x90 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0x90 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x94 "NSF3V_SUP_C01,Color 0 suppression max" hexmask.long.byte 0x94 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x94 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0x98 "NSF3V_SUP_C10,Color 1 suppression max" hexmask.long.byte 0x98 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x98 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x98 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0x98 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x9C "NSF3V_SUP_C11,Color 1 suppression max" hexmask.long.byte 0x9C 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x9C 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA0 "NSF3V_SUP_C20,Color 2 suppression max" hexmask.long.byte 0xA0 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA0 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xA4 "NSF3V_SUP_C21,Color 2 suppression max" hexmask.long.byte 0xA4 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xA4 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA8 "NSF3V_SUP_C30,Color 3 suppression max" hexmask.long.byte 0xA8 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA8 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xAC "NSF3V_SUP_C31,Color 3 suppression max" hexmask.long.byte 0xAC 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xAC 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xB0 "NSF3V_EE_C00,Color 0 edge enhancement max" hexmask.long.word 0xB0 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xB0 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xB4 "NSF3V_EE_C01,Color 0 edge enhancement max" hexmask.long.word 0xB4 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xB4 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xB8 "NSF3V_EE_C02,Color 0 edge enhancement max" hexmask.long.word 0xB8 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xB8 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xBC "NSF3V_EE_C10,Color 1 edge enhancement max" hexmask.long.word 0xBC 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xBC 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xC0 "NSF3V_EE_C11,Color 1 edge enhancement max" hexmask.long.word 0xC0 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xC0 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xC4 "NSF3V_EE_C12,Color 1 edge enhancement max" hexmask.long.word 0xC4 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xC4 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xC8 "NSF3V_EE_C20,Color 2 edge enhancement max" hexmask.long.word 0xC8 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xC8 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xCC "NSF3V_EE_C21,Color 2 edge enhancement max" hexmask.long.word 0xCC 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xCC 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xD0 "NSF3V_EE_C22,Color 2 edge enhancement max" hexmask.long.word 0xD0 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xD0 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xD4 "NSF3V_EE_C30,Color 3 edge enhancement max" hexmask.long.word 0xD4 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xD4 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xD8 "NSF3V_EE_C31,Color 3 edge enhancement max" hexmask.long.word 0xD8 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xD8 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xDC "NSF3V_EE_C32,Color 3 edge enhancement max" hexmask.long.word 0xDC 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xDC 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xE0 "NSF3V_DS_THR,Desaturation thresholds" bitfld.long 0xE0 16.--21. "THR2,desaturation threshold 2 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 0.--5. "THR1,desaturation threhsold 1 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "NSF3V_DS_SLOPE,Desaturation slopes" hexmask.long.word 0xE4 16.--25. 1. "SLOPE2,desaturation slope 2 U0.10" hexmask.long.word 0xE4 0.--9. 1. "SLOPE1,desaturation slope 1 U0.10" width 0x0B tree.end tree "ISP6P5_NSF3V" base ad:0x52050810 group.long 0x00++0x03 line.long 0x00 "NSF3V_SYSCONFIG,OCP interface" bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Reset (software or other) ongoing" group.long 0x08++0xE7 line.long 0x00 "NSF3V_CTRL,Control" bitfld.long 0x00 0. "EN,Enable NSF3V operation for either single frame or video depending onNSF3V_CFG.ONESHOT" "0,1" line.long 0x04 "NSF3V_CFG,Configuration" bitfld.long 0x04 17. "FORCE_CLKON,Force clock to be on disabling clock autogating" "0,1" bitfld.long 0x04 16. "SUPPRS_ALL,Suppress all subband signals (debug mode)" "0,1" bitfld.long 0x04 15. "BYPASS_W_DELAY,Bypass all processing so that output = input but maintain the same latency" "0,1" bitfld.long 0x04 14. "BBORDER_REP,Replicate top border to not lose 7 lines per color on the bottom" "0,1" newline bitfld.long 0x04 13. "TBORDER_REP,Replicate top border to not lose 7 lines per color on the top" "0,1" bitfld.long 0x04 12. "RBORDER_REP,Replicate right border to not lose 8 data points per color on the right" "0,1" bitfld.long 0x04 11. "LBORDER_REP,Replicate left border to not lose 8 data points per color on the left" "0,1" bitfld.long 0x04 10. "DESAT_EN,enable chroma desaturation" "0,1" newline bitfld.long 0x04 9. "SHD_EN,enable shading gain" "0,1" bitfld.long 0x04 8. "EE_EN,enable edge enhancement" "0,1" bitfld.long 0x04 7. "ONESHOT,Video (continuous operation) or one shot (single-frame)" "video,one-shot" bitfld.long 0x04 6. "HARD_THR_EN_422UV,Hard thresholding enable applicable to YUV422 (normal and interleaved) UV path" "0,1" newline bitfld.long 0x04 0.--3. "MODE,Mode of operation" "Bayer,Bayer interleaved 2x2,Bayer interleaved 3x3,YUV422,YUV420 Y plane,YuV420 UV plane,YUV422 interleaved,YUV420 Y interleaved,YUV420 UV interleaved 9 ~,?,?,?,?,?,?,reserved" line.long 0x08 "NSF3V_DIM,Image block dimension" hexmask.long.word 0x08 16.--29. 1. "IH,Image height in lines" hexmask.long.word 0x08 0.--13. 1. "IW,Image width in pixels" line.long 0x0C "NSF3V_VPOUT_CTRL,Video port output control" hexmask.long.word 0x0C 0.--15. 1. "PCLK,Video port output data rate indicate that VPOUT EN signal should be sent functional clock * PCLK / 65536" line.long 0x10 "NSF3V_SHD_ST,Shading gain starting coordinate" hexmask.long.word 0x10 16.--29. 1. "Y,shading gain starting Y coordinate" hexmask.long.word 0x10 0.--13. 1. "X,shading gain starting X coordinate" line.long 0x14 "NSF3V_SHD_HA,Shading gain HA1/HA2" hexmask.long.word 0x14 16.--28. 1. "HA2,shading gain HA2 coefficient" hexmask.long.word 0x14 0.--12. 1. "HA1,shading gain HA1 coefficient" line.long 0x18 "NSF3V_SHD_VA,Shading gain VA1/VA2" hexmask.long.word 0x18 16.--28. 1. "VA2,shading gain VA2 coefficient" hexmask.long.word 0x18 0.--12. 1. "VA1,shading gain VA1 coefficient" line.long 0x1C "NSF3V_SHD_HSVS,Shading gain shift counts" bitfld.long 0x1C 28.--29. "VCS,Vshading gain VCS shift count only 1 or 2 allowed" "0,1,2,3" bitfld.long 0x1C 24.--27. "VS2,shading gain VS2 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 20.--23. "VS1,shading gain VS1 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--13. "HCS,shading gain HCS shift count only 1 or 2 allowed" "0,1,2,3" newline bitfld.long 0x1C 8.--11. "HS2,shading gain HS2 bit count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. "HS1,shading gain HS1 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--3. "S0,shading gain S0 shift count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x20 "NSF3V_SHD_ADJ,Shading gain adjustment" hexmask.long.word 0x20 16.--28. 1. "OADJ,shading gain offset adjustment" hexmask.long.byte 0x20 0.--7. 1. "GADJ,shading gain gain adjustment unsigned" line.long 0x24 "NSF3V_SHD_MAXG,Max shading gain" hexmask.long.word 0x24 0.--8. 1. "MAXG,Max shading gain" line.long 0x28 "NSF3V_TN_C00,Color 0 noise threshold" hexmask.long.word 0x28 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x28 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x2C "NSF3V_TN_C01,Color 0 noise threshold" hexmask.long.word 0x2C 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x2C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x30 "NSF3V_TN_C02,Color 0 noise threshold" hexmask.long.word 0x30 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x30 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x34 "NSF3V_TN_C03,Color 0 noise threshold" hexmask.long.word 0x34 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x34 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x38 "NSF3V_TN_C04,Color 0 noise threshold" hexmask.long.word 0x38 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x38 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x3C "NSF3V_TN_C05,Color 0 noise threshold" hexmask.long.word 0x3C 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x3C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x40 "NSF3V_TN_C10,Color 1 noise threshold" hexmask.long.word 0x40 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x40 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x44 "NSF3V_TN_C11,Color 1 noise threshold" hexmask.long.word 0x44 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x44 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x48 "NSF3V_TN_C12,Color 1 noise threshold" hexmask.long.word 0x48 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x48 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x4C "NSF3V_TN_C13,Color 1 noise threshold" hexmask.long.word 0x4C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x4C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x50 "NSF3V_TN_C14,Color 1 noise threshold" hexmask.long.word 0x50 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x50 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x54 "NSF3V_TN_C15,Color 1 noise threshold" hexmask.long.word 0x54 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x54 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x58 "NSF3V_TN_C20,Color 2 noise threshold" hexmask.long.word 0x58 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x58 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x5C "NSF3V_TN_C21,Color 2 noise threshold" hexmask.long.word 0x5C 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x5C 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x60 "NSF3V_TN_C22,Color 2 noise threshold" hexmask.long.word 0x60 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x60 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x64 "NSF3V_TN_C23,Color 2 noise threshold" hexmask.long.word 0x64 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x64 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x68 "NSF3V_TN_C24,Color 2 noise threshold" hexmask.long.word 0x68 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x68 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x6C "NSF3V_TN_C25,Color 2 noise threshold" hexmask.long.word 0x6C 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x6C 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x70 "NSF3V_TN_C30,Color 3 noise threshold" hexmask.long.word 0x70 16.--26. 1. "S0_Y,segment 0 Y coordinate U11" hexmask.long.word 0x70 0.--11. 1. "S0_X,segment 0 X coordinate U12 fixed to 0 (read-only)" line.long 0x74 "NSF3V_TN_C31,Color 3 noise threshold" hexmask.long.word 0x74 16.--27. 1. "S1_X,segment 1 X coordinate U12" hexmask.long.word 0x74 0.--13. 1. "S0_S,segment 0 slope S3.11" line.long 0x78 "NSF3V_TN_C32,Color 3 noise threshold" hexmask.long.word 0x78 16.--29. 1. "S1_S,segment 1 slope S3.11" hexmask.long.word 0x78 0.--10. 1. "S1_Y,segment 1 Y coordinate U11" line.long 0x7C "NSF3V_TN_C33,Color 3 noise threshold" hexmask.long.word 0x7C 16.--26. 1. "S2_Y,segment 2 Y coordinate U11" hexmask.long.word 0x7C 0.--11. 1. "S2_X,segment 2 X coordinate U12" line.long 0x80 "NSF3V_TN_C34,Color 3 noise threshold" hexmask.long.word 0x80 16.--27. 1. "S3_X,segment 3 X coordinate U12" hexmask.long.word 0x80 0.--13. 1. "S2_S,segment 2 slope S3.11" line.long 0x84 "NSF3V_TN_C35,Color 3 noise threshold" hexmask.long.word 0x84 16.--29. 1. "S3_S,segment 3 slope S3.11" hexmask.long.word 0x84 0.--10. 1. "S3_Y,segment 3 Y coordinate U11" line.long 0x88 "NSF3V_TN_SCALE," hexmask.long.byte 0x88 16.--23. 1. "TN3_TO_TN2,Scaling factor to get TN3 noise threshold for level 3 subbands U3.5" hexmask.long.byte 0x88 0.--7. 1. "TN1_TO_TN2,Scaling factor to get TN1 noise threshold for level 1 subbands U3.5" line.long 0x8C "NSF3V_THR_KNEE,Thresholding knee points" hexmask.long.byte 0x8C 16.--23. 1. "U3,Knee point u3 above which ee = ee_max" hexmask.long.byte 0x8C 8.--15. 1. "U2,Knee point u2 below which ee = 0" hexmask.long.byte 0x8C 0.--7. 1. "U1,Knee point u1 below which suppression = suppression_max" line.long 0x90 "NSF3V_SUP_C00,Color 0 suppression max" hexmask.long.byte 0x90 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x90 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x90 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0x90 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x94 "NSF3V_SUP_C01,Color 0 suppression max" hexmask.long.byte 0x94 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x94 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0x98 "NSF3V_SUP_C10,Color 1 suppression max" hexmask.long.byte 0x98 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0x98 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0x98 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0x98 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0x9C "NSF3V_SUP_C11,Color 1 suppression max" hexmask.long.byte 0x9C 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0x9C 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA0 "NSF3V_SUP_C20,Color 2 suppression max" hexmask.long.byte 0xA0 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA0 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0xA0 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xA4 "NSF3V_SUP_C21,Color 2 suppression max" hexmask.long.byte 0xA4 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xA4 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xA8 "NSF3V_SUP_C30,Color 3 suppression max" hexmask.long.byte 0xA8 24.--31. 1. "L2_HH,Level 2 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 16.--23. 1. "L2_LH,Level 2 LH and HL subband suppression_max U1.7" hexmask.long.byte 0xA8 8.--15. 1. "L1_HH,Level 1 HH subband suppression_max U1.7" hexmask.long.byte 0xA8 0.--7. 1. "L1_LH,Level 1 LH and HL subband suppression_max U1.7" line.long 0xAC "NSF3V_SUP_C31,Color 3 suppression max" hexmask.long.byte 0xAC 8.--15. 1. "L3_HH,Level 3 HH subband suppression_max U1.7" hexmask.long.byte 0xAC 0.--7. 1. "L3_LH,Level 3 LH and HL subband suppression_max U1.7" line.long 0xB0 "NSF3V_EE_C00,Color 0 edge enhancement max" hexmask.long.word 0xB0 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xB0 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xB4 "NSF3V_EE_C01,Color 0 edge enhancement max" hexmask.long.word 0xB4 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xB4 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xB8 "NSF3V_EE_C02,Color 0 edge enhancement max" hexmask.long.word 0xB8 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xB8 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xBC "NSF3V_EE_C10,Color 1 edge enhancement max" hexmask.long.word 0xBC 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xBC 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xC0 "NSF3V_EE_C11,Color 1 edge enhancement max" hexmask.long.word 0xC0 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xC0 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xC4 "NSF3V_EE_C12,Color 1 edge enhancement max" hexmask.long.word 0xC4 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xC4 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xC8 "NSF3V_EE_C20,Color 2 edge enhancement max" hexmask.long.word 0xC8 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xC8 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xCC "NSF3V_EE_C21,Color 2 edge enhancement max" hexmask.long.word 0xCC 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xCC 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xD0 "NSF3V_EE_C22,Color 2 edge enhancement max" hexmask.long.word 0xD0 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xD0 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xD4 "NSF3V_EE_C30,Color 3 edge enhancement max" hexmask.long.word 0xD4 16.--27. 1. "L1_HH,Level 1 HH suband ee_max U10.2" hexmask.long.word 0xD4 0.--11. 1. "L1_LH,Level 1 LH and HL subband ee_max U10.2" line.long 0xD8 "NSF3V_EE_C31,Color 3 edge enhancement max" hexmask.long.word 0xD8 16.--27. 1. "L2_HH,Level 2 HH suband ee_max U10.2" hexmask.long.word 0xD8 0.--11. 1. "L2_LH,Level 2 LH and HL subband ee_max U10.2" line.long 0xDC "NSF3V_EE_C32,Color 3 edge enhancement max" hexmask.long.word 0xDC 16.--27. 1. "L3_HH,Level 3 HH suband ee_max U10.2" hexmask.long.word 0xDC 0.--11. 1. "L3_LH,Level 3 LH and HL subband ee_max U10.2" line.long 0xE0 "NSF3V_DS_THR,Desaturation thresholds" bitfld.long 0xE0 16.--21. "THR2,desaturation threshold 2 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 0.--5. "THR1,desaturation threhsold 1 U6.0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "NSF3V_DS_SLOPE,Desaturation slopes" hexmask.long.word 0xE4 16.--25. 1. "SLOPE2,desaturation slope 2 U0.10" hexmask.long.word 0xE4 0.--9. 1. "SLOPE1,desaturation slope 1 U0.10" width 0x0B tree.end tree "ISP6P5_RESIZER" base ad:0x52040400 rgroup.long 0x00++0x07 line.long 0x00 "RSZ_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "RSZ_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is not shadowed" bitfld.long 0x04 9. "RSZB_CLK_EN,Resizer B clock enable This bit enable to enable / disable the RESIZER B clock" "RSZB_CLK_EN_0,RSZB_CLK_EN_1" bitfld.long 0x04 8. "RSZA_CLK_EN,Resizer A clock enable This bit enable to enable / disable the RESIZER A clock" "RSZA_CLK_EN_0,RSZA_CLK_EN_1" newline bitfld.long 0x04 0. "AUTOGATING,Internal Clock Gating Strategy Enables or disables auto clock gating" "AUTOGATING_0,AUTOGATING_1" hgroup.long 0x08++0x03 hide.long 0x00 "RSZ_SYSSTATUS,SYSTEM STATUS REGISTER This register is not shadowed" group.long 0x0C++0x0B line.long 0x00 "RSZ_IN_FIFO_CTRL,INPUT DATA BUFFER CONTROL REGISTER This register is not shadowed" hexmask.long.word 0x00 16.--28. 1. "THRLD_LOW,WhenRSZ_IN_FIFO_CTRL.THRLD_HIGH = RSZ_IN_FIFO_CTRL.THRLD_LOW the rsz_stall_input is not asserted" hexmask.long.word 0x00 0.--12. 1. "THRLD_HIGH,High threshold value" line.long 0x04 "RSZ_GNC,GENERIC PARAMETER REGISTER" hexmask.long.word 0x04 16.--28. 1. "RSZB_MEM_LINE_SIZE,Resizer #B memory line size (pixels)" hexmask.long.word 0x04 0.--12. 1. "RSZA_MEM_LINE_SIZE,Resizer #A memory line size (pixels)" line.long 0x08 "RSZ_FRACDIV,Fractional clock divider settings" hexmask.long.word 0x08 0.--15. 1. "RSZ_FRACDIV,Fractional clock divider value" group.long 0x20++0x2F line.long 0x00 "RSZ_SRC_EN,RESIZER ENABLE REGISTER This register is not shadowed" bitfld.long 0x00 0. "EN,Resizer module enable The start flag of the RESIZER module" "EN_0,EN_1" line.long 0x04 "RSZ_SRC_MODE,This register is not shadowed" bitfld.long 0x04 1. "WRT,Video port WEN signal selection This bit selects whether the WEN signal which is present on the IPIPE and IPIPEIF video port is used or not to select the input data" "WRT_0,WRT_1" bitfld.long 0x04 0. "OST,The processing mode selection of the RESIZER module" "OST_0,OST_1" line.long 0x08 "RSZ_SRC_FMT0,This register is not shadowed" bitfld.long 0x08 1. "BYPASS,Pass Through This bit enables or disables the RESIZER module pass through mode" "BYPASS_0,BYPASS_1" bitfld.long 0x08 0. "SEL,Input selection This bit selects which of the two video port is selected to push data through the RESIZER module" "SEL_0,SEL_1" line.long 0x0C "RSZ_SRC_FMT1," bitfld.long 0x0C 3. "CHR,Cb/Cr order This bit indicates if Cb/Cr is flipped" "Normal,Flipped" bitfld.long 0x0C 2. "COL,Y/C selection This bit is valid only if the input data is YUV420 (IN420 = '1')" "COL_0,COL_1" newline bitfld.long 0x0C 1. "IN420,Chroma Format Selection This bit sets the chroma undersampling when YUV data is input to the RESIZER module" "IN420_0,IN420_1" bitfld.long 0x0C 0. "RAW,Pass-through mode input data format selection This bit affects the horizontal reversal (flipping) process" "RAW_0,RAW_1" line.long 0x10 "RSZ_SRC_VPS,VERTICAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x10 0.--15. 1. "VPS,Vertical Start Position Sets the vertical position of the global frame from the rising edge of the VD" line.long 0x14 "RSZ_SRC_VSZ,VERTICAL SIZER REGISTER" hexmask.long.word 0x14 0.--12. 1. "VSZ,Vertical Processing Size Sets the vertical size of the processing area" line.long 0x18 "RSZ_SRC_HPS,HORIZONTAL POSITION REGISTER This register is not shadowed" hexmask.long.word 0x18 0.--15. 1. "HPS,Horizontal Start Position TheRSZ_SRC_HPS register has two functions" line.long 0x1C "RSZ_SRC_HSZ,HORIZONTAL SIZE REGISTER The HSZ value is given by HSZ concatenated with HSZ_LSB" hexmask.long.word 0x1C 0.--12. 1. "HSZ,Horizontal size Sets the horizontal size of the processing area" line.long 0x20 "RSZ_DMA_RZA,RESIZER A - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x20 0.--15. 1. "RZA,Sets the minimum inteval btw two consecutive memory request for resizer #A" line.long 0x24 "RSZ_DMA_RZB,RESIZER B - MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x24 0.--15. 1. "RZB,Sets the minimum inteval btw two consecutive memory request for resizer #B" line.long 0x28 "RSZ_DMA_STA,RESIZER STATUS REGISTER" bitfld.long 0x28 0. "STATUS,Resizer process status This bit is set in the time window from rsz_int_reg to rsz_int_dma" "STATUS_0,STATUS_1" line.long 0x2C "RSZ_GCK_MMR,MMR CLOCK CONTROL REGISTER This register is not shadowed" bitfld.long 0x2C 0. "MMR,The on/off selection of the MMR interface clock which is used for MMR register access" "MMR_0,MMR_1" group.long 0x54++0x143 line.long 0x00 "RSZ_GCK_SDR,CORE CLOCK CONTROL REGISTER This register is not shadowed" bitfld.long 0x00 0. "CORE,RSZ Core Clock Enable" "CORE_0,CORE_1" line.long 0x04 "RSZ_IRQ_RZA,RESIZER A - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" bitfld.long 0x04 24. "ICMA_CTRL_COL,Choose luma done (P_DONE_A) or chroma done (P_DONE_AC) to control - LUMA" "ICMA_CTRL_COL_0,ICMA_CTRL_COL_1" bitfld.long 0x04 21. "ICMA_CHR_EOF,Enable the generation of P_DONE_AC pulse at the end of each frame if the height is not a multiple of RZA" "ICMA_CHR_EOF_0,ICMA_CHR_EOF_1" newline bitfld.long 0x04 20. "ICMA_CHR_EN,Enable hand-shaking with ICM (RSZ-A) in Chroma Channel This is only valid in YUV-420 mode with chroma output" "ICMA_CHR_EN_0,ICMA_CHR_EN_1" bitfld.long 0x04 17. "ICMA_EOF,Enable the generation of P_DONE_A pulse at the end of each frame if the height is not a multiple of RZA" "ICMA_EOF_0,ICMA_EOF_1" newline bitfld.long 0x04 16. "ICMA_EN,Enable hand-shaking with ICM (RSZ-A) - DISABLE" "ICMA_EN_0,ICMA_EN_1" hexmask.long.word 0x04 0.--12. 1. "RZA,Resizer A circular buffer interval" line.long 0x08 "RSZ_IRQ_RZB,RESIZER B - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" bitfld.long 0x08 24. "ICMB_CTRL_COL,Choose luma done (P_DONE_B) or chroma done (P_DONE_BC) to control - LUMA" "ICMB_CTRL_COL_0,ICMB_CTRL_COL_1" bitfld.long 0x08 21. "ICMB_CHR_EOF,Enable the generation of P_DONE_BC pulse at the end of each frame if the height is not a multiple of RZB" "ICMB_CHR_EOF_0,ICMB_CHR_EOF_1" newline bitfld.long 0x08 20. "ICMB_CHR_EN,Enable hand-shaking with ICM (RSZ-B) in Chroma Channel This is only valid in YUV-420 mode with chroma output" "ICMB_CHR_EN_0,ICMB_CHR_EN_1" bitfld.long 0x08 17. "ICMB_EOF,Enable the generation of P_DONE_B pulse at the end of each frame if the height is not a multiple of RZB" "ICMB_EOF_0,ICMB_EOF_1" newline bitfld.long 0x08 16. "ICMB_EN,Enalbe handshake between RSZB and ICM - DISABLE" "ICMB_EN_0,ICMB_EN_1" hexmask.long.word 0x08 0.--12. 1. "RZB,Resizer B circular buffer interval" line.long 0x0C "RSZ_YUV_Y_MIN,LUMINANCE SATURATION REGISTER" hexmask.long.byte 0x0C 0.--7. 1. "MIN,The minimum value of Luminance (8bits unsigned)" line.long 0x10 "RSZ_YUV_Y_MAX,LUMINANCE SATURATION REGISTER" hexmask.long.byte 0x10 0.--7. 1. "MAX,The maximum value of Luminance (8bits unsigned)" line.long 0x14 "RSZ_YUV_C_MIN,CHROMINANCE SATURATION REGISTER" hexmask.long.byte 0x14 0.--7. 1. "MIN,The minimum value of Chrominance (8bits unsigned)" line.long 0x18 "RSZ_YUV_C_MAX,CHROMINANCE SATURATION REGISTER" hexmask.long.byte 0x18 0.--7. 1. "MAX,The maximum value of Chrominance (8bits unsigned)" line.long 0x1C "RSZ_YUV_PHS,The phase position of the output of the Chrominance" bitfld.long 0x1C 0. "POS,The phase position of the output of the chrominance" "POS_0,POS_1" line.long 0x20 "RSZ_SEQ," bitfld.long 0x20 4. "CRV,Chroma sampling point" "CRV_0,CRV_1" bitfld.long 0x20 3. "VRVB,Resizer B - Vertical reversal of output image - NEWENUM1" "VRVB_0,VRVB_1" newline bitfld.long 0x20 2. "HRVB,Resizer B -Horizontal reversal of output image - NEWENUM1" "HRVB_0,HRVB_1" bitfld.long 0x20 1. "VRVA,Resizer A - Vertical reversal of output image - NEWENUM1" "VRVA_0,VRVA_1" newline bitfld.long 0x20 0. "HRVA,Resizer A - Horizontal reversal of output image - NEWENUM1" "HRVA_0,HRVA_1" line.long 0x24 "RZA_EN,RESIZER A - ENABLE REGISTER" bitfld.long 0x24 0. "EN,Enable resizer #A This bit is latched on video port VD input" "EN_0,EN_1" line.long 0x28 "RZA_MODE,RESIZER #A MODE REGISTER" bitfld.long 0x28 0. "MODE,Select 'Free Run mode' or 'One Shot Mode' - NEWENUM1" "MODE_0,MODE_1" line.long 0x2C "RZA_420,YEN/CEN" bitfld.long 0x2C 1. "CEN,Output Enable for Chrominance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is" "CEN_0,CEN_1" bitfld.long 0x2C 0. "YEN,Output Enable for Luminance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is" "YEN_0,YEN_1" line.long 0x30 "RZA_I_VPS,RESIZER A - INPUT VERTICAL START REGISTER Note: The height of the image after the second crop must be 2 or larger" hexmask.long.word 0x30 0.--12. 1. "VPS,Input Vertical Position Sets the vertical start position of the input image within the global frame" line.long 0x34 "RZA_I_HPS,RESIZER A - INPUT HORIZONTAL START REGISTER" hexmask.long.word 0x34 0.--12. 1. "HPS,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame" line.long 0x38 "RZA_O_VSZ,RESIZER A - OUTPUT VERTICAL SIZE REGISTER In 422 to 420 mode. chorma output lines number is 1/2 of this value" hexmask.long.word 0x38 0.--12. 1. "VSZ,The target output size of the resized image" line.long 0x3C "RZA_O_HSZ,RESIZER A - OUTPUT HORIZONTAL SIZE REGISTER When CNFA is enabled. this value must be - Same as CNFA width. if CDS is off" hexmask.long.word 0x3C 1.--12. 1. "HSZ,The horizontal size of output image" rbitfld.long 0x3C 0. "HSZ_LSB,The least significant bit of HSZ is forced to 1" "HSZ_LSB_0,HSZ_LSB_1" line.long 0x40 "RZA_V_PHS_Y,RESIZER A - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.word 0x40 0.--13. 1. "Y,The initial value for the luma phase in vertical resizing process" line.long 0x44 "RZA_V_PHS_C,RESIZER A - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.word 0x44 0.--13. 1. "C,The initial value for the chroma phase in vertical resizing process" line.long 0x48 "RZA_V_DIF,RESIZER A - VERTICAL RESIZER REGISTER" abitfld.long 0x48 0.--13. "V,The parameter for vertical resize" "0x0010=RZA_V_DIF = 4096,0x0100=RZA_V_DIF = 4096" line.long 0x4C "RZA_V_TYP,RESIZER A - INTERPOLATION METHOD FOR VERTICAL RESIZING" bitfld.long 0x4C 1. "C,Selection of resizing method for" "C_0,C_1" bitfld.long 0x4C 0. "Y,Selection of resizing method for luminance: vertical - NEWENUM1" "Y_0,Y_1" line.long 0x50 "RZA_V_LPF,RESIZER A - VERTICAL LPF INTENSITY REGISTER" bitfld.long 0x50 6.--11. "C,The intensity parameter for chroma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x50 0.--5. "Y,The intensity parameter for luma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "RZA_H_PHS,RESIZER A - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.word 0x54 0.--13. 1. "PHS,Initial value for the phase in horizontal resizing process i.e. the sampling position is shifted" line.long 0x58 "RZA_H_PHS_ADJ,RESIZER A - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and.." hexmask.long.word 0x58 0.--8. 1. "ADJ,Horizontal phase adjustment value" line.long 0x5C "RZA_H_DIF,RESIZER A - HORIZONTAL RESIZER REGISTER" abitfld.long 0x5C 0.--13. "H,The parameter for horizontal resizing process" "0x0010=RSZ_RZA_H_DIF =4096 In down-scale mode,0x0100=RSZ_RZA_H_DIF =4096" line.long 0x60 "RZA_H_TYP,Resize-A" bitfld.long 0x60 1. "C,Selection of resizing method for" "C_0,C_1" bitfld.long 0x60 0. "Y,Selection of resizing method for luminance: horizontal - NEWENUM1" "Y_0,Y_1" line.long 0x64 "RZA_H_LPF,RESIZER A - HORIZONTAL LPF INTENSITY REGISTER" bitfld.long 0x64 6.--11. "C,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 0.--5. "Y,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "RZA_DWN_EN,RESIZER #A - DOWNSCALE ENABLE REGISTER" bitfld.long 0x68 0. "DWN_EN,Resizer downscale enable - NEWENUM1" "DWN_EN_0,DWN_EN_1" line.long 0x6C "RZA_DWN_AV,Resize-A" bitfld.long 0x6C 3.--5. "V,Vertical averaging size : 1/2^(VWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" bitfld.long 0x6C 0.--2. "H,Horizontal averaging size : 1/2^(HWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" line.long 0x70 "RZA_RGB_EN,RESIZER #A - RGB OUTPUT ENABLE" bitfld.long 0x70 0. "RGB_EN,Enable of RGB output In pass through mode this register must be 0" "RGB_EN_0,RGB_EN_1" line.long 0x74 "RZA_RGB_TYP,RESIZER A - RGB OUTPUT CONTROL REGISTER" bitfld.long 0x74 2. "MSK1,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK1_0,MSK1_1" bitfld.long 0x74 1. "MSK0,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK0_0,MSK0_1" newline bitfld.long 0x74 0. "TYP,16bit/32bit output selection - NEWENUM1" "TYP_0,TYP_1" line.long 0x78 "RZA_RGB_BLD,RESIZER A - RGB BLEND REGISTER" hexmask.long.byte 0x78 0.--7. 1. "BLD,The alpha value used in 32-bit RGBA output mode" line.long 0x7C "RZA_SDR_Y_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x7C 0.--15. 1. "Y_BAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x80 "RZA_SDR_Y_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x80 0.--15. 1. "Y_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x84 "RZA_SDR_Y_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x84 0.--15. 1. "Y_SAD_H,Memory Start Address Sets the 16 upper bits of the 32-bit start address in memory" line.long 0x88 "RZA_SDR_Y_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x88 0.--15. 1. "Y_SAD_L,Memory Start Address Sets 16 lower bits of the 32-bit start address in memory" line.long 0x8C "RZA_SDR_Y_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x8C 0.--16. 1. "Y_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x90 "RZA_SDR_Y_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x90 0.--12. 1. "Y_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x94 "RZA_SDR_Y_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x94 0.--12. 1. "Y_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0x98 "RZA_SDR_C_BAD_H,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x98 0.--15. 1. "C_BAD_H,Memory Base Address Sets the 16 higher bits of the 32-bit base address of the circular buffer in memory" line.long 0x9C "RZA_SDR_C_BAD_L,RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x9C 0.--15. 1. "C_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0xA0 "RZA_SDR_C_SAD_H,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xA0 0.--15. 1. "C_SAD_H,Memory Base Address Sets the 16 higher bits of the 32-bit start address in memory" line.long 0xA4 "RZA_SDR_C_SAD_L,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xA4 0.--15. 1. "C_SAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0xA8 "RZA_SDR_C_OFT,RESIZER A - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0xA8 0.--16. 1. "C_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0xAC "RZA_SDR_C_PTR_S,RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xAC 0.--12. 1. "C_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0xB0 "RZA_SDR_C_PTR_E,RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0xB0 0.--12. 1. "C_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0xB4 "RZB_EN,RESIZER B - ENABLE REGISTER" bitfld.long 0xB4 0. "EN,Enable resizer #A This bit is latched on the video port VD input signal" "EN_0,EN_1" line.long 0xB8 "RZB_MODE,RESIZER B MODE REGISTER" bitfld.long 0xB8 0. "MODE,Select 'Free Run mode' or 'One Shot Mode' - NEWENUM1" "MODE_0,MODE_1" line.long 0xBC "RZB_420,YEN/CEN" bitfld.long 0xBC 1. "CEN,Output Enable for Chrominance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is" "CEN_0,CEN_1" bitfld.long 0xBC 0. "YEN,Output Enable for Luminance This bit is valid in 422 input mode.When CEN=0 and YEN=0 output is" "YEN_0,YEN_1" line.long 0xC0 "RZB_I_VPS,RESIZER B - INPUT VERTICAL START REGISTER Note: The height of the image after the second crop must be 2 or larger" hexmask.long.word 0xC0 0.--12. 1. "VPS,Input Vertical Position Sets the vertical start position of the input image within the global frame" line.long 0xC4 "RZB_I_HPS,RESIZER B - INPUT HORIZONTAL START REGISTER" hexmask.long.word 0xC4 0.--12. 1. "HPS,Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame" line.long 0xC8 "RZB_O_VSZ,RESIZER B - OUTPUT VERTICAL SIZER REGISTER In 422 to 420 mode. chorma output lines number is 1/2 of this value" hexmask.long.word 0xC8 0.--12. 1. "VSZ,The target output size of the resized image" line.long 0xCC "RZB_O_HSZ,RESIZER B - OUTPUT HORIZONTAL SIZE REGISTER When CNFB is enabled. this value must be - Same as CNFB width. if CDS is off" hexmask.long.word 0xCC 1.--12. 1. "HSZ,The horizontal size of output image" rbitfld.long 0xCC 0. "HSZ_LSB,The least significant bit of HSZ is forced to 1" "HSZ_LSB_0,HSZ_LSB_1" line.long 0xD0 "RZB_V_PHS_Y,RESIZER B - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.word 0xD0 0.--13. 1. "Y,The initial value for the luma phase in vertical resizing process" line.long 0xD4 "RZB_V_PHS_C,RESIZER B - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV422 data are output. the phase values for luma and chroma should typicall be equal. i.e.. RZX_V_PHS_Y= RZX_V_PHS_C" hexmask.long.word 0xD4 0.--13. 1. "C,The initial value for the chroma phase in vertical resizing process" line.long 0xD8 "RZB_V_DIF,RESIZER B - VERTICAL RESIZER REGISTERR" abitfld.long 0xD8 0.--13. "V,The parameter for vertical resize" "0x0010=RZB_V_DIF = 4096,0x0100=RZB_V_DIF = 4096" line.long 0xDC "RZB_V_TYP,RESIZER B - INTERPOLATION METHOD FOR VERTICAL RESIZING" bitfld.long 0xDC 1. "C,Selection of resizing method for" "C_0,C_1" bitfld.long 0xDC 0. "Y,Selection of resizing method for luminance: vertical - NEWENUM1" "Y_0,Y_1" line.long 0xE0 "RZB_V_LPF,RESIZER B - VERTICAL LPF INTENSITY REGISTER" bitfld.long 0xE0 6.--11. "C,The intensity parameter for chroma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xE0 0.--5. "Y,The intensity parameter for luma vertical low pass filtering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xE4 "RZB_H_PHS,RESIZER B - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" hexmask.long.word 0xE4 0.--13. 1. "PHS,Initial value for the phase in horizontal resizing process i.e. the sampling position is shifted" line.long 0xE8 "RZB_H_PHS_ADJ,RESIZER B - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and.." hexmask.long.word 0xE8 0.--8. 1. "ADJ,Horizontal phase adjustment value" line.long 0xEC "RZB_H_DIF,RESIZER B - HORIZONTAL RESIZER REGISTER" abitfld.long 0xEC 0.--13. "H,The parameter for horizontal resizing process" "0x0010=RSZ_RZA_H_DIF =4096 In down-scale mode,0x0100=RSZ_RZA_H_DIF =4096" line.long 0xF0 "RZB_H_TYP,RESIZER B" bitfld.long 0xF0 1. "C,Selection of resizing method for" "C_0,C_1" bitfld.long 0xF0 0. "Y,Selection of resizing method for luminance: horizontal - NEWENUM1" "Y_0,Y_1" line.long 0xF4 "RZB_H_LPF,RESIZER B - HORIZONTAL LPF INTENSITY REGISTER" bitfld.long 0xF4 6.--11. "C,Horizontal LPF Intensity for Chrominance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xF4 0.--5. "Y,Selection of resizing method for Luminance in horizontal direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0xF8 "RZB_DWN_EN,RESIZER B - DOWNSCALE ENABLE REGISTER" bitfld.long 0xF8 0. "DWN_EN,Resizer downscale enable - NEWENUM1" "DWN_EN_0,DWN_EN_1" line.long 0xFC "RZB_DWN_AV,RESIZER B" bitfld.long 0xFC 3.--5. "V,Vertical averaging size : 1/2^(VWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" bitfld.long 0xFC 0.--2. "H,Horizontal averaging size : 1/2^(HWT+1) The range goes from 1/2 to 1/256 in power of two" "_DIV21/2 down scale,_DIV41/4 down scale,_DIV81/8 down scale,_DIV161/16 down scale,_DIV321/32 down scale,_DIV641/64 down scale,_DIV1281/128 down scale,_DIV2561/256 down scale" line.long 0x100 "RZB_RGB_EN,RESIZER B - RGB OUTPUT ENABLE" bitfld.long 0x100 0. "RGB_EN,Enable of RGB output In pass through mode this register must be 0" "RGB_EN_0,RGB_EN_1" line.long 0x104 "RZB_RGB_TYP,RESIZER B - RGB OUTPUT CONTROL REGISTER" bitfld.long 0x104 2. "MSK1,Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK1_0,MSK1_1" bitfld.long 0x104 1. "MSK0,Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV422 to YUV444 conversion" "MSK0_0,MSK0_1" newline bitfld.long 0x104 0. "TYP,16bit/32bit output selection - NEWENUM1" "TYP_0,TYP_1" line.long 0x108 "RZB_RGB_BLD,RESIZER B - RGB BLEND REGISTER" hexmask.long.byte 0x108 0.--7. 1. "BLD,The alpha value used in 32-bit RGBA output mode" line.long 0x10C "RZB_SDR_Y_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x10C 0.--15. 1. "Y_BAD_H,Memory Base Address Sets 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x110 "RZB_SDR_Y_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x110 0.--15. 1. "Y_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x114 "RZB_SDR_Y_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x114 0.--15. 1. "Y_SAD_H,Memory Start Address Sets 16 upper bits of the 32-bit start address in memory" line.long 0x118 "RZB_SDR_Y_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420. RGB565. RGBA" hexmask.long.word 0x118 0.--15. 1. "Y_SAD_L,Memory Start Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0x11C "RZB_SDR_Y_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.tbyte 0x11C 0.--16. 1. "Y_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x120 "RZB_SDR_Y_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x120 0.--12. 1. "Y_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x124 "RZB_SDR_Y_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW. YUV422. YUV420 or RGBA" hexmask.long.word 0x124 0.--12. 1. "Y_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" line.long 0x128 "RZB_SDR_C_BAD_H,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x128 0.--15. 1. "C_BAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory" line.long 0x12C "RZB_SDR_C_BAD_L,RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x12C 0.--15. 1. "C_BAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory" line.long 0x130 "RZB_SDR_C_SAD_H,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x130 0.--15. 1. "C_SAD_H,Memory Base Address Sets the 16 upper bits of the 32-bit start address in memory" line.long 0x134 "RZB_SDR_C_SAD_L,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x134 0.--15. 1. "C_SAD_L,Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory" line.long 0x138 "RZB_SDR_C_OFT,RESIZER B - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.tbyte 0x138 0.--16. 1. "C_OFT,Memory Line Offset Sets the size of each line in the circular buffer" line.long 0x13C "RZB_SDR_C_PTR_S,RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x13C 0.--12. 1. "C_PTR_S,Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space" line.long 0x140 "RZB_SDR_C_PTR_E,RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV420) This register is used if the output data format is YUV420" hexmask.long.word 0x140 0.--12. 1. "C_PTR_E,End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space" width 0x0B tree.end tree "ISP6P5_SYS1" base ad:0x52040000 rgroup.long 0x00++0x0B line.long 0x00 "ISP5_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ISP5_HWINFO1,GENERIC PARAMETER REGISTER Information about the IP module's hardware configuration" hexmask.long.word 0x04 16.--28. 1. "ISIF_RFM_LINE_SIZE,Memory line size for the data reformatter in the ISIF module" hexmask.long.word 0x04 0.--12. 1. "IPIPE_LINE_SIZE,Memory line size for the IPIPE module" line.long 0x08 "ISP5_HWINFO2,GENERIC PARAMETER REGISTER Information about the IP module's hardware configuration" hexmask.long.word 0x08 0.--12. 1. "H3A_LINE_SIZE,Memory line size for the H3A module" group.long 0x10++0x03 line.long 0x00 "ISP5_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" rbitfld.long 0x00 0. "AUTO_IDLE,Auto clock gating" "AUTO_IDLE_0,AUTO_IDLE_1" group.long 0x20++0x6B line.long 0x00 "ISP5_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3" line.long 0x04 "ISP5_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x04 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x04 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x04 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x04 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x04 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x04 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x04 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x04 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x04 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x04 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x04 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x04 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x04 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x04 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x04 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x04 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x04 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x04 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x04 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x04 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x04 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x04 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x04 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x04 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x04 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x04 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x04 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x08 "ISP5_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x08 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x08 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x08 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x08 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x08 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x08 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x08 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x08 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x08 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x08 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x08 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x08 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x08 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x08 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x08 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x08 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x08 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x08 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x08 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x08 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x08 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x08 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x08 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x08 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x08 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x08 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x08 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x08 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x0C "ISP5_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x0C 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x0C 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x0C 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x0C 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x0C 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x0C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x0C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x0C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x0C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x0C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x0C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x0C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x0C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x0C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x0C 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x0C 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x0C 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x0C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x0C 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x0C 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x0C 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x0C 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x0C 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x0C 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x0C 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x0C 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x0C 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x10 "ISP5_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x10 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x10 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x10 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x10 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x10 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x10 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x10 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x10 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x10 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x10 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x10 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x10 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x10 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x10 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x10 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x10 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x10 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x10 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x10 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x10 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x10 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x10 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x10 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x10 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x10 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x10 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x10 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x14 "ISP5_IRQSTATUS_RAW_1,Per-event raw interrupt status vector" bitfld.long 0x14 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x14 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x14 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x14 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x14 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x14 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x14 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x14 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x14 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x14 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x14 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x14 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x14 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x14 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x14 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x14 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x14 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x14 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x14 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x14 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x14 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x14 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x14 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x14 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x14 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x14 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x14 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x14 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x18 "ISP5_IRQSTATUS_1,Per-event 'enabled' interrupt status vector" bitfld.long 0x18 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x18 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x18 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x18 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x18 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x18 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x18 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x18 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x18 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x18 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x18 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x18 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x18 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x18 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x18 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x18 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x18 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x18 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x18 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x18 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x18 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x18 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x18 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x18 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x18 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x18 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x18 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x18 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x1C "ISP5_IRQENABLE_SET_1,Per-event interrupt enable bit vector" bitfld.long 0x1C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x1C 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x1C 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x1C 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x1C 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x1C 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x1C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x1C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x1C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x1C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x1C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x1C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x1C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x1C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x1C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x1C 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x1C 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x1C 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x1C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x1C 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x1C 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x1C 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x1C 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x1C 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x1C 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x1C 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x1C 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x1C 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x20 "ISP5_IRQENABLE_CLR_1,Per-event interrupt enable bit vector" bitfld.long 0x20 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x20 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x20 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x20 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x20 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x20 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x20 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x20 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x20 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x20 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x20 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x20 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x20 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x20 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x20 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x20 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x20 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x20 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x20 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x20 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x20 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x20 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x20 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x20 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x20 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x20 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x20 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x20 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x24 "ISP5_IRQSTATUS_RAW_2,Per-event raw interrupt status vector" bitfld.long 0x24 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x24 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x24 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x24 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x24 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x24 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x24 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x24 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x24 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x24 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x24 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x24 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x24 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x24 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x24 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x24 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x24 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x24 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x24 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x24 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x24 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x24 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x24 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x24 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x24 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x24 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x24 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x24 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x28 "ISP5_IRQSTATUS_2,Per-event 'enabled' interrupt status vector" bitfld.long 0x28 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x28 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x28 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x28 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x28 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x28 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x28 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x28 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x28 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x28 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x28 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x28 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x28 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x28 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x28 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x28 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x28 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x28 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x28 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x28 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x28 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x28 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x28 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x28 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x28 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x28 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x28 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x28 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x2C "ISP5_IRQENABLE_SET_2,Per-event interrupt enable bit vector" bitfld.long 0x2C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x2C 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x2C 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x2C 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x2C 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x2C 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x2C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x2C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x2C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x2C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x2C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x2C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x2C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x2C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x2C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x2C 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x2C 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x2C 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x2C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x2C 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x2C 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x2C 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x2C 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x2C 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x2C 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x2C 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x2C 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x2C 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x30 "ISP5_IRQENABLE_CLR_2,Per-event interrupt enable bit vector" bitfld.long 0x30 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x30 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x30 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x30 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x30 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x30 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x30 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x30 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x30 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x30 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x30 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x30 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x30 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x30 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x30 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x30 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x30 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x30 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x30 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x30 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x30 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x30 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x30 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x30 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x30 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x30 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x30 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x30 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x34 "ISP5_IRQSTATUS_RAW_3,Per-event raw interrupt status vector" bitfld.long 0x34 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x34 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x34 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x34 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x34 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x34 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x34 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x34 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x34 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x34 18. "RSZ_FIFO_OVF,Resizer module overflow This event is set when overflow happens in the RESIZER module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x34 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x34 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x34 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x34 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x34 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x34 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x34 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x34 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x34 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x34 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x34 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x34 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x34 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x34 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x34 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x34 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x34 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x34 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x38 "ISP5_IRQSTATUS_3,Per-event 'enabled' interrupt status vector" bitfld.long 0x38 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x38 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x38 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x38 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x38 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x38 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x38 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x38 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x38 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x38 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x38 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x38 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x38 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x38 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x38 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x38 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x38 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x38 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x38 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x38 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x38 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x38 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x38 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x38 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x38 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x38 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x38 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x38 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x3C "ISP5_IRQENABLE_SET_3,Per-event interrupt enable bit vector" bitfld.long 0x3C 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x3C 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x3C 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x3C 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x3C 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x3C 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x3C 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x3C 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x3C 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x3C 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x3C 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x3C 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x3C 15. "RSZ_INT_DMA,This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x3C 14. "RSZ_INT_LAST_PIX,This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x3C 13. "RSZ_INT_REG,This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x3C 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x3C 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x3C 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x3C 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x3C 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x3C 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x3C 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x3C 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x3C 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x3C 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x3C 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x3C 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x3C 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x40 "ISP5_IRQENABLE_CLR_3,Per-event interrupt enable bit vector" bitfld.long 0x40 31. "OCP_ERR_IRQ,An OCP error has been received on the ISP5 master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" bitfld.long 0x40 29. "IPIPE_INT_DPC_RNEW1,- NOACTION" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x40 28. "IPIPE_INT_DPC_RNEW0,- NOACTION" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x40 27. "IPIPE_INT_DPC_INI,- NOACTION" "IPIPE_INT_DPC_INI_0,IPIPE_INT_DPC_INI_1" bitfld.long 0x40 25. "IPIPE_INT_EOF,- NOACTION" "IPIPE_INT_EOF_0,IPIPE_INT_EOF_1" bitfld.long 0x40 24. "H3A_INT_EOF,- NOACTION" "H3A_INT_EOF_0,H3A_INT_EOF_1" newline bitfld.long 0x40 23. "RSZ_INT_EOF1,RESIZER module event: This event signals that the BL has received the eof signal from the resizer B engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF1_0,RSZ_INT_EOF1_1" bitfld.long 0x40 22. "RSZ_INT_EOF0,RESIZER module event: This event signals that the BL has received the eof signal from the resizer A engine which happens one the last transfer in the frame has happened" "RSZ_INT_EOF0_0,RSZ_INT_EOF0_1" bitfld.long 0x40 19. "RSZ_FIFO_IN_BLK_ERR,This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule" "RSZ_FIFO_IN_BLK_ERR_0,RSZ_FIFO_IN_BLK_ERR_1" newline bitfld.long 0x40 18. "RSZ_FIFO_OVF,This event would typically happen while processing a frame because the video port pixel clock is too high: the firmware shall take care to use a lower pixel clock at the input of the resizer module" "RSZ_FIFO_OVF_0,RSZ_FIFO_OVF_1" bitfld.long 0x40 17. "RSZ_INT_CYC_RZB,RESIZER module event: This event is the circular interrupt for RESIZER #B" "RSZ_INT_CYC_RZB_0,RSZ_INT_CYC_RZB_1" bitfld.long 0x40 16. "RSZ_INT_CYC_RZA,RESIZER module event: This event is the circular interrupt for RESIZER #A" "RSZ_INT_CYC_RZA_0,RSZ_INT_CYC_RZA_1" newline bitfld.long 0x40 15. "RSZ_INT_DMA,RESIZER module event: This event is triggered when the last eof (of the two MTC interfaces) is sent out to the BL and that the resizer core has returned to idle" "RSZ_INT_DMA_0,RSZ_INT_DMA_1" bitfld.long 0x40 14. "RSZ_INT_LAST_PIX,RESIZER module event: This event is triggered when the last pixel of the valid area is received" "RSZ_INT_LAST_PIX_0,RSZ_INT_LAST_PIX_1" bitfld.long 0x40 13. "RSZ_INT_REG,RESIZER module event: This event is triggered when the first pixel of the valid area is received" "RSZ_INT_REG_0,RSZ_INT_REG_1" newline bitfld.long 0x40 12. "H3A_INT,- NOACTION" "H3A_INT_0,H3A_INT_1" bitfld.long 0x40 11. "AF_INT,- NOACTION" "AF_INT_0,AF_INT_1" bitfld.long 0x40 10. "AEW_INT,- NOACTION" "AEW_INT_0,AEW_INT_1" newline bitfld.long 0x40 9. "IPIPEIF_IRQ,IPIPEIF module interrupt - NOACTION" "IPIPEIF_IRQ_0,IPIPEIF_IRQ_1" bitfld.long 0x40 8. "IPIPE_INT_HST,- NOACTION" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x40 7. "IPIPE_INT_BSC,- NOACTION" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" newline bitfld.long 0x40 6. "IPIPE_INT_DMA,- NOACTION" "IPIPE_INT_DMA_0,IPIPE_INT_DMA_1" bitfld.long 0x40 5. "IPIPE_INT_LAST_PIX,- NOACTION" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x40 4. "IPIPE_INT_REG,- NOACTION" "IPIPE_INT_REG_0,IPIPE_INT_REG_1" newline bitfld.long 0x40 3. "ISIF_INT_3,- NOACTION" "ISIF_INT_3_0,ISIF_INT_3_1" bitfld.long 0x40 2. "ISIF_INT_2,- NOACTION" "ISIF_INT_2_0,ISIF_INT_2_1" bitfld.long 0x40 1. "ISIF_INT_1,- NOACTION" "ISIF_INT_1_0,ISIF_INT_1_1" newline bitfld.long 0x40 0. "ISIF_INT_0,- NOACTION" "ISIF_INT_0_0,ISIF_INT_0_1" line.long 0x44 "ISP5_DMAENABLE_SET,Per-line DMA enable bit vector Write 1 to set (enable DMA request generation)" bitfld.long 0x44 4. "IPIPE_INT_DPC_RNEW1,Enable for ISP5 DMA request generation on line #2 This DMA request shall be set to transfer the DPC data from memory to the IPIPE internal RAM" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x44 3. "IPIPE_INT_LAST_PIX,Enable for ISP5 DMA request generation on line #3 This DMA request shall be set to transfer the GAMMA data from memory to the IPIPE internal RAM or to initialize the DPC table" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x44 2. "IPIPE_INT_DPC_RNEW0,Enable for ISP5 DMA request generation on line #2 This DMA request shall be set to transfer the DPC data from memory to the IPIPE internal RAM" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x44 1. "IPIPE_INT_HST,Enable for ISP5 DMA request generation on line #1 This DMA request shall be set to transfer the HIST data from the IPIPE internal RAM to memory" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x44 0. "IPIPE_INT_BSC,Enable for ISP5 DMA request generation on line #0 This DMA request shall be set to transfer the BSC data from the IPIPE internal RAM to memory" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" line.long 0x48 "ISP5_DMAENABLE_CLR,Per-line DMA clear bit vector Write 1 to clear (disable DMA request generation)" bitfld.long 0x48 4. "IPIPE_INT_DPC_RNEW1,Clear for ISP5 DMA request generation on line ISP5_DMA_REQ[2]" "IPIPE_INT_DPC_RNEW1_0,IPIPE_INT_DPC_RNEW1_1" bitfld.long 0x48 3. "IPIPE_INT_LAST_PIX,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[3]" "IPIPE_INT_LAST_PIX_0,IPIPE_INT_LAST_PIX_1" bitfld.long 0x48 2. "IPIPE_INT_DPC_RNEW0,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[2]" "IPIPE_INT_DPC_RNEW0_0,IPIPE_INT_DPC_RNEW0_1" newline bitfld.long 0x48 1. "IPIPE_INT_HST,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[1]" "IPIPE_INT_HST_0,IPIPE_INT_HST_1" bitfld.long 0x48 0. "IPIPE_INT_BSC,Clear for ISP5 DMA request generation on ISP5_DMA_REQ[0]" "IPIPE_INT_BSC_0,IPIPE_INT_BSC_1" line.long 0x4C "ISP5_CTRL,ISP5 CONTROL REGISTER" bitfld.long 0x4C 30.--31. "DMA3_CFG,This bitfield selects the DMA transfer configuration which is used with the ISP5_DMA_REQ[3] DMA request signal" "DMA3_CFG_0,DMA3_CFG_1,DMA3_CFG_2,DMA3_CFG_3" bitfld.long 0x4C 27. "BSC_RD_CHK,When the BSC computation is enabled and the BSC DMA request not used to read out the data this register enables to ensure that the data were read fast enough else an interrupt IPIPE_BSC_ERR is triggered" "BSC_RD_CHK_0,BSC_RD_CHK_1" bitfld.long 0x4C 26. "HST_RD_CHK,When the HISTOGRAM computation is enabled and the HST DMA request not used to read out the data this register enables to ensure that the data were read fast enough else an interrupt IPIPE_HST_ERR is triggered" "HST_RD_CHK_0,HST_RD_CHK_1" newline bitfld.long 0x4C 25. "DPC_EVT_INI,Select the IPIPE module event to be used to generate the DMA requests for the DPC submodule" "DPC_EVT_INI_0,DPC_EVT_INI_1" bitfld.long 0x4C 24. "MSTANDBY,MStandby signal assertion and de-assertion control for power management transitions" "MSTANDBY_0,MSTANDBY_1" bitfld.long 0x4C 23. "VD_PULSE_EXT,VD pulse extension enable This bit enables or disables the VD extension bridge" "VD_PULSE_EXT_0,VD_PULSE_EXT_1" newline bitfld.long 0x4C 22. "PCLK_INV,Pixel clock inversion This bit enables or disables pixel clock inversion" "PCLK_INV_0,PCLK_INV_1" bitfld.long 0x4C 21. "MFLAG,MFlag signal generation control This bit controls how the OCP MFlag signal is generated on the ISS NOC" "MFLAG_0,MFLAG_1" rbitfld.long 0x4C 20. "MSTANDDBY_WAIT,MStandby / Wait power management status bit" "MSTANDDBY_WAIT_0,MSTANDDBY_WAIT_1" newline bitfld.long 0x4C 19. "GLBCE_CLK_ENABLE,GLBCE clock enable - NEWENUM1" "GLBCE_CLK_ENABLE_0,GLBCE_CLK_ENABLE_1" bitfld.long 0x4C 18. "NSF3V_CLK_ENABLE,NSF3V clock enable - NEWENUM1" "NSF3V_CLK_ENABLE_0,NSF3V_CLK_ENABLE_1" bitfld.long 0x4C 17. "CNFB_CLK_ENABLE,CNFB clock enable - NEWENUM1" "CNFB_CLK_ENABLE_0,CNFB_CLK_ENABLE_1" newline bitfld.long 0x4C 16. "CNFA_CLK_ENABLE,CNFA clock enable - NEWENUM1" "CNFA_CLK_ENABLE_0,CNFA_CLK_ENABLE_1" bitfld.long 0x4C 15. "BL_CLK_ENABLE,BL clock enable - NEWENUM1" "BL_CLK_ENABLE_0,BL_CLK_ENABLE_1" bitfld.long 0x4C 14. "ISIF_CLK_ENABLE,ISIF clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "ISIF_CLK_ENABLE_0,ISIF_CLK_ENABLE_1" newline bitfld.long 0x4C 13. "H3A_CLK_ENABLE,H3A clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "H3A_CLK_ENABLE_0,H3A_CLK_ENABLE_1" bitfld.long 0x4C 12. "RSZ_CLK_ENABLE,RESIZER clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "RSZ_CLK_ENABLE_0,RSZ_CLK_ENABLE_1" bitfld.long 0x4C 11. "IPIPE_CLK_ENABLE,IPIPE clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "IPIPE_CLK_ENABLE_0,IPIPE_CLK_ENABLE_1" newline bitfld.long 0x4C 10. "IPIPEIF_CLK_ENABLE,IPIPEIF clock enable The ISP5 will return OCP_ERROR if one tries to program the module MMR or memory when the clock is disabled" "IPIPEIF_CLK_ENABLE_0,IPIPEIF_CLK_ENABLE_1" bitfld.long 0x4C 9. "SYNC_ENABLE,PCLK Sync module enable - NEWENUM1" "SYNC_ENABLE_0,SYNC_ENABLE_1" bitfld.long 0x4C 8. "PSYNC_CLK_SEL,PCLK Sync clock select" "PSYNC_CLK_SEL_0,PSYNC_CLK_SEL_1" newline bitfld.long 0x4C 4.--7. "VBUSM_CIDS,BL MAX VBUSM CIDs The BL module supports up to 16 CIDs/tags" "VBUSM_CIDS_0,VBUSM_CIDS_1,VBUSM_CIDS_2,VBUSM_CIDS_3,VBUSM_CIDS_4,VBUSM_CIDS_5,VBUSM_CIDS_6,VBUSM_CIDS_7,VBUSM_CIDS_8,VBUSM_CIDS_9,VBUSM_CIDS_10,VBUSM_CIDS_11,VBUSM_CIDS_12,VBUSM_CIDS_13,VBUSM_CIDS_14,VBUSM_CIDS_15" bitfld.long 0x4C 1.--3. "VBUSM_CPRIORITY,BL VBUSM priority setting - NEWENUM7" "VBUSM_CPRIORITY_0,VBUSM_CPRIORITY_1,VBUSM_CPRIORITY_2,VBUSM_CPRIORITY_3,VBUSM_CPRIORITY_4,VBUSM_CPRIORITY_5,VBUSM_CPRIORITY_6,VBUSM_CPRIORITY_7" bitfld.long 0x4C 0. "OCP_WRNP,ISP5 OCP master port non-posted write control" "OCP_WRNP_0,OCP_WRNP_1" line.long 0x50 "ISP5_PG,PATTERN GENERATOR REGISTER" bitfld.long 0x50 4.--5. "SRC_SEL,Input mux selection - NEWENUM1" "SRC_SEL_0,SRC_SEL_1,SRC_SEL_2,SRC_SEL_3" bitfld.long 0x50 3. "EN,- NEWENUM1" "EN_0,EN_1" bitfld.long 0x50 2. "WEN,- NEWENUM1" "WEN_0,WEN_1" newline bitfld.long 0x50 1. "HDPOL,- NEWENUM1" "HDPOL_0,HDPOL_1" bitfld.long 0x50 0. "VDPOL,- NEWENUM1" "VDPOL_0,VDPOL_1" line.long 0x54 "ISP5_PG_PULSE_CTRL,PATTERN GENERATOR REGISTER" hexmask.long.word 0x54 16.--27. 1. "VDW,Pattern generator VD width Width = VDW+1" hexmask.long.word 0x54 0.--12. 1. "HDW,Pattern generator HD width Width = HDW+1" line.long 0x58 "ISP5_PG_FRAME_SIZE,PATTERN GENERATOR REGISTER" hexmask.long.word 0x58 16.--31. 1. "PPLN,Pattern Generator: pixels per line PPLN+1" hexmask.long.word 0x58 0.--15. 1. "HLPFR,Pattern Generator: half lines per frame HLPFR+1" line.long 0x5C "ISP5_MPSR,ISP5 memory access register" bitfld.long 0x5C 31. "IPIPEIF_CMP_LUT2,IPIPEIF Companding LUT memory access priority" "IPIPEIF_CMP_LUT2_0,IPIPEIF_CMP_LUT2_1" bitfld.long 0x5C 30. "IPIPEIF_DECMP_LUT1,IPIPEIF Memory Read path Decompanding LUT memory access priority" "IPIPEIF_DECMP_LUT1_0,IPIPEIF_DECMP_LUT1_1" bitfld.long 0x5C 29. "IPIPEIF_DECMP_LUT0,IPIPEIF VPORT Decompanding LUT memory access priority" "IPIPEIF_DECMP_LUT0_0,IPIPEIF_DECMP_LUT0_1" newline bitfld.long 0x5C 28. "ISP_GLBCE_TB,ISP GLBCE TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISP_GLBCE_TB_0,ISP_GLBCE_TB_1" bitfld.long 0x5C 24. "IPIPE_GAMMA_RGB_COPY,GAMMA table RGB Copy This bit shall be enable when one wants to use the same Gamma table for the R G and B color components" "IPIPE_GAMMA_RGB_COPY_0,IPIPE_GAMMA_RGB_COPY_1" bitfld.long 0x5C 20. "IPIPE_BSC_TB1,IPIPE BSC TB1 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period" "IPIPE_BSC_TB1_0,IPIPE_BSC_TB1_1" newline bitfld.long 0x5C 19. "IPIPE_BSC_TB0,IPIPE BSC TB0 memory access priority This memory is expected to be read by the CPU or the DMA to get BSC information during vertical blanking period" "IPIPE_BSC_TB0_0,IPIPE_BSC_TB0_1" bitfld.long 0x5C 18. "IPIPE_HST_TB3,IPIPE histogram memory #3 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB3_0,IPIPE_HST_TB3_1" bitfld.long 0x5C 17. "IPIPE_HST_TB2,IPIPE histogram memory #2 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB2_0,IPIPE_HST_TB2_1" newline bitfld.long 0x5C 16. "IPIPE_HST_TB1,IPIPE histogram memory #1 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB1_0,IPIPE_HST_TB1_1" bitfld.long 0x5C 15. "IPIPE_HST_TB0,IPIPE histogram memory #0 access priority This memory is expected to be read by the CPU or the DMA to get HST information during vertical blanking period" "IPIPE_HST_TB0_0,IPIPE_HST_TB0_1" bitfld.long 0x5C 14. "IPIPE_D3L_TB3,D3L TB3 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB3_0,IPIPE_D3L_TB3_1" newline bitfld.long 0x5C 13. "IPIPE_D3L_TB2,D3L TB2 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB2_0,IPIPE_D3L_TB2_1" bitfld.long 0x5C 12. "IPIPE_D3L_TB1,D3L TB1 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB1_0,IPIPE_D3L_TB1_1" bitfld.long 0x5C 11. "IPIPE_D3L_TB0,D3L TB0 memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_D3L_TB0_0,IPIPE_D3L_TB0_1" newline bitfld.long 0x5C 10. "IPIPE_GBC_TB,IPIPE GBC TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GBC_TB_0,IPIPE_GBC_TB_1" bitfld.long 0x5C 9. "IPIPE_YEE_TB,YEE TB memory access priority This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_YEE_TB_0,IPIPE_YEE_TB_1" bitfld.long 0x5C 8. "IPIPE_GMM_TBR,IPIPE Gamma LUT R memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBR_0,IPIPE_GMM_TBR_1" newline bitfld.long 0x5C 7. "IPIPE_GMM_TBG,IPIPE Gamma LUT G memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBG_0,IPIPE_GMM_TBG_1" bitfld.long 0x5C 6. "IPIPE_GMM_TBB,IPIPE Gamma LUT B memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_GMM_TBB_0,IPIPE_GMM_TBB_1" bitfld.long 0x5C 5. "IPIPE_DPC_TB,IPIPE defect pixel memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "IPIPE_DPC_TB_0,IPIPE_DPC_TB_1" newline bitfld.long 0x5C 4. "ISIF_DCLAMP,ISIF DC accumulation memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_DCLAMP_0,ISIF_DCLAMP_1" bitfld.long 0x5C 3. "ISIF_LSC_TB1,ISIF LSC memory 1 access This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LSC_TB1_0,ISIF_LSC_TB1_1" bitfld.long 0x5C 2. "ISIF_LSC_TB0,ISIF LSC memory 0 access This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LSC_TB0_0,ISIF_LSC_TB0_1" newline bitfld.long 0x5C 1. "ISIF_LIN_TB,ISIF linearity compensation memory arbitration This memory is expected to be written during ISP5 initialization and potentially updated during vertical blanking periods" "ISIF_LIN_TB_0,ISIF_LIN_TB_1" line.long 0x60 "ISP5_BL_MTC_1,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x60 16.--31. 1. "ISIF_R,Sets the minimum interval btw two consecutive memory requests for the ISIF-Read port" hexmask.long.word 0x60 0.--15. 1. "IPIPEIF_R,Sets the minimum interval btw two consecutive memory requests for the IPIPEIF-Read port" line.long 0x64 "ISP5_BL_MTC_2,MEMORY REQUEST MINIMUM INTERVAL REGISTER" hexmask.long.word 0x64 16.--31. 1. "H3A_W,Sets the minimum interval btw two consecutive memory requests for the H3A-Write port" line.long 0x68 "ISP5_BL_VBUSM,BL VBUSM TUNING REGISTER The settings in the register are static and not expected to be modified dynamically" bitfld.long 0x68 5. "MFLAG_THRES,MFLAG Threshold value The value of this bit field is a threshold which is compared to the MFlag output of the ISP5" "MFLAG_THRES_0,MFLAG_THRES_1" bitfld.long 0x68 0.--4. "LASTCMD_DLY,The value of this bitfield represents a delay expressed in cycles (L3 clock)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree.end tree "ISS_Interfaces" tree "CAL_A" base ad:0x52012000 group.long 0x130++0x07 line.long 0x00 "CAL_BYS_CTRL1,BYS port control register" bitfld.long 0x00 31. "BYSINEN,Enable/disable the BYS input port Note: the BYS output port is disabled by setting PCLK=0 - DIS" "BYSINEN_0,BYSINEN_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,BYSout port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_BYS_CTRL2,BYS port control register" bitfld.long 0x04 11. "FREERUNNING,Controls PCLK generation when the BYSout state machine is in the IDLE state - NO" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 10. "DUPLICATEDDATA,Control if data sent to the BYS output port should also be send to the DPCM encoder - NO" "DUPLICATEDDATA_0,DUPLICATEDDATA_1" bitfld.long 0x04 5.--9. "CPORTOUT,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "CPORTIN,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x07 line.long 0x00 "CAL_CTRL,Global control register" hexmask.long.byte 0x00 24.--31. 1. "MFLAGH,refer to real time traffic section of the spec" bitfld.long 0x00 22. "RD_DMA_STALL,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0" "RD_DMA_STALL_0,RD_DMA_STALL_1" bitfld.long 0x00 21. "PWRSCPCLK,Controls autogating of the PWRSCP clock - AUTO" "PWRSCPCLK_0,PWRSCPCLK_1" newline hexmask.long.byte 0x00 13.--20. 1. "MFLAGL,refer to real time traffic section of the spec" bitfld.long 0x00 7.--12. "LL_FORCE_STATE,Forces the state of the CSI-3 low level protocol state machine" "the next OCPI transaction for this CPORT will..,the next OCPI transaction for this CPORT will..,?..." bitfld.long 0x00 5.--6. "BURSTSIZE,Maximum allowed burst size for the write DMA" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 1.--4. "TAGCNT,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "POSTED_WRITES,- NONPOSTED" "POSTED_WRITES_0,POSTED_WRITES_1" line.long 0x04 "CAL_CTRL1,CAL global control register" bitfld.long 0x04 4.--5. "INTERLEAVE23,Controls stream interleaving Context #2 and #3 - DISABLED" "INTERLEAVE23_0,INTERLEAVE23_1,INTERLEAVE23_2,INTERLEAVE23_3" bitfld.long 0x04 2.--3. "INTERLEAVE01,Controls stream interleaving Context #0 and #1 - DISABLED" "INTERLEAVE01_0,INTERLEAVE01_1,INTERLEAVE01_2,INTERLEAVE01_3" bitfld.long 0x04 0.--1. "PPI_GROUPING,Controls PPI grouping - DISABLED" "PPI_GROUPING_0,PPI_GROUPING_1,PPI_GROUPING_2,PPI_GROUPING_3" rgroup.long 0x04++0x03 line.long 0x00 "CAL_HL_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x00 30.--31. "NPPI_CONTEXTS1,Number of contexts for PPI interface #1 - RESERVED" "NPPI_CONTEXTS1_0_r,NPPI_CONTEXTS1_1_r,NPPI_CONTEXTS1_2_r,NPPI_CONTEXTS1_3_r" bitfld.long 0x00 28.--29. "NPPI_CONTEXTS0,Number of contexts for PPI interface #0 - RESERVED" "NPPI_CONTEXTS0_0_r,NPPI_CONTEXTS0_1_r,NPPI_CONTEXTS0_2_r,NPPI_CONTEXTS0_3_r" bitfld.long 0x00 23.--27. "NCPORT,Number of supported CPORTs (including CPORT #0) minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--22. "VFIFO,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--18. "WCTX,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--12. "PCTX,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "RFIFO,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "WFIFO,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" rgroup.long 0x00++0x03 line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration - FORCE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset - NOACTION" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x108++0x03 line.long 0x00 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event" hexmask.long.word 0x00 16.--29. 1. "LINE," bitfld.long 0x00 0.--4. "CPORT,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x03 line.long 0x00 "CAL_RD_DMA_CTRL,Read DMA control register" hexmask.long.tbyte 0x00 15.--31. 1. "PCLK,Controls the data rate at which data is read from the read DMA FIFO and sent to the internal processing pipeline" bitfld.long 0x00 11.--14. "OCP_TAG_CNT,Maximum allowed number of outstanding OCP read requests minus 1 (i.e. 0xF meand up to 16 outstanding requests)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--10. 1. "BW_LIMITER,Defines a minimum cycle count between to consecutive read requests issued by the RD DMA" newline bitfld.long 0x00 1. "INIT,Enable reading of DPCM decoder initialization data from SDRAM - DIS" "INIT_0,INIT_1" bitfld.long 0x00 0. "GO,Start data read from memory" "GO_0_r,GO_1_r" group.long 0x16C++0x03 line.long 0x00 "CAL_RD_DMA_CTRL2,Read DMA control register" hexmask.long.word 0x00 16.--29. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 6. "BYSOUT_LE_WAIT,Controls the behavior of the RD DMA when the line end is reached" "BYSOUT_LE_WAIT_0,BYSOUT_LE_WAIT_1" bitfld.long 0x00 4.--5. "RD_PATTERN,Data read pattern - LINEAR" "RD_PATTERN_0,RD_PATTERN_1,RD_PATTERN_2,RD_PATTERN_3" newline bitfld.long 0x00 3. "ICM_CSTART,Enables monitoring of the ICM_CSTART signal - DIS" "ICM_CSTART_0,ICM_CSTART_1" bitfld.long 0x00 0.--2. "CIRC_MODE,Circular mode control - ONE" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3,CIRC_MODE_4,CIRC_MODE_5,?,?" group.long 0x154++0x03 line.long 0x00 "CAL_RD_DMA_INIT_ADDR,Read address" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" group.long 0x168++0x03 line.long 0x00 "CAL_RD_DMA_INIT_OFST,Byte offset between two consecutive line starts" hexmask.long 0x00 3.--31. 1. "OFST,Offset in words of 8 bytes" group.long 0x144++0x0F line.long 0x00 "CAL_RD_DMA_PIX_ADDR,Byte address of the top left corner of the buffer to read in system memory" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" line.long 0x04 "CAL_RD_DMA_PIX_OFST,Byte offset between two consecutive line starts Shall be 16 byte aligned for YUV420" hexmask.long 0x04 4.--31. 1. "OFST,Offset in words of 16 bytes" line.long 0x08 "CAL_RD_DMA_XSIZE,Number of bytes to read per line" hexmask.long.word 0x08 19.--31. 1. "XSIZE,Words of 64-bits to read per line" line.long 0x0C "CAL_RD_DMA_YSIZE,Number of lines to" hexmask.long.word 0x0C 16.--29. 1. "YSIZE," group.long 0x120++0x07 line.long 0x00 "CAL_VPORT_CTRL1,Video port control register" bitfld.long 0x00 31. "WIDTH,Video port width - ONE" "WIDTH_0,WIDTH_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,Video port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_VPORT_CTRL2,Video port control register" hexmask.long.word 0x04 18.--31. 1. "RDY_THR,Data shall be send to the video port after frame start only when (RDY_THR+1)*4 pixels are ready and the 4 PCLK cycles (require before each frame start) have been sent" bitfld.long 0x04 17. "FSM_RESET,Forces a reset of the video port FSM - NOEFFECT" "FSM_RESET_0_w,FSM_RESET_1_w" bitfld.long 0x04 16. "FS_RESETS,Controls the behavior of the timing generator when a data tagged as PIX_DAT_FS is received" "FS_RESETS_0,FS_RESETS_1" newline bitfld.long 0x04 15. "FREERUNNING,Controls PCLK generation during IDLE" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 0.--4. "CPORT,Cport ID Valid range=0..(CAL_HL_HWINFO.NCPORT-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "Channel_0" group.long 0x304++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_0,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x310++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x308++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x330++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_0,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_0,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_0,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_0,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_0,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_0,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_0,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_0,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x300++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_0,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x30C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_0,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x350++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_0,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_0,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_0,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_0,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_0,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_0,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_0,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_0,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x314++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_0,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x328++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x2C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x28++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x20++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC0++0x03 line.long 0x00 "CAL_PIX_PROC_i_0,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x204++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_0,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x200++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_0,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x208++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_0,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_0,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "Channel_1" group.long 0x384++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_1,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x390++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x388++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x3B0++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_1,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_1,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_1,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_1,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_1,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_1,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_1,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_1,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x380++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_1,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x38C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_1,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x3D0++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_1,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_1,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_1,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_1,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_1,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_1,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_1,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_1,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x394++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_1,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3A8++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x38++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x30++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC4++0x03 line.long 0x00 "CAL_PIX_PROC_i_1,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x214++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_1,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x210++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_1,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x218++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_1,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_1,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_2" group.long 0x4C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x48++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x40++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC8++0x03 line.long 0x00 "CAL_PIX_PROC_i_2,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x224++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_2,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x220++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_2,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x228++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_2,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_2,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_3" group.long 0x5C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x58++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x50++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_3,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_3,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xCC++0x03 line.long 0x00 "CAL_PIX_PROC_i_3,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x234++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_3,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x230++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_3,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x238++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_3,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_3,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_4" group.long 0x6C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x68++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x60++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x244++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_4,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x240++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_4,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x248++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_4,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_4,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_5" group.long 0x7C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x78++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x70++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x254++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_5,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x250++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_5,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x258++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_5,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_5,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_6" group.long 0x8C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_6,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x88++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_6,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x80++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_6,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x264++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_6,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x260++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_6,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x268++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_6,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_6,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_7" group.long 0x9C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_7,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x98++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_7,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x90++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_7,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_7,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x274++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_7,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x270++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_7,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x278++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_7,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_7,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_8" group.long 0xAC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_8,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_8,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_8,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_8,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end tree "IRQ_Line_9" group.long 0xBC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_9,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_9,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_9,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_9,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end width 0x0B tree.end tree "CAL_B" base ad:0x52013000 group.long 0x130++0x07 line.long 0x00 "CAL_BYS_CTRL1,BYS port control register" bitfld.long 0x00 31. "BYSINEN,Enable/disable the BYS input port Note: the BYS output port is disabled by setting PCLK=0 - DIS" "BYSINEN_0,BYSINEN_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,BYSout port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_BYS_CTRL2,BYS port control register" bitfld.long 0x04 11. "FREERUNNING,Controls PCLK generation when the BYSout state machine is in the IDLE state - NO" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 10. "DUPLICATEDDATA,Control if data sent to the BYS output port should also be send to the DPCM encoder - NO" "DUPLICATEDDATA_0,DUPLICATEDDATA_1" bitfld.long 0x04 5.--9. "CPORTOUT,BYS output port processes data received with the CPORT ID defined in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "CPORTIN,Cport ID used for data received from the BYSin port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x07 line.long 0x00 "CAL_CTRL,Global control register" hexmask.long.byte 0x00 24.--31. 1. "MFLAGH,refer to real time traffic section of the spec" bitfld.long 0x00 22. "RD_DMA_STALL,Controls if the pixel stream from the RD DMA's FIFO to the internal pipeline shall be stalled when MFlag/=0" "RD_DMA_STALL_0,RD_DMA_STALL_1" bitfld.long 0x00 21. "PWRSCPCLK,Controls autogating of the PWRSCP clock - AUTO" "PWRSCPCLK_0,PWRSCPCLK_1" newline hexmask.long.byte 0x00 13.--20. 1. "MFLAGL,refer to real time traffic section of the spec" bitfld.long 0x00 7.--12. "LL_FORCE_STATE,Forces the state of the CSI-3 low level protocol state machine" "the next OCPI transaction for this CPORT will..,the next OCPI transaction for this CPORT will..,?..." bitfld.long 0x00 5.--6. "BURSTSIZE,Maximum allowed burst size for the write DMA" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 1.--4. "TAGCNT,Maximum number of outstanding OCP transactions = TAGCNT+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "POSTED_WRITES,- NONPOSTED" "POSTED_WRITES_0,POSTED_WRITES_1" line.long 0x04 "CAL_CTRL1,CAL global control register" bitfld.long 0x04 4.--5. "INTERLEAVE23,Controls stream interleaving Context #2 and #3 - DISABLED" "INTERLEAVE23_0,INTERLEAVE23_1,INTERLEAVE23_2,INTERLEAVE23_3" bitfld.long 0x04 2.--3. "INTERLEAVE01,Controls stream interleaving Context #0 and #1 - DISABLED" "INTERLEAVE01_0,INTERLEAVE01_1,INTERLEAVE01_2,INTERLEAVE01_3" bitfld.long 0x04 0.--1. "PPI_GROUPING,Controls PPI grouping - DISABLED" "PPI_GROUPING_0,PPI_GROUPING_1,PPI_GROUPING_2,PPI_GROUPING_3" rgroup.long 0x04++0x03 line.long 0x00 "CAL_HL_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x00 30.--31. "NPPI_CONTEXTS1,Number of contexts for PPI interface #1 - RESERVED" "NPPI_CONTEXTS1_0_r,NPPI_CONTEXTS1_1_r,NPPI_CONTEXTS1_2_r,NPPI_CONTEXTS1_3_r" bitfld.long 0x00 28.--29. "NPPI_CONTEXTS0,Number of contexts for PPI interface #0 - RESERVED" "NPPI_CONTEXTS0_0_r,NPPI_CONTEXTS0_1_r,NPPI_CONTEXTS0_2_r,NPPI_CONTEXTS0_3_r" bitfld.long 0x00 23.--27. "NCPORT,Number of supported CPORTs (including CPORT #0) minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 19.--22. "VFIFO,Video port FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--18. "WCTX,Number of implemented DMA write contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--12. "PCTX,Number of implemented pixel processing contexts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "RFIFO,Read FIFO size 2^RFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "WFIFO,Write FIFO size 2^WFIFO words of 16 bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CAL_HL_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" rgroup.long 0x00++0x03 line.long 0x00 "CAL_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "CAL_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration - FORCE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset - NOACTION" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x108++0x03 line.long 0x00 "CAL_LINE_NUMBER_EVT,Controls generation of the line number event" hexmask.long.word 0x00 16.--29. 1. "LINE," bitfld.long 0x00 0.--4. "CPORT,CPort ID to monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x140++0x03 line.long 0x00 "CAL_RD_DMA_CTRL,Read DMA control register" hexmask.long.tbyte 0x00 15.--31. 1. "PCLK,Controls the data rate at which data is read from the read DMA FIFO and sent to the internal processing pipeline" bitfld.long 0x00 11.--14. "OCP_TAG_CNT,Maximum allowed number of outstanding OCP read requests minus 1 (i.e. 0xF meand up to 16 outstanding requests)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 2.--10. 1. "BW_LIMITER,Defines a minimum cycle count between to consecutive read requests issued by the RD DMA" newline bitfld.long 0x00 1. "INIT,Enable reading of DPCM decoder initialization data from SDRAM - DIS" "INIT_0,INIT_1" bitfld.long 0x00 0. "GO,Start data read from memory" "GO_0_r,GO_1_r" group.long 0x16C++0x03 line.long 0x00 "CAL_RD_DMA_CTRL2,Read DMA control register" hexmask.long.word 0x00 16.--29. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 6. "BYSOUT_LE_WAIT,Controls the behavior of the RD DMA when the line end is reached" "BYSOUT_LE_WAIT_0,BYSOUT_LE_WAIT_1" bitfld.long 0x00 4.--5. "RD_PATTERN,Data read pattern - LINEAR" "RD_PATTERN_0,RD_PATTERN_1,RD_PATTERN_2,RD_PATTERN_3" newline bitfld.long 0x00 3. "ICM_CSTART,Enables monitoring of the ICM_CSTART signal - DIS" "ICM_CSTART_0,ICM_CSTART_1" bitfld.long 0x00 0.--2. "CIRC_MODE,Circular mode control - ONE" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3,CIRC_MODE_4,CIRC_MODE_5,?,?" group.long 0x154++0x03 line.long 0x00 "CAL_RD_DMA_INIT_ADDR,Read address" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" group.long 0x168++0x03 line.long 0x00 "CAL_RD_DMA_INIT_OFST,Byte offset between two consecutive line starts" hexmask.long 0x00 3.--31. 1. "OFST,Offset in words of 8 bytes" group.long 0x144++0x0F line.long 0x00 "CAL_RD_DMA_PIX_ADDR,Byte address of the top left corner of the buffer to read in system memory" hexmask.long 0x00 3.--31. 1. "ADDR,Address in words of 8 bytes" line.long 0x04 "CAL_RD_DMA_PIX_OFST,Byte offset between two consecutive line starts Shall be 16 byte aligned for YUV420" hexmask.long 0x04 4.--31. 1. "OFST,Offset in words of 16 bytes" line.long 0x08 "CAL_RD_DMA_XSIZE,Number of bytes to read per line" hexmask.long.word 0x08 19.--31. 1. "XSIZE,Words of 64-bits to read per line" line.long 0x0C "CAL_RD_DMA_YSIZE,Number of lines to" hexmask.long.word 0x0C 16.--29. 1. "YSIZE," group.long 0x120++0x07 line.long 0x00 "CAL_VPORT_CTRL1,Video port control register" bitfld.long 0x00 31. "WIDTH,Video port width - ONE" "WIDTH_0,WIDTH_1" bitfld.long 0x00 25.--30. "YBLK,Vertical blanking = YBLK lines Valid range : 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 17.--24. 1. "XBLK,Horizontal blanking = 8*XBLK cycles Valid range = 0..2040 cycles" newline hexmask.long.tbyte 0x00 0.--16. 1. "PCLK,Video port pixel clock = FCLK * PCLK / 2^16 Valid range: 0" line.long 0x04 "CAL_VPORT_CTRL2,Video port control register" hexmask.long.word 0x04 18.--31. 1. "RDY_THR,Data shall be send to the video port after frame start only when (RDY_THR+1)*4 pixels are ready and the 4 PCLK cycles (require before each frame start) have been sent" bitfld.long 0x04 17. "FSM_RESET,Forces a reset of the video port FSM - NOEFFECT" "FSM_RESET_0_w,FSM_RESET_1_w" bitfld.long 0x04 16. "FS_RESETS,Controls the behavior of the timing generator when a data tagged as PIX_DAT_FS is received" "FS_RESETS_0,FS_RESETS_1" newline bitfld.long 0x04 15. "FREERUNNING,Controls PCLK generation during IDLE" "FREERUNNING_0,FREERUNNING_1" bitfld.long 0x04 0.--4. "CPORT,Cport ID Valid range=0..(CAL_HL_HWINFO.NCPORT-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree "Channel_0" group.long 0x304++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_0,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x310++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x308++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x330++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_0,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_0,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_0,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_0,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_0,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_0,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_0,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_0,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x300++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_0,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x30C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_0,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x350++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_0,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_0,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_0,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_0,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_0,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_0,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_0,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_0,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x314++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_0,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_0,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x328++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_0,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x2C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x28++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x20++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC0++0x03 line.long 0x00 "CAL_PIX_PROC_i_0,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x204++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_0,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x200++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_0,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x208++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_0,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_0,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "Channel_1" group.long 0x384++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_CFG_l_1,COMPLEXIO CONFIGURATION REGISTER This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addition to the.." bitfld.long 0x00 30. "RESET_CTRL,Controls the reset of the complex IO - RESET" "RESET_CTRL_0,RESET_CTRL_1" rbitfld.long 0x00 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io - RESETCOMPLETED" "RESET_DONE_0_r,RESET_DONE_1_r" newline bitfld.long 0x00 27.--28. "PWR_CMD,Command for power control of the complex io - STATE_OFF" "PWR_CMD_0,PWR_CMD_1,PWR_CMD_2,?" rbitfld.long 0x00 25.--26. "PWR_STATUS,Status of the power control of the complex io - STATE_ULP" "PWR_STATUS_0_r,PWR_STATUS_1_r,PWR_STATUS_2_r,?" newline bitfld.long 0x00 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO - DISABLE" "PWR_AUTO_0,PWR_AUTO_1" bitfld.long 0x00 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "DATA4_POL_0,DATA4_POL_1" newline bitfld.long 0x00 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "DATA4_POSITION_0,DATA4_POSITION_1,DATA4_POSITION_2,DATA4_POSITION_3,DATA4_POSITION_4,DATA4_POSITION_5,?,?" bitfld.long 0x00 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "DATA3_POL_0,DATA3_POL_1" newline bitfld.long 0x00 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "DATA3_POSITION_0,DATA3_POSITION_1,DATA3_POSITION_2,DATA3_POSITION_3,DATA3_POSITION_4,DATA3_POSITION_5,?,?" bitfld.long 0x00 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "DATA2_POL_0,DATA2_POL_1" newline bitfld.long 0x00 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "DATA2_POSITION_0,DATA2_POSITION_1,DATA2_POSITION_2,DATA2_POSITION_3,DATA2_POSITION_4,DATA2_POSITION_5,?,?" bitfld.long 0x00 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "DATA1_POL_0,DATA1_POL_1" newline bitfld.long 0x00 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,DATA1_POSITION_1,DATA1_POSITION_2,DATA1_POSITION_3,DATA1_POSITION_4,DATA1_POSITION_5,?,?" bitfld.long 0x00 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "CLOCK_POL_0,CLOCK_POL_1" newline bitfld.long 0x00 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,CLOCK_POSITION_1,CLOCK_POSITION_2,CLOCK_POSITION_3,CLOCK_POSITION_4,CLOCK_POSITION_5,?,?" group.long 0x390++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - DISABLE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - DISABLE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - DISABLE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - DISABLE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - DISABLE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - DISABLE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - DISABLE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - DISABLE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - DISABLE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - DISABLE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - DISABLE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - DISABLE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - DISABLE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - DISABLE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - DISABLE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - DISABLE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - DISABLE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - DISABLE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - DISABLE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - DISABLE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - DISABLE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - DISABLE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - DISABLE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - DISABLE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - DISABLE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - DISABLE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - DISABLE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x388++0x03 line.long 0x00 "CAL_CSI2_COMPLEXIO_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - All errors from complex IO #1" bitfld.long 0x00 30. "ECC_NO_CORRECTION,ECC has not been used to correct the header because there is more than 1-bit error (short and long packets)" "ECC_NO_CORRECTION_0,ECC_NO_CORRECTION_1" bitfld.long 0x00 28. "SHORT_PACKET,Short packet (other than FS FE LS LE) received" "SHORT_PACKET_0,SHORT_PACKET_1" newline bitfld.long 0x00 27. "FIFO_OVR,CSI-2 low level protocol interface FIFO overflow - FALSE" "FIFO_OVR_0,FIFO_OVR_1" bitfld.long 0x00 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM - FALSE" "STATEALLULPMEXIT_0,STATEALLULPMEXIT_1" newline bitfld.long 0x00 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "STATEALLULPMENTER_0,STATEALLULPMENTER_1" bitfld.long 0x00 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode - FALSE" "STATEULPM5_0,STATEULPM5_1" newline bitfld.long 0x00 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode - FALSE" "STATEULPM4_0,STATEULPM4_1" bitfld.long 0x00 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode - FALSE" "STATEULPM3_0,STATEULPM3_1" newline bitfld.long 0x00 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode - FALSE" "STATEULPM2_0,STATEULPM2_1" bitfld.long 0x00 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode - FALSE" "STATEULPM1_0,STATEULPM1_1" newline bitfld.long 0x00 19. "ERRCONTROL5,Control error for lane #5 - FALSE" "ERRCONTROL5_0,ERRCONTROL5_1" bitfld.long 0x00 18. "ERRCONTROL4,Control error for lane #4 - FALSE" "ERRCONTROL4_0,ERRCONTROL4_1" newline bitfld.long 0x00 17. "ERRCONTROL3,Control error for lane #3 - FALSE" "ERRCONTROL3_0,ERRCONTROL3_1" bitfld.long 0x00 16. "ERRCONTROL2,Control error for lane #2 - FALSE" "ERRCONTROL2_0,ERRCONTROL2_1" newline bitfld.long 0x00 15. "ERRCONTROL1,Control error for lane #1 - FALSE" "ERRCONTROL1_0,ERRCONTROL1_1" bitfld.long 0x00 14. "ERRESC5,Escape entry error for lane #5 - FALSE" "ERRESC5_0,ERRESC5_1" newline bitfld.long 0x00 13. "ERRESC4,Escape entry error for lane #4 - FALSE" "ERRESC4_0,ERRESC4_1" bitfld.long 0x00 12. "ERRESC3,Escape entry error for lane #3 - FALSE" "ERRESC3_0,ERRESC3_1" newline bitfld.long 0x00 11. "ERRESC2,Escape entry error for lane #2 - FALSE" "ERRESC2_0,ERRESC2_1" bitfld.long 0x00 10. "ERRESC1,Escape entry error for lane #1 - FALSE" "ERRESC1_0,ERRESC1_1" newline bitfld.long 0x00 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 - FALSE" "ERRSOTSYNCHS5_0,ERRSOTSYNCHS5_1" bitfld.long 0x00 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 - FALSE" "ERRSOTSYNCHS4_0,ERRSOTSYNCHS4_1" newline bitfld.long 0x00 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 - FALSE" "ERRSOTSYNCHS3_0,ERRSOTSYNCHS3_1" bitfld.long 0x00 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 - FALSE" "ERRSOTSYNCHS2_0,ERRSOTSYNCHS2_1" newline bitfld.long 0x00 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 - FALSE" "ERRSOTSYNCHS1_0,ERRSOTSYNCHS1_1" bitfld.long 0x00 4. "ERRSOTHS5,Start of transmission error for lane #5 - FALSE" "ERRSOTHS5_0,ERRSOTHS5_1" newline bitfld.long 0x00 3. "ERRSOTHS4,Start of transmission error for lane #4 - FALSE" "ERRSOTHS4_0,ERRSOTHS4_1" bitfld.long 0x00 2. "ERRSOTHS3,Start of transmission error for lane #3 - FALSE" "ERRSOTHS3_0,ERRSOTHS3_1" newline bitfld.long 0x00 1. "ERRSOTHS2,Start of transmission error for lane #2 - FALSE" "ERRSOTHS2_0,ERRSOTHS2_1" bitfld.long 0x00 0. "ERRSOTHS1,Start of transmission error for lane #1 - FALSE" "ERRSOTHS1_0,ERRSOTHS1_1" group.long 0x3B0++0x1F line.long 0x00 "CAL_CSI2_CTX0_l_1,Context control" hexmask.long.word 0x00 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x00 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x00 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x00 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x00 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x04 "CAL_CSI2_CTX1_l_1,Context control" hexmask.long.word 0x04 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x04 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x04 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x04 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x04 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x08 "CAL_CSI2_CTX2_l_1,Context control" hexmask.long.word 0x08 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x08 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x08 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x08 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x08 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x0C "CAL_CSI2_CTX3_l_1,Context control" hexmask.long.word 0x0C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x0C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x0C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x0C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x0C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x10 "CAL_CSI2_CTX4_l_1,Context control" hexmask.long.word 0x10 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x10 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x10 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x10 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x10 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x14 "CAL_CSI2_CTX5_l_1,Context control" hexmask.long.word 0x14 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x14 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x14 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x14 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x14 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x18 "CAL_CSI2_CTX6_l_1,Context control" hexmask.long.word 0x18 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x18 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x18 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x18 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x18 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" line.long 0x1C "CAL_CSI2_CTX7_l_1,Context control" hexmask.long.word 0x1C 16.--29. 1. "LINES,Number of expected lines" bitfld.long 0x1C 14. "PACK_MODE,Controls the data packing" "PACK_MODE_0,PACK_MODE_1" newline bitfld.long 0x1C 13. "ATT,Selects which tags to use for the CAL internal pipeline - PIX" "ATT_0,ATT_1" bitfld.long 0x1C 8.--12. "CPORT,CAL internal CPort ID to use for Data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--7. "VC,Virtual channel" "0,1,2,3" bitfld.long 0x1C 0.--5. "DT,DT value received over CSI-2 to use for data" "context is disabled (don't receive data),filter is disabled (accept any DT) 0x02 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,reserved 0x10 ~,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,receive data with Data Type field = DT" group.long 0x380++0x03 line.long 0x00 "CAL_CSI2_PPI_CTRL_l_1,Controls the low level CSI-2 protocol interface (PPI)" bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "FRAME_0,FRAME_1" bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "ECC_EN_0,ECC_EN_1" newline bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "IF_EN_0,IF_EN_1" rgroup.long 0x38C++0x03 line.long 0x00 "CAL_CSI2_SHORT_PACKET_l_1,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F" hexmask.long.tbyte 0x00 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD" rgroup.long 0x3D0++0x1F line.long 0x00 "CAL_CSI2_STATUS0_l_1,Context status register" hexmask.long.word 0x00 0.--15. 1. "FRAME,Frame number" line.long 0x04 "CAL_CSI2_STATUS1_l_1,Context status register" hexmask.long.word 0x04 0.--15. 1. "FRAME,Frame number" line.long 0x08 "CAL_CSI2_STATUS2_l_1,Context status register" hexmask.long.word 0x08 0.--15. 1. "FRAME,Frame number" line.long 0x0C "CAL_CSI2_STATUS3_l_1,Context status register" hexmask.long.word 0x0C 0.--15. 1. "FRAME,Frame number" line.long 0x10 "CAL_CSI2_STATUS4_l_1,Context status register" hexmask.long.word 0x10 0.--15. 1. "FRAME,Frame number" line.long 0x14 "CAL_CSI2_STATUS5_l_1,Context status register" hexmask.long.word 0x14 0.--15. 1. "FRAME,Frame number" line.long 0x18 "CAL_CSI2_STATUS6_l_1,Context status register" hexmask.long.word 0x18 0.--15. 1. "FRAME,Frame number" line.long 0x1C "CAL_CSI2_STATUS7_l_1,Context status register" hexmask.long.word 0x1C 0.--15. 1. "FRAME,Frame number" group.long 0x394++0x07 line.long 0x00 "CAL_CSI2_TIMING_l_1,TIMING REGISTER This register shall not be =modified when .IF_EN=1 It is used to indicate the number of functional clock cycles for the Stop State monitoring" bitfld.long 0x00 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal - DEASSERTION" "FORCE_RX_MODE_IO1_0,FORCE_RX_MODE_IO1_1" bitfld.long 0x00 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X16_IO1_0,STOP_STATE_X16_IO1_1" newline bitfld.long 0x00 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field - DISABLE" "STOP_STATE_X4_IO1_0,STOP_STATE_X4_IO1_1" hexmask.long.word 0x00 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring" line.long 0x04 "CAL_CSI2_VC_IRQENABLE_l_1,INTERRUPT ENABLE REGISTER - Virtual channels" bitfld.long 0x04 29. "ECC_CORRECTION0_IRQ_3,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_3_0,ECC_CORRECTION0_IRQ_3_1" bitfld.long 0x04 28. "CS_IRQ_3,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x04 27. "LE_IRQ_3,Line end sync code detection" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x04 26. "LS_IRQ_3,Line start sync code detection" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x04 25. "FE_IRQ_3,Frame end sync code detection" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x04 24. "FS_IRQ_3,Frame start sync code detection" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x04 21. "ECC_CORRECTION0_IRQ_2,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_2_0,ECC_CORRECTION0_IRQ_2_1" bitfld.long 0x04 20. "CS_IRQ_2,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x04 19. "LE_IRQ_2,Line end sync code detection" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x04 18. "LS_IRQ_2,Line start sync code detection" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x04 17. "FE_IRQ_2,Frame end sync code detection" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x04 16. "FS_IRQ_2,Frame start sync code detection" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x04 13. "ECC_CORRECTION0_IRQ_1,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_1_0,ECC_CORRECTION0_IRQ_1_1" bitfld.long 0x04 12. "CS_IRQ_1,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x04 11. "LE_IRQ_1,Line end sync code detection" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x04 10. "LS_IRQ_1,Line start sync code detection" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x04 9. "FE_IRQ_1,Frame end sync code detection" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x04 8. "FS_IRQ_1,Frame start sync code detection" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x04 5. "ECC_CORRECTION0_IRQ_0,ECC has been used to correct the only 1-bit error - DISABLE" "ECC_CORRECTION0_IRQ_0_0,ECC_CORRECTION0_IRQ_0_1" bitfld.long 0x04 4. "CS_IRQ_0,Check-Sum of the payload mismatch detection - DISABLE" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x04 3. "LE_IRQ_0,Line end sync code detection" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x04 2. "LS_IRQ_0,Line start sync code detection" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x04 1. "FE_IRQ_0,Frame end sync code detection" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x04 0. "FS_IRQ_0,Frame start sync code detection" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3A8++0x03 line.long 0x00 "CAL_CSI2_VC_IRQSTATUS_l_1,INTERRUPT STATUS REGISTER - Virtual channels This register regroups all the events related to Context" bitfld.long 0x00 29. "ECC_CORRECTION_IRQ_3,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_3_0,ECC_CORRECTION_IRQ_3_1" bitfld.long 0x00 28. "CS_IRQ_3,Check-Sum mismatch status" "CS_IRQ_3_0,CS_IRQ_3_1" newline bitfld.long 0x00 27. "LE_IRQ_3,Line end sync code detection status" "LE_IRQ_3_0,LE_IRQ_3_1" bitfld.long 0x00 26. "LS_IRQ_3,Line start sync code detection status" "LS_IRQ_3_0,LS_IRQ_3_1" newline bitfld.long 0x00 25. "FE_IRQ_3,Frame end sync code detection status" "FE_IRQ_3_0,FE_IRQ_3_1" bitfld.long 0x00 24. "FS_IRQ_3,Frame start sync code detection status" "FS_IRQ_3_0,FS_IRQ_3_1" newline bitfld.long 0x00 21. "ECC_CORRECTION_IRQ_2,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_2_0,ECC_CORRECTION_IRQ_2_1" bitfld.long 0x00 20. "CS_IRQ_2,Check-Sum mismatch status" "CS_IRQ_2_0,CS_IRQ_2_1" newline bitfld.long 0x00 19. "LE_IRQ_2,Line end sync code detection status" "LE_IRQ_2_0,LE_IRQ_2_1" bitfld.long 0x00 18. "LS_IRQ_2,Line start sync code detection status" "LS_IRQ_2_0,LS_IRQ_2_1" newline bitfld.long 0x00 17. "FE_IRQ_2,Frame end sync code detection status" "FE_IRQ_2_0,FE_IRQ_2_1" bitfld.long 0x00 16. "FS_IRQ_2,Frame start sync code detection status" "FS_IRQ_2_0,FS_IRQ_2_1" newline bitfld.long 0x00 13. "ECC_CORRECTION_IRQ_1,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_1_0,ECC_CORRECTION_IRQ_1_1" bitfld.long 0x00 12. "CS_IRQ_1,Check-Sum mismatch status" "CS_IRQ_1_0,CS_IRQ_1_1" newline bitfld.long 0x00 11. "LE_IRQ_1,Line end sync code detection status" "LE_IRQ_1_0,LE_IRQ_1_1" bitfld.long 0x00 10. "LS_IRQ_1,Line start sync code detection status" "LS_IRQ_1_0,LS_IRQ_1_1" newline bitfld.long 0x00 9. "FE_IRQ_1,Frame end sync code detection status" "FE_IRQ_1_0,FE_IRQ_1_1" bitfld.long 0x00 8. "FS_IRQ_1,Frame start sync code detection status" "FS_IRQ_1_0,FS_IRQ_1_1" newline bitfld.long 0x00 5. "ECC_CORRECTION_IRQ_0,ECC has been used to do the correction of the only 1-bit error status - FALSE" "ECC_CORRECTION_IRQ_0_0,ECC_CORRECTION_IRQ_0_1" bitfld.long 0x00 4. "CS_IRQ_0,Check-Sum mismatch status" "CS_IRQ_0_0,CS_IRQ_0_1" newline bitfld.long 0x00 3. "LE_IRQ_0,Line end sync code detection status" "LE_IRQ_0_0,LE_IRQ_0_1" bitfld.long 0x00 2. "LS_IRQ_0,Line start sync code detection status" "LS_IRQ_0_0,LS_IRQ_0_1" newline bitfld.long 0x00 1. "FE_IRQ_0,Frame end sync code detection status" "FE_IRQ_0_0,FE_IRQ_0_1" bitfld.long 0x00 0. "FS_IRQ_0,Frame start sync code detection status" "FS_IRQ_0_0,FS_IRQ_0_1" group.long 0x3C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x38++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x30++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" newline bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" newline bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" newline bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" newline bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" newline bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" newline bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" newline bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC4++0x03 line.long 0x00 "CAL_PIX_PROC_i_1,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" newline bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x214++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_1,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x210++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_1,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" newline bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" newline bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x218++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_1,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" newline hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_1,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_2" group.long 0x4C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x48++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x40++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_2,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_2,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xC8++0x03 line.long 0x00 "CAL_PIX_PROC_i_2,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x224++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_2,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x220++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_2,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x228++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_2,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_2,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_3" group.long 0x5C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x58++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x50++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_3,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_3,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0xCC++0x03 line.long 0x00 "CAL_PIX_PROC_i_3,Pixel processing control" bitfld.long 0x00 19.--23. "CPORT,CPort ID to process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--18. "PACK,Control pixel packing - ARGB" "PACK_0,?,PACK_2,PACK_3,PACK_4,PACK_5,PACK_6,?" bitfld.long 0x00 11.--15. "DPCME,DPCM encoder - DPCM_16_8_16_1" "DPCME_0,?,DPCME_2,?,?,?,?,?,DPCME_8,?,?,?,?,?,DPCME_14,?,DPCME_16,?,DPCME_18,?,DPCME_20,?,DPCME_22,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 5.--9. "DPCMD,DPCM Decoder - DPCM_16_8_16_1" "DPCMD_0,?,DPCMD_2,?,DPCMD_4,DPCMD_5,DPCMD_6,DPCMD_7,DPCMD_8,?,DPCMD_10,?,DPCMD_12,?,DPCMD_14,?,DPCMD_16,?,DPCMD_18,?,DPCMD_20,?,DPCMD_22,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 1.--4. "EXTRACT,Control pixel extraction from the byte stream - B12_MIPI" "EXTRACT_0,EXTRACT_1,EXTRACT_2,EXTRACT_3,EXTRACT_4,EXTRACT_5,EXTRACT_6,EXTRACT_7,EXTRACT_8,EXTRACT_9,EXTRACT_10,?,?,?,?,?" bitfld.long 0x00 0. "EN,Enable the pixel processing context - DIS" "EN_0,EN_1" group.long 0x234++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_3,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x230++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_3,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x238++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_3,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_3,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_4" group.long 0x6C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x68++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x60++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x244++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_4,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x240++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_4,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x248++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_4,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_4,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_5" group.long 0x7C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x78++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x70++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x254++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_5,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x250++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_5,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x258++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_5,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_5,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_6" group.long 0x8C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_6,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x88++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_6,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x80++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_6,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x264++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_6,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x260++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_6,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x268++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_6,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_6,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_7" group.long 0x9C++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_7,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x98++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_7,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0x90++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_7,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_7,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" newline bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" newline bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" newline bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" newline bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" newline bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" newline bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" group.long 0x274++0x03 line.long 0x00 "CAL_WR_DMA_ADDR_k_7,Byte address of the top left corner of the buffer to write in system memory" hexmask.long 0x00 4.--31. 1. "ADDR,Destination address in words of 16 bytes" group.long 0x270++0x03 line.long 0x00 "CAL_WR_DMA_CTRL_k_7,Write DMA control register" hexmask.long.word 0x00 18.--31. 1. "YSIZE,Maximum number of lines the WR DMA can write to memory" bitfld.long 0x00 14. "STALL_RD_DMA,Controls if a the RD DMA shall be stalled when the write context is stalled because it waits for the PSTART pulse" "STALL_RD_DMA_0,STALL_RD_DMA_1" bitfld.long 0x00 9.--13. "CPORT,Cport ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--8. "DTAG,Store data tagged as DTAG - D6" "DTAG_0,DTAG_1,DTAG_2,DTAG_3,DTAG_4,DTAG_5,DTAG_6,DTAG_7" newline bitfld.long 0x00 5. "ICM_PSTART,Enables monitoring of the ICM_PSTART[x] signal - DIS" "ICM_PSTART_0,ICM_PSTART_1" bitfld.long 0x00 3.--4. "WR_PATTERN,Data write pattern" "WR_PATTERN_0,WR_PATTERN_1,WR_PATTERN_2,WR_PATTERN_3" bitfld.long 0x00 0.--2. "MODE,Mode - SHD" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,?,?" group.long 0x278++0x07 line.long 0x00 "CAL_WR_DMA_OFST_k_7,Offset between two consecutive line starts" hexmask.long.byte 0x00 24.--31. 1. "CIRC_SIZE,Circular buffer size minus one" bitfld.long 0x00 22.--23. "CIRC_MODE,Defines the granularity for circular buffer mode" "CIRC_MODE_0,CIRC_MODE_1,CIRC_MODE_2,CIRC_MODE_3" hexmask.long.word 0x00 4.--18. 1. "OFST,S14" line.long 0x04 "CAL_WR_DMA_XSIZE_k_7,Defines the size of a line written to memory" hexmask.long.word 0x04 19.--31. 1. "XSIZE,Words of 64-bits to write per line Valid range = 0 or 1..n" hexmask.long.word 0x04 3.--15. 1. "XSKIP,Words of 64 bits to skip from the line start" tree.end tree "IRQ_Line_8" group.long 0xAC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_8,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_8,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xA0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_8,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_8,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end tree "IRQ_Line_9" group.long 0xBC++0x03 line.long 0x00 "CAL_HL_IRQENABLE_CLR_j_9,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB8++0x03 line.long 0x00 "CAL_HL_IRQENABLE_SET_j_9,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "IRQ31,Check spec for details - NOACTION" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NOACTION" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NOACTION" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NOACTION" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NOACTION" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NOACTION" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NOACTION" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NOACTION" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NOACTION" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NOACTION" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NOACTION" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NOACTION" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NOACTION" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NOACTION" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NOACTION" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NOACTION" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NOACTION" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NOACTION" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NOACTION" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NOACTION" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NOACTION" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NOACTION" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NOACTION" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NOACTION" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NOACTION" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NOACTION" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NOACTION" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NOACTION" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NOACTION" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NOACTION" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NOACTION" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NOACTION" "IRQ0_0_r,IRQ0_1_r" group.long 0xB0++0x07 line.long 0x00 "CAL_HL_IRQSTATUS_RAW_j_9,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x00 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x00 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x00 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x00 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x00 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x00 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x00 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x00 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x00 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x00 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x00 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x00 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x00 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x00 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x00 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x00 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x00 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x00 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x00 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x00 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x00 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x00 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x00 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x00 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x00 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x00 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x00 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x00 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x00 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x00 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x00 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" line.long 0x04 "CAL_HL_IRQSTATUS_j_9,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x04 31. "IRQ31,Check spec for details - NACT" "IRQ31_0_r,IRQ31_1_r" bitfld.long 0x04 30. "IRQ30,Check spec for details - NACT" "IRQ30_0_r,IRQ30_1_r" bitfld.long 0x04 29. "IRQ29,Check spec for details - NACT" "IRQ29_0_r,IRQ29_1_r" bitfld.long 0x04 28. "IRQ28,Check spec for details - NACT" "IRQ28_0_r,IRQ28_1_r" bitfld.long 0x04 27. "IRQ27,Check spec for details - NACT" "IRQ27_0_r,IRQ27_1_r" bitfld.long 0x04 26. "IRQ26,Check spec for details - NACT" "IRQ26_0_r,IRQ26_1_r" bitfld.long 0x04 25. "IRQ25,Check spec for details - NACT" "IRQ25_0_r,IRQ25_1_r" newline bitfld.long 0x04 24. "IRQ24,Check spec for details - NACT" "IRQ24_0_r,IRQ24_1_r" bitfld.long 0x04 23. "IRQ23,Check spec for details - NACT" "IRQ23_0_r,IRQ23_1_r" bitfld.long 0x04 22. "IRQ22,Check spec for details - NACT" "IRQ22_0_r,IRQ22_1_r" bitfld.long 0x04 21. "IRQ21,Check spec for details - NACT" "IRQ21_0_r,IRQ21_1_r" bitfld.long 0x04 20. "IRQ20,Check spec for details - NACT" "IRQ20_0_r,IRQ20_1_r" bitfld.long 0x04 19. "IRQ19,Check spec for details - NACT" "IRQ19_0_r,IRQ19_1_r" bitfld.long 0x04 18. "IRQ18,Check spec for details - NACT" "IRQ18_0_r,IRQ18_1_r" newline bitfld.long 0x04 17. "IRQ17,Check spec for details - NACT" "IRQ17_0_r,IRQ17_1_r" bitfld.long 0x04 16. "IRQ16,Check spec for details - NACT" "IRQ16_0_r,IRQ16_1_r" bitfld.long 0x04 15. "IRQ15,Check spec for details - NACT" "IRQ15_0_r,IRQ15_1_r" bitfld.long 0x04 14. "IRQ14,Check spec for details - NACT" "IRQ14_0_r,IRQ14_1_r" bitfld.long 0x04 13. "IRQ13,Check spec for details - NACT" "IRQ13_0_r,IRQ13_1_r" bitfld.long 0x04 12. "IRQ12,Check spec for details - NACT" "IRQ12_0_r,IRQ12_1_r" bitfld.long 0x04 11. "IRQ11,Check spec for details - NACT" "IRQ11_0_r,IRQ11_1_r" newline bitfld.long 0x04 10. "IRQ10,Check spec for details - NACT" "IRQ10_0_r,IRQ10_1_r" bitfld.long 0x04 9. "IRQ9,Check spec for details - NACT" "IRQ9_0_r,IRQ9_1_r" bitfld.long 0x04 8. "IRQ8,Check spec for details - NACT" "IRQ8_0_r,IRQ8_1_r" bitfld.long 0x04 7. "IRQ7,Check spec for details - NACT" "IRQ7_0_r,IRQ7_1_r" bitfld.long 0x04 6. "IRQ6,Check spec for details - NACT" "IRQ6_0_r,IRQ6_1_r" bitfld.long 0x04 5. "IRQ5,Check spec for details - NACT" "IRQ5_0_r,IRQ5_1_r" bitfld.long 0x04 4. "IRQ4,Check spec for details - NACT" "IRQ4_0_r,IRQ4_1_r" newline bitfld.long 0x04 3. "IRQ3,Check spec for details - NACT" "IRQ3_0_r,IRQ3_1_r" bitfld.long 0x04 2. "IRQ2,Check spec for details - NACT" "IRQ2_0_r,IRQ2_1_r" bitfld.long 0x04 1. "IRQ1,Check spec for details - NACT" "IRQ1_0_r,IRQ1_1_r" bitfld.long 0x04 0. "IRQ0,Check spec for details - NACT" "IRQ0_0_r,IRQ0_1_r" tree.end width 0x0B tree.end tree "CAMERARX_CORE_0" base ad:0x52012800 group.long 0x00++0x0B line.long 0x00 "REG0,First register" bitfld.long 0x00 24. "HSCLOCKCONFIG,Disable clock missing detector" "0,1" hexmask.long.byte 0x00 8.--15. 1. "THS_TERM,THS_TERM timing parameter in multiples of DDR clock frequency" hexmask.long.byte 0x00 0.--7. 1. "THS_SETTLE,THS_SETTLE timing parameter in multiples of DDR clock frequency Effective THS_SETTLE seen on line (starting to look for sync pattern) = synchronizer delay + timer delay + LPRX delay + combinational routing delay - pipeline delay in HS data.." line.long 0x04 "REG1,Second register" bitfld.long 0x04 30.--31. "RESVD_READ_BIT,Reserved bit" "0,1,2,3" rbitfld.long 0x04 28.--29. "RESET_DONE_STATUS,Reset done read bits" "?,?,?,?" rbitfld.long 0x04 25. "CLOCK_MISS_DETECTOR_STATUS,Clock missing detector status" "CLOCK_MISS_DETECTOR_STATUS_0,?" newline hexmask.long.byte 0x04 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.." hexmask.long.byte 0x04 10.--17. 1. "DPHY_HS_SYNC_PATTERN,DPHY mode HS sync pattern in byte order (reverse of received order) See CSI2 PHY Error Signals" bitfld.long 0x04 8.--9. "TCLK_DIV,CTRLCLK_DIV_FACTOR Divide factor for CTRLCLK for CLKMISS detector Programmed value = ceil (15ns/CTRLCLK Period) - 1 Default value: 1 (for 96 MHz) CLKMISS detection time = (5*TCLK_DIV+1)*(CTRLCLK period) < 60ns Note: Only the CTRLCLK.." "0,1,2,3" newline hexmask.long.byte 0x04 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.." line.long 0x08 "REG2,Third register" bitfld.long 0x08 30.--31. "TRIGGER_CMD_RXTRIGESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "'01100010','01011101','00100001','10100000'" bitfld.long 0x08 28.--29. "TRIGGER_CMD_RXTRIGESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "'01011101','00100001','10100000','01100010'" bitfld.long 0x08 26.--27. "TRIGGER_CMD_RXTRIGESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "'00100001','01100010','01100010','01011101'" newline bitfld.long 0x08 24.--25. "TRIGGER_CMD_RXTRIGESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "'10100000','01100010','01011101','00100001'" hexmask.long.tbyte 0x08 0.--23. 1. "CCP2_SYNC_PATTERN,CCP2 mode sync pattern in byte order (reverse of received order) See CSI2 PHY Error Signals" width 0x0B tree.end tree "ISS_TCTRL" base ad:0x520000C0 rgroup.long 0x00++0x0B line.long 0x00 "TCTRL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "TCTRL_SYSCONFIG,OCP-SOCKET SYSTEM CONFIGURATION REGISTER" bitfld.long 0x04 1. "SOFT_RESET,Software reset" "SOFT_RESET_0,SOFT_RESET_1" bitfld.long 0x04 0. "AUTO_IDLE,Internal OCP and functional clock gating strategy - Free" "AUTO_IDLE_0,AUTO_IDLE_1" line.long 0x08 "TCTRL_SYSSTATUS,OCP-SOCKET SYSTEM STATUS REGISTER" bitfld.long 0x08 0. "RESET_DONE,Internal reset monitoring - Completed" "RESET_DONE_0_r,RESET_DONE_1_r" group.long 0x10++0x1B line.long 0x00 "TCTRL_STRB_LENGTH,TIMING CONTROL - STROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal" hexmask.long.tbyte 0x00 0.--23. 1. "LENGTH,Sets the length of the CAM_STROBE signal assertion in cycles of the CNTCLK clock" line.long 0x04 "TCTRL_PSTRB_LENGTH,TIMING CONTROL - PRESTROBE LENGTH REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal" hexmask.long.tbyte 0x04 0.--23. 1. "LENGTH,Sets the length of the CAM_PRESTROBE signal assertion in cycles of the CNTCLK clock" line.long 0x08 "TCTRL_SHUT_LENGTH,TIMING CONTROL - SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the CAM_SHUTTER signal" hexmask.long.tbyte 0x08 0.--23. 1. "LENGTH,Sets the length of the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock" line.long 0x0C "TCTRL_GRESET_LENGTH,TIMING CONTROL - GLOBAL SHUTTER LENGTH REGISTER This register is used by the TIMING CTRL module to generate the CAM_GLOBALRESET signal" hexmask.long.tbyte 0x0C 0.--23. 1. "LENGTH,Sets the length of the CAM_GLOBALRESET signal assertion in cycles of the CNTCLK clock" line.long 0x10 "TCTRL_STRB_DELAY,TIMING CONTROL - STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the STROBE signal" hexmask.long 0x10 0.--24. 1. "DELAY,Sets the delay for the CAM_STROBE signal assertion in cycles of the CNTCLK clock" line.long 0x14 "TCTRL_PSTRB_DELAY,TIMING CONTROL - PRE STROBE DELAY REGISTER This register is used by the TIMING CTRL module to generate the PRESTROBE signal" hexmask.long 0x14 0.--24. 1. "DELAY,Sets the delay for the PRESTROBE signal assertion in cycles of the CNTCLK clock" line.long 0x18 "TCTRL_SHUT_DELAY,TIMING CONTROL - SHUTTER DELAY REGISTER This register is used by the TIMING CTRL module to generate the CAM_SHUTTER signal" hexmask.long 0x18 0.--24. 1. "DELAY,Sets the delay for the CAM_SHUTTER signal assertion in cycles of the CNTCLK clock" group.long 0x30++0x0B line.long 0x00 "TCTRL_CTRL,TIMING CONTROL - CONTROL REGISTER" bitfld.long 0x00 31. "GRESETDIR,Sets the direction of the CAM_GLOBAL_RESET signal" "INPUT - CAM_GLOBALRESET is an input to the..,OUTPUT - CAM_GLOBALRESET is an output of the.." bitfld.long 0x00 30. "GRESETPOL,Sets the polarity of the global reset signal: CAM_GLOBALRESET" "active high,active low" bitfld.long 0x00 29. "GRESETEN,Triggers the generation of the CAM_GLOBALRESET signal" "GRESETEN_0,GRESETEN_1" newline bitfld.long 0x00 27.--28. "INSEL,Sets the mode that will trigger the SHUTTER PRESTROBE and STROBE signals" "INSEL_0,INSEL_1,INSEL_2,INSEL_3" bitfld.long 0x00 26. "STRBPSTRBPOL,Sets the polarity of the strobe and prestrobe signals" "STRBPSTRBPOL_0,STRBPSTRBPOL_1" bitfld.long 0x00 24. "SHUTPOL,Sets the polarity of the mechanical shutter signal: CAM_SHUTTER - High" "SHUTPOL_0,SHUTPOL_1" newline bitfld.long 0x00 23. "STRBEN,Flash strobe signal enable" "STRBEN_0,STRBEN_1" bitfld.long 0x00 22. "PSTRBEN,Flash prestrobe signal enable" "PSTRBEN_0,PSTRBEN_1" bitfld.long 0x00 21. "SHUTEN,Mechanical shutter signal enable" "SHUTEN_0,SHUTEN_1" newline hexmask.long.word 0x00 10.--18. 1. "DIVC,Sets the clock divisor value for the CNTCLK clock generation based on the CLK input clock" line.long 0x04 "TCTRL_PSTRB_REPLAY,TIMING CONTROL - PRESTROBE REPLAY REGISTER This register is used by the TIMING CTRL module to generate the prestrobe signal" hexmask.long.byte 0x04 25.--31. 1. "COUNTER,Sets the number of PRESTROBE pulses after the original pulse" hexmask.long 0x04 0.--24. 1. "DELAY,Sets the delay for the PRESTROBE signal reassertion in cycles of the CNTCLK clock" line.long 0x08 "TCTRL_FRAME,TIMING CONTROL - FRAME REGISTER This register is used by the TIMING CTRL module to generate the SHUTTER. PRESTROBE. and STROBE signals" bitfld.long 0x08 12.--17. "STRB,Frame counter for the STROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 6.--11. "PSTRB,Frame counter for the PRESTROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 0.--5. "SHUT,Frame counter for the SHUTTER signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "LVDSRX" base ad:0x52004000 rgroup.long 0x00++0x03 line.long 0x00 "LVDSRX_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" hgroup.long 0x10++0x03 hide.long 0x00 "LVDSRX_SYSCONFIG,Reserved" group.long 0x14++0x03 line.long 0x00 "LVDSRX_CAMCFG,Camera port enable" bitfld.long 0x00 19. "CAM4TEST,Camera port #4 monitor - DIABLE" "CAM4TEST_0,CAM4TEST_1" bitfld.long 0x00 18. "CAM3TEST,Camera port #3 monitor - DIABLE" "CAM3TEST_0,CAM3TEST_1" newline bitfld.long 0x00 17. "CAM2TEST,Camera port #2 monitor - DIABLE" "CAM2TEST_0,CAM2TEST_1" bitfld.long 0x00 16. "CAM1TEST,Camera port #1 monitor - DIABLE" "CAM1TEST_0,CAM1TEST_1" newline bitfld.long 0x00 3. "CAM4ENA,Camera port #4 control - DIABLE" "CAM4ENA_0,CAM4ENA_1" bitfld.long 0x00 2. "CAM3ENA,Camera port #3 control - DIABLE" "CAM3ENA_0,CAM3ENA_1" newline bitfld.long 0x00 1. "CAM2ENA,Camera port #2 control - DIABLE" "CAM2ENA_0,CAM2ENA_1" bitfld.long 0x00 0. "CAM1ENA,Camera port #1 control - DIABLE" "CAM1ENA_0,CAM1ENA_1" group.long 0x1C++0xD3 line.long 0x00 "LVDSRX_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3,LINE_NUMBER_4,?,?,?" line.long 0x04 "LVDSRX_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x04 9. "CAM1_ERR7,sync detected timeout reached - NOEVENT" "CAM1_ERR7_0,CAM1_ERR7_1" bitfld.long 0x04 8. "CAM1_ERR6,CRC error - NOEVENT" "CAM1_ERR6_0,CAM1_ERR6_1" newline bitfld.long 0x04 7. "CAM1_ERR5,unexpected SOF - NOEVENT" "CAM1_ERR5_0,CAM1_ERR5_1" bitfld.long 0x04 6. "CAM1_ERR4,unexpected SOL - NOEVENT" "CAM1_ERR4_0,CAM1_ERR4_1" newline bitfld.long 0x04 5. "CAM1_ERR3,unexpected EOF - NOEVENT" "CAM1_ERR3_0,CAM1_ERR3_1" bitfld.long 0x04 4. "CAM1_ERR2,unexpected EOL - NOEVENT" "CAM1_ERR2_0,CAM1_ERR2_1" newline bitfld.long 0x04 3. "CAM1_ERR1,unexpected SOV - NOEVENT" "CAM1_ERR1_0,CAM1_ERR1_1" bitfld.long 0x04 2. "CAM1_ERR0,EOX not received - NOEVENT" "CAM1_ERR0_0,CAM1_ERR0_1" newline bitfld.long 0x04 1. "CAM1_EOF,End of frame timing - NOEVENT" "CAM1_EOF_0,CAM1_EOF_1" bitfld.long 0x04 0. "CAM1_SOF,Start of frame timing - NOEVENT" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x08 "LVDSRX_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 9. "CAM1_ERR7,sync detected timeout reached - NOEVENT" "CAM1_ERR7_0,CAM1_ERR7_1" bitfld.long 0x08 8. "CAM1_ERR6,CRC error - NOEVENT" "CAM1_ERR6_0,CAM1_ERR6_1" newline bitfld.long 0x08 7. "CAM1_ERR5,unexpected SOF - NOEVENT" "CAM1_ERR5_0,CAM1_ERR5_1" bitfld.long 0x08 6. "CAM1_ERR4,unexpected SOL - NOEVENT" "CAM1_ERR4_0,CAM1_ERR4_1" newline bitfld.long 0x08 5. "CAM1_ERR3,unexpected EOF - NOEVENT" "CAM1_ERR3_0,CAM1_ERR3_1" bitfld.long 0x08 4. "CAM1_ERR2,unexpected EOL - NOEVENT" "CAM1_ERR2_0,CAM1_ERR2_1" newline bitfld.long 0x08 3. "CAM1_ERR1,unexpected SOV - NOEVENT" "CAM1_ERR1_0,CAM1_ERR1_1" bitfld.long 0x08 2. "CAM1_ERR0,EOX not received - NOEVENT" "CAM1_ERR0_0,CAM1_ERR0_1" newline bitfld.long 0x08 1. "CAM1_EOF,End of frame timing - NOEVENT" "CAM1_EOF_0,CAM1_EOF_1" bitfld.long 0x08 0. "CAM1_SOF,Start of frame timing - NOEVENT" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x0C "LVDSRX_IRQENABLE_SET_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x0C 9. "CAM1_ERR7,sync detected timeout reached - NOACTION" "CAM1_ERR7_0,CAM1_ERR7_1" bitfld.long 0x0C 8. "CAM1_ERR6,CRC error - NOACTION" "CAM1_ERR6_0,CAM1_ERR6_1" newline bitfld.long 0x0C 7. "CAM1_ERR5,unexpected SOF - NOACTION" "CAM1_ERR5_0,CAM1_ERR5_1" bitfld.long 0x0C 6. "CAM1_ERR4,unexpected SOL - NOACTION" "CAM1_ERR4_0,CAM1_ERR4_1" newline bitfld.long 0x0C 5. "CAM1_ERR3,unexpected EOF - NOACTION" "CAM1_ERR3_0,CAM1_ERR3_1" bitfld.long 0x0C 4. "CAM1_ERR2,unexpected EOL - NOACTION" "CAM1_ERR2_0,CAM1_ERR2_1" newline bitfld.long 0x0C 3. "CAM1_ERR1,unexpected SOV - NOACTION" "CAM1_ERR1_0,CAM1_ERR1_1" bitfld.long 0x0C 2. "CAM1_ERR0,EOX not received - NOACTION" "CAM1_ERR0_0,CAM1_ERR0_1" newline bitfld.long 0x0C 1. "CAM1_EOF,End of frame timing - NOACTION" "CAM1_EOF_0,CAM1_EOF_1" bitfld.long 0x0C 0. "CAM1_SOF,Start of frame timing - NOACTION" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x10 "LVDSRX_IRQENABLE_CLR_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x10 9. "CAM1_ERR7,sync detected timeout reached - NOACTION" "CAM1_ERR7_0,CAM1_ERR7_1" bitfld.long 0x10 8. "CAM1_ERR6,CRC error - NOACTION" "CAM1_ERR6_0,CAM1_ERR6_1" newline bitfld.long 0x10 7. "CAM1_ERR5,unexpected SOF - NOACTION" "CAM1_ERR5_0,CAM1_ERR5_1" bitfld.long 0x10 6. "CAM1_ERR4,unexpected SOL - NOACTION" "CAM1_ERR4_0,CAM1_ERR4_1" newline bitfld.long 0x10 5. "CAM1_ERR3,unexpected EOF - NOACTION" "CAM1_ERR3_0,CAM1_ERR3_1" bitfld.long 0x10 4. "CAM1_ERR2,unexpected EOL - NOACTION" "CAM1_ERR2_0,CAM1_ERR2_1" newline bitfld.long 0x10 3. "CAM1_ERR1,unexpected SOV - NOACTION" "CAM1_ERR1_0,CAM1_ERR1_1" bitfld.long 0x10 2. "CAM1_ERR0,EOX not received - NOACTION" "CAM1_ERR0_0,CAM1_ERR0_1" newline bitfld.long 0x10 1. "CAM1_EOF,End of frame timing - NOACTION" "CAM1_EOF_0,CAM1_EOF_1" bitfld.long 0x10 0. "CAM1_SOF,Start of frame timing - NOACTION" "CAM1_SOF_0,CAM1_SOF_1" line.long 0x14 "LVDSRX_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #1" bitfld.long 0x14 9. "CAM2_ERR7,sync detected timeout reached - NOEVENT" "CAM2_ERR7_0,CAM2_ERR7_1" bitfld.long 0x14 8. "CAM2_ERR6,CRC error - NOEVENT" "CAM2_ERR6_0,CAM2_ERR6_1" newline bitfld.long 0x14 7. "CAM2_ERR5,unexpected SOF - NOEVENT" "CAM2_ERR5_0,CAM2_ERR5_1" bitfld.long 0x14 6. "CAM2_ERR4,unexpected SOL - NOEVENT" "CAM2_ERR4_0,CAM2_ERR4_1" newline bitfld.long 0x14 5. "CAM2_ERR3,unexpected EOF - NOEVENT" "CAM2_ERR3_0,CAM2_ERR3_1" bitfld.long 0x14 4. "CAM2_ERR2,unexpected EOL - NOEVENT" "CAM2_ERR2_0,CAM2_ERR2_1" newline bitfld.long 0x14 3. "CAM2_ERR1,unexpected SOV - NOEVENT" "CAM2_ERR1_0,CAM2_ERR1_1" bitfld.long 0x14 2. "CAM2_ERR0,EOX not received - NOEVENT" "CAM2_ERR0_0,CAM2_ERR0_1" newline bitfld.long 0x14 1. "CAM2_EOF,End of frame timing - NOEVENT" "CAM2_EOF_0,CAM2_EOF_1" bitfld.long 0x14 0. "CAM2_SOF,Start of frame timing - NOEVENT" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x18 "LVDSRX_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1" bitfld.long 0x18 9. "CAM2_ERR7,sync detected timeout reached - NOEVENT" "CAM2_ERR7_0,CAM2_ERR7_1" bitfld.long 0x18 8. "CAM2_ERR6,CRC error - NOEVENT" "CAM2_ERR6_0,CAM2_ERR6_1" newline bitfld.long 0x18 7. "CAM2_ERR5,unexpected SOF - NOEVENT" "CAM2_ERR5_0,CAM2_ERR5_1" bitfld.long 0x18 6. "CAM2_ERR4,unexpected SOL - NOEVENT" "CAM2_ERR4_0,CAM2_ERR4_1" newline bitfld.long 0x18 5. "CAM2_ERR3,unexpected EOF - NOEVENT" "CAM2_ERR3_0,CAM2_ERR3_1" bitfld.long 0x18 4. "CAM2_ERR2,unexpected EOL - NOEVENT" "CAM2_ERR2_0,CAM2_ERR2_1" newline bitfld.long 0x18 3. "CAM2_ERR1,unexpected SOV - NOEVENT" "CAM2_ERR1_0,CAM2_ERR1_1" bitfld.long 0x18 2. "CAM2_ERR0,EOX not received - NOEVENT" "CAM2_ERR0_0,CAM2_ERR0_1" newline bitfld.long 0x18 1. "CAM2_EOF,End of frame timing - NOEVENT" "CAM2_EOF_0,CAM2_EOF_1" bitfld.long 0x18 0. "CAM2_SOF,Start of frame timing - NOEVENT" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x1C "LVDSRX_IRQENABLE_SET_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x1C 9. "CAM2_ERR7,sync detected timeout reached - NOACTION" "CAM2_ERR7_0,CAM2_ERR7_1" bitfld.long 0x1C 8. "CAM2_ERR6,CRC error - NOACTION" "CAM2_ERR6_0,CAM2_ERR6_1" newline bitfld.long 0x1C 7. "CAM2_ERR5,unexpected SOF - NOACTION" "CAM2_ERR5_0,CAM2_ERR5_1" bitfld.long 0x1C 6. "CAM2_ERR4,unexpected SOL - NOACTION" "CAM2_ERR4_0,CAM2_ERR4_1" newline bitfld.long 0x1C 5. "CAM2_ERR3,unexpected EOF - NOACTION" "CAM2_ERR3_0,CAM2_ERR3_1" bitfld.long 0x1C 4. "CAM2_ERR2,unexpected EOL - NOACTION" "CAM2_ERR2_0,CAM2_ERR2_1" newline bitfld.long 0x1C 3. "CAM2_ERR1,unexpected SOV - NOACTION" "CAM2_ERR1_0,CAM2_ERR1_1" bitfld.long 0x1C 2. "CAM2_ERR0,EOX not received - NOACTION" "CAM2_ERR0_0,CAM2_ERR0_1" newline bitfld.long 0x1C 1. "CAM2_EOF,End of frame timing - NOACTION" "CAM2_EOF_0,CAM2_EOF_1" bitfld.long 0x1C 0. "CAM2_SOF,Start of frame timing - NOACTION" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x20 "LVDSRX_IRQENABLE_CLR_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x20 9. "CAM2_ERR7,sync detected timeout reached - NOACTION" "CAM2_ERR7_0,CAM2_ERR7_1" bitfld.long 0x20 8. "CAM2_ERR6,CRC error - NOACTION" "CAM2_ERR6_0,CAM2_ERR6_1" newline bitfld.long 0x20 7. "CAM2_ERR5,unexpected SOF - NOACTION" "CAM2_ERR5_0,CAM2_ERR5_1" bitfld.long 0x20 6. "CAM2_ERR4,unexpected SOL - NOACTION" "CAM2_ERR4_0,CAM2_ERR4_1" newline bitfld.long 0x20 5. "CAM2_ERR3,unexpected EOF - NOACTION" "CAM2_ERR3_0,CAM2_ERR3_1" bitfld.long 0x20 4. "CAM2_ERR2,unexpected EOL - NOACTION" "CAM2_ERR2_0,CAM2_ERR2_1" newline bitfld.long 0x20 3. "CAM2_ERR1,unexpected SOV - NOACTION" "CAM2_ERR1_0,CAM2_ERR1_1" bitfld.long 0x20 2. "CAM2_ERR0,EOX not received - NOACTION" "CAM2_ERR0_0,CAM2_ERR0_1" newline bitfld.long 0x20 1. "CAM2_EOF,End of frame timing - NOACTION" "CAM2_EOF_0,CAM2_EOF_1" bitfld.long 0x20 0. "CAM2_SOF,Start of frame timing - NOACTION" "CAM2_SOF_0,CAM2_SOF_1" line.long 0x24 "LVDSRX_IRQSTATUS_RAW2_2,Per-event raw interrupt status vector. line #2" bitfld.long 0x24 9. "CAM3_ERR7,sync detected timeout reached - NOEVENT" "CAM3_ERR7_0,CAM3_ERR7_1" bitfld.long 0x24 8. "CAM3_ERR6,CRC error - NOEVENT" "CAM3_ERR6_0,CAM3_ERR6_1" newline bitfld.long 0x24 7. "CAM3_ERR5,unexpected SOF - NOEVENT" "CAM3_ERR5_0,CAM3_ERR5_1" bitfld.long 0x24 6. "CAM3_ERR4,unexpected SOL - NOEVENT" "CAM3_ERR4_0,CAM3_ERR4_1" newline bitfld.long 0x24 5. "CAM3_ERR3,unexpected EOF - NOEVENT" "CAM3_ERR3_0,CAM3_ERR3_1" bitfld.long 0x24 4. "CAM3_ERR2,unexpected EOL - NOEVENT" "CAM3_ERR2_0,CAM3_ERR2_1" newline bitfld.long 0x24 3. "CAM3_ERR1,unexpected SOV - NOEVENT" "CAM3_ERR1_0,CAM3_ERR1_1" bitfld.long 0x24 2. "CAM3_ERR0,EOX not received - NOEVENT" "CAM3_ERR0_0,CAM3_ERR0_1" newline bitfld.long 0x24 1. "CAM3_EOF,End of frame timing - NOEVENT" "CAM3_EOF_0,CAM3_EOF_1" bitfld.long 0x24 0. "CAM3_SOF,Start of frame timing - NOEVENT" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x28 "LVDSRX_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. line #2" bitfld.long 0x28 9. "CAM3_ERR7,sync detected timeout reached - NOEVENT" "CAM3_ERR7_0,CAM3_ERR7_1" bitfld.long 0x28 8. "CAM3_ERR6,CRC error - NOEVENT" "CAM3_ERR6_0,CAM3_ERR6_1" newline bitfld.long 0x28 7. "CAM3_ERR5,unexpected SOF - NOEVENT" "CAM3_ERR5_0,CAM3_ERR5_1" bitfld.long 0x28 6. "CAM3_ERR4,unexpected SOL - NOEVENT" "CAM3_ERR4_0,CAM3_ERR4_1" newline bitfld.long 0x28 5. "CAM3_ERR3,unexpected EOF - NOEVENT" "CAM3_ERR3_0,CAM3_ERR3_1" bitfld.long 0x28 4. "CAM3_ERR2,unexpected EOL - NOEVENT" "CAM3_ERR2_0,CAM3_ERR2_1" newline bitfld.long 0x28 3. "CAM3_ERR1,unexpected SOV - NOEVENT" "CAM3_ERR1_0,CAM3_ERR1_1" bitfld.long 0x28 2. "CAM3_ERR0,EOX not received - NOEVENT" "CAM3_ERR0_0,CAM3_ERR0_1" newline bitfld.long 0x28 1. "CAM3_EOF,End of frame timing - NOEVENT" "CAM3_EOF_0,CAM3_EOF_1" bitfld.long 0x28 0. "CAM3_SOF,Start of frame timing - NOEVENT" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x2C "LVDSRX_IRQENABLE_SET_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x2C 9. "CAM3_ERR7,sync detected timeout reached - NOACTION" "CAM3_ERR7_0,CAM3_ERR7_1" bitfld.long 0x2C 8. "CAM3_ERR6,CRC error - NOACTION" "CAM3_ERR6_0,CAM3_ERR6_1" newline bitfld.long 0x2C 7. "CAM3_ERR5,unexpected SOF - NOACTION" "CAM3_ERR5_0,CAM3_ERR5_1" bitfld.long 0x2C 6. "CAM3_ERR4,unexpected SOL - NOACTION" "CAM3_ERR4_0,CAM3_ERR4_1" newline bitfld.long 0x2C 5. "CAM3_ERR3,unexpected EOF - NOACTION" "CAM3_ERR3_0,CAM3_ERR3_1" bitfld.long 0x2C 4. "CAM3_ERR2,unexpected EOL - NOACTION" "CAM3_ERR2_0,CAM3_ERR2_1" newline bitfld.long 0x2C 3. "CAM3_ERR1,unexpected SOV - NOACTION" "CAM3_ERR1_0,CAM3_ERR1_1" bitfld.long 0x2C 2. "CAM3_ERR0,EOX not received - NOACTION" "CAM3_ERR0_0,CAM3_ERR0_1" newline bitfld.long 0x2C 1. "CAM3_EOF,End of frame timing - NOEVENT" "CAM3_EOF_0,CAM3_EOF_1" bitfld.long 0x2C 0. "CAM3_SOF,Start of frame timing - NOACTION" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x30 "LVDSRX_IRQENABLE_CLR_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x30 9. "CAM3_ERR7,sync detected timeout reached - NOACTION" "CAM3_ERR7_0,CAM3_ERR7_1" bitfld.long 0x30 8. "CAM3_ERR6,CRC error - NOACTION" "CAM3_ERR6_0,CAM3_ERR6_1" newline bitfld.long 0x30 7. "CAM3_ERR5,unexpected SOF - NOACTION" "CAM3_ERR5_0,CAM3_ERR5_1" bitfld.long 0x30 6. "CAM3_ERR4,unexpected SOL - NOACTION" "CAM3_ERR4_0,CAM3_ERR4_1" newline bitfld.long 0x30 5. "CAM3_ERR3,unexpected EOF - NOACTION" "CAM3_ERR3_0,CAM3_ERR3_1" bitfld.long 0x30 4. "CAM3_ERR2,unexpected EOL - NOACTION" "CAM3_ERR2_0,CAM3_ERR2_1" newline bitfld.long 0x30 3. "CAM3_ERR1,unexpected SOV - NOACTION" "CAM3_ERR1_0,CAM3_ERR1_1" bitfld.long 0x30 2. "CAM3_ERR0,EOX not received - NOACTION" "CAM3_ERR0_0,CAM3_ERR0_1" newline bitfld.long 0x30 1. "CAM3_EOF,End of frame timing - NOEVENT" "CAM3_EOF_0,CAM3_EOF_1" bitfld.long 0x30 0. "CAM3_SOF,Start of frame timing - NOACTION" "CAM3_SOF_0,CAM3_SOF_1" line.long 0x34 "LVDSRX_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line #3" bitfld.long 0x34 9. "CAM4_ERR7,sync detected timeout reached - NOEVENT" "CAM4_ERR7_0,CAM4_ERR7_1" bitfld.long 0x34 8. "CAM4_ERR6,CRC error - NOEVENT" "CAM4_ERR6_0,CAM4_ERR6_1" newline bitfld.long 0x34 7. "CAM4_ERR5,unexpected SOF - NOEVENT" "CAM4_ERR5_0,CAM4_ERR5_1" bitfld.long 0x34 6. "CAM4_ERR4,unexpected SOL - NOEVENT" "CAM4_ERR4_0,CAM4_ERR4_1" newline bitfld.long 0x34 5. "CAM4_ERR3,unexpected EOF - NOEVENT" "CAM4_ERR3_0,CAM4_ERR3_1" bitfld.long 0x34 4. "CAM4_ERR2,unexpected EOL - NOEVENT" "CAM4_ERR2_0,CAM4_ERR2_1" newline bitfld.long 0x34 3. "CAM5_ERR1,unexpected SOV - NOEVENT" "CAM5_ERR1_0,CAM5_ERR1_1" bitfld.long 0x34 2. "CAM4_ERR0,EOX not received - NOEVENT" "CAM4_ERR0_0,CAM4_ERR0_1" newline bitfld.long 0x34 1. "CAM4_EOF,End of frame timing - NOEVENT" "CAM4_EOF_0,CAM4_EOF_1" bitfld.long 0x34 0. "CAM4_SOF,Start of frame timing - NOEVENT" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x38 "LVDSRX_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x38 9. "CAM4_ERR7,sync detected timeout reached - NOEVENT" "CAM4_ERR7_0,CAM4_ERR7_1" bitfld.long 0x38 8. "CAM4_ERR6,CRC error - NOEVENT" "CAM4_ERR6_0,CAM4_ERR6_1" newline bitfld.long 0x38 7. "CAM4_ERR5,unexpected SOF - NOEVENT" "CAM4_ERR5_0,CAM4_ERR5_1" bitfld.long 0x38 6. "CAM4_ERR4,unexpected SOL - NOEVENT" "CAM4_ERR4_0,CAM4_ERR4_1" newline bitfld.long 0x38 5. "CAM4_ERR3,unexpected EOF - NOEVENT" "CAM4_ERR3_0,CAM4_ERR3_1" bitfld.long 0x38 4. "CAM4_ERR2,unexpected EOL - NOEVENT" "CAM4_ERR2_0,CAM4_ERR2_1" newline bitfld.long 0x38 3. "CAM4_ERR1,unexpected SOV - NOEVENT" "CAM4_ERR1_0,CAM4_ERR1_1" bitfld.long 0x38 2. "CAM4_ERR0,EOX not received - NOEVENT" "CAM4_ERR0_0,CAM4_ERR0_1" newline bitfld.long 0x38 1. "CAM4_EOF,End of frame timing - NOEVENT" "CAM4_EOF_0,CAM4_EOF_1" bitfld.long 0x38 0. "CAM4_SOF,Start of frame timing - NOEVENT" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x3C "LVDSRX_IRQENABLE_SET_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x3C 9. "CAM4_ERR7,sync detected timeout reached - NOACTION" "CAM4_ERR7_0,CAM4_ERR7_1" bitfld.long 0x3C 8. "CAM4_ERR6,CRC error - NOACTION" "CAM4_ERR6_0,CAM4_ERR6_1" newline bitfld.long 0x3C 7. "CAM4_ERR5,unexpected SOF - NOACTION" "CAM4_ERR5_0,CAM4_ERR5_1" bitfld.long 0x3C 6. "CAM4_ERR4,unexpected SOL - NOACTION" "CAM4_ERR4_0,CAM4_ERR4_1" newline bitfld.long 0x3C 5. "CAM4_ERR3,unexpected EOF - NOACTION" "CAM4_ERR3_0,CAM4_ERR3_1" bitfld.long 0x3C 4. "CAM4_ERR2,unexpected EOL - NOACTION" "CAM4_ERR2_0,CAM4_ERR2_1" newline bitfld.long 0x3C 3. "CAM4_ERR1,unexpected SOV - NOACTION" "CAM4_ERR1_0,CAM4_ERR1_1" bitfld.long 0x3C 2. "CAM4_ERR0,EOX not received - NOACTION" "CAM4_ERR0_0,CAM4_ERR0_1" newline bitfld.long 0x3C 1. "CAM4_EOF,End of frame timing - NOACTION" "CAM4_EOF_0,CAM4_EOF_1" bitfld.long 0x3C 0. "CAM4_SOF,Start of frame timing - NOACTION" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x40 "LVDSRX_IRQENABLE_CLR_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x40 9. "CAM4_ERR7,sync detected timeout reached - NOACTION" "CAM4_ERR7_0,CAM4_ERR7_1" bitfld.long 0x40 8. "CAM4_ERR6,CRC error - NOACTION" "CAM4_ERR6_0,CAM4_ERR6_1" newline bitfld.long 0x40 7. "CAM4_ERR5,unexpected SOF - NOACTION" "CAM4_ERR5_0,CAM4_ERR5_1" bitfld.long 0x40 6. "CAM4_ERR4,unexpected SOL - NOACTION" "CAM4_ERR4_0,CAM4_ERR4_1" newline bitfld.long 0x40 5. "CAM4_ERR3,unexpected EOF - NOACTION" "CAM4_ERR3_0,CAM4_ERR3_1" bitfld.long 0x40 4. "CAM4_ERR2,unexpected EOL - NOACTION" "CAM4_ERR2_0,CAM4_ERR2_1" newline bitfld.long 0x40 3. "CAM4_ERR1,unexpected SOV - NOACTION" "CAM4_ERR1_0,CAM4_ERR1_1" bitfld.long 0x40 2. "CAM4_ERR0,EOX not received - NOACTION" "CAM4_ERR0_0,CAM4_ERR0_1" newline bitfld.long 0x40 1. "CAM4_EOF,End of frame timing - NOACTION" "CAM4_EOF_0,CAM4_EOF_1" bitfld.long 0x40 0. "CAM4_SOF,Start of frame timing - NOACTION" "CAM4_SOF_0,CAM4_SOF_1" line.long 0x44 "LVDSRX_CAM1_CFG,CAM output port #1 configuration This register associate one bit for each context in order to enable/disable each context individually" bitfld.long 0x44 28.--30. "NUM_LANE4,Number of lanes of PHY4 when NUM_PHY 3" "0,1,2,3,4,5,6,7" bitfld.long 0x44 24.--26. "NUM_LANE3,Number of lanes of PHY3 when NUM_PHY 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 20.--22. "NUM_LANE2,Number of lanes of PHY2 when NUM_PHY 1" "0,1,2,3,4,5,6,7" bitfld.long 0x44 16.--18. "NUM_LANE1,Number of lanes of PHY1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0x44 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0x44 13. "FILEN," "0,1" bitfld.long 0x44 12. "CRCEN," "0,1" newline bitfld.long 0x44 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0x44 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0x44 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" bitfld.long 0x44 4.--6. "NUMPHY,Number of PHYs 0 ~ 4 is available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x44 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x48 "LVDSRX_CAM1_FRMSIZE,CAM port #1 frame X*Y width" hexmask.long.word 0x48 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x48 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x4C "LVDSRX_CAM1_MAXWIDTH,CAM port #1 maximum line width" hexmask.long.word 0x4C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x50 "LVDSRX_CAM1_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x50 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x50 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x54 "LVDSRX_CAM1_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x54 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x54 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x58 "LVDSRX_CAM1_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x58 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x58 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x5C "LVDSRX_CAM1_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x5C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x5C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0x60 "LVDSRX_CAM1_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0x60 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x60 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0x64 "LVDSRX_CAM2_CFG,CAM output port #2 configuration This register associate one bit for each context in order to enable/disable each context individually" bitfld.long 0x64 16.--18. "NUM_LANE,Number of lanes of PHY2" "0,1,2,3,4,5,6,7" bitfld.long 0x64 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" newline bitfld.long 0x64 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" bitfld.long 0x64 13. "FILEN," "0,1" newline bitfld.long 0x64 12. "CRCEN," "0,1" bitfld.long 0x64 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" newline bitfld.long 0x64 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." bitfld.long 0x64 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" newline bitfld.long 0x64 4.--5. "NUMPHY,Number of PHYs 0 ~ 1 is available" "0,1,2,3" bitfld.long 0x64 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x68 "LVDSRX_CAM2_FRMSIZE,CAM port #2 frame X*Y width" hexmask.long.word 0x68 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x68 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x6C "LVDSRX_CAM2_MAXWIDTH,CAM port #2 maximum line width" hexmask.long.word 0x6C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x70 "LVDSRX_CAM2_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x70 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x70 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x74 "LVDSRX_CAM2_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x74 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x74 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x78 "LVDSRX_CAM2_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x78 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x78 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x7C "LVDSRX_CAM2_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x7C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x7C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0x80 "LVDSRX_CAM2_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0x80 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x80 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0x84 "LVDSRX_CAM3_CFG,CAM output port #3 configuration This register associate one bit for each context in order to enable/disable each context individually" bitfld.long 0x84 20.--22. "NUM_LANE2,Number of lanes of PHY4 when NUM_PHY 1" "0,1,2,3,4,5,6,7" bitfld.long 0x84 16.--18. "NUM_LANE1,Number of lanes of PHY3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x84 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" bitfld.long 0x84 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" newline bitfld.long 0x84 13. "FILEN," "0,1" bitfld.long 0x84 12. "CRCEN," "0,1" newline bitfld.long 0x84 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" bitfld.long 0x84 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." newline bitfld.long 0x84 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" bitfld.long 0x84 4.--5. "NUMPHY,Number of PHYs 0 1 2 is available" "0,1,2,3" newline bitfld.long 0x84 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-15: Reserved,?..." line.long 0x88 "LVDSRX_CAM3_FRMSIZE,CAM port #3 frame X*Y width" hexmask.long.word 0x88 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0x88 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0x8C "LVDSRX_CAM3_MAXWIDTH,CAM port #3 maximum line width" hexmask.long.word 0x8C 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0x90 "LVDSRX_CAM3_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0x90 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x90 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0x94 "LVDSRX_CAM3_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0x94 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x94 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0x98 "LVDSRX_CAM3_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0x98 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x98 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0x9C "LVDSRX_CAM3_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0x9C 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0x9C 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0xA0 "LVDSRX_CAM3_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0xA0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xA0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0xA4 "LVDSRX_CAM4_CFG,CAM output port #4 configuration This register associate one bit for each context in order to enable/disable each context individually" bitfld.long 0xA4 16.--18. "NUM_LANE,Number of lanes of PHY4" "0,1,2,3,4,5,6,7" bitfld.long 0xA4 15. "ALIGN,MSB LSB alignment for output pixel data" "LSB align,MSB align" newline bitfld.long 0xA4 14. "DENDIAN,Transmit format of none SYNC area" "Little endian,big endian" bitfld.long 0xA4 13. "FILEN," "0,1" newline bitfld.long 0xA4 12. "CRCEN," "0,1" bitfld.long 0xA4 11. "SENDIAN,Transmit format of SYNC area" "Little endian,big endian" newline bitfld.long 0xA4 8.--10. "PIX_WIDTH,Word width of recovered parallel data" "8-BITS,10-BITS,12-BITS,14-BITS,16-BITS 5-7:..,?..." bitfld.long 0xA4 7. "FRSTAT_INIT,Specifies Initial frame state in mode2 mode4 mod5 and mode8" "0,1" newline bitfld.long 0xA4 4. "NUMPHY,Number of PHYs 0 1 is available" "0,1" bitfld.long 0xA4 0.--3. "OP_MODE,Protocol selection" "Serial LVDS mode 1,Serial LVDS mode 2,Serial LVDS mode 3,Serial LVDS mode 4,Serial LVDS mode 5,Serial LVDS mode 6,Serial LVDS mode 7,Serial LVDS mode 8,Serial LVDS mode 9 9-13: Reserved,?,?,?,?,?,CMOS parallel IF (CCIR656 embeded sync),CMOS parallel IF (extenal HSYNC/VSYNC) When in.." line.long 0xA8 "LVDSRX_CAM4_FRMSIZE,CAM port #4 frame X*Y width" hexmask.long.word 0xA8 16.--31. 1. "FRWIDTH,Frame size in number of image lines" hexmask.long.word 0xA8 0.--15. 1. "LNWIDTH,Image line width in number of data words" line.long 0xAC "LVDSRX_CAM4_MAXWIDTH,CAM port #4 maximum line width" hexmask.long.word 0xAC 0.--15. 1. "MAXWIDTH,The maximum line width expected in number of pixels" line.long 0xB0 "LVDSRX_CAM4_SYNCSOF,Specifies SYNC pattern" hexmask.long.word 0xB0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Frame) sync pattern" line.long 0xB4 "LVDSRX_CAM4_SYNCEOF,Specifies SYNC pattern" hexmask.long.word 0xB4 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB4 0.--15. 1. "SOFPTN,Specifies SOF(End Of Frame) sync pattern" line.long 0xB8 "LVDSRX_CAM4_SYNCSOL,Specifies SYNC pattern" hexmask.long.word 0xB8 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xB8 0.--15. 1. "SOFPTN,Specifies SOF(Start Of Line) sync pattern" line.long 0xBC "LVDSRX_CAM4_SYNCEOL,Specifies SYNC pattern" hexmask.long.word 0xBC 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xBC 0.--15. 1. "SOFPTN,Specifies SOF(End Of Line) sync pattern" line.long 0xC0 "LVDSRX_CAM4_SYNCSOV,Specifies SYNC pattern" hexmask.long.word 0xC0 16.--31. 1. "BITMASK,Specifies the mask bit to be compared" hexmask.long.word 0xC0 0.--15. 1. "SOFPTN,Specifies SOF(Start Of V-blanking) sync pattern" line.long 0xC4 "LVDSRX_WDRCFG," bitfld.long 0xC4 8.--11. "PIX_WIDTH,Word width after de-companded" "12-BITS,13-BITS,14-BITS,15-BITS,16-BITS,17-BITS,18-BITS,19-BITS,20-BITS 9-15:..,?..." bitfld.long 0xC4 4. "WDRMODE,WDR mode select" "de-companding,bit interlaced format Not alloweed to.." newline bitfld.long 0xC4 3. "WDRENA4,WDR mode enable for CAM port #4" "disable,enable WDR function.." bitfld.long 0xC4 2. "WDRENA3,WDR mode enable for CAM port #3" "disable,enable WDR function.." newline bitfld.long 0xC4 1. "WDRENA2,WDR mode enable for CAM port #2" "disable,enable WDR function.." bitfld.long 0xC4 0. "WDRENA1,WDR mode enable for CAM port #1" "disable,enable WDR function.." line.long 0xC8 "LVDSRX_WDRGN,WDR gain configuration" bitfld.long 0xC8 16.--21. "WDRNPXY1,Specifies the pixel level for area #1 knee point inX/ Y axis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0xC8 8.--11. "WDRGN4,Specifies the gain for area #4 Gain = 1/2^WDRGN4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC8 4.--7. "WDRGN3,Specifies the gain for area #3 Gain = 1/2^WDRGN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0xC8 0.--3. "WDRGN2,Specifies the gain for area #2 Gain = 1/2^WDRGN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0xCC "LVDSRX_WDRKP1,WDR knee point configuration" hexmask.long.word 0xCC 16.--25. 1. "WDRNPY3,Specifies the pixel level for area #3 knee point in Y axis" hexmask.long.word 0xCC 0.--9. 1. "WDRNPY2,Specifies the pixel level for area #2 knee point in Y axis" line.long 0xD0 "LVDSRX_WDRKP2," hexmask.long.word 0xD0 16.--29. 1. "WDRNPX3,Specifies the pixel level for area #3 knee point in X axis" hexmask.long.word 0xD0 0.--13. 1. "WDRNPX2,Specifies the pixel level for area #2 knee point in X axis" rgroup.long 0x100++0x0F line.long 0x00 "LVDSRX_TEST1,When.CAM1TEST=1. PHY #1 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x00 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x00 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x00 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x00 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x04 "LVDSRX_TEST2,When.CAM2TEST=1. PHY #2 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x04 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x04 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x04 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x04 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x08 "LVDSRX_TEST3,When.CAM3TEST=1. PHY #3 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x08 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x08 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x08 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x08 0.--7. 1. "LANE1,lane #1 byte data" line.long 0x0C "LVDSRX_TEST4,When.CAM4TEST=1. PHY #4 data (8bitx4 lanes) can be monitored by this register" hexmask.long.byte 0x0C 24.--31. 1. "LANE4,lane #4 byte data" hexmask.long.byte 0x0C 16.--23. 1. "LANE3,lane #3 byte data" newline hexmask.long.byte 0x0C 8.--15. 1. "LANE2,lane #2 byte data" hexmask.long.byte 0x0C 0.--7. 1. "LANE1,lane #1 byte data" width 0x0B tree.end tree.end tree "ISS_Overview" tree "ISS_CTSET" base ad:0x52010000 rgroup.long 0x00++0x03 line.long 0x00 "CTSETIDEN,CTSET identification register" group.long 0x10++0x07 line.long 0x00 "CTSETSYSCFG,CTSET system configuration register" bitfld.long 0x00 2.--3. "IDLEMODE," "0,1,2,3" bitfld.long 0x00 0. "SOFTRESET," "0,1" line.long 0x04 "SETSTR,SET status register" bitfld.long 0x04 8. "HWFIFOEMPTY," "0,1" bitfld.long 0x04 0. "RESETDONE," "0,1" group.long 0x24++0x07 line.long 0x00 "CTSETCFG,CTSET configuration register" bitfld.long 0x00 28.--31. "OWNERSHIP,Claim control and status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. "CAPENABLE,When high the system event capture is enabled" "0,1" bitfld.long 0x00 4. "EVENTEDGE,High or Low level event detection" "0,1" bitfld.long 0x00 3. "DETECTMODE,Message generated based on event detection or sampling window" "0,1" bitfld.long 0x00 2. "STOPCAPONTRIG,Stop capturing system events from external trigger detection" "0,1" bitfld.long 0x00 1. "STARTCAPONTRIG,Start capturing systetm events from external trigger detection" "0,1" line.long 0x04 "SETSPLREG,System event sampling window register" hexmask.long.byte 0x04 0.--7. 1. "WINDOWSIZE," group.long 0x30++0x23 line.long 0x00 "SETEVTENBL1,System event detection enable register 1" line.long 0x04 "SETEVTENBL2,System event detection enable register 2" line.long 0x08 "SETEVTENBL3," line.long 0x0C "SETEVTENBL4," line.long 0x10 "SETEVTENBL5," line.long 0x14 "SETEVTENBL6," line.long 0x18 "SETEVTENBL7," line.long 0x1C "SETEVTENBL8," hexmask.long 0x1C 0.--30. 1. "EVTENABLE,Event 225 to 255 detection enable bits" line.long 0x20 "SETMSTID,System Event Master ID" hexmask.long.byte 0x20 0.--7. 1. "MASTID,HW Master ID for SET" group.long 0x800++0x03 line.long 0x00 "CTCNTL,Counter Timer Control" rbitfld.long 0x00 26.--31. "NUMSTM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT," rbitfld.long 0x00 13.--17. "NUMTIMR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "ENBL," "0,1" group.long 0x820++0x0B line.long 0x00 "CTSTMCNTL,Counter Timer STM Control" bitfld.long 0x00 6.--11. "NUMXPORT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 5. "XPORTACT," "0,1" bitfld.long 0x00 4. "CCMXPORT," "0,1" rbitfld.long 0x00 3. "CCMAVAIL," "0,1" bitfld.long 0x00 2. "CSMXPORT," "0,1" bitfld.long 0x00 1. "SENDOVR," "0,1" bitfld.long 0x00 0. "ENBL," "0,1" line.long 0x04 "CTSTMMSTID,CTM STM Master ID register" hexmask.long.byte 0x04 0.--7. 1. "MASTID," line.long 0x08 "CTSTMINTVL,CTM STM interval register" hexmask.long.word 0x08 0.--15. 1. "INTERVAL," rgroup.long 0x8C0++0x03 line.long 0x00 "CTNUMDBG,CTM Debug Event Register" bitfld.long 0x00 0.--3. "NUMEVNT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC00++0x13 line.long 0x00 "CTEOI,Counter Timer EOI Register" bitfld.long 0x00 0. "EOI," "0,1" line.long 0x04 "CTIRQSTAT_RAW,Counter Timer IRQ raw status register" hexmask.long.byte 0x04 0.--7. 1. "TIM_INT_IRQ," line.long 0x08 "CTIRQSTAT,Counter Timer IRQ Status Register" hexmask.long.byte 0x08 0.--7. 1. "TIM_INT," line.long 0x0C "CTIRQENABLE_SET,Counter Timer IRQ eable set register" hexmask.long.byte 0x0C 0.--7. 1. "TIM_INT_IES," line.long 0x10 "CTIRQENABLE_CLR,Counter Timer IRQ enable clear register" hexmask.long.byte 0x10 0.--7. 1. "TIM_INT_IEC," repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xB40)++0x03 line.long 0x00 "CTCNTR$1,Counter Timer Counter Register" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xB00)++0x03 line.long 0x00 "CTCNTR$1,Counter Timer Counter Register" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA40)++0x03 line.long 0x00 "CTCR$1,Counter Timer Control Register" hexmask.long.byte 0x00 24.--31. 1. "WDRESET," hexmask.long.byte 0x00 16.--23. 1. "INPSEL," newline bitfld.long 0x00 12. "DBG_TRIG_STAT," "0,1" bitfld.long 0x00 11. "WDMODE," "0,1" newline bitfld.long 0x00 10. "RESTART," "0,1" bitfld.long 0x00 9. "DBG," "0,1" newline bitfld.long 0x00 8. "INT," "0,1" rbitfld.long 0x00 7. "CHNSDW," "0,1" newline rbitfld.long 0x00 6. "OVRFLW," "0,1" bitfld.long 0x00 5. "IDLE," "0,1" newline bitfld.long 0x00 4. "FREE," "0,1" bitfld.long 0x00 3. "DURMODE," "0,1" newline bitfld.long 0x00 2. "CHAIN," "0,1" bitfld.long 0x00 1. "RESET," "0,1" newline bitfld.long 0x00 0. "ENBL," "0,1" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA00)++0x03 line.long 0x00 "CTCR$1,Counter Timer Control Register" hexmask.long.byte 0x00 24.--31. 1. "WDRESET," hexmask.long.byte 0x00 16.--23. 1. "INPSEL," newline bitfld.long 0x00 12. "DBG_TRIG_STAT," "0,1" bitfld.long 0x00 11. "WDMODE," "0,1" newline bitfld.long 0x00 10. "RESTART," "0,1" bitfld.long 0x00 9. "DBG," "0,1" newline bitfld.long 0x00 8. "INT," "0,1" rbitfld.long 0x00 7. "CHNSDW," "0,1" newline rbitfld.long 0x00 6. "OVRFLW," "0,1" bitfld.long 0x00 5. "IDLE," "0,1" newline bitfld.long 0x00 4. "FREE," "0,1" bitfld.long 0x00 3. "DURMODE," "0,1" newline bitfld.long 0x00 2. "CHAIN," "0,1" bitfld.long 0x00 1. "RESET," "0,1" newline bitfld.long 0x00 0. "ENBL," "0,1" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x9F8)++0x03 line.long 0x00 "CTGRST$1,CTM Global Reset Register 0" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x9F0)++0x03 line.long 0x00 "CTGNBL$1,CTM Global Enable Register 0" repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x8C4)++0x03 line.long 0x00 "CTDBGSGL$1,CTM Debug Event Register" hexmask.long.byte 0x00 0.--7. 1. "INPSEL," repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x840)++0x03 line.long 0x00 "TINTVLR$1,Timer Interval Register 0" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x82C)++0x03 line.long 0x00 "CTSTMSEL$1,CTM STM counter select register" repeat.end width 0x0B tree.end tree "ISS_TOP" base ad:0x52000000 tree "Channel_6" group.long 0x1E0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_6,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x160++0x03 line.long 0x00 "ISS_ICM_A_TC_k_6,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x260++0x03 line.long 0x00 "ISS_ICM_B_TC_k_6,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "Channel_7" group.long 0x1F0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_7,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x170++0x03 line.long 0x00 "ISS_ICM_A_TC_k_7,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x270++0x03 line.long 0x00 "ISS_ICM_B_TC_k_7,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_0" group.long 0x2C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x28++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x24++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x180++0x03 line.long 0x00 "ISS_ICM_A_CME_k_0,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x100++0x03 line.long 0x00 "ISS_ICM_A_TC_k_0,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x200++0x03 line.long 0x00 "ISS_ICM_B_TC_k_0,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_1" group.long 0x3C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x38++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x34++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x190++0x03 line.long 0x00 "ISS_ICM_A_CME_k_1,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x03 line.long 0x00 "ISS_ICM_A_TC_k_1,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x210++0x03 line.long 0x00 "ISS_ICM_B_TC_k_1,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_2" group.long 0x4C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x48++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x44++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x1A0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_2,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x120++0x03 line.long 0x00 "ISS_ICM_A_TC_k_2,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x220++0x03 line.long 0x00 "ISS_ICM_B_TC_k_2,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_3" group.long 0x5C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x58++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x54++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x1B0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_3,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x130++0x03 line.long 0x00 "ISS_ICM_A_TC_k_3,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x230++0x03 line.long 0x00 "ISS_ICM_B_TC_k_3,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_4" group.long 0x6C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_4,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x68++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_4,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x64++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_4,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x1C0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_4,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x03 line.long 0x00 "ISS_ICM_A_TC_k_4,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x240++0x03 line.long 0x00 "ISS_ICM_B_TC_k_4,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end tree "IRQ_Line_5" group.long 0x7C++0x03 line.long 0x00 "ISS_HL_IRQENABLE_CLR_i_5,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Disable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x78++0x03 line.long 0x00 "ISS_HL_IRQENABLE_SET_i_5,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" bitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOACTION" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No action,Enable interrupt" bitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOACTION" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOACTION" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" bitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" bitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline bitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOACTION" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline bitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" bitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" bitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x74++0x03 line.long 0x00 "ISS_HL_IRQSTATUS_i_5,Per-event 'enabled' interrupt status vector. line #0" rbitfld.long 0x00 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x00 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x00 27. "LVDSRX1_IRQ," "0,1" rbitfld.long 0x00 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" newline rbitfld.long 0x00 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 23. "CAL_B_IRQ,Event generated by CAL #B" "No (enabled) event pending,Event pending" rbitfld.long 0x00 22. "CAL_A_IRQ,Event generated by CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" newline rbitfld.long 0x00 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x00 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x00 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x00 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" rbitfld.long 0x00 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" newline rbitfld.long 0x00 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x00 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x00 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x00 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x00 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" group.long 0x1D0++0x03 line.long 0x00 "ISS_ICM_A_CME_k_5,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 16.--21. "PRODUCER,P_START / P_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "CONSUMER,C_START / C_DONE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x150++0x03 line.long 0x00 "ISS_ICM_A_TC_k_5,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" group.long 0x250++0x03 line.long 0x00 "ISS_ICM_B_TC_k_5,This register is reserved and users should write the reset value to this register location" hexmask.long.byte 0x00 16.--23. 1. "RESYNC,ID of the frame resynchronization event" hexmask.long.byte 0x00 0.--7. 1. "SYNC,ID of the transfer trigger event" tree.end group.long 0x90++0x03 line.long 0x00 "ISS_BYS,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 14. "CSI3A_IN,This bit field is reserved and users should write the reset value to this bit location" "CSI3A_IN_0,CSI3A_IN_1" bitfld.long 0x00 4.--6. "BYSB_IN,This bit field is reserved and users should write the reset value to this bit location" "BYSB_IN_0,BYSB_IN_1,?,?,BYSB_IN_4,BYSB_IN_5,?,?" bitfld.long 0x00 0.--2. "BYSA_IN,This bit field is reserved and users should write the reset value to this bit location" "BYSA_IN_0,BYSA_IN_1,?,?,BYSA_IN_4,BYSA_IN_5,?,?" group.long 0x84++0x07 line.long 0x00 "ISS_CLKCTRL,ISS clock control register" bitfld.long 0x00 29. "LVDSRX_OUT3_PCLK,Enables the pixel clock at VMUX input level" "LVDSRX_OUT3_PCLK_0,LVDSRX_OUT3_PCLK_1" bitfld.long 0x00 28. "LVDSRX_OUT2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT2_PCLK_0,LVDSRX_OUT2_PCLK_1" bitfld.long 0x00 27. "LVDSRX_OUT1_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT1_PCLK_0,LVDSRX_OUT1_PCLK_1" newline bitfld.long 0x00 26. "LVDSRX_OUT0_PCLK,Enables the pixel clock at VMUX input level" "LVDSRX_OUT0_PCLK_0,LVDSRX_OUT0_PCLK_1" bitfld.long 0x00 25. "GLBCE_OUT_PCLK,Enables the pixel clock at VMUX input level" "GLBCE_OUT_PCLK_0,GLBCE_OUT_PCLK_1" bitfld.long 0x00 24. "NSF3V_OUT_PCLK,Enables the pixel clock at VMUX input level" "NSF3V_OUT_PCLK_0,NSF3V_OUT_PCLK_1" newline bitfld.long 0x00 23. "BYS_B_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_OUT_PCLK_0,BYS_B_OUT_PCLK_1" bitfld.long 0x00 22. "BYS_A_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_OUT_PCLK_0,BYS_A_OUT_PCLK_1" bitfld.long 0x00 21. "PARALLEL_A_PCLK,Enables the pixel clock at VMUX input level" "PARALLEL_A_PCLK_0,PARALLEL_A_PCLK_1" newline bitfld.long 0x00 20. "CAL_B_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_B_OUT_PCLK_0,CAL_B_OUT_PCLK_1" bitfld.long 0x00 19. "CAL_B_BYS_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_B_BYS_OUT_PCLK_0,CAL_B_BYS_OUT_PCLK_1" bitfld.long 0x00 18. "CAL_A_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_A_OUT_PCLK_0,CAL_A_OUT_PCLK_1" newline bitfld.long 0x00 17. "CAL_A_BYS_OUT_PCLK,Enables the pixel clock at VMUX input level" "CAL_A_BYS_OUT_PCLK_0,CAL_A_BYS_OUT_PCLK_1" bitfld.long 0x00 16. "CCP2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PCLK_0,CCP2_PCLK_1" bitfld.long 0x00 14. "CTSET,CTSET - OFF" "CTSET_0,CTSET_1" newline bitfld.long 0x00 13. "LVDSRX,LVDSRX - OFF" "LVDSRX_0,LVDSRX_1" bitfld.long 0x00 12. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1" bitfld.long 0x00 11. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1" newline bitfld.long 0x00 10. "CAL_B,CAL #B - OFF" "CAL_B_0,CAL_B_1" bitfld.long 0x00 9. "CAL_A,CAL #A - OFF" "CAL_A_0,CAL_A_1" bitfld.long 0x00 7. "BYS_B,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_0,BYS_B_1" newline bitfld.long 0x00 5. "BYS_A,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_0,BYS_A_1" bitfld.long 0x00 4. "CCP2,This bit field is reserved and users should write the reset value to this bit location" "CCP2_0,CCP2_1" bitfld.long 0x00 1. "ISP,ISP - OFF" "ISP_0,ISP_1" newline bitfld.long 0x00 0. "SIMCOP,SIMCOP - OFF" "SIMCOP_0,SIMCOP_1" line.long 0x04 "ISS_CLKSTAT,ISS clock status register" bitfld.long 0x04 29. "LVDSRX_OUT3_PCLK,Status of the pixel clock - OFF" "LVDSRX_OUT3_PCLK_0,LVDSRX_OUT3_PCLK_1" bitfld.long 0x04 28. "LVDSRX_OUT2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT2_PCLK_0,LVDSRX_OUT2_PCLK_1" bitfld.long 0x04 27. "LVDSRX_OUT1_PCLK,This bit field is reserved and users should write the reset value to this bit location" "LVDSRX_OUT1_PCLK_0,LVDSRX_OUT1_PCLK_1" newline bitfld.long 0x04 26. "LVDSRX_OUT0_PCLK,Status of the pixel clock - OFF" "LVDSRX_OUT0_PCLK_0,LVDSRX_OUT0_PCLK_1" bitfld.long 0x04 25. "GLBCE_OUT_PCLK,Status of the pixel clock - OFF" "GLBCE_OUT_PCLK_0,GLBCE_OUT_PCLK_1" bitfld.long 0x04 24. "NSF3V_OUT_PCLK,Status of the pixel clock - OFF" "NSF3V_OUT_PCLK_0,NSF3V_OUT_PCLK_1" newline bitfld.long 0x04 23. "BYS_B_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_OUT_PCLK_0,BYS_B_OUT_PCLK_1" bitfld.long 0x04 22. "BYS_A_OUT_PCLK,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_OUT_PCLK_0,BYS_A_OUT_PCLK_1" bitfld.long 0x04 21. "PARALLEL_A_PCLK,Status of the pixel clock - OFF" "PARALLEL_A_PCLK_0,PARALLEL_A_PCLK_1" newline bitfld.long 0x04 20. "CAL_B_OUT_PCLK,Status of the pixel clock - OFF" "CAL_B_OUT_PCLK_0,CAL_B_OUT_PCLK_1" bitfld.long 0x04 19. "CAL_B_BYS_OUT_PCLK,Status of the pixel clock - OFF" "CAL_B_BYS_OUT_PCLK_0,CAL_B_BYS_OUT_PCLK_1" bitfld.long 0x04 18. "CAL_A_OUT_PCLK,Status of the pixel clock - OFF" "CAL_A_OUT_PCLK_0,CAL_A_OUT_PCLK_1" newline bitfld.long 0x04 17. "CAL_A_BYS_OUT_PCLK,Status of the pixel clock - OFF" "CAL_A_BYS_OUT_PCLK_0,CAL_A_BYS_OUT_PCLK_1" bitfld.long 0x04 16. "CCP2_PCLK,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PCLK_0,CCP2_PCLK_1" bitfld.long 0x04 14. "CTSET,CTSET - OFF" "CTSET_0,CTSET_1" newline bitfld.long 0x04 13. "LVDSRX,LVDSRX - OFF" "LVDSRX_0,LVDSRX_1" bitfld.long 0x04 12. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1" bitfld.long 0x04 11. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1" newline bitfld.long 0x04 10. "CAL_B,CAL #B - OFF" "CAL_B_0,CAL_B_1" bitfld.long 0x04 9. "CAL_A,CAL #A - OFF" "CAL_A_0,CAL_A_1" bitfld.long 0x04 7. "BYS_B,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_0,BYS_B_1" newline bitfld.long 0x04 5. "BYS_A,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_0,BYS_A_1" bitfld.long 0x04 4. "CCP2,This bit field is reserved and users should write the reset value to this bit location" "CCP2_0,CCP2_1" bitfld.long 0x04 1. "ISP,ISP - OFF" "ISP_0,ISP_1" newline bitfld.long 0x04 0. "SIMCOP,SIMCOP - OFF" "SIMCOP_0,SIMCOP_1" group.long 0x80++0x03 line.long 0x00 "ISS_CTRL,ISS control register" bitfld.long 0x00 20.--23. "CCP2W_TAG_CNT,This bit field is reserved and users should write the reset value to this bit location" "CCP2W_TAG_CNT_0,CCP2W_TAG_CNT_1,CCP2W_TAG_CNT_2,CCP2W_TAG_CNT_3,CCP2W_TAG_CNT_4,CCP2W_TAG_CNT_5,CCP2W_TAG_CNT_6,CCP2W_TAG_CNT_7,CCP2W_TAG_CNT_8,CCP2W_TAG_CNT_9,CCP2W_TAG_CNT_10,CCP2W_TAG_CNT_11,CCP2W_TAG_CNT_12,CCP2W_TAG_CNT_13,CCP2W_TAG_CNT_14,CCP2W_TAG_CNT_15" bitfld.long 0x00 16.--19. "CCP2R_TAG_CNT,This bit field is reserved and users should write the reset value to this bit location" "CCP2R_TAG_CNT_0,CCP2R_TAG_CNT_1,CCP2R_TAG_CNT_2,CCP2R_TAG_CNT_3,CCP2R_TAG_CNT_4,CCP2R_TAG_CNT_5,CCP2R_TAG_CNT_6,CCP2R_TAG_CNT_7,CCP2R_TAG_CNT_8,CCP2R_TAG_CNT_9,CCP2R_TAG_CNT_10,CCP2R_TAG_CNT_11,CCP2R_TAG_CNT_12,CCP2R_TAG_CNT_13,CCP2R_TAG_CNT_14,CCP2R_TAG_CNT_15" bitfld.long 0x00 6.--7. "INPUT_SEL2,This bit field is reserved and users should write the reset value to this bit location" "INPUT_SEL2_0,INPUT_SEL2_1,INPUT_SEL2_2,INPUT_SEL2_3" newline bitfld.long 0x00 4.--5. "ISS_CLK_DIV,ISS functional clock division CLK refers to the input clock provided to the ISS FCLK is the functional clock provided to ISS top level and sub modules CFGCLK is the clock used for the configuration network - NONE" "ISS_CLK_DIV_0,ISS_CLK_DIV_1,ISS_CLK_DIV_2,ISS_CLK_DIV_3" bitfld.long 0x00 2.--3. "INPUT_SEL,This bit field is reserved and users should write the reset value to this bit location" "INPUT_SEL_0,?,INPUT_SEL_2,INPUT_SEL_3" bitfld.long 0x00 0.--1. "SYNC_DETECT,Chooses among rising and falling edge for the HS_VS_IRQ synchronization event - HSF" "SYNC_DETECT_0,SYNC_DETECT_1,SYNC_DETECT_2,SYNC_DETECT_3" group.long 0x94++0x03 line.long 0x00 "ISS_CTRL1,ISS control register" bitfld.long 0x00 16. "PPI_MODE,Controls PPI interface - CAL mux at ISS level" "PPI_MODE_0,PPI_MODE_1" bitfld.long 0x00 13.--15. "STALL_MODE,Refer to the functional specification for details" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--12. "SENSOR_HUB_SYNC,This bit field is reserved and users should write the reset value to this bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 5.--6. "BTE_WMEM,This bit field is reserved and users should write the reset value to this bit location" "BTE_WMEM_0,BTE_WMEM_1,?,?" bitfld.long 0x00 4. "ENABLE_VMUX,Enables the video mux instead of legacy mode for ISP #A input and BYS connections" "ENABLE_VMUX_0,ENABLE_VMUX_1" bitfld.long 0x00 0.--1. "CTSET_EVT,CTSET event selection" "0,1,2,3" group.long 0xA8++0x03 line.long 0x00 "ISS_EMU_OUT,Select exported ISS level events" bitfld.long 0x00 24.--25. "EMU3_H," "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. "EMU3_L," bitfld.long 0x00 8.--9. "EMU2_H," "0,1,2,3" newline hexmask.long.byte 0x00 0.--7. 1. "EMU2_L," rgroup.long 0x04++0x03 line.long 0x00 "ISS_HL_HWINFO,This register is reserved and users should write the reset value to this register location" bitfld.long 0x00 0.--2. "BRIDGE_BUFF,Size of the re-ordering buffer in the CCP2 read bridge" "BRIDGE_BUFF_0,BRIDGE_BUFF_1,BRIDGE_BUFF_2,BRIDGE_BUFF_3,BRIDGE_BUFF_4,?,?,?" group.long 0x1C++0x07 line.long 0x00 "ISS_HL_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3,LINE_NUMBER_4,LINE_NUMBER_5,?,?" line.long 0x04 "ISS_HL_IRQSTATUS_RAW_i,Per-event raw interrupt status vector. line #0" rbitfld.long 0x04 29. "LVDSRX3_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX3_IRQ_0,LVDSRX3_IRQ_1" rbitfld.long 0x04 28. "LVDSRX2_IRQ," "0,1" rbitfld.long 0x04 27. "LVDSRX1_IRQ," "0,1" newline rbitfld.long 0x04 26. "LVDSRX0_IRQ,Event generated by LVDSRX - NOEVENT" "LVDSRX0_IRQ_0,LVDSRX0_IRQ_1" rbitfld.long 0x04 25. "ICM_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 24. "ICM_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline bitfld.long 0x04 23. "CAL_B_IRQ,Event generated by the CAL #B" "No event pending,Event pending" rbitfld.long 0x04 22. "CAL_A_IRQ,Event generated by the CAL #A - NOEVENT" "CAL_A_IRQ_0,CAL_A_IRQ_1" rbitfld.long 0x04 20. "BYS_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 19. "VMUX_IRQ,Event generated by VMUX - NOEVENT" "VMUX_IRQ_0,VMUX_IRQ_1" rbitfld.long 0x04 18. "BYS_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 17. "HS_VS_IRQ,HS or VS synchronization event" "HS_VS_IRQ_0,HS_VS_IRQ_1" newline rbitfld.long 0x04 16. "CCP2_IRQ8,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 15. "SIMCOP_IRQ3,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ3_0,SIMCOP_IRQ3_1" rbitfld.long 0x04 14. "SIMCOP_IRQ2,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ2_0,SIMCOP_IRQ2_1" newline rbitfld.long 0x04 13. "SIMCOP_IRQ1,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ1_0,SIMCOP_IRQ1_1" rbitfld.long 0x04 12. "SIMCOP_IRQ0,Event generated by SIMCOP - NOEVENT" "SIMCOP_IRQ0_0,SIMCOP_IRQ0_1" rbitfld.long 0x04 11. "BTE_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 10. "CBUFF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 9. "CCP2_IRQ3,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 8. "CCP2_IRQ2,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 7. "CCP2_IRQ1,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 6. "CCP2_IRQ0,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 3. "ISP_IRQ3,Combined interrupt event provided by the ISP" "ISP_IRQ3_0,ISP_IRQ3_1" newline rbitfld.long 0x04 2. "ISP_IRQ2,Combined interrupt event provided by the ISP" "ISP_IRQ2_0,ISP_IRQ2_1" rbitfld.long 0x04 1. "ISP_IRQ1,Combined interrupt event provided by the ISP" "ISP_IRQ1_0,ISP_IRQ1_1" rbitfld.long 0x04 0. "ISP_IRQ0,Combined interrupt event provided by the ISP" "ISP_IRQ0_0,ISP_IRQ0_1" rgroup.long 0x00++0x03 line.long 0x00 "ISS_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "ISS_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Master interface power management standby/Wait control - FORCE" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,IDLE protocol configuration - FORCE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" rgroup.long 0x8C++0x03 line.long 0x00 "ISS_PM_STATUS,ISS power manager status register" bitfld.long 0x00 26.--27. "CTSET,Power status of the CTSET module - STANDBY" "CTSET_0,CTSET_1,CTSET_2,?" bitfld.long 0x00 24.--25. "ICM_A,This bit field is reserved and users should write the reset value to this bit location" "ICM_A_0,ICM_A_1,ICM_A_2,?" bitfld.long 0x00 22.--23. "ICM_B,This bit field is reserved and users should write the reset value to this bit location" "ICM_B_0,ICM_B_1,ICM_B_2,?" newline bitfld.long 0x00 20.--21. "CAL_B,Power status of the CAL #B module - STANDBY" "CAL_B_0,CAL_B_1,CAL_B_2,?" bitfld.long 0x00 18.--19. "CAL_A,Power status of the CAL #A module - STANDBY" "CAL_A_0,CAL_A_1,CAL_A_2,?" bitfld.long 0x00 12.--13. "CBUFF_PM,This bit field is reserved and users should write the reset value to this bit location" "CBUFF_PM_0,CBUFF_PM_1,CBUFF_PM_2,?" newline bitfld.long 0x00 10.--11. "BTE_PM,This bit field is reserved and users should write the reset value to this bit location" "BTE_PM_0,BTE_PM_1,BTE_PM_2,?" bitfld.long 0x00 8.--9. "SIMCOP_PM,Power status of the SIMCOP module - STANDBY" "SIMCOP_PM_0,SIMCOP_PM_1,SIMCOP_PM_2,?" bitfld.long 0x00 6.--7. "ISP_PM,Power status of the ISP module - STANDBY" "ISP_PM_0,ISP_PM_1,ISP_PM_2,?" newline bitfld.long 0x00 4.--5. "CCP2_PM,This bit field is reserved and users should write the reset value to this bit location" "CCP2_PM_0,CCP2_PM_1,CCP2_PM_2,?" group.long 0x300++0x03 line.long 0x00 "ISS_REQINFO_MAP0_7,MReqInfo remapping table" bitfld.long 0x00 28.--30. "REQINFO_7,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "REQINFO_6,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "REQINFO_5,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "REQINFO_4,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "REQINFO_3,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "REQINFO_2,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "REQINFO_1,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "REQINFO_0,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" group.long 0x308++0x07 line.long 0x00 "ISS_REQINFO_MAP16_23,MReqInfo remapping table" bitfld.long 0x00 28.--30. "REQINFO_23,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "REQINFO_22,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "REQINFO_21,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "REQINFO_20,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "REQINFO_19,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "REQINFO_18,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "REQINFO_17,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "REQINFO_16,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" line.long 0x04 "ISS_REQINFO_MAP24_31,MReqInfo remapping table" bitfld.long 0x04 28.--30. "REQINFO_31,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "REQINFO_30,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. "REQINFO_29,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 16.--18. "REQINFO_28,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12.--14. "REQINFO_27,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "REQINFO_26,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "REQINFO_25,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "REQINFO_24,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" group.long 0x304++0x03 line.long 0x00 "ISS_REQINFO_MAP8_15,MReqInfo remapping table" bitfld.long 0x00 28.--30. "REQINFO_15,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "REQINFO_14,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "REQINFO_13,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "REQINFO_12,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "REQINFO_11,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "REQINFO_10,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "REQINFO_9,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "REQINFO_8,MReqInfo value visible @ ISS boundary" "0,1,2,3,4,5,6,7" group.long 0x9C++0x0B line.long 0x00 "ISS_ROUTE1,Controls traffic routing inside ISS" bitfld.long 0x00 14.--15. "CALA_7,CPort #7 - OCPM2" "CALA_7_0,CALA_7_1,CALA_7_2,CALA_7_3" bitfld.long 0x00 12.--13. "CALA_6,CPort #6 - OCPM2" "CALA_6_0,CALA_6_1,CALA_6_2,CALA_6_3" bitfld.long 0x00 10.--11. "CALA_5,CPort #5 - OCPM2" "CALA_5_0,CALA_5_1,CALA_5_2,CALA_5_3" newline bitfld.long 0x00 8.--9. "CALA_4,CPort #4 - OCPM2" "CALA_4_0,CALA_4_1,CALA_4_2,CALA_4_3" bitfld.long 0x00 6.--7. "CALA_3,CPort #3 - OCPM2" "CALA_3_0,CALA_3_1,CALA_3_2,CALA_3_3" bitfld.long 0x00 4.--5. "CALA_2,CPort #2 - OCPM2" "CALA_2_0,CALA_2_1,CALA_2_2,CALA_2_3" newline bitfld.long 0x00 2.--3. "CALA_1,CPort #1 - OCPM2" "CALA_1_0,CALA_1_1,CALA_1_2,CALA_1_3" bitfld.long 0x00 0.--1. "CALA_0,CPort #0" "CALA_0_0,CALA_0_1,CALA_0_2,CALA_0_3" line.long 0x04 "ISS_ROUTE2,This register is reserved and users should write the reset value to this register location.Controls traffic routing inside ISS" bitfld.long 0x04 14.--15. "CALB_7,CPort #7 - OCPM2" "CALB_7_0,CALB_7_1,CALB_7_2,CALB_7_3" bitfld.long 0x04 12.--13. "CALB_6,CPort #6 - OCPM2" "CALB_6_0,CALB_6_1,CALB_6_2,CALB_6_3" bitfld.long 0x04 10.--11. "CALB_5,CPort #5 - OCPM2" "CALB_5_0,CALB_5_1,CALB_5_2,CALB_5_3" newline bitfld.long 0x04 8.--9. "CALB_4,CPort #4 - OCPM2" "CALB_4_0,CALB_4_1,CALB_4_2,CALB_4_3" bitfld.long 0x04 6.--7. "CALB_3,CPort #3 - OCPM2" "CALB_3_0,CALB_3_1,CALB_3_2,CALB_3_3" bitfld.long 0x04 4.--5. "CALB_2,CPort #2 - OCPM2" "CALB_2_0,CALB_2_1,CALB_2_2,CALB_2_3" newline bitfld.long 0x04 2.--3. "CALB_1,CPort #1 - OCPM2" "CALB_1_0,CALB_1_1,CALB_1_2,CALB_1_3" bitfld.long 0x04 0.--1. "CALB_0,CPort #0" "CALB_0_0,CALB_0_1,CALB_0_2,CALB_0_3" line.long 0x08 "ISS_ROUTE3,Controls traffic routing inside ISS" bitfld.long 0x08 26.--27. "CCP2_WR,This bit field is reserved and users should write the reset value to this bit location" "CCP2_WR_0,CCP2_WR_1,CCP2_WR_2,CCP2_WR_3" bitfld.long 0x08 24.--25. "CCP2_RD,This bit field is reserved and users should write the reset value to this bit location" "CCP2_RD_0,CCP2_RD_1,CCP2_RD_2,CCP2_RD_3" bitfld.long 0x08 22.--23. "LDC,SIMCOP LDC - OCPM2" "LDC_0,LDC_1,LDC_2,LDC_3" newline bitfld.long 0x08 20.--21. "SDMA,SIMCOP - DMA - OCPM2" "SDMA_0,SDMA_1,SDMA_2,SDMA_3" bitfld.long 0x08 18.--19. "ICMB,This bit field is reserved and users should write the reset value to this bit location" "ICMB_0,ICMB_1,ICMB_2,ICMB_3" bitfld.long 0x08 16.--17. "ICMA,This bit field is reserved and users should write the reset value to this bit location" "ICMA_0,ICMA_1,ICMA_2,ICMA_3" newline bitfld.long 0x08 12.--13. "ISP_RSZB,ISP RSZ B - OCPM2" "ISP_RSZB_0,ISP_RSZB_1,ISP_RSZB_2,ISP_RSZB_3" bitfld.long 0x08 10.--11. "ISP_RSZA,ISP RSZ A - OCPM2" "ISP_RSZA_0,ISP_RSZA_1,ISP_RSZA_2,ISP_RSZA_3" bitfld.long 0x08 8.--9. "ISP_H3A,ISP H3A - OCPM2" "ISP_H3A_0,ISP_H3A_1,ISP_H3A_2,ISP_H3A_3" newline bitfld.long 0x08 6.--7. "ISP_BOXCAR,ISP_BOXCAR - OCPM2" "ISP_BOXCAR_0,ISP_BOXCAR_1,ISP_BOXCAR_2,ISP_BOXCAR_3" bitfld.long 0x08 4.--5. "ISP_RAW,ISP_RAW - OCPM2" "ISP_RAW_0,ISP_RAW_1,ISP_RAW_2,ISP_RAW_3" bitfld.long 0x08 2.--3. "ISP_LSC,ISP LSC - OCPM2" "ISP_LSC_0,ISP_LSC_1,ISP_LSC_2,ISP_LSC_3" newline bitfld.long 0x08 0.--1. "ISP_IPIPEIF,IPIPEIF - OCPM2" "ISP_IPIPEIF_0,ISP_IPIPEIF_1,ISP_IPIPEIF_2,ISP_IPIPEIF_3" group.long 0x98++0x03 line.long 0x00 "ISS_VMUX,ISS video mux control" bitfld.long 0x00 28.--30. "BYS_B_IN,This bit field is reserved and users should write the reset value to this bit location" "BYS_B_IN_0,BYS_B_IN_1,BYS_B_IN_2,BYS_B_IN_3,BYS_B_IN_4,BYS_B_IN_5,?,?" bitfld.long 0x00 24.--26. "BYS_A_IN,This bit field is reserved and users should write the reset value to this bit location" "BYS_A_IN_0,BYS_A_IN_1,BYS_A_IN_2,BYS_A_IN_3,BYS_A_IN_4,BYS_A_IN_5,?,?" bitfld.long 0x00 20.--23. "CAL_B_BYS_IN,This bit field is reserved and users should write the reset value to this bit location" "CAL_B_BYS_IN_0,CAL_B_BYS_IN_1,CAL_B_BYS_IN_2,CAL_B_BYS_IN_3,CAL_B_BYS_IN_4,CAL_B_BYS_IN_5,CAL_B_BYS_IN_6,?,CAL_B_BYS_IN_8,CAL_B_BYS_IN_9,?,?,?,?,?,?" newline bitfld.long 0x00 16.--19. "CAL_A_BYS_IN,Data source connected to the BYSin port of CAL #A - LVDSRX_OUT3" "CAL_A_BYS_IN_0,CAL_A_BYS_IN_1,CAL_A_BYS_IN_2,CAL_A_BYS_IN_3,CAL_A_BYS_IN_4,CAL_A_BYS_IN_5,CAL_A_BYS_IN_6,CAL_A_BYS_IN_7,CAL_A_BYS_IN_8,CAL_A_BYS_IN_9,?,?,?,?,?,?" bitfld.long 0x00 8.--11. "GLBCE_IN,Data source connected to GLBCE - ZERO" "GLBCE_IN_0,GLBCE_IN_1,GLBCE_IN_2,GLBCE_IN_3,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 4.--7. "NSF3V_IN,Data source connected to NSF3V - ZERO" "NSF3V_IN_0,NSF3V_IN_1,NSF3V_IN_2,NSF3V_IN_3,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0.--3. "ISP_IN,Data source connected to ISP - LVDSRX_OUT2" "ISP_IN_0,ISP_IN_1,ISP_IN_2,ISP_IN_3,ISP_IN_4,ISP_IN_5,ISP_IN_6,ISP_IN_7,ISP_IN_8,?,?,?,?,?,?,?" group.long 0xBC++0x03 line.long 0x00 "ISS_VMUX_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" rbitfld.long 0x00 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x00 12. "F304_426_E_OVR_IRQ," "0,1" rbitfld.long 0x00 11. "F304_426_D_OVR_IRQ," "0,1" newline rbitfld.long 0x00 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x00 9. "F304_426_B_OVR_IRQ," "0,1" rbitfld.long 0x00 8. "F304_426_A_OVR_IRQ," "0,1" newline rbitfld.long 0x00 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x00 6. "F426_304_A_OVR_IRQ," "0,1" bitfld.long 0x00 5. "W64_32_A_OVR_IRQ,- NOACTION" "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" newline bitfld.long 0x00 4. "W32_16_A_OVR_IRQ,- NOACTION" "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x00 3. "W64_16_B_OVR_IRQ,- NOACTION" "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" bitfld.long 0x00 2. "W64_16_A_OVR_IRQ,- NOACTION" "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" newline bitfld.long 0x00 1. "W16_64_B_OVR_IRQ,- NOACTION" "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x00 0. "W16_64_A_OVR_IRQ,- NOACTION" "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" group.long 0xB8++0x03 line.long 0x00 "ISS_VMUX_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" rbitfld.long 0x00 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x00 12. "F304_426_E_OVR_IRQ," "0,1" rbitfld.long 0x00 11. "F304_426_D_OVR_IRQ," "0,1" newline rbitfld.long 0x00 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x00 9. "F304_426_B_OVR_IRQ," "0,1" rbitfld.long 0x00 8. "F304_426_A_OVR_IRQ," "0,1" newline rbitfld.long 0x00 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x00 6. "F426_304_A_OVR_IRQ," "0,1" bitfld.long 0x00 5. "W64_32_A_OVR_IRQ,- NOACTION" "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" newline bitfld.long 0x00 4. "W32_16_A_OVR_IRQ,- NOACTION" "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x00 3. "W64_16_B_OVR_IRQ,- NOACTION" "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" bitfld.long 0x00 2. "W64_16_A_OVR_IRQ,- NOACTION" "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" newline bitfld.long 0x00 1. "W16_64_B_OVR_IRQ,- NOACTION" "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x00 0. "W16_64_A_OVR_IRQ,- NOACTION" "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" group.long 0xB4++0x03 line.long 0x00 "ISS_VMUX_IRQSTATUS,Per-event 'enabled' interrupt status vector" rbitfld.long 0x00 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x00 12. "F304_426_E_OVR_IRQ," "0,1" rbitfld.long 0x00 11. "F304_426_D_OVR_IRQ," "0,1" newline rbitfld.long 0x00 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x00 9. "F304_426_B_OVR_IRQ," "0,1" rbitfld.long 0x00 8. "F304_426_A_OVR_IRQ," "0,1" newline rbitfld.long 0x00 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x00 6. "F426_304_A_OVR_IRQ," "0,1" bitfld.long 0x00 5. "W64_32_A_OVR_IRQ,- NOACTION" "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" newline bitfld.long 0x00 4. "W32_16_A_OVR_IRQ,- NOACTION" "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x00 3. "W64_16_B_OVR_IRQ,- NOACTION" "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" bitfld.long 0x00 2. "W64_16_A_OVR_IRQ,- NOACTION" "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" newline bitfld.long 0x00 1. "W16_64_B_OVR_IRQ,- NOACTION" "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x00 0. "W16_64_A_OVR_IRQ,- NOACTION" "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" group.long 0xB0++0x03 line.long 0x00 "ISS_VMUX_IRQSTATUS_RAW,Per-event raw interrupt status vector" rbitfld.long 0x00 13. "F304_426_F_OVR_IRQ," "0,1" rbitfld.long 0x00 12. "F304_426_E_OVR_IRQ," "0,1" rbitfld.long 0x00 11. "F304_426_D_OVR_IRQ," "0,1" newline rbitfld.long 0x00 10. "F304_426_C_OVR_IRQ," "0,1" rbitfld.long 0x00 9. "F304_426_B_OVR_IRQ," "0,1" rbitfld.long 0x00 8. "F304_426_A_OVR_IRQ," "0,1" newline rbitfld.long 0x00 7. "F426_304_B_OVR_IRQ," "0,1" rbitfld.long 0x00 6. "F426_304_A_OVR_IRQ," "0,1" bitfld.long 0x00 5. "W64_32_A_OVR_IRQ,- NOACTION" "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" newline bitfld.long 0x00 4. "W32_16_A_OVR_IRQ,- NOACTION" "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x00 3. "W64_16_B_OVR_IRQ,- NOACTION" "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" bitfld.long 0x00 2. "W64_16_A_OVR_IRQ,- NOACTION" "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" newline bitfld.long 0x00 1. "W16_64_B_OVR_IRQ,- NOACTION" "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x00 0. "W16_64_A_OVR_IRQ,- NOACTION" "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" group.long 0xAC++0x03 line.long 0x00 "ISS_VMUX_RESET,For debug purposes only" bitfld.long 0x00 13. "F304_426_F_OVR_IRQ,- NOEFFECT" "F304_426_F_OVR_IRQ_0,F304_426_F_OVR_IRQ_1" bitfld.long 0x00 12. "F304_426_E_OVR_IRQ,- NOEFFECT" "F304_426_E_OVR_IRQ_0,F304_426_E_OVR_IRQ_1" bitfld.long 0x00 11. "F304_426_D_OVR_IRQ,- NOEFFECT" "F304_426_D_OVR_IRQ_0,F304_426_D_OVR_IRQ_1" newline bitfld.long 0x00 10. "F304_426_C_OVR_IRQ,- NOEFFECT" "F304_426_C_OVR_IRQ_0,F304_426_C_OVR_IRQ_1" bitfld.long 0x00 9. "F304_426_B_OVR_IRQ,- NOEFFECT" "F304_426_B_OVR_IRQ_0,F304_426_B_OVR_IRQ_1" bitfld.long 0x00 8. "F304_426_A_OVR_IRQ,- NOEFFECT" "F304_426_A_OVR_IRQ_0,F304_426_A_OVR_IRQ_1" newline bitfld.long 0x00 7. "F426_304_B_OVR_IRQ,- NOEFFECT" "F426_304_B_OVR_IRQ_0,F426_304_B_OVR_IRQ_1" bitfld.long 0x00 6. "F426_304_A_OVR_IRQ,- NOEFFECT" "F426_304_A_OVR_IRQ_0,F426_304_A_OVR_IRQ_1" bitfld.long 0x00 5. "W64_32_A_OVR_IRQ,- NOEFFECT" "W64_32_A_OVR_IRQ_0,W64_32_A_OVR_IRQ_1" newline bitfld.long 0x00 4. "W32_16_A_OVR_IRQ,- NOEFFECT" "W32_16_A_OVR_IRQ_0,W32_16_A_OVR_IRQ_1" bitfld.long 0x00 3. "W64_16_B_OVR_IRQ,- NOEFFECT" "W64_16_B_OVR_IRQ_0,W64_16_B_OVR_IRQ_1" bitfld.long 0x00 2. "W64_16_A_OVR_IRQ,- NOEFFECT" "W64_16_A_OVR_IRQ_0,W64_16_A_OVR_IRQ_1" newline bitfld.long 0x00 1. "W16_64_B_OVR_IRQ,- NOEFFECT" "W16_64_B_OVR_IRQ_0,W16_64_B_OVR_IRQ_1" bitfld.long 0x00 0. "W16_64_A_OVR_IRQ,- NOEFFECT" "W16_64_A_OVR_IRQ_0,W16_64_A_OVR_IRQ_1" width 0x0B tree.end tree.end tree "ISS_SIMCOP_DMA_Module" base ad:0x52020200 tree "DMA_Channel_0" group.long 0x94++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_0,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0xA4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_0,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x90++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_0,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x8C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_0,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x80++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_0,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" newline bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" newline bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" newline bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" newline bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0xA0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_0,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x98++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_0,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x84++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_0,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_0,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" group.long 0x2C++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x20++0x07 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_RAW_j_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" line.long 0x04 "SIMCOP_DMA_IRQSTATUS_j_0,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 0. "BUS_ERR,BUS error" "BUS_ERR_0_r,BUS_ERR_1_w" tree.end tree "DMA_Channel_1" group.long 0xC4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_1,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0xD4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_1,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0xC0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_1,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0xBC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_1,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0xB0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_1,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" newline bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" newline bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" newline bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" newline bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0xD0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_1,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0xC8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_1,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0xB4++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_1,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_1,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" group.long 0x3C++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_CLR_j_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x38++0x03 line.long 0x00 "SIMCOP_DMA_IRQENABLE_SET_j_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" group.long 0x30++0x07 line.long 0x00 "SIMCOP_DMA_IRQSTATUS_RAW_j_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x00 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x00 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x00 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x00 0. "OCP_ERR,OCP error" "OCP_ERR_0_r,OCP_ERR_1_w" line.long 0x04 "SIMCOP_DMA_IRQSTATUS_j_1,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 31. "CHAN7_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN7_FRAME_DONE_IRQ_0_r,CHAN7_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 30. "CHAN6_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN6_FRAME_DONE_IRQ_0_r,CHAN6_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 29. "CHAN5_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN5_FRAME_DONE_IRQ_0_r,CHAN5_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 28. "CHAN4_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN4_FRAME_DONE_IRQ_0_r,CHAN4_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 27. "CHAN3_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN3_FRAME_DONE_IRQ_0_r,CHAN3_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 26. "CHAN2_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN2_FRAME_DONE_IRQ_0_r,CHAN2_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 25. "CHAN1_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN1_FRAME_DONE_IRQ_0_r,CHAN1_FRAME_DONE_IRQ_1_w" bitfld.long 0x04 24. "CHAN0_FRAME_DONE_IRQ,Channel has completed transfer of the full frame" "CHAN0_FRAME_DONE_IRQ_0_r,CHAN0_FRAME_DONE_IRQ_1_w" newline bitfld.long 0x04 23. "CHAN7_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN7_BLOCK_DONE_IRQ_0_r,CHAN7_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 22. "CHAN6_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN6_BLOCK_DONE_IRQ_0_r,CHAN6_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 21. "CHAN5_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN5_BLOCK_DONE_IRQ_0_r,CHAN5_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 20. "CHAN4_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN4_BLOCK_DONE_IRQ_0_r,CHAN4_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 19. "CHAN3_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN3_BLOCK_DONE_IRQ_0_r,CHAN3_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 18. "CHAN2_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN2_BLOCK_DONE_IRQ_0_r,CHAN2_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 17. "CHAN1_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN1_BLOCK_DONE_IRQ_0_r,CHAN1_BLOCK_DONE_IRQ_1_w" bitfld.long 0x04 16. "CHAN0_BLOCK_DONE_IRQ,Channel has completed transfer of one 2D block" "CHAN0_BLOCK_DONE_IRQ_0_r,CHAN0_BLOCK_DONE_IRQ_1_w" newline bitfld.long 0x04 0. "BUS_ERR,BUS error" "BUS_ERR_0_r,BUS_ERR_1_w" tree.end tree "DMA_Channel_2" group.long 0xF4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_2,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x104++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_2,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0xF0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_2,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0xEC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_2,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0xE0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_2,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x100++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_2,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0xF8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_2,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0xE4++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_2,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_2,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end tree "DMA_Channel_3" group.long 0x124++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_3,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x134++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_3,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x120++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_3,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x11C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_3,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x110++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_3,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x130++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_3,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x128++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_3,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x114++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_3,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_3,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end tree "DMA_Channel_4" group.long 0x154++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_4,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x164++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_4,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x150++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_4,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x14C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_4,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x140++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_4,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x160++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_4,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x158++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_4,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x144++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_4,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_4,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end tree "DMA_Channel_5" group.long 0x184++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_5,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x194++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_5,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x180++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_5,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x17C++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_5,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x170++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_5,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x190++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_5,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x188++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_5,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x174++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_5,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_5,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end tree "DMA_Channel_6" group.long 0x1B4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_6,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x1C4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_6,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x1B0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_6,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x1AC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_6,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x1A0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_6,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x1C0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_6,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x1B8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_6,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x1A4++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_6,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_6,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end tree "DMA_Channel_7" group.long 0x1E4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_SIZE_i_7,2D block size" hexmask.long.word 0x00 16.--28. 1. "YNUM,Height in lines per 2D block Valid values are 1- 8191" hexmask.long.word 0x00 4.--13. 1. "XNUM,Width in 128-bit words per 2D block" group.long 0x1F4++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BLOCK_STEP_i_7,Offset between 2D blocks" hexmask.long.word 0x00 16.--29. 1. "YSTEP,Vertical offset in lines between rows of 2D blocks" hexmask.long.word 0x00 4.--14. 1. "XSTEP,Horizontal offset in 128-bit words between 2D block columns" group.long 0x1E0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_ADDR_i_7,SIMCOP memory address" hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Address in 128-bit words" group.long 0x1DC++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_BUF_OFST_i_7,SIMCOP memory line offset" hexmask.long.tbyte 0x00 4.--23. 1. "OFST,Line offset" group.long 0x1D0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CTRL_i_7,Logical channel control register" bitfld.long 0x00 20.--22. "HWSTOP,DMA logical channel HW synchronization" "HWSTOP_0,?,?,?,HWSTOP_4,HWSTOP_5,HWSTOP_6,HWSTOP_7" bitfld.long 0x00 17.--19. "HWSTART,DMA logical channel HW synchronization" "HWSTART_0,?,?,?,HWSTART_4,HWSTART_5,HWSTART_6,HWSTART_7" bitfld.long 0x00 12.--16. "LINKED,DMA logical channel linking" "LINKED_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,LINKED_16,LINKED_17,LINKED_18,LINKED_19,LINKED_20,LINKED_21,LINKED_22,LINKED_23,?,?,?,?,?,?,?,?" bitfld.long 0x00 6. "TILERMODE,Selects OCP transaction breakdown" "TILERMODE_0,TILERMODE_1" bitfld.long 0x00 5. "DIR,Transfer direction" "DIR_0,DIR_1" newline rbitfld.long 0x00 3.--4. "STATUS,SW could poll this bit to know the state of" "STATUS_0_r,STATUS_1_r,STATUS_2_r,STATUS_3_r" bitfld.long 0x00 2. "SWTRIGGER,Software trigger of the DMA channel" "SWTRIGGER_0_w,SWTRIGGER_1_w" bitfld.long 0x00 1. "DISABLE,Disable control of the logical channel" "DISABLE_0_w,DISABLE_1_w" bitfld.long 0x00 0. "ENABLE,Enable control of the logical channel" "ENABLE_0_w,ENABLE_1_w" rgroup.long 0x1F0++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_CURRENT_BLOCK_i_7,SW could read the coordinates of the last transferred block" hexmask.long.word 0x00 16.--25. 1. "BY,Vertical position of the last transferred 2D block in the frame" hexmask.long.word 0x00 0.--9. 1. "BX,Horizontal position of the last transferred 2D block in the frame" group.long 0x1E8++0x03 line.long 0x00 "SIMCOP_DMA_CHAN_FRAME_i_7,Defines a frame" hexmask.long.word 0x00 16.--25. 1. "YCNT,Vertical count of 2D blocks per frame" hexmask.long.word 0x00 0.--9. 1. "XCNT,Horizontal count of 2D blocks per frame" group.long 0x1D4++0x07 line.long 0x00 "SIMCOP_DMA_CHAN_SMEM_ADDR_i_7,System memory address" hexmask.long 0x00 4.--31. 1. "ADDR,Address in 128-bit words" line.long 0x04 "SIMCOP_DMA_CHAN_SMEM_OFST_i_7,System memory line offset in 128-bit words" hexmask.long.word 0x04 4.--19. 1. "OFST,Line offset" tree.end group.long 0x1C++0x03 line.long 0x00 "SIMCOP_DMA_CTRL," hexmask.long.word 0x00 16.--31. 1. "BW_LIMITER,SIMCOP DMA guarantees that there are at least BW_LIMITER functional clock cycles between two OCP requests" bitfld.long 0x00 4.--7. "TAG_CNT,Limits the outstanding transactions count" "TAG_CNT_0,TAG_CNT_1,TAG_CNT_2,TAG_CNT_3,TAG_CNT_4,TAG_CNT_5,TAG_CNT_6,TAG_CNT_7,TAG_CNT_8,TAG_CNT_9,TAG_CNT_10,TAG_CNT_11,TAG_CNT_12,TAG_CNT_13,TAG_CNT_14,TAG_CNT_15" bitfld.long 0x00 3. "POSTED_WRITES,Select write type" "POSTED_WRITES_0,POSTED_WRITES_1" bitfld.long 0x00 0.--1. "MAX_BURST_SIZE,Defines the maximum burst length for INCR bursts" "MAX_BURST_SIZE_0,MAX_BURST_SIZE_1,MAX_BURST_SIZE_2,MAX_BURST_SIZE_3" rgroup.long 0x04++0x03 line.long 0x00 "SIMCOP_DMA_HWINFO,Information about the IP module's hardware configuration. i.e" bitfld.long 0x00 2. "CHAN,Logical" "CHAN_0_r,CHAN_1_r" bitfld.long 0x00 0.--1. "CONTEXT,Maximum outstanding OCP transactions" "CONTEXT_0_r,CONTEXT_1_r,CONTEXT_2_r,?" group.long 0x18++0x03 line.long 0x00 "SIMCOP_DMA_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,?,?" rgroup.long 0x00++0x03 line.long 0x00 "SIMCOP_DMA_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "SIMCOP_DMA_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" width 0x0B tree.end tree "ISS_SIMCOP_Hardware_Sequencer_and_Buffers_Module" base ad:0x52020000 tree "Channel_0" group.long 0x8C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_0,HW sequencer step control register" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0x80++0x07 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_0,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" newline bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" newline bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module - DISABLED" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA - CHAN2" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" newline bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module - DISABLED" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module - DISABLED" "LDC_SYNC_0,LDC_SYNC_1" line.long 0x04 "SIMCOP_HWSEQ_STEP_SWITCH_i_0,Image buffer switch control" bitfld.long 0x04 28.--31. "IMBUFF_H,Switch for image buffer #h - DCT_F" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x04 24.--27. "IMBUFF_G,Switch for image buffer #g - DCT_F" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x04 20.--23. "IMBUFF_F,Switch for image buffer #f - LDC_O" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" bitfld.long 0x04 16.--19. "IMBUFF_E,Switch for image buffer #e - LDC_O" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" newline bitfld.long 0x04 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" bitfld.long 0x04 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" bitfld.long 0x04 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" bitfld.long 0x04 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" tree.end tree "Channel_1" group.long 0x9C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_1,HW sequencer step control register" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0x90++0x07 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_1,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" newline bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" newline bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module - DISABLED" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA - CHAN2" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" newline bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module - DISABLED" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module - DISABLED" "LDC_SYNC_0,LDC_SYNC_1" line.long 0x04 "SIMCOP_HWSEQ_STEP_SWITCH_i_1,Image buffer switch control" bitfld.long 0x04 28.--31. "IMBUFF_H,Switch for image buffer #h - DCT_F" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x04 24.--27. "IMBUFF_G,Switch for image buffer #g - DCT_F" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x04 20.--23. "IMBUFF_F,Switch for image buffer #f - LDC_O" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" bitfld.long 0x04 16.--19. "IMBUFF_E,Switch for image buffer #e - LDC_O" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" newline bitfld.long 0x04 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" bitfld.long 0x04 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" bitfld.long 0x04 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" bitfld.long 0x04 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" tree.end tree "Channel_2" group.long 0xAC++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_2,HW sequencer step control register" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0xA0++0x07 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_2,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" newline bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" newline bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module - DISABLED" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA - CHAN2" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" newline bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module - DISABLED" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module - DISABLED" "LDC_SYNC_0,LDC_SYNC_1" line.long 0x04 "SIMCOP_HWSEQ_STEP_SWITCH_i_2,Image buffer switch control" bitfld.long 0x04 28.--31. "IMBUFF_H,Switch for image buffer #h - DCT_F" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x04 24.--27. "IMBUFF_G,Switch for image buffer #g - DCT_F" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x04 20.--23. "IMBUFF_F,Switch for image buffer #f - LDC_O" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" bitfld.long 0x04 16.--19. "IMBUFF_E,Switch for image buffer #e - LDC_O" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" newline bitfld.long 0x04 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" bitfld.long 0x04 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" bitfld.long 0x04 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" bitfld.long 0x04 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" tree.end tree "Channel_3" group.long 0xBC++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_i_3,HW sequencer step control register" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" newline bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0xB0++0x07 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_i_3,HW sequencer step control register" bitfld.long 0x00 31. "CPU_SYNC,Enable HW synchronization with the CPU so that it could be used for some processing on in the macro-block pipeline" "CPU_SYNC_0,CPU_SYNC_1" bitfld.long 0x00 28.--30. "DMA_OFST,Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000" "DMA_OFST_0,DMA_OFST_1,DMA_OFST_2,DMA_OFST_3,DMA_OFST_4,DMA_OFST_5,DMA_OFST_6,DMA_OFST_7" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" newline bitfld.long 0x00 23. "EXT_SYNC,The HW sequencer waits for an external start pulse i(START_STEP signal) n addition to internally selected synchronization events" "0,1" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" newline bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 9.--10. "NEXT,Next channel in the sync" "NEXT_0,NEXT_1,NEXT_2,NEXT_3" bitfld.long 0x00 8. "VTNF_SYNC,Enable HW synchronization with the VTNF module - DISABLED" "VTNF_SYNC_0,VTNF_SYNC_1" newline bitfld.long 0x00 5.--7. "DMA_SYNC,Enable HW synchronization with the SIMCOP DMA - CHAN2" "DMA_SYNC_0,DMA_SYNC_1,DMA_SYNC_2,DMA_SYNC_3,DMA_SYNC_4,DMA_SYNC_5,DMA_SYNC_6,DMA_SYNC_7" bitfld.long 0x00 4. "ROT_A_SYNC,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_SYNC_0,ROT_A_SYNC_1" bitfld.long 0x00 3. "NSF_SYNC,This bit field is reserved and users should write the reset value to this bit location" "NSF_SYNC_0,NSF_SYNC_1" bitfld.long 0x00 2. "VLCDJ_SYNC,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_SYNC_0,VLCDJ_SYNC_1" newline bitfld.long 0x00 1. "DCT_SYNC,Enable HW synchronization with the DCT module - DISABLED" "DCT_SYNC_0,DCT_SYNC_1" bitfld.long 0x00 0. "LDC_SYNC,Enable HW synchronization with the LDC module - DISABLED" "LDC_SYNC_0,LDC_SYNC_1" line.long 0x04 "SIMCOP_HWSEQ_STEP_SWITCH_i_3,Image buffer switch control" bitfld.long 0x04 28.--31. "IMBUFF_H,Switch for image buffer #h - DCT_F" "IMBUFF_H_0,IMBUFF_H_1,IMBUFF_H_2,IMBUFF_H_3,IMBUFF_H_4,IMBUFF_H_5,IMBUFF_H_6,IMBUFF_H_7,IMBUFF_H_8,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x04 24.--27. "IMBUFF_G,Switch for image buffer #g - DCT_F" "IMBUFF_G_0,IMBUFF_G_1,IMBUFF_G_2,IMBUFF_G_3,IMBUFF_G_4,IMBUFF_G_5,IMBUFF_G_6,IMBUFF_G_7,IMBUFF_G_8,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x04 20.--23. "IMBUFF_F,Switch for image buffer #f - LDC_O" "IMBUFF_F_0,IMBUFF_F_1,IMBUFF_F_2,IMBUFF_F_3,IMBUFF_F_4,IMBUFF_F_5,IMBUFF_F_6,IMBUFF_F_7,IMBUFF_F_8,?,?,?,?,?,?,?" bitfld.long 0x04 16.--19. "IMBUFF_E,Switch for image buffer #e - LDC_O" "IMBUFF_E_0,IMBUFF_E_1,IMBUFF_E_2,IMBUFF_E_3,IMBUFF_E_4,IMBUFF_E_5,IMBUFF_E_6,IMBUFF_E_7,IMBUFF_E_8,?,?,?,?,?,?,?" newline bitfld.long 0x04 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" bitfld.long 0x04 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" bitfld.long 0x04 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" bitfld.long 0x04 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" tree.end group.long 0x68++0x03 line.long 0x00 "SIMCOP_HWSEQ_CTRL,SIMCOP HW sequencer control register" hexmask.long.word 0x00 16.--31. 1. "HW_SEQ_STEP_COUNTER,Number of steps executed by the HW sequencer" bitfld.long 0x00 15. "BBM_LDC,This bit field is reserved and users should write the reset value to this bit location" "BBM_LDC_0,BBM_LDC_1" bitfld.long 0x00 11.--12. "STEP,This register is automatically updated by the HW sequencer when it is active" "STEP_0,STEP_1,STEP_2,STEP_3" newline bitfld.long 0x00 10. "CPU_PROC_DONE,Used by the CPU to tell that it has completed data processing" "CPU_PROC_DONE_0,CPU_PROC_DONE_1" bitfld.long 0x00 8.--9. "BBM_SYNC_CHAN,This bit field is reserved and users should write the reset value to this bit location" "BBM_SYNC_CHAN_0,BBM_SYNC_CHAN_1,BBM_SYNC_CHAN_2,BBM_SYNC_CHAN_3" rbitfld.long 0x00 7. "BBM_STATUS,This bit field is reserved and users should write the reset value to this bit location" "BBM_STATUS_0,BBM_STATUS_1" newline bitfld.long 0x00 4.--6. "BITSTREAM,This bit field is reserved and users should write the reset value to this bit location" "BITSTREAM_0,BITSTREAM_1,BITSTREAM_2,BITSTREAM_3,BITSTREAM_4,BITSTREAM_5,BITSTREAM_6,?" bitfld.long 0x00 2.--3. "BITSTR_XFER_SIZE,This bit field is reserved and users should write the reset value to this bit location" "BITSTR_XFER_SIZE_0,BITSTR_XFER_SIZE_1,BITSTR_XFER_SIZE_2,BITSTR_XFER_SIZE_3" bitfld.long 0x00 1. "HW_SEQ_STOP,Stop the HW sequencer" "HW_SEQ_STOP_0,HW_SEQ_STOP_1" newline bitfld.long 0x00 0. "HW_SEQ_START,Start the HW sequencer" "HW_SEQ_START_0,HW_SEQ_START_1" group.long 0x70++0x03 line.long 0x00 "SIMCOP_HWSEQ_OVERRIDE,HW sequencer override control register" bitfld.long 0x00 19. "VTNF_IO_OFST_OVR," "0,1" bitfld.long 0x00 18. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1" bitfld.long 0x00 17. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1" newline bitfld.long 0x00 16. "IMBUFF_H," "IMBUFF_H_0,IMBUFF_H_1" bitfld.long 0x00 15. "IMBUFF_G," "IMBUFF_G_0,IMBUFF_G_1" bitfld.long 0x00 14. "IMBUFF_F," "IMBUFF_F_0,IMBUFF_F_1" newline bitfld.long 0x00 13. "IMBUFF_E," "IMBUFF_E_0,IMBUFF_E_1" bitfld.long 0x00 12. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1" bitfld.long 0x00 11. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1" newline bitfld.long 0x00 10. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1" bitfld.long 0x00 9. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1" bitfld.long 0x00 8. "LDC_O_OFST_OVR," "LDC_O_OFST_OVR_0,LDC_O_OFST_OVR_1" newline bitfld.long 0x00 7. "ROT_O_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_OVR_0,ROT_O_OFST_OVR_1" bitfld.long 0x00 6. "ROT_I_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_OVR_0,ROT_I_OFST_OVR_1" bitfld.long 0x00 5. "NSF_IO_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "NSF_IO_OFST_OVR_0,NSF_IO_OFST_OVR_1" newline bitfld.long 0x00 4. "DCT_F_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_OVR_0,DCT_F_OFST_OVR_1" bitfld.long 0x00 3. "DCT_S_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_OVR_0,DCT_S_OFST_OVR_1" bitfld.long 0x00 2. "VLCDJ_IO_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_OVR_0,VLCDJ_IO_OFST_OVR_1" newline bitfld.long 0x00 1. "IMX_B_D_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_OVR_0,IMX_B_D_OFST_OVR_1" bitfld.long 0x00 0. "IMX_A_D_OFST_OVR,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_OVR_0,IMX_A_D_OFST_OVR_1" rgroup.long 0x6C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STATUS,HW sequencer status register" hexmask.long.word 0x00 16.--31. 1. "HW_SEQ_STEP_COUNTER,Current step number" bitfld.long 0x00 0. "STATE,Current state - IDLE" "STATE_0,STATE_1" group.long 0x7C++0x03 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL2_OVERRIDE,HW sequencer override register" bitfld.long 0x00 12.--13. "VTNF_IO_OFST,Controls VTNF_IO bus mapping to image buffers: 0x0000" "VTNF_IO_OFST_0,VTNF_IO_OFST_1,VTNF_IO_OFST_2,VTNF_IO_OFST_3" bitfld.long 0x00 10.--11. "NSF2_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "NSF2_IO_OFST_0,NSF2_IO_OFST_1,NSF2_IO_OFST_2,NSF2_IO_OFST_3" bitfld.long 0x00 8.--9. "LDC_O_OFST,Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000" "LDC_O_OFST_0,LDC_O_OFST_1,LDC_O_OFST_2,LDC_O_OFST_3" newline bitfld.long 0x00 4.--6. "COEFF_B,This bit field is reserved and users should write the reset value to this bit location" "COEFF_B_0,COEFF_B_1,COEFF_B_2,COEFF_B_3,COEFF_B_4,COEFF_B_5,COEFF_B_6,COEFF_B_7" bitfld.long 0x00 0.--2. "COEFF_A,This bit field is reserved and users should write the reset value to this bit location" "COEFF_A_0,COEFF_A_1,COEFF_A_2,COEFF_A_3,COEFF_A_4,COEFF_A_5,COEFF_A_6,COEFF_A_7" group.long 0x74++0x07 line.long 0x00 "SIMCOP_HWSEQ_STEP_CTRL_OVERRIDE,HW sequencer override register" bitfld.long 0x00 26.--27. "ROT_O_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_O_OFST_0,ROT_O_OFST_1,ROT_O_OFST_2,ROT_O_OFST_3" bitfld.long 0x00 24.--25. "ROT_I_OFST,This bit field is reserved and users should write the reset value to this bit location" "ROT_I_OFST_0,ROT_I_OFST_1,ROT_I_OFST_2,ROT_I_OFST_3" bitfld.long 0x00 20.--22. "DCT_F_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_F_OFST_0,DCT_F_OFST_1,DCT_F_OFST_2,DCT_F_OFST_3,DCT_F_OFST_4,DCT_F_OFST_5,?,?" newline bitfld.long 0x00 18.--19. "DCT_S_OFST,This bit field is reserved and users should write the reset value to this bit location" "DCT_S_OFST_0,DCT_S_OFST_1,DCT_S_OFST_2,DCT_S_OFST_3" bitfld.long 0x00 15.--17. "VLCDJ_IO_OFST,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_IO_OFST_0,VLCDJ_IO_OFST_1,VLCDJ_IO_OFST_2,VLCDJ_IO_OFST_3,VLCDJ_IO_OFST_4,VLCDJ_IO_OFST_5,?,?" bitfld.long 0x00 13.--14. "IMX_B_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_D_OFST_0,IMX_B_D_OFST_1,IMX_B_D_OFST_2,IMX_B_D_OFST_3" newline bitfld.long 0x00 11.--12. "IMX_A_D_OFST,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_D_OFST_0,IMX_A_D_OFST_1,IMX_A_D_OFST_2,IMX_A_D_OFST_3" bitfld.long 0x00 8. "VTNF_TRIGGER,SW controlled START/DONE synchronization - WZERO" "VTNF_TRIGGER_0,VTNF_TRIGGER_1" bitfld.long 0x00 5.--7. "DMA_TRIGGER,SW controlled START/DONE synchronization - CHAN2" "DMA_TRIGGER_0,DMA_TRIGGER_1,DMA_TRIGGER_2,DMA_TRIGGER_3,DMA_TRIGGER_4,DMA_TRIGGER_5,DMA_TRIGGER_6,DMA_TRIGGER_7" newline bitfld.long 0x00 4. "ROT_A_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_TRIGGER_0,ROT_A_TRIGGER_1" bitfld.long 0x00 3. "NSF_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "NSF_TRIGGER_0,NSF_TRIGGER_1" bitfld.long 0x00 2. "VLCDJ_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_TRIGGER_0,VLCDJ_TRIGGER_1" newline bitfld.long 0x00 1. "DCT_TRIGGER,This bit field is reserved and users should write the reset value to this bit location" "DCT_TRIGGER_0,DCT_TRIGGER_1" bitfld.long 0x00 0. "LDC_TRIGGER,SW controlled START/DONE synchronization - WZERO" "LDC_TRIGGER_0,LDC_TRIGGER_1" line.long 0x04 "SIMCOP_HWSEQ_STEP_SWITCH_OVERRIDE,HW sequencer override register" bitfld.long 0x04 28.--31. "IMBUFF_H,Switch for image buffer #h - COPR" "IMBUFF_H_0,IMBUFF_H_1,?,?,?,?,?,?,?,IMBUFF_H_9,IMBUFF_H_10,?,?,?,?,?" bitfld.long 0x04 24.--27. "IMBUFF_G,Switch for image buffer #g - COPR" "IMBUFF_G_0,IMBUFF_G_1,?,?,?,?,?,?,?,IMBUFF_G_9,IMBUFF_G_10,?,?,?,?,?" bitfld.long 0x04 20.--23. "IMBUFF_F,Switch for image buffer #f - COPR" "IMBUFF_F_0,IMBUFF_F_1,?,?,?,?,IMBUFF_F_6,?,IMBUFF_F_8,?,?,?,?,?,?,?" newline bitfld.long 0x04 16.--19. "IMBUFF_E,Switch for image buffer #e - COPR" "IMBUFF_E_0,IMBUFF_E_1,?,?,?,?,IMBUFF_E_6,?,IMBUFF_E_8,?,?,?,?,?,?,?" bitfld.long 0x04 12.--14. "IMBUFF_D,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_D_0,IMBUFF_D_1,IMBUFF_D_2,IMBUFF_D_3,IMBUFF_D_4,IMBUFF_D_5,IMBUFF_D_6,IMBUFF_D_7" bitfld.long 0x04 8.--10. "IMBUFF_C,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_C_0,IMBUFF_C_1,IMBUFF_C_2,IMBUFF_C_3,IMBUFF_C_4,IMBUFF_C_5,IMBUFF_C_6,IMBUFF_C_7" newline bitfld.long 0x04 4.--6. "IMBUFF_B,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_B_0,IMBUFF_B_1,IMBUFF_B_2,IMBUFF_B_3,IMBUFF_B_4,IMBUFF_B_5,IMBUFF_B_6,IMBUFF_B_7" bitfld.long 0x04 0.--2. "IMBUFF_A,This bit field is reserved and users should write the reset value to this bit location" "IMBUFF_A_0,IMBUFF_A_1,IMBUFF_A_2,IMBUFF_A_3,IMBUFF_A_4,IMBUFF_A_5,IMBUFF_A_6,IMBUFF_A_7" width 0x0B tree.end tree "ISS_SIMCOP_LDC_Module" base ad:0x52020100 rgroup.long 0x00++0x2B line.long 0x00 "LDC_PID,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "LDC_PCR,LDC Peripheral Control" bitfld.long 0x04 16.--17. "STANDBYMODE,Configuration of the local initiator state management mode" "0,1,2,3" rbitfld.long 0x04 11. "SCS_SUPPORT,Reports '1' if SCS feature is supported by LDC" "0,1" newline bitfld.long 0x04 10. "AFF_EXPANDEN,Enables expanded format of affine warp coefficients (A B D and E)" "A B D E are treated as S14Q12,A B D E are treated as S16Q12" bitfld.long 0x04 9. "CIRCEN,Enables circular addressing mode" "Disable circular addressing for input data,Enable circular addressing" newline bitfld.long 0x04 8. "SCSEN,Enable/Disable smart codec statistic (SCS) function" "Disable SCS,Enable SCS" bitfld.long 0x04 7. "PWARPEN,Enable perspective warp transform" "0,1" newline bitfld.long 0x04 5.--6. "BMODE,Bayer data format (only applicable when MODE=1)" "Unpacked 12-bit data in/out,Packed 12-bit data in/out,Packed 8-bit data in/out,A-law data in/out" bitfld.long 0x04 3.--4. "MODE," "YCbCr 4:2:2 Lens Distortion,Bayer chromatic aberration mode,?..." newline bitfld.long 0x04 2. "BUSY,Idle/busy status " "Idle,Busy.." bitfld.long 0x04 1. "LDMAPEN,LD Mapping Enable " "Disabled,Enabled" newline bitfld.long 0x04 0. "EN,Write 1 to start the function as specified in MODE" "EN_0,EN_1" line.long 0x08 "LDC_RD_BASE,LDC Read Frame Base" line.long 0x0C "LDC_RD_OFST," hexmask.long.word 0x0C 16.--29. 1. "MOD,Sets the circular buffer size if circular buffering mode is used" hexmask.long.word 0x0C 0.--15. 1. "ROFST,Read frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x10 "LDC_FRAME_SIZE,LDC Frame Size" hexmask.long.word 0x10 16.--29. 1. "H,Frame number of lines" hexmask.long.word 0x10 0.--13. 1. "W,Frame width" line.long 0x14 "LDC_INITXY,LDC Initial XY" hexmask.long.word 0x14 16.--29. 1. "INITY,Output starting Y-coordinate (must be even)" hexmask.long.word 0x14 0.--13. 1. "INITX,Output starting X-coordiinate (must be even)" line.long 0x18 "LDC_WR_BASE,LDC Write Frame Base" line.long 0x1C "LDC_WR_OFST,LDC Write Frame Line Offset" hexmask.long.word 0x1C 0.--15. 1. "WOFST,Write frame line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x20 "LDC_420C_RD_BASE,LDC Read Frame Base For Cb/Cr in 420 Mode" line.long 0x24 "LDC_420C_WR_BASE,LDC Write Frame Base for Cb/Cr in 420 Mode" line.long 0x28 "LDC_CONFIG,LDC Configuration" bitfld.long 0x28 7. "CNST_MD,Constant output address mode" "CNST_MD_0,CNST_MD_1" bitfld.long 0x28 6. "YINT_TYP,Interpolation type for Y data " "bicubic,bilinear" newline bitfld.long 0x28 4.--5. "INITC,Initial color for LD back mapping (Bayer mode only) " "R,Gr,Gb,B" group.long 0x34++0x03 line.long 0x00 "LDC_BLOCK,LDC Block Size" bitfld.long 0x00 16.--19. "PIXPAD,Pixel pad (must be greater than 1)" "PIXPAD_0,PIXPAD_1,PIXPAD_2,PIXPAD_3,PIXPAD_4,PIXPAD_5,PIXPAD_6,PIXPAD_7,PIXPAD_8,PIXPAD_9,PIXPAD_10,PIXPAD_11,PIXPAD_12,PIXPAD_13,PIXPAD_14,PIXPAD_15" hexmask.long.byte 0x00 8.--15. 1. "OBH,Output block height (must be 0 and even)" newline hexmask.long.byte 0x00 0.--7. 1. "OBW,Output block width (must be 0 and multiple of 8 in 422 mode or in 420 mode 16 or in Bayer mode 8 16 or 32 depending on Bayer format)" group.long 0x44++0x23 line.long 0x00 "LDC_AB,LDC Affine Transwarp A/B" hexmask.long.word 0x00 16.--31. 1. "B,Affine transwarp B (S16Q12)" hexmask.long.word 0x00 0.--15. 1. "A,Affine transwarp A (S16Q12)" line.long 0x04 "LDC_CD,LDC Affine Transwarp C/D" hexmask.long.word 0x04 16.--31. 1. "D,Affine transwarp D (S16Q12)" hexmask.long.word 0x04 0.--15. 1. "C,Affine transwarp C (S16Q3)" line.long 0x08 "LDC_EF,LDC Affine Transwarp EF" hexmask.long.word 0x08 16.--31. 1. "F,Affine transwarp F (S16Q3)" hexmask.long.word 0x08 0.--15. 1. "E,Affine transwarp E (S16Q12)" line.long 0x0C "LDC_GH,LDC Perspective Transformation Parameters. G and H" hexmask.long.word 0x0C 16.--31. 1. "H,Perspective Transformation H (S16Q23)" hexmask.long.word 0x0C 0.--15. 1. "G,Perspective Transformation G (S16Q23)" line.long 0x10 "LDC_SCS_CTL,Define number of regions and output divider for region based statistics" hexmask.long.word 0x10 16.--29. 1. "SLICE_SIZE,Sets the number of output lines computed by LDC before the computed macroblock row statistics are transferred to system memory" bitfld.long 0x10 5.--6. "REGION,Sets the number of regions in both directions for the region based statistics" "0,1,2,3" newline bitfld.long 0x10 0.--4. "ACCSHIFT,Sets the output divider for sum of pixels in a region and sum of squares of pixels in a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "LDC_INPUT_FRAME_SIZE,Defines the total input frame size" hexmask.long.word 0x14 16.--29. 1. "H,Height of input image" hexmask.long.word 0x14 0.--13. 1. "W,Width of input image" line.long 0x18 "LDC_MESHTABLE_BASE,Read address for mesh offset table" line.long 0x1C "LDC_MESHTABLE_OFST,Defines the stride between rows for the offset table (in bytes)" hexmask.long.word 0x1C 0.--15. 1. "OFST,LDC Mesh table line offset must be 16-byte aligned so internally [3:0] bits are hard-wired zero" line.long 0x20 "LDC_MESHTABLE_CONFIG,Defines the downsampling factors used for the mesh offset tables" bitfld.long 0x20 0.--2. "M,Mesh table downsampling factor" "?,2 -..,4,8,16,32,64,128" width 0x0B tree.end tree "ISS_SIMCOP_Overview" base ad:0x52020000 tree "IRQ_Line_0" group.long 0x2C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_0,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x28++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_0,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x20++0x07 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_0,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" line.long 0x04 "SIMCOP_HL_IRQSTATUS_i_0,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x04 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x04 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x04 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x04 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x04 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x04 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x04 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x04 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x04 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x04 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x04 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" tree.end tree "IRQ_Line_1" group.long 0x3C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_1,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x38++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_1,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x30++0x07 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_1,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" line.long 0x04 "SIMCOP_HL_IRQSTATUS_i_1,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x04 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x04 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x04 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x04 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x04 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x04 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x04 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x04 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x04 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x04 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x04 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" tree.end tree "IRQ_Line_2" group.long 0x4C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_2,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x48++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_2,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x40++0x07 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_2,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" line.long 0x04 "SIMCOP_HL_IRQSTATUS_i_2,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x04 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x04 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x04 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x04 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x04 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x04 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x04 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x04 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x04 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x04 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x04 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" tree.end tree "IRQ_Line_3" group.long 0x5C++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_CLR_i_3,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x58++0x03 line.long 0x00 "SIMCOP_HL_IRQENABLE_SET_i_3,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" bitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline bitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" group.long 0x50++0x07 line.long 0x00 "SIMCOP_HL_IRQSTATUS_RAW_i_3,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x00 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x00 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x00 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x00 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x00 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x00 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x00 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x00 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x00 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x00 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x00 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x00 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x00 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location.Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer" "0,1" bitfld.long 0x00 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x00 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" line.long 0x04 "SIMCOP_HL_IRQSTATUS_i_3,Per-event 'enabled' interrupt status vector Enabled status isn't set unless event is enabled" bitfld.long 0x04 19. "CPU_PROC_START_IRQ,Event triggered by the HW sequencer to instruct the CPU to process a macro block - NOACTION" "CPU_PROC_START_IRQ_0,CPU_PROC_START_IRQ_1" rbitfld.long 0x04 18. "SIMCOP_DMA_IRQ1,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ1_0,SIMCOP_DMA_IRQ1_1" bitfld.long 0x04 16. "OCP_ERR_IRQ,An OCP error has been received on the OCPMB master port" "OCP_ERR_IRQ_0,OCP_ERR_IRQ_1" newline rbitfld.long 0x04 15. "VLCDJ_DECODE_ERR_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 14. "DONE_IRQ,Event triggered when the HW sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received" "DONE_IRQ_0,DONE_IRQ_1" bitfld.long 0x04 13. "STEP3_IRQ,Event triggered when STEP3 is activated by the HW sequencer - NOACTION" "STEP3_IRQ_0,STEP3_IRQ_1" newline bitfld.long 0x04 12. "STEP2_IRQ,Event triggered when STEP2 is activated by the HW sequencer - NOACTION" "STEP2_IRQ_0,STEP2_IRQ_1" bitfld.long 0x04 11. "STEP1_IRQ,Event triggered when STEP1 is activated by the HW sequencer - NOACTION" "STEP1_IRQ_0,STEP1_IRQ_1" bitfld.long 0x04 10. "STEP0_IRQ,Event triggered when STEP0 is activated by the HW sequencer - NOACTION" "STEP0_IRQ_0,STEP0_IRQ_1" newline bitfld.long 0x04 9. "LDC_BLOCK_IRQ,This event is triggered by LDC when a macro-block has been processed - NOACTION" "LDC_BLOCK_IRQ_0,LDC_BLOCK_IRQ_1" bitfld.long 0x04 8. "VTNF_IRQ,Event triggered by the VTNF imaging accelerator when processing of a block is done" "VTNF_IRQ_0,VTNF_IRQ_1" rbitfld.long 0x04 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 6. "IMX_B_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 5. "IMX_A_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 4. "NSF_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" newline rbitfld.long 0x04 3. "VLCDJ_BLOC_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" rbitfld.long 0x04 2. "DCT_IRQ,This bit field is reserved and users should write the reset value to this bit location" "0,1" bitfld.long 0x04 1. "LDC_FRAME_IRQ,This event is triggered by LDC when a full frame has been processed - NOACTION" "LDC_FRAME_IRQ_0,LDC_FRAME_IRQ_1" newline rbitfld.long 0x04 0. "SIMCOP_DMA_IRQ0,Event triggered by the SIMCOP DMA" "SIMCOP_DMA_IRQ0_0,SIMCOP_DMA_IRQ0_1" tree.end group.long 0x64++0x03 line.long 0x00 "SIMCOP_CLKCTRL,SIMCOP clock control register" bitfld.long 0x00 9. "VTNF,VTNF - WOFF" "VTNF_0,VTNF_1" bitfld.long 0x00 7. "ROT_A,This bit field is reserved and users should write the reset value to this bit location" "ROT_A_0,ROT_A_1" newline bitfld.long 0x00 6. "IMX_B,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_0,IMX_B_1" bitfld.long 0x00 5. "IMX_A,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_0,IMX_A_1" newline bitfld.long 0x00 4. "NSF2,This bit field is reserved and users should write the reset value to this bit location" "NSF2_0,NSF2_1" bitfld.long 0x00 3. "VLCDJ,This bit field is reserved and users should write the reset value to this bit location" "VLCDJ_0,VLCDJ_1" newline bitfld.long 0x00 2. "DCT,This bit field is reserved and users should write the reset value to this bit location" "DCT_0,DCT_1" bitfld.long 0x00 1. "LDC,LDC - WOFF" "LDC_0,LDC_1" newline bitfld.long 0x00 0. "DMA,DMA - WOFF" "DMA_0,DMA_1" group.long 0x60++0x03 line.long 0x00 "SIMCOP_CTRL,SIMCOP control register" bitfld.long 0x00 28. "LDC_R_BURST_BREAK,Controls if bursts issued by LDC bridge could cross burst length boundaries" "LDC_R_BURST_BREAK_0,LDC_R_BURST_BREAK_1" bitfld.long 0x00 26.--27. "LDC_R_MAX_BURST_LENGTH,Limits the maximum burst length that could be used by LDC - B128" "LDC_R_MAX_BURST_LENGTH_0,LDC_R_MAX_BURST_LENGTH_1,LDC_R_MAX_BURST_LENGTH_2,LDC_R_MAX_BURST_LENGTH_3" newline bitfld.long 0x00 21.--24. "LDC_R_TAG_CNT,Limits the maximum number of outstanding LDC requests to LDC_R_TAG_CNT+1" "LDC_R_TAG_CNT_0,LDC_R_TAG_CNT_1,LDC_R_TAG_CNT_2,LDC_R_TAG_CNT_3,LDC_R_TAG_CNT_4,LDC_R_TAG_CNT_5,LDC_R_TAG_CNT_6,LDC_R_TAG_CNT_7,LDC_R_TAG_CNT_8,LDC_R_TAG_CNT_9,LDC_R_TAG_CNT_10,LDC_R_TAG_CNT_11,LDC_R_TAG_CNT_12,LDC_R_TAG_CNT_13,LDC_R_TAG_CNT_14,LDC_R_TAG_CNT_15" bitfld.long 0x00 16.--19. "LDC_R_TAG_OFST,Reserved" "LDC_R_TAG_OFST_0,LDC_R_TAG_OFST_1,LDC_R_TAG_OFST_2,LDC_R_TAG_OFST_3,LDC_R_TAG_OFST_4,LDC_R_TAG_OFST_5,LDC_R_TAG_OFST_6,LDC_R_TAG_OFST_7,LDC_R_TAG_OFST_8,LDC_R_TAG_OFST_9,LDC_R_TAG_OFST_10,LDC_R_TAG_OFST_11,LDC_R_TAG_OFST_12,LDC_R_TAG_OFST_13,LDC_R_TAG_OFST_14,LDC_R_TAG_OFST_15" newline bitfld.long 0x00 14. "IMX_B_CMD,This bit field is reserved and users should write the reset value to this bit location" "IMX_B_CMD_0,IMX_B_CMD_1" bitfld.long 0x00 12.--13. "IMX_A_CMD,This bit field is reserved and users should write the reset value to this bit location" "IMX_A_CMD_0,IMX_A_CMD_1,IMX_A_CMD_2,?" newline bitfld.long 0x00 11. "HUFF,This bit field is reserved and users should write the reset value to this bit location" "HUFF_0,HUFF_1" bitfld.long 0x00 10. "QUANT,This bit field is reserved and users should write the reset value to this bit location" "QUANT_0,QUANT_1" newline bitfld.long 0x00 6.--7. "LDC_INPUT,This bit field is reserved and users should write the reset value to this bit location" "LDC_INPUT_0,LDC_INPUT_1,LDC_INPUT_2,LDC_INPUT_3" bitfld.long 0x00 4.--5. "NSF_WMEM,This bit field is reserved and users should write the reset value to this bit location" "NSF_WMEM_0,NSF_WMEM_1,NSF_WMEM_2,NSF_WMEM_3" newline bitfld.long 0x00 3. "IRQ3_MODE,Interrupt generation method - OR" "IRQ3_MODE_0,IRQ3_MODE_1" bitfld.long 0x00 2. "IRQ2_MODE,Interrupt generation method - OR" "IRQ2_MODE_0,IRQ2_MODE_1" newline bitfld.long 0x00 1. "IRQ1_MODE,Interrupt generation method - OR" "IRQ1_MODE_0,IRQ1_MODE_1" bitfld.long 0x00 0. "IRQ0_MODE,Interrupt generation method - OR" "IRQ0_MODE_0,IRQ0_MODE_1" group.long 0xFC++0x03 line.long 0x00 "SIMCOP_CTRL2,Simcop control register" abitfld.long 0x00 0.--11. "LDCR_BW_CTRL,Limits the mean bandwidth (computed over one block) that the LDC module can request for read from system memory" "0x000=The BW limiter is bypassed 1~4095,0x001=1.6 MBytes/s @ 426 MHz,0xFFF=6.8 GBytes/s @ 426 Mhz" rgroup.long 0x04++0x03 line.long 0x00 "SIMCOP_HL_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x00 16. "VTNF_ENABLE,The VTNF module is present when this parameter is set" "0,1" bitfld.long 0x00 14.--15. "LDCIMXNSF_BOOST,- ZERO" "LDCIMXNSF_BOOST_0,LDCIMXNSF_BOOST_1,LDCIMXNSF_BOOST_2,LDCIMXNSF_BOOST_3" newline bitfld.long 0x00 8.--9. "IMAGE_BUFFERS,This parameter defines the image buffer count" "IMAGE_BUFFERS_0,IMAGE_BUFFERS_1,?,?" bitfld.long 0x00 7. "NSF3_ENABLE,The NSF3 module is present when this parameter is set" "NSF3_ENABLE_0,NSF3_ENABLE_1" newline bitfld.long 0x00 6. "ROT_A_ENABLE,The ROT #a module is present when this parameter is set" "ROT_A_ENABLE_0,ROT_A_ENABLE_1" bitfld.long 0x00 5. "IMX_B_ENABLE,The iMX #b module and the CMD#b COEFF#b memories are present when this parameter is set" "IMX_B_ENABLE_0,IMX_B_ENABLE_1" newline bitfld.long 0x00 4. "IMX_A_ENABLE,The iMX #a module and the CMD#a COEFF#a memories are present when this parameter is set" "IMX_A_ENABLE_0,IMX_A_ENABLE_1" bitfld.long 0x00 3. "NSF_ENABLE,The NSF2 module is present when this parameter is set" "NSF_ENABLE_0,NSF_ENABLE_1" newline bitfld.long 0x00 2. "VLCDJ_ENABLE,The VLCD module and the QUANT HUFFMAN BITSTREAM memories are present when this parameter is set" "VLCDJ_ENABLE_0,VLCDJ_ENABLE_1" bitfld.long 0x00 1. "DCT_ENABLE,The DCT module is present when this parameter is set" "DCT_ENABLE_0,DCT_ENABLE_1" newline bitfld.long 0x00 0. "LDC_ENABLE,The LDC module and the LDC LUT are present when this parameter is set" "LDC_ENABLE_0,LDC_ENABLE_1" group.long 0x1C++0x03 line.long 0x00 "SIMCOP_HL_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3" rgroup.long 0x00++0x03 line.long 0x00 "SIMCOP_HL_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "SIMCOP_HL_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 0. "SOFTRESET,Software reset - DONE" "SOFTRESET_0,SOFTRESET_1" width 0x0B tree.end tree "ISS_SIMCOP_VTNF_Module" tree "VTNF" base ad:0x52020A00 rgroup.long 0x00++0x63 line.long 0x00 "VTNF_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "VTNF_CTRL,Control" bitfld.long 0x04 16. "BUSY,Idle/busy status (read-only)" "idle,busy" bitfld.long 0x04 10. "AUTOGATING,Internal clock gating on OCP clock and functional clock" "clocks are free-running,clocks are gated off in subblocks that are not.." bitfld.long 0x04 9. "TRIG_SRC,Starting mechanism trigger source" "software writing 1 to EN,HW sequencer sending pulse on START signal" newline bitfld.long 0x04 8. "INTEN,Interrupt enable" "disable,enable" bitfld.long 0x04 0. "EN,Write 1 when TRIG_SRC=0 to start module operation" "0,1" line.long 0x08 "VTNF_CFG," bitfld.long 0x08 4.--7. "T,Round-down number of bits for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0. "FMT,Previous frame output and current frame output format" "NV12,YV12" line.long 0x0C "VTNF_SZ,Configuration" hexmask.long.word 0x0C 16.--31. 1. "BLKH,Block height valid range 4..128 multiple of 4" hexmask.long.word 0x0C 0.--15. 1. "BLKW,Block width valid range 32..512 multiple of 32" line.long 0x10 "VTNF_CADR,Current frame input byte address" hexmask.long.word 0x10 4.--15. 1. "ADDR,Address in 128-bit words" line.long 0x14 "VTNF_PADR,Previous frame output byte address" hexmask.long.word 0x14 4.--15. 1. "ADDR,Address in 128-bit words" line.long 0x18 "VTNF_OADR,Current frame output byte address" hexmask.long.word 0x18 4.--15. 1. "ADDR,Address in 128-bit words" line.long 0x1C "VTNF_LOFST,Line offset for C. P. O arrays" hexmask.long.word 0x1C 4.--15. 1. "LOFST,Line offset in 128-bit words" line.long 0x20 "VTNF_WEIGHTS,Weights for SAD calculation" bitfld.long 0x20 16.--21. "W2,W2 parameter chroma weight for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x20 0.--5. "W1,W1 oarameter luma weight for SAD calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "VTNF_LUT1_0,Lookup table 1" hexmask.long.byte 0x24 24.--31. 1. "LUT1_3,LUT1[3]" hexmask.long.byte 0x24 16.--23. 1. "LUT1_2,LUT1[2]" hexmask.long.byte 0x24 8.--15. 1. "LUT1_1,LUT1[1]" newline hexmask.long.byte 0x24 0.--7. 1. "LUT1_0,LUT1[0]" line.long 0x28 "VTNF_LUT1_4,Lookup table 1" hexmask.long.byte 0x28 24.--31. 1. "LUT1_7,LUT1[7]" hexmask.long.byte 0x28 16.--23. 1. "LUT1_6,LUT1[6]" hexmask.long.byte 0x28 8.--15. 1. "LUT1_5,LUT1[5]" newline hexmask.long.byte 0x28 0.--7. 1. "LUT1_4,LUT1[4]" line.long 0x2C "VTNF_LUT1_8,Lookup table 1" hexmask.long.byte 0x2C 24.--31. 1. "LUT1_11,LUT1[11]" hexmask.long.byte 0x2C 16.--23. 1. "LUT1_10,LUT1[10]" hexmask.long.byte 0x2C 8.--15. 1. "LUT1_9,LUT1[9]" newline hexmask.long.byte 0x2C 0.--7. 1. "LUT1_8,LUT1[8]" line.long 0x30 "VTNF_LUT1_12,Lookup table 1" hexmask.long.byte 0x30 24.--31. 1. "LUT1_15,LUT1[15]" hexmask.long.byte 0x30 16.--23. 1. "LUT1_14,LUT1[14]" hexmask.long.byte 0x30 8.--15. 1. "LUT1_13,LUT1[13]" newline hexmask.long.byte 0x30 0.--7. 1. "LUT1_12,LUT1[12]" line.long 0x34 "VTNF_LUT1_16,Lookup table 1" hexmask.long.byte 0x34 24.--31. 1. "LUT1_19,LUT1[19]" hexmask.long.byte 0x34 16.--23. 1. "LUT1_18,LUT1[18]" hexmask.long.byte 0x34 8.--15. 1. "LUT1_17,LUT1[17]" newline hexmask.long.byte 0x34 0.--7. 1. "LUT1_16,LUT1[16]" line.long 0x38 "VTNF_LUT1_20,Lookup table 1" hexmask.long.byte 0x38 24.--31. 1. "LUT1_23,LUT1[23]" hexmask.long.byte 0x38 16.--23. 1. "LUT1_22,LUT1[22]" hexmask.long.byte 0x38 8.--15. 1. "LUT1_21,LUT1[21]" newline hexmask.long.byte 0x38 0.--7. 1. "LUT1_20,LUT1[20]" line.long 0x3C "VTNF_LUT1_24,Lookup table 1" hexmask.long.byte 0x3C 24.--31. 1. "LUT1_27,LUT1[27]" hexmask.long.byte 0x3C 16.--23. 1. "LUT1_26,LUT1[26]" hexmask.long.byte 0x3C 8.--15. 1. "LUT1_25,LUT1[25]" newline hexmask.long.byte 0x3C 0.--7. 1. "LUT1_24,LUT1[24]" line.long 0x40 "VTNF_LUT1_28,Lookup table 1" hexmask.long.byte 0x40 24.--31. 1. "LUT1_31,LUT1[31]" hexmask.long.byte 0x40 16.--23. 1. "LUT1_30,LUT1[30]" hexmask.long.byte 0x40 8.--15. 1. "LUT1_29,LUT1[29]" newline hexmask.long.byte 0x40 0.--7. 1. "LUT1_28,LUT1[28]" line.long 0x44 "VTNF_LUT2_0,Lookup table 1" hexmask.long.byte 0x44 24.--31. 1. "LUT2_3,LUT2[3]" hexmask.long.byte 0x44 16.--23. 1. "LUT2_2,LUT2[2]" hexmask.long.byte 0x44 8.--15. 1. "LUT2_1,LUT2[1]" newline hexmask.long.byte 0x44 0.--7. 1. "LUT2_0,LUT2[0]" line.long 0x48 "VTNF_LUT2_4,Lookup table 1" hexmask.long.byte 0x48 24.--31. 1. "LUT2_7,LUT2[7]" hexmask.long.byte 0x48 16.--23. 1. "LUT2_6,LUT2[6]" hexmask.long.byte 0x48 8.--15. 1. "LUT2_5,LUT2[5]" newline hexmask.long.byte 0x48 0.--7. 1. "LUT2_4,LUT2[4]" line.long 0x4C "VTNF_LUT2_8,Lookup table 1" hexmask.long.byte 0x4C 24.--31. 1. "LUT2_11,LUT2[11]" hexmask.long.byte 0x4C 16.--23. 1. "LUT2_10,LUT2[10]" hexmask.long.byte 0x4C 8.--15. 1. "LUT2_9,LUT2[9]" newline hexmask.long.byte 0x4C 0.--7. 1. "LUT2_8,LUT2[8]" line.long 0x50 "VTNF_LUT2_12,Lookup table 1" hexmask.long.byte 0x50 24.--31. 1. "LUT2_15,LUT2[15]" hexmask.long.byte 0x50 16.--23. 1. "LUT2_14,LUT2[14]" hexmask.long.byte 0x50 8.--15. 1. "LUT2_13,LUT2[13]" newline hexmask.long.byte 0x50 0.--7. 1. "LUT2_12,LUT2[12]" line.long 0x54 "VTNF_LUT2_16,Lookup table 1" hexmask.long.byte 0x54 24.--31. 1. "LUT2_19,LUT2[19]" hexmask.long.byte 0x54 16.--23. 1. "LUT2_18,LUT2[18]" hexmask.long.byte 0x54 8.--15. 1. "LUT2_17,LUT2[17]" newline hexmask.long.byte 0x54 0.--7. 1. "LUT2_16,LUT2[16]" line.long 0x58 "VTNF_LUT2_20,Lookup table 1" hexmask.long.byte 0x58 24.--31. 1. "LUT2_23,LUT2[23]" hexmask.long.byte 0x58 16.--23. 1. "LUT2_22,LUT2[22]" hexmask.long.byte 0x58 8.--15. 1. "LUT2_21,LUT2[21]" newline hexmask.long.byte 0x58 0.--7. 1. "LUT2_20,LUT2[20]" line.long 0x5C "VTNF_LUT2_24,Lookup table 1" hexmask.long.byte 0x5C 24.--31. 1. "LUT2_27,LUT2[27]" hexmask.long.byte 0x5C 16.--23. 1. "LUT2_26,LUT2[26]" hexmask.long.byte 0x5C 8.--15. 1. "LUT2_25,LUT2[25]" newline hexmask.long.byte 0x5C 0.--7. 1. "LUT2_24,LUT2[24]" line.long 0x60 "VTNF_LUT2_28,Lookup table 1" hexmask.long.byte 0x60 24.--31. 1. "LUT2_31,LUT2[31]" hexmask.long.byte 0x60 16.--23. 1. "LUT2_30,LUT2[30]" hexmask.long.byte 0x60 8.--15. 1. "LUT2_29,LUT2[29]" newline hexmask.long.byte 0x60 0.--7. 1. "LUT2_28,LUT2[28]" width 0x0B tree.end tree.end tree "IVA_CALCulation_Engine_3" sif (cpuis("TDA2PXIVA*")) tree "CALC3_BFSW_ICONT" base ad:0xD8200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_CALCROBUF,View mode selection for CALCROBUF" "0,1" bitfld.long 0x00 0. "VIEW_CALCRPBUF,View mode selection for CALCRPBUF" "0,1" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_CALCROBUF_B,Master selection for CALCROBUF B" "0,1" bitfld.long 0x04 2. "MST_CALCROBUF_A,Master selection for CALCROBUF A" "0,1" bitfld.long 0x04 1. "MST_CALCRPBUF_B,Master selection for CALCRPBUF B" "0,1" bitfld.long 0x04 0. "MST_CALCRPBUF_A,Master selection for CALCRPBUF A" "0,1" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_CALCWBUF,Master selection for CALCWBUF" "0,1" bitfld.long 0x08 0. "MST_CALCQBUF,Master selection for CALCQBUF" "0,1" width 0x0B tree.end endif tree "CALC3_BFSW_L3_MAINInterconnect" base ad:0x5A058200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_CALCROBUF,View mode selection for CALCROBUF" "0,1" bitfld.long 0x00 0. "VIEW_CALCRPBUF,View mode selection for CALCRPBUF" "0,1" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_CALCROBUF_B,Master selection for CALCROBUF B" "0,1" bitfld.long 0x04 2. "MST_CALCROBUF_A,Master selection for CALCROBUF A" "0,1" bitfld.long 0x04 1. "MST_CALCRPBUF_B,Master selection for CALCRPBUF B" "0,1" bitfld.long 0x04 0. "MST_CALCRPBUF_A,Master selection for CALCRPBUF A" "0,1" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_CALCWBUF,Master selection for CALCWBUF" "0,1" bitfld.long 0x08 0. "MST_CALCQBUF,Master selection for CALCQBUF" "0,1" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "CALC3_IPGW_ICONT" base ad:0xD8400 group.long 0x08++0x07 line.long 0x00 "CALC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "CALC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "CALC3_IPQSTATUS_RAW_0,Per-event raw interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Settable raw status for int_end load (LSE)" "No event pending,Set event (debug)" line.long 0x04 "CALC3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. int_end (CALC3 core)" bitfld.long 0x04 0. "EVENT0,Settable raw status for int_end (CALC3 core)" "No event pending,Set event (debug)" line.long 0x08 "CALC3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Settable raw status for int_end store (LSE)" "No event pending,Set event (debug)" line.long 0x0C "CALC3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Settable raw status for int_undef (LSE)" "No event pending,Set event (debug)" group.long 0x30++0x0F line.long 0x00 "CALC3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for int_end load (LSE)" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "CALC3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. int_end (CALC3 Core)" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for int_end (CALC3 core)" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "CALC3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for int_end store (LSE)" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "CALC3_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for int_undef (LSE)" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "CALC3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "CALC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "CALC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "Interrupt disabled (masked),Enable interrupt" line.long 0x0C "CALC3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "CALC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "CALC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "CALC3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "CALC3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "CALC3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 3. "ACLREN3,For int_undef (LSE)" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For int_end store (LSE)" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For int_end (CALC3 core)" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For int_end load (LSE)" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end endif tree "CALC3_IPGW_L3_MAINInterconnect" base ad:0x5A058400 group.long 0x08++0x07 line.long 0x00 "CALC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "CALC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "CALC3_IPQSTATUS_RAW_0,Per-event raw interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Settable raw status for int_end load (LSE)" "No event pending,Set event (debug)" line.long 0x04 "CALC3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. int_end (CALC3 core)" bitfld.long 0x04 0. "EVENT0,Settable raw status for int_end (CALC3 core)" "No event pending,Set event (debug)" line.long 0x08 "CALC3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Settable raw status for int_end store (LSE)" "No event pending,Set event (debug)" line.long 0x0C "CALC3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Settable raw status for int_undef (LSE)" "No event pending,Set event (debug)" group.long 0x30++0x0F line.long 0x00 "CALC3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for int_end load (LSE)" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "CALC3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. int_end (CALC3 Core)" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for int_end (CALC3 core)" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "CALC3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for int_end store (LSE)" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "CALC3_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for int_undef (LSE)" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "CALC3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "CALC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "CALC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "Interrupt disabled (masked),Enable interrupt" line.long 0x0C "CALC3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "CALC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "CALC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "CALC3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "CALC3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "CALC3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 3. "ACLREN3,For int_undef (LSE)" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For int_end store (LSE)" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For int_end (CALC3 core)" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For int_end load (LSE)" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "CALC3_MMR_ICONT" base ad:0xD8000 rgroup.long 0x00++0x1B line.long 0x00 "CALC_PID,CALC3 PID register" line.long 0x04 "CALC_COUNT,CALC3 cycle counter register" bitfld.long 0x04 31. "CALC_CE,Cycle counter enable [1]: Active [0]: Not active" "CALC_CE_0,CALC_CE_1" bitfld.long 0x04 30. "CALC_CRST,Counter reset [1]: Reset counter [0]: No effect" "CALC_CRST_0,CALC_CRST_1" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Cycle counter 16-bit counter Cycle counter is increasing during CALC_EN = 1 in CALC_CTRL" line.long 0x08 "CALC_CTRL,CALC3 control register" bitfld.long 0x08 0. "CALC_EN,CALC3 module status and start bit Write [0]: Ignored Write [1]: Start CALC3 module" "CALC_EN_0,CALC_EN_1" line.long 0x0C "CALC_TEST,CALC3 test register It is only for debug purpose" rbitfld.long 0x0C 24. "CALC_CMD_OPECNT,MB counter register for MBAFF mode For H.264 MBAFF this status bit is used for CALC3 core and command wrapper" "CALC_CMD_OPECNT_0,CALC_CMD_OPECNT_1" bitfld.long 0x0C 13. "CALC_CMD_MNG_DIS,CALC3 command wrapper function of data management (that is neighboring pixel copying) disable flag" "CALC_CMD_MNG_DIS_0,CALC_CMD_MNG_DIS_1" newline bitfld.long 0x0C 12. "CALC_CMD_GEN_DIS,CALC3 command wrapper function of CALC3 core specific command generation disable flag" "CALC_CMD_GEN_DIS_0,CALC_CMD_GEN_DIS_1" bitfld.long 0x0C 6. "CALC_2ND_MB_DIS,CALC3 2nd Mb disable flag ( it is effective only for MBAFF ) [1]: 2nd Mb operation for MBAFF is disable for CALC3 core and command wrapper [0]: 2nd Mb operation for MBAFF is enable for CALC3 core and command wrapper" "CALC_2ND_MB_DIS_0,CALC_2ND_MB_DIS_1" newline bitfld.long 0x0C 5. "CALC_TIT_DIS,CALC3 transform function disable flag [1]: Transform function is skipped in CALC3 core" "CALC_TIT_DIS_0,CALC_TIT_DIS_1" bitfld.long 0x0C 4. "CALC_QIQ_DIS,CALC3 QIQ function disable flag [1]: QIQ function is skipped in CALC3 core" "CALC_QIQ_DIS_0,CALC_QIQ_DIS_1" newline bitfld.long 0x0C 0. "CALC_CORE_DIS,CALC3 core disable flag" "CALC_CORE_DIS_0,CALC_CORE_DIS_1" line.long 0x10 "CALC_MODE,CALC3 mode select register" bitfld.long 0x10 31. "CALC_H263_ANNEXI,In H.264[0] : Intra_8x8 Pre-Filter is active" "CALC_H263_ANNEXI_0,CALC_H263_ANNEXI_1" bitfld.long 0x10 30. "CALC_MPEG4_QUANT_TYPE,MPEG-4 QuantType set flag - It is effective for MPEG-4 only" "CALC_MPEG4_QUANT_TYPE_0,CALC_MPEG4_QUANT_TYPE_1" newline bitfld.long 0x10 29. "CALC_VC1_NONUNIQUANT,VC-1 NonUniformQuantize set flag - It is effective for VC-1 only" "CALC_VC1_NONUNIQUANT_0,CALC_VC1_NONUNIQUANT_1" bitfld.long 0x10 28. "CALC_VC1_DC_DEF_NONZERO,VC-1 DcDefaultNonZero set flag - It is effective for VC-1 only" "CALC_VC1_DC_DEF_NONZERO_0,CALC_VC1_DC_DEF_NONZERO_1" newline bitfld.long 0x10 24.--27. "CALC_CODEC_TYPE,Codec type set register[0]: JPEG" "CALC_CODEC_TYPE_0,CALC_CODEC_TYPE_1,CALC_CODEC_TYPE_2,CALC_CODEC_TYPE_3,CALC_CODEC_TYPE_4,CALC_CODEC_TYPE_5,CALC_CODEC_TYPE_6,CALC_CODEC_TYPE_7,CALC_CODEC_TYPE_8,CALC_CODEC_TYPE_9,CALC_CODEC_TYPE_10,CALC_CODEC_TYPE_11,CALC_CODEC_TYPE_12,CALC_CODEC_TYPE_13,CALC_CODEC_TYPE_14,CALC_CODEC_TYPE_15" bitfld.long 0x10 23. "CALC_CBPCNT0_INTER_EN,CBPControl #0 enable flag for Inter Block[0]: Disable" "CALC_CBPCNT0_INTER_EN_0,CALC_CBPCNT0_INTER_EN_1" newline bitfld.long 0x10 22. "CALC_CBPCNT0_LUMA_DCTRANS_EN,CBPControl #0 enable flag for Luma DC Trans mode[0]: Disable" "CALC_CBPCNT0_LUMA_DCTRANS_EN_0,CALC_CBPCNT0_LUMA_DCTRANS_EN_1" bitfld.long 0x10 21. "CALC_CBPCNT0_CHRO_DCTRANS_EN,CBPControl #0 enable flag for Chroma DC Trans mode[0]: Disable" "CALC_CBPCNT0_CHRO_DCTRANS_EN_0,CALC_CBPCNT0_CHRO_DCTRANS_EN_1" newline bitfld.long 0x10 20. "CALC_CBPCNT0_INTER_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_INTER_EN - It is effective for CALC_CBPCNT0_INTER_EN = 1" "CALC_CBPCNT0_INTER_THR_0,CALC_CBPCNT0_INTER_THR_1" bitfld.long 0x10 19. "CALC_CBPCNT0_LUMA_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_LUMA_DCTRANS_EN - It is effective for CALC_CBPCNT0_LUMA_DCTRANS_EN = 1" "CALC_CBPCNT0_LUMA_DCTRANS_THR_0,CALC_CBPCNT0_LUMA_DCTRANS_THR_1" newline bitfld.long 0x10 18. "CALC_CBPCNT0_CHRO_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_CHRO_DCTRANS_EN - It is effective for CALC_CBPCNT0_CHRO_DCTRANS_EN = 1" "CALC_CBPCNT0_CHRO_DCTRANS_THR_0,CALC_CBPCNT0_CHRO_DCTRANS_THR_1" bitfld.long 0x10 17. "CALC_CBPCNT1_EN,CBP Control #1 enable flag[0]: OFF" "CALC_CBPCNT1_EN_0,CALC_CBPCNT1_EN_1" newline bitfld.long 0x10 16. "CALC_ENC,Enc or Dec mode flag[0]: Dec" "CALC_ENC_0,CALC_ENC_1" bitfld.long 0x10 15. "CALC_MPEG2_QSCLTYPE,q_scale_type of MPEG-2 set register for command wrapper" "CALC_MPEG2_QSCLTYPE_0,CALC_MPEG2_QSCLTYPE_1" newline bitfld.long 0x10 13.--14. "CALC_MPEG2_INTRADCPREC,intra_dc_precision of MPEG-2 set register for command wrapper" "CALC_MPEG2_INTRADCPREC_0,CALC_MPEG2_INTRADCPREC_1,CALC_MPEG2_INTRADCPREC_2,CALC_MPEG2_INTRADCPREC_3" bitfld.long 0x10 12. "CALC_ACPRED_DIS,AC prediction disable flag for command wrapper" "CALC_ACPRED_DIS_0,CALC_ACPRED_DIS_1" newline bitfld.long 0x10 11. "CALC_H264_CONST_INTRA,Constraint intra set of H.264 flag for command wrapper" "CALC_H264_CONST_INTRA_0,CALC_H264_CONST_INTRA_1" bitfld.long 0x10 9.--10. "CALC_PICTCODINGTYPE,Picture coding type set register for command wrapper[0]: I Picture" "CALC_PICTCODINGTYPE_0,CALC_PICTCODINGTYPE_1,CALC_PICTCODINGTYPE_2,CALC_PICTCODINGTYPE_3" newline bitfld.long 0x10 8. "CALC_RECON_16BIT_EN,Reconstruct format flag[0]: 8-bit mode" "CALC_RECON_16BIT_EN_0,CALC_RECON_16BIT_EN_1" bitfld.long 0x10 6.--7. "CALC_VC1_PROFILE,VC-1 Profile register for command wrapper[0]: Simple" "CALC_VC1_PROFILE_0,CALC_VC1_PROFILE_1,CALC_VC1_PROFILE_2,CALC_VC1_PROFILE_3" newline bitfld.long 0x10 5. "CALC_SORENSON_EN,Sorenson Spark setting register" "CALC_SORENSON_EN_0,CALC_SORENSON_EN_1" bitfld.long 0x10 2.--4. "CALC_JPG_FORMAT,JPEG color mode setting register" "CALC_JPG_FORMAT_0,CALC_JPG_FORMAT_1,CALC_JPG_FORMAT_2,CALC_JPG_FORMAT_3,CALC_JPG_FORMAT_4,CALC_JPG_FORMAT_5,CALC_JPG_FORMAT_6,CALC_JPG_FORMAT_7" newline bitfld.long 0x10 0.--1. "CALC_PICT_STRUCT,Picture Structure setting register[0]: Frame structure" "CALC_PICT_STRUCT_0,CALC_PICT_STRUCT_1,CALC_PICT_STRUCT_2,CALC_PICT_STRUCT_3" line.long 0x14 "CALC_FWDQ_RND_INTRA,CALC3 forward quantization's rounding coefficients and shift offsets for intra MB" hexmask.long 0x14 7.--31. 1. "CALC_Q_RND_COEF_INTRA,Forward quantization's rounding coefficients for intra MB" bitfld.long 0x14 0.--3. "CALC_Q_SHIFT_ADJ_INTRA,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTRA_0,CALC_Q_SHIFT_ADJ_INTRA_1,CALC_Q_SHIFT_ADJ_INTRA_2,CALC_Q_SHIFT_ADJ_INTRA_3,CALC_Q_SHIFT_ADJ_INTRA_4,CALC_Q_SHIFT_ADJ_INTRA_5,CALC_Q_SHIFT_ADJ_INTRA_6,CALC_Q_SHIFT_ADJ_INTRA_7,CALC_Q_SHIFT_ADJ_INTRA_8,CALC_Q_SHIFT_ADJ_INTRA_9,CALC_Q_SHIFT_ADJ_INTRA_10,CALC_Q_SHIFT_ADJ_INTRA_11,CALC_Q_SHIFT_ADJ_INTRA_12,CALC_Q_SHIFT_ADJ_INTRA_13,CALC_Q_SHIFT_ADJ_INTRA_14,CALC_Q_SHIFT_ADJ_INTRA_15" line.long 0x18 "CALC_FWDQ_RND_INTER,CALC3 forward quantization's rounding coefficients and shift offsets for inter MB" hexmask.long 0x18 7.--31. 1. "CALC_Q_RND_COEF_INTER,Forward quantization's rounding coefficients for inter MB" bitfld.long 0x18 0.--3. "CALC_Q_SHIFT_ADJ_INTER,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTER_0,CALC_Q_SHIFT_ADJ_INTER_1,CALC_Q_SHIFT_ADJ_INTER_2,CALC_Q_SHIFT_ADJ_INTER_3,CALC_Q_SHIFT_ADJ_INTER_4,CALC_Q_SHIFT_ADJ_INTER_5,CALC_Q_SHIFT_ADJ_INTER_6,CALC_Q_SHIFT_ADJ_INTER_7,CALC_Q_SHIFT_ADJ_INTER_8,CALC_Q_SHIFT_ADJ_INTER_9,CALC_Q_SHIFT_ADJ_INTER_10,CALC_Q_SHIFT_ADJ_INTER_11,CALC_Q_SHIFT_ADJ_INTER_12,CALC_Q_SHIFT_ADJ_INTER_13,CALC_Q_SHIFT_ADJ_INTER_14,CALC_Q_SHIFT_ADJ_INTER_15" group.long 0x20++0x07 line.long 0x00 "CALC_FWDQ_RND_INTRA_DC,Round offset value setting for fwd Q. intra and DC coefficient" hexmask.long 0x00 7.--31. 1. "CALC_Q_RND_COEF_INTRA_DC,Forward quantization's rounding coefficients for intra MB and its DC coefficients" line.long 0x04 "CALC_FWDQ_RND_INTER_DC,Round offset value setting for fwd Q. inter and DC coefficient" hexmask.long 0x04 7.--31. 1. "CALC_Q_RND_COEF_INTER_DC,Forward quantization's rounding coefficients for inter MB and its DC coefficients" width 0x0B tree.end endif tree "CALC3_MMR_L3_MAINInterconnect" base ad:0x5A058000 rgroup.long 0x00++0x1B line.long 0x00 "CALC_PID,CALC3 PID register" line.long 0x04 "CALC_COUNT,CALC3 cycle counter register" bitfld.long 0x04 31. "CALC_CE,Cycle counter enable [1]: Active [0]: Not active" "CALC_CE_0,CALC_CE_1" bitfld.long 0x04 30. "CALC_CRST,Counter reset [1]: Reset counter [0]: No effect" "CALC_CRST_0,CALC_CRST_1" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Cycle counter 16-bit counter Cycle counter is increasing during CALC_EN = 1 in CALC_CTRL" line.long 0x08 "CALC_CTRL,CALC3 control register" bitfld.long 0x08 0. "CALC_EN,CALC3 module status and start bit Write [0]: Ignored Write [1]: Start CALC3 module" "CALC_EN_0,CALC_EN_1" line.long 0x0C "CALC_TEST,CALC3 test register It is only for debug purpose" rbitfld.long 0x0C 24. "CALC_CMD_OPECNT,MB counter register for MBAFF mode For H.264 MBAFF this status bit is used for CALC3 core and command wrapper" "CALC_CMD_OPECNT_0,CALC_CMD_OPECNT_1" bitfld.long 0x0C 13. "CALC_CMD_MNG_DIS,CALC3 command wrapper function of data management (that is neighboring pixel copying) disable flag" "CALC_CMD_MNG_DIS_0,CALC_CMD_MNG_DIS_1" newline bitfld.long 0x0C 12. "CALC_CMD_GEN_DIS,CALC3 command wrapper function of CALC3 core specific command generation disable flag" "CALC_CMD_GEN_DIS_0,CALC_CMD_GEN_DIS_1" bitfld.long 0x0C 6. "CALC_2ND_MB_DIS,CALC3 2nd Mb disable flag ( it is effective only for MBAFF ) [1]: 2nd Mb operation for MBAFF is disable for CALC3 core and command wrapper [0]: 2nd Mb operation for MBAFF is enable for CALC3 core and command wrapper" "CALC_2ND_MB_DIS_0,CALC_2ND_MB_DIS_1" newline bitfld.long 0x0C 5. "CALC_TIT_DIS,CALC3 transform function disable flag [1]: Transform function is skipped in CALC3 core" "CALC_TIT_DIS_0,CALC_TIT_DIS_1" bitfld.long 0x0C 4. "CALC_QIQ_DIS,CALC3 QIQ function disable flag [1]: QIQ function is skipped in CALC3 core" "CALC_QIQ_DIS_0,CALC_QIQ_DIS_1" newline bitfld.long 0x0C 0. "CALC_CORE_DIS,CALC3 core disable flag" "CALC_CORE_DIS_0,CALC_CORE_DIS_1" line.long 0x10 "CALC_MODE,CALC3 mode select register" bitfld.long 0x10 31. "CALC_H263_ANNEXI,In H.264[0] : Intra_8x8 Pre-Filter is active" "CALC_H263_ANNEXI_0,CALC_H263_ANNEXI_1" bitfld.long 0x10 30. "CALC_MPEG4_QUANT_TYPE,MPEG-4 QuantType set flag - It is effective for MPEG-4 only" "CALC_MPEG4_QUANT_TYPE_0,CALC_MPEG4_QUANT_TYPE_1" newline bitfld.long 0x10 29. "CALC_VC1_NONUNIQUANT,VC-1 NonUniformQuantize set flag - It is effective for VC-1 only" "CALC_VC1_NONUNIQUANT_0,CALC_VC1_NONUNIQUANT_1" bitfld.long 0x10 28. "CALC_VC1_DC_DEF_NONZERO,VC-1 DcDefaultNonZero set flag - It is effective for VC-1 only" "CALC_VC1_DC_DEF_NONZERO_0,CALC_VC1_DC_DEF_NONZERO_1" newline bitfld.long 0x10 24.--27. "CALC_CODEC_TYPE,Codec type set register[0]: JPEG" "CALC_CODEC_TYPE_0,CALC_CODEC_TYPE_1,CALC_CODEC_TYPE_2,CALC_CODEC_TYPE_3,CALC_CODEC_TYPE_4,CALC_CODEC_TYPE_5,CALC_CODEC_TYPE_6,CALC_CODEC_TYPE_7,CALC_CODEC_TYPE_8,CALC_CODEC_TYPE_9,CALC_CODEC_TYPE_10,CALC_CODEC_TYPE_11,CALC_CODEC_TYPE_12,CALC_CODEC_TYPE_13,CALC_CODEC_TYPE_14,CALC_CODEC_TYPE_15" bitfld.long 0x10 23. "CALC_CBPCNT0_INTER_EN,CBPControl #0 enable flag for Inter Block[0]: Disable" "CALC_CBPCNT0_INTER_EN_0,CALC_CBPCNT0_INTER_EN_1" newline bitfld.long 0x10 22. "CALC_CBPCNT0_LUMA_DCTRANS_EN,CBPControl #0 enable flag for Luma DC Trans mode[0]: Disable" "CALC_CBPCNT0_LUMA_DCTRANS_EN_0,CALC_CBPCNT0_LUMA_DCTRANS_EN_1" bitfld.long 0x10 21. "CALC_CBPCNT0_CHRO_DCTRANS_EN,CBPControl #0 enable flag for Chroma DC Trans mode[0]: Disable" "CALC_CBPCNT0_CHRO_DCTRANS_EN_0,CALC_CBPCNT0_CHRO_DCTRANS_EN_1" newline bitfld.long 0x10 20. "CALC_CBPCNT0_INTER_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_INTER_EN - It is effective for CALC_CBPCNT0_INTER_EN = 1" "CALC_CBPCNT0_INTER_THR_0,CALC_CBPCNT0_INTER_THR_1" bitfld.long 0x10 19. "CALC_CBPCNT0_LUMA_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_LUMA_DCTRANS_EN - It is effective for CALC_CBPCNT0_LUMA_DCTRANS_EN = 1" "CALC_CBPCNT0_LUMA_DCTRANS_THR_0,CALC_CBPCNT0_LUMA_DCTRANS_THR_1" newline bitfld.long 0x10 18. "CALC_CBPCNT0_CHRO_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_CHRO_DCTRANS_EN - It is effective for CALC_CBPCNT0_CHRO_DCTRANS_EN = 1" "CALC_CBPCNT0_CHRO_DCTRANS_THR_0,CALC_CBPCNT0_CHRO_DCTRANS_THR_1" bitfld.long 0x10 17. "CALC_CBPCNT1_EN,CBP Control #1 enable flag[0]: OFF" "CALC_CBPCNT1_EN_0,CALC_CBPCNT1_EN_1" newline bitfld.long 0x10 16. "CALC_ENC,Enc or Dec mode flag[0]: Dec" "CALC_ENC_0,CALC_ENC_1" bitfld.long 0x10 15. "CALC_MPEG2_QSCLTYPE,q_scale_type of MPEG-2 set register for command wrapper" "CALC_MPEG2_QSCLTYPE_0,CALC_MPEG2_QSCLTYPE_1" newline bitfld.long 0x10 13.--14. "CALC_MPEG2_INTRADCPREC,intra_dc_precision of MPEG-2 set register for command wrapper" "CALC_MPEG2_INTRADCPREC_0,CALC_MPEG2_INTRADCPREC_1,CALC_MPEG2_INTRADCPREC_2,CALC_MPEG2_INTRADCPREC_3" bitfld.long 0x10 12. "CALC_ACPRED_DIS,AC prediction disable flag for command wrapper" "CALC_ACPRED_DIS_0,CALC_ACPRED_DIS_1" newline bitfld.long 0x10 11. "CALC_H264_CONST_INTRA,Constraint intra set of H.264 flag for command wrapper" "CALC_H264_CONST_INTRA_0,CALC_H264_CONST_INTRA_1" bitfld.long 0x10 9.--10. "CALC_PICTCODINGTYPE,Picture coding type set register for command wrapper[0]: I Picture" "CALC_PICTCODINGTYPE_0,CALC_PICTCODINGTYPE_1,CALC_PICTCODINGTYPE_2,CALC_PICTCODINGTYPE_3" newline bitfld.long 0x10 8. "CALC_RECON_16BIT_EN,Reconstruct format flag[0]: 8-bit mode" "CALC_RECON_16BIT_EN_0,CALC_RECON_16BIT_EN_1" bitfld.long 0x10 6.--7. "CALC_VC1_PROFILE,VC-1 Profile register for command wrapper[0]: Simple" "CALC_VC1_PROFILE_0,CALC_VC1_PROFILE_1,CALC_VC1_PROFILE_2,CALC_VC1_PROFILE_3" newline bitfld.long 0x10 5. "CALC_SORENSON_EN,Sorenson Spark setting register" "CALC_SORENSON_EN_0,CALC_SORENSON_EN_1" bitfld.long 0x10 2.--4. "CALC_JPG_FORMAT,JPEG color mode setting register" "CALC_JPG_FORMAT_0,CALC_JPG_FORMAT_1,CALC_JPG_FORMAT_2,CALC_JPG_FORMAT_3,CALC_JPG_FORMAT_4,CALC_JPG_FORMAT_5,CALC_JPG_FORMAT_6,CALC_JPG_FORMAT_7" newline bitfld.long 0x10 0.--1. "CALC_PICT_STRUCT,Picture Structure setting register[0]: Frame structure" "CALC_PICT_STRUCT_0,CALC_PICT_STRUCT_1,CALC_PICT_STRUCT_2,CALC_PICT_STRUCT_3" line.long 0x14 "CALC_FWDQ_RND_INTRA,CALC3 forward quantization's rounding coefficients and shift offsets for intra MB" hexmask.long 0x14 7.--31. 1. "CALC_Q_RND_COEF_INTRA,Forward quantization's rounding coefficients for intra MB" bitfld.long 0x14 0.--3. "CALC_Q_SHIFT_ADJ_INTRA,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTRA_0,CALC_Q_SHIFT_ADJ_INTRA_1,CALC_Q_SHIFT_ADJ_INTRA_2,CALC_Q_SHIFT_ADJ_INTRA_3,CALC_Q_SHIFT_ADJ_INTRA_4,CALC_Q_SHIFT_ADJ_INTRA_5,CALC_Q_SHIFT_ADJ_INTRA_6,CALC_Q_SHIFT_ADJ_INTRA_7,CALC_Q_SHIFT_ADJ_INTRA_8,CALC_Q_SHIFT_ADJ_INTRA_9,CALC_Q_SHIFT_ADJ_INTRA_10,CALC_Q_SHIFT_ADJ_INTRA_11,CALC_Q_SHIFT_ADJ_INTRA_12,CALC_Q_SHIFT_ADJ_INTRA_13,CALC_Q_SHIFT_ADJ_INTRA_14,CALC_Q_SHIFT_ADJ_INTRA_15" line.long 0x18 "CALC_FWDQ_RND_INTER,CALC3 forward quantization's rounding coefficients and shift offsets for inter MB" hexmask.long 0x18 7.--31. 1. "CALC_Q_RND_COEF_INTER,Forward quantization's rounding coefficients for inter MB" bitfld.long 0x18 0.--3. "CALC_Q_SHIFT_ADJ_INTER,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTER_0,CALC_Q_SHIFT_ADJ_INTER_1,CALC_Q_SHIFT_ADJ_INTER_2,CALC_Q_SHIFT_ADJ_INTER_3,CALC_Q_SHIFT_ADJ_INTER_4,CALC_Q_SHIFT_ADJ_INTER_5,CALC_Q_SHIFT_ADJ_INTER_6,CALC_Q_SHIFT_ADJ_INTER_7,CALC_Q_SHIFT_ADJ_INTER_8,CALC_Q_SHIFT_ADJ_INTER_9,CALC_Q_SHIFT_ADJ_INTER_10,CALC_Q_SHIFT_ADJ_INTER_11,CALC_Q_SHIFT_ADJ_INTER_12,CALC_Q_SHIFT_ADJ_INTER_13,CALC_Q_SHIFT_ADJ_INTER_14,CALC_Q_SHIFT_ADJ_INTER_15" group.long 0x20++0x07 line.long 0x00 "CALC_FWDQ_RND_INTRA_DC,Round offset value setting for fwd Q. intra and DC coefficient" hexmask.long 0x00 7.--31. 1. "CALC_Q_RND_COEF_INTRA_DC,Forward quantization's rounding coefficients for intra MB and its DC coefficients" line.long 0x04 "CALC_FWDQ_RND_INTER_DC,Round offset value setting for fwd Q. inter and DC coefficient" hexmask.long 0x04 7.--31. 1. "CALC_Q_RND_COEF_INTER_DC,Forward quantization's rounding coefficients for inter MB and its DC coefficients" width 0x0B tree.end tree.end tree "IVA_Entropy_Coder_Decoder" sif (cpuis("TDA2PXIVA*")) tree "ECD3_BFSW_ICONT" base ad:0xD9A00 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View Mode Register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_ERSDBUF,View mode selection for ersdbuf" "Full view mode is selected,Ping-pong view mode is selected" bitfld.long 0x00 0. "VIEW_ECDABUF,View mode selection for ecdabuf" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_ERSDBUF_B,Master selection for ersdbuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 2. "MST_ERSDBUF_A,Master selection for ersdbuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" newline bitfld.long 0x04 1. "MST_ECDABUF_B,Master selection for ecdabuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 0. "MST_ECDABUF_A,Master selection for ecdabuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 1.--31. 1. "RSRV,Reserved" bitfld.long 0x08 0. "MST_ECDWBUF,Master selection for ecdwbuf" "The buffer is assigned to DMA,The buffer is assigned to HWA" width 0x0B tree.end endif tree "ECD3_BFSW_L3_MAINInterconnect" base ad:0x5A059A00 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View Mode Register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_ERSDBUF,View mode selection for ersdbuf" "Full view mode is selected,Ping-pong view mode is selected" bitfld.long 0x00 0. "VIEW_ECDABUF,View mode selection for ecdabuf" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_ERSDBUF_B,Master selection for ersdbuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 2. "MST_ERSDBUF_A,Master selection for ersdbuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" newline bitfld.long 0x04 1. "MST_ECDABUF_B,Master selection for ecdabuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 0. "MST_ECDABUF_A,Master selection for ecdabuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 1.--31. 1. "RSRV,Reserved" bitfld.long 0x08 0. "MST_ECDWBUF,Master selection for ecdwbuf" "The buffer is assigned to DMA,The buffer is assigned to HWA" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "ECD3_IPGW_ICONT" base ad:0xD9C00 group.long 0x08++0x07 line.long 0x00 "ECD3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "IP module is sensitive to emulation suspend,IP module is not sensitive to emulation suspend" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Initiate software reset" line.long 0x04 "ECD3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "Reads always 0 (no EOI memory),EOI for interrupt output line #1,EOI for interrupt output line #2,EOI for interrupt output line #3,EOI for interrupt output line #4,EOI for interrupt output line #5,EOI for interrupt output line #6,?..." group.long 0x14++0x6F line.long 0x00 "ECD3_IPQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x04 "ECD3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. line #1" bitfld.long 0x04 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x08 "ECD3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. line #2" bitfld.long 0x08 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x0C "ECD3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. line #3" bitfld.long 0x0C 1. "EVENT1,settable raw status for event #1" "No event pending,Set event (debug)" bitfld.long 0x0C 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x10 "ECD3_IPQSTATUS_RAW_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x10 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x14 "ECD3_IPQSTATUS_RAW_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x14 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x18 "ECD3_IPQSTATUS_RAW_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x18 1. "EVENT1,settable raw status for event #1" "No event pending,Set event (debug)" bitfld.long 0x18 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x1C "ECD3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x1C 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x20 "ECD3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1" bitfld.long 0x20 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x24 "ECD3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. line #2" bitfld.long 0x24 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x28 "ECD3_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x28 1. "EVENT1,clearable enabled status for event #1" "No (enabled) event pending,Clear (raw) event" bitfld.long 0x28 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x2C "ECD3_IRQSTATUS_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x2C 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x30 "ECD3_IRQSTATUS_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x30 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x34 "ECD3_IRQSTATUS_6,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x34 1. "EVENT1,clearable enabled status for event #1" "No (enabled) event pending,Clear (raw) event" bitfld.long 0x34 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x38 "ECD3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0" bitfld.long 0x38 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x3C "ECD3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x3C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x40 "ECD3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x40 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x44 "ECD3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line #0" bitfld.long 0x44 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x44 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x48 "ECD3_IRQENABLE_SET_4,Per-event interrupt enable bit vector. line #0" bitfld.long 0x48 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x4C "ECD3_IRQENABLE_SET_5,Per-event interrupt enable bit vector. line #0" bitfld.long 0x4C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x50 "ECD3_IRQENABLE_SET_6,Per-event interrupt enable bit vector. line #0" bitfld.long 0x50 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x50 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x54 "ECD3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0" bitfld.long 0x54 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x58 "ECD3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x58 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x5C "ECD3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x5C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x60 "ECD3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line #2" bitfld.long 0x60 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x60 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x64 "ECD3_IRQENABLE_CLR_4,Per-event interrupt enable bit vector. line #0" bitfld.long 0x64 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x68 "ECD3_IRQENABLE_CLR_5,Per-event interrupt enable bit vector. line #0" bitfld.long 0x68 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x6C "ECD3_IRQENABLE_CLR_6,Per-event interrupt enable bit vector. line #2" bitfld.long 0x6C 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x6C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" group.long 0xC0++0x03 line.long 0x00 "ECD3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 6. "ACLREN6,For line 6" "ACLREN6_0,ACLREN6_1" bitfld.long 0x00 5. "ACLREN5,For line 5" "ACLREN5_0,ACLREN5_1" newline bitfld.long 0x00 4. "ACLREN4,For line 4" "ACLREN4_0,ACLREN4_1" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" newline bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" newline bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end endif tree "ECD3_IPGW_L3_MAINInterconnect" base ad:0x5A059C00 group.long 0x08++0x07 line.long 0x00 "ECD3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wake-up-capable mode" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "IP module is sensitive to emulation suspend,IP module is not sensitive to emulation suspend" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Initiate software reset" line.long 0x04 "ECD3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "Reads always 0 (no EOI memory),EOI for interrupt output line #1,EOI for interrupt output line #2,EOI for interrupt output line #3,EOI for interrupt output line #4,EOI for interrupt output line #5,EOI for interrupt output line #6,?..." group.long 0x14++0x6F line.long 0x00 "ECD3_IPQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x04 "ECD3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. line #1" bitfld.long 0x04 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x08 "ECD3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. line #2" bitfld.long 0x08 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x0C "ECD3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. line #3" bitfld.long 0x0C 1. "EVENT1,settable raw status for event #1" "No event pending,Set event (debug)" bitfld.long 0x0C 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x10 "ECD3_IPQSTATUS_RAW_4,Per-event raw interrupt status vector. line #0" bitfld.long 0x10 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x14 "ECD3_IPQSTATUS_RAW_5,Per-event raw interrupt status vector. line #0" bitfld.long 0x14 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x18 "ECD3_IPQSTATUS_RAW_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x18 1. "EVENT1,settable raw status for event #1" "No event pending,Set event (debug)" bitfld.long 0x18 0. "EVENT0,settable raw status for event #0" "No event pending,Set event (debug)" line.long 0x1C "ECD3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x1C 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x20 "ECD3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1" bitfld.long 0x20 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x24 "ECD3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. line #2" bitfld.long 0x24 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x28 "ECD3_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x28 1. "EVENT1,clearable enabled status for event #1" "No (enabled) event pending,Clear (raw) event" bitfld.long 0x28 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x2C "ECD3_IRQSTATUS_4,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x2C 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x30 "ECD3_IRQSTATUS_5,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x30 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x34 "ECD3_IRQSTATUS_6,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x34 1. "EVENT1,clearable enabled status for event #1" "No (enabled) event pending,Clear (raw) event" bitfld.long 0x34 0. "EVENT0,clearable enabled status for event #0" "No (enabled) event pending,Clear (raw) event" line.long 0x38 "ECD3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0" bitfld.long 0x38 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x3C "ECD3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x3C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x40 "ECD3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x40 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x44 "ECD3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line #0" bitfld.long 0x44 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x44 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x48 "ECD3_IRQENABLE_SET_4,Per-event interrupt enable bit vector. line #0" bitfld.long 0x48 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x4C "ECD3_IRQENABLE_SET_5,Per-event interrupt enable bit vector. line #0" bitfld.long 0x4C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x50 "ECD3_IRQENABLE_SET_6,Per-event interrupt enable bit vector. line #0" bitfld.long 0x50 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x50 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x54 "ECD3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0" bitfld.long 0x54 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x58 "ECD3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x58 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x5C "ECD3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x5C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x60 "ECD3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line #2" bitfld.long 0x60 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x60 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x64 "ECD3_IRQENABLE_CLR_4,Per-event interrupt enable bit vector. line #0" bitfld.long 0x64 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x68 "ECD3_IRQENABLE_CLR_5,Per-event interrupt enable bit vector. line #0" bitfld.long 0x68 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" line.long 0x6C "ECD3_IRQENABLE_CLR_6,Per-event interrupt enable bit vector. line #2" bitfld.long 0x6C 1. "ENABLE1,Enable for event #1" "Interrupt disabled (masked),Interrupt enabled" bitfld.long 0x6C 0. "ENABLE0,Enable for event #0" "Interrupt disabled (masked),Interrupt enabled" group.long 0xC0++0x03 line.long 0x00 "ECD3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 6. "ACLREN6,For line 6" "ACLREN6_0,ACLREN6_1" bitfld.long 0x00 5. "ACLREN5,For line 5" "ACLREN5_0,ACLREN5_1" newline bitfld.long 0x00 4. "ACLREN4,For line 4" "ACLREN4_0,ACLREN4_1" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" newline bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" newline bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end tree "ECD3_LSE_ICONT" base ad:0xD9B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX without the.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9] : OCP CFG IP_CORE side" "When Sresp is not ERR,When Sresp is ERR,?..." newline rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "Normal Mode,Enable Single Step Mdde" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "Enable internal bfsw change (default) Then LSE..,Disable BFSW change (If Host want to control.." newline bitfld.long 0x00 4. "CSB,Command Status Bit" "LSE command is defined,LSE command is undefined Writing 0 is ignored.." bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps need to set before this bit is set" "Idle Writing 0 is ignored This bit is cleared..,Execute 'LD task'" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode" "Idle Writing 0 is ignored This bit is cleared..,Execute 'Comp task'" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps need to set before this bit is set" "Idle Writing 0 is ignored This bit is cleared..,Execute 'Store task'" newline bitfld.long 0x00 0. "SB_BYPS,Sync-Box Byps mode" "LSE function normal SYNCBOX mode and waits..,LSE functions SYNCBOX bypass mode and executes.." line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree "ECD3_LSE_L3_MAINInterconnect" base ad:0x5A059B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX without the.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9] : OCP CFG IP_CORE side" "When Sresp is not ERR,When Sresp is ERR,?..." newline rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "Normal Mode,Enable Single Step Mdde" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "Enable internal bfsw change (default) Then LSE..,Disable BFSW change (If Host want to control.." newline bitfld.long 0x00 4. "CSB,Command Status Bit" "LSE command is defined,LSE command is undefined Writing 0 is ignored.." bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps need to set before this bit is set" "Idle Writing 0 is ignored This bit is cleared..,Execute 'LD task'" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode" "Idle Writing 0 is ignored This bit is cleared..,Execute 'Comp task'" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps need to set before this bit is set" "Idle Writing 0 is ignored This bit is cleared..,Execute 'Store task'" newline bitfld.long 0x00 0. "SB_BYPS,Sync-Box Byps mode" "LSE function normal SYNCBOX mode and waits..,LSE functions SYNCBOX bypass mode and executes.." line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "ECD3_MMR_ICONT" base ad:0xD9800 rgroup.long 0x00++0x33 line.long 0x00 "ECD_PID,Product Identification" line.long 0x04 "ECD_COUNT,Cycle Counter" bitfld.long 0x04 31. "CNT_EN," "Disable the cycle counter,Enable the cycle counter" newline bitfld.long 0x04 30. "CNT_RST,Resets the cycle counter COUNT value to 0" "No effect,Clears COUNT" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Displays the current counter value" line.long 0x08 "ECD_CTRL,Control" rbitfld.long 0x08 20.--23. "CDM_ADD_15_12,Specifies the starting byte address [15:12] of command sequence stored in ECDABUF" "CDM_ADD_15_12_0,CDM_ADD_15_12_1,CDM_ADD_15_12_2,CDM_ADD_15_12_3,CDM_ADD_15_12_4,CDM_ADD_15_12_5,CDM_ADD_15_12_6,CDM_ADD_15_12_7,CDM_ADD_15_12_8,CDM_ADD_15_12_9,CDM_ADD_15_12_10,CDM_ADD_15_12_11,CDM_ADD_15_12_12,CDM_ADD_15_12_13,CDM_ADD_15_12_14,CDM_ADD_15_12_15" newline hexmask.long.byte 0x08 12.--19. 1. "CDM_ADD_11_4,Specifies the starting byte address [11:4] of command sequence stored in ECDABUF" newline rbitfld.long 0x08 8.--11. "CDM_ADD_3_0,Specifies the starting byte address [3:0] of command sequence stored in ECDABUF" "CDM_ADD_3_0_0,CDM_ADD_3_0_1,CDM_ADD_3_0_2,CDM_ADD_3_0_3,CDM_ADD_3_0_4,CDM_ADD_3_0_5,CDM_ADD_3_0_6,CDM_ADD_3_0_7,CDM_ADD_3_0_8,CDM_ADD_3_0_9,CDM_ADD_3_0_10,CDM_ADD_3_0_11,CDM_ADD_3_0_12,CDM_ADD_3_0_13,CDM_ADD_3_0_14,CDM_ADD_3_0_15" newline bitfld.long 0x08 2. "SSM," "SSM_0,SSM_1" newline bitfld.long 0x08 1. "CSB," "Indicates that the last command processing ended..,Indicates that ECD3 found an undefined op-code.." newline bitfld.long 0x08 0. "EN," "EN_0,EN_1" line.long 0x0C "ECD_STAT,ECD Status" bitfld.long 0x0C 30. "EOS_ACK_DIS," "Indicates that ECD3 waits for an acknowledge..,Indicates that the EOS interrupt handshake.." newline bitfld.long 0x0C 29. "ERR_ACK_DIS," "Indicates that ECD3 waits for an acknowledge..,Indicates that the ERR interrupt handshake.." newline bitfld.long 0x0C 2. "EOS," "Force to exit busy state while waiting for an..,Indicates that the last macroblock is at the end.." newline bitfld.long 0x0C 1. "ERR," "Force to exit busy state while waiting for an..,Indicates an error was found in the stream while.." newline rbitfld.long 0x0C 0. "BUSY," "BUSY_0,BUSY_1" line.long 0x10 "SBC_CTRL,Stream Buffer Controller Control" bitfld.long 0x10 31. "SBC_RST,Resets the Stream Buffer Controller" "No effect,Resets all registers of.." newline bitfld.long 0x10 16. "SBC_CLOSE,Close the bitstream data" "No effect,Brings it back to idle.." newline bitfld.long 0x10 12. "SBC_DMA_TRG_B,Start DMA to fill empty page in the Buffer B manually" "SBC_DMA_TRG_B_0,SBC_DMA_TRG_B_1" newline bitfld.long 0x10 8. "SBC_DMA_TRG_A,Start DMA to fill empty page in the Buffer A manually" "SBC_DMA_TRG_A_0,SBC_DMA_TRG_A_1" newline bitfld.long 0x10 4. "SBC_BIT_CNT_RST,Reset bit counter in the Stream Buffer" "SBC_BIT_CNT_RST_0,SBC_BIT_CNT_RST_1" newline bitfld.long 0x10 0. "SBC_BUFSEL,Selects active buffer between A and B: Write" "Buffer A is selected,Buffer B is selected This bit is ignored if.." line.long 0x14 "SBC_STAT,Stream Buffer Controller Status" rbitfld.long 0x14 6. "SBC_ST_SRCH," "SBC_ST_SRCH_0,SBC_ST_SRCH_1" newline bitfld.long 0x14 5. "SBC_DMA_B," "Force to exit busy state while waiting for an..,Indicates that the Stream Buffer Controller is.." newline bitfld.long 0x14 4. "SBC_DMA_A," "Force to exit busy state while waiting for an..,Indicates that the Stream Buffer Controller is.." newline rbitfld.long 0x14 3. "SBC_WR_HLT," "SBC_WR_HLT_0,SBC_WR_HLT_1" newline rbitfld.long 0x14 2. "SBC_RD_HLT," "SBC_RD_HLT_0,SBC_RD_HLT_1" newline rbitfld.long 0x14 1. "SBC_WR," "SBC_WR_0,SBC_WR_1" newline rbitfld.long 0x14 0. "SBC_RD," "SBC_RD_0,SBC_RD_1" line.long 0x18 "SBC_BUFCFG,Stream Buffer Controller Buffer Configuration" bitfld.long 0x18 31. "SBC_FLUSH_MODE,SBC FIFO flush mode select for encoding" "Flush FIFO when EOS flag is sent by Codec Engine,Flush FIFO when DONE or EOS flag is sent by.." newline bitfld.long 0x18 30. "SBC_FMO_MODE,SBC FIFO flush mode select for encoding" "Buffer A and B pointers are used for Stream Data..,Buffer A pointer and SBC_A_BITPTR[30:28].." newline bitfld.long 0x18 24. "SBC_DBL,Enables double buffer mode" "disabled (buffer A only mode),enabled (buffer A and buffer B)" newline bitfld.long 0x18 20.--21. "SBC_PGSZ,Specifies the page size of buffer A and B in the unit of 1024 [byte]" "SBC_PGSZ_0,SBC_PGSZ_1,SBC_PGSZ_2,SBC_PGSZ_3" newline hexmask.long.word 0x18 4.--17. 1. "SBC_BUFTOP_17_4,Specifies the base address [17:4] of the bitstream buffer in SL2" newline rbitfld.long 0x18 0.--3. "SBC_BUFTOP_3_0,Specifies the base address [3:0] of the bitstream buffer in SL2" "SBC_BUFTOP_3_0_0,SBC_BUFTOP_3_0_1,SBC_BUFTOP_3_0_2,SBC_BUFTOP_3_0_3,SBC_BUFTOP_3_0_4,SBC_BUFTOP_3_0_5,SBC_BUFTOP_3_0_6,SBC_BUFTOP_3_0_7,SBC_BUFTOP_3_0_8,SBC_BUFTOP_3_0_9,SBC_BUFTOP_3_0_10,SBC_BUFTOP_3_0_11,SBC_BUFTOP_3_0_12,SBC_BUFTOP_3_0_13,SBC_BUFTOP_3_0_14,SBC_BUFTOP_3_0_15" line.long 0x1C "SBC_A_BITPTR,Stream Buffer Controller A Bit Pointer" bitfld.long 0x1C 28.--30. "FMO_DMA_ID,Indicates the ID number of bitstream data in SL2 memory" "FMO_DMA_ID_0,FMO_DMA_ID_1,FMO_DMA_ID_2,FMO_DMA_ID_3,FMO_DMA_ID_4,FMO_DMA_ID_5,FMO_DMA_ID_6,FMO_DMA_ID_7" newline bitfld.long 0x1C 24.--25. "NUM_ZERO_A,Indicates the number of 0 bytes in the past for buffer A" "NUM_ZERO_A_0,NUM_ZERO_A_1,NUM_ZERO_A_2,NUM_ZERO_A_3" newline hexmask.long.word 0x1C 8.--21. 1. "BYTEPTR_A,Indicates the current byte offset address in Buffer A of the byte containing the next bit in the bitstream" newline bitfld.long 0x1C 0.--2. "BITPTR_A,Indicates the next bit position in the byte at BYTEPTR_A" "BITPTR_A_0,BITPTR_A_1,BITPTR_A_2,BITPTR_A_3,BITPTR_A_4,BITPTR_A_5,BITPTR_A_6,BITPTR_A_7" line.long 0x20 "SBC_A_DMAPG,Stream Buffer Controller A DMA Page" hexmask.long.byte 0x20 0.--7. 1. "DMAPG_A,Indicates the page that is being accessed from DMA for bitstream data transferring" line.long 0x24 "SBC_B_BITPTR,Stream Buffer Controller B Bit Pointer" bitfld.long 0x24 24.--25. "NUM_ZERO_B,Indicates the number of 0 bytes in the past for buffer B" "NUM_ZERO_B_0,NUM_ZERO_B_1,NUM_ZERO_B_2,NUM_ZERO_B_3" newline hexmask.long.word 0x24 8.--21. 1. "BYTEPTR_B,Indicates the current byte offset address in Buffer B of the byte containing the next bit in the bitstream" newline bitfld.long 0x24 0.--2. "BITPTR_B,Indicates the next bit position in the byte at BYTEPTR_B" "BITPTR_B_0,BITPTR_B_1,BITPTR_B_2,BITPTR_B_3,BITPTR_B_4,BITPTR_B_5,BITPTR_B_6,BITPTR_B_7" line.long 0x28 "SBC_B_DMAPG,Stream Buffer Controller B DMA Page" bitfld.long 0x28 0. "DMAPG_B,Indicates the page that is being accessed from DMA for bitstream data transferring" "DMAPG_B_0,DMAPG_B_1" line.long 0x2C "SBC_TTLCNT,Stream Buffer Controller Total Bit Counter" line.long 0x30 "SBC_RSDCNT,Stream Buffer Controller Residual Layer Bit Counter" group.long 0x38++0x0B line.long 0x00 "SBC_SRCH_PG_CNT,Buffer page counter for start code searching" hexmask.long.word 0x00 0.--15. 1. "SRCH_PG_CNT,ECD3 search start code until the page counter reach this number" line.long 0x04 "SBC_FMO_DMA_STAT,FMO_DMA status register" hexmask.long.byte 0x04 0.--7. 1. "FMO_DMA,Indicates FMO_DMA_ID for stream interrupt at buffer page boundary" line.long 0x08 "MBPC_PIC_DIM,Picture Dimension" bitfld.long 0x08 31. "CUR_MBAFF,CUR_MBAFF = 1 indicates that current picture is in H.264 MBAFF mode" "CUR_MBAFF_0,CUR_MBAFF_1" newline hexmask.long.word 0x08 16.--29. 1. "PIC_H,PIC_H specifies the picture height in macroblocks which is calculated by PIC_H = ((picture height in pixels) + 15)/16" newline hexmask.long.word 0x08 0.--13. 1. "PIC_W,PIC_W specifies the picture width in macroblocks which is calculated by PIC_W = ((picture width in pixels) + 15)/16" group.long 0x50++0x0F line.long 0x00 "MBPC_STAT,MB Position Controller Status" bitfld.long 0x00 9. "PIC_END_FLAG,PIC_END_FLAG = 1 indicates that the macroblock will be processed is at the end of the picture" "PIC_END_FLAG_0,PIC_END_FLAG_1" newline bitfld.long 0x00 8. "FIRST_MB_FLAG,FIRST_MB_FLAG = 1 indicates that the macroblock will be processed is the first macroblock in the slice" "FIRST_MB_FLAG_0,FIRST_MB_FLAG_1" newline bitfld.long 0x00 4.--7. "PIC_BOUND,PIC_BOUND indicates that the picture boundary status of the current macroblock (in case of MBAFF mode the unit is macroblock-pair)" "PIC_BOUND_0,PIC_BOUND_1,PIC_BOUND_2,PIC_BOUND_3,PIC_BOUND_4,PIC_BOUND_5,PIC_BOUND_6,PIC_BOUND_7,PIC_BOUND_8,PIC_BOUND_9,PIC_BOUND_10,PIC_BOUND_11,PIC_BOUND_12,PIC_BOUND_13,PIC_BOUND_14,PIC_BOUND_15" newline bitfld.long 0x00 0.--3. "MB_AVAIL,MB_AVAIL indicates that the availabilities of neighboring macroblocks (in case of MBAFF mode the unit is macroblock-pair)" "MB_AVAIL_0,MB_AVAIL_1,MB_AVAIL_2,MB_AVAIL_3,MB_AVAIL_4,MB_AVAIL_5,MB_AVAIL_6,MB_AVAIL_7,MB_AVAIL_8,MB_AVAIL_9,MB_AVAIL_10,MB_AVAIL_11,MB_AVAIL_12,MB_AVAIL_13,MB_AVAIL_14,MB_AVAIL_15" line.long 0x04 "MBPC_POS,Macroblock Position" hexmask.long.word 0x04 16.--28. 1. "MB_Y,MB_Y equals the macroblock y-position in the picture" newline hexmask.long.word 0x04 0.--12. 1. "MB_X,MB_X equals the macroblock x-position in the picture" line.long 0x08 "MBPC_PMC,Macroblock Count In Picture" hexmask.long 0x08 0.--25. 1. "PIC_MB_CNT,PIC_MB_CNT equals the macroblock count in the picture" line.long 0x0C "MBPC_SMC,Macroblock Count In Slice" hexmask.long 0x0C 0.--25. 1. "SLC_MB_CNT,SLC_MB_CNT equals the macroblock count in the slice" group.long 0x64++0x17 line.long 0x00 "DTBC_BP_MB,Data Buffer Controller MB Base Buffer Pointer" rbitfld.long 0x00 28.--31. "BP_MB_UR_15_12,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_15_12_0,BP_MB_UR_15_12_1,BP_MB_UR_15_12_2,BP_MB_UR_15_12_3,BP_MB_UR_15_12_4,BP_MB_UR_15_12_5,BP_MB_UR_15_12_6,BP_MB_UR_15_12_7,BP_MB_UR_15_12_8,BP_MB_UR_15_12_9,BP_MB_UR_15_12_10,BP_MB_UR_15_12_11,BP_MB_UR_15_12_12,BP_MB_UR_15_12_13,BP_MB_UR_15_12_14,BP_MB_UR_15_12_15" newline hexmask.long.byte 0x00 20.--27. 1. "BP_MB_UR_11_4,BP_MB_UR specifies the base pointer to the upper macroblock buffer" newline rbitfld.long 0x00 16.--19. "BP_MB_UR_3_0,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_3_0_0,BP_MB_UR_3_0_1,BP_MB_UR_3_0_2,BP_MB_UR_3_0_3,BP_MB_UR_3_0_4,BP_MB_UR_3_0_5,BP_MB_UR_3_0_6,BP_MB_UR_3_0_7,BP_MB_UR_3_0_8,BP_MB_UR_3_0_9,BP_MB_UR_3_0_10,BP_MB_UR_3_0_11,BP_MB_UR_3_0_12,BP_MB_UR_3_0_13,BP_MB_UR_3_0_14,BP_MB_UR_3_0_15" newline rbitfld.long 0x00 12.--15. "BP_MB_CUR_15_12,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_15_12_0,BP_MB_CUR_15_12_1,BP_MB_CUR_15_12_2,BP_MB_CUR_15_12_3,BP_MB_CUR_15_12_4,BP_MB_CUR_15_12_5,BP_MB_CUR_15_12_6,BP_MB_CUR_15_12_7,BP_MB_CUR_15_12_8,BP_MB_CUR_15_12_9,BP_MB_CUR_15_12_10,BP_MB_CUR_15_12_11,BP_MB_CUR_15_12_12,BP_MB_CUR_15_12_13,BP_MB_CUR_15_12_14,BP_MB_CUR_15_12_15" newline hexmask.long.byte 0x00 4.--11. 1. "BP_MB_CUR_11_4,BP_MB_CUR specifies the base pointer to the current macroblock buffer" newline rbitfld.long 0x00 0.--3. "BP_MB_CUR_3_0,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_3_0_0,BP_MB_CUR_3_0_1,BP_MB_CUR_3_0_2,BP_MB_CUR_3_0_3,BP_MB_CUR_3_0_4,BP_MB_CUR_3_0_5,BP_MB_CUR_3_0_6,BP_MB_CUR_3_0_7,BP_MB_CUR_3_0_8,BP_MB_CUR_3_0_9,BP_MB_CUR_3_0_10,BP_MB_CUR_3_0_11,BP_MB_CUR_3_0_12,BP_MB_CUR_3_0_13,BP_MB_CUR_3_0_14,BP_MB_CUR_3_0_15" line.long 0x04 "DTBC_BP_COL,Data Buffer Controller Co-located MB Buffer Base Pointer" rbitfld.long 0x04 28.--31. "BP_COL_B_15_12,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_15_12_0,BP_COL_B_15_12_1,BP_COL_B_15_12_2,BP_COL_B_15_12_3,BP_COL_B_15_12_4,BP_COL_B_15_12_5,BP_COL_B_15_12_6,BP_COL_B_15_12_7,BP_COL_B_15_12_8,BP_COL_B_15_12_9,BP_COL_B_15_12_10,BP_COL_B_15_12_11,BP_COL_B_15_12_12,BP_COL_B_15_12_13,BP_COL_B_15_12_14,BP_COL_B_15_12_15" newline hexmask.long.byte 0x04 20.--27. 1. "BP_COL_B_11_4,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" newline rbitfld.long 0x04 16.--19. "BP_COL_B_3_0,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_3_0_0,BP_COL_B_3_0_1,BP_COL_B_3_0_2,BP_COL_B_3_0_3,BP_COL_B_3_0_4,BP_COL_B_3_0_5,BP_COL_B_3_0_6,BP_COL_B_3_0_7,BP_COL_B_3_0_8,BP_COL_B_3_0_9,BP_COL_B_3_0_10,BP_COL_B_3_0_11,BP_COL_B_3_0_12,BP_COL_B_3_0_13,BP_COL_B_3_0_14,BP_COL_B_3_0_15" newline rbitfld.long 0x04 12.--15. "BP_COL_A_15_12,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_15_12_0,BP_COL_A_15_12_1,BP_COL_A_15_12_2,BP_COL_A_15_12_3,BP_COL_A_15_12_4,BP_COL_A_15_12_5,BP_COL_A_15_12_6,BP_COL_A_15_12_7,BP_COL_A_15_12_8,BP_COL_A_15_12_9,BP_COL_A_15_12_10,BP_COL_A_15_12_11,BP_COL_A_15_12_12,BP_COL_A_15_12_13,BP_COL_A_15_12_14,BP_COL_A_15_12_15" newline hexmask.long.byte 0x04 4.--11. 1. "BP_COL_A_11_4,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" newline rbitfld.long 0x04 0.--3. "BP_COL_A_3_0,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_3_0_0,BP_COL_A_3_0_1,BP_COL_A_3_0_2,BP_COL_A_3_0_3,BP_COL_A_3_0_4,BP_COL_A_3_0_5,BP_COL_A_3_0_6,BP_COL_A_3_0_7,BP_COL_A_3_0_8,BP_COL_A_3_0_9,BP_COL_A_3_0_10,BP_COL_A_3_0_11,BP_COL_A_3_0_12,BP_COL_A_3_0_13,BP_COL_A_3_0_14,BP_COL_A_3_0_15" line.long 0x08 "DTBC_BP_RSD,Data Buffer Controller Residual Buffer Base Pointer" rbitfld.long 0x08 28.--31. "BP_RSD_15_12,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_15_12_0,BP_RSD_15_12_1,BP_RSD_15_12_2,BP_RSD_15_12_3,BP_RSD_15_12_4,BP_RSD_15_12_5,BP_RSD_15_12_6,BP_RSD_15_12_7,BP_RSD_15_12_8,BP_RSD_15_12_9,BP_RSD_15_12_10,BP_RSD_15_12_11,BP_RSD_15_12_12,BP_RSD_15_12_13,BP_RSD_15_12_14,BP_RSD_15_12_15" newline hexmask.long.byte 0x08 20.--27. 1. "BP_RSD_11_4,BP_RSD specifies the base pointer to the residual data buffer" newline rbitfld.long 0x08 16.--19. "BP_RSD_3_0,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_3_0_0,BP_RSD_3_0_1,BP_RSD_3_0_2,BP_RSD_3_0_3,BP_RSD_3_0_4,BP_RSD_3_0_5,BP_RSD_3_0_6,BP_RSD_3_0_7,BP_RSD_3_0_8,BP_RSD_3_0_9,BP_RSD_3_0_10,BP_RSD_3_0_11,BP_RSD_3_0_12,BP_RSD_3_0_13,BP_RSD_3_0_14,BP_RSD_3_0_15" line.long 0x0C "DTBC_DP_UL,Data Buffer Controller Data Pointer 0" rbitfld.long 0x0C 13.--15. "PTR_MB_UL_15_13,Current pointer [15:13] to the upper left macroblock data in work buffer" "PTR_MB_UL_15_13_0,PTR_MB_UL_15_13_1,PTR_MB_UL_15_13_2,PTR_MB_UL_15_13_3,PTR_MB_UL_15_13_4,PTR_MB_UL_15_13_5,PTR_MB_UL_15_13_6,PTR_MB_UL_15_13_7" newline hexmask.long.word 0x0C 4.--12. 1. "PTR_MB_UL_12_4,Current pointer [12:4] to the upper left macroblock data in work buffer" newline rbitfld.long 0x0C 0.--3. "PTR_MB_UL_3_0,Current pointer [3:0] to the upper left macroblock data in work buffer" "PTR_MB_UL_3_0_0,PTR_MB_UL_3_0_1,PTR_MB_UL_3_0_2,PTR_MB_UL_3_0_3,PTR_MB_UL_3_0_4,PTR_MB_UL_3_0_5,PTR_MB_UL_3_0_6,PTR_MB_UL_3_0_7,PTR_MB_UL_3_0_8,PTR_MB_UL_3_0_9,PTR_MB_UL_3_0_10,PTR_MB_UL_3_0_11,PTR_MB_UL_3_0_12,PTR_MB_UL_3_0_13,PTR_MB_UL_3_0_14,PTR_MB_UL_3_0_15" line.long 0x10 "DTBC_DP_UU_UR,Data Buffer Controller Data Pointer 1" rbitfld.long 0x10 29.--31. "PTR_MB_UU_15_13,Current pointer [15:13] to the upper macroblock data in work buffer" "PTR_MB_UU_15_13_0,PTR_MB_UU_15_13_1,PTR_MB_UU_15_13_2,PTR_MB_UU_15_13_3,PTR_MB_UU_15_13_4,PTR_MB_UU_15_13_5,PTR_MB_UU_15_13_6,PTR_MB_UU_15_13_7" newline hexmask.long.word 0x10 20.--28. 1. "PTR_MB_UU_12_4,Current pointer [12:4] to the upper macroblock data in work buffer" newline rbitfld.long 0x10 16.--19. "PTR_MB_UU_3_0,Current pointer [3:0] to the upper macroblock data in work buffer" "PTR_MB_UU_3_0_0,PTR_MB_UU_3_0_1,PTR_MB_UU_3_0_2,PTR_MB_UU_3_0_3,PTR_MB_UU_3_0_4,PTR_MB_UU_3_0_5,PTR_MB_UU_3_0_6,PTR_MB_UU_3_0_7,PTR_MB_UU_3_0_8,PTR_MB_UU_3_0_9,PTR_MB_UU_3_0_10,PTR_MB_UU_3_0_11,PTR_MB_UU_3_0_12,PTR_MB_UU_3_0_13,PTR_MB_UU_3_0_14,PTR_MB_UU_3_0_15" newline rbitfld.long 0x10 13.--15. "PTR_MB_UR_15_13,Current pointer [15:13] to the upper-right macroblock data in work buffer" "PTR_MB_UR_15_13_0,PTR_MB_UR_15_13_1,PTR_MB_UR_15_13_2,PTR_MB_UR_15_13_3,PTR_MB_UR_15_13_4,PTR_MB_UR_15_13_5,PTR_MB_UR_15_13_6,PTR_MB_UR_15_13_7" newline hexmask.long.word 0x10 4.--12. 1. "PTR_MB_UR_12_4,Current pointer [12:4] to the upper-right macroblock data in work buffer" newline rbitfld.long 0x10 0.--3. "PTR_MB_UR_3_0,Current pointer [3:0] to the upper-right macroblock data in work buffer" "PTR_MB_UR_3_0_0,PTR_MB_UR_3_0_1,PTR_MB_UR_3_0_2,PTR_MB_UR_3_0_3,PTR_MB_UR_3_0_4,PTR_MB_UR_3_0_5,PTR_MB_UR_3_0_6,PTR_MB_UR_3_0_7,PTR_MB_UR_3_0_8,PTR_MB_UR_3_0_9,PTR_MB_UR_3_0_10,PTR_MB_UR_3_0_11,PTR_MB_UR_3_0_12,PTR_MB_UR_3_0_13,PTR_MB_UR_3_0_14,PTR_MB_UR_3_0_15" line.long 0x14 "DTBC_DP_LL_CUR,Data Buffer Controller Data Pointer 2" rbitfld.long 0x14 29.--31. "PTR_MB_LL_15_13,Current pointer [15:13] to the left macroblock data in work buffer" "PTR_MB_LL_15_13_0,PTR_MB_LL_15_13_1,PTR_MB_LL_15_13_2,PTR_MB_LL_15_13_3,PTR_MB_LL_15_13_4,PTR_MB_LL_15_13_5,PTR_MB_LL_15_13_6,PTR_MB_LL_15_13_7" newline hexmask.long.word 0x14 20.--28. 1. "PTR_MB_LL_12_4,Current pointer [12:4] to the left macroblock data in work buffer" newline rbitfld.long 0x14 16.--19. "PTR_MB_LL_3_0,Current pointer [3:0] to the left macroblock data in work buffer" "PTR_MB_LL_3_0_0,PTR_MB_LL_3_0_1,PTR_MB_LL_3_0_2,PTR_MB_LL_3_0_3,PTR_MB_LL_3_0_4,PTR_MB_LL_3_0_5,PTR_MB_LL_3_0_6,PTR_MB_LL_3_0_7,PTR_MB_LL_3_0_8,PTR_MB_LL_3_0_9,PTR_MB_LL_3_0_10,PTR_MB_LL_3_0_11,PTR_MB_LL_3_0_12,PTR_MB_LL_3_0_13,PTR_MB_LL_3_0_14,PTR_MB_LL_3_0_15" newline rbitfld.long 0x14 13.--15. "PTR_MB_CUR_15_13,Current pointer [15:13] to the current macroblock data in work buffer" "PTR_MB_CUR_15_13_0,PTR_MB_CUR_15_13_1,PTR_MB_CUR_15_13_2,PTR_MB_CUR_15_13_3,PTR_MB_CUR_15_13_4,PTR_MB_CUR_15_13_5,PTR_MB_CUR_15_13_6,PTR_MB_CUR_15_13_7" newline hexmask.long.word 0x14 4.--12. 1. "PTR_MB_CUR_12_4,Current pointer [12:4] to the current macroblock data in work buffer" newline rbitfld.long 0x14 0.--3. "PTR_MB_CUR_3_0,Current pointer [3:0] to the current macroblock data in work buffer" "PTR_MB_CUR_3_0_0,PTR_MB_CUR_3_0_1,PTR_MB_CUR_3_0_2,PTR_MB_CUR_3_0_3,PTR_MB_CUR_3_0_4,PTR_MB_CUR_3_0_5,PTR_MB_CUR_3_0_6,PTR_MB_CUR_3_0_7,PTR_MB_CUR_3_0_8,PTR_MB_CUR_3_0_9,PTR_MB_CUR_3_0_10,PTR_MB_CUR_3_0_11,PTR_MB_CUR_3_0_12,PTR_MB_CUR_3_0_13,PTR_MB_CUR_3_0_14,PTR_MB_CUR_3_0_15" group.long 0x84++0x0F line.long 0x00 "DTBC_DP_ULUR2,Data Buffer Controller Data Pointer 5" rbitfld.long 0x00 29.--31. "PTR_MB_UL2_15_13,Current pointer [15:13] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_15_13_0,PTR_MB_UL2_15_13_1,PTR_MB_UL2_15_13_2,PTR_MB_UL2_15_13_3,PTR_MB_UL2_15_13_4,PTR_MB_UL2_15_13_5,PTR_MB_UL2_15_13_6,PTR_MB_UL2_15_13_7" newline hexmask.long.word 0x00 20.--28. 1. "PTR_MB_UL2_12_4,Current pointer [12:4] to the macroblock left to the upper left macroblock data in work buffer" newline rbitfld.long 0x00 16.--19. "PTR_MB_UL2_3_0,Current pointer [3:0] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_3_0_0,PTR_MB_UL2_3_0_1,PTR_MB_UL2_3_0_2,PTR_MB_UL2_3_0_3,PTR_MB_UL2_3_0_4,PTR_MB_UL2_3_0_5,PTR_MB_UL2_3_0_6,PTR_MB_UL2_3_0_7,PTR_MB_UL2_3_0_8,PTR_MB_UL2_3_0_9,PTR_MB_UL2_3_0_10,PTR_MB_UL2_3_0_11,PTR_MB_UL2_3_0_12,PTR_MB_UL2_3_0_13,PTR_MB_UL2_3_0_14,PTR_MB_UL2_3_0_15" newline rbitfld.long 0x00 13.--15. "PTR_MB_UR2_15_13,Current pointer [15:13] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_15_13_0,PTR_MB_UR2_15_13_1,PTR_MB_UR2_15_13_2,PTR_MB_UR2_15_13_3,PTR_MB_UR2_15_13_4,PTR_MB_UR2_15_13_5,PTR_MB_UR2_15_13_6,PTR_MB_UR2_15_13_7" newline hexmask.long.word 0x00 4.--12. 1. "PTR_MB_UR2_12_4,Current pointer [12:4] to the macroblock right to the upper-right macroblock data in work buffer" newline rbitfld.long 0x00 0.--3. "PTR_MB_UR2_3_0,Current pointer [3:0] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_3_0_0,PTR_MB_UR2_3_0_1,PTR_MB_UR2_3_0_2,PTR_MB_UR2_3_0_3,PTR_MB_UR2_3_0_4,PTR_MB_UR2_3_0_5,PTR_MB_UR2_3_0_6,PTR_MB_UR2_3_0_7,PTR_MB_UR2_3_0_8,PTR_MB_UR2_3_0_9,PTR_MB_UR2_3_0_10,PTR_MB_UR2_3_0_11,PTR_MB_UR2_3_0_12,PTR_MB_UR2_3_0_13,PTR_MB_UR2_3_0_14,PTR_MB_UR2_3_0_15" line.long 0x04 "DTBC_DP_SLICE,Slice data pointer" rbitfld.long 0x04 13.--15. "PTR_SLICE_15_13,Specifies the pointer [15:13] to slice or picture information data" "PTR_SLICE_15_13_0,PTR_SLICE_15_13_1,PTR_SLICE_15_13_2,PTR_SLICE_15_13_3,PTR_SLICE_15_13_4,PTR_SLICE_15_13_5,PTR_SLICE_15_13_6,PTR_SLICE_15_13_7" newline hexmask.long.word 0x04 4.--12. 1. "PTR_SLICE_12_4,Specifies the pointer [12:4] to slice or picture information data" newline rbitfld.long 0x04 0.--3. "PTR_SLICE_3_0,Specifies the pointer [3:0] to slice or picture information data" "PTR_SLICE_3_0_0,PTR_SLICE_3_0_1,PTR_SLICE_3_0_2,PTR_SLICE_3_0_3,PTR_SLICE_3_0_4,PTR_SLICE_3_0_5,PTR_SLICE_3_0_6,PTR_SLICE_3_0_7,PTR_SLICE_3_0_8,PTR_SLICE_3_0_9,PTR_SLICE_3_0_10,PTR_SLICE_3_0_11,PTR_SLICE_3_0_12,PTR_SLICE_3_0_13,PTR_SLICE_3_0_14,PTR_SLICE_3_0_15" line.long 0x08 "DTBC_DP_LL2,Data Buffer Controller data pointer" rbitfld.long 0x08 13.--15. "PTR_MB_LL2_15_13,Current pointer [15:13] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_15_13_0,PTR_MB_LL2_15_13_1,PTR_MB_LL2_15_13_2,PTR_MB_LL2_15_13_3,PTR_MB_LL2_15_13_4,PTR_MB_LL2_15_13_5,PTR_MB_LL2_15_13_6,PTR_MB_LL2_15_13_7" newline hexmask.long.word 0x08 4.--12. 1. "PTR_MB_LL2_12_4,Current pointer [12:4] to the macroblock left to the left macroblock data in work buffer" newline rbitfld.long 0x08 0.--3. "PTR_MB_LL2_3_0,Current pointer [3:0] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_3_0_0,PTR_MB_LL2_3_0_1,PTR_MB_LL2_3_0_2,PTR_MB_LL2_3_0_3,PTR_MB_LL2_3_0_4,PTR_MB_LL2_3_0_5,PTR_MB_LL2_3_0_6,PTR_MB_LL2_3_0_7,PTR_MB_LL2_3_0_8,PTR_MB_LL2_3_0_9,PTR_MB_LL2_3_0_10,PTR_MB_LL2_3_0_11,PTR_MB_LL2_3_0_12,PTR_MB_LL2_3_0_13,PTR_MB_LL2_3_0_14,PTR_MB_LL2_3_0_15" line.long 0x0C "DTBC_CUR_MB_SIZE,Current Picture Macro Block element size" hexmask.long.byte 0x0C 4.--11. 1. "CUR_MB_SIZE_11_4,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" newline rbitfld.long 0x0C 0.--3. "CUR_MB_SIZE_3_0,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" "CUR_MB_SIZE_3_0_0,CUR_MB_SIZE_3_0_1,CUR_MB_SIZE_3_0_2,CUR_MB_SIZE_3_0_3,CUR_MB_SIZE_3_0_4,CUR_MB_SIZE_3_0_5,CUR_MB_SIZE_3_0_6,CUR_MB_SIZE_3_0_7,CUR_MB_SIZE_3_0_8,CUR_MB_SIZE_3_0_9,CUR_MB_SIZE_3_0_10,CUR_MB_SIZE_3_0_11,CUR_MB_SIZE_3_0_12,CUR_MB_SIZE_3_0_13,CUR_MB_SIZE_3_0_14,CUR_MB_SIZE_3_0_15" group.long 0xA0++0x07 line.long 0x00 "CDC_MODE,Codec Mode (also works as view page)" bitfld.long 0x00 4. "DIR,Selects the codec direction: Write" "Indicates the codec engine is decoding,Indicates the codec engine is encoding" newline bitfld.long 0x00 0.--3. "MODE,Selects the active codec Selected Codec (Selected Codec Engine)" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,MODE_6,MODE_7,MODE_8,MODE_9,MODE_10,?,?,?,?,?" line.long 0x04 "AVS_STAT,AVS STAT register" bitfld.long 0x04 31. "STAT_END_OF_SLICE,stat_end_of_vop ECD sets this field to 1 when the current macroblock is the last macroblock in a VOP Once this field is set ECD keeps this field to 1 until the next macroblock processing is started" "0,1" newline bitfld.long 0x04 9. "ERR_ILL_NEXT_START_CODE_SEARCH,err_ill_next_start_code_search If ECD founds error and ECD status is changed into ERR in error detection described in section 8.5. ECD starts to search the next start code search" "0,1" newline bitfld.long 0x04 8. "ERR_ILL_END_OF_SLICE,err_ill_end_of_slice Some encoder wrongly encode EOS" "0,1" newline bitfld.long 0x04 7. "ERR_ILL_MB_SKIP_RUN,err_ill_mb_skip_run If ECD founds decoded mb_skip_run is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 6. "ERR_ILL_MB_TYPE,err_ill_mb_type If ECD founds decoded mb_type is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 5. "ERR_ILL_INTRA_CHROMA_PRED_MODE,err_ill_intra_chroma_pred_mode If ECD founds decoded intra_chroma_pred_mode is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 4. "ERR_ILL_MV_DIFF,err_ill_mv_diff If ECD founds decoded mv_diff is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 3. "ERR_ILL_CBP,err_ill_cbp If ECD founds decoded cbp is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 2. "ERR_ILL_MB_QP_DELTA,err_ill_mb_qp_delta If ECD founds decoded mb_qp_delta is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 1. "ERR_ILL_COEFF,err_ill_coeff If ECD founds decoded coefficient is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 0. "ERR_ILL_EOB,err_ill_eob If ECD cannot found end of block in 64 coefficients this field is set to 1 by ECD; otherwise 0" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "H264_ERR_STAT,H.264 STAT register" bitfld.long 0x00 31. "EOS," "0,1" newline bitfld.long 0x00 4. "SC_ERR," "0,1" newline bitfld.long 0x00 3. "MV_ERR," "0,1" newline bitfld.long 0x00 2. "ALGN_ERR," "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR," "0,1" newline bitfld.long 0x00 0. "SYM_ERR," "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "INT_STATUS,INT STAT register" bitfld.long 0x00 31. "PRCS_DONE,If encoding or decoding of a picture is finished an interrupt pulse is asserted and this status bit becomes high" "not finished,processing done" newline bitfld.long 0x00 30. "EOS_DONE,If encoding of decoding of a scan is finished an interrupt pulse is asserted and this status bit becomes high" "not finished,processing done" newline bitfld.long 0x00 2. "BLK_COEF_NUM_ERR,If current MCU has a block which has more than 64 coefficients this error bit becomes high" "correct (all blocks inside the current MCU have..,incorrect (some blocks inside the current MCU.." newline bitfld.long 0x00 1. "RSTRT_INTVL_ERR,If number of MCU between neighbored restart markers is not equal to restart interval this error bit becomes high" "no error,restart interval error.." newline bitfld.long 0x00 0. "VLD_TBL_ERR,If stream data which is out of table is detected the JPEG core makes this bit high" "no error,out of table error.." rgroup.long 0xA4++0x03 line.long 0x00 "MP2_STAT,MP2 STAT register" bitfld.long 0x00 31. "STAT_END_OF_SLICE,Showing the current macroblock is the last macroblock in a slice" "0,1" newline bitfld.long 0x00 15. "ERR_DCCOEF_OVERFLOW,Showing the result of dc prediction is overflowed or under flowed" "0,1" newline bitfld.long 0x00 14. "ERR_ILL_NEXT_START_CODE_SEARCH,Showing next start code searching infinite error" "0,1" newline bitfld.long 0x00 13. "ERR_ILL_SLICE_START_POSITION,In decoding showing the following two data is mismatched: - macroblock position derived from slice_vertical_position and macroblock_address_increment - macroblock position in ECD MMR In encoding this field is fixed to 0" "0,1" newline bitfld.long 0x00 12. "ERR_ILL_QUANTISER_SCALE_CODE,In decoding decoded quantizer_scale_code is 0" "0,1" newline bitfld.long 0x00 11. "ERR_ILL_END_OF_SLICE,In decoding EOS cannot be found at the end of picture" "0,1" newline bitfld.long 0x00 10. "ERR_MB_ADDR_INCREMENT,In decoding VLD out of table in macroblock_address_increment" "0,1" newline bitfld.long 0x00 9. "ERR_MB_TYPE,In decoding VLD out of table in macroblock_type" "0,1" newline bitfld.long 0x00 8. "ERR_MOTION_CODE,In decoding VLD out of table in motion_code and dmv" "0,1" newline bitfld.long 0x00 7. "ERR_CBP,In decoding VLD out of table in coded_block_pattern" "0,1" newline bitfld.long 0x00 6. "ERR_DCT_COEF,In decoding VLD out of table in DCT coefficient" "0,1" newline bitfld.long 0x00 5. "ERR_ILL_MBTYPE_D_PIC,In decoding decoded macroblock_type != 1 when D-picture" "0,1" newline bitfld.long 0x00 4. "ERR_ILL_MARKER_CONCEALMENT,In decoding decoded marker_bit != 0 when both the concealment_motion_vector and macroblock_intra are equal to 1" "0,1" newline bitfld.long 0x00 3. "ERR_ILL_MP2_ESCAPE_LVL,In decoding decoded level from MPEG-2 ESCAPE code is 0x000 or 0x800" "0,1" newline bitfld.long 0x00 2. "ERR_ILL_MP1_ESCAPE_LVL,In decoding decoded level from MPEG-1 ESCAPE code is 0x0000 or 0x8000" "0,1" newline bitfld.long 0x00 1. "ERR_ILL_EOB,In decoding ECD cannot find EOB end of block in a 64 coefficient block" "0,1" newline bitfld.long 0x00 0. "ERR_ILL_EOM,In decoding ECD cannot find EOM end of macroblock at the end of macroblock when picture_type is D-picture" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "MP4_STAT,MP4 STAT register" bitfld.long 0x00 31. "STAT_END_OF_PACKET,ECD sets this field to 1 when the current macroblock is the last macroblock in a packet" "0,1" newline bitfld.long 0x00 25. "ERR_NEXT_START_CODE_SEARCH,ECD sets this field to 1 if next start code search is 'failed'" "0,1" newline bitfld.long 0x00 24. "ERR_PKT_RESYNC_MARKER,ECD sets this field to 1 when resync_marker at the beginning of packet header is incorrect" "0,1" newline bitfld.long 0x00 23. "ERR_PKT_NEXT_START_CODE,ECD sets this field to 1 when next_start_code at the end of VOP is incorrect or start_code at the beginning of slice or at the end of VOP is incorrect" "0,1" newline bitfld.long 0x00 22. "ERR_PKT_ZERO_BIT,ECD sets this field to 1 when zero_bit at the end of GOB or slice layer is incorrect or emulation_prevention_bit in slice header is incorrect" "0,1" newline bitfld.long 0x00 21. "ERR_PKT_MBNUM,ECD sets this field to 1 when macroblock_number in packet header is dropped" "0,1" newline bitfld.long 0x00 20. "ERR_PKT_QUANT_SCALE,ECD sets this field to 1 when quant_scale in packet header is illegal" "0,1" newline bitfld.long 0x00 19. "ERR_PKT_TIME,ECD sets this field to 1 when modulo_time or vop_time_increment in packet header is changed" "0,1" newline bitfld.long 0x00 18. "ERR_PKT_MARKER_BIT,ECD sets this field to 1 when marker_bit in packet header is incorrect" "0,1" newline bitfld.long 0x00 17. "ERR_PKT_CHG_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is changed" "0,1" newline bitfld.long 0x00 16. "ERR_PKT_ILL_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is illegal" "0,1" newline bitfld.long 0x00 15. "ERR_PKT_VOP_FCODE,ECD sets this field to 1 when vop_fcode_forward or vop_fcode_backward in packet header is illegal" "0,1" newline bitfld.long 0x00 14. "ERR_GOB_GOBNUM,ECD sets this field to 1 when gob_number is dropped or macroblock_address in slice header is dropped" "0,1" newline bitfld.long 0x00 13. "ERR_GOB_GOB_FRAME_ID,ECD sets this field to 1 when gob_frame_id is changed" "0,1" newline bitfld.long 0x00 12. "ERR_GOB_QUANT_SCALE,ECD sets this field to 1 when quant_scale in GOB header is illegal or slice_quantizer_information in slice header is illegal" "0,1" newline bitfld.long 0x00 11. "ERR_MBHD_MCBPC,ECD sets this field to 1 when mcbpc code is illegal" "0,1" newline bitfld.long 0x00 10. "ERR_MBHD_H263_4MV,ECD3 sets this field to 1 if one of the following two conditions is true: - H263_mode is ON deblocking_filter_mode = 0 no_gob_header = 0 and decoded macroblock type is INTRA4V or INTRA4V_Q" "0,1" newline bitfld.long 0x00 9. "ERR_MBHD_CBPY,ECD sets this field to 1 when cpby code is illegal (non-B-VOP)" "0,1" newline bitfld.long 0x00 7. "ERR_MBHD_MB_TYPE,ECD sets this field to 1 when mb_type code is illegal (B-VOP)" "0,1" newline bitfld.long 0x00 6. "ERR_MBHD_MV_DATA,ECD sets this field to 1 when horizontal_mv_data or vertical_mv_data code is illegal" "0,1" newline bitfld.long 0x00 5. "ERR_BLK_DCT_DC_SIZE,ECD sets this field to 1 when dct_dc_size code is illegal" "0,1" newline bitfld.long 0x00 4. "ERR_BLK_TCOEF,ECD sets this field to 1 when tcoef code is illegal" "0,1" newline bitfld.long 0x00 3. "ERR_BLK_MARKER_BIT,ECD sets this field to 1 when marker_bit in dct_dc_size ESCAPE3 or RVLC is incorrect" "0,1" newline bitfld.long 0x00 2. "ERR_BLK_ESCAPE_LEVEL,ECD sets this field to 1 when ESCAPE3 level = 0 or 0x800 RVLC ESCAPE level = 0 H.263 DC = 0x00 or 0x80 or H.263 ESCAPE level = 0 or 0x80" "0,1" newline bitfld.long 0x00 1. "ERR_BLK_RVLC_ESCAPE_CODE,ECD sets this field to 1 when the last ESCAPE code of RVLC ESCAPE is not '0000s'" "0,1" newline bitfld.long 0x00 0. "ERR_BLK_EOB,ECD sets this field to 1 when ECD cannot find EOB in 64 coefficients" "0,1" rgroup.long 0xA4++0x07 line.long 0x00 "VC1_STAT,VC-1 STAT register" bitfld.long 0x00 31. "INT_EOS," "0,1" newline bitfld.long 0x00 10. "WARN_EOS_SYNCMARKER,This issue is raised when ECD3 cannot find syncmarker header syntax even though a single-bit just after decoding last MB is equal to 0" "0,1" newline bitfld.long 0x00 9. "WARN_EOS_TRAILINGBIT," "0,1" newline bitfld.long 0x00 8. "WARN_MQUANT_OVERFLOW,warn_mquant_overflow" "MQUANT does not overflow,MQUANT overflow" newline bitfld.long 0x00 2. "ERR_EOS,err_eos indicates an error during search processing for next start code" "0,1" newline bitfld.long 0x00 1. "ERR_VLC_TABLE,err_vlc_table indicates when the following irregular cases happen" "0,1" newline bitfld.long 0x00 0. "ERR_BLK_COEF,err_blk_coef indicates when the following irregular cases happen" "0,1" line.long 0x04 "AVS_MASK,AVS MASK register" bitfld.long 0x04 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 9. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 8. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 7. "MASK_ERR_ILL_MB_SKIP_RUN,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 6. "MASK_ERR_ILL_MB_TYPE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 5. "MASK_ERR_ILL_INTRA_CHROMA_PRED_MODE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 4. "MASK_ERR_ILL_MV_DIFF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 3. "MASK_ERR_ILL_CBP,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 2. "MASK_ERR_ILL_MB_QP_DELTA,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 1. "MASK_ERR_ILL_COEFF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 0. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "H264_ERR_MSK,H.264 MASK register" rbitfld.long 0x00 31. "EOS_MSK,EOS_MSK = 1 enables detection of an EOS" "0,1" newline rbitfld.long 0x00 4. "SC_ERR_MSK,SC_ERR_MSK = 0 (fixed) which indicates that int_err will never be issued on detecting start code search error" "0,1" newline rbitfld.long 0x00 3. "MV_ERR_MSK,MV_ERR_MSK = 1 enables detection of mv errors (MV_ERR)" "0,1" newline bitfld.long 0x00 2. "ALGN_ERR_MSK,ALGN_ERR_MSK = 1 enables detection of CABAC alignment bits errors (ALGN_ERR)" "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR_MSK,IPCM_ALGN_ERR_MSK = 1 enables detection of I_PCM alignment bits errors (IPCM_ALGN_ERR)" "0,1" newline rbitfld.long 0x00 0. "SYM_ERR_MSK,SYM_ERR_MSK = 1 enables detections of all other bitstream errors (SYM_ERR)" "0,1" rgroup.long 0xA8++0x03 line.long 0x00 "INT_MASK,INT MASK register" bitfld.long 0x00 31. "PRCS_DONE_MASK,Mask register for prcs_done signal" "PRCS_DONE signal disable,PRCS_DONE signal enable" newline bitfld.long 0x00 30. "EOS_MASK,Mask register for eos_done pulse signal" "EOS_DONE signal disable,EOS_DONE signal enable" newline bitfld.long 0x00 0. "VLD_TBL_ERR,Mask register for control of error interrupt assertion" "no error interrupt is asserted though condition..,error interrupt is asserted if condition is hit" group.long 0xA8++0x03 line.long 0x00 "MP2_MASK,MP2 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 15. "MASK_ERR_DCCOEF_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 13. "MASK_ERR_ILL_SLICE_START_POSITION,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_ILL_QUANTISER_SCALE_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 11. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MB_ADDR_INCREMENT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 9. "MASK_ERR_MB_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 8. "MASK_ERR_MOTION_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 7. "MASK_ERR_CBP,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 6. "MASK_ERR_DCT_COEF,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 5. "MASK_ERR_ILL_MBTYPE_D_PIC,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 4. "MASK_ERR_ILL_MARKER_CONCEALMENT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 3. "MASK_ERR_ILL_MP2_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_ILL_MP1_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 0. "MASK_ERR_ILL_EOM,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "MP4_MASK,MP4 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_PACKET,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 25. "MASK_ERR_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 24. "MASK_ERR_PKT_RESYNC_MARKER,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 23. "MASK_ERR_PKT_NEXT_START_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 22. "MASK_ERR_PKT_ZERO_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 21. "MASK_ERR_PKT_MBNUM,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 20. "MASK_ERR_PKT_QUANT_SCALE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 19. "MASK_ERR_PKT_TIME,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 18. "MASK_ERR_PKT_MARKER_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 17. "MASK_ERR_PKT_CHG_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 16. "MASK_ERR_PKT_ILL_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 15. "MASK_ERR_PKT_VOP_FCODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_GOB_GOBNUM,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 13. "MASK_ERR_GOB_GOB_FRAME_ID,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_GOB_QUANT_SCALE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 11. "MASK_ERR_MBHD_MCBPC,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MBHD_H263_4MV,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 9. "MASK_ERR_MBHD_CBPY,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 7. "MASK_ERR_MBHD_MB_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 6. "MASK_ERR_MBHD_MV_DATA,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 5. "MASK_ERR_BLK_DCT_DC_SIZE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 4. "MASK_ERR_BLK_TCOEF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 3. "MASK_ERR_BLK_MARKER_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_BLK_ESCAPE_LEVEL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_BLK_RVLC_ESCAPE_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 0. "MASK_ERR_BLK_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x07 line.long 0x00 "VC1_MASK,VC-1 MASK register" rbitfld.long 0x00 31. "MASK_INT_EOS," "0,1" newline rbitfld.long 0x00 10. "MASK_EOS_SYNCMARKER," "0,1" newline rbitfld.long 0x00 9. "MASK_WARN_EOS_TRAILINGBIT,Reserved" "0,1" newline bitfld.long 0x00 8. "MASK_MQUANT_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_EOS,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_VLC_TABLE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 0. "MASK_ERR_BLK_COEF,Mask flags correspond to status bits" "0,1" line.long 0x04 "AVS_WORK0,AVS WORK0 register" hexmask.long.word 0x04 16.--29. 1. "SKIPMBCOUNT,SkipMbCount This field specifies SkipMbCount described in AVS standard section 9.3" newline bitfld.long 0x04 9. "SLICE_DATA_RD_EN,Slice data read enable flag" "slice data is read only at the first macroblock..,slice data is read at every macroblocks AVS RTL.." newline bitfld.long 0x04 8. "NEXT_START_CODE_SEARCH,next_start_code_search This field specifies ECD starts start code search or not when error is occurred" "non-search,search" group.long 0xAC++0x03 line.long 0x00 "CFG_QP," bitfld.long 0x00 31. "MV_FLAG_EN,MV_FLAG_EN =1 enables motion vector and reference index comparison in decoding" "0,1" newline bitfld.long 0x00 30. "H264_RSV,Reserved for future use" "0,1" newline bitfld.long 0x00 29. "FORCE_SLC_LD,FORCE_SLC_LD = 1 forces slice information data loading from memory for each macroblock process" "0,1" newline rbitfld.long 0x00 28. "USE_CABAC,USE_CABAC = 1 indicates that the CABAC is in use for entropy coding" "0,1" newline bitfld.long 0x00 18.--19. "COL_MB_FMT,COL_MB_FMT indicates the macroblock header format type for the co-located macroblock data" "Bi-16-MV format,16-MV format,Bi-4-MV format,The reserved ECD3 automatically loads.." newline bitfld.long 0x00 16.--17. "MB_FMT,MB_FMT indicates the macroblock header format type for the current macroblock and neighboring macroblocks in the current picture" "Bi-16-MV format,16-MV format,Bi-4-MV format,The reserved ECD3 automatically loads.." newline bitfld.long 0x00 8.--13. "QP_DELTA,QP_DELTA is equal to mb_qp_delta of the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "QP,QP is equal to the quantizer parameter for the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x03 line.long 0x00 "JPEG_CTRL,JPEG Control register" hexmask.long.word 0x00 16.--31. 1. "DC_PRED_Y,Luminance DC prediction value is stored in register" newline rbitfld.long 0x00 8.--10. "RSTRT_MRKR_CNT,Restart marker counter value (during encoding only) is reflected in this register" "RSTRT_MRKR_CNT_0,RSTRT_MRKR_CNT_1,RSTRT_MRKR_CNT_2,RSTRT_MRKR_CNT_3,RSTRT_MRKR_CNT_4,RSTRT_MRKR_CNT_5,RSTRT_MRKR_CNT_6,RSTRT_MRKR_CNT_7" newline bitfld.long 0x00 1. "DC_PRED_RST,If this register bit is high DC prediction for the first block of the current MCU is not executed" "DC prediction is executed,DC prediction is reset" newline bitfld.long 0x00 0. "INIT_EN,This bit controls initialization of JPEG core on ECD module" "initialize disable,initialize start" group.long 0xAC++0x03 line.long 0x00 "MP2_WORK0,MP2 WORK0 register" hexmask.long.word 0x00 16.--31. 1. "MB_SKIP_RUN,Specifies the number of macroblocks to be skipped" newline bitfld.long 0x00 11. "START_CODE_SEARCH_FLAG,Specifies whether ECD starts searching next start code or not when error is occurred in decoding" "Not search next start code,Search next start code In encoding this field.." newline bitfld.long 0x00 10. "MACROBLOCK_MOTION_BACKWARD,Specifies macroblock_motion_backward described in MPEG-2 standard section 6.3.17.1" "0,1" newline bitfld.long 0x00 9. "MACROBLOCK_MOTION_FORWARD,Specifies macroblock_motion_forward described in MPEG-2 standard section 6.3.17.1" "0,1" newline bitfld.long 0x00 0.--4. "PREV_QUANTISER_SCALE_CODE,Specifies previous macroblock's quantizer_scale_code described in MPEG-2 standard section 6.3.16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x03 line.long 0x00 "MP4_WORK0,MP4 WORK0 register" bitfld.long 0x00 24.--28. "RUNNINGQP,This field is used for reserving runningQp for the next macroblock not showing the current macroblock's quantizer_scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--22. "VOP_FCODE_BACKWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "VOP_FCODE_FORWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--15. "DP_MODE,This field indicates which data is encoding or decoding in data partitioning mode" "GOB header or motion and header information..,texture header processing,TCOEF processing or packet header In non data..,?..." newline bitfld.long 0x00 12.--13. "GOB_FRAME_ID,This field specifies gob_frame_id which is updated at gob header" "0,1,2,3" newline bitfld.long 0x00 8.--10. "INTRA_DC_VLC_THR,This is a 3-bit code that specifies a threshold value of quantizer scale used to switch between two VLC's for coding of Intra DC coefficients" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "FIRST_NON_EMPTY_HEADER,This is the flag to indicate the first non empty GOB header or not" "0,1" newline bitfld.long 0x00 6. "MINI_SLICE_HEADER_FLAG,In H.263 decoding this field specifies whether the current slice header is mini slice header or not" "non mini slice header,mini slice header Otherwise this field must be 0" newline bitfld.long 0x00 5. "START_CODE_SEARCH_FLAG,In decoding this field specifies whether ECD starts searching next_start_code and resync_marker or not when error is occurred in decoding" "Not search next start code and resync marker,Search next start code and resync marker In.." newline bitfld.long 0x00 0.--4. "GOB_NUMBER,In decoding this field specifies gob_number of the current macroblock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x07 line.long 0x00 "VC1_WORK,VC-1 WORK register" bitfld.long 0x00 8. "FIXED_LENTH_CODE,Presence of Fixed Length Code (escape mode 3) Setting 1 specifies the first case of escape mode 3 in a frame" "non-first case of escape mode 3 in frame,first case of escape mode 3 in frame" newline rbitfld.long 0x00 7. "FIXED_TO_ZERO," "0,1" newline bitfld.long 0x00 4.--6. "RUN_CODE_SIZEOFESCAPE_MODE_3,Run code size of escape mode 3 Run code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "LEVEL_CODE_SIZEOFESCAPE_MODE_3,Level code size of escape mode 3 Level code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AVS_WORK1,AVS WORK1 register" hexmask.long.word 0x04 20.--31. 1. "PTR_MVD_15_4,PTR_MVD Start address of temporary MVD info" newline rbitfld.long 0x04 16.--19. "PTR_MVD_3_0,PTR_MVD Start address of temporary MVD info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x04 4.--15. 1. "PTR_RUNLVL_15_4,PTR_RUNLVL Start address of temporary run level info" newline rbitfld.long 0x04 0.--3. "PTR_RUNLVL_3_0,PTR_RUNLVL Start address of temporary run level info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x03 line.long 0x00 "CDC_VP_4," hexmask.long.word 0x00 3.--15. 1. "ACPREDPTR_15_3,ACPREDPTR I picture except simple/main I picture" group.long 0xB0++0x03 line.long 0x00 "MP2_WORK1,MP2 WORK1 register" hexmask.long.word 0x00 16.--26. 1. "DCT_DC_PRED1,In decoding this value specifies dct_dc_pred[1] described in MPEG-2 standard section 7.2.1" newline hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED0,In decoding this value specifies dct_dc_pred[0] described in MPEG-2 standard section 7.2.1" group.long 0xB0++0x03 line.long 0x00 "MP4_WORK1,MP4 WORK1 register" hexmask.long.word 0x00 16.--29. 1. "SKIPRUN,In the case of B-VOP decoding if decoded macroblock_number in video_packet_header > the macroblock address counter ECD notices the macroblocks from the macroblock address counter to macroblock_number -1 would be not_coded macroblock" newline hexmask.long.byte 0x00 8.--15. 1. "SLICE_Y,In data partitioning this field shows the position of the first macroblock in a slice" newline hexmask.long.byte 0x00 0.--7. 1. "SLICE_X,In data partitioning this field shows the position of the first macroblock in a slice" group.long 0xB0++0x03 line.long 0x00 "SKIP_RUN," hexmask.long.word 0x00 0.--15. 1. "SKIP_RUN_NB,SKIP_RUN_NB indicates the number of skipped macroblocks left in CAVLC" group.long 0xB0++0x07 line.long 0x00 "VLC_HUFFPTR_DC,Pointers to Huffman table for VLC DC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_DC_CHROMA_31_29,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_31_29_0,VLCHUFFPTR_DC_CHROMA_31_29_1,VLCHUFFPTR_DC_CHROMA_31_29_2,VLCHUFFPTR_DC_CHROMA_31_29_3,VLCHUFFPTR_DC_CHROMA_31_29_4,VLCHUFFPTR_DC_CHROMA_31_29_5,VLCHUFFPTR_DC_CHROMA_31_29_6,VLCHUFFPTR_DC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_DC_CHROMA_28_19,Indicating start address of Huffman table for VLC DC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_DC_CHROMA_18_16,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_18_16_0,VLCHUFFPTR_DC_CHROMA_18_16_1,VLCHUFFPTR_DC_CHROMA_18_16_2,VLCHUFFPTR_DC_CHROMA_18_16_3,VLCHUFFPTR_DC_CHROMA_18_16_4,VLCHUFFPTR_DC_CHROMA_18_16_5,VLCHUFFPTR_DC_CHROMA_18_16_6,VLCHUFFPTR_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "VLCHUFFPTR_DC_LUMA_15_13,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_15_13_0,VLCHUFFPTR_DC_LUMA_15_13_1,VLCHUFFPTR_DC_LUMA_15_13_2,VLCHUFFPTR_DC_LUMA_15_13_3,VLCHUFFPTR_DC_LUMA_15_13_4,VLCHUFFPTR_DC_LUMA_15_13_5,VLCHUFFPTR_DC_LUMA_15_13_6,VLCHUFFPTR_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_DC_LUMA_12_3,Indicating start address of Huffman table for VLC DC-luma" newline rbitfld.long 0x00 0.--2. "VLCHUFFPTR_DC_LUMA_2_0,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_2_0_0,VLCHUFFPTR_DC_LUMA_2_0_1,VLCHUFFPTR_DC_LUMA_2_0_2,VLCHUFFPTR_DC_LUMA_2_0_3,VLCHUFFPTR_DC_LUMA_2_0_4,VLCHUFFPTR_DC_LUMA_2_0_5,VLCHUFFPTR_DC_LUMA_2_0_6,VLCHUFFPTR_DC_LUMA_2_0_7" line.long 0x04 "CABAC_REG," bitfld.long 0x04 29. "PRE_SKIP,PRE_SKIP = 1 indicates that both top and bottom macroblocks in MB-AFF mode decoding are skipped" "0,1" newline bitfld.long 0x04 28. "FIRST_BIT,FIRST_BIT = 1 indicates that the next bit put by CABAC is the first bit since the last CABAC initialization" "0,1" newline hexmask.long.word 0x04 16.--25. 1. "C_LOW_OFST,C_LOW_OFST is equal to codILow in encoding and codIOffset in decoding" newline hexmask.long.word 0x04 0.--8. 1. "C_RNG,C_RNG is equal to codIRange" group.long 0xB4++0x03 line.long 0x00 "CDC_VP_5," hexmask.long.word 0x00 3.--15. 1. "OVERFLAGPTR_15_3,OVERFLAGPTR I picture except simple/main I picture" group.long 0xB4++0x03 line.long 0x00 "MP2_WORK2,MP2 WORK2 register" hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED2,In decoding this value specifies dct_dc_pred[2] described in MPEG-2 standard section 7.2.1" group.long 0xB4++0x03 line.long 0x00 "MP4_WORK2,MP4 WORK2 register" hexmask.long.word 0x00 16.--29. 1. "SLICE_MBADDR,In data partition decoding this field shows the macroblock address of the first macroblock in the current slice" newline bitfld.long 0x00 0.--1. "GOB_MBROW,In the case h263_mode = 1 and decoding this field shows the vertical position of current macroblock in a slice or GOB" "0,1,2,3" group.long 0xB4++0x07 line.long 0x00 "VLC_HUFFPTR_AC,Pointers to Huffman table for VLC AC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_AC_CHROMA_31_29,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_31_29_0,VLCHUFFPTR_AC_CHROMA_31_29_1,VLCHUFFPTR_AC_CHROMA_31_29_2,VLCHUFFPTR_AC_CHROMA_31_29_3,VLCHUFFPTR_AC_CHROMA_31_29_4,VLCHUFFPTR_AC_CHROMA_31_29_5,VLCHUFFPTR_AC_CHROMA_31_29_6,VLCHUFFPTR_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_AC_CHROMA_28_19,Indicating start address of Huffman table for VLC AC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_AC_CHROMA_18_16,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_18_16_0,VLCHUFFPTR_AC_CHROMA_18_16_1,VLCHUFFPTR_AC_CHROMA_18_16_2,VLCHUFFPTR_AC_CHROMA_18_16_3,VLCHUFFPTR_AC_CHROMA_18_16_4,VLCHUFFPTR_AC_CHROMA_18_16_5,VLCHUFFPTR_AC_CHROMA_18_16_6,VLCHUFFPTR_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "VLCHUFFPTR_AC_LUMA_15_13,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_15_13_0,VLCHUFFPTR_AC_LUMA_15_13_1,VLCHUFFPTR_AC_LUMA_15_13_2,VLCHUFFPTR_AC_LUMA_15_13_3,VLCHUFFPTR_AC_LUMA_15_13_4,VLCHUFFPTR_AC_LUMA_15_13_5,VLCHUFFPTR_AC_LUMA_15_13_6,VLCHUFFPTR_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_AC_LUMA_12_3,Indicating start address of Huffman table for VLC AC-luma" newline rbitfld.long 0x00 0.--2. "VLCHUFFPTR_AC_LUMA_2_0,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_2_0_0,VLCHUFFPTR_AC_LUMA_2_0_1,VLCHUFFPTR_AC_LUMA_2_0_2,VLCHUFFPTR_AC_LUMA_2_0_3,VLCHUFFPTR_AC_LUMA_2_0_4,VLCHUFFPTR_AC_LUMA_2_0_5,VLCHUFFPTR_AC_LUMA_2_0_6,VLCHUFFPTR_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_6," hexmask.long.word 0x04 3.--15. 1. "MVMODEPTR_15_3,MVMODEPTR Progressive P picture" group.long 0xB8++0x03 line.long 0x00 "MP2_WORK3,MP2 WORK3 register" hexmask.long.word 0x00 16.--31. 1. "PMV1,Specifies PMV[0][0][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV0,Specifies PMV[0[0][0] described in MPEG-2 standard section 7.6.3. They are half-pel precision" group.long 0xB8++0x03 line.long 0x00 "MP4_WORK3," rbitfld.long 0x00 13.--14. "PTR_MVD_14_13,This field specifies temporary MVD data pointer" "0,1,2,3" newline hexmask.long.word 0x00 4.--12. 1. "PTR_MVD_12_4,This field specifies temporary MVD data pointer" newline rbitfld.long 0x00 0.--3. "PTR_MVD_3_0,This field specifies temporary MVD data pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x03 line.long 0x00 "SYM_CNT," group.long 0xB8++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_DC,Pointers to control table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_DC_CHROMA_31_29,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_31_29_0,UVLD_CTRL_DC_CHROMA_31_29_1,UVLD_CTRL_DC_CHROMA_31_29_2,UVLD_CTRL_DC_CHROMA_31_29_3,UVLD_CTRL_DC_CHROMA_31_29_4,UVLD_CTRL_DC_CHROMA_31_29_5,UVLD_CTRL_DC_CHROMA_31_29_6,UVLD_CTRL_DC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_DC_CHROMA_28_19,Indicating start address of control table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_DC_CHROMA_18_16,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_18_16_0,UVLD_CTRL_DC_CHROMA_18_16_1,UVLD_CTRL_DC_CHROMA_18_16_2,UVLD_CTRL_DC_CHROMA_18_16_3,UVLD_CTRL_DC_CHROMA_18_16_4,UVLD_CTRL_DC_CHROMA_18_16_5,UVLD_CTRL_DC_CHROMA_18_16_6,UVLD_CTRL_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CTRL_DC_LUMA_15_13,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_15_13_0,UVLD_CTRL_DC_LUMA_15_13_1,UVLD_CTRL_DC_LUMA_15_13_2,UVLD_CTRL_DC_LUMA_15_13_3,UVLD_CTRL_DC_LUMA_15_13_4,UVLD_CTRL_DC_LUMA_15_13_5,UVLD_CTRL_DC_LUMA_15_13_6,UVLD_CTRL_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_DC_LUMA_12_3,Indicating start address of control table for UVLD DC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CTRL_DC_LUMA_2_0,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_2_0_0,UVLD_CTRL_DC_LUMA_2_0_1,UVLD_CTRL_DC_LUMA_2_0_2,UVLD_CTRL_DC_LUMA_2_0_3,UVLD_CTRL_DC_LUMA_2_0_4,UVLD_CTRL_DC_LUMA_2_0_5,UVLD_CTRL_DC_LUMA_2_0_6,UVLD_CTRL_DC_LUMA_2_0_7" line.long 0x04 "BITS_OSTD," group.long 0xBC++0x03 line.long 0x00 "CDC_VP_7," hexmask.long.word 0x00 3.--15. 1. "SKIPMBPTR_15_3,SKIPMBPTR Progressive P/B picture Interlace Frame P/B picture" group.long 0xBC++0x03 line.long 0x00 "MP2_WORK4,MP2 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "PMV4,Specifies PMV[0][1][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV3,Specifies PMV[0][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xBC++0x03 line.long 0x00 "MP4_WORK4,MP4 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "MVP01,MVP[0][1]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP00,MVP[0][0]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" group.long 0xBC++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_AC,Pointers to control table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_AC_CHROMA_31_29,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_31_29_0,UVLD_CTRL_AC_CHROMA_31_29_1,UVLD_CTRL_AC_CHROMA_31_29_2,UVLD_CTRL_AC_CHROMA_31_29_3,UVLD_CTRL_AC_CHROMA_31_29_4,UVLD_CTRL_AC_CHROMA_31_29_5,UVLD_CTRL_AC_CHROMA_31_29_6,UVLD_CTRL_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_AC_CHROMA_28_19,Indicating start address of control table for UVLD AC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_AC_CHROMA_18_16,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_18_16_0,UVLD_CTRL_AC_CHROMA_18_16_1,UVLD_CTRL_AC_CHROMA_18_16_2,UVLD_CTRL_AC_CHROMA_18_16_3,UVLD_CTRL_AC_CHROMA_18_16_4,UVLD_CTRL_AC_CHROMA_18_16_5,UVLD_CTRL_AC_CHROMA_18_16_6,UVLD_CTRL_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CTRL_AC_LUMA_15_13,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_15_13_0,UVLD_CTRL_AC_LUMA_15_13_1,UVLD_CTRL_AC_LUMA_15_13_2,UVLD_CTRL_AC_LUMA_15_13_3,UVLD_CTRL_AC_LUMA_15_13_4,UVLD_CTRL_AC_LUMA_15_13_5,UVLD_CTRL_AC_LUMA_15_13_6,UVLD_CTRL_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_AC_LUMA_12_3,Indicating start address of control table for UVLD AC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CTRL_AC_LUMA_2_0,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_2_0_0,UVLD_CTRL_AC_LUMA_2_0_1,UVLD_CTRL_AC_LUMA_2_0_2,UVLD_CTRL_AC_LUMA_2_0_3,UVLD_CTRL_AC_LUMA_2_0_4,UVLD_CTRL_AC_LUMA_2_0_5,UVLD_CTRL_AC_LUMA_2_0_6,UVLD_CTRL_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_8," hexmask.long.word 0x04 3.--15. 1. "DIRECTPT_15_3,DIRECTPTR Progressive B picture Interlace Frame B picture" group.long 0xC0++0x03 line.long 0x00 "MP2_WORK5,MP2 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "PMV6,Specifies PMV[1][0][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV5,Specifies PMV[1][0][0] described in MPEG-2 standard section 7.6.3" group.long 0xC0++0x03 line.long 0x00 "MP4_WORK5,MP4 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "MVP11,MVP[1][1]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP10,MVP[1][0]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" group.long 0xC0++0x03 line.long 0x00 "MVD_CUR_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_CUR_1_15_13,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 19.--28. 1. "DP_MVD_CUR_1_12_3,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_CUR_1_2_0,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 13.--15. "DP_MVD_CUR_0_15_13,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_CUR_0_12_3,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" newline rbitfld.long 0x00 0.--2. "DP_MVD_CUR_0_2_0,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC0++0x07 line.long 0x00 "UVLD_CODE_TBPTR_DC,Pointers to code table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_DC_CHROMA31_29,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA31_29_0,UVLD_CODE_DC_CHROMA31_29_1,UVLD_CODE_DC_CHROMA31_29_2,UVLD_CODE_DC_CHROMA31_29_3,UVLD_CODE_DC_CHROMA31_29_4,UVLD_CODE_DC_CHROMA31_29_5,UVLD_CODE_DC_CHROMA31_29_6,UVLD_CODE_DC_CHROMA31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_DC_CHROMA_28_19,Indicating start address of code table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_DC_CHROMA_18_16,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA_18_16_0,UVLD_CODE_DC_CHROMA_18_16_1,UVLD_CODE_DC_CHROMA_18_16_2,UVLD_CODE_DC_CHROMA_18_16_3,UVLD_CODE_DC_CHROMA_18_16_4,UVLD_CODE_DC_CHROMA_18_16_5,UVLD_CODE_DC_CHROMA_18_16_6,UVLD_CODE_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CODE_DC_LUMA_15_13,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_15_13_0,UVLD_CODE_DC_LUMA_15_13_1,UVLD_CODE_DC_LUMA_15_13_2,UVLD_CODE_DC_LUMA_15_13_3,UVLD_CODE_DC_LUMA_15_13_4,UVLD_CODE_DC_LUMA_15_13_5,UVLD_CODE_DC_LUMA_15_13_6,UVLD_CODE_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_DC_LUMA_12_3,Indicating start address of code table for UVLD DC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CODE_DC_LUMA_2_0,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_2_0_0,UVLD_CODE_DC_LUMA_2_0_1,UVLD_CODE_DC_LUMA_2_0_2,UVLD_CODE_DC_LUMA_2_0_3,UVLD_CODE_DC_LUMA_2_0_4,UVLD_CODE_DC_LUMA_2_0_5,UVLD_CODE_DC_LUMA_2_0_6,UVLD_CODE_DC_LUMA_2_0_7" line.long 0x04 "CDC_VP_9," hexmask.long.word 0x04 3.--15. 1. "FIELDTXPTR_31_3,FIELDTXPTR Interlace Frame I picture" group.long 0xC4++0x03 line.long 0x00 "MP2_WORK6,MP2 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "PMV8,Specifies PMV[1][1][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV7,Specifies PMV[1][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xC4++0x03 line.long 0x00 "MP4_WORK6,MP4 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "MVP21,MVP[2][1]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP20,MVP[2][0]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" group.long 0xC4++0x03 line.long 0x00 "MVD_LFT_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_LFT_1_15_13,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 19.--28. 1. "DP_MVD_LFT_1_12_3,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_LFT_1_2_0,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 13.--15. "DP_MVD_LFT_0_15_13,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_LFT_0_12_3,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" newline rbitfld.long 0x00 0.--2. "DP_MVD_LFT_0_2_0,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC4++0x07 line.long 0x00 "UVLD_CODE_TBPTR_AC,Pointers to code table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_AC_CHROMA_31_29,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_31_29_0,UVLD_CODE_AC_CHROMA_31_29_1,UVLD_CODE_AC_CHROMA_31_29_2,UVLD_CODE_AC_CHROMA_31_29_3,UVLD_CODE_AC_CHROMA_31_29_4,UVLD_CODE_AC_CHROMA_31_29_5,UVLD_CODE_AC_CHROMA_31_29_6,UVLD_CODE_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_AC_CHROMA_28_19,Indicating start address of code table for UVLD AC Chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_AC_CHROMA_18_16,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_18_16_0,UVLD_CODE_AC_CHROMA_18_16_1,UVLD_CODE_AC_CHROMA_18_16_2,UVLD_CODE_AC_CHROMA_18_16_3,UVLD_CODE_AC_CHROMA_18_16_4,UVLD_CODE_AC_CHROMA_18_16_5,UVLD_CODE_AC_CHROMA_18_16_6,UVLD_CODE_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CODE_AC_LUMA_15_13,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_15_13_0,UVLD_CODE_AC_LUMA_15_13_1,UVLD_CODE_AC_LUMA_15_13_2,UVLD_CODE_AC_LUMA_15_13_3,UVLD_CODE_AC_LUMA_15_13_4,UVLD_CODE_AC_LUMA_15_13_5,UVLD_CODE_AC_LUMA_15_13_6,UVLD_CODE_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_AC_LUMA_12_3,Indicating start address of code table for UVLD AC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CODE_AC_LUMA_2_0,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_2_0_0,UVLD_CODE_AC_LUMA_2_0_1,UVLD_CODE_AC_LUMA_2_0_2,UVLD_CODE_AC_LUMA_2_0_3,UVLD_CODE_AC_LUMA_2_0_4,UVLD_CODE_AC_LUMA_2_0_5,UVLD_CODE_AC_LUMA_2_0_6,UVLD_CODE_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_A," hexmask.long.word 0x04 3.--15. 1. "FWDBITPTR_15_3,FWDBITPTR Interlace Field B picture" group.long 0xC8++0x03 line.long 0x00 "MP4_WORK7,MP4 WORK7 register" hexmask.long.word 0x00 16.--31. 1. "MVP31,MVP[3][1]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP30,MVP[3][0]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" group.long 0xC8++0x07 line.long 0x00 "UVLD_TBL_TYPE,Setting for UVLD code table" bitfld.long 0x00 29. "UVLD_AC_CHROMA,Indicating type of UVLD code table for AC-chroma data" "zero-leading,one-leading" newline bitfld.long 0x00 24.--28. "UVLD_AC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-chroma" "UVLD_AC_CHROMA_LEN_MAX_0,UVLD_AC_CHROMA_LEN_MAX_1,UVLD_AC_CHROMA_LEN_MAX_2,UVLD_AC_CHROMA_LEN_MAX_3,UVLD_AC_CHROMA_LEN_MAX_4,UVLD_AC_CHROMA_LEN_MAX_5,UVLD_AC_CHROMA_LEN_MAX_6,UVLD_AC_CHROMA_LEN_MAX_7,UVLD_AC_CHROMA_LEN_MAX_8,UVLD_AC_CHROMA_LEN_MAX_9,UVLD_AC_CHROMA_LEN_MAX_10,UVLD_AC_CHROMA_LEN_MAX_11,UVLD_AC_CHROMA_LEN_MAX_12,UVLD_AC_CHROMA_LEN_MAX_13,UVLD_AC_CHROMA_LEN_MAX_14,UVLD_AC_CHROMA_LEN_MAX_15,UVLD_AC_CHROMA_LEN_MAX_16,UVLD_AC_CHROMA_LEN_MAX_17,UVLD_AC_CHROMA_LEN_MAX_18,UVLD_AC_CHROMA_LEN_MAX_19,UVLD_AC_CHROMA_LEN_MAX_20,UVLD_AC_CHROMA_LEN_MAX_21,UVLD_AC_CHROMA_LEN_MAX_22,UVLD_AC_CHROMA_LEN_MAX_23,UVLD_AC_CHROMA_LEN_MAX_24,UVLD_AC_CHROMA_LEN_MAX_25,UVLD_AC_CHROMA_LEN_MAX_26,UVLD_AC_CHROMA_LEN_MAX_27,UVLD_AC_CHROMA_LEN_MAX_28,UVLD_AC_CHROMA_LEN_MAX_29,UVLD_AC_CHROMA_LEN_MAX_30,UVLD_AC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 21. "UVLD_AC_LUMA,Indicating type of UVLD code table for AC-luma data" "zero-leading,one-leading" newline bitfld.long 0x00 16.--20. "UVLD_AC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-luma" "UVLD_AC_LUMA_LEN_MAX_0,UVLD_AC_LUMA_LEN_MAX_1,UVLD_AC_LUMA_LEN_MAX_2,UVLD_AC_LUMA_LEN_MAX_3,UVLD_AC_LUMA_LEN_MAX_4,UVLD_AC_LUMA_LEN_MAX_5,UVLD_AC_LUMA_LEN_MAX_6,UVLD_AC_LUMA_LEN_MAX_7,UVLD_AC_LUMA_LEN_MAX_8,UVLD_AC_LUMA_LEN_MAX_9,UVLD_AC_LUMA_LEN_MAX_10,UVLD_AC_LUMA_LEN_MAX_11,UVLD_AC_LUMA_LEN_MAX_12,UVLD_AC_LUMA_LEN_MAX_13,UVLD_AC_LUMA_LEN_MAX_14,UVLD_AC_LUMA_LEN_MAX_15,UVLD_AC_LUMA_LEN_MAX_16,UVLD_AC_LUMA_LEN_MAX_17,UVLD_AC_LUMA_LEN_MAX_18,UVLD_AC_LUMA_LEN_MAX_19,UVLD_AC_LUMA_LEN_MAX_20,UVLD_AC_LUMA_LEN_MAX_21,UVLD_AC_LUMA_LEN_MAX_22,UVLD_AC_LUMA_LEN_MAX_23,UVLD_AC_LUMA_LEN_MAX_24,UVLD_AC_LUMA_LEN_MAX_25,UVLD_AC_LUMA_LEN_MAX_26,UVLD_AC_LUMA_LEN_MAX_27,UVLD_AC_LUMA_LEN_MAX_28,UVLD_AC_LUMA_LEN_MAX_29,UVLD_AC_LUMA_LEN_MAX_30,UVLD_AC_LUMA_LEN_MAX_31" newline bitfld.long 0x00 13. "UVLD_DC_CHROMA,Indicating type of UVLD code table for DC-chroma data" "zero-leading,one-leading" newline bitfld.long 0x00 8.--12. "UVLD_DC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-chroma" "UVLD_DC_CHROMA_LEN_MAX_0,UVLD_DC_CHROMA_LEN_MAX_1,UVLD_DC_CHROMA_LEN_MAX_2,UVLD_DC_CHROMA_LEN_MAX_3,UVLD_DC_CHROMA_LEN_MAX_4,UVLD_DC_CHROMA_LEN_MAX_5,UVLD_DC_CHROMA_LEN_MAX_6,UVLD_DC_CHROMA_LEN_MAX_7,UVLD_DC_CHROMA_LEN_MAX_8,UVLD_DC_CHROMA_LEN_MAX_9,UVLD_DC_CHROMA_LEN_MAX_10,UVLD_DC_CHROMA_LEN_MAX_11,UVLD_DC_CHROMA_LEN_MAX_12,UVLD_DC_CHROMA_LEN_MAX_13,UVLD_DC_CHROMA_LEN_MAX_14,UVLD_DC_CHROMA_LEN_MAX_15,UVLD_DC_CHROMA_LEN_MAX_16,UVLD_DC_CHROMA_LEN_MAX_17,UVLD_DC_CHROMA_LEN_MAX_18,UVLD_DC_CHROMA_LEN_MAX_19,UVLD_DC_CHROMA_LEN_MAX_20,UVLD_DC_CHROMA_LEN_MAX_21,UVLD_DC_CHROMA_LEN_MAX_22,UVLD_DC_CHROMA_LEN_MAX_23,UVLD_DC_CHROMA_LEN_MAX_24,UVLD_DC_CHROMA_LEN_MAX_25,UVLD_DC_CHROMA_LEN_MAX_26,UVLD_DC_CHROMA_LEN_MAX_27,UVLD_DC_CHROMA_LEN_MAX_28,UVLD_DC_CHROMA_LEN_MAX_29,UVLD_DC_CHROMA_LEN_MAX_30,UVLD_DC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 5. "UVLD_DC_LUMA,Indicating type of UVLD code table for DC-luma data" "zero-leading,one-leading" newline bitfld.long 0x00 0.--4. "UVLD_DC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-luma" "UVLD_DC_LUMA_LEN_MAX_0,UVLD_DC_LUMA_LEN_MAX_1,UVLD_DC_LUMA_LEN_MAX_2,UVLD_DC_LUMA_LEN_MAX_3,UVLD_DC_LUMA_LEN_MAX_4,UVLD_DC_LUMA_LEN_MAX_5,UVLD_DC_LUMA_LEN_MAX_6,UVLD_DC_LUMA_LEN_MAX_7,UVLD_DC_LUMA_LEN_MAX_8,UVLD_DC_LUMA_LEN_MAX_9,UVLD_DC_LUMA_LEN_MAX_10,UVLD_DC_LUMA_LEN_MAX_11,UVLD_DC_LUMA_LEN_MAX_12,UVLD_DC_LUMA_LEN_MAX_13,UVLD_DC_LUMA_LEN_MAX_14,UVLD_DC_LUMA_LEN_MAX_15,UVLD_DC_LUMA_LEN_MAX_16,UVLD_DC_LUMA_LEN_MAX_17,UVLD_DC_LUMA_LEN_MAX_18,UVLD_DC_LUMA_LEN_MAX_19,UVLD_DC_LUMA_LEN_MAX_20,UVLD_DC_LUMA_LEN_MAX_21,UVLD_DC_LUMA_LEN_MAX_22,UVLD_DC_LUMA_LEN_MAX_23,UVLD_DC_LUMA_LEN_MAX_24,UVLD_DC_LUMA_LEN_MAX_25,UVLD_DC_LUMA_LEN_MAX_26,UVLD_DC_LUMA_LEN_MAX_27,UVLD_DC_LUMA_LEN_MAX_28,UVLD_DC_LUMA_LEN_MAX_29,UVLD_DC_LUMA_LEN_MAX_30,UVLD_DC_LUMA_LEN_MAX_31" line.long 0x04 "DC_PRED_CHROMA,JPEG DC PRED Chroma register - TI internal" hexmask.long.word 0x04 16.--31. 1. "DC_PRED_CB,Chrominance (Cb) DC prediction value is stored in register" newline hexmask.long.word 0x04 0.--15. 1. "DC_PRED_CR,Chrominance (Cr) DC prediction value is stored in register" repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0xF0)++0x03 line.long 0x00 "CMDP_GPR$1,Command Processor General Purpose Register 0" repeat.end width 0x0B tree.end endif tree "ECD3_MMR_L3_MAINInterconnect" base ad:0x5A059800 rgroup.long 0x00++0x33 line.long 0x00 "ECD_PID,Product Identification" line.long 0x04 "ECD_COUNT,Cycle Counter" bitfld.long 0x04 31. "CNT_EN," "Disable the cycle counter,Enable the cycle counter" newline bitfld.long 0x04 30. "CNT_RST,Resets the cycle counter COUNT value to 0" "No effect,Clears COUNT" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Displays the current counter value" line.long 0x08 "ECD_CTRL,Control" rbitfld.long 0x08 20.--23. "CDM_ADD_15_12,Specifies the starting byte address [15:12] of command sequence stored in ECDABUF" "CDM_ADD_15_12_0,CDM_ADD_15_12_1,CDM_ADD_15_12_2,CDM_ADD_15_12_3,CDM_ADD_15_12_4,CDM_ADD_15_12_5,CDM_ADD_15_12_6,CDM_ADD_15_12_7,CDM_ADD_15_12_8,CDM_ADD_15_12_9,CDM_ADD_15_12_10,CDM_ADD_15_12_11,CDM_ADD_15_12_12,CDM_ADD_15_12_13,CDM_ADD_15_12_14,CDM_ADD_15_12_15" newline hexmask.long.byte 0x08 12.--19. 1. "CDM_ADD_11_4,Specifies the starting byte address [11:4] of command sequence stored in ECDABUF" newline rbitfld.long 0x08 8.--11. "CDM_ADD_3_0,Specifies the starting byte address [3:0] of command sequence stored in ECDABUF" "CDM_ADD_3_0_0,CDM_ADD_3_0_1,CDM_ADD_3_0_2,CDM_ADD_3_0_3,CDM_ADD_3_0_4,CDM_ADD_3_0_5,CDM_ADD_3_0_6,CDM_ADD_3_0_7,CDM_ADD_3_0_8,CDM_ADD_3_0_9,CDM_ADD_3_0_10,CDM_ADD_3_0_11,CDM_ADD_3_0_12,CDM_ADD_3_0_13,CDM_ADD_3_0_14,CDM_ADD_3_0_15" newline bitfld.long 0x08 2. "SSM," "SSM_0,SSM_1" newline bitfld.long 0x08 1. "CSB," "Indicates that the last command processing ended..,Indicates that ECD3 found an undefined op-code.." newline bitfld.long 0x08 0. "EN," "EN_0,EN_1" line.long 0x0C "ECD_STAT,ECD Status" bitfld.long 0x0C 30. "EOS_ACK_DIS," "Indicates that ECD3 waits for an acknowledge..,Indicates that the EOS interrupt handshake.." newline bitfld.long 0x0C 29. "ERR_ACK_DIS," "Indicates that ECD3 waits for an acknowledge..,Indicates that the ERR interrupt handshake.." newline bitfld.long 0x0C 2. "EOS," "Force to exit busy state while waiting for an..,Indicates that the last macroblock is at the end.." newline bitfld.long 0x0C 1. "ERR," "Force to exit busy state while waiting for an..,Indicates an error was found in the stream while.." newline rbitfld.long 0x0C 0. "BUSY," "BUSY_0,BUSY_1" line.long 0x10 "SBC_CTRL,Stream Buffer Controller Control" bitfld.long 0x10 31. "SBC_RST,Resets the Stream Buffer Controller" "No effect,Resets all registers of.." newline bitfld.long 0x10 16. "SBC_CLOSE,Close the bitstream data" "No effect,Brings it back to idle.." newline bitfld.long 0x10 12. "SBC_DMA_TRG_B,Start DMA to fill empty page in the Buffer B manually" "SBC_DMA_TRG_B_0,SBC_DMA_TRG_B_1" newline bitfld.long 0x10 8. "SBC_DMA_TRG_A,Start DMA to fill empty page in the Buffer A manually" "SBC_DMA_TRG_A_0,SBC_DMA_TRG_A_1" newline bitfld.long 0x10 4. "SBC_BIT_CNT_RST,Reset bit counter in the Stream Buffer" "SBC_BIT_CNT_RST_0,SBC_BIT_CNT_RST_1" newline bitfld.long 0x10 0. "SBC_BUFSEL,Selects active buffer between A and B: Write" "Buffer A is selected,Buffer B is selected This bit is ignored if.." line.long 0x14 "SBC_STAT,Stream Buffer Controller Status" rbitfld.long 0x14 6. "SBC_ST_SRCH," "SBC_ST_SRCH_0,SBC_ST_SRCH_1" newline bitfld.long 0x14 5. "SBC_DMA_B," "Force to exit busy state while waiting for an..,Indicates that the Stream Buffer Controller is.." newline bitfld.long 0x14 4. "SBC_DMA_A," "Force to exit busy state while waiting for an..,Indicates that the Stream Buffer Controller is.." newline rbitfld.long 0x14 3. "SBC_WR_HLT," "SBC_WR_HLT_0,SBC_WR_HLT_1" newline rbitfld.long 0x14 2. "SBC_RD_HLT," "SBC_RD_HLT_0,SBC_RD_HLT_1" newline rbitfld.long 0x14 1. "SBC_WR," "SBC_WR_0,SBC_WR_1" newline rbitfld.long 0x14 0. "SBC_RD," "SBC_RD_0,SBC_RD_1" line.long 0x18 "SBC_BUFCFG,Stream Buffer Controller Buffer Configuration" bitfld.long 0x18 31. "SBC_FLUSH_MODE,SBC FIFO flush mode select for encoding" "Flush FIFO when EOS flag is sent by Codec Engine,Flush FIFO when DONE or EOS flag is sent by.." newline bitfld.long 0x18 30. "SBC_FMO_MODE,SBC FIFO flush mode select for encoding" "Buffer A and B pointers are used for Stream Data..,Buffer A pointer and SBC_A_BITPTR[30:28].." newline bitfld.long 0x18 24. "SBC_DBL,Enables double buffer mode" "disabled (buffer A only mode),enabled (buffer A and buffer B)" newline bitfld.long 0x18 20.--21. "SBC_PGSZ,Specifies the page size of buffer A and B in the unit of 1024 [byte]" "SBC_PGSZ_0,SBC_PGSZ_1,SBC_PGSZ_2,SBC_PGSZ_3" newline hexmask.long.word 0x18 4.--17. 1. "SBC_BUFTOP_17_4,Specifies the base address [17:4] of the bitstream buffer in SL2" newline rbitfld.long 0x18 0.--3. "SBC_BUFTOP_3_0,Specifies the base address [3:0] of the bitstream buffer in SL2" "SBC_BUFTOP_3_0_0,SBC_BUFTOP_3_0_1,SBC_BUFTOP_3_0_2,SBC_BUFTOP_3_0_3,SBC_BUFTOP_3_0_4,SBC_BUFTOP_3_0_5,SBC_BUFTOP_3_0_6,SBC_BUFTOP_3_0_7,SBC_BUFTOP_3_0_8,SBC_BUFTOP_3_0_9,SBC_BUFTOP_3_0_10,SBC_BUFTOP_3_0_11,SBC_BUFTOP_3_0_12,SBC_BUFTOP_3_0_13,SBC_BUFTOP_3_0_14,SBC_BUFTOP_3_0_15" line.long 0x1C "SBC_A_BITPTR,Stream Buffer Controller A Bit Pointer" bitfld.long 0x1C 28.--30. "FMO_DMA_ID,Indicates the ID number of bitstream data in SL2 memory" "FMO_DMA_ID_0,FMO_DMA_ID_1,FMO_DMA_ID_2,FMO_DMA_ID_3,FMO_DMA_ID_4,FMO_DMA_ID_5,FMO_DMA_ID_6,FMO_DMA_ID_7" newline bitfld.long 0x1C 24.--25. "NUM_ZERO_A,Indicates the number of 0 bytes in the past for buffer A" "NUM_ZERO_A_0,NUM_ZERO_A_1,NUM_ZERO_A_2,NUM_ZERO_A_3" newline hexmask.long.word 0x1C 8.--21. 1. "BYTEPTR_A,Indicates the current byte offset address in Buffer A of the byte containing the next bit in the bitstream" newline bitfld.long 0x1C 0.--2. "BITPTR_A,Indicates the next bit position in the byte at BYTEPTR_A" "BITPTR_A_0,BITPTR_A_1,BITPTR_A_2,BITPTR_A_3,BITPTR_A_4,BITPTR_A_5,BITPTR_A_6,BITPTR_A_7" line.long 0x20 "SBC_A_DMAPG,Stream Buffer Controller A DMA Page" hexmask.long.byte 0x20 0.--7. 1. "DMAPG_A,Indicates the page that is being accessed from DMA for bitstream data transferring" line.long 0x24 "SBC_B_BITPTR,Stream Buffer Controller B Bit Pointer" bitfld.long 0x24 24.--25. "NUM_ZERO_B,Indicates the number of 0 bytes in the past for buffer B" "NUM_ZERO_B_0,NUM_ZERO_B_1,NUM_ZERO_B_2,NUM_ZERO_B_3" newline hexmask.long.word 0x24 8.--21. 1. "BYTEPTR_B,Indicates the current byte offset address in Buffer B of the byte containing the next bit in the bitstream" newline bitfld.long 0x24 0.--2. "BITPTR_B,Indicates the next bit position in the byte at BYTEPTR_B" "BITPTR_B_0,BITPTR_B_1,BITPTR_B_2,BITPTR_B_3,BITPTR_B_4,BITPTR_B_5,BITPTR_B_6,BITPTR_B_7" line.long 0x28 "SBC_B_DMAPG,Stream Buffer Controller B DMA Page" bitfld.long 0x28 0. "DMAPG_B,Indicates the page that is being accessed from DMA for bitstream data transferring" "DMAPG_B_0,DMAPG_B_1" line.long 0x2C "SBC_TTLCNT,Stream Buffer Controller Total Bit Counter" line.long 0x30 "SBC_RSDCNT,Stream Buffer Controller Residual Layer Bit Counter" group.long 0x38++0x0B line.long 0x00 "SBC_SRCH_PG_CNT,Buffer page counter for start code searching" hexmask.long.word 0x00 0.--15. 1. "SRCH_PG_CNT,ECD3 search start code until the page counter reach this number" line.long 0x04 "SBC_FMO_DMA_STAT,FMO_DMA status register" hexmask.long.byte 0x04 0.--7. 1. "FMO_DMA,Indicates FMO_DMA_ID for stream interrupt at buffer page boundary" line.long 0x08 "MBPC_PIC_DIM,Picture Dimension" bitfld.long 0x08 31. "CUR_MBAFF,CUR_MBAFF = 1 indicates that current picture is in H.264 MBAFF mode" "CUR_MBAFF_0,CUR_MBAFF_1" newline hexmask.long.word 0x08 16.--29. 1. "PIC_H,PIC_H specifies the picture height in macroblocks which is calculated by PIC_H = ((picture height in pixels) + 15)/16" newline hexmask.long.word 0x08 0.--13. 1. "PIC_W,PIC_W specifies the picture width in macroblocks which is calculated by PIC_W = ((picture width in pixels) + 15)/16" group.long 0x50++0x0F line.long 0x00 "MBPC_STAT,MB Position Controller Status" bitfld.long 0x00 9. "PIC_END_FLAG,PIC_END_FLAG = 1 indicates that the macroblock will be processed is at the end of the picture" "PIC_END_FLAG_0,PIC_END_FLAG_1" newline bitfld.long 0x00 8. "FIRST_MB_FLAG,FIRST_MB_FLAG = 1 indicates that the macroblock will be processed is the first macroblock in the slice" "FIRST_MB_FLAG_0,FIRST_MB_FLAG_1" newline bitfld.long 0x00 4.--7. "PIC_BOUND,PIC_BOUND indicates that the picture boundary status of the current macroblock (in case of MBAFF mode the unit is macroblock-pair)" "PIC_BOUND_0,PIC_BOUND_1,PIC_BOUND_2,PIC_BOUND_3,PIC_BOUND_4,PIC_BOUND_5,PIC_BOUND_6,PIC_BOUND_7,PIC_BOUND_8,PIC_BOUND_9,PIC_BOUND_10,PIC_BOUND_11,PIC_BOUND_12,PIC_BOUND_13,PIC_BOUND_14,PIC_BOUND_15" newline bitfld.long 0x00 0.--3. "MB_AVAIL,MB_AVAIL indicates that the availabilities of neighboring macroblocks (in case of MBAFF mode the unit is macroblock-pair)" "MB_AVAIL_0,MB_AVAIL_1,MB_AVAIL_2,MB_AVAIL_3,MB_AVAIL_4,MB_AVAIL_5,MB_AVAIL_6,MB_AVAIL_7,MB_AVAIL_8,MB_AVAIL_9,MB_AVAIL_10,MB_AVAIL_11,MB_AVAIL_12,MB_AVAIL_13,MB_AVAIL_14,MB_AVAIL_15" line.long 0x04 "MBPC_POS,Macroblock Position" hexmask.long.word 0x04 16.--28. 1. "MB_Y,MB_Y equals the macroblock y-position in the picture" newline hexmask.long.word 0x04 0.--12. 1. "MB_X,MB_X equals the macroblock x-position in the picture" line.long 0x08 "MBPC_PMC,Macroblock Count In Picture" hexmask.long 0x08 0.--25. 1. "PIC_MB_CNT,PIC_MB_CNT equals the macroblock count in the picture" line.long 0x0C "MBPC_SMC,Macroblock Count In Slice" hexmask.long 0x0C 0.--25. 1. "SLC_MB_CNT,SLC_MB_CNT equals the macroblock count in the slice" group.long 0x64++0x17 line.long 0x00 "DTBC_BP_MB,Data Buffer Controller MB Base Buffer Pointer" rbitfld.long 0x00 28.--31. "BP_MB_UR_15_12,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_15_12_0,BP_MB_UR_15_12_1,BP_MB_UR_15_12_2,BP_MB_UR_15_12_3,BP_MB_UR_15_12_4,BP_MB_UR_15_12_5,BP_MB_UR_15_12_6,BP_MB_UR_15_12_7,BP_MB_UR_15_12_8,BP_MB_UR_15_12_9,BP_MB_UR_15_12_10,BP_MB_UR_15_12_11,BP_MB_UR_15_12_12,BP_MB_UR_15_12_13,BP_MB_UR_15_12_14,BP_MB_UR_15_12_15" newline hexmask.long.byte 0x00 20.--27. 1. "BP_MB_UR_11_4,BP_MB_UR specifies the base pointer to the upper macroblock buffer" newline rbitfld.long 0x00 16.--19. "BP_MB_UR_3_0,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_3_0_0,BP_MB_UR_3_0_1,BP_MB_UR_3_0_2,BP_MB_UR_3_0_3,BP_MB_UR_3_0_4,BP_MB_UR_3_0_5,BP_MB_UR_3_0_6,BP_MB_UR_3_0_7,BP_MB_UR_3_0_8,BP_MB_UR_3_0_9,BP_MB_UR_3_0_10,BP_MB_UR_3_0_11,BP_MB_UR_3_0_12,BP_MB_UR_3_0_13,BP_MB_UR_3_0_14,BP_MB_UR_3_0_15" newline rbitfld.long 0x00 12.--15. "BP_MB_CUR_15_12,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_15_12_0,BP_MB_CUR_15_12_1,BP_MB_CUR_15_12_2,BP_MB_CUR_15_12_3,BP_MB_CUR_15_12_4,BP_MB_CUR_15_12_5,BP_MB_CUR_15_12_6,BP_MB_CUR_15_12_7,BP_MB_CUR_15_12_8,BP_MB_CUR_15_12_9,BP_MB_CUR_15_12_10,BP_MB_CUR_15_12_11,BP_MB_CUR_15_12_12,BP_MB_CUR_15_12_13,BP_MB_CUR_15_12_14,BP_MB_CUR_15_12_15" newline hexmask.long.byte 0x00 4.--11. 1. "BP_MB_CUR_11_4,BP_MB_CUR specifies the base pointer to the current macroblock buffer" newline rbitfld.long 0x00 0.--3. "BP_MB_CUR_3_0,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_3_0_0,BP_MB_CUR_3_0_1,BP_MB_CUR_3_0_2,BP_MB_CUR_3_0_3,BP_MB_CUR_3_0_4,BP_MB_CUR_3_0_5,BP_MB_CUR_3_0_6,BP_MB_CUR_3_0_7,BP_MB_CUR_3_0_8,BP_MB_CUR_3_0_9,BP_MB_CUR_3_0_10,BP_MB_CUR_3_0_11,BP_MB_CUR_3_0_12,BP_MB_CUR_3_0_13,BP_MB_CUR_3_0_14,BP_MB_CUR_3_0_15" line.long 0x04 "DTBC_BP_COL,Data Buffer Controller Co-located MB Buffer Base Pointer" rbitfld.long 0x04 28.--31. "BP_COL_B_15_12,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_15_12_0,BP_COL_B_15_12_1,BP_COL_B_15_12_2,BP_COL_B_15_12_3,BP_COL_B_15_12_4,BP_COL_B_15_12_5,BP_COL_B_15_12_6,BP_COL_B_15_12_7,BP_COL_B_15_12_8,BP_COL_B_15_12_9,BP_COL_B_15_12_10,BP_COL_B_15_12_11,BP_COL_B_15_12_12,BP_COL_B_15_12_13,BP_COL_B_15_12_14,BP_COL_B_15_12_15" newline hexmask.long.byte 0x04 20.--27. 1. "BP_COL_B_11_4,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" newline rbitfld.long 0x04 16.--19. "BP_COL_B_3_0,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_3_0_0,BP_COL_B_3_0_1,BP_COL_B_3_0_2,BP_COL_B_3_0_3,BP_COL_B_3_0_4,BP_COL_B_3_0_5,BP_COL_B_3_0_6,BP_COL_B_3_0_7,BP_COL_B_3_0_8,BP_COL_B_3_0_9,BP_COL_B_3_0_10,BP_COL_B_3_0_11,BP_COL_B_3_0_12,BP_COL_B_3_0_13,BP_COL_B_3_0_14,BP_COL_B_3_0_15" newline rbitfld.long 0x04 12.--15. "BP_COL_A_15_12,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_15_12_0,BP_COL_A_15_12_1,BP_COL_A_15_12_2,BP_COL_A_15_12_3,BP_COL_A_15_12_4,BP_COL_A_15_12_5,BP_COL_A_15_12_6,BP_COL_A_15_12_7,BP_COL_A_15_12_8,BP_COL_A_15_12_9,BP_COL_A_15_12_10,BP_COL_A_15_12_11,BP_COL_A_15_12_12,BP_COL_A_15_12_13,BP_COL_A_15_12_14,BP_COL_A_15_12_15" newline hexmask.long.byte 0x04 4.--11. 1. "BP_COL_A_11_4,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" newline rbitfld.long 0x04 0.--3. "BP_COL_A_3_0,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_3_0_0,BP_COL_A_3_0_1,BP_COL_A_3_0_2,BP_COL_A_3_0_3,BP_COL_A_3_0_4,BP_COL_A_3_0_5,BP_COL_A_3_0_6,BP_COL_A_3_0_7,BP_COL_A_3_0_8,BP_COL_A_3_0_9,BP_COL_A_3_0_10,BP_COL_A_3_0_11,BP_COL_A_3_0_12,BP_COL_A_3_0_13,BP_COL_A_3_0_14,BP_COL_A_3_0_15" line.long 0x08 "DTBC_BP_RSD,Data Buffer Controller Residual Buffer Base Pointer" rbitfld.long 0x08 28.--31. "BP_RSD_15_12,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_15_12_0,BP_RSD_15_12_1,BP_RSD_15_12_2,BP_RSD_15_12_3,BP_RSD_15_12_4,BP_RSD_15_12_5,BP_RSD_15_12_6,BP_RSD_15_12_7,BP_RSD_15_12_8,BP_RSD_15_12_9,BP_RSD_15_12_10,BP_RSD_15_12_11,BP_RSD_15_12_12,BP_RSD_15_12_13,BP_RSD_15_12_14,BP_RSD_15_12_15" newline hexmask.long.byte 0x08 20.--27. 1. "BP_RSD_11_4,BP_RSD specifies the base pointer to the residual data buffer" newline rbitfld.long 0x08 16.--19. "BP_RSD_3_0,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_3_0_0,BP_RSD_3_0_1,BP_RSD_3_0_2,BP_RSD_3_0_3,BP_RSD_3_0_4,BP_RSD_3_0_5,BP_RSD_3_0_6,BP_RSD_3_0_7,BP_RSD_3_0_8,BP_RSD_3_0_9,BP_RSD_3_0_10,BP_RSD_3_0_11,BP_RSD_3_0_12,BP_RSD_3_0_13,BP_RSD_3_0_14,BP_RSD_3_0_15" line.long 0x0C "DTBC_DP_UL,Data Buffer Controller Data Pointer 0" rbitfld.long 0x0C 13.--15. "PTR_MB_UL_15_13,Current pointer [15:13] to the upper left macroblock data in work buffer" "PTR_MB_UL_15_13_0,PTR_MB_UL_15_13_1,PTR_MB_UL_15_13_2,PTR_MB_UL_15_13_3,PTR_MB_UL_15_13_4,PTR_MB_UL_15_13_5,PTR_MB_UL_15_13_6,PTR_MB_UL_15_13_7" newline hexmask.long.word 0x0C 4.--12. 1. "PTR_MB_UL_12_4,Current pointer [12:4] to the upper left macroblock data in work buffer" newline rbitfld.long 0x0C 0.--3. "PTR_MB_UL_3_0,Current pointer [3:0] to the upper left macroblock data in work buffer" "PTR_MB_UL_3_0_0,PTR_MB_UL_3_0_1,PTR_MB_UL_3_0_2,PTR_MB_UL_3_0_3,PTR_MB_UL_3_0_4,PTR_MB_UL_3_0_5,PTR_MB_UL_3_0_6,PTR_MB_UL_3_0_7,PTR_MB_UL_3_0_8,PTR_MB_UL_3_0_9,PTR_MB_UL_3_0_10,PTR_MB_UL_3_0_11,PTR_MB_UL_3_0_12,PTR_MB_UL_3_0_13,PTR_MB_UL_3_0_14,PTR_MB_UL_3_0_15" line.long 0x10 "DTBC_DP_UU_UR,Data Buffer Controller Data Pointer 1" rbitfld.long 0x10 29.--31. "PTR_MB_UU_15_13,Current pointer [15:13] to the upper macroblock data in work buffer" "PTR_MB_UU_15_13_0,PTR_MB_UU_15_13_1,PTR_MB_UU_15_13_2,PTR_MB_UU_15_13_3,PTR_MB_UU_15_13_4,PTR_MB_UU_15_13_5,PTR_MB_UU_15_13_6,PTR_MB_UU_15_13_7" newline hexmask.long.word 0x10 20.--28. 1. "PTR_MB_UU_12_4,Current pointer [12:4] to the upper macroblock data in work buffer" newline rbitfld.long 0x10 16.--19. "PTR_MB_UU_3_0,Current pointer [3:0] to the upper macroblock data in work buffer" "PTR_MB_UU_3_0_0,PTR_MB_UU_3_0_1,PTR_MB_UU_3_0_2,PTR_MB_UU_3_0_3,PTR_MB_UU_3_0_4,PTR_MB_UU_3_0_5,PTR_MB_UU_3_0_6,PTR_MB_UU_3_0_7,PTR_MB_UU_3_0_8,PTR_MB_UU_3_0_9,PTR_MB_UU_3_0_10,PTR_MB_UU_3_0_11,PTR_MB_UU_3_0_12,PTR_MB_UU_3_0_13,PTR_MB_UU_3_0_14,PTR_MB_UU_3_0_15" newline rbitfld.long 0x10 13.--15. "PTR_MB_UR_15_13,Current pointer [15:13] to the upper-right macroblock data in work buffer" "PTR_MB_UR_15_13_0,PTR_MB_UR_15_13_1,PTR_MB_UR_15_13_2,PTR_MB_UR_15_13_3,PTR_MB_UR_15_13_4,PTR_MB_UR_15_13_5,PTR_MB_UR_15_13_6,PTR_MB_UR_15_13_7" newline hexmask.long.word 0x10 4.--12. 1. "PTR_MB_UR_12_4,Current pointer [12:4] to the upper-right macroblock data in work buffer" newline rbitfld.long 0x10 0.--3. "PTR_MB_UR_3_0,Current pointer [3:0] to the upper-right macroblock data in work buffer" "PTR_MB_UR_3_0_0,PTR_MB_UR_3_0_1,PTR_MB_UR_3_0_2,PTR_MB_UR_3_0_3,PTR_MB_UR_3_0_4,PTR_MB_UR_3_0_5,PTR_MB_UR_3_0_6,PTR_MB_UR_3_0_7,PTR_MB_UR_3_0_8,PTR_MB_UR_3_0_9,PTR_MB_UR_3_0_10,PTR_MB_UR_3_0_11,PTR_MB_UR_3_0_12,PTR_MB_UR_3_0_13,PTR_MB_UR_3_0_14,PTR_MB_UR_3_0_15" line.long 0x14 "DTBC_DP_LL_CUR,Data Buffer Controller Data Pointer 2" rbitfld.long 0x14 29.--31. "PTR_MB_LL_15_13,Current pointer [15:13] to the left macroblock data in work buffer" "PTR_MB_LL_15_13_0,PTR_MB_LL_15_13_1,PTR_MB_LL_15_13_2,PTR_MB_LL_15_13_3,PTR_MB_LL_15_13_4,PTR_MB_LL_15_13_5,PTR_MB_LL_15_13_6,PTR_MB_LL_15_13_7" newline hexmask.long.word 0x14 20.--28. 1. "PTR_MB_LL_12_4,Current pointer [12:4] to the left macroblock data in work buffer" newline rbitfld.long 0x14 16.--19. "PTR_MB_LL_3_0,Current pointer [3:0] to the left macroblock data in work buffer" "PTR_MB_LL_3_0_0,PTR_MB_LL_3_0_1,PTR_MB_LL_3_0_2,PTR_MB_LL_3_0_3,PTR_MB_LL_3_0_4,PTR_MB_LL_3_0_5,PTR_MB_LL_3_0_6,PTR_MB_LL_3_0_7,PTR_MB_LL_3_0_8,PTR_MB_LL_3_0_9,PTR_MB_LL_3_0_10,PTR_MB_LL_3_0_11,PTR_MB_LL_3_0_12,PTR_MB_LL_3_0_13,PTR_MB_LL_3_0_14,PTR_MB_LL_3_0_15" newline rbitfld.long 0x14 13.--15. "PTR_MB_CUR_15_13,Current pointer [15:13] to the current macroblock data in work buffer" "PTR_MB_CUR_15_13_0,PTR_MB_CUR_15_13_1,PTR_MB_CUR_15_13_2,PTR_MB_CUR_15_13_3,PTR_MB_CUR_15_13_4,PTR_MB_CUR_15_13_5,PTR_MB_CUR_15_13_6,PTR_MB_CUR_15_13_7" newline hexmask.long.word 0x14 4.--12. 1. "PTR_MB_CUR_12_4,Current pointer [12:4] to the current macroblock data in work buffer" newline rbitfld.long 0x14 0.--3. "PTR_MB_CUR_3_0,Current pointer [3:0] to the current macroblock data in work buffer" "PTR_MB_CUR_3_0_0,PTR_MB_CUR_3_0_1,PTR_MB_CUR_3_0_2,PTR_MB_CUR_3_0_3,PTR_MB_CUR_3_0_4,PTR_MB_CUR_3_0_5,PTR_MB_CUR_3_0_6,PTR_MB_CUR_3_0_7,PTR_MB_CUR_3_0_8,PTR_MB_CUR_3_0_9,PTR_MB_CUR_3_0_10,PTR_MB_CUR_3_0_11,PTR_MB_CUR_3_0_12,PTR_MB_CUR_3_0_13,PTR_MB_CUR_3_0_14,PTR_MB_CUR_3_0_15" group.long 0x84++0x0F line.long 0x00 "DTBC_DP_ULUR2,Data Buffer Controller Data Pointer 5" rbitfld.long 0x00 29.--31. "PTR_MB_UL2_15_13,Current pointer [15:13] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_15_13_0,PTR_MB_UL2_15_13_1,PTR_MB_UL2_15_13_2,PTR_MB_UL2_15_13_3,PTR_MB_UL2_15_13_4,PTR_MB_UL2_15_13_5,PTR_MB_UL2_15_13_6,PTR_MB_UL2_15_13_7" newline hexmask.long.word 0x00 20.--28. 1. "PTR_MB_UL2_12_4,Current pointer [12:4] to the macroblock left to the upper left macroblock data in work buffer" newline rbitfld.long 0x00 16.--19. "PTR_MB_UL2_3_0,Current pointer [3:0] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_3_0_0,PTR_MB_UL2_3_0_1,PTR_MB_UL2_3_0_2,PTR_MB_UL2_3_0_3,PTR_MB_UL2_3_0_4,PTR_MB_UL2_3_0_5,PTR_MB_UL2_3_0_6,PTR_MB_UL2_3_0_7,PTR_MB_UL2_3_0_8,PTR_MB_UL2_3_0_9,PTR_MB_UL2_3_0_10,PTR_MB_UL2_3_0_11,PTR_MB_UL2_3_0_12,PTR_MB_UL2_3_0_13,PTR_MB_UL2_3_0_14,PTR_MB_UL2_3_0_15" newline rbitfld.long 0x00 13.--15. "PTR_MB_UR2_15_13,Current pointer [15:13] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_15_13_0,PTR_MB_UR2_15_13_1,PTR_MB_UR2_15_13_2,PTR_MB_UR2_15_13_3,PTR_MB_UR2_15_13_4,PTR_MB_UR2_15_13_5,PTR_MB_UR2_15_13_6,PTR_MB_UR2_15_13_7" newline hexmask.long.word 0x00 4.--12. 1. "PTR_MB_UR2_12_4,Current pointer [12:4] to the macroblock right to the upper-right macroblock data in work buffer" newline rbitfld.long 0x00 0.--3. "PTR_MB_UR2_3_0,Current pointer [3:0] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_3_0_0,PTR_MB_UR2_3_0_1,PTR_MB_UR2_3_0_2,PTR_MB_UR2_3_0_3,PTR_MB_UR2_3_0_4,PTR_MB_UR2_3_0_5,PTR_MB_UR2_3_0_6,PTR_MB_UR2_3_0_7,PTR_MB_UR2_3_0_8,PTR_MB_UR2_3_0_9,PTR_MB_UR2_3_0_10,PTR_MB_UR2_3_0_11,PTR_MB_UR2_3_0_12,PTR_MB_UR2_3_0_13,PTR_MB_UR2_3_0_14,PTR_MB_UR2_3_0_15" line.long 0x04 "DTBC_DP_SLICE,Slice data pointer" rbitfld.long 0x04 13.--15. "PTR_SLICE_15_13,Specifies the pointer [15:13] to slice or picture information data" "PTR_SLICE_15_13_0,PTR_SLICE_15_13_1,PTR_SLICE_15_13_2,PTR_SLICE_15_13_3,PTR_SLICE_15_13_4,PTR_SLICE_15_13_5,PTR_SLICE_15_13_6,PTR_SLICE_15_13_7" newline hexmask.long.word 0x04 4.--12. 1. "PTR_SLICE_12_4,Specifies the pointer [12:4] to slice or picture information data" newline rbitfld.long 0x04 0.--3. "PTR_SLICE_3_0,Specifies the pointer [3:0] to slice or picture information data" "PTR_SLICE_3_0_0,PTR_SLICE_3_0_1,PTR_SLICE_3_0_2,PTR_SLICE_3_0_3,PTR_SLICE_3_0_4,PTR_SLICE_3_0_5,PTR_SLICE_3_0_6,PTR_SLICE_3_0_7,PTR_SLICE_3_0_8,PTR_SLICE_3_0_9,PTR_SLICE_3_0_10,PTR_SLICE_3_0_11,PTR_SLICE_3_0_12,PTR_SLICE_3_0_13,PTR_SLICE_3_0_14,PTR_SLICE_3_0_15" line.long 0x08 "DTBC_DP_LL2,Data Buffer Controller data pointer" rbitfld.long 0x08 13.--15. "PTR_MB_LL2_15_13,Current pointer [15:13] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_15_13_0,PTR_MB_LL2_15_13_1,PTR_MB_LL2_15_13_2,PTR_MB_LL2_15_13_3,PTR_MB_LL2_15_13_4,PTR_MB_LL2_15_13_5,PTR_MB_LL2_15_13_6,PTR_MB_LL2_15_13_7" newline hexmask.long.word 0x08 4.--12. 1. "PTR_MB_LL2_12_4,Current pointer [12:4] to the macroblock left to the left macroblock data in work buffer" newline rbitfld.long 0x08 0.--3. "PTR_MB_LL2_3_0,Current pointer [3:0] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_3_0_0,PTR_MB_LL2_3_0_1,PTR_MB_LL2_3_0_2,PTR_MB_LL2_3_0_3,PTR_MB_LL2_3_0_4,PTR_MB_LL2_3_0_5,PTR_MB_LL2_3_0_6,PTR_MB_LL2_3_0_7,PTR_MB_LL2_3_0_8,PTR_MB_LL2_3_0_9,PTR_MB_LL2_3_0_10,PTR_MB_LL2_3_0_11,PTR_MB_LL2_3_0_12,PTR_MB_LL2_3_0_13,PTR_MB_LL2_3_0_14,PTR_MB_LL2_3_0_15" line.long 0x0C "DTBC_CUR_MB_SIZE,Current Picture Macro Block element size" hexmask.long.byte 0x0C 4.--11. 1. "CUR_MB_SIZE_11_4,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" newline rbitfld.long 0x0C 0.--3. "CUR_MB_SIZE_3_0,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" "CUR_MB_SIZE_3_0_0,CUR_MB_SIZE_3_0_1,CUR_MB_SIZE_3_0_2,CUR_MB_SIZE_3_0_3,CUR_MB_SIZE_3_0_4,CUR_MB_SIZE_3_0_5,CUR_MB_SIZE_3_0_6,CUR_MB_SIZE_3_0_7,CUR_MB_SIZE_3_0_8,CUR_MB_SIZE_3_0_9,CUR_MB_SIZE_3_0_10,CUR_MB_SIZE_3_0_11,CUR_MB_SIZE_3_0_12,CUR_MB_SIZE_3_0_13,CUR_MB_SIZE_3_0_14,CUR_MB_SIZE_3_0_15" group.long 0xA0++0x07 line.long 0x00 "CDC_MODE,Codec Mode (also works as view page)" bitfld.long 0x00 4. "DIR,Selects the codec direction: Write" "Indicates the codec engine is decoding,Indicates the codec engine is encoding" newline bitfld.long 0x00 0.--3. "MODE,Selects the active codec Selected Codec (Selected Codec Engine)" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,MODE_6,MODE_7,MODE_8,MODE_9,MODE_10,?,?,?,?,?" line.long 0x04 "AVS_STAT,AVS STAT register" bitfld.long 0x04 31. "STAT_END_OF_SLICE,stat_end_of_vop ECD sets this field to 1 when the current macroblock is the last macroblock in a VOP Once this field is set ECD keeps this field to 1 until the next macroblock processing is started" "0,1" newline bitfld.long 0x04 9. "ERR_ILL_NEXT_START_CODE_SEARCH,err_ill_next_start_code_search If ECD founds error and ECD status is changed into ERR in error detection described in section 8.5. ECD starts to search the next start code search" "0,1" newline bitfld.long 0x04 8. "ERR_ILL_END_OF_SLICE,err_ill_end_of_slice Some encoder wrongly encode EOS" "0,1" newline bitfld.long 0x04 7. "ERR_ILL_MB_SKIP_RUN,err_ill_mb_skip_run If ECD founds decoded mb_skip_run is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 6. "ERR_ILL_MB_TYPE,err_ill_mb_type If ECD founds decoded mb_type is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 5. "ERR_ILL_INTRA_CHROMA_PRED_MODE,err_ill_intra_chroma_pred_mode If ECD founds decoded intra_chroma_pred_mode is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 4. "ERR_ILL_MV_DIFF,err_ill_mv_diff If ECD founds decoded mv_diff is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 3. "ERR_ILL_CBP,err_ill_cbp If ECD founds decoded cbp is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 2. "ERR_ILL_MB_QP_DELTA,err_ill_mb_qp_delta If ECD founds decoded mb_qp_delta is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 1. "ERR_ILL_COEFF,err_ill_coeff If ECD founds decoded coefficient is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 0. "ERR_ILL_EOB,err_ill_eob If ECD cannot found end of block in 64 coefficients this field is set to 1 by ECD; otherwise 0" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "H264_ERR_STAT,H.264 STAT register" bitfld.long 0x00 31. "EOS," "0,1" newline bitfld.long 0x00 4. "SC_ERR," "0,1" newline bitfld.long 0x00 3. "MV_ERR," "0,1" newline bitfld.long 0x00 2. "ALGN_ERR," "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR," "0,1" newline bitfld.long 0x00 0. "SYM_ERR," "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "INT_STATUS,INT STAT register" bitfld.long 0x00 31. "PRCS_DONE,If encoding or decoding of a picture is finished an interrupt pulse is asserted and this status bit becomes high" "not finished,processing done" newline bitfld.long 0x00 30. "EOS_DONE,If encoding of decoding of a scan is finished an interrupt pulse is asserted and this status bit becomes high" "not finished,processing done" newline bitfld.long 0x00 2. "BLK_COEF_NUM_ERR,If current MCU has a block which has more than 64 coefficients this error bit becomes high" "correct (all blocks inside the current MCU have..,incorrect (some blocks inside the current MCU.." newline bitfld.long 0x00 1. "RSTRT_INTVL_ERR,If number of MCU between neighbored restart markers is not equal to restart interval this error bit becomes high" "no error,restart interval error.." newline bitfld.long 0x00 0. "VLD_TBL_ERR,If stream data which is out of table is detected the JPEG core makes this bit high" "no error,out of table error.." rgroup.long 0xA4++0x03 line.long 0x00 "MP2_STAT,MP2 STAT register" bitfld.long 0x00 31. "STAT_END_OF_SLICE,Showing the current macroblock is the last macroblock in a slice" "0,1" newline bitfld.long 0x00 15. "ERR_DCCOEF_OVERFLOW,Showing the result of dc prediction is overflowed or under flowed" "0,1" newline bitfld.long 0x00 14. "ERR_ILL_NEXT_START_CODE_SEARCH,Showing next start code searching infinite error" "0,1" newline bitfld.long 0x00 13. "ERR_ILL_SLICE_START_POSITION,In decoding showing the following two data is mismatched: - macroblock position derived from slice_vertical_position and macroblock_address_increment - macroblock position in ECD MMR In encoding this field is fixed to 0" "0,1" newline bitfld.long 0x00 12. "ERR_ILL_QUANTISER_SCALE_CODE,In decoding decoded quantizer_scale_code is 0" "0,1" newline bitfld.long 0x00 11. "ERR_ILL_END_OF_SLICE,In decoding EOS cannot be found at the end of picture" "0,1" newline bitfld.long 0x00 10. "ERR_MB_ADDR_INCREMENT,In decoding VLD out of table in macroblock_address_increment" "0,1" newline bitfld.long 0x00 9. "ERR_MB_TYPE,In decoding VLD out of table in macroblock_type" "0,1" newline bitfld.long 0x00 8. "ERR_MOTION_CODE,In decoding VLD out of table in motion_code and dmv" "0,1" newline bitfld.long 0x00 7. "ERR_CBP,In decoding VLD out of table in coded_block_pattern" "0,1" newline bitfld.long 0x00 6. "ERR_DCT_COEF,In decoding VLD out of table in DCT coefficient" "0,1" newline bitfld.long 0x00 5. "ERR_ILL_MBTYPE_D_PIC,In decoding decoded macroblock_type != 1 when D-picture" "0,1" newline bitfld.long 0x00 4. "ERR_ILL_MARKER_CONCEALMENT,In decoding decoded marker_bit != 0 when both the concealment_motion_vector and macroblock_intra are equal to 1" "0,1" newline bitfld.long 0x00 3. "ERR_ILL_MP2_ESCAPE_LVL,In decoding decoded level from MPEG-2 ESCAPE code is 0x000 or 0x800" "0,1" newline bitfld.long 0x00 2. "ERR_ILL_MP1_ESCAPE_LVL,In decoding decoded level from MPEG-1 ESCAPE code is 0x0000 or 0x8000" "0,1" newline bitfld.long 0x00 1. "ERR_ILL_EOB,In decoding ECD cannot find EOB end of block in a 64 coefficient block" "0,1" newline bitfld.long 0x00 0. "ERR_ILL_EOM,In decoding ECD cannot find EOM end of macroblock at the end of macroblock when picture_type is D-picture" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "MP4_STAT,MP4 STAT register" bitfld.long 0x00 31. "STAT_END_OF_PACKET,ECD sets this field to 1 when the current macroblock is the last macroblock in a packet" "0,1" newline bitfld.long 0x00 25. "ERR_NEXT_START_CODE_SEARCH,ECD sets this field to 1 if next start code search is 'failed'" "0,1" newline bitfld.long 0x00 24. "ERR_PKT_RESYNC_MARKER,ECD sets this field to 1 when resync_marker at the beginning of packet header is incorrect" "0,1" newline bitfld.long 0x00 23. "ERR_PKT_NEXT_START_CODE,ECD sets this field to 1 when next_start_code at the end of VOP is incorrect or start_code at the beginning of slice or at the end of VOP is incorrect" "0,1" newline bitfld.long 0x00 22. "ERR_PKT_ZERO_BIT,ECD sets this field to 1 when zero_bit at the end of GOB or slice layer is incorrect or emulation_prevention_bit in slice header is incorrect" "0,1" newline bitfld.long 0x00 21. "ERR_PKT_MBNUM,ECD sets this field to 1 when macroblock_number in packet header is dropped" "0,1" newline bitfld.long 0x00 20. "ERR_PKT_QUANT_SCALE,ECD sets this field to 1 when quant_scale in packet header is illegal" "0,1" newline bitfld.long 0x00 19. "ERR_PKT_TIME,ECD sets this field to 1 when modulo_time or vop_time_increment in packet header is changed" "0,1" newline bitfld.long 0x00 18. "ERR_PKT_MARKER_BIT,ECD sets this field to 1 when marker_bit in packet header is incorrect" "0,1" newline bitfld.long 0x00 17. "ERR_PKT_CHG_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is changed" "0,1" newline bitfld.long 0x00 16. "ERR_PKT_ILL_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is illegal" "0,1" newline bitfld.long 0x00 15. "ERR_PKT_VOP_FCODE,ECD sets this field to 1 when vop_fcode_forward or vop_fcode_backward in packet header is illegal" "0,1" newline bitfld.long 0x00 14. "ERR_GOB_GOBNUM,ECD sets this field to 1 when gob_number is dropped or macroblock_address in slice header is dropped" "0,1" newline bitfld.long 0x00 13. "ERR_GOB_GOB_FRAME_ID,ECD sets this field to 1 when gob_frame_id is changed" "0,1" newline bitfld.long 0x00 12. "ERR_GOB_QUANT_SCALE,ECD sets this field to 1 when quant_scale in GOB header is illegal or slice_quantizer_information in slice header is illegal" "0,1" newline bitfld.long 0x00 11. "ERR_MBHD_MCBPC,ECD sets this field to 1 when mcbpc code is illegal" "0,1" newline bitfld.long 0x00 10. "ERR_MBHD_H263_4MV,ECD3 sets this field to 1 if one of the following two conditions is true: - H263_mode is ON deblocking_filter_mode = 0 no_gob_header = 0 and decoded macroblock type is INTRA4V or INTRA4V_Q" "0,1" newline bitfld.long 0x00 9. "ERR_MBHD_CBPY,ECD sets this field to 1 when cpby code is illegal (non-B-VOP)" "0,1" newline bitfld.long 0x00 7. "ERR_MBHD_MB_TYPE,ECD sets this field to 1 when mb_type code is illegal (B-VOP)" "0,1" newline bitfld.long 0x00 6. "ERR_MBHD_MV_DATA,ECD sets this field to 1 when horizontal_mv_data or vertical_mv_data code is illegal" "0,1" newline bitfld.long 0x00 5. "ERR_BLK_DCT_DC_SIZE,ECD sets this field to 1 when dct_dc_size code is illegal" "0,1" newline bitfld.long 0x00 4. "ERR_BLK_TCOEF,ECD sets this field to 1 when tcoef code is illegal" "0,1" newline bitfld.long 0x00 3. "ERR_BLK_MARKER_BIT,ECD sets this field to 1 when marker_bit in dct_dc_size ESCAPE3 or RVLC is incorrect" "0,1" newline bitfld.long 0x00 2. "ERR_BLK_ESCAPE_LEVEL,ECD sets this field to 1 when ESCAPE3 level = 0 or 0x800 RVLC ESCAPE level = 0 H.263 DC = 0x00 or 0x80 or H.263 ESCAPE level = 0 or 0x80" "0,1" newline bitfld.long 0x00 1. "ERR_BLK_RVLC_ESCAPE_CODE,ECD sets this field to 1 when the last ESCAPE code of RVLC ESCAPE is not '0000s'" "0,1" newline bitfld.long 0x00 0. "ERR_BLK_EOB,ECD sets this field to 1 when ECD cannot find EOB in 64 coefficients" "0,1" rgroup.long 0xA4++0x07 line.long 0x00 "VC1_STAT,VC-1 STAT register" bitfld.long 0x00 31. "INT_EOS," "0,1" newline bitfld.long 0x00 10. "WARN_EOS_SYNCMARKER,This issue is raised when ECD3 cannot find syncmarker header syntax even though a single-bit just after decoding last MB is equal to 0" "0,1" newline bitfld.long 0x00 9. "WARN_EOS_TRAILINGBIT," "0,1" newline bitfld.long 0x00 8. "WARN_MQUANT_OVERFLOW,warn_mquant_overflow" "MQUANT does not overflow,MQUANT overflow" newline bitfld.long 0x00 2. "ERR_EOS,err_eos indicates an error during search processing for next start code" "0,1" newline bitfld.long 0x00 1. "ERR_VLC_TABLE,err_vlc_table indicates when the following irregular cases happen" "0,1" newline bitfld.long 0x00 0. "ERR_BLK_COEF,err_blk_coef indicates when the following irregular cases happen" "0,1" line.long 0x04 "AVS_MASK,AVS MASK register" bitfld.long 0x04 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 9. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 8. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 7. "MASK_ERR_ILL_MB_SKIP_RUN,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 6. "MASK_ERR_ILL_MB_TYPE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 5. "MASK_ERR_ILL_INTRA_CHROMA_PRED_MODE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 4. "MASK_ERR_ILL_MV_DIFF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 3. "MASK_ERR_ILL_CBP,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 2. "MASK_ERR_ILL_MB_QP_DELTA,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 1. "MASK_ERR_ILL_COEFF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 0. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "H264_ERR_MSK,H.264 MASK register" rbitfld.long 0x00 31. "EOS_MSK,EOS_MSK = 1 enables detection of an EOS" "0,1" newline rbitfld.long 0x00 4. "SC_ERR_MSK,SC_ERR_MSK = 0 (fixed) which indicates that int_err will never be issued on detecting start code search error" "0,1" newline rbitfld.long 0x00 3. "MV_ERR_MSK,MV_ERR_MSK = 1 enables detection of mv errors (MV_ERR)" "0,1" newline bitfld.long 0x00 2. "ALGN_ERR_MSK,ALGN_ERR_MSK = 1 enables detection of CABAC alignment bits errors (ALGN_ERR)" "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR_MSK,IPCM_ALGN_ERR_MSK = 1 enables detection of I_PCM alignment bits errors (IPCM_ALGN_ERR)" "0,1" newline rbitfld.long 0x00 0. "SYM_ERR_MSK,SYM_ERR_MSK = 1 enables detections of all other bitstream errors (SYM_ERR)" "0,1" rgroup.long 0xA8++0x03 line.long 0x00 "INT_MASK,INT MASK register" bitfld.long 0x00 31. "PRCS_DONE_MASK,Mask register for prcs_done signal" "PRCS_DONE signal disable,PRCS_DONE signal enable" newline bitfld.long 0x00 30. "EOS_MASK,Mask register for eos_done pulse signal" "EOS_DONE signal disable,EOS_DONE signal enable" newline bitfld.long 0x00 0. "VLD_TBL_ERR,Mask register for control of error interrupt assertion" "no error interrupt is asserted though condition..,error interrupt is asserted if condition is hit" group.long 0xA8++0x03 line.long 0x00 "MP2_MASK,MP2 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 15. "MASK_ERR_DCCOEF_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 13. "MASK_ERR_ILL_SLICE_START_POSITION,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_ILL_QUANTISER_SCALE_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 11. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MB_ADDR_INCREMENT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 9. "MASK_ERR_MB_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 8. "MASK_ERR_MOTION_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 7. "MASK_ERR_CBP,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 6. "MASK_ERR_DCT_COEF,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 5. "MASK_ERR_ILL_MBTYPE_D_PIC,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 4. "MASK_ERR_ILL_MARKER_CONCEALMENT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 3. "MASK_ERR_ILL_MP2_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_ILL_MP1_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 0. "MASK_ERR_ILL_EOM,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "MP4_MASK,MP4 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_PACKET,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 25. "MASK_ERR_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 24. "MASK_ERR_PKT_RESYNC_MARKER,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 23. "MASK_ERR_PKT_NEXT_START_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 22. "MASK_ERR_PKT_ZERO_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 21. "MASK_ERR_PKT_MBNUM,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 20. "MASK_ERR_PKT_QUANT_SCALE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 19. "MASK_ERR_PKT_TIME,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 18. "MASK_ERR_PKT_MARKER_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 17. "MASK_ERR_PKT_CHG_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 16. "MASK_ERR_PKT_ILL_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 15. "MASK_ERR_PKT_VOP_FCODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_GOB_GOBNUM,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 13. "MASK_ERR_GOB_GOB_FRAME_ID,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_GOB_QUANT_SCALE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 11. "MASK_ERR_MBHD_MCBPC,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MBHD_H263_4MV,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 9. "MASK_ERR_MBHD_CBPY,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 7. "MASK_ERR_MBHD_MB_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 6. "MASK_ERR_MBHD_MV_DATA,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 5. "MASK_ERR_BLK_DCT_DC_SIZE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 4. "MASK_ERR_BLK_TCOEF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 3. "MASK_ERR_BLK_MARKER_BIT,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_BLK_ESCAPE_LEVEL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_BLK_RVLC_ESCAPE_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 0. "MASK_ERR_BLK_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x07 line.long 0x00 "VC1_MASK,VC-1 MASK register" rbitfld.long 0x00 31. "MASK_INT_EOS," "0,1" newline rbitfld.long 0x00 10. "MASK_EOS_SYNCMARKER," "0,1" newline rbitfld.long 0x00 9. "MASK_WARN_EOS_TRAILINGBIT,Reserved" "0,1" newline bitfld.long 0x00 8. "MASK_MQUANT_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_EOS,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_VLC_TABLE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 0. "MASK_ERR_BLK_COEF,Mask flags correspond to status bits" "0,1" line.long 0x04 "AVS_WORK0,AVS WORK0 register" hexmask.long.word 0x04 16.--29. 1. "SKIPMBCOUNT,SkipMbCount This field specifies SkipMbCount described in AVS standard section 9.3" newline bitfld.long 0x04 9. "SLICE_DATA_RD_EN,Slice data read enable flag" "slice data is read only at the first macroblock..,slice data is read at every macroblocks AVS RTL.." newline bitfld.long 0x04 8. "NEXT_START_CODE_SEARCH,next_start_code_search This field specifies ECD starts start code search or not when error is occurred" "non-search,search" group.long 0xAC++0x03 line.long 0x00 "CFG_QP," bitfld.long 0x00 31. "MV_FLAG_EN,MV_FLAG_EN =1 enables motion vector and reference index comparison in decoding" "0,1" newline bitfld.long 0x00 30. "H264_RSV,Reserved for future use" "0,1" newline bitfld.long 0x00 29. "FORCE_SLC_LD,FORCE_SLC_LD = 1 forces slice information data loading from memory for each macroblock process" "0,1" newline rbitfld.long 0x00 28. "USE_CABAC,USE_CABAC = 1 indicates that the CABAC is in use for entropy coding" "0,1" newline bitfld.long 0x00 18.--19. "COL_MB_FMT,COL_MB_FMT indicates the macroblock header format type for the co-located macroblock data" "Bi-16-MV format,16-MV format,Bi-4-MV format,The reserved ECD3 automatically loads.." newline bitfld.long 0x00 16.--17. "MB_FMT,MB_FMT indicates the macroblock header format type for the current macroblock and neighboring macroblocks in the current picture" "Bi-16-MV format,16-MV format,Bi-4-MV format,The reserved ECD3 automatically loads.." newline bitfld.long 0x00 8.--13. "QP_DELTA,QP_DELTA is equal to mb_qp_delta of the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "QP,QP is equal to the quantizer parameter for the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x03 line.long 0x00 "JPEG_CTRL,JPEG Control register" hexmask.long.word 0x00 16.--31. 1. "DC_PRED_Y,Luminance DC prediction value is stored in register" newline rbitfld.long 0x00 8.--10. "RSTRT_MRKR_CNT,Restart marker counter value (during encoding only) is reflected in this register" "RSTRT_MRKR_CNT_0,RSTRT_MRKR_CNT_1,RSTRT_MRKR_CNT_2,RSTRT_MRKR_CNT_3,RSTRT_MRKR_CNT_4,RSTRT_MRKR_CNT_5,RSTRT_MRKR_CNT_6,RSTRT_MRKR_CNT_7" newline bitfld.long 0x00 1. "DC_PRED_RST,If this register bit is high DC prediction for the first block of the current MCU is not executed" "DC prediction is executed,DC prediction is reset" newline bitfld.long 0x00 0. "INIT_EN,This bit controls initialization of JPEG core on ECD module" "initialize disable,initialize start" group.long 0xAC++0x03 line.long 0x00 "MP2_WORK0,MP2 WORK0 register" hexmask.long.word 0x00 16.--31. 1. "MB_SKIP_RUN,Specifies the number of macroblocks to be skipped" newline bitfld.long 0x00 11. "START_CODE_SEARCH_FLAG,Specifies whether ECD starts searching next start code or not when error is occurred in decoding" "Not search next start code,Search next start code In encoding this field.." newline bitfld.long 0x00 10. "MACROBLOCK_MOTION_BACKWARD,Specifies macroblock_motion_backward described in MPEG-2 standard section 6.3.17.1" "0,1" newline bitfld.long 0x00 9. "MACROBLOCK_MOTION_FORWARD,Specifies macroblock_motion_forward described in MPEG-2 standard section 6.3.17.1" "0,1" newline bitfld.long 0x00 0.--4. "PREV_QUANTISER_SCALE_CODE,Specifies previous macroblock's quantizer_scale_code described in MPEG-2 standard section 6.3.16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x03 line.long 0x00 "MP4_WORK0,MP4 WORK0 register" bitfld.long 0x00 24.--28. "RUNNINGQP,This field is used for reserving runningQp for the next macroblock not showing the current macroblock's quantizer_scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--22. "VOP_FCODE_BACKWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "VOP_FCODE_FORWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--15. "DP_MODE,This field indicates which data is encoding or decoding in data partitioning mode" "GOB header or motion and header information..,texture header processing,TCOEF processing or packet header In non data..,?..." newline bitfld.long 0x00 12.--13. "GOB_FRAME_ID,This field specifies gob_frame_id which is updated at gob header" "0,1,2,3" newline bitfld.long 0x00 8.--10. "INTRA_DC_VLC_THR,This is a 3-bit code that specifies a threshold value of quantizer scale used to switch between two VLC's for coding of Intra DC coefficients" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "FIRST_NON_EMPTY_HEADER,This is the flag to indicate the first non empty GOB header or not" "0,1" newline bitfld.long 0x00 6. "MINI_SLICE_HEADER_FLAG,In H.263 decoding this field specifies whether the current slice header is mini slice header or not" "non mini slice header,mini slice header Otherwise this field must be 0" newline bitfld.long 0x00 5. "START_CODE_SEARCH_FLAG,In decoding this field specifies whether ECD starts searching next_start_code and resync_marker or not when error is occurred in decoding" "Not search next start code and resync marker,Search next start code and resync marker In.." newline bitfld.long 0x00 0.--4. "GOB_NUMBER,In decoding this field specifies gob_number of the current macroblock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x07 line.long 0x00 "VC1_WORK,VC-1 WORK register" bitfld.long 0x00 8. "FIXED_LENTH_CODE,Presence of Fixed Length Code (escape mode 3) Setting 1 specifies the first case of escape mode 3 in a frame" "non-first case of escape mode 3 in frame,first case of escape mode 3 in frame" newline rbitfld.long 0x00 7. "FIXED_TO_ZERO," "0,1" newline bitfld.long 0x00 4.--6. "RUN_CODE_SIZEOFESCAPE_MODE_3,Run code size of escape mode 3 Run code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "LEVEL_CODE_SIZEOFESCAPE_MODE_3,Level code size of escape mode 3 Level code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AVS_WORK1,AVS WORK1 register" hexmask.long.word 0x04 20.--31. 1. "PTR_MVD_15_4,PTR_MVD Start address of temporary MVD info" newline rbitfld.long 0x04 16.--19. "PTR_MVD_3_0,PTR_MVD Start address of temporary MVD info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x04 4.--15. 1. "PTR_RUNLVL_15_4,PTR_RUNLVL Start address of temporary run level info" newline rbitfld.long 0x04 0.--3. "PTR_RUNLVL_3_0,PTR_RUNLVL Start address of temporary run level info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x03 line.long 0x00 "CDC_VP_4," hexmask.long.word 0x00 3.--15. 1. "ACPREDPTR_15_3,ACPREDPTR I picture except simple/main I picture" group.long 0xB0++0x03 line.long 0x00 "MP2_WORK1,MP2 WORK1 register" hexmask.long.word 0x00 16.--26. 1. "DCT_DC_PRED1,In decoding this value specifies dct_dc_pred[1] described in MPEG-2 standard section 7.2.1" newline hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED0,In decoding this value specifies dct_dc_pred[0] described in MPEG-2 standard section 7.2.1" group.long 0xB0++0x03 line.long 0x00 "MP4_WORK1,MP4 WORK1 register" hexmask.long.word 0x00 16.--29. 1. "SKIPRUN,In the case of B-VOP decoding if decoded macroblock_number in video_packet_header > the macroblock address counter ECD notices the macroblocks from the macroblock address counter to macroblock_number -1 would be not_coded macroblock" newline hexmask.long.byte 0x00 8.--15. 1. "SLICE_Y,In data partitioning this field shows the position of the first macroblock in a slice" newline hexmask.long.byte 0x00 0.--7. 1. "SLICE_X,In data partitioning this field shows the position of the first macroblock in a slice" group.long 0xB0++0x03 line.long 0x00 "SKIP_RUN," hexmask.long.word 0x00 0.--15. 1. "SKIP_RUN_NB,SKIP_RUN_NB indicates the number of skipped macroblocks left in CAVLC" group.long 0xB0++0x07 line.long 0x00 "VLC_HUFFPTR_DC,Pointers to Huffman table for VLC DC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_DC_CHROMA_31_29,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_31_29_0,VLCHUFFPTR_DC_CHROMA_31_29_1,VLCHUFFPTR_DC_CHROMA_31_29_2,VLCHUFFPTR_DC_CHROMA_31_29_3,VLCHUFFPTR_DC_CHROMA_31_29_4,VLCHUFFPTR_DC_CHROMA_31_29_5,VLCHUFFPTR_DC_CHROMA_31_29_6,VLCHUFFPTR_DC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_DC_CHROMA_28_19,Indicating start address of Huffman table for VLC DC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_DC_CHROMA_18_16,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_18_16_0,VLCHUFFPTR_DC_CHROMA_18_16_1,VLCHUFFPTR_DC_CHROMA_18_16_2,VLCHUFFPTR_DC_CHROMA_18_16_3,VLCHUFFPTR_DC_CHROMA_18_16_4,VLCHUFFPTR_DC_CHROMA_18_16_5,VLCHUFFPTR_DC_CHROMA_18_16_6,VLCHUFFPTR_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "VLCHUFFPTR_DC_LUMA_15_13,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_15_13_0,VLCHUFFPTR_DC_LUMA_15_13_1,VLCHUFFPTR_DC_LUMA_15_13_2,VLCHUFFPTR_DC_LUMA_15_13_3,VLCHUFFPTR_DC_LUMA_15_13_4,VLCHUFFPTR_DC_LUMA_15_13_5,VLCHUFFPTR_DC_LUMA_15_13_6,VLCHUFFPTR_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_DC_LUMA_12_3,Indicating start address of Huffman table for VLC DC-luma" newline rbitfld.long 0x00 0.--2. "VLCHUFFPTR_DC_LUMA_2_0,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_2_0_0,VLCHUFFPTR_DC_LUMA_2_0_1,VLCHUFFPTR_DC_LUMA_2_0_2,VLCHUFFPTR_DC_LUMA_2_0_3,VLCHUFFPTR_DC_LUMA_2_0_4,VLCHUFFPTR_DC_LUMA_2_0_5,VLCHUFFPTR_DC_LUMA_2_0_6,VLCHUFFPTR_DC_LUMA_2_0_7" line.long 0x04 "CABAC_REG," bitfld.long 0x04 29. "PRE_SKIP,PRE_SKIP = 1 indicates that both top and bottom macroblocks in MB-AFF mode decoding are skipped" "0,1" newline bitfld.long 0x04 28. "FIRST_BIT,FIRST_BIT = 1 indicates that the next bit put by CABAC is the first bit since the last CABAC initialization" "0,1" newline hexmask.long.word 0x04 16.--25. 1. "C_LOW_OFST,C_LOW_OFST is equal to codILow in encoding and codIOffset in decoding" newline hexmask.long.word 0x04 0.--8. 1. "C_RNG,C_RNG is equal to codIRange" group.long 0xB4++0x03 line.long 0x00 "CDC_VP_5," hexmask.long.word 0x00 3.--15. 1. "OVERFLAGPTR_15_3,OVERFLAGPTR I picture except simple/main I picture" group.long 0xB4++0x03 line.long 0x00 "MP2_WORK2,MP2 WORK2 register" hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED2,In decoding this value specifies dct_dc_pred[2] described in MPEG-2 standard section 7.2.1" group.long 0xB4++0x03 line.long 0x00 "MP4_WORK2,MP4 WORK2 register" hexmask.long.word 0x00 16.--29. 1. "SLICE_MBADDR,In data partition decoding this field shows the macroblock address of the first macroblock in the current slice" newline bitfld.long 0x00 0.--1. "GOB_MBROW,In the case h263_mode = 1 and decoding this field shows the vertical position of current macroblock in a slice or GOB" "0,1,2,3" group.long 0xB4++0x07 line.long 0x00 "VLC_HUFFPTR_AC,Pointers to Huffman table for VLC AC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_AC_CHROMA_31_29,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_31_29_0,VLCHUFFPTR_AC_CHROMA_31_29_1,VLCHUFFPTR_AC_CHROMA_31_29_2,VLCHUFFPTR_AC_CHROMA_31_29_3,VLCHUFFPTR_AC_CHROMA_31_29_4,VLCHUFFPTR_AC_CHROMA_31_29_5,VLCHUFFPTR_AC_CHROMA_31_29_6,VLCHUFFPTR_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_AC_CHROMA_28_19,Indicating start address of Huffman table for VLC AC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_AC_CHROMA_18_16,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_18_16_0,VLCHUFFPTR_AC_CHROMA_18_16_1,VLCHUFFPTR_AC_CHROMA_18_16_2,VLCHUFFPTR_AC_CHROMA_18_16_3,VLCHUFFPTR_AC_CHROMA_18_16_4,VLCHUFFPTR_AC_CHROMA_18_16_5,VLCHUFFPTR_AC_CHROMA_18_16_6,VLCHUFFPTR_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "VLCHUFFPTR_AC_LUMA_15_13,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_15_13_0,VLCHUFFPTR_AC_LUMA_15_13_1,VLCHUFFPTR_AC_LUMA_15_13_2,VLCHUFFPTR_AC_LUMA_15_13_3,VLCHUFFPTR_AC_LUMA_15_13_4,VLCHUFFPTR_AC_LUMA_15_13_5,VLCHUFFPTR_AC_LUMA_15_13_6,VLCHUFFPTR_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_AC_LUMA_12_3,Indicating start address of Huffman table for VLC AC-luma" newline rbitfld.long 0x00 0.--2. "VLCHUFFPTR_AC_LUMA_2_0,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_2_0_0,VLCHUFFPTR_AC_LUMA_2_0_1,VLCHUFFPTR_AC_LUMA_2_0_2,VLCHUFFPTR_AC_LUMA_2_0_3,VLCHUFFPTR_AC_LUMA_2_0_4,VLCHUFFPTR_AC_LUMA_2_0_5,VLCHUFFPTR_AC_LUMA_2_0_6,VLCHUFFPTR_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_6," hexmask.long.word 0x04 3.--15. 1. "MVMODEPTR_15_3,MVMODEPTR Progressive P picture" group.long 0xB8++0x03 line.long 0x00 "MP2_WORK3,MP2 WORK3 register" hexmask.long.word 0x00 16.--31. 1. "PMV1,Specifies PMV[0][0][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV0,Specifies PMV[0[0][0] described in MPEG-2 standard section 7.6.3. They are half-pel precision" group.long 0xB8++0x03 line.long 0x00 "MP4_WORK3," rbitfld.long 0x00 13.--14. "PTR_MVD_14_13,This field specifies temporary MVD data pointer" "0,1,2,3" newline hexmask.long.word 0x00 4.--12. 1. "PTR_MVD_12_4,This field specifies temporary MVD data pointer" newline rbitfld.long 0x00 0.--3. "PTR_MVD_3_0,This field specifies temporary MVD data pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x03 line.long 0x00 "SYM_CNT," group.long 0xB8++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_DC,Pointers to control table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_DC_CHROMA_31_29,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_31_29_0,UVLD_CTRL_DC_CHROMA_31_29_1,UVLD_CTRL_DC_CHROMA_31_29_2,UVLD_CTRL_DC_CHROMA_31_29_3,UVLD_CTRL_DC_CHROMA_31_29_4,UVLD_CTRL_DC_CHROMA_31_29_5,UVLD_CTRL_DC_CHROMA_31_29_6,UVLD_CTRL_DC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_DC_CHROMA_28_19,Indicating start address of control table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_DC_CHROMA_18_16,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_18_16_0,UVLD_CTRL_DC_CHROMA_18_16_1,UVLD_CTRL_DC_CHROMA_18_16_2,UVLD_CTRL_DC_CHROMA_18_16_3,UVLD_CTRL_DC_CHROMA_18_16_4,UVLD_CTRL_DC_CHROMA_18_16_5,UVLD_CTRL_DC_CHROMA_18_16_6,UVLD_CTRL_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CTRL_DC_LUMA_15_13,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_15_13_0,UVLD_CTRL_DC_LUMA_15_13_1,UVLD_CTRL_DC_LUMA_15_13_2,UVLD_CTRL_DC_LUMA_15_13_3,UVLD_CTRL_DC_LUMA_15_13_4,UVLD_CTRL_DC_LUMA_15_13_5,UVLD_CTRL_DC_LUMA_15_13_6,UVLD_CTRL_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_DC_LUMA_12_3,Indicating start address of control table for UVLD DC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CTRL_DC_LUMA_2_0,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_2_0_0,UVLD_CTRL_DC_LUMA_2_0_1,UVLD_CTRL_DC_LUMA_2_0_2,UVLD_CTRL_DC_LUMA_2_0_3,UVLD_CTRL_DC_LUMA_2_0_4,UVLD_CTRL_DC_LUMA_2_0_5,UVLD_CTRL_DC_LUMA_2_0_6,UVLD_CTRL_DC_LUMA_2_0_7" line.long 0x04 "BITS_OSTD," group.long 0xBC++0x03 line.long 0x00 "CDC_VP_7," hexmask.long.word 0x00 3.--15. 1. "SKIPMBPTR_15_3,SKIPMBPTR Progressive P/B picture Interlace Frame P/B picture" group.long 0xBC++0x03 line.long 0x00 "MP2_WORK4,MP2 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "PMV4,Specifies PMV[0][1][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV3,Specifies PMV[0][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xBC++0x03 line.long 0x00 "MP4_WORK4,MP4 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "MVP01,MVP[0][1]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP00,MVP[0][0]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" group.long 0xBC++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_AC,Pointers to control table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_AC_CHROMA_31_29,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_31_29_0,UVLD_CTRL_AC_CHROMA_31_29_1,UVLD_CTRL_AC_CHROMA_31_29_2,UVLD_CTRL_AC_CHROMA_31_29_3,UVLD_CTRL_AC_CHROMA_31_29_4,UVLD_CTRL_AC_CHROMA_31_29_5,UVLD_CTRL_AC_CHROMA_31_29_6,UVLD_CTRL_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_AC_CHROMA_28_19,Indicating start address of control table for UVLD AC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_AC_CHROMA_18_16,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_18_16_0,UVLD_CTRL_AC_CHROMA_18_16_1,UVLD_CTRL_AC_CHROMA_18_16_2,UVLD_CTRL_AC_CHROMA_18_16_3,UVLD_CTRL_AC_CHROMA_18_16_4,UVLD_CTRL_AC_CHROMA_18_16_5,UVLD_CTRL_AC_CHROMA_18_16_6,UVLD_CTRL_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CTRL_AC_LUMA_15_13,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_15_13_0,UVLD_CTRL_AC_LUMA_15_13_1,UVLD_CTRL_AC_LUMA_15_13_2,UVLD_CTRL_AC_LUMA_15_13_3,UVLD_CTRL_AC_LUMA_15_13_4,UVLD_CTRL_AC_LUMA_15_13_5,UVLD_CTRL_AC_LUMA_15_13_6,UVLD_CTRL_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_AC_LUMA_12_3,Indicating start address of control table for UVLD AC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CTRL_AC_LUMA_2_0,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_2_0_0,UVLD_CTRL_AC_LUMA_2_0_1,UVLD_CTRL_AC_LUMA_2_0_2,UVLD_CTRL_AC_LUMA_2_0_3,UVLD_CTRL_AC_LUMA_2_0_4,UVLD_CTRL_AC_LUMA_2_0_5,UVLD_CTRL_AC_LUMA_2_0_6,UVLD_CTRL_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_8," hexmask.long.word 0x04 3.--15. 1. "DIRECTPT_15_3,DIRECTPTR Progressive B picture Interlace Frame B picture" group.long 0xC0++0x03 line.long 0x00 "MP2_WORK5,MP2 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "PMV6,Specifies PMV[1][0][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV5,Specifies PMV[1][0][0] described in MPEG-2 standard section 7.6.3" group.long 0xC0++0x03 line.long 0x00 "MP4_WORK5,MP4 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "MVP11,MVP[1][1]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP10,MVP[1][0]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" group.long 0xC0++0x03 line.long 0x00 "MVD_CUR_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_CUR_1_15_13,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 19.--28. 1. "DP_MVD_CUR_1_12_3,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_CUR_1_2_0,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 13.--15. "DP_MVD_CUR_0_15_13,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_CUR_0_12_3,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" newline rbitfld.long 0x00 0.--2. "DP_MVD_CUR_0_2_0,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC0++0x07 line.long 0x00 "UVLD_CODE_TBPTR_DC,Pointers to code table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_DC_CHROMA31_29,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA31_29_0,UVLD_CODE_DC_CHROMA31_29_1,UVLD_CODE_DC_CHROMA31_29_2,UVLD_CODE_DC_CHROMA31_29_3,UVLD_CODE_DC_CHROMA31_29_4,UVLD_CODE_DC_CHROMA31_29_5,UVLD_CODE_DC_CHROMA31_29_6,UVLD_CODE_DC_CHROMA31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_DC_CHROMA_28_19,Indicating start address of code table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_DC_CHROMA_18_16,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA_18_16_0,UVLD_CODE_DC_CHROMA_18_16_1,UVLD_CODE_DC_CHROMA_18_16_2,UVLD_CODE_DC_CHROMA_18_16_3,UVLD_CODE_DC_CHROMA_18_16_4,UVLD_CODE_DC_CHROMA_18_16_5,UVLD_CODE_DC_CHROMA_18_16_6,UVLD_CODE_DC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CODE_DC_LUMA_15_13,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_15_13_0,UVLD_CODE_DC_LUMA_15_13_1,UVLD_CODE_DC_LUMA_15_13_2,UVLD_CODE_DC_LUMA_15_13_3,UVLD_CODE_DC_LUMA_15_13_4,UVLD_CODE_DC_LUMA_15_13_5,UVLD_CODE_DC_LUMA_15_13_6,UVLD_CODE_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_DC_LUMA_12_3,Indicating start address of code table for UVLD DC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CODE_DC_LUMA_2_0,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_2_0_0,UVLD_CODE_DC_LUMA_2_0_1,UVLD_CODE_DC_LUMA_2_0_2,UVLD_CODE_DC_LUMA_2_0_3,UVLD_CODE_DC_LUMA_2_0_4,UVLD_CODE_DC_LUMA_2_0_5,UVLD_CODE_DC_LUMA_2_0_6,UVLD_CODE_DC_LUMA_2_0_7" line.long 0x04 "CDC_VP_9," hexmask.long.word 0x04 3.--15. 1. "FIELDTXPTR_31_3,FIELDTXPTR Interlace Frame I picture" group.long 0xC4++0x03 line.long 0x00 "MP2_WORK6,MP2 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "PMV8,Specifies PMV[1][1][1] described in MPEG-2 standard section 7.6.3" newline hexmask.long.word 0x00 0.--15. 1. "PMV7,Specifies PMV[1][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xC4++0x03 line.long 0x00 "MP4_WORK6,MP4 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "MVP21,MVP[2][1]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP20,MVP[2][0]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" group.long 0xC4++0x03 line.long 0x00 "MVD_LFT_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_LFT_1_15_13,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 19.--28. 1. "DP_MVD_LFT_1_12_3,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_LFT_1_2_0,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 13.--15. "DP_MVD_LFT_0_15_13,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_LFT_0_12_3,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" newline rbitfld.long 0x00 0.--2. "DP_MVD_LFT_0_2_0,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC4++0x07 line.long 0x00 "UVLD_CODE_TBPTR_AC,Pointers to code table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_AC_CHROMA_31_29,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_31_29_0,UVLD_CODE_AC_CHROMA_31_29_1,UVLD_CODE_AC_CHROMA_31_29_2,UVLD_CODE_AC_CHROMA_31_29_3,UVLD_CODE_AC_CHROMA_31_29_4,UVLD_CODE_AC_CHROMA_31_29_5,UVLD_CODE_AC_CHROMA_31_29_6,UVLD_CODE_AC_CHROMA_31_29_7" newline hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_AC_CHROMA_28_19,Indicating start address of code table for UVLD AC Chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_AC_CHROMA_18_16,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_18_16_0,UVLD_CODE_AC_CHROMA_18_16_1,UVLD_CODE_AC_CHROMA_18_16_2,UVLD_CODE_AC_CHROMA_18_16_3,UVLD_CODE_AC_CHROMA_18_16_4,UVLD_CODE_AC_CHROMA_18_16_5,UVLD_CODE_AC_CHROMA_18_16_6,UVLD_CODE_AC_CHROMA_18_16_7" newline rbitfld.long 0x00 13.--15. "UVLD_CODE_AC_LUMA_15_13,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_15_13_0,UVLD_CODE_AC_LUMA_15_13_1,UVLD_CODE_AC_LUMA_15_13_2,UVLD_CODE_AC_LUMA_15_13_3,UVLD_CODE_AC_LUMA_15_13_4,UVLD_CODE_AC_LUMA_15_13_5,UVLD_CODE_AC_LUMA_15_13_6,UVLD_CODE_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_AC_LUMA_12_3,Indicating start address of code table for UVLD AC-luma" newline rbitfld.long 0x00 0.--2. "UVLD_CODE_AC_LUMA_2_0,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_2_0_0,UVLD_CODE_AC_LUMA_2_0_1,UVLD_CODE_AC_LUMA_2_0_2,UVLD_CODE_AC_LUMA_2_0_3,UVLD_CODE_AC_LUMA_2_0_4,UVLD_CODE_AC_LUMA_2_0_5,UVLD_CODE_AC_LUMA_2_0_6,UVLD_CODE_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_A," hexmask.long.word 0x04 3.--15. 1. "FWDBITPTR_15_3,FWDBITPTR Interlace Field B picture" group.long 0xC8++0x03 line.long 0x00 "MP4_WORK7,MP4 WORK7 register" hexmask.long.word 0x00 16.--31. 1. "MVP31,MVP[3][1]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" newline hexmask.long.word 0x00 0.--15. 1. "MVP30,MVP[3][0]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" group.long 0xC8++0x07 line.long 0x00 "UVLD_TBL_TYPE,Setting for UVLD code table" bitfld.long 0x00 29. "UVLD_AC_CHROMA,Indicating type of UVLD code table for AC-chroma data" "zero-leading,one-leading" newline bitfld.long 0x00 24.--28. "UVLD_AC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-chroma" "UVLD_AC_CHROMA_LEN_MAX_0,UVLD_AC_CHROMA_LEN_MAX_1,UVLD_AC_CHROMA_LEN_MAX_2,UVLD_AC_CHROMA_LEN_MAX_3,UVLD_AC_CHROMA_LEN_MAX_4,UVLD_AC_CHROMA_LEN_MAX_5,UVLD_AC_CHROMA_LEN_MAX_6,UVLD_AC_CHROMA_LEN_MAX_7,UVLD_AC_CHROMA_LEN_MAX_8,UVLD_AC_CHROMA_LEN_MAX_9,UVLD_AC_CHROMA_LEN_MAX_10,UVLD_AC_CHROMA_LEN_MAX_11,UVLD_AC_CHROMA_LEN_MAX_12,UVLD_AC_CHROMA_LEN_MAX_13,UVLD_AC_CHROMA_LEN_MAX_14,UVLD_AC_CHROMA_LEN_MAX_15,UVLD_AC_CHROMA_LEN_MAX_16,UVLD_AC_CHROMA_LEN_MAX_17,UVLD_AC_CHROMA_LEN_MAX_18,UVLD_AC_CHROMA_LEN_MAX_19,UVLD_AC_CHROMA_LEN_MAX_20,UVLD_AC_CHROMA_LEN_MAX_21,UVLD_AC_CHROMA_LEN_MAX_22,UVLD_AC_CHROMA_LEN_MAX_23,UVLD_AC_CHROMA_LEN_MAX_24,UVLD_AC_CHROMA_LEN_MAX_25,UVLD_AC_CHROMA_LEN_MAX_26,UVLD_AC_CHROMA_LEN_MAX_27,UVLD_AC_CHROMA_LEN_MAX_28,UVLD_AC_CHROMA_LEN_MAX_29,UVLD_AC_CHROMA_LEN_MAX_30,UVLD_AC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 21. "UVLD_AC_LUMA,Indicating type of UVLD code table for AC-luma data" "zero-leading,one-leading" newline bitfld.long 0x00 16.--20. "UVLD_AC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-luma" "UVLD_AC_LUMA_LEN_MAX_0,UVLD_AC_LUMA_LEN_MAX_1,UVLD_AC_LUMA_LEN_MAX_2,UVLD_AC_LUMA_LEN_MAX_3,UVLD_AC_LUMA_LEN_MAX_4,UVLD_AC_LUMA_LEN_MAX_5,UVLD_AC_LUMA_LEN_MAX_6,UVLD_AC_LUMA_LEN_MAX_7,UVLD_AC_LUMA_LEN_MAX_8,UVLD_AC_LUMA_LEN_MAX_9,UVLD_AC_LUMA_LEN_MAX_10,UVLD_AC_LUMA_LEN_MAX_11,UVLD_AC_LUMA_LEN_MAX_12,UVLD_AC_LUMA_LEN_MAX_13,UVLD_AC_LUMA_LEN_MAX_14,UVLD_AC_LUMA_LEN_MAX_15,UVLD_AC_LUMA_LEN_MAX_16,UVLD_AC_LUMA_LEN_MAX_17,UVLD_AC_LUMA_LEN_MAX_18,UVLD_AC_LUMA_LEN_MAX_19,UVLD_AC_LUMA_LEN_MAX_20,UVLD_AC_LUMA_LEN_MAX_21,UVLD_AC_LUMA_LEN_MAX_22,UVLD_AC_LUMA_LEN_MAX_23,UVLD_AC_LUMA_LEN_MAX_24,UVLD_AC_LUMA_LEN_MAX_25,UVLD_AC_LUMA_LEN_MAX_26,UVLD_AC_LUMA_LEN_MAX_27,UVLD_AC_LUMA_LEN_MAX_28,UVLD_AC_LUMA_LEN_MAX_29,UVLD_AC_LUMA_LEN_MAX_30,UVLD_AC_LUMA_LEN_MAX_31" newline bitfld.long 0x00 13. "UVLD_DC_CHROMA,Indicating type of UVLD code table for DC-chroma data" "zero-leading,one-leading" newline bitfld.long 0x00 8.--12. "UVLD_DC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-chroma" "UVLD_DC_CHROMA_LEN_MAX_0,UVLD_DC_CHROMA_LEN_MAX_1,UVLD_DC_CHROMA_LEN_MAX_2,UVLD_DC_CHROMA_LEN_MAX_3,UVLD_DC_CHROMA_LEN_MAX_4,UVLD_DC_CHROMA_LEN_MAX_5,UVLD_DC_CHROMA_LEN_MAX_6,UVLD_DC_CHROMA_LEN_MAX_7,UVLD_DC_CHROMA_LEN_MAX_8,UVLD_DC_CHROMA_LEN_MAX_9,UVLD_DC_CHROMA_LEN_MAX_10,UVLD_DC_CHROMA_LEN_MAX_11,UVLD_DC_CHROMA_LEN_MAX_12,UVLD_DC_CHROMA_LEN_MAX_13,UVLD_DC_CHROMA_LEN_MAX_14,UVLD_DC_CHROMA_LEN_MAX_15,UVLD_DC_CHROMA_LEN_MAX_16,UVLD_DC_CHROMA_LEN_MAX_17,UVLD_DC_CHROMA_LEN_MAX_18,UVLD_DC_CHROMA_LEN_MAX_19,UVLD_DC_CHROMA_LEN_MAX_20,UVLD_DC_CHROMA_LEN_MAX_21,UVLD_DC_CHROMA_LEN_MAX_22,UVLD_DC_CHROMA_LEN_MAX_23,UVLD_DC_CHROMA_LEN_MAX_24,UVLD_DC_CHROMA_LEN_MAX_25,UVLD_DC_CHROMA_LEN_MAX_26,UVLD_DC_CHROMA_LEN_MAX_27,UVLD_DC_CHROMA_LEN_MAX_28,UVLD_DC_CHROMA_LEN_MAX_29,UVLD_DC_CHROMA_LEN_MAX_30,UVLD_DC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 5. "UVLD_DC_LUMA,Indicating type of UVLD code table for DC-luma data" "zero-leading,one-leading" newline bitfld.long 0x00 0.--4. "UVLD_DC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-luma" "UVLD_DC_LUMA_LEN_MAX_0,UVLD_DC_LUMA_LEN_MAX_1,UVLD_DC_LUMA_LEN_MAX_2,UVLD_DC_LUMA_LEN_MAX_3,UVLD_DC_LUMA_LEN_MAX_4,UVLD_DC_LUMA_LEN_MAX_5,UVLD_DC_LUMA_LEN_MAX_6,UVLD_DC_LUMA_LEN_MAX_7,UVLD_DC_LUMA_LEN_MAX_8,UVLD_DC_LUMA_LEN_MAX_9,UVLD_DC_LUMA_LEN_MAX_10,UVLD_DC_LUMA_LEN_MAX_11,UVLD_DC_LUMA_LEN_MAX_12,UVLD_DC_LUMA_LEN_MAX_13,UVLD_DC_LUMA_LEN_MAX_14,UVLD_DC_LUMA_LEN_MAX_15,UVLD_DC_LUMA_LEN_MAX_16,UVLD_DC_LUMA_LEN_MAX_17,UVLD_DC_LUMA_LEN_MAX_18,UVLD_DC_LUMA_LEN_MAX_19,UVLD_DC_LUMA_LEN_MAX_20,UVLD_DC_LUMA_LEN_MAX_21,UVLD_DC_LUMA_LEN_MAX_22,UVLD_DC_LUMA_LEN_MAX_23,UVLD_DC_LUMA_LEN_MAX_24,UVLD_DC_LUMA_LEN_MAX_25,UVLD_DC_LUMA_LEN_MAX_26,UVLD_DC_LUMA_LEN_MAX_27,UVLD_DC_LUMA_LEN_MAX_28,UVLD_DC_LUMA_LEN_MAX_29,UVLD_DC_LUMA_LEN_MAX_30,UVLD_DC_LUMA_LEN_MAX_31" line.long 0x04 "DC_PRED_CHROMA,JPEG DC PRED Chroma register - TI internal" hexmask.long.word 0x04 16.--31. 1. "DC_PRED_CB,Chrominance (Cb) DC prediction value is stored in register" newline hexmask.long.word 0x04 0.--15. 1. "DC_PRED_CR,Chrominance (Cr) DC prediction value is stored in register" repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0xF0)++0x03 line.long 0x00 "CMDP_GPR$1,Command Processor General Purpose Register 0" repeat.end width 0x0B tree.end tree.end sif (cpuis("TDA2PXIVA*")) tree "IVA_Imaging_Controller" tree "ICONT1_CFG_ICONT" base ad:0xF0000 rgroup.long 0x00++0x07 line.long 0x00 "ICONT_REVISION,ICONT Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ICONT_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 20.--23. "NB_LCH,Number of Data Mover Logical channel" "NB_LCH_0,NB_LCH_1,NB_LCH_2,NB_LCH_3,NB_LCH_4,NB_LCH_5,NB_LCH_6,NB_LCH_7,NB_LCH_8,NB_LCH_9,NB_LCH_10,NB_LCH_11,NB_LCH_12,NB_LCH_13,NB_LCH_14,NB_LCH_15" bitfld.long 0x04 16.--19. "NB_TASK,Number of SYNCBOX tasks" "NB_TASK_0,NB_TASK_1,NB_TASK_2,NB_TASK_3,NB_TASK_4,NB_TASK_5,NB_TASK_6,NB_TASK_7,NB_TASK_8,NB_TASK_9,NB_TASK_10,NB_TASK_11,NB_TASK_12,NB_TASK_13,NB_TASK_14,NB_TASK_15" hexmask.long.byte 0x04 8.--15. 1. "DTCM_SIZE,Size of DTCM (in kBytes)" hexmask.long.byte 0x04 0.--7. 1. "ICTM_SIZE,Size of ITCM (in kBytes)" group.long 0x10++0x03 line.long 0x00 "ICONT_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,?" width 0x0B tree.end tree "ICONT1_CFG_L3_MAINInterconnect" base ad:0x5A070000 rgroup.long 0x00++0x07 line.long 0x00 "ICONT_REVISION,ICONT Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ICONT_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 20.--23. "NB_LCH,Number of Data Mover Logical channel" "NB_LCH_0,NB_LCH_1,NB_LCH_2,NB_LCH_3,NB_LCH_4,NB_LCH_5,NB_LCH_6,NB_LCH_7,NB_LCH_8,NB_LCH_9,NB_LCH_10,NB_LCH_11,NB_LCH_12,NB_LCH_13,NB_LCH_14,NB_LCH_15" bitfld.long 0x04 16.--19. "NB_TASK,Number of SYNCBOX tasks" "NB_TASK_0,NB_TASK_1,NB_TASK_2,NB_TASK_3,NB_TASK_4,NB_TASK_5,NB_TASK_6,NB_TASK_7,NB_TASK_8,NB_TASK_9,NB_TASK_10,NB_TASK_11,NB_TASK_12,NB_TASK_13,NB_TASK_14,NB_TASK_15" hexmask.long.byte 0x04 8.--15. 1. "DTCM_SIZE,Size of DTCM (in kBytes)" hexmask.long.byte 0x04 0.--7. 1. "ICTM_SIZE,Size of ITCM (in kBytes)" group.long 0x10++0x03 line.long 0x00 "ICONT_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,?" width 0x0B tree.end tree "ICONT2_CFG_ICONT" base ad:0xF1000 rgroup.long 0x00++0x07 line.long 0x00 "ICONT_REVISION,ICONT Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ICONT_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 20.--23. "NB_LCH,Number of Data Mover Logical channel" "NB_LCH_0,NB_LCH_1,NB_LCH_2,NB_LCH_3,NB_LCH_4,NB_LCH_5,NB_LCH_6,NB_LCH_7,NB_LCH_8,NB_LCH_9,NB_LCH_10,NB_LCH_11,NB_LCH_12,NB_LCH_13,NB_LCH_14,NB_LCH_15" bitfld.long 0x04 16.--19. "NB_TASK,Number of SYNCBOX tasks" "NB_TASK_0,NB_TASK_1,NB_TASK_2,NB_TASK_3,NB_TASK_4,NB_TASK_5,NB_TASK_6,NB_TASK_7,NB_TASK_8,NB_TASK_9,NB_TASK_10,NB_TASK_11,NB_TASK_12,NB_TASK_13,NB_TASK_14,NB_TASK_15" hexmask.long.byte 0x04 8.--15. 1. "DTCM_SIZE,Size of DTCM (in kBytes)" hexmask.long.byte 0x04 0.--7. 1. "ICTM_SIZE,Size of ITCM (in kBytes)" group.long 0x10++0x03 line.long 0x00 "ICONT_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,?" width 0x0B tree.end tree "ICONT2_CFG_L3_MAINInterconnect" base ad:0x5A071000 rgroup.long 0x00++0x07 line.long 0x00 "ICONT_REVISION,ICONT Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "ICONT_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 20.--23. "NB_LCH,Number of Data Mover Logical channel" "NB_LCH_0,NB_LCH_1,NB_LCH_2,NB_LCH_3,NB_LCH_4,NB_LCH_5,NB_LCH_6,NB_LCH_7,NB_LCH_8,NB_LCH_9,NB_LCH_10,NB_LCH_11,NB_LCH_12,NB_LCH_13,NB_LCH_14,NB_LCH_15" bitfld.long 0x04 16.--19. "NB_TASK,Number of SYNCBOX tasks" "NB_TASK_0,NB_TASK_1,NB_TASK_2,NB_TASK_3,NB_TASK_4,NB_TASK_5,NB_TASK_6,NB_TASK_7,NB_TASK_8,NB_TASK_9,NB_TASK_10,NB_TASK_11,NB_TASK_12,NB_TASK_13,NB_TASK_14,NB_TASK_15" hexmask.long.byte 0x04 8.--15. 1. "DTCM_SIZE,Size of DTCM (in kBytes)" hexmask.long.byte 0x04 0.--7. 1. "ICTM_SIZE,Size of ITCM (in kBytes)" group.long 0x10++0x03 line.long 0x00 "ICONT_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,?" width 0x0B tree.end tree "ICONT1_DM_ICONT" base ad:0xF0800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT1_DM_ICONTSelf_Access" base ad:0xF2800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT1_DM_L3_MAINInterconnect" base ad:0x5A070800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT2_DM_ICONT" base ad:0xF1800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT2_DM_ICONTSelf_Access" base ad:0xF3800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT2_DM_L3_MAINInterconnect" base ad:0x5A071800 tree "Channel_0" group.long 0x48++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_0,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x44++0x03 line.long 0x00 "ICONT_DMDESTADD_i_0,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x40++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_0,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x4C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_0,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_1" group.long 0x68++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_1,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x64++0x03 line.long 0x00 "ICONT_DMDESTADD_i_1,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x60++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_1,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x6C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_1,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_2" group.long 0x88++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_2,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0x84++0x03 line.long 0x00 "ICONT_DMDESTADD_i_2,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0x80++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_2,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0x8C++0x03 line.long 0x00 "ICONT_DMSTATUS_i_2,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end tree "Channel_3" group.long 0xA8++0x03 line.long 0x00 "ICONT_DMCONTEXT_i_3,Data Mover Context n" bitfld.long 0x00 20. "END_TYPE," "0,1" bitfld.long 0x00 19. "START_TYPE," "0,1" bitfld.long 0x00 16.--18. "CMD_TYPE,Type of transfer" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3,CMD_TYPE_4,CMD_TYPE_5,CMD_TYPE_6,CMD_TYPE_7" hexmask.long.word 0x00 0.--15. 1. "NB_BYTE,Number of bytes to transfer (must be a multiple of 128b)" group.long 0xA4++0x03 line.long 0x00 "ICONT_DMDESTADD_i_3,Data mover destination address for context n (byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "DESTADDR,Destination address of transfer" group.long 0xA0++0x03 line.long 0x00 "ICONT_DMSOURCEADD_i_3,Data mover source address for context n (Byte address. must be aligned on 128-bit boundary)" hexmask.long.tbyte 0x00 0.--17. 1. "SOURCEADDR,Source address of transfer" rgroup.long 0xAC++0x03 line.long 0x00 "ICONT_DMSTATUS_i_3,Data Mover status register for context n" bitfld.long 0x00 0.--1. "STATUS," "?,LCHn is in WAIT FOR HW EVENT state,LCHn is in either QUEUED state in ON GOING state..,Reserved" tree.end group.long 0x20++0x03 line.long 0x00 "ICONT_DM_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" group.long 0x30++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_CLR,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bitfiled: Read" "No action Write,Disable interrupt,?..." group.long 0x2C++0x03 line.long 0x00 "ICONT_DM_IRQENABLE_SET,Per-event interrupt enable bit vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Enable for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Enable interrupt,?..." group.long 0x28++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS,Per-event 'enabled' interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Clearable enabled status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Clear (raw) event,?..." group.long 0x24++0x03 line.long 0x00 "ICONT_DM_IRQSTATUS_RAW,Per-event raw interrupt status vector (DM interrupt)" bitfld.long 0x00 0.--3. "LCHN_0,Settable raw status for Logical Channel n to 0 (n=NB_DM_LCH-1) For each bit of the bit field: Read" "No action Write,Set event (debug),?..." width 0x0B tree.end tree "ICONT1_IRQ_ICONT" base ad:0xF0400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT1_IRQ_ICONTSelf_Access" base ad:0xF2400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT1_IRQ_L3_MAINInterconnect" base ad:0x5A070400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT2_IRQ_ICONT" base ad:0xF1400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT2_IRQ_ICONTSelf_Access" base ad:0xF3400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT2_IRQ_L3_MAINInterconnect" base ad:0x5A071400 group.long 0x20++0x13 line.long 0x00 "ICONT_IRQ_EOI,End Of Interrupt register - Interrupt handler" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_IRQSTATUS_RAW,Per-event raw interrupt status vector (interrupt handler)" line.long 0x08 "ICONT_IRQSTATUS,Per-event 'enabled' interrupt status vector (interrupt handler)" line.long 0x0C "ICONT_IRQENABLE_SET,Per-event interrupt enable bit vector (interrupt handler)" line.long 0x10 "ICONT_IRQENABLE_CLR,Per-event interrupt enable bit vector (interrupt handler)" group.long 0x40++0x13 line.long 0x00 "ICONT_SWI_EOI,End Of Interrupt register - Software interrupt" bitfld.long 0x00 0. "LINE_NUMBER,End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SWISTATUS_RAW,Per-event raw interrupt status vector (software interrupt)" bitfld.long 0x04 0. "SWI_IRQ,Settable raw status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x08 "ICONT_SWISTATUS,Per-event 'enabled' interrupt status vector (software interrupt)" bitfld.long 0x08 0. "SWI_IRQ,Clearable enabled status for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x0C "ICONT_SWIENABLE_SET,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x0C 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" line.long 0x10 "ICONT_SWIENABLE_CLR,Per-event interrupt enable bit vector (software interrupt)" bitfld.long 0x10 0. "SWI_IRQ,Enable for software interrupt event" "SWI_IRQ_0_r,SWI_IRQ_1_w" group.long 0x60++0x0B line.long 0x00 "ICONT_SYNCMASK,This register allow to mask each input of Sync logic" line.long 0x04 "ICONT_SYNCCLR,Clear Interrupt line This register is used to clear status bit of interrupt n" line.long 0x08 "ICONT_SYNCSTATUS,Status of masked Sync interrupt input n" rgroup.long 0x70++0x03 line.long 0x00 "ICONT_SYNCRAWSTATUS,Status of Sync interrupt n input before mask" group.long 0x80++0x13 line.long 0x00 "ICONT_SYNC_IRQ_EOI,End Of Interrupt - SYNC interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,?" line.long 0x04 "ICONT_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYNC_IRQ,Settable raw status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x08 "ICONT_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x08 0. "SYNC_IRQ,Clearable enabled status for outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x0C "ICONT_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" line.long 0x10 "ICONT_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYNC_IRQ,Enable for Outgoing Sync IRQ event" "SYNC_IRQ_0_r,SYNC_IRQ_1_w" width 0x0B tree.end tree "ICONT1_SBH_ICONT" base ad:0xF0C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree "ICONT1_SBH_ICONTSelf_Access" base ad:0xF2C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree "ICONT1_SBH_L3_MAINInterconnect" base ad:0x5A070C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree "ICONT2_SBH_ICONT" base ad:0xF1C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree "ICONT2_SBH_ICONTSelf_Access" base ad:0xF3C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree "ICONT2_SBH_L3_MAINInterconnect" base ad:0x5A071C00 tree "Channel_0" group.long 0x90++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_0,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB0++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_0,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_0,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_1" group.long 0x94++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_1,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB4++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_1,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_1,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_2" group.long 0x98++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_2,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xB8++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_2,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x03 line.long 0x00 "ICONT_SBH_TCCR_i_2,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end tree "Channel_3" group.long 0x9C++0x03 line.long 0x00 "ICONT_SBH_COUNTER_j_3,Initialization value of SYNCBOX Handler Counter n" hexmask.long.byte 0x00 0.--7. 1. "COUNT,Value to preload on counter" group.long 0xBC++0x03 line.long 0x00 "ICONT_SBH_DMLCH_CFG_j_3,This register defines which DMA_IVA group is associated to the Data Mover Logical Chanel n" bitfld.long 0x00 0.--4. "VDMA_GROUP_ID,DMA_IVA group identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C++0x0B line.long 0x00 "ICONT_SBH_TCCR_i_3,Task n Configuration Control Register" bitfld.long 0x00 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x00 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x00 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x00 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x00 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x04 "ICONT_SBH_TCCR_i_4,Task n Configuration Control Register" bitfld.long 0x04 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x04 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x04 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x04 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x04 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" line.long 0x08 "ICONT_SBH_TCCR_i_5,Task n Configuration Control Register" bitfld.long 0x08 24.--25. "COUNTER_ID,Counter Identifier" "0,1,2,3" bitfld.long 0x08 22. "COUNTER_EN,Counter Enable Bit" "0,1" hexmask.long.byte 0x08 13.--20. 1. "VDMA_G_SELECT,DMA_IVA Group Selector" bitfld.long 0x08 10.--11. "VDMA_SG_SELECT,DMA_IVA Super Group Enable" "VDMA_SG_SELECT_0,VDMA_SG_SELECT_1,VDMA_SG_SELECT_2,VDMA_SG_SELECT_3" bitfld.long 0x08 4.--7. "DM_LCHN_0_EN,Enable Data Mover Logical channel n to 0 (n=NB_DM_LCH-1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--2. "TASK_TYPE,Task Type" "TASK_TYPE_0,TASK_TYPE_1,TASK_TYPE_2,TASK_TYPE_3,TASK_TYPE_4,TASK_TYPE_5,TASK_TYPE_6,TASK_TYPE_7" tree.end group.long 0x08++0x03 line.long 0x00 "ICONT_SBH_ACK,Acknowledge Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x04++0x03 line.long 0x00 "ICONT_SBH_ATLR,Activation Task List register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0xD4++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_END,SYNCBOX Bypass mode DMA_IVA group End register status" group.long 0xD0++0x03 line.long 0x00 "ICONT_SBH_BYP_VDMAG_START,SYNCBOX Bypass mode DMA_IVA group Start register" group.long 0x00++0x03 line.long 0x00 "ICONT_SBH_CTRL,SYNCBOX Handler control register" bitfld.long 0x00 0. "BYPASS,Control SYNCBOX bypass mode" "BYPASS_0,BYPASS_1" group.long 0x0C++0x03 line.long 0x00 "ICONT_SBH_EOT,End Of Task register" bitfld.long 0x00 0.--5. "TX_0,Task x to 0 (x=SYNCBOX_NB_TASK-1)" "TX_0_0,TX_0_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x20++0x03 line.long 0x00 "ICONT_SBH_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x30++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x40++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x2C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,enable for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x3C++0x03 line.long 0x00 "ICONT_SBH_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,enable for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x28++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,clearable enabled status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x38++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1 (error)" bitfld.long 0x00 0. "SBH_ERR,clearable enabled status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" group.long 0x24++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line #0 (end of transfer)" bitfld.long 0x00 0. "VDMAG_END,settable raw status for end of transfer interrupt event" "VDMAG_END_0_r,VDMAG_END_1_w" group.long 0x34++0x03 line.long 0x00 "ICONT_SBH_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line #0 (error)" bitfld.long 0x00 0. "SBH_ERR,settable raw status for SBH error event" "SBH_ERR_0_r,SBH_ERR_1_w" width 0x0B tree.end tree.end endif tree "IVA_Intra_Prediction_Estimation" sif (cpuis("TDA2PXIVA*")) tree "IPE3_BFSW_ICONT" base ad:0xD8A00 group.long 0x00++0x07 line.long 0x00 "IPE3_BFSW_VIEWMODE," bitfld.long 0x00 0. "VIEW_IPORGBUF,View mode selection for iporgbuf" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "IPE3_BFSW_MSTID,Master ID 1 register" bitfld.long 0x04 1. "MST_IPORGBUF_B,Master selection for iporgbuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA This bit has no.." bitfld.long 0x04 0. "MST_IPORGBUF_A,Master selection for iporgbuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" width 0x0B tree.end endif tree "IPE3_BFSW_L3_MAINInterconnect" base ad:0x5A058A00 group.long 0x00++0x07 line.long 0x00 "IPE3_BFSW_VIEWMODE," bitfld.long 0x00 0. "VIEW_IPORGBUF,View mode selection for iporgbuf" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "IPE3_BFSW_MSTID,Master ID 1 register" bitfld.long 0x04 1. "MST_IPORGBUF_B,Master selection for iporgbuf B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA This bit has no.." bitfld.long 0x04 0. "MST_IPORGBUF_A,Master selection for iporgbuf A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" width 0x0B tree.end tree "IPE3_IPGW_ICONT" base ad:0xD8C00 group.long 0x08++0x07 line.long 0x00 "IPE3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Initiate software reset" line.long 0x04 "IPE3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "IPE3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x04 "IPE3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x08 "IPE3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x0C "IPE3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" group.long 0x30++0x0F line.long 0x00 "IPE3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "IPE3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "IPE3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "IPE3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "IPE3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "IPE3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "IPE3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x0C "IPE3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "IPE3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "IPE3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "IPE3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "IPE3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line 2" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "IPE3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,Auto clear enable for line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,Auto clear enable for line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,Auto clear enable for line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,Auto clear enable for line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end tree "IPE3_IPGW_L3_MAINInterconnect" base ad:0x5A058C00 group.long 0x08++0x07 line.long 0x00 "IPE3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Initiate software reset" line.long 0x04 "IPE3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "IPE3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x04 "IPE3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x08 "IPE3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" line.long 0x0C "IPE3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Programmable raw status for event 0" "No event pending,Reserved" group.long 0x30++0x0F line.long 0x00 "IPE3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "IPE3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "IPE3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "IPE3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "IPE3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "IPE3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "IPE3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x0C "IPE3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "IPE3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "IPE3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "IPE3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "IPE3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line 2" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "IPE3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,Auto clear enable for line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,Auto clear enable for line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,Auto clear enable for line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,Auto clear enable for line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end tree "IPE3_LSE_ICONT" base ad:0xD8B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE processes for the slice boundary after..,int_eos is passed through to SYNCBOX_IPE3.." bitfld.long 0x00 9.--11. "ERR,Error status bit [11]: DMA IP_CORE side [10]: DMA SL2 side [9]: CFG IP_CORE side" "Sresp is not ERR,Sresp is ERR,?..." newline rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to recognize the prologue (first MB): -Token status signal -Token start/end signal -DMA pointer Writing 0 is ignored" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single-step mode" "Normal mode,Enable Single-step mode" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "Enable internal BFSW change (default) Then LSE..,Disable BFSW change (for host to control BFSW.." newline bitfld.long 0x00 4. "CSB,Command status bit" "LSE command is defined,LSE command is undefined" bitfld.long 0x00 3. "LD_GO,Execute LOAD task in bypass mode" "Idle Writing 0 is ignored,Execute LD task" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task in bypass mode" "Idle Writing 0 is ignored,Execute Comp task" bitfld.long 0x00 1. "ST_GO,Execute Store task in bypass mode" "Idle Writing 0 is ignored,Execute Store task" newline bitfld.long 0x00 0. "SB_BYPS,Sync-Box bypass mode" "LSE functions in normal SYNCBOX_IPE3 mode and..,LSE functions in SYNCBOX_IPE3 bypass mode and.." line.long 0x04 "LSE_PARAM,Parameter address for SB bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_ LD_BYPS,Bypass mode only" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ ST_BYPS,Bypass mode only" width 0x0B tree.end tree "IPE3_LSE_L3_MAINInterconnect" base ad:0x5A058B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE processes for the slice boundary after..,int_eos is passed through to SYNCBOX_IPE3.." bitfld.long 0x00 9.--11. "ERR,Error status bit [11]: DMA IP_CORE side [10]: DMA SL2 side [9]: CFG IP_CORE side" "Sresp is not ERR,Sresp is ERR,?..." newline rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to recognize the prologue (first MB): -Token status signal -Token start/end signal -DMA pointer Writing 0 is ignored" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single-step mode" "Normal mode,Enable Single-step mode" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "Enable internal BFSW change (default) Then LSE..,Disable BFSW change (for host to control BFSW.." newline bitfld.long 0x00 4. "CSB,Command status bit" "LSE command is defined,LSE command is undefined" bitfld.long 0x00 3. "LD_GO,Execute LOAD task in bypass mode" "Idle Writing 0 is ignored,Execute LD task" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task in bypass mode" "Idle Writing 0 is ignored,Execute Comp task" bitfld.long 0x00 1. "ST_GO,Execute Store task in bypass mode" "Idle Writing 0 is ignored,Execute Store task" newline bitfld.long 0x00 0. "SB_BYPS,Sync-Box bypass mode" "LSE functions in normal SYNCBOX_IPE3 mode and..,LSE functions in SYNCBOX_IPE3 bypass mode and.." line.long 0x04 "LSE_PARAM,Parameter address for SB bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_ LD_BYPS,Bypass mode only" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ ST_BYPS,Bypass mode only" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "IPE3_MMR_ICONT" base ad:0xD8800 rgroup.long 0x00++0x53 line.long 0x00 "IPE3_PID,Peripheral ID register" line.long 0x04 "IPE3_COUNT,IPE3 cycle counter register Determines the cycle number between start of IPE3 core and end (interrupt generation)" bitfld.long 0x04 31. "CNT_EN,Counter enable" "Benchmark counter is disabled,Benchmark counter is enabled" bitfld.long 0x04 30. "CNT_RST,Counter reset" "No effect,Clear the benchmark.." hexmask.long.word 0x04 0.--15. 1. "CNT_VALUE,Current value of the benchmark counter" line.long 0x08 "IPE3_CTRL,IPE3 control register" bitfld.long 0x08 18.--19. "IPE_ADDR,Address of parameter set" "Process first MB,Process second MB,Process third MB ( full-view mode only),Process fourth MB ( full-view mode only)" bitfld.long 0x08 2. "IPE_SSM,Single-step mode" "Normal mode,Single-step mode" bitfld.long 0x08 0. "IPE_EN,IPE3 start and status Setting this bit to 1 makes IPE3 start processing" "0,1" line.long 0x0C "IPE3_NS,Horizontal noise suppression register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x0C 1. "NS1,Bottom block status for horizontal noise suppression" "Activity is not higher than H_threshold,Activity is higher than H_threshold" bitfld.long 0x0C 0. "NS0,Top block status for horizontal noise suppression" "Activity is not higher than H_threshold,Activity is higher than H_threshold" line.long 0x10 "IPE3_NA,nA mode register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x10 28.--31. "PRED_NA7,Intraprediction mode of 4 x 4 block 15 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "PRED_NA6,Intraprediction mode of 4 x 4 block 13 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "PRED_NA5,Intraprediction mode of 4 x 4 block 7 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "PRED_NA4,Intraprediction mode of 4 x 4 block 5 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "PRED_NA3,Intraprediction mode of 4 x 4 block 15 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "PRED_NA2,Intraprediction mode of 4 x 4 block 13 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "PRED_NA1,Intraprediction mode of 4 x 4 block 7 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "PRED_NA0,Intraprediction mode of 4 x 4 block 5 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "IPE3_L_LF_T0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x14 24.--31. 1. "IPE_L_LF_TOP3,Luma left sample for top MB line 3" hexmask.long.byte 0x14 16.--23. 1. "IPE_L_LF_TOP2,Luma left sample for top MB line 2" hexmask.long.byte 0x14 8.--15. 1. "IPE_L_LF_TOP1,Luma left sample for top MB line 1" newline hexmask.long.byte 0x14 0.--7. 1. "IPE_L_LF_TOP0,Luma left sample for top MB line 0" line.long 0x18 "IPE3_L_LF_T1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x18 24.--31. 1. "IPE_L_LF_TOP7,Luma left sample for top MB line 7" hexmask.long.byte 0x18 16.--23. 1. "IPE_L_LF_TOP6,Luma left sample for top MB line 6" hexmask.long.byte 0x18 8.--15. 1. "IPE_L_LF_TOP5,Luma left sample for top MB line 5" newline hexmask.long.byte 0x18 0.--7. 1. "IPE_L_LF_TOP4,Luma left sample for top MB line 4" line.long 0x1C "IPE3_L_LF_T2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x1C 24.--31. 1. "IPE_L_LF_TOP11,Luma left sample for top MB line 11" hexmask.long.byte 0x1C 16.--23. 1. "IPE_L_LF_TOP10,Luma left sample for top MB line 10" hexmask.long.byte 0x1C 8.--15. 1. "IPE_L_LF_TOP9,Luma left sample for top MB line 9 The right-most luminance pixel of top MB line 9 in the left MB" newline hexmask.long.byte 0x1C 0.--7. 1. "IPE_L_LF_TOP8,Luma left sample for top MB line 8 The right-most luminance pixel of top MB line 8 in the left MB" line.long 0x20 "IPE3_L_LF_T3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x20 24.--31. 1. "IPE_L_LF_TOP15,Luma left sample for top MB line 15" hexmask.long.byte 0x20 16.--23. 1. "IPE_L_LF_TOP14,Luma left sample for top MB line 14" hexmask.long.byte 0x20 8.--15. 1. "IPE_L_LF_TOP13,Luma left sample for top MB line 13" newline hexmask.long.byte 0x20 0.--7. 1. "IPE_L_LF_TOP12,Luma left sample for top MB line 12" line.long 0x24 "IPE3_L_LF_B0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x24 24.--31. 1. "IPE_L_LF_BOT3,Luma left sample for bottom MB line 3" hexmask.long.byte 0x24 16.--23. 1. "IPE_L_LF_BOT2,Luma left sample for bottom MB line 2" hexmask.long.byte 0x24 8.--15. 1. "IPE_L_LF_BOT1,Luma left sample for bottom MB line 1" newline hexmask.long.byte 0x24 0.--7. 1. "IPE_L_LF_BOT0,Luma left sample for bottom MB line 0" line.long 0x28 "IPE3_L_LF_B1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x28 24.--31. 1. "IPE_L_LF_BOT7,Luma left sample for bottom MB line 7" hexmask.long.byte 0x28 16.--23. 1. "IPE_L_LF_BOT6,Luma left sample for bottom MB line 6" hexmask.long.byte 0x28 8.--15. 1. "IPE_L_LF_BOT5,Luma left sample for bottom MB line 5" newline hexmask.long.byte 0x28 0.--7. 1. "IPE_L_LF_BOT4,Luma left sample for bottom MB line 4" line.long 0x2C "IPE3_L_LF_B2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x2C 24.--31. 1. "IPE_L_LF_BOT11,Luma left sample for bottom MB line 11" hexmask.long.byte 0x2C 16.--23. 1. "IPE_L_LF_BOT10,Luma left sample for bottom MB line 10" hexmask.long.byte 0x2C 8.--15. 1. "IPE_L_LF_BOT9,Luma left sample for bottom MB line 9" newline hexmask.long.byte 0x2C 0.--7. 1. "IPE_L_LF_BOT8,Luma left sample for bottom MB line 8" line.long 0x30 "IPE3_L_LF_B3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x30 24.--31. 1. "IPE_L_LF_BOT15,Luma left sample for bottom MB line 15" hexmask.long.byte 0x30 16.--23. 1. "IPE_L_LF_BOT14,Luma left sample for bottom MB line 14" hexmask.long.byte 0x30 8.--15. 1. "IPE_L_LF_BOT13,Luma left sample for bottom MB line 13" newline hexmask.long.byte 0x30 0.--7. 1. "IPE_L_LF_BOT12,Luma left sample for bottom MB line 12" line.long 0x34 "IPE3_C_LF_T0,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x34 24.--31. 1. "IPE_CR_LF_TOP1,Left Cr sample of top MB line .1 The right-most Cr pixel of top MB line 1 in the left MB" hexmask.long.byte 0x34 16.--23. 1. "IPE_CB_LF_TOP1,Left Cb sample of top MB line 1" hexmask.long.byte 0x34 8.--15. 1. "IPE_CR_LF_TOP0,Left Cr sample of top MB line 0" newline hexmask.long.byte 0x34 0.--7. 1. "IPE_CB_LF_TOP0,Left Cb sample of top MB line 0" line.long 0x38 "IPE3_C_LF_T1,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x38 24.--31. 1. "IPE_CR_LF_TOP3,Left Cr sample of top MB line 3" hexmask.long.byte 0x38 16.--23. 1. "IPE_CB_LF_TOP3,Left Cb sample of top MB line 3" hexmask.long.byte 0x38 8.--15. 1. "IPE_CR_LF_TOP2,Left Cr sample of top MB line 2" newline hexmask.long.byte 0x38 0.--7. 1. "IPE_CB_LF_TOP2,Left Cb sample of top MB line 2" line.long 0x3C "IPE3_C_LF_T2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x3C 24.--31. 1. "IPE_CR_LF_TOP5,Left Cr sample of top MB line 5" hexmask.long.byte 0x3C 16.--23. 1. "IPE_CB_LF_TOP5,Left Cb sample of top MB line 5" hexmask.long.byte 0x3C 8.--15. 1. "IPE_CR_LF_TOP4,Left Cr sample of top MB line 4" newline hexmask.long.byte 0x3C 0.--7. 1. "IPE_CB_LF_TOP4,Left Cb sample of top MB line 4" line.long 0x40 "IPE3_C_LF_T3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x40 24.--31. 1. "IPE_CR_LF_TOP7,Left Cr sample of top MB line 7" hexmask.long.byte 0x40 16.--23. 1. "IPE_CB_LF_TOP7,Left Cb sample of top MB line 7" hexmask.long.byte 0x40 8.--15. 1. "IPE_CR_LF_TOP6,Left Cr sample of top MB line 6" newline hexmask.long.byte 0x40 0.--7. 1. "IPE_CB_LF_TOP6,Left Cb sample of top MB line 6" line.long 0x44 "IPE3_C_LF_B0,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x44 24.--31. 1. "IPE_CR_LF_BOT1,Left Cr sample of bottom MB line 1" hexmask.long.byte 0x44 16.--23. 1. "IPE_CB_LF_BOT1,Left Cb sample of bottom MB line 1" hexmask.long.byte 0x44 8.--15. 1. "IPE_CR_LF_BOT0,Left Cr sample of bottom MB line 0" newline hexmask.long.byte 0x44 0.--7. 1. "IPE_CB_LF_BOT0,Left Cb sample of bottom MB line 0" line.long 0x48 "IPE3_C_LF_B1,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x48 24.--31. 1. "IPE_CR_LF_BOT3,Left Cr sample of bottom MB line 3" hexmask.long.byte 0x48 16.--23. 1. "IPE_CB_LF_BOT3,Left Cb sample of bottom MB line 3" hexmask.long.byte 0x48 8.--15. 1. "IPE_CR_LF_BOT2,Left Cr sample of bottom MB line 2" newline hexmask.long.byte 0x48 0.--7. 1. "IPE_CB_LF_BOT2,Left Cb sample of bottom MB line 2" line.long 0x4C "IPE3_C_LF_B2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x4C 24.--31. 1. "IPE_CR_LF_BOT5,Left Cr sample of bottom MB line 5" hexmask.long.byte 0x4C 16.--23. 1. "IPE_CB_LF_BOT5,Left Cb sample of bottom MB line 5" hexmask.long.byte 0x4C 8.--15. 1. "IPE_CR_LF_BOT4,Left Cr sample of bottom MB line 4" newline hexmask.long.byte 0x4C 0.--7. 1. "IPE_CB_LF_BOT4,Left Cb sample of bottom MB line 4" line.long 0x50 "IPE3_C_LF_B3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x50 24.--31. 1. "IPE_CR_LF_BOT7,Left Cr sample of bottom MB line 7" hexmask.long.byte 0x50 16.--23. 1. "IPE_CB_LF_BOT7,Left Cb sample of bottom MB line 7" hexmask.long.byte 0x50 8.--15. 1. "IPE_CR_LF_BOT6,Left Cr sample of bottom MB line 6" newline hexmask.long.byte 0x50 0.--7. 1. "IPE_CB_LF_BOT6,Left Cb sample of bottom MB line 6" width 0x0B tree.end endif tree "IPE3_MMR_L3_MAINInterconnect" base ad:0x5A058800 rgroup.long 0x00++0x53 line.long 0x00 "IPE3_PID,Peripheral ID register" line.long 0x04 "IPE3_COUNT,IPE3 cycle counter register Determines the cycle number between start of IPE3 core and end (interrupt generation)" bitfld.long 0x04 31. "CNT_EN,Counter enable" "Benchmark counter is disabled,Benchmark counter is enabled" bitfld.long 0x04 30. "CNT_RST,Counter reset" "No effect,Clear the benchmark.." hexmask.long.word 0x04 0.--15. 1. "CNT_VALUE,Current value of the benchmark counter" line.long 0x08 "IPE3_CTRL,IPE3 control register" bitfld.long 0x08 18.--19. "IPE_ADDR,Address of parameter set" "Process first MB,Process second MB,Process third MB ( full-view mode only),Process fourth MB ( full-view mode only)" bitfld.long 0x08 2. "IPE_SSM,Single-step mode" "Normal mode,Single-step mode" bitfld.long 0x08 0. "IPE_EN,IPE3 start and status Setting this bit to 1 makes IPE3 start processing" "0,1" line.long 0x0C "IPE3_NS,Horizontal noise suppression register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x0C 1. "NS1,Bottom block status for horizontal noise suppression" "Activity is not higher than H_threshold,Activity is higher than H_threshold" bitfld.long 0x0C 0. "NS0,Top block status for horizontal noise suppression" "Activity is not higher than H_threshold,Activity is higher than H_threshold" line.long 0x10 "IPE3_NA,nA mode register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x10 28.--31. "PRED_NA7,Intraprediction mode of 4 x 4 block 15 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "PRED_NA6,Intraprediction mode of 4 x 4 block 13 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "PRED_NA5,Intraprediction mode of 4 x 4 block 7 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "PRED_NA4,Intraprediction mode of 4 x 4 block 5 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "PRED_NA3,Intraprediction mode of 4 x 4 block 15 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "PRED_NA2,Intraprediction mode of 4 x 4 block 13 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "PRED_NA1,Intraprediction mode of 4 x 4 block 7 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "PRED_NA0,Intraprediction mode of 4 x 4 block 5 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "IPE3_L_LF_T0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x14 24.--31. 1. "IPE_L_LF_TOP3,Luma left sample for top MB line 3" hexmask.long.byte 0x14 16.--23. 1. "IPE_L_LF_TOP2,Luma left sample for top MB line 2" hexmask.long.byte 0x14 8.--15. 1. "IPE_L_LF_TOP1,Luma left sample for top MB line 1" newline hexmask.long.byte 0x14 0.--7. 1. "IPE_L_LF_TOP0,Luma left sample for top MB line 0" line.long 0x18 "IPE3_L_LF_T1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x18 24.--31. 1. "IPE_L_LF_TOP7,Luma left sample for top MB line 7" hexmask.long.byte 0x18 16.--23. 1. "IPE_L_LF_TOP6,Luma left sample for top MB line 6" hexmask.long.byte 0x18 8.--15. 1. "IPE_L_LF_TOP5,Luma left sample for top MB line 5" newline hexmask.long.byte 0x18 0.--7. 1. "IPE_L_LF_TOP4,Luma left sample for top MB line 4" line.long 0x1C "IPE3_L_LF_T2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x1C 24.--31. 1. "IPE_L_LF_TOP11,Luma left sample for top MB line 11" hexmask.long.byte 0x1C 16.--23. 1. "IPE_L_LF_TOP10,Luma left sample for top MB line 10" hexmask.long.byte 0x1C 8.--15. 1. "IPE_L_LF_TOP9,Luma left sample for top MB line 9 The right-most luminance pixel of top MB line 9 in the left MB" newline hexmask.long.byte 0x1C 0.--7. 1. "IPE_L_LF_TOP8,Luma left sample for top MB line 8 The right-most luminance pixel of top MB line 8 in the left MB" line.long 0x20 "IPE3_L_LF_T3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x20 24.--31. 1. "IPE_L_LF_TOP15,Luma left sample for top MB line 15" hexmask.long.byte 0x20 16.--23. 1. "IPE_L_LF_TOP14,Luma left sample for top MB line 14" hexmask.long.byte 0x20 8.--15. 1. "IPE_L_LF_TOP13,Luma left sample for top MB line 13" newline hexmask.long.byte 0x20 0.--7. 1. "IPE_L_LF_TOP12,Luma left sample for top MB line 12" line.long 0x24 "IPE3_L_LF_B0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x24 24.--31. 1. "IPE_L_LF_BOT3,Luma left sample for bottom MB line 3" hexmask.long.byte 0x24 16.--23. 1. "IPE_L_LF_BOT2,Luma left sample for bottom MB line 2" hexmask.long.byte 0x24 8.--15. 1. "IPE_L_LF_BOT1,Luma left sample for bottom MB line 1" newline hexmask.long.byte 0x24 0.--7. 1. "IPE_L_LF_BOT0,Luma left sample for bottom MB line 0" line.long 0x28 "IPE3_L_LF_B1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x28 24.--31. 1. "IPE_L_LF_BOT7,Luma left sample for bottom MB line 7" hexmask.long.byte 0x28 16.--23. 1. "IPE_L_LF_BOT6,Luma left sample for bottom MB line 6" hexmask.long.byte 0x28 8.--15. 1. "IPE_L_LF_BOT5,Luma left sample for bottom MB line 5" newline hexmask.long.byte 0x28 0.--7. 1. "IPE_L_LF_BOT4,Luma left sample for bottom MB line 4" line.long 0x2C "IPE3_L_LF_B2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x2C 24.--31. 1. "IPE_L_LF_BOT11,Luma left sample for bottom MB line 11" hexmask.long.byte 0x2C 16.--23. 1. "IPE_L_LF_BOT10,Luma left sample for bottom MB line 10" hexmask.long.byte 0x2C 8.--15. 1. "IPE_L_LF_BOT9,Luma left sample for bottom MB line 9" newline hexmask.long.byte 0x2C 0.--7. 1. "IPE_L_LF_BOT8,Luma left sample for bottom MB line 8" line.long 0x30 "IPE3_L_LF_B3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x30 24.--31. 1. "IPE_L_LF_BOT15,Luma left sample for bottom MB line 15" hexmask.long.byte 0x30 16.--23. 1. "IPE_L_LF_BOT14,Luma left sample for bottom MB line 14" hexmask.long.byte 0x30 8.--15. 1. "IPE_L_LF_BOT13,Luma left sample for bottom MB line 13" newline hexmask.long.byte 0x30 0.--7. 1. "IPE_L_LF_BOT12,Luma left sample for bottom MB line 12" line.long 0x34 "IPE3_C_LF_T0,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x34 24.--31. 1. "IPE_CR_LF_TOP1,Left Cr sample of top MB line .1 The right-most Cr pixel of top MB line 1 in the left MB" hexmask.long.byte 0x34 16.--23. 1. "IPE_CB_LF_TOP1,Left Cb sample of top MB line 1" hexmask.long.byte 0x34 8.--15. 1. "IPE_CR_LF_TOP0,Left Cr sample of top MB line 0" newline hexmask.long.byte 0x34 0.--7. 1. "IPE_CB_LF_TOP0,Left Cb sample of top MB line 0" line.long 0x38 "IPE3_C_LF_T1,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x38 24.--31. 1. "IPE_CR_LF_TOP3,Left Cr sample of top MB line 3" hexmask.long.byte 0x38 16.--23. 1. "IPE_CB_LF_TOP3,Left Cb sample of top MB line 3" hexmask.long.byte 0x38 8.--15. 1. "IPE_CR_LF_TOP2,Left Cr sample of top MB line 2" newline hexmask.long.byte 0x38 0.--7. 1. "IPE_CB_LF_TOP2,Left Cb sample of top MB line 2" line.long 0x3C "IPE3_C_LF_T2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x3C 24.--31. 1. "IPE_CR_LF_TOP5,Left Cr sample of top MB line 5" hexmask.long.byte 0x3C 16.--23. 1. "IPE_CB_LF_TOP5,Left Cb sample of top MB line 5" hexmask.long.byte 0x3C 8.--15. 1. "IPE_CR_LF_TOP4,Left Cr sample of top MB line 4" newline hexmask.long.byte 0x3C 0.--7. 1. "IPE_CB_LF_TOP4,Left Cb sample of top MB line 4" line.long 0x40 "IPE3_C_LF_T3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x40 24.--31. 1. "IPE_CR_LF_TOP7,Left Cr sample of top MB line 7" hexmask.long.byte 0x40 16.--23. 1. "IPE_CB_LF_TOP7,Left Cb sample of top MB line 7" hexmask.long.byte 0x40 8.--15. 1. "IPE_CR_LF_TOP6,Left Cr sample of top MB line 6" newline hexmask.long.byte 0x40 0.--7. 1. "IPE_CB_LF_TOP6,Left Cb sample of top MB line 6" line.long 0x44 "IPE3_C_LF_B0,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x44 24.--31. 1. "IPE_CR_LF_BOT1,Left Cr sample of bottom MB line 1" hexmask.long.byte 0x44 16.--23. 1. "IPE_CB_LF_BOT1,Left Cb sample of bottom MB line 1" hexmask.long.byte 0x44 8.--15. 1. "IPE_CR_LF_BOT0,Left Cr sample of bottom MB line 0" newline hexmask.long.byte 0x44 0.--7. 1. "IPE_CB_LF_BOT0,Left Cb sample of bottom MB line 0" line.long 0x48 "IPE3_C_LF_B1,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x48 24.--31. 1. "IPE_CR_LF_BOT3,Left Cr sample of bottom MB line 3" hexmask.long.byte 0x48 16.--23. 1. "IPE_CB_LF_BOT3,Left Cb sample of bottom MB line 3" hexmask.long.byte 0x48 8.--15. 1. "IPE_CR_LF_BOT2,Left Cr sample of bottom MB line 2" newline hexmask.long.byte 0x48 0.--7. 1. "IPE_CB_LF_BOT2,Left Cb sample of bottom MB line 2" line.long 0x4C "IPE3_C_LF_B2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x4C 24.--31. 1. "IPE_CR_LF_BOT5,Left Cr sample of bottom MB line 5" hexmask.long.byte 0x4C 16.--23. 1. "IPE_CB_LF_BOT5,Left Cb sample of bottom MB line 5" hexmask.long.byte 0x4C 8.--15. 1. "IPE_CR_LF_BOT4,Left Cr sample of bottom MB line 4" newline hexmask.long.byte 0x4C 0.--7. 1. "IPE_CB_LF_BOT4,Left Cb sample of bottom MB line 4" line.long 0x50 "IPE3_C_LF_B3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x50 24.--31. 1. "IPE_CR_LF_BOT7,Left Cr sample of bottom MB line 7" hexmask.long.byte 0x50 16.--23. 1. "IPE_CB_LF_BOT7,Left Cb sample of bottom MB line 7" hexmask.long.byte 0x50 8.--15. 1. "IPE_CR_LF_BOT6,Left Cr sample of bottom MB line 6" newline hexmask.long.byte 0x50 0.--7. 1. "IPE_CB_LF_BOT6,Left Cb sample of bottom MB line 6" width 0x0B tree.end tree.end tree "IVA_Load_and_Store_Engine" sif (cpuis("TDA2PXIVA*")) tree "CALC3_LSE_ICONT" base ad:0xD8300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end endif tree "CALC3_LSE_L3_MAINInterconnect" base ad:0x5A058300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "ECD3_LSE_ICONT" base ad:0xD9B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end endif tree "ECD3_LSE_L3_MAINInterconnect" base ad:0x5A059B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree "IPE3_LSE_ICONT" base ad:0xD8B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree "IPE3_LSE_L3_MAINInterconnect" base ad:0x5A058B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree "MC3_LSE_ICONT" base ad:0xD9300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree "MC3_LSE_L3_MAINInterconnect" base ad:0x5A059300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "LSE does the process for slice boundary after..,int_eos is passed through to SYNCBOX_CALC3.." bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" newline bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" newline bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" newline bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" width 0x0B tree.end tree.end tree "IVA_Loop_Filter" sif (cpuis("TDA2PXIVA*")) tree "ILF3_ICONT" base ad:0xD2000 tree "Channel_0" group.long 0x1C8++0x03 line.long 0x00 "ILF3_BS_l_0,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x03 line.long 0x00 "ILF3_IPB_n_0,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x94++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_0,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x4C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x128++0x03 line.long 0x00 "ILF3_QP_IDX_j_0,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE0++0x03 line.long 0x00 "ILF3_QP_m_0,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_0,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_1" group.long 0x1CC++0x03 line.long 0x00 "ILF3_BS_l_1,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x420++0x03 line.long 0x00 "ILF3_IPB_n_1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x98++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_1,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x44++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_1,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x50++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_1,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x12C++0x03 line.long 0x00 "ILF3_QP_IDX_j_1,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE4++0x03 line.long 0x00 "ILF3_QP_m_1,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_1,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_10" group.long 0x1F0++0x03 line.long 0x00 "ILF3_BS_l_10,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x444++0x03 line.long 0x00 "ILF3_IPB_n_10,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x74++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_10,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x150++0x03 line.long 0x00 "ILF3_QP_IDX_j_10,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "ILF3_QP_m_10,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_100" group.long 0x358++0x03 line.long 0x00 "ILF3_BS_l_100,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5AC++0x03 line.long 0x00 "ILF3_IPB_n_100,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_101" group.long 0x35C++0x03 line.long 0x00 "ILF3_BS_l_101,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B0++0x03 line.long 0x00 "ILF3_IPB_n_101,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_102" group.long 0x360++0x03 line.long 0x00 "ILF3_BS_l_102,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B4++0x03 line.long 0x00 "ILF3_IPB_n_102,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_103" group.long 0x364++0x03 line.long 0x00 "ILF3_BS_l_103,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B8++0x03 line.long 0x00 "ILF3_IPB_n_103,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_104" group.long 0x368++0x03 line.long 0x00 "ILF3_BS_l_104,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5BC++0x03 line.long 0x00 "ILF3_IPB_n_104,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_105" group.long 0x36C++0x03 line.long 0x00 "ILF3_BS_l_105,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C0++0x03 line.long 0x00 "ILF3_IPB_n_105,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_106" group.long 0x370++0x03 line.long 0x00 "ILF3_BS_l_106,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C4++0x03 line.long 0x00 "ILF3_IPB_n_106,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_107" group.long 0x374++0x03 line.long 0x00 "ILF3_BS_l_107,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C8++0x03 line.long 0x00 "ILF3_IPB_n_107,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_108" group.long 0x378++0x03 line.long 0x00 "ILF3_BS_l_108,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5CC++0x03 line.long 0x00 "ILF3_IPB_n_108,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_109" group.long 0x37C++0x03 line.long 0x00 "ILF3_BS_l_109,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D0++0x03 line.long 0x00 "ILF3_IPB_n_109,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_11" group.long 0x1F4++0x03 line.long 0x00 "ILF3_BS_l_11,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x448++0x03 line.long 0x00 "ILF3_IPB_n_11,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x78++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_11,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x154++0x03 line.long 0x00 "ILF3_QP_IDX_j_11,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x10C++0x03 line.long 0x00 "ILF3_QP_m_11,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_110" group.long 0x380++0x03 line.long 0x00 "ILF3_BS_l_110,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D4++0x03 line.long 0x00 "ILF3_IPB_n_110,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_111" group.long 0x384++0x03 line.long 0x00 "ILF3_BS_l_111,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D8++0x03 line.long 0x00 "ILF3_IPB_n_111,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_112" group.long 0x388++0x03 line.long 0x00 "ILF3_BS_l_112,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5DC++0x03 line.long 0x00 "ILF3_IPB_n_112,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_113" group.long 0x38C++0x03 line.long 0x00 "ILF3_BS_l_113,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E0++0x03 line.long 0x00 "ILF3_IPB_n_113,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_114" group.long 0x390++0x03 line.long 0x00 "ILF3_BS_l_114,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E4++0x03 line.long 0x00 "ILF3_IPB_n_114,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_115" group.long 0x394++0x03 line.long 0x00 "ILF3_BS_l_115,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E8++0x03 line.long 0x00 "ILF3_IPB_n_115,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_116" group.long 0x398++0x03 line.long 0x00 "ILF3_BS_l_116,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5EC++0x03 line.long 0x00 "ILF3_IPB_n_116,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_117" group.long 0x39C++0x03 line.long 0x00 "ILF3_BS_l_117,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F0++0x03 line.long 0x00 "ILF3_IPB_n_117,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_118" group.long 0x3A0++0x03 line.long 0x00 "ILF3_BS_l_118,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F4++0x03 line.long 0x00 "ILF3_IPB_n_118,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_119" group.long 0x3A4++0x03 line.long 0x00 "ILF3_BS_l_119,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F8++0x03 line.long 0x00 "ILF3_IPB_n_119,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_12" group.long 0x1F8++0x03 line.long 0x00 "ILF3_BS_l_12,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44C++0x03 line.long 0x00 "ILF3_IPB_n_12,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x7C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_12,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x158++0x03 line.long 0x00 "ILF3_QP_IDX_j_12,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "ILF3_QP_m_12,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_120" group.long 0x3A8++0x03 line.long 0x00 "ILF3_BS_l_120,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5FC++0x03 line.long 0x00 "ILF3_IPB_n_120,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_121" group.long 0x3AC++0x03 line.long 0x00 "ILF3_BS_l_121,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x600++0x03 line.long 0x00 "ILF3_IPB_n_121,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_122" group.long 0x3B0++0x03 line.long 0x00 "ILF3_BS_l_122,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x604++0x03 line.long 0x00 "ILF3_IPB_n_122,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_123" group.long 0x3B4++0x03 line.long 0x00 "ILF3_BS_l_123,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x608++0x03 line.long 0x00 "ILF3_IPB_n_123,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_124" group.long 0x3B8++0x03 line.long 0x00 "ILF3_BS_l_124,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x60C++0x03 line.long 0x00 "ILF3_IPB_n_124,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_125" group.long 0x3BC++0x03 line.long 0x00 "ILF3_BS_l_125,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x610++0x03 line.long 0x00 "ILF3_IPB_n_125,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_126" group.long 0x3C0++0x03 line.long 0x00 "ILF3_BS_l_126,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x614++0x03 line.long 0x00 "ILF3_IPB_n_126,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_127" group.long 0x3C4++0x03 line.long 0x00 "ILF3_BS_l_127,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x618++0x03 line.long 0x00 "ILF3_IPB_n_127,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_128" group.long 0x3C8++0x03 line.long 0x00 "ILF3_BS_l_128,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x61C++0x03 line.long 0x00 "ILF3_IPB_n_128,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_129" group.long 0x3CC++0x03 line.long 0x00 "ILF3_BS_l_129,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x620++0x03 line.long 0x00 "ILF3_IPB_n_129,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_13" group.long 0x1FC++0x03 line.long 0x00 "ILF3_BS_l_13,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x450++0x03 line.long 0x00 "ILF3_IPB_n_13,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x80++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_13,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x15C++0x03 line.long 0x00 "ILF3_QP_IDX_j_13,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x114++0x03 line.long 0x00 "ILF3_QP_m_13,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_130" group.long 0x3D0++0x03 line.long 0x00 "ILF3_BS_l_130,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x624++0x03 line.long 0x00 "ILF3_IPB_n_130,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_131" group.long 0x3D4++0x03 line.long 0x00 "ILF3_BS_l_131,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x628++0x03 line.long 0x00 "ILF3_IPB_n_131,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_132" group.long 0x3D8++0x03 line.long 0x00 "ILF3_BS_l_132,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x62C++0x03 line.long 0x00 "ILF3_IPB_n_132,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_133" group.long 0x3DC++0x03 line.long 0x00 "ILF3_BS_l_133,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x630++0x03 line.long 0x00 "ILF3_IPB_n_133,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_134" group.long 0x3E0++0x03 line.long 0x00 "ILF3_BS_l_134,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x634++0x03 line.long 0x00 "ILF3_IPB_n_134,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_135" group.long 0x3E4++0x03 line.long 0x00 "ILF3_BS_l_135,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x638++0x03 line.long 0x00 "ILF3_IPB_n_135,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_136" group.long 0x3E8++0x03 line.long 0x00 "ILF3_BS_l_136,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x63C++0x03 line.long 0x00 "ILF3_IPB_n_136,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_137" group.long 0x3EC++0x03 line.long 0x00 "ILF3_BS_l_137,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x640++0x03 line.long 0x00 "ILF3_IPB_n_137,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_138" group.long 0x3F0++0x03 line.long 0x00 "ILF3_BS_l_138,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x644++0x03 line.long 0x00 "ILF3_IPB_n_138,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_139" group.long 0x3F4++0x03 line.long 0x00 "ILF3_BS_l_139,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x648++0x03 line.long 0x00 "ILF3_IPB_n_139,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_14" group.long 0x200++0x03 line.long 0x00 "ILF3_BS_l_14,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x454++0x03 line.long 0x00 "ILF3_IPB_n_14,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x84++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_14,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x160++0x03 line.long 0x00 "ILF3_QP_IDX_j_14,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "ILF3_QP_m_14,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_140" group.long 0x3F8++0x03 line.long 0x00 "ILF3_BS_l_140,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x64C++0x03 line.long 0x00 "ILF3_IPB_n_140,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_141" group.long 0x3FC++0x03 line.long 0x00 "ILF3_BS_l_141,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x650++0x03 line.long 0x00 "ILF3_IPB_n_141,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_142" group.long 0x400++0x03 line.long 0x00 "ILF3_BS_l_142,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x654++0x03 line.long 0x00 "ILF3_IPB_n_142,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_143" group.long 0x404++0x03 line.long 0x00 "ILF3_BS_l_143,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x658++0x03 line.long 0x00 "ILF3_IPB_n_143,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_144" group.long 0x408++0x03 line.long 0x00 "ILF3_BS_l_144,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x65C++0x03 line.long 0x00 "ILF3_IPB_n_144,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_145" group.long 0x40C++0x03 line.long 0x00 "ILF3_BS_l_145,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x660++0x03 line.long 0x00 "ILF3_IPB_n_145,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_146" group.long 0x410++0x03 line.long 0x00 "ILF3_BS_l_146,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x664++0x03 line.long 0x00 "ILF3_IPB_n_146,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_147" group.long 0x414++0x03 line.long 0x00 "ILF3_BS_l_147,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x668++0x03 line.long 0x00 "ILF3_IPB_n_147,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_148" group.long 0x418++0x03 line.long 0x00 "ILF3_BS_l_148,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x66C++0x8AF line.long 0x00 "ILF3_IPB_n_148,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x04 "ILF3_IPB_n_149,Input buffer bank" bitfld.long 0x04 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x08 "ILF3_IPB_n_150,Input buffer bank" bitfld.long 0x08 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x0C "ILF3_IPB_n_151,Input buffer bank" bitfld.long 0x0C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x10 "ILF3_IPB_n_152,Input buffer bank" bitfld.long 0x10 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x14 "ILF3_IPB_n_153,Input buffer bank" bitfld.long 0x14 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x18 "ILF3_IPB_n_154,Input buffer bank" bitfld.long 0x18 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C "ILF3_IPB_n_155,Input buffer bank" bitfld.long 0x1C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x20 "ILF3_IPB_n_156,Input buffer bank" bitfld.long 0x20 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x24 "ILF3_IPB_n_157,Input buffer bank" bitfld.long 0x24 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x28 "ILF3_IPB_n_158,Input buffer bank" bitfld.long 0x28 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C "ILF3_IPB_n_159,Input buffer bank" bitfld.long 0x2C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x30 "ILF3_IPB_n_160,Input buffer bank" bitfld.long 0x30 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x34 "ILF3_IPB_n_161,Input buffer bank" bitfld.long 0x34 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x38 "ILF3_IPB_n_162,Input buffer bank" bitfld.long 0x38 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C "ILF3_IPB_n_163,Input buffer bank" bitfld.long 0x3C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x40 "ILF3_IPB_n_164,Input buffer bank" bitfld.long 0x40 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x44 "ILF3_IPB_n_165,Input buffer bank" bitfld.long 0x44 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x48 "ILF3_IPB_n_166,Input buffer bank" bitfld.long 0x48 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x48 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C "ILF3_IPB_n_167,Input buffer bank" bitfld.long 0x4C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x50 "ILF3_IPB_n_168,Input buffer bank" bitfld.long 0x50 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x54 "ILF3_IPB_n_169,Input buffer bank" bitfld.long 0x54 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x54 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x58 "ILF3_IPB_n_170,Input buffer bank" bitfld.long 0x58 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x58 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C "ILF3_IPB_n_171,Input buffer bank" bitfld.long 0x5C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x60 "ILF3_IPB_n_172,Input buffer bank" bitfld.long 0x60 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x60 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x64 "ILF3_IPB_n_173,Input buffer bank" bitfld.long 0x64 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x64 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x68 "ILF3_IPB_n_174,Input buffer bank" bitfld.long 0x68 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x68 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C "ILF3_IPB_n_175,Input buffer bank" bitfld.long 0x6C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x70 "ILF3_IPB_n_176,Input buffer bank" bitfld.long 0x70 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x70 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x74 "ILF3_IPB_n_177,Input buffer bank" bitfld.long 0x74 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x74 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x78 "ILF3_IPB_n_178,Input buffer bank" bitfld.long 0x78 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C "ILF3_IPB_n_179,Input buffer bank" bitfld.long 0x7C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x80 "ILF3_IPB_n_180,Input buffer bank" bitfld.long 0x80 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x84 "ILF3_IPB_n_181,Input buffer bank" bitfld.long 0x84 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x84 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x88 "ILF3_IPB_n_182,Input buffer bank" bitfld.long 0x88 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x88 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8C "ILF3_IPB_n_183,Input buffer bank" bitfld.long 0x8C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x90 "ILF3_IPB_n_184,Input buffer bank" bitfld.long 0x90 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x90 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x94 "ILF3_IPB_n_185,Input buffer bank" bitfld.long 0x94 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x94 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x98 "ILF3_IPB_n_186,Input buffer bank" bitfld.long 0x98 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x98 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x9C "ILF3_IPB_n_187,Input buffer bank" bitfld.long 0x9C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x9C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA0 "ILF3_IPB_n_188,Input buffer bank" bitfld.long 0xA0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA4 "ILF3_IPB_n_189,Input buffer bank" bitfld.long 0xA4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA8 "ILF3_IPB_n_190,Input buffer bank" bitfld.long 0xA8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xAC "ILF3_IPB_n_191,Input buffer bank" bitfld.long 0xAC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB0 "ILF3_IPB_n_192,Input buffer bank" bitfld.long 0xB0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB4 "ILF3_IPB_n_193,Input buffer bank" bitfld.long 0xB4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB8 "ILF3_IPB_n_194,Input buffer bank" bitfld.long 0xB8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xBC "ILF3_IPB_n_195,Input buffer bank" bitfld.long 0xBC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xBC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC0 "ILF3_IPB_n_196,Input buffer bank" bitfld.long 0xC0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC4 "ILF3_IPB_n_197,Input buffer bank" bitfld.long 0xC4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC8 "ILF3_IPB_n_198,Input buffer bank" bitfld.long 0xC8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xCC "ILF3_IPB_n_199,Input buffer bank" bitfld.long 0xCC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD0 "ILF3_IPB_n_200,Input buffer bank" bitfld.long 0xD0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD4 "ILF3_IPB_n_201,Input buffer bank" bitfld.long 0xD4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD8 "ILF3_IPB_n_202,Input buffer bank" bitfld.long 0xD8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xDC "ILF3_IPB_n_203,Input buffer bank" bitfld.long 0xDC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xDC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE0 "ILF3_IPB_n_204,Input buffer bank" bitfld.long 0xE0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE4 "ILF3_IPB_n_205,Input buffer bank" bitfld.long 0xE4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE8 "ILF3_IPB_n_206,Input buffer bank" bitfld.long 0xE8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xEC "ILF3_IPB_n_207,Input buffer bank" bitfld.long 0xEC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xEC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF0 "ILF3_IPB_n_208,Input buffer bank" bitfld.long 0xF0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF4 "ILF3_IPB_n_209,Input buffer bank" bitfld.long 0xF4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF8 "ILF3_IPB_n_210,Input buffer bank" bitfld.long 0xF8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xFC "ILF3_IPB_n_211,Input buffer bank" bitfld.long 0xFC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xFC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x100 "ILF3_IPB_n_212,Input buffer bank" bitfld.long 0x100 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x100 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x104 "ILF3_IPB_n_213,Input buffer bank" bitfld.long 0x104 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x104 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x108 "ILF3_IPB_n_214,Input buffer bank" bitfld.long 0x108 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x108 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x10C "ILF3_IPB_n_215,Input buffer bank" bitfld.long 0x10C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x110 "ILF3_IPB_n_216,Input buffer bank" bitfld.long 0x110 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x110 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x114 "ILF3_IPB_n_217,Input buffer bank" bitfld.long 0x114 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x114 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x118 "ILF3_IPB_n_218,Input buffer bank" bitfld.long 0x118 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x118 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x11C "ILF3_IPB_n_219,Input buffer bank" bitfld.long 0x11C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x11C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x120 "ILF3_IPB_n_220,Input buffer bank" bitfld.long 0x120 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x120 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x124 "ILF3_IPB_n_221,Input buffer bank" bitfld.long 0x124 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x124 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x128 "ILF3_IPB_n_222,Input buffer bank" bitfld.long 0x128 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x128 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x12C "ILF3_IPB_n_223,Input buffer bank" bitfld.long 0x12C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x12C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x130 "ILF3_IPB_n_224,Input buffer bank" bitfld.long 0x130 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x130 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x134 "ILF3_IPB_n_225,Input buffer bank" bitfld.long 0x134 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x134 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x138 "ILF3_IPB_n_226,Input buffer bank" bitfld.long 0x138 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x138 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x13C "ILF3_IPB_n_227,Input buffer bank" bitfld.long 0x13C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x13C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x140 "ILF3_IPB_n_228,Input buffer bank" bitfld.long 0x140 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x140 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x144 "ILF3_IPB_n_229,Input buffer bank" bitfld.long 0x144 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x144 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x148 "ILF3_IPB_n_230,Input buffer bank" bitfld.long 0x148 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x148 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x14C "ILF3_IPB_n_231,Input buffer bank" bitfld.long 0x14C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x150 "ILF3_IPB_n_232,Input buffer bank" bitfld.long 0x150 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x150 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x154 "ILF3_IPB_n_233,Input buffer bank" bitfld.long 0x154 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x154 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x158 "ILF3_IPB_n_234,Input buffer bank" bitfld.long 0x158 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x158 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x15C "ILF3_IPB_n_235,Input buffer bank" bitfld.long 0x15C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x15C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x160 "ILF3_IPB_n_236,Input buffer bank" bitfld.long 0x160 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x160 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x164 "ILF3_IPB_n_237,Input buffer bank" bitfld.long 0x164 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x164 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x168 "ILF3_IPB_n_238,Input buffer bank" bitfld.long 0x168 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x168 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x16C "ILF3_IPB_n_239,Input buffer bank" bitfld.long 0x16C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x16C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x170 "ILF3_IPB_n_240,Input buffer bank" bitfld.long 0x170 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x170 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x174 "ILF3_IPB_n_241,Input buffer bank" bitfld.long 0x174 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x174 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x178 "ILF3_IPB_n_242,Input buffer bank" bitfld.long 0x178 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x178 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x17C "ILF3_IPB_n_243,Input buffer bank" bitfld.long 0x17C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x17C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x180 "ILF3_IPB_n_244,Input buffer bank" bitfld.long 0x180 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x180 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x184 "ILF3_IPB_n_245,Input buffer bank" bitfld.long 0x184 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x184 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x188 "ILF3_IPB_n_246,Input buffer bank" bitfld.long 0x188 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x188 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x18C "ILF3_IPB_n_247,Input buffer bank" bitfld.long 0x18C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x190 "ILF3_IPB_n_248,Input buffer bank" bitfld.long 0x190 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x190 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x194 "ILF3_IPB_n_249,Input buffer bank" bitfld.long 0x194 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x194 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x198 "ILF3_IPB_n_250,Input buffer bank" bitfld.long 0x198 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x198 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x19C "ILF3_IPB_n_251,Input buffer bank" bitfld.long 0x19C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x19C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A0 "ILF3_IPB_n_252,Input buffer bank" bitfld.long 0x1A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A4 "ILF3_IPB_n_253,Input buffer bank" bitfld.long 0x1A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A8 "ILF3_IPB_n_254,Input buffer bank" bitfld.long 0x1A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1AC "ILF3_IPB_n_255,Input buffer bank" bitfld.long 0x1AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B0 "ILF3_IPB_n_256,Input buffer bank" bitfld.long 0x1B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B4 "ILF3_IPB_n_257,Input buffer bank" bitfld.long 0x1B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B8 "ILF3_IPB_n_258,Input buffer bank" bitfld.long 0x1B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1BC "ILF3_IPB_n_259,Input buffer bank" bitfld.long 0x1BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C0 "ILF3_IPB_n_260,Input buffer bank" bitfld.long 0x1C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C4 "ILF3_IPB_n_261,Input buffer bank" bitfld.long 0x1C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C8 "ILF3_IPB_n_262,Input buffer bank" bitfld.long 0x1C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1CC "ILF3_IPB_n_263,Input buffer bank" bitfld.long 0x1CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D0 "ILF3_IPB_n_264,Input buffer bank" bitfld.long 0x1D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D4 "ILF3_IPB_n_265,Input buffer bank" bitfld.long 0x1D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D8 "ILF3_IPB_n_266,Input buffer bank" bitfld.long 0x1D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1DC "ILF3_IPB_n_267,Input buffer bank" bitfld.long 0x1DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E0 "ILF3_IPB_n_268,Input buffer bank" bitfld.long 0x1E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E4 "ILF3_IPB_n_269,Input buffer bank" bitfld.long 0x1E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E8 "ILF3_IPB_n_270,Input buffer bank" bitfld.long 0x1E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1EC "ILF3_IPB_n_271,Input buffer bank" bitfld.long 0x1EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F0 "ILF3_IPB_n_272,Input buffer bank" bitfld.long 0x1F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F4 "ILF3_IPB_n_273,Input buffer bank" bitfld.long 0x1F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F8 "ILF3_IPB_n_274,Input buffer bank" bitfld.long 0x1F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1FC "ILF3_IPB_n_275,Input buffer bank" bitfld.long 0x1FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x200 "ILF3_IPB_n_276,Input buffer bank" bitfld.long 0x200 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x200 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x204 "ILF3_IPB_n_277,Input buffer bank" bitfld.long 0x204 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x204 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x208 "ILF3_IPB_n_278,Input buffer bank" bitfld.long 0x208 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x208 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x20C "ILF3_IPB_n_279,Input buffer bank" bitfld.long 0x20C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x210 "ILF3_IPB_n_280,Input buffer bank" bitfld.long 0x210 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x210 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x214 "ILF3_IPB_n_281,Input buffer bank" bitfld.long 0x214 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x214 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x218 "ILF3_IPB_n_282,Input buffer bank" bitfld.long 0x218 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x218 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x21C "ILF3_IPB_n_283,Input buffer bank" bitfld.long 0x21C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x21C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x220 "ILF3_IPB_n_284,Input buffer bank" bitfld.long 0x220 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x220 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x224 "ILF3_IPB_n_285,Input buffer bank" bitfld.long 0x224 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x224 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x228 "ILF3_IPB_n_286,Input buffer bank" bitfld.long 0x228 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x228 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x22C "ILF3_IPB_n_287,Input buffer bank" bitfld.long 0x22C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x22C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x230 "ILF3_IPB_n_288,Input buffer bank" bitfld.long 0x230 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x230 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x234 "ILF3_IPB_n_289,Input buffer bank" bitfld.long 0x234 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x234 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x238 "ILF3_IPB_n_290,Input buffer bank" bitfld.long 0x238 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x238 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x23C "ILF3_IPB_n_291,Input buffer bank" bitfld.long 0x23C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x23C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x240 "ILF3_IPB_n_292,Input buffer bank" bitfld.long 0x240 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x240 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x244 "ILF3_IPB_n_293,Input buffer bank" bitfld.long 0x244 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x244 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x248 "ILF3_IPB_n_294,Input buffer bank" bitfld.long 0x248 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x248 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x24C "ILF3_IPB_n_295,Input buffer bank" bitfld.long 0x24C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x250 "ILF3_IPB_n_296,Input buffer bank" bitfld.long 0x250 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x250 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x254 "ILF3_IPB_n_297,Input buffer bank" bitfld.long 0x254 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x254 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x258 "ILF3_IPB_n_298,Input buffer bank" bitfld.long 0x258 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x258 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x25C "ILF3_IPB_n_299,Input buffer bank" bitfld.long 0x25C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x25C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x260 "ILF3_IPB_n_300,Input buffer bank" bitfld.long 0x260 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x260 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x264 "ILF3_IPB_n_301,Input buffer bank" bitfld.long 0x264 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x264 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x268 "ILF3_IPB_n_302,Input buffer bank" bitfld.long 0x268 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x268 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x26C "ILF3_IPB_n_303,Input buffer bank" bitfld.long 0x26C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x26C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x270 "ILF3_IPB_n_304,Input buffer bank" bitfld.long 0x270 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x270 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x274 "ILF3_IPB_n_305,Input buffer bank" bitfld.long 0x274 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x274 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x278 "ILF3_IPB_n_306,Input buffer bank" bitfld.long 0x278 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x278 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x27C "ILF3_IPB_n_307,Input buffer bank" bitfld.long 0x27C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x27C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x280 "ILF3_IPB_n_308,Input buffer bank" bitfld.long 0x280 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x280 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x284 "ILF3_IPB_n_309,Input buffer bank" bitfld.long 0x284 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x284 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x288 "ILF3_IPB_n_310,Input buffer bank" bitfld.long 0x288 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x288 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x28C "ILF3_IPB_n_311,Input buffer bank" bitfld.long 0x28C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x290 "ILF3_IPB_n_312,Input buffer bank" bitfld.long 0x290 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x290 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x294 "ILF3_IPB_n_313,Input buffer bank" bitfld.long 0x294 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x294 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x298 "ILF3_IPB_n_314,Input buffer bank" bitfld.long 0x298 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x298 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x29C "ILF3_IPB_n_315,Input buffer bank" bitfld.long 0x29C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x29C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A0 "ILF3_IPB_n_316,Input buffer bank" bitfld.long 0x2A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A4 "ILF3_IPB_n_317,Input buffer bank" bitfld.long 0x2A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A8 "ILF3_IPB_n_318,Input buffer bank" bitfld.long 0x2A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2AC "ILF3_IPB_n_319,Input buffer bank" bitfld.long 0x2AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B0 "ILF3_IPB_n_320,Input buffer bank" bitfld.long 0x2B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B4 "ILF3_IPB_n_321,Input buffer bank" bitfld.long 0x2B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B8 "ILF3_IPB_n_322,Input buffer bank" bitfld.long 0x2B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2BC "ILF3_IPB_n_323,Input buffer bank" bitfld.long 0x2BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C0 "ILF3_IPB_n_324,Input buffer bank" bitfld.long 0x2C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C4 "ILF3_IPB_n_325,Input buffer bank" bitfld.long 0x2C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C8 "ILF3_IPB_n_326,Input buffer bank" bitfld.long 0x2C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2CC "ILF3_IPB_n_327,Input buffer bank" bitfld.long 0x2CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D0 "ILF3_IPB_n_328,Input buffer bank" bitfld.long 0x2D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D4 "ILF3_IPB_n_329,Input buffer bank" bitfld.long 0x2D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D8 "ILF3_IPB_n_330,Input buffer bank" bitfld.long 0x2D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2DC "ILF3_IPB_n_331,Input buffer bank" bitfld.long 0x2DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E0 "ILF3_IPB_n_332,Input buffer bank" bitfld.long 0x2E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E4 "ILF3_IPB_n_333,Input buffer bank" bitfld.long 0x2E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E8 "ILF3_IPB_n_334,Input buffer bank" bitfld.long 0x2E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2EC "ILF3_IPB_n_335,Input buffer bank" bitfld.long 0x2EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F0 "ILF3_IPB_n_336,Input buffer bank" bitfld.long 0x2F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F4 "ILF3_IPB_n_337,Input buffer bank" bitfld.long 0x2F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F8 "ILF3_IPB_n_338,Input buffer bank" bitfld.long 0x2F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2FC "ILF3_IPB_n_339,Input buffer bank" bitfld.long 0x2FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x300 "ILF3_IPB_n_340,Input buffer bank" bitfld.long 0x300 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x300 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x304 "ILF3_IPB_n_341,Input buffer bank" bitfld.long 0x304 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x304 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x308 "ILF3_IPB_n_342,Input buffer bank" bitfld.long 0x308 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x308 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x30C "ILF3_IPB_n_343,Input buffer bank" bitfld.long 0x30C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x310 "ILF3_IPB_n_344,Input buffer bank" bitfld.long 0x310 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x310 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x314 "ILF3_IPB_n_345,Input buffer bank" bitfld.long 0x314 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x314 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x318 "ILF3_IPB_n_346,Input buffer bank" bitfld.long 0x318 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x318 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x31C "ILF3_IPB_n_347,Input buffer bank" bitfld.long 0x31C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x31C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x320 "ILF3_IPB_n_348,Input buffer bank" bitfld.long 0x320 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x320 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x324 "ILF3_IPB_n_349,Input buffer bank" bitfld.long 0x324 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x324 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x328 "ILF3_IPB_n_350,Input buffer bank" bitfld.long 0x328 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x328 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x32C "ILF3_IPB_n_351,Input buffer bank" bitfld.long 0x32C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x32C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x330 "ILF3_IPB_n_352,Input buffer bank" bitfld.long 0x330 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x330 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x334 "ILF3_IPB_n_353,Input buffer bank" bitfld.long 0x334 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x334 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x338 "ILF3_IPB_n_354,Input buffer bank" bitfld.long 0x338 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x338 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x33C "ILF3_IPB_n_355,Input buffer bank" bitfld.long 0x33C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x33C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x340 "ILF3_IPB_n_356,Input buffer bank" bitfld.long 0x340 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x340 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x344 "ILF3_IPB_n_357,Input buffer bank" bitfld.long 0x344 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x344 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x348 "ILF3_IPB_n_358,Input buffer bank" bitfld.long 0x348 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x348 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x34C "ILF3_IPB_n_359,Input buffer bank" bitfld.long 0x34C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x350 "ILF3_IPB_n_360,Input buffer bank" bitfld.long 0x350 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x350 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x354 "ILF3_IPB_n_361,Input buffer bank" bitfld.long 0x354 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x354 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x358 "ILF3_IPB_n_362,Input buffer bank" bitfld.long 0x358 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x358 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x35C "ILF3_IPB_n_363,Input buffer bank" bitfld.long 0x35C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x35C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x360 "ILF3_IPB_n_364,Input buffer bank" bitfld.long 0x360 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x360 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x364 "ILF3_IPB_n_365,Input buffer bank" bitfld.long 0x364 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x364 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x368 "ILF3_IPB_n_366,Input buffer bank" bitfld.long 0x368 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x368 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x36C "ILF3_IPB_n_367,Input buffer bank" bitfld.long 0x36C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x36C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x370 "ILF3_IPB_n_368,Input buffer bank" bitfld.long 0x370 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x370 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x374 "ILF3_IPB_n_369,Input buffer bank" bitfld.long 0x374 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x374 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x378 "ILF3_IPB_n_370,Input buffer bank" bitfld.long 0x378 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x378 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x37C "ILF3_IPB_n_371,Input buffer bank" bitfld.long 0x37C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x37C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x380 "ILF3_IPB_n_372,Input buffer bank" bitfld.long 0x380 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x380 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x384 "ILF3_IPB_n_373,Input buffer bank" bitfld.long 0x384 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x384 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x388 "ILF3_IPB_n_374,Input buffer bank" bitfld.long 0x388 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x388 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x38C "ILF3_IPB_n_375,Input buffer bank" bitfld.long 0x38C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x390 "ILF3_IPB_n_376,Input buffer bank" bitfld.long 0x390 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x390 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x394 "ILF3_IPB_n_377,Input buffer bank" bitfld.long 0x394 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x394 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x398 "ILF3_IPB_n_378,Input buffer bank" bitfld.long 0x398 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x398 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x39C "ILF3_IPB_n_379,Input buffer bank" bitfld.long 0x39C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x39C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A0 "ILF3_IPB_n_380,Input buffer bank" bitfld.long 0x3A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A4 "ILF3_IPB_n_381,Input buffer bank" bitfld.long 0x3A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A8 "ILF3_IPB_n_382,Input buffer bank" bitfld.long 0x3A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3AC "ILF3_IPB_n_383,Input buffer bank" bitfld.long 0x3AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B0 "ILF3_IPB_n_384,Input buffer bank" bitfld.long 0x3B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B4 "ILF3_IPB_n_385,Input buffer bank" bitfld.long 0x3B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B8 "ILF3_IPB_n_386,Input buffer bank" bitfld.long 0x3B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3BC "ILF3_IPB_n_387,Input buffer bank" bitfld.long 0x3BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C0 "ILF3_IPB_n_388,Input buffer bank" bitfld.long 0x3C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C4 "ILF3_IPB_n_389,Input buffer bank" bitfld.long 0x3C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C8 "ILF3_IPB_n_390,Input buffer bank" bitfld.long 0x3C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3CC "ILF3_IPB_n_391,Input buffer bank" bitfld.long 0x3CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D0 "ILF3_IPB_n_392,Input buffer bank" bitfld.long 0x3D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D4 "ILF3_IPB_n_393,Input buffer bank" bitfld.long 0x3D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D8 "ILF3_IPB_n_394,Input buffer bank" bitfld.long 0x3D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3DC "ILF3_IPB_n_395,Input buffer bank" bitfld.long 0x3DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E0 "ILF3_IPB_n_396,Input buffer bank" bitfld.long 0x3E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E4 "ILF3_IPB_n_397,Input buffer bank" bitfld.long 0x3E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E8 "ILF3_IPB_n_398,Input buffer bank" bitfld.long 0x3E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3EC "ILF3_IPB_n_399,Input buffer bank" bitfld.long 0x3EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F0 "ILF3_IPB_n_400,Input buffer bank" bitfld.long 0x3F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F4 "ILF3_IPB_n_401,Input buffer bank" bitfld.long 0x3F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F8 "ILF3_IPB_n_402,Input buffer bank" bitfld.long 0x3F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3FC "ILF3_IPB_n_403,Input buffer bank" bitfld.long 0x3FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x400 "ILF3_IPB_n_404,Input buffer bank" bitfld.long 0x400 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x400 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x404 "ILF3_IPB_n_405,Input buffer bank" bitfld.long 0x404 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x404 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x408 "ILF3_IPB_n_406,Input buffer bank" bitfld.long 0x408 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x408 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x40C "ILF3_IPB_n_407,Input buffer bank" bitfld.long 0x40C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x410 "ILF3_IPB_n_408,Input buffer bank" bitfld.long 0x410 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x410 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x414 "ILF3_IPB_n_409,Input buffer bank" bitfld.long 0x414 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x414 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x418 "ILF3_IPB_n_410,Input buffer bank" bitfld.long 0x418 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x418 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x41C "ILF3_IPB_n_411,Input buffer bank" bitfld.long 0x41C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x41C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x420 "ILF3_IPB_n_412,Input buffer bank" bitfld.long 0x420 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x420 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x424 "ILF3_IPB_n_413,Input buffer bank" bitfld.long 0x424 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x424 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x428 "ILF3_IPB_n_414,Input buffer bank" bitfld.long 0x428 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x428 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x42C "ILF3_IPB_n_415,Input buffer bank" bitfld.long 0x42C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x42C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x430 "ILF3_IPB_n_416,Input buffer bank" bitfld.long 0x430 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x430 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x434 "ILF3_IPB_n_417,Input buffer bank" bitfld.long 0x434 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x434 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x438 "ILF3_IPB_n_418,Input buffer bank" bitfld.long 0x438 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x438 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x43C "ILF3_IPB_n_419,Input buffer bank" bitfld.long 0x43C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x43C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x440 "ILF3_IPB_n_420,Input buffer bank" bitfld.long 0x440 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x440 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x444 "ILF3_IPB_n_421,Input buffer bank" bitfld.long 0x444 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x444 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x448 "ILF3_IPB_n_422,Input buffer bank" bitfld.long 0x448 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x448 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x44C "ILF3_IPB_n_423,Input buffer bank" bitfld.long 0x44C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x450 "ILF3_IPB_n_424,Input buffer bank" bitfld.long 0x450 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x450 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x454 "ILF3_IPB_n_425,Input buffer bank" bitfld.long 0x454 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x454 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x458 "ILF3_IPB_n_426,Input buffer bank" bitfld.long 0x458 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x458 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x45C "ILF3_IPB_n_427,Input buffer bank" bitfld.long 0x45C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x45C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x460 "ILF3_IPB_n_428,Input buffer bank" bitfld.long 0x460 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x460 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x464 "ILF3_IPB_n_429,Input buffer bank" bitfld.long 0x464 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x464 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x468 "ILF3_IPB_n_430,Input buffer bank" bitfld.long 0x468 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x468 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x46C "ILF3_IPB_n_431,Input buffer bank" bitfld.long 0x46C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x46C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x470 "ILF3_IPB_n_432,Input buffer bank" bitfld.long 0x470 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x470 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x474 "ILF3_IPB_n_433,Input buffer bank" bitfld.long 0x474 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x474 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x478 "ILF3_IPB_n_434,Input buffer bank" bitfld.long 0x478 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x478 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x47C "ILF3_IPB_n_435,Input buffer bank" bitfld.long 0x47C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x47C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x480 "ILF3_IPB_n_436,Input buffer bank" bitfld.long 0x480 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x480 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x484 "ILF3_IPB_n_437,Input buffer bank" bitfld.long 0x484 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x484 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x488 "ILF3_IPB_n_438,Input buffer bank" bitfld.long 0x488 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x488 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x48C "ILF3_IPB_n_439,Input buffer bank" bitfld.long 0x48C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x48C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x490 "ILF3_IPB_n_440,Input buffer bank" bitfld.long 0x490 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x490 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x494 "ILF3_IPB_n_441,Input buffer bank" bitfld.long 0x494 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x494 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x498 "ILF3_IPB_n_442,Input buffer bank" bitfld.long 0x498 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x498 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x49C "ILF3_IPB_n_443,Input buffer bank" bitfld.long 0x49C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x49C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A0 "ILF3_IPB_n_444,Input buffer bank" bitfld.long 0x4A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A4 "ILF3_IPB_n_445,Input buffer bank" bitfld.long 0x4A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A8 "ILF3_IPB_n_446,Input buffer bank" bitfld.long 0x4A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4AC "ILF3_IPB_n_447,Input buffer bank" bitfld.long 0x4AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B0 "ILF3_IPB_n_448,Input buffer bank" bitfld.long 0x4B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B4 "ILF3_IPB_n_449,Input buffer bank" bitfld.long 0x4B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B8 "ILF3_IPB_n_450,Input buffer bank" bitfld.long 0x4B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4BC "ILF3_IPB_n_451,Input buffer bank" bitfld.long 0x4BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C0 "ILF3_IPB_n_452,Input buffer bank" bitfld.long 0x4C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C4 "ILF3_IPB_n_453,Input buffer bank" bitfld.long 0x4C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C8 "ILF3_IPB_n_454,Input buffer bank" bitfld.long 0x4C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4CC "ILF3_IPB_n_455,Input buffer bank" bitfld.long 0x4CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D0 "ILF3_IPB_n_456,Input buffer bank" bitfld.long 0x4D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D4 "ILF3_IPB_n_457,Input buffer bank" bitfld.long 0x4D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D8 "ILF3_IPB_n_458,Input buffer bank" bitfld.long 0x4D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4DC "ILF3_IPB_n_459,Input buffer bank" bitfld.long 0x4DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E0 "ILF3_IPB_n_460,Input buffer bank" bitfld.long 0x4E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E4 "ILF3_IPB_n_461,Input buffer bank" bitfld.long 0x4E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E8 "ILF3_IPB_n_462,Input buffer bank" bitfld.long 0x4E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4EC "ILF3_IPB_n_463,Input buffer bank" bitfld.long 0x4EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F0 "ILF3_IPB_n_464,Input buffer bank" bitfld.long 0x4F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F4 "ILF3_IPB_n_465,Input buffer bank" bitfld.long 0x4F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F8 "ILF3_IPB_n_466,Input buffer bank" bitfld.long 0x4F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4FC "ILF3_IPB_n_467,Input buffer bank" bitfld.long 0x4FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x500 "ILF3_IPB_n_468,Input buffer bank" bitfld.long 0x500 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x500 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x504 "ILF3_IPB_n_469,Input buffer bank" bitfld.long 0x504 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x504 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x508 "ILF3_IPB_n_470,Input buffer bank" bitfld.long 0x508 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x508 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x50C "ILF3_IPB_n_471,Input buffer bank" bitfld.long 0x50C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x510 "ILF3_IPB_n_472,Input buffer bank" bitfld.long 0x510 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x510 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x514 "ILF3_IPB_n_473,Input buffer bank" bitfld.long 0x514 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x514 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x518 "ILF3_IPB_n_474,Input buffer bank" bitfld.long 0x518 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x518 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x51C "ILF3_IPB_n_475,Input buffer bank" bitfld.long 0x51C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x51C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x520 "ILF3_IPB_n_476,Input buffer bank" bitfld.long 0x520 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x520 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x524 "ILF3_IPB_n_477,Input buffer bank" bitfld.long 0x524 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x524 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x528 "ILF3_IPB_n_478,Input buffer bank" bitfld.long 0x528 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x528 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x52C "ILF3_IPB_n_479,Input buffer bank" bitfld.long 0x52C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x52C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x530 "ILF3_IPB_n_480,Input buffer bank" bitfld.long 0x530 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x530 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x534 "ILF3_IPB_n_481,Input buffer bank" bitfld.long 0x534 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x534 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x538 "ILF3_IPB_n_482,Input buffer bank" bitfld.long 0x538 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x538 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x53C "ILF3_IPB_n_483,Input buffer bank" bitfld.long 0x53C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x53C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x540 "ILF3_IPB_n_484,Input buffer bank" bitfld.long 0x540 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x540 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x544 "ILF3_IPB_n_485,Input buffer bank" bitfld.long 0x544 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x544 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x548 "ILF3_IPB_n_486,Input buffer bank" bitfld.long 0x548 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x548 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x54C "ILF3_IPB_n_487,Input buffer bank" bitfld.long 0x54C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x54C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x550 "ILF3_IPB_n_488,Input buffer bank" bitfld.long 0x550 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x550 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x554 "ILF3_IPB_n_489,Input buffer bank" bitfld.long 0x554 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x554 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x558 "ILF3_IPB_n_490,Input buffer bank" bitfld.long 0x558 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x558 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x55C "ILF3_IPB_n_491,Input buffer bank" bitfld.long 0x55C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x55C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x560 "ILF3_IPB_n_492,Input buffer bank" bitfld.long 0x560 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x560 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x564 "ILF3_IPB_n_493,Input buffer bank" bitfld.long 0x564 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x564 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x568 "ILF3_IPB_n_494,Input buffer bank" bitfld.long 0x568 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x568 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x56C "ILF3_IPB_n_495,Input buffer bank" bitfld.long 0x56C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x56C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x570 "ILF3_IPB_n_496,Input buffer bank" bitfld.long 0x570 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x570 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x574 "ILF3_IPB_n_497,Input buffer bank" bitfld.long 0x574 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x574 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x578 "ILF3_IPB_n_498,Input buffer bank" bitfld.long 0x578 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x578 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x57C "ILF3_IPB_n_499,Input buffer bank" bitfld.long 0x57C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x57C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x580 "ILF3_IPB_n_500,Input buffer bank" bitfld.long 0x580 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x580 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x584 "ILF3_IPB_n_501,Input buffer bank" bitfld.long 0x584 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x584 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x588 "ILF3_IPB_n_502,Input buffer bank" bitfld.long 0x588 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x588 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x58C "ILF3_IPB_n_503,Input buffer bank" bitfld.long 0x58C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x58C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x590 "ILF3_IPB_n_504,Input buffer bank" bitfld.long 0x590 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x590 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x594 "ILF3_IPB_n_505,Input buffer bank" bitfld.long 0x594 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x594 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x598 "ILF3_IPB_n_506,Input buffer bank" bitfld.long 0x598 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x598 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x59C "ILF3_IPB_n_507,Input buffer bank" bitfld.long 0x59C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x59C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A0 "ILF3_IPB_n_508,Input buffer bank" bitfld.long 0x5A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A4 "ILF3_IPB_n_509,Input buffer bank" bitfld.long 0x5A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A8 "ILF3_IPB_n_510,Input buffer bank" bitfld.long 0x5A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5AC "ILF3_IPB_n_511,Input buffer bank" bitfld.long 0x5AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B0 "ILF3_IPB_n_512,Input buffer bank" bitfld.long 0x5B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B4 "ILF3_IPB_n_513,Input buffer bank" bitfld.long 0x5B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B8 "ILF3_IPB_n_514,Input buffer bank" bitfld.long 0x5B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5BC "ILF3_IPB_n_515,Input buffer bank" bitfld.long 0x5BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C0 "ILF3_IPB_n_516,Input buffer bank" bitfld.long 0x5C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C4 "ILF3_IPB_n_517,Input buffer bank" bitfld.long 0x5C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C8 "ILF3_IPB_n_518,Input buffer bank" bitfld.long 0x5C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5CC "ILF3_IPB_n_519,Input buffer bank" bitfld.long 0x5CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D0 "ILF3_IPB_n_520,Input buffer bank" bitfld.long 0x5D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D4 "ILF3_IPB_n_521,Input buffer bank" bitfld.long 0x5D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D8 "ILF3_IPB_n_522,Input buffer bank" bitfld.long 0x5D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5DC "ILF3_IPB_n_523,Input buffer bank" bitfld.long 0x5DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E0 "ILF3_IPB_n_524,Input buffer bank" bitfld.long 0x5E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E4 "ILF3_IPB_n_525,Input buffer bank" bitfld.long 0x5E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E8 "ILF3_IPB_n_526,Input buffer bank" bitfld.long 0x5E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5EC "ILF3_IPB_n_527,Input buffer bank" bitfld.long 0x5EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F0 "ILF3_IPB_n_528,Input buffer bank" bitfld.long 0x5F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F4 "ILF3_IPB_n_529,Input buffer bank" bitfld.long 0x5F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F8 "ILF3_IPB_n_530,Input buffer bank" bitfld.long 0x5F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5FC "ILF3_IPB_n_531,Input buffer bank" bitfld.long 0x5FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x600 "ILF3_IPB_n_532,Input buffer bank" bitfld.long 0x600 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x600 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x604 "ILF3_IPB_n_533,Input buffer bank" bitfld.long 0x604 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x604 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x608 "ILF3_IPB_n_534,Input buffer bank" bitfld.long 0x608 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x608 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x60C "ILF3_IPB_n_535,Input buffer bank" bitfld.long 0x60C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x60C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x610 "ILF3_IPB_n_536,Input buffer bank" bitfld.long 0x610 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x610 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x614 "ILF3_IPB_n_537,Input buffer bank" bitfld.long 0x614 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x614 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x618 "ILF3_IPB_n_538,Input buffer bank" bitfld.long 0x618 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x618 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x61C "ILF3_IPB_n_539,Input buffer bank" bitfld.long 0x61C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x61C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x620 "ILF3_IPB_n_540,Input buffer bank" bitfld.long 0x620 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x620 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x624 "ILF3_IPB_n_541,Input buffer bank" bitfld.long 0x624 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x624 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x628 "ILF3_IPB_n_542,Input buffer bank" bitfld.long 0x628 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x628 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x62C "ILF3_IPB_n_543,Input buffer bank" bitfld.long 0x62C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x62C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x630 "ILF3_IPB_n_544,Input buffer bank" bitfld.long 0x630 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x630 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x634 "ILF3_IPB_n_545,Input buffer bank" bitfld.long 0x634 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x634 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x638 "ILF3_IPB_n_546,Input buffer bank" bitfld.long 0x638 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x638 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x63C "ILF3_IPB_n_547,Input buffer bank" bitfld.long 0x63C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x63C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x640 "ILF3_IPB_n_548,Input buffer bank" bitfld.long 0x640 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x640 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x644 "ILF3_IPB_n_549,Input buffer bank" bitfld.long 0x644 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x644 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x648 "ILF3_IPB_n_550,Input buffer bank" bitfld.long 0x648 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x648 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x64C "ILF3_IPB_n_551,Input buffer bank" bitfld.long 0x64C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x64C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x650 "ILF3_IPB_n_552,Input buffer bank" bitfld.long 0x650 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x650 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x654 "ILF3_IPB_n_553,Input buffer bank" bitfld.long 0x654 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x654 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x658 "ILF3_IPB_n_554,Input buffer bank" bitfld.long 0x658 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x658 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x65C "ILF3_IPB_n_555,Input buffer bank" bitfld.long 0x65C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x65C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x660 "ILF3_IPB_n_556,Input buffer bank" bitfld.long 0x660 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x660 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x664 "ILF3_IPB_n_557,Input buffer bank" bitfld.long 0x664 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x664 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x668 "ILF3_IPB_n_558,Input buffer bank" bitfld.long 0x668 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x668 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x66C "ILF3_IPB_n_559,Input buffer bank" bitfld.long 0x66C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x66C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x670 "ILF3_IPB_n_560,Input buffer bank" bitfld.long 0x670 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x670 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x674 "ILF3_IPB_n_561,Input buffer bank" bitfld.long 0x674 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x674 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x678 "ILF3_IPB_n_562,Input buffer bank" bitfld.long 0x678 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x678 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x67C "ILF3_IPB_n_563,Input buffer bank" bitfld.long 0x67C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x67C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x680 "ILF3_IPB_n_564,Input buffer bank" bitfld.long 0x680 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x680 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x684 "ILF3_IPB_n_565,Input buffer bank" bitfld.long 0x684 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x684 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x688 "ILF3_IPB_n_566,Input buffer bank" bitfld.long 0x688 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x688 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x68C "ILF3_IPB_n_567,Input buffer bank" bitfld.long 0x68C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x68C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x690 "ILF3_IPB_n_568,Input buffer bank" bitfld.long 0x690 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x690 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x694 "ILF3_IPB_n_569,Input buffer bank" bitfld.long 0x694 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x694 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x698 "ILF3_IPB_n_570,Input buffer bank" bitfld.long 0x698 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x698 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x69C "ILF3_IPB_n_571,Input buffer bank" bitfld.long 0x69C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x69C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A0 "ILF3_IPB_n_572,Input buffer bank" bitfld.long 0x6A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A4 "ILF3_IPB_n_573,Input buffer bank" bitfld.long 0x6A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A8 "ILF3_IPB_n_574,Input buffer bank" bitfld.long 0x6A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6AC "ILF3_IPB_n_575,Input buffer bank" bitfld.long 0x6AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B0 "ILF3_IPB_n_576,Input buffer bank" bitfld.long 0x6B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B4 "ILF3_IPB_n_577,Input buffer bank" bitfld.long 0x6B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B8 "ILF3_IPB_n_578,Input buffer bank" bitfld.long 0x6B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6BC "ILF3_IPB_n_579,Input buffer bank" bitfld.long 0x6BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C0 "ILF3_IPB_n_580,Input buffer bank" bitfld.long 0x6C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C4 "ILF3_IPB_n_581,Input buffer bank" bitfld.long 0x6C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C8 "ILF3_IPB_n_582,Input buffer bank" bitfld.long 0x6C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6CC "ILF3_IPB_n_583,Input buffer bank" bitfld.long 0x6CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D0 "ILF3_IPB_n_584,Input buffer bank" bitfld.long 0x6D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D4 "ILF3_IPB_n_585,Input buffer bank" bitfld.long 0x6D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D8 "ILF3_IPB_n_586,Input buffer bank" bitfld.long 0x6D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6DC "ILF3_IPB_n_587,Input buffer bank" bitfld.long 0x6DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E0 "ILF3_IPB_n_588,Input buffer bank" bitfld.long 0x6E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E4 "ILF3_IPB_n_589,Input buffer bank" bitfld.long 0x6E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E8 "ILF3_IPB_n_590,Input buffer bank" bitfld.long 0x6E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6EC "ILF3_IPB_n_591,Input buffer bank" bitfld.long 0x6EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F0 "ILF3_IPB_n_592,Input buffer bank" bitfld.long 0x6F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F4 "ILF3_IPB_n_593,Input buffer bank" bitfld.long 0x6F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F8 "ILF3_IPB_n_594,Input buffer bank" bitfld.long 0x6F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6FC "ILF3_IPB_n_595,Input buffer bank" bitfld.long 0x6FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x700 "ILF3_IPB_n_596,Input buffer bank" bitfld.long 0x700 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x700 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x704 "ILF3_IPB_n_597,Input buffer bank" bitfld.long 0x704 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x704 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x708 "ILF3_IPB_n_598,Input buffer bank" bitfld.long 0x708 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x708 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x70C "ILF3_IPB_n_599,Input buffer bank" bitfld.long 0x70C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x70C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x710 "ILF3_IPB_n_600,Input buffer bank" bitfld.long 0x710 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x710 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x714 "ILF3_IPB_n_601,Input buffer bank" bitfld.long 0x714 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x714 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x718 "ILF3_IPB_n_602,Input buffer bank" bitfld.long 0x718 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x718 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x71C "ILF3_IPB_n_603,Input buffer bank" bitfld.long 0x71C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x71C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x720 "ILF3_IPB_n_604,Input buffer bank" bitfld.long 0x720 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x720 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x724 "ILF3_IPB_n_605,Input buffer bank" bitfld.long 0x724 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x724 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x728 "ILF3_IPB_n_606,Input buffer bank" bitfld.long 0x728 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x728 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x72C "ILF3_IPB_n_607,Input buffer bank" bitfld.long 0x72C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x72C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x730 "ILF3_IPB_n_608,Input buffer bank" bitfld.long 0x730 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x730 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x734 "ILF3_IPB_n_609,Input buffer bank" bitfld.long 0x734 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x734 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x738 "ILF3_IPB_n_610,Input buffer bank" bitfld.long 0x738 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x738 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x73C "ILF3_IPB_n_611,Input buffer bank" bitfld.long 0x73C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x73C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x740 "ILF3_IPB_n_612,Input buffer bank" bitfld.long 0x740 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x740 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x744 "ILF3_IPB_n_613,Input buffer bank" bitfld.long 0x744 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x744 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x748 "ILF3_IPB_n_614,Input buffer bank" bitfld.long 0x748 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x748 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x74C "ILF3_IPB_n_615,Input buffer bank" bitfld.long 0x74C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x74C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x750 "ILF3_IPB_n_616,Input buffer bank" bitfld.long 0x750 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x750 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x754 "ILF3_IPB_n_617,Input buffer bank" bitfld.long 0x754 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x754 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x758 "ILF3_IPB_n_618,Input buffer bank" bitfld.long 0x758 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x758 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x75C "ILF3_IPB_n_619,Input buffer bank" bitfld.long 0x75C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x75C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x760 "ILF3_IPB_n_620,Input buffer bank" bitfld.long 0x760 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x760 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x764 "ILF3_IPB_n_621,Input buffer bank" bitfld.long 0x764 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x764 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x768 "ILF3_IPB_n_622,Input buffer bank" bitfld.long 0x768 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x768 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x76C "ILF3_IPB_n_623,Input buffer bank" bitfld.long 0x76C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x76C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x770 "ILF3_IPB_n_624,Input buffer bank" bitfld.long 0x770 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x770 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x774 "ILF3_IPB_n_625,Input buffer bank" bitfld.long 0x774 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x774 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x778 "ILF3_IPB_n_626,Input buffer bank" bitfld.long 0x778 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x778 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x77C "ILF3_IPB_n_627,Input buffer bank" bitfld.long 0x77C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x77C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x780 "ILF3_IPB_n_628,Input buffer bank" bitfld.long 0x780 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x780 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x784 "ILF3_IPB_n_629,Input buffer bank" bitfld.long 0x784 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x784 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x788 "ILF3_IPB_n_630,Input buffer bank" bitfld.long 0x788 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x788 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x78C "ILF3_IPB_n_631,Input buffer bank" bitfld.long 0x78C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x790 "ILF3_IPB_n_632,Input buffer bank" bitfld.long 0x790 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x790 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x794 "ILF3_IPB_n_633,Input buffer bank" bitfld.long 0x794 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x794 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x798 "ILF3_IPB_n_634,Input buffer bank" bitfld.long 0x798 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x798 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x79C "ILF3_IPB_n_635,Input buffer bank" bitfld.long 0x79C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x79C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A0 "ILF3_IPB_n_636,Input buffer bank" bitfld.long 0x7A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A4 "ILF3_IPB_n_637,Input buffer bank" bitfld.long 0x7A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A8 "ILF3_IPB_n_638,Input buffer bank" bitfld.long 0x7A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7AC "ILF3_IPB_n_639,Input buffer bank" bitfld.long 0x7AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B0 "ILF3_IPB_n_640,Input buffer bank" bitfld.long 0x7B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B4 "ILF3_IPB_n_641,Input buffer bank" bitfld.long 0x7B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B8 "ILF3_IPB_n_642,Input buffer bank" bitfld.long 0x7B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7BC "ILF3_IPB_n_643,Input buffer bank" bitfld.long 0x7BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C0 "ILF3_IPB_n_644,Input buffer bank" bitfld.long 0x7C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C4 "ILF3_IPB_n_645,Input buffer bank" bitfld.long 0x7C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C8 "ILF3_IPB_n_646,Input buffer bank" bitfld.long 0x7C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7CC "ILF3_IPB_n_647,Input buffer bank" bitfld.long 0x7CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D0 "ILF3_IPB_n_648,Input buffer bank" bitfld.long 0x7D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D4 "ILF3_IPB_n_649,Input buffer bank" bitfld.long 0x7D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D8 "ILF3_IPB_n_650,Input buffer bank" bitfld.long 0x7D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7DC "ILF3_IPB_n_651,Input buffer bank" bitfld.long 0x7DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E0 "ILF3_IPB_n_652,Input buffer bank" bitfld.long 0x7E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E4 "ILF3_IPB_n_653,Input buffer bank" bitfld.long 0x7E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E8 "ILF3_IPB_n_654,Input buffer bank" bitfld.long 0x7E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7EC "ILF3_IPB_n_655,Input buffer bank" bitfld.long 0x7EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F0 "ILF3_IPB_n_656,Input buffer bank" bitfld.long 0x7F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F4 "ILF3_IPB_n_657,Input buffer bank" bitfld.long 0x7F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F8 "ILF3_IPB_n_658,Input buffer bank" bitfld.long 0x7F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7FC "ILF3_IPB_n_659,Input buffer bank" bitfld.long 0x7FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x800 "ILF3_IPB_n_660,Input buffer bank" bitfld.long 0x800 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x800 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x804 "ILF3_IPB_n_661,Input buffer bank" bitfld.long 0x804 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x804 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x808 "ILF3_IPB_n_662,Input buffer bank" bitfld.long 0x808 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x808 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x80C "ILF3_IPB_n_663,Input buffer bank" bitfld.long 0x80C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x810 "ILF3_IPB_n_664,Input buffer bank" bitfld.long 0x810 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x810 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x814 "ILF3_IPB_n_665,Input buffer bank" bitfld.long 0x814 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x814 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x818 "ILF3_IPB_n_666,Input buffer bank" bitfld.long 0x818 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x818 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x81C "ILF3_IPB_n_667,Input buffer bank" bitfld.long 0x81C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x81C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x820 "ILF3_IPB_n_668,Input buffer bank" bitfld.long 0x820 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x820 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x824 "ILF3_IPB_n_669,Input buffer bank" bitfld.long 0x824 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x824 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x828 "ILF3_IPB_n_670,Input buffer bank" bitfld.long 0x828 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x828 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x82C "ILF3_IPB_n_671,Input buffer bank" bitfld.long 0x82C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x82C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x830 "ILF3_IPB_n_672,Input buffer bank" bitfld.long 0x830 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x830 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x834 "ILF3_IPB_n_673,Input buffer bank" bitfld.long 0x834 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x834 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x838 "ILF3_IPB_n_674,Input buffer bank" bitfld.long 0x838 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x838 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x83C "ILF3_IPB_n_675,Input buffer bank" bitfld.long 0x83C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x83C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x840 "ILF3_IPB_n_676,Input buffer bank" bitfld.long 0x840 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x840 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x844 "ILF3_IPB_n_677,Input buffer bank" bitfld.long 0x844 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x844 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x848 "ILF3_IPB_n_678,Input buffer bank" bitfld.long 0x848 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x848 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x84C "ILF3_IPB_n_679,Input buffer bank" bitfld.long 0x84C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x84C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x850 "ILF3_IPB_n_680,Input buffer bank" bitfld.long 0x850 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x850 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x854 "ILF3_IPB_n_681,Input buffer bank" bitfld.long 0x854 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x854 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x858 "ILF3_IPB_n_682,Input buffer bank" bitfld.long 0x858 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x858 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x85C "ILF3_IPB_n_683,Input buffer bank" bitfld.long 0x85C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x85C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x860 "ILF3_IPB_n_684,Input buffer bank" bitfld.long 0x860 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x860 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x864 "ILF3_IPB_n_685,Input buffer bank" bitfld.long 0x864 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x864 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x868 "ILF3_IPB_n_686,Input buffer bank" bitfld.long 0x868 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x868 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x86C "ILF3_IPB_n_687,Input buffer bank" bitfld.long 0x86C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x86C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x870 "ILF3_IPB_n_688,Input buffer bank" bitfld.long 0x870 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x870 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x874 "ILF3_IPB_n_689,Input buffer bank" bitfld.long 0x874 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x874 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x878 "ILF3_IPB_n_690,Input buffer bank" bitfld.long 0x878 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x878 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x87C "ILF3_IPB_n_691,Input buffer bank" bitfld.long 0x87C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x87C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x880 "ILF3_IPB_n_692,Input buffer bank" bitfld.long 0x880 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x880 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x884 "ILF3_IPB_n_693,Input buffer bank" bitfld.long 0x884 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x884 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x888 "ILF3_IPB_n_694,Input buffer bank" bitfld.long 0x888 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x888 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x88C "ILF3_IPB_n_695,Input buffer bank" bitfld.long 0x88C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x88C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x890 "ILF3_IPB_n_696,Input buffer bank" bitfld.long 0x890 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x890 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x894 "ILF3_IPB_n_697,Input buffer bank" bitfld.long 0x894 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x894 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x898 "ILF3_IPB_n_698,Input buffer bank" bitfld.long 0x898 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x898 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x89C "ILF3_IPB_n_699,Input buffer bank" bitfld.long 0x89C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x89C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A0 "ILF3_IPB_n_700,Input buffer bank" bitfld.long 0x8A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A4 "ILF3_IPB_n_701,Input buffer bank" bitfld.long 0x8A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A8 "ILF3_IPB_n_702,Input buffer bank" bitfld.long 0x8A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8AC "ILF3_IPB_n_703,Input buffer bank" bitfld.long 0x8AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_15" group.long 0x204++0x03 line.long 0x00 "ILF3_BS_l_15,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x458++0x03 line.long 0x00 "ILF3_IPB_n_15,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x88++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_15,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x164++0x03 line.long 0x00 "ILF3_QP_IDX_j_15,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x11C++0x03 line.long 0x00 "ILF3_QP_m_15,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_16" group.long 0x208++0x03 line.long 0x00 "ILF3_BS_l_16,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x45C++0x03 line.long 0x00 "ILF3_IPB_n_16,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x168++0x03 line.long 0x00 "ILF3_QP_IDX_j_16,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "ILF3_QP_m_16,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_17" group.long 0x20C++0x03 line.long 0x00 "ILF3_BS_l_17,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x460++0x03 line.long 0x00 "ILF3_IPB_n_17,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x16C++0x03 line.long 0x00 "ILF3_QP_IDX_j_17,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "ILF3_QP_m_17,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_18" group.long 0x210++0x03 line.long 0x00 "ILF3_BS_l_18,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x464++0x03 line.long 0x00 "ILF3_IPB_n_18,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x170++0x03 line.long 0x00 "ILF3_QP_IDX_j_18,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_19" group.long 0x214++0x03 line.long 0x00 "ILF3_BS_l_19,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x468++0x03 line.long 0x00 "ILF3_IPB_n_19,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x174++0x03 line.long 0x00 "ILF3_QP_IDX_j_19,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" group.long 0x1D0++0x03 line.long 0x00 "ILF3_BS_l_2,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x424++0x03 line.long 0x00 "ILF3_IPB_n_2,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x9C++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_2,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_2,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x54++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_2,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x130++0x03 line.long 0x00 "ILF3_QP_IDX_j_2,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE8++0x03 line.long 0x00 "ILF3_QP_m_2,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC4++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_2,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_20" group.long 0x218++0x03 line.long 0x00 "ILF3_BS_l_20,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x46C++0x03 line.long 0x00 "ILF3_IPB_n_20,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x178++0x03 line.long 0x00 "ILF3_QP_IDX_j_20,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_21" group.long 0x21C++0x03 line.long 0x00 "ILF3_BS_l_21,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x470++0x03 line.long 0x00 "ILF3_IPB_n_21,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x17C++0x03 line.long 0x00 "ILF3_QP_IDX_j_21,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_22" group.long 0x220++0x03 line.long 0x00 "ILF3_BS_l_22,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x474++0x03 line.long 0x00 "ILF3_IPB_n_22,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x180++0x03 line.long 0x00 "ILF3_QP_IDX_j_22,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_23" group.long 0x224++0x03 line.long 0x00 "ILF3_BS_l_23,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x478++0x03 line.long 0x00 "ILF3_IPB_n_23,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x184++0x03 line.long 0x00 "ILF3_QP_IDX_j_23,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_24" group.long 0x228++0x03 line.long 0x00 "ILF3_BS_l_24,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x47C++0x03 line.long 0x00 "ILF3_IPB_n_24,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x188++0x03 line.long 0x00 "ILF3_QP_IDX_j_24,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_25" group.long 0x22C++0x03 line.long 0x00 "ILF3_BS_l_25,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x480++0x03 line.long 0x00 "ILF3_IPB_n_25,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x18C++0x03 line.long 0x00 "ILF3_QP_IDX_j_25,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_26" group.long 0x230++0x03 line.long 0x00 "ILF3_BS_l_26,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x484++0x03 line.long 0x00 "ILF3_IPB_n_26,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x190++0x03 line.long 0x00 "ILF3_QP_IDX_j_26,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_27" group.long 0x234++0x03 line.long 0x00 "ILF3_BS_l_27,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x488++0x03 line.long 0x00 "ILF3_IPB_n_27,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x194++0x03 line.long 0x00 "ILF3_QP_IDX_j_27,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_28" group.long 0x238++0x03 line.long 0x00 "ILF3_BS_l_28,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48C++0x03 line.long 0x00 "ILF3_IPB_n_28,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x198++0x03 line.long 0x00 "ILF3_QP_IDX_j_28,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_29" group.long 0x23C++0x03 line.long 0x00 "ILF3_BS_l_29,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x490++0x03 line.long 0x00 "ILF3_IPB_n_29,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x19C++0x03 line.long 0x00 "ILF3_QP_IDX_j_29,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" group.long 0x1D4++0x03 line.long 0x00 "ILF3_BS_l_3,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x03 line.long 0x00 "ILF3_IPB_n_3,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0xA0++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x58++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x134++0x03 line.long 0x00 "ILF3_QP_IDX_j_3,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "ILF3_QP_m_3,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_30" group.long 0x240++0x03 line.long 0x00 "ILF3_BS_l_30,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x494++0x03 line.long 0x00 "ILF3_IPB_n_30,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A0++0x03 line.long 0x00 "ILF3_QP_IDX_j_30,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_31" group.long 0x244++0x03 line.long 0x00 "ILF3_BS_l_31,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x498++0x03 line.long 0x00 "ILF3_IPB_n_31,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A4++0x03 line.long 0x00 "ILF3_QP_IDX_j_31,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_32" group.long 0x248++0x03 line.long 0x00 "ILF3_BS_l_32,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x49C++0x03 line.long 0x00 "ILF3_IPB_n_32,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A8++0x03 line.long 0x00 "ILF3_QP_IDX_j_32,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_33" group.long 0x24C++0x03 line.long 0x00 "ILF3_BS_l_33,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A0++0x03 line.long 0x00 "ILF3_IPB_n_33,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1AC++0x03 line.long 0x00 "ILF3_QP_IDX_j_33,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_34" group.long 0x250++0x03 line.long 0x00 "ILF3_BS_l_34,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A4++0x03 line.long 0x00 "ILF3_IPB_n_34,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B0++0x03 line.long 0x00 "ILF3_QP_IDX_j_34,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_35" group.long 0x254++0x03 line.long 0x00 "ILF3_BS_l_35,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A8++0x03 line.long 0x00 "ILF3_IPB_n_35,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B4++0x03 line.long 0x00 "ILF3_QP_IDX_j_35,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_36" group.long 0x258++0x03 line.long 0x00 "ILF3_BS_l_36,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4AC++0x03 line.long 0x00 "ILF3_IPB_n_36,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B8++0x03 line.long 0x00 "ILF3_QP_IDX_j_36,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_37" group.long 0x25C++0x03 line.long 0x00 "ILF3_BS_l_37,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B0++0x03 line.long 0x00 "ILF3_IPB_n_37,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1BC++0x03 line.long 0x00 "ILF3_QP_IDX_j_37,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_38" group.long 0x260++0x03 line.long 0x00 "ILF3_BS_l_38,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B4++0x03 line.long 0x00 "ILF3_IPB_n_38,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1C0++0x03 line.long 0x00 "ILF3_QP_IDX_j_38,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_39" group.long 0x264++0x03 line.long 0x00 "ILF3_BS_l_39,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B8++0x03 line.long 0x00 "ILF3_IPB_n_39,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1C4++0x03 line.long 0x00 "ILF3_QP_IDX_j_39,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_4" group.long 0x1D8++0x03 line.long 0x00 "ILF3_BS_l_4,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x03 line.long 0x00 "ILF3_IPB_n_4,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x5C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_4,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x138++0x03 line.long 0x00 "ILF3_QP_IDX_j_4,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "ILF3_QP_m_4,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_40" group.long 0x268++0x03 line.long 0x00 "ILF3_BS_l_40,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4BC++0x03 line.long 0x00 "ILF3_IPB_n_40,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_41" group.long 0x26C++0x03 line.long 0x00 "ILF3_BS_l_41,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C0++0x03 line.long 0x00 "ILF3_IPB_n_41,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_42" group.long 0x270++0x03 line.long 0x00 "ILF3_BS_l_42,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C4++0x03 line.long 0x00 "ILF3_IPB_n_42,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_43" group.long 0x274++0x03 line.long 0x00 "ILF3_BS_l_43,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C8++0x03 line.long 0x00 "ILF3_IPB_n_43,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_44" group.long 0x278++0x03 line.long 0x00 "ILF3_BS_l_44,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4CC++0x03 line.long 0x00 "ILF3_IPB_n_44,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_45" group.long 0x27C++0x03 line.long 0x00 "ILF3_BS_l_45,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D0++0x03 line.long 0x00 "ILF3_IPB_n_45,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_46" group.long 0x280++0x03 line.long 0x00 "ILF3_BS_l_46,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D4++0x03 line.long 0x00 "ILF3_IPB_n_46,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_47" group.long 0x284++0x03 line.long 0x00 "ILF3_BS_l_47,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D8++0x03 line.long 0x00 "ILF3_IPB_n_47,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_48" group.long 0x288++0x03 line.long 0x00 "ILF3_BS_l_48,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4DC++0x03 line.long 0x00 "ILF3_IPB_n_48,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_49" group.long 0x28C++0x03 line.long 0x00 "ILF3_BS_l_49,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E0++0x03 line.long 0x00 "ILF3_IPB_n_49,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_5" group.long 0x1DC++0x03 line.long 0x00 "ILF3_BS_l_5,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x430++0x03 line.long 0x00 "ILF3_IPB_n_5,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x60++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_5,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x13C++0x03 line.long 0x00 "ILF3_QP_IDX_j_5,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF4++0x03 line.long 0x00 "ILF3_QP_m_5,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_50" group.long 0x290++0x03 line.long 0x00 "ILF3_BS_l_50,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E4++0x03 line.long 0x00 "ILF3_IPB_n_50,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_51" group.long 0x294++0x03 line.long 0x00 "ILF3_BS_l_51,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "ILF3_IPB_n_51,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_52" group.long 0x298++0x03 line.long 0x00 "ILF3_BS_l_52,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4EC++0x03 line.long 0x00 "ILF3_IPB_n_52,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_53" group.long 0x29C++0x03 line.long 0x00 "ILF3_BS_l_53,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F0++0x03 line.long 0x00 "ILF3_IPB_n_53,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_54" group.long 0x2A0++0x03 line.long 0x00 "ILF3_BS_l_54,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F4++0x03 line.long 0x00 "ILF3_IPB_n_54,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_55" group.long 0x2A4++0x03 line.long 0x00 "ILF3_BS_l_55,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F8++0x03 line.long 0x00 "ILF3_IPB_n_55,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_56" group.long 0x2A8++0x03 line.long 0x00 "ILF3_BS_l_56,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4FC++0x03 line.long 0x00 "ILF3_IPB_n_56,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_57" group.long 0x2AC++0x03 line.long 0x00 "ILF3_BS_l_57,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x500++0x03 line.long 0x00 "ILF3_IPB_n_57,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_58" group.long 0x2B0++0x03 line.long 0x00 "ILF3_BS_l_58,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x504++0x03 line.long 0x00 "ILF3_IPB_n_58,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_59" group.long 0x2B4++0x03 line.long 0x00 "ILF3_BS_l_59,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x508++0x03 line.long 0x00 "ILF3_IPB_n_59,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_6" group.long 0x1E0++0x03 line.long 0x00 "ILF3_BS_l_6,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x434++0x03 line.long 0x00 "ILF3_IPB_n_6,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x64++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_6,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x140++0x03 line.long 0x00 "ILF3_QP_IDX_j_6,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF8++0x03 line.long 0x00 "ILF3_QP_m_6,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_60" group.long 0x2B8++0x03 line.long 0x00 "ILF3_BS_l_60,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50C++0x03 line.long 0x00 "ILF3_IPB_n_60,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_61" group.long 0x2BC++0x03 line.long 0x00 "ILF3_BS_l_61,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x510++0x03 line.long 0x00 "ILF3_IPB_n_61,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_62" group.long 0x2C0++0x03 line.long 0x00 "ILF3_BS_l_62,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x514++0x03 line.long 0x00 "ILF3_IPB_n_62,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_63" group.long 0x2C4++0x03 line.long 0x00 "ILF3_BS_l_63,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x518++0x03 line.long 0x00 "ILF3_IPB_n_63,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_64" group.long 0x2C8++0x03 line.long 0x00 "ILF3_BS_l_64,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x51C++0x03 line.long 0x00 "ILF3_IPB_n_64,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_65" group.long 0x2CC++0x03 line.long 0x00 "ILF3_BS_l_65,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x520++0x03 line.long 0x00 "ILF3_IPB_n_65,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_66" group.long 0x2D0++0x03 line.long 0x00 "ILF3_BS_l_66,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x524++0x03 line.long 0x00 "ILF3_IPB_n_66,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_67" group.long 0x2D4++0x03 line.long 0x00 "ILF3_BS_l_67,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x528++0x03 line.long 0x00 "ILF3_IPB_n_67,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_68" group.long 0x2D8++0x03 line.long 0x00 "ILF3_BS_l_68,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x52C++0x03 line.long 0x00 "ILF3_IPB_n_68,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_69" group.long 0x2DC++0x03 line.long 0x00 "ILF3_BS_l_69,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x530++0x03 line.long 0x00 "ILF3_IPB_n_69,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_7" group.long 0x1E4++0x03 line.long 0x00 "ILF3_BS_l_7,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x438++0x03 line.long 0x00 "ILF3_IPB_n_7,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x68++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_7,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x144++0x03 line.long 0x00 "ILF3_QP_IDX_j_7,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xFC++0x03 line.long 0x00 "ILF3_QP_m_7,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_70" group.long 0x2E0++0x03 line.long 0x00 "ILF3_BS_l_70,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x534++0x03 line.long 0x00 "ILF3_IPB_n_70,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_71" group.long 0x2E4++0x03 line.long 0x00 "ILF3_BS_l_71,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x538++0x03 line.long 0x00 "ILF3_IPB_n_71,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_72" group.long 0x2E8++0x03 line.long 0x00 "ILF3_BS_l_72,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x53C++0x03 line.long 0x00 "ILF3_IPB_n_72,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_73" group.long 0x2EC++0x03 line.long 0x00 "ILF3_BS_l_73,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x540++0x03 line.long 0x00 "ILF3_IPB_n_73,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_74" group.long 0x2F0++0x03 line.long 0x00 "ILF3_BS_l_74,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x544++0x03 line.long 0x00 "ILF3_IPB_n_74,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_75" group.long 0x2F4++0x03 line.long 0x00 "ILF3_BS_l_75,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x548++0x03 line.long 0x00 "ILF3_IPB_n_75,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_76" group.long 0x2F8++0x03 line.long 0x00 "ILF3_BS_l_76,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54C++0x03 line.long 0x00 "ILF3_IPB_n_76,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_77" group.long 0x2FC++0x03 line.long 0x00 "ILF3_BS_l_77,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x550++0x03 line.long 0x00 "ILF3_IPB_n_77,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_78" group.long 0x300++0x03 line.long 0x00 "ILF3_BS_l_78,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x554++0x03 line.long 0x00 "ILF3_IPB_n_78,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_79" group.long 0x304++0x03 line.long 0x00 "ILF3_BS_l_79,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x558++0x03 line.long 0x00 "ILF3_IPB_n_79,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_8" group.long 0x1E8++0x03 line.long 0x00 "ILF3_BS_l_8,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43C++0x03 line.long 0x00 "ILF3_IPB_n_8,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x6C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_8,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x148++0x03 line.long 0x00 "ILF3_QP_IDX_j_8,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x100++0x03 line.long 0x00 "ILF3_QP_m_8,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_80" group.long 0x308++0x03 line.long 0x00 "ILF3_BS_l_80,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x55C++0x03 line.long 0x00 "ILF3_IPB_n_80,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_81" group.long 0x30C++0x03 line.long 0x00 "ILF3_BS_l_81,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x560++0x03 line.long 0x00 "ILF3_IPB_n_81,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_82" group.long 0x310++0x03 line.long 0x00 "ILF3_BS_l_82,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x564++0x03 line.long 0x00 "ILF3_IPB_n_82,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_83" group.long 0x314++0x03 line.long 0x00 "ILF3_BS_l_83,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x568++0x03 line.long 0x00 "ILF3_IPB_n_83,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_84" group.long 0x318++0x03 line.long 0x00 "ILF3_BS_l_84,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x56C++0x03 line.long 0x00 "ILF3_IPB_n_84,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_85" group.long 0x31C++0x03 line.long 0x00 "ILF3_BS_l_85,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x570++0x03 line.long 0x00 "ILF3_IPB_n_85,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_86" group.long 0x320++0x03 line.long 0x00 "ILF3_BS_l_86,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x574++0x03 line.long 0x00 "ILF3_IPB_n_86,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_87" group.long 0x324++0x03 line.long 0x00 "ILF3_BS_l_87,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x578++0x03 line.long 0x00 "ILF3_IPB_n_87,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_88" group.long 0x328++0x03 line.long 0x00 "ILF3_BS_l_88,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x57C++0x03 line.long 0x00 "ILF3_IPB_n_88,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_89" group.long 0x32C++0x03 line.long 0x00 "ILF3_BS_l_89,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x580++0x03 line.long 0x00 "ILF3_IPB_n_89,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_9" group.long 0x1EC++0x03 line.long 0x00 "ILF3_BS_l_9,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x440++0x03 line.long 0x00 "ILF3_IPB_n_9,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x70++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_9,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x14C++0x03 line.long 0x00 "ILF3_QP_IDX_j_9,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x104++0x03 line.long 0x00 "ILF3_QP_m_9,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_90" group.long 0x330++0x03 line.long 0x00 "ILF3_BS_l_90,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x584++0x03 line.long 0x00 "ILF3_IPB_n_90,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_91" group.long 0x334++0x03 line.long 0x00 "ILF3_BS_l_91,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x588++0x03 line.long 0x00 "ILF3_IPB_n_91,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_92" group.long 0x338++0x03 line.long 0x00 "ILF3_BS_l_92,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58C++0x03 line.long 0x00 "ILF3_IPB_n_92,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_93" group.long 0x33C++0x03 line.long 0x00 "ILF3_BS_l_93,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x590++0x03 line.long 0x00 "ILF3_IPB_n_93,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_94" group.long 0x340++0x03 line.long 0x00 "ILF3_BS_l_94,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x594++0x03 line.long 0x00 "ILF3_IPB_n_94,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_95" group.long 0x344++0x03 line.long 0x00 "ILF3_BS_l_95,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x598++0x03 line.long 0x00 "ILF3_IPB_n_95,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_96" group.long 0x348++0x03 line.long 0x00 "ILF3_BS_l_96,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x59C++0x03 line.long 0x00 "ILF3_IPB_n_96,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_97" group.long 0x34C++0x03 line.long 0x00 "ILF3_BS_l_97,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A0++0x03 line.long 0x00 "ILF3_IPB_n_97,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_98" group.long 0x350++0x03 line.long 0x00 "ILF3_BS_l_98,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A4++0x03 line.long 0x00 "ILF3_IPB_n_98,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_99" group.long 0x354++0x03 line.long 0x00 "ILF3_BS_l_99,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A8++0x03 line.long 0x00 "ILF3_IPB_n_99,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end group.long 0xFFC++0x03 line.long 0x00 "ILF3_COMMAND,ILF3 command register: A write to this register decodes a command" bitfld.long 0x00 0.--2. "CMD,DATA/COMMAND 0x1 -> Start() 0x2 -> Stop() 0x3 -> DbgEn() 0x4 -> DbgDis() 0x5 -> DbgStep()" "0,1,2,3,4,5,6,7" group.long 0x30++0x03 line.long 0x00 "ILF3_CONFIG,Configuration register" hexmask.long.byte 0x00 24.--31. 1. "AUTOINCCOUNTER,This field indicates the current increment in MB for the auto-increment mechanism" bitfld.long 0x00 17.--18. "MBINFO_SIZE,Selects one of the three different MBinfo sizes to be loaded" "MBINFO_SIZE_0,MBINFO_SIZE_1,MBINFO_SIZE_2,MBINFO_SIZE_3" newline bitfld.long 0x00 16. "IRQAUTOCLEAR_EN," "0,1" hexmask.long.byte 0x00 8.--15. 1. "CODEC,Indicates the codec to be used" newline bitfld.long 0x00 0.--4. "PPA_TASK,Bit" "Load MB info Bit,Compute BS,Load MB,Filter MB,Store MB,?..." group.long 0x18++0x03 line.long 0x00 "ILF3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x28++0x03 line.long 0x00 "ILF3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x24++0x03 line.long 0x00 "ILF3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x20++0x03 line.long 0x00 "ILF3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0x1C++0x03 line.long 0x00 "ILF3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0xB0++0x03 line.long 0x00 "ILF3_MBCONFIG_AUTOINC,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 11. "AUTOINC,This bit must set to 1 to activate the auto-increment scheme" "0,1" bitfld.long 0x00 8.--10. "PIXEL_FORMAT,This field indicates the number of pixel rows in the top-row buffer and also the number of rows of 8-bit pixels and 16-bit pixels (VC-1 case with OVT activated)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_COUNT,Maximum value of Counter for auto-increment" repeat 2. (list 0123. 4567. )(list 0x00 0x04 ) group.long ($2+0x8C)++0x03 line.long 0x00 "ILF3_MBCONFIG_COEFFICIENTS$1,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.byte 0x00 24.--31. 1. "COEFF3,GDP coefficient 3" hexmask.long.byte 0x00 16.--23. 1. "COEFF2,GDP coefficient 2" newline hexmask.long.byte 0x00 8.--15. 1. "COEFF1,GDP coefficient 1" hexmask.long.byte 0x00 0.--7. 1. "COEFF0,GDP coefficient 0" repeat.end group.long 0xB4++0x03 line.long 0x00 "ILF3_MBCONFIG_NEXTMBCONFIG,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 0.--15. 1. "NEXTMBCONFIGADDRESS,Contains the next MB address" group.long 0x38++0x07 line.long 0x00 "ILF3_MBCONFIG_SLICEINFO01,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "SLICEINFO1,Parameter" hexmask.long.word 0x00 0.--15. 1. "SLICEINFO0,Parameter" line.long 0x04 "ILF3_MBCONFIG_SLICEINFO2,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x04 0.--15. 1. "MBCONFIG_ADDRESS_SLICEINFO2,Parameter" group.long 0xB8++0x03 line.long 0x00 "ILF3_MBSTATUS,Provides MB properties" bitfld.long 0x00 25. "ISFIRSTMB,Indicates which MB of the MB pair is being processed" "ISFIRSTMB_0,ISFIRSTMB_1" bitfld.long 0x00 23.--24. "COMPONENT,Indicates if IPB contains Luma or Chroma pixels" "Luma pixels,Chroma pixels,?..." newline bitfld.long 0x00 22. "TOP_LEFT_FIELD,Indicates the type of the top-left MB pair" "TOP_LEFT_FIELD_0_r,TOP_LEFT_FIELD_1_r" bitfld.long 0x00 21. "TOP_FIELD,Indicates the type of the top MB pair" "TOP_FIELD_0_r,TOP_FIELD_1_r" newline bitfld.long 0x00 20. "LEFT_FIELD,Indicates the type of the left MB pair" "LEFT_FIELD_0_r,LEFT_FIELD_1_r" bitfld.long 0x00 19. "CUR_FIELD,Indicates the type of the current MB" "CUR_FIELD_0_r,CUR_FIELD_1_r" newline bitfld.long 0x00 17.--18. "ALT_V,Indicates the type of left edge" "ALT_V_0_r,ALT_V_1_r,ALT_V_2_r,ALT_V_3_r" bitfld.long 0x00 16. "ALT_H,Indicates the type of the top horizontal edge" "ALT_H_0_r,ALT_H_1_r" newline bitfld.long 0x00 8. "LOAD_SLICEINFO,This flag indicates if the slice information must be updated or not" "LOAD_SLICEINFO_0_r,LOAD_SLICEINFO_1_r" bitfld.long 0x00 0.--4. "PPA_TASK_STATUS,1 means which elementary task has been executed" "Load MB info Bit,Compute BS Bit,Load MB Bit,Filter MB Bit,Store MB,?..." rgroup.long 0x00++0x03 line.long 0x00 "ILF3_REVISION,IP revision identifier (X.Y.R) Used by software to track features. bugs. and compatibility" rgroup.long 0x34++0x03 line.long 0x00 "ILF3_STATUS,Provides information on the progress of the ILF3 execution" bitfld.long 0x00 27. "WRITEREGERROR,This bit is cleared by a Start() command when in INITIALIZED or COMPLETED state" "WRITEREGERROR_0_r,WRITEREGERROR_1_r" bitfld.long 0x00 24.--25. "EXECSTATE,Execution states" "EXECSTATE_0_r,EXECSTATE_1_r,EXECSTATE_2_r,EXECSTATE_3_r" newline hexmask.long.word 0x00 0.--15. 1. "CYCLECOUNT,Total number of cycles executed" group.long 0x10++0x03 line.long 0x00 "ILF3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset (optional)" "SOFTRESET_0_w,SOFTRESET_1_r" width 0x0B tree.end endif tree "ILF3_L3_MAINInterconnect" base ad:0x5A052000 tree "Channel_0" group.long 0x1C8++0x03 line.long 0x00 "ILF3_BS_l_0,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x03 line.long 0x00 "ILF3_IPB_n_0,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x94++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_0,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x4C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x128++0x03 line.long 0x00 "ILF3_QP_IDX_j_0,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE0++0x03 line.long 0x00 "ILF3_QP_m_0,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_0,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_1" group.long 0x1CC++0x03 line.long 0x00 "ILF3_BS_l_1,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x420++0x03 line.long 0x00 "ILF3_IPB_n_1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x98++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_1,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x44++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_1,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x50++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_1,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x12C++0x03 line.long 0x00 "ILF3_QP_IDX_j_1,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE4++0x03 line.long 0x00 "ILF3_QP_m_1,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC0++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_1,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_10" group.long 0x1F0++0x03 line.long 0x00 "ILF3_BS_l_10,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x444++0x03 line.long 0x00 "ILF3_IPB_n_10,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x74++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_10,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x150++0x03 line.long 0x00 "ILF3_QP_IDX_j_10,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "ILF3_QP_m_10,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_100" group.long 0x358++0x03 line.long 0x00 "ILF3_BS_l_100,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5AC++0x03 line.long 0x00 "ILF3_IPB_n_100,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_101" group.long 0x35C++0x03 line.long 0x00 "ILF3_BS_l_101,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B0++0x03 line.long 0x00 "ILF3_IPB_n_101,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_102" group.long 0x360++0x03 line.long 0x00 "ILF3_BS_l_102,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B4++0x03 line.long 0x00 "ILF3_IPB_n_102,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_103" group.long 0x364++0x03 line.long 0x00 "ILF3_BS_l_103,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5B8++0x03 line.long 0x00 "ILF3_IPB_n_103,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_104" group.long 0x368++0x03 line.long 0x00 "ILF3_BS_l_104,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5BC++0x03 line.long 0x00 "ILF3_IPB_n_104,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_105" group.long 0x36C++0x03 line.long 0x00 "ILF3_BS_l_105,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C0++0x03 line.long 0x00 "ILF3_IPB_n_105,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_106" group.long 0x370++0x03 line.long 0x00 "ILF3_BS_l_106,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C4++0x03 line.long 0x00 "ILF3_IPB_n_106,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_107" group.long 0x374++0x03 line.long 0x00 "ILF3_BS_l_107,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C8++0x03 line.long 0x00 "ILF3_IPB_n_107,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_108" group.long 0x378++0x03 line.long 0x00 "ILF3_BS_l_108,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5CC++0x03 line.long 0x00 "ILF3_IPB_n_108,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_109" group.long 0x37C++0x03 line.long 0x00 "ILF3_BS_l_109,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D0++0x03 line.long 0x00 "ILF3_IPB_n_109,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_11" group.long 0x1F4++0x03 line.long 0x00 "ILF3_BS_l_11,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x448++0x03 line.long 0x00 "ILF3_IPB_n_11,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x78++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_11,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x154++0x03 line.long 0x00 "ILF3_QP_IDX_j_11,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x10C++0x03 line.long 0x00 "ILF3_QP_m_11,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_110" group.long 0x380++0x03 line.long 0x00 "ILF3_BS_l_110,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D4++0x03 line.long 0x00 "ILF3_IPB_n_110,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_111" group.long 0x384++0x03 line.long 0x00 "ILF3_BS_l_111,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5D8++0x03 line.long 0x00 "ILF3_IPB_n_111,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_112" group.long 0x388++0x03 line.long 0x00 "ILF3_BS_l_112,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5DC++0x03 line.long 0x00 "ILF3_IPB_n_112,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_113" group.long 0x38C++0x03 line.long 0x00 "ILF3_BS_l_113,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E0++0x03 line.long 0x00 "ILF3_IPB_n_113,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_114" group.long 0x390++0x03 line.long 0x00 "ILF3_BS_l_114,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E4++0x03 line.long 0x00 "ILF3_IPB_n_114,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_115" group.long 0x394++0x03 line.long 0x00 "ILF3_BS_l_115,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5E8++0x03 line.long 0x00 "ILF3_IPB_n_115,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_116" group.long 0x398++0x03 line.long 0x00 "ILF3_BS_l_116,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5EC++0x03 line.long 0x00 "ILF3_IPB_n_116,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_117" group.long 0x39C++0x03 line.long 0x00 "ILF3_BS_l_117,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F0++0x03 line.long 0x00 "ILF3_IPB_n_117,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_118" group.long 0x3A0++0x03 line.long 0x00 "ILF3_BS_l_118,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F4++0x03 line.long 0x00 "ILF3_IPB_n_118,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_119" group.long 0x3A4++0x03 line.long 0x00 "ILF3_BS_l_119,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5F8++0x03 line.long 0x00 "ILF3_IPB_n_119,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_12" group.long 0x1F8++0x03 line.long 0x00 "ILF3_BS_l_12,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44C++0x03 line.long 0x00 "ILF3_IPB_n_12,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x7C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_12,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x158++0x03 line.long 0x00 "ILF3_QP_IDX_j_12,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "ILF3_QP_m_12,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_120" group.long 0x3A8++0x03 line.long 0x00 "ILF3_BS_l_120,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5FC++0x03 line.long 0x00 "ILF3_IPB_n_120,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_121" group.long 0x3AC++0x03 line.long 0x00 "ILF3_BS_l_121,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x600++0x03 line.long 0x00 "ILF3_IPB_n_121,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_122" group.long 0x3B0++0x03 line.long 0x00 "ILF3_BS_l_122,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x604++0x03 line.long 0x00 "ILF3_IPB_n_122,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_123" group.long 0x3B4++0x03 line.long 0x00 "ILF3_BS_l_123,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x608++0x03 line.long 0x00 "ILF3_IPB_n_123,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_124" group.long 0x3B8++0x03 line.long 0x00 "ILF3_BS_l_124,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x60C++0x03 line.long 0x00 "ILF3_IPB_n_124,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_125" group.long 0x3BC++0x03 line.long 0x00 "ILF3_BS_l_125,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x610++0x03 line.long 0x00 "ILF3_IPB_n_125,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_126" group.long 0x3C0++0x03 line.long 0x00 "ILF3_BS_l_126,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x614++0x03 line.long 0x00 "ILF3_IPB_n_126,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_127" group.long 0x3C4++0x03 line.long 0x00 "ILF3_BS_l_127,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x618++0x03 line.long 0x00 "ILF3_IPB_n_127,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_128" group.long 0x3C8++0x03 line.long 0x00 "ILF3_BS_l_128,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x61C++0x03 line.long 0x00 "ILF3_IPB_n_128,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_129" group.long 0x3CC++0x03 line.long 0x00 "ILF3_BS_l_129,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x620++0x03 line.long 0x00 "ILF3_IPB_n_129,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_13" group.long 0x1FC++0x03 line.long 0x00 "ILF3_BS_l_13,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x450++0x03 line.long 0x00 "ILF3_IPB_n_13,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x80++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_13,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x15C++0x03 line.long 0x00 "ILF3_QP_IDX_j_13,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x114++0x03 line.long 0x00 "ILF3_QP_m_13,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_130" group.long 0x3D0++0x03 line.long 0x00 "ILF3_BS_l_130,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x624++0x03 line.long 0x00 "ILF3_IPB_n_130,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_131" group.long 0x3D4++0x03 line.long 0x00 "ILF3_BS_l_131,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x628++0x03 line.long 0x00 "ILF3_IPB_n_131,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_132" group.long 0x3D8++0x03 line.long 0x00 "ILF3_BS_l_132,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x62C++0x03 line.long 0x00 "ILF3_IPB_n_132,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_133" group.long 0x3DC++0x03 line.long 0x00 "ILF3_BS_l_133,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x630++0x03 line.long 0x00 "ILF3_IPB_n_133,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_134" group.long 0x3E0++0x03 line.long 0x00 "ILF3_BS_l_134,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x634++0x03 line.long 0x00 "ILF3_IPB_n_134,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_135" group.long 0x3E4++0x03 line.long 0x00 "ILF3_BS_l_135,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x638++0x03 line.long 0x00 "ILF3_IPB_n_135,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_136" group.long 0x3E8++0x03 line.long 0x00 "ILF3_BS_l_136,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x63C++0x03 line.long 0x00 "ILF3_IPB_n_136,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_137" group.long 0x3EC++0x03 line.long 0x00 "ILF3_BS_l_137,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x640++0x03 line.long 0x00 "ILF3_IPB_n_137,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_138" group.long 0x3F0++0x03 line.long 0x00 "ILF3_BS_l_138,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x644++0x03 line.long 0x00 "ILF3_IPB_n_138,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_139" group.long 0x3F4++0x03 line.long 0x00 "ILF3_BS_l_139,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x648++0x03 line.long 0x00 "ILF3_IPB_n_139,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_14" group.long 0x200++0x03 line.long 0x00 "ILF3_BS_l_14,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x454++0x03 line.long 0x00 "ILF3_IPB_n_14,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x84++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_14,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x160++0x03 line.long 0x00 "ILF3_QP_IDX_j_14,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "ILF3_QP_m_14,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_140" group.long 0x3F8++0x03 line.long 0x00 "ILF3_BS_l_140,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x64C++0x03 line.long 0x00 "ILF3_IPB_n_140,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_141" group.long 0x3FC++0x03 line.long 0x00 "ILF3_BS_l_141,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x650++0x03 line.long 0x00 "ILF3_IPB_n_141,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_142" group.long 0x400++0x03 line.long 0x00 "ILF3_BS_l_142,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x654++0x03 line.long 0x00 "ILF3_IPB_n_142,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_143" group.long 0x404++0x03 line.long 0x00 "ILF3_BS_l_143,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x658++0x03 line.long 0x00 "ILF3_IPB_n_143,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_144" group.long 0x408++0x03 line.long 0x00 "ILF3_BS_l_144,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x65C++0x03 line.long 0x00 "ILF3_IPB_n_144,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_145" group.long 0x40C++0x03 line.long 0x00 "ILF3_BS_l_145,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x660++0x03 line.long 0x00 "ILF3_IPB_n_145,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_146" group.long 0x410++0x03 line.long 0x00 "ILF3_BS_l_146,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x664++0x03 line.long 0x00 "ILF3_IPB_n_146,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_147" group.long 0x414++0x03 line.long 0x00 "ILF3_BS_l_147,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x668++0x03 line.long 0x00 "ILF3_IPB_n_147,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_148" group.long 0x418++0x03 line.long 0x00 "ILF3_BS_l_148,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x66C++0x8AF line.long 0x00 "ILF3_IPB_n_148,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x04 "ILF3_IPB_n_149,Input buffer bank" bitfld.long 0x04 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x08 "ILF3_IPB_n_150,Input buffer bank" bitfld.long 0x08 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x0C "ILF3_IPB_n_151,Input buffer bank" bitfld.long 0x0C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x10 "ILF3_IPB_n_152,Input buffer bank" bitfld.long 0x10 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x14 "ILF3_IPB_n_153,Input buffer bank" bitfld.long 0x14 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x18 "ILF3_IPB_n_154,Input buffer bank" bitfld.long 0x18 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C "ILF3_IPB_n_155,Input buffer bank" bitfld.long 0x1C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x20 "ILF3_IPB_n_156,Input buffer bank" bitfld.long 0x20 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x24 "ILF3_IPB_n_157,Input buffer bank" bitfld.long 0x24 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x28 "ILF3_IPB_n_158,Input buffer bank" bitfld.long 0x28 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C "ILF3_IPB_n_159,Input buffer bank" bitfld.long 0x2C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x30 "ILF3_IPB_n_160,Input buffer bank" bitfld.long 0x30 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x34 "ILF3_IPB_n_161,Input buffer bank" bitfld.long 0x34 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x38 "ILF3_IPB_n_162,Input buffer bank" bitfld.long 0x38 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C "ILF3_IPB_n_163,Input buffer bank" bitfld.long 0x3C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x40 "ILF3_IPB_n_164,Input buffer bank" bitfld.long 0x40 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x44 "ILF3_IPB_n_165,Input buffer bank" bitfld.long 0x44 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x48 "ILF3_IPB_n_166,Input buffer bank" bitfld.long 0x48 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x48 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C "ILF3_IPB_n_167,Input buffer bank" bitfld.long 0x4C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x50 "ILF3_IPB_n_168,Input buffer bank" bitfld.long 0x50 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x54 "ILF3_IPB_n_169,Input buffer bank" bitfld.long 0x54 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x54 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x58 "ILF3_IPB_n_170,Input buffer bank" bitfld.long 0x58 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x58 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C "ILF3_IPB_n_171,Input buffer bank" bitfld.long 0x5C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x60 "ILF3_IPB_n_172,Input buffer bank" bitfld.long 0x60 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x60 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x64 "ILF3_IPB_n_173,Input buffer bank" bitfld.long 0x64 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x64 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x68 "ILF3_IPB_n_174,Input buffer bank" bitfld.long 0x68 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x68 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C "ILF3_IPB_n_175,Input buffer bank" bitfld.long 0x6C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x70 "ILF3_IPB_n_176,Input buffer bank" bitfld.long 0x70 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x70 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x74 "ILF3_IPB_n_177,Input buffer bank" bitfld.long 0x74 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x74 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x78 "ILF3_IPB_n_178,Input buffer bank" bitfld.long 0x78 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C "ILF3_IPB_n_179,Input buffer bank" bitfld.long 0x7C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x80 "ILF3_IPB_n_180,Input buffer bank" bitfld.long 0x80 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x84 "ILF3_IPB_n_181,Input buffer bank" bitfld.long 0x84 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x84 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x88 "ILF3_IPB_n_182,Input buffer bank" bitfld.long 0x88 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x88 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8C "ILF3_IPB_n_183,Input buffer bank" bitfld.long 0x8C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x90 "ILF3_IPB_n_184,Input buffer bank" bitfld.long 0x90 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x90 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x94 "ILF3_IPB_n_185,Input buffer bank" bitfld.long 0x94 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x94 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x98 "ILF3_IPB_n_186,Input buffer bank" bitfld.long 0x98 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x98 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x9C "ILF3_IPB_n_187,Input buffer bank" bitfld.long 0x9C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x9C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA0 "ILF3_IPB_n_188,Input buffer bank" bitfld.long 0xA0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA4 "ILF3_IPB_n_189,Input buffer bank" bitfld.long 0xA4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xA8 "ILF3_IPB_n_190,Input buffer bank" bitfld.long 0xA8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xA8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xAC "ILF3_IPB_n_191,Input buffer bank" bitfld.long 0xAC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xAC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB0 "ILF3_IPB_n_192,Input buffer bank" bitfld.long 0xB0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB4 "ILF3_IPB_n_193,Input buffer bank" bitfld.long 0xB4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xB8 "ILF3_IPB_n_194,Input buffer bank" bitfld.long 0xB8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xB8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xBC "ILF3_IPB_n_195,Input buffer bank" bitfld.long 0xBC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xBC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC0 "ILF3_IPB_n_196,Input buffer bank" bitfld.long 0xC0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC4 "ILF3_IPB_n_197,Input buffer bank" bitfld.long 0xC4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xC8 "ILF3_IPB_n_198,Input buffer bank" bitfld.long 0xC8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xCC "ILF3_IPB_n_199,Input buffer bank" bitfld.long 0xCC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xCC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD0 "ILF3_IPB_n_200,Input buffer bank" bitfld.long 0xD0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD4 "ILF3_IPB_n_201,Input buffer bank" bitfld.long 0xD4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xD8 "ILF3_IPB_n_202,Input buffer bank" bitfld.long 0xD8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xD8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xDC "ILF3_IPB_n_203,Input buffer bank" bitfld.long 0xDC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xDC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE0 "ILF3_IPB_n_204,Input buffer bank" bitfld.long 0xE0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE4 "ILF3_IPB_n_205,Input buffer bank" bitfld.long 0xE4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xE8 "ILF3_IPB_n_206,Input buffer bank" bitfld.long 0xE8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xE8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xEC "ILF3_IPB_n_207,Input buffer bank" bitfld.long 0xEC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xEC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF0 "ILF3_IPB_n_208,Input buffer bank" bitfld.long 0xF0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF4 "ILF3_IPB_n_209,Input buffer bank" bitfld.long 0xF4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xF8 "ILF3_IPB_n_210,Input buffer bank" bitfld.long 0xF8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xF8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0xFC "ILF3_IPB_n_211,Input buffer bank" bitfld.long 0xFC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xFC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x100 "ILF3_IPB_n_212,Input buffer bank" bitfld.long 0x100 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x100 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x104 "ILF3_IPB_n_213,Input buffer bank" bitfld.long 0x104 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x104 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x108 "ILF3_IPB_n_214,Input buffer bank" bitfld.long 0x108 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x108 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x10C "ILF3_IPB_n_215,Input buffer bank" bitfld.long 0x10C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x110 "ILF3_IPB_n_216,Input buffer bank" bitfld.long 0x110 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x110 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x114 "ILF3_IPB_n_217,Input buffer bank" bitfld.long 0x114 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x114 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x118 "ILF3_IPB_n_218,Input buffer bank" bitfld.long 0x118 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x118 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x11C "ILF3_IPB_n_219,Input buffer bank" bitfld.long 0x11C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x11C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x120 "ILF3_IPB_n_220,Input buffer bank" bitfld.long 0x120 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x120 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x124 "ILF3_IPB_n_221,Input buffer bank" bitfld.long 0x124 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x124 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x128 "ILF3_IPB_n_222,Input buffer bank" bitfld.long 0x128 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x128 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x12C "ILF3_IPB_n_223,Input buffer bank" bitfld.long 0x12C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x12C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x130 "ILF3_IPB_n_224,Input buffer bank" bitfld.long 0x130 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x130 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x134 "ILF3_IPB_n_225,Input buffer bank" bitfld.long 0x134 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x134 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x138 "ILF3_IPB_n_226,Input buffer bank" bitfld.long 0x138 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x138 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x13C "ILF3_IPB_n_227,Input buffer bank" bitfld.long 0x13C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x13C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x140 "ILF3_IPB_n_228,Input buffer bank" bitfld.long 0x140 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x140 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x144 "ILF3_IPB_n_229,Input buffer bank" bitfld.long 0x144 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x144 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x148 "ILF3_IPB_n_230,Input buffer bank" bitfld.long 0x148 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x148 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x14C "ILF3_IPB_n_231,Input buffer bank" bitfld.long 0x14C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x150 "ILF3_IPB_n_232,Input buffer bank" bitfld.long 0x150 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x150 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x154 "ILF3_IPB_n_233,Input buffer bank" bitfld.long 0x154 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x154 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x158 "ILF3_IPB_n_234,Input buffer bank" bitfld.long 0x158 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x158 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x15C "ILF3_IPB_n_235,Input buffer bank" bitfld.long 0x15C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x15C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x160 "ILF3_IPB_n_236,Input buffer bank" bitfld.long 0x160 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x160 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x164 "ILF3_IPB_n_237,Input buffer bank" bitfld.long 0x164 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x164 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x168 "ILF3_IPB_n_238,Input buffer bank" bitfld.long 0x168 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x168 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x16C "ILF3_IPB_n_239,Input buffer bank" bitfld.long 0x16C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x16C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x170 "ILF3_IPB_n_240,Input buffer bank" bitfld.long 0x170 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x170 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x174 "ILF3_IPB_n_241,Input buffer bank" bitfld.long 0x174 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x174 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x178 "ILF3_IPB_n_242,Input buffer bank" bitfld.long 0x178 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x178 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x17C "ILF3_IPB_n_243,Input buffer bank" bitfld.long 0x17C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x17C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x180 "ILF3_IPB_n_244,Input buffer bank" bitfld.long 0x180 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x180 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x184 "ILF3_IPB_n_245,Input buffer bank" bitfld.long 0x184 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x184 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x188 "ILF3_IPB_n_246,Input buffer bank" bitfld.long 0x188 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x188 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x18C "ILF3_IPB_n_247,Input buffer bank" bitfld.long 0x18C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x190 "ILF3_IPB_n_248,Input buffer bank" bitfld.long 0x190 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x190 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x194 "ILF3_IPB_n_249,Input buffer bank" bitfld.long 0x194 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x194 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x198 "ILF3_IPB_n_250,Input buffer bank" bitfld.long 0x198 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x198 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x19C "ILF3_IPB_n_251,Input buffer bank" bitfld.long 0x19C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x19C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A0 "ILF3_IPB_n_252,Input buffer bank" bitfld.long 0x1A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A4 "ILF3_IPB_n_253,Input buffer bank" bitfld.long 0x1A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1A8 "ILF3_IPB_n_254,Input buffer bank" bitfld.long 0x1A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1AC "ILF3_IPB_n_255,Input buffer bank" bitfld.long 0x1AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B0 "ILF3_IPB_n_256,Input buffer bank" bitfld.long 0x1B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B4 "ILF3_IPB_n_257,Input buffer bank" bitfld.long 0x1B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1B8 "ILF3_IPB_n_258,Input buffer bank" bitfld.long 0x1B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1BC "ILF3_IPB_n_259,Input buffer bank" bitfld.long 0x1BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C0 "ILF3_IPB_n_260,Input buffer bank" bitfld.long 0x1C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C4 "ILF3_IPB_n_261,Input buffer bank" bitfld.long 0x1C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1C8 "ILF3_IPB_n_262,Input buffer bank" bitfld.long 0x1C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1CC "ILF3_IPB_n_263,Input buffer bank" bitfld.long 0x1CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D0 "ILF3_IPB_n_264,Input buffer bank" bitfld.long 0x1D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D4 "ILF3_IPB_n_265,Input buffer bank" bitfld.long 0x1D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1D8 "ILF3_IPB_n_266,Input buffer bank" bitfld.long 0x1D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1DC "ILF3_IPB_n_267,Input buffer bank" bitfld.long 0x1DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E0 "ILF3_IPB_n_268,Input buffer bank" bitfld.long 0x1E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E4 "ILF3_IPB_n_269,Input buffer bank" bitfld.long 0x1E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1E8 "ILF3_IPB_n_270,Input buffer bank" bitfld.long 0x1E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1EC "ILF3_IPB_n_271,Input buffer bank" bitfld.long 0x1EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F0 "ILF3_IPB_n_272,Input buffer bank" bitfld.long 0x1F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F4 "ILF3_IPB_n_273,Input buffer bank" bitfld.long 0x1F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1F8 "ILF3_IPB_n_274,Input buffer bank" bitfld.long 0x1F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x1FC "ILF3_IPB_n_275,Input buffer bank" bitfld.long 0x1FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x200 "ILF3_IPB_n_276,Input buffer bank" bitfld.long 0x200 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x200 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x204 "ILF3_IPB_n_277,Input buffer bank" bitfld.long 0x204 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x204 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x208 "ILF3_IPB_n_278,Input buffer bank" bitfld.long 0x208 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x208 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x20C "ILF3_IPB_n_279,Input buffer bank" bitfld.long 0x20C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x210 "ILF3_IPB_n_280,Input buffer bank" bitfld.long 0x210 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x210 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x214 "ILF3_IPB_n_281,Input buffer bank" bitfld.long 0x214 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x214 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x218 "ILF3_IPB_n_282,Input buffer bank" bitfld.long 0x218 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x218 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x21C "ILF3_IPB_n_283,Input buffer bank" bitfld.long 0x21C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x21C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x220 "ILF3_IPB_n_284,Input buffer bank" bitfld.long 0x220 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x220 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x224 "ILF3_IPB_n_285,Input buffer bank" bitfld.long 0x224 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x224 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x228 "ILF3_IPB_n_286,Input buffer bank" bitfld.long 0x228 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x228 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x22C "ILF3_IPB_n_287,Input buffer bank" bitfld.long 0x22C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x22C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x230 "ILF3_IPB_n_288,Input buffer bank" bitfld.long 0x230 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x230 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x234 "ILF3_IPB_n_289,Input buffer bank" bitfld.long 0x234 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x234 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x238 "ILF3_IPB_n_290,Input buffer bank" bitfld.long 0x238 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x238 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x23C "ILF3_IPB_n_291,Input buffer bank" bitfld.long 0x23C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x23C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x240 "ILF3_IPB_n_292,Input buffer bank" bitfld.long 0x240 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x240 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x244 "ILF3_IPB_n_293,Input buffer bank" bitfld.long 0x244 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x244 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x248 "ILF3_IPB_n_294,Input buffer bank" bitfld.long 0x248 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x248 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x24C "ILF3_IPB_n_295,Input buffer bank" bitfld.long 0x24C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x250 "ILF3_IPB_n_296,Input buffer bank" bitfld.long 0x250 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x250 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x254 "ILF3_IPB_n_297,Input buffer bank" bitfld.long 0x254 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x254 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x258 "ILF3_IPB_n_298,Input buffer bank" bitfld.long 0x258 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x258 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x25C "ILF3_IPB_n_299,Input buffer bank" bitfld.long 0x25C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x25C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x260 "ILF3_IPB_n_300,Input buffer bank" bitfld.long 0x260 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x260 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x264 "ILF3_IPB_n_301,Input buffer bank" bitfld.long 0x264 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x264 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x268 "ILF3_IPB_n_302,Input buffer bank" bitfld.long 0x268 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x268 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x26C "ILF3_IPB_n_303,Input buffer bank" bitfld.long 0x26C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x26C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x270 "ILF3_IPB_n_304,Input buffer bank" bitfld.long 0x270 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x270 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x274 "ILF3_IPB_n_305,Input buffer bank" bitfld.long 0x274 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x274 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x278 "ILF3_IPB_n_306,Input buffer bank" bitfld.long 0x278 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x278 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x27C "ILF3_IPB_n_307,Input buffer bank" bitfld.long 0x27C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x27C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x280 "ILF3_IPB_n_308,Input buffer bank" bitfld.long 0x280 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x280 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x284 "ILF3_IPB_n_309,Input buffer bank" bitfld.long 0x284 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x284 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x288 "ILF3_IPB_n_310,Input buffer bank" bitfld.long 0x288 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x288 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x28C "ILF3_IPB_n_311,Input buffer bank" bitfld.long 0x28C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x290 "ILF3_IPB_n_312,Input buffer bank" bitfld.long 0x290 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x290 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x294 "ILF3_IPB_n_313,Input buffer bank" bitfld.long 0x294 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x294 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x298 "ILF3_IPB_n_314,Input buffer bank" bitfld.long 0x298 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x298 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x29C "ILF3_IPB_n_315,Input buffer bank" bitfld.long 0x29C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x29C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A0 "ILF3_IPB_n_316,Input buffer bank" bitfld.long 0x2A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A4 "ILF3_IPB_n_317,Input buffer bank" bitfld.long 0x2A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2A8 "ILF3_IPB_n_318,Input buffer bank" bitfld.long 0x2A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2AC "ILF3_IPB_n_319,Input buffer bank" bitfld.long 0x2AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B0 "ILF3_IPB_n_320,Input buffer bank" bitfld.long 0x2B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B4 "ILF3_IPB_n_321,Input buffer bank" bitfld.long 0x2B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2B8 "ILF3_IPB_n_322,Input buffer bank" bitfld.long 0x2B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2BC "ILF3_IPB_n_323,Input buffer bank" bitfld.long 0x2BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C0 "ILF3_IPB_n_324,Input buffer bank" bitfld.long 0x2C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C4 "ILF3_IPB_n_325,Input buffer bank" bitfld.long 0x2C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2C8 "ILF3_IPB_n_326,Input buffer bank" bitfld.long 0x2C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2CC "ILF3_IPB_n_327,Input buffer bank" bitfld.long 0x2CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D0 "ILF3_IPB_n_328,Input buffer bank" bitfld.long 0x2D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D4 "ILF3_IPB_n_329,Input buffer bank" bitfld.long 0x2D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2D8 "ILF3_IPB_n_330,Input buffer bank" bitfld.long 0x2D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2DC "ILF3_IPB_n_331,Input buffer bank" bitfld.long 0x2DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E0 "ILF3_IPB_n_332,Input buffer bank" bitfld.long 0x2E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E4 "ILF3_IPB_n_333,Input buffer bank" bitfld.long 0x2E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2E8 "ILF3_IPB_n_334,Input buffer bank" bitfld.long 0x2E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2EC "ILF3_IPB_n_335,Input buffer bank" bitfld.long 0x2EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F0 "ILF3_IPB_n_336,Input buffer bank" bitfld.long 0x2F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F4 "ILF3_IPB_n_337,Input buffer bank" bitfld.long 0x2F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2F8 "ILF3_IPB_n_338,Input buffer bank" bitfld.long 0x2F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x2FC "ILF3_IPB_n_339,Input buffer bank" bitfld.long 0x2FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x300 "ILF3_IPB_n_340,Input buffer bank" bitfld.long 0x300 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x300 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x304 "ILF3_IPB_n_341,Input buffer bank" bitfld.long 0x304 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x304 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x308 "ILF3_IPB_n_342,Input buffer bank" bitfld.long 0x308 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x308 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x30C "ILF3_IPB_n_343,Input buffer bank" bitfld.long 0x30C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x310 "ILF3_IPB_n_344,Input buffer bank" bitfld.long 0x310 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x310 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x314 "ILF3_IPB_n_345,Input buffer bank" bitfld.long 0x314 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x314 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x318 "ILF3_IPB_n_346,Input buffer bank" bitfld.long 0x318 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x318 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x31C "ILF3_IPB_n_347,Input buffer bank" bitfld.long 0x31C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x31C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x320 "ILF3_IPB_n_348,Input buffer bank" bitfld.long 0x320 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x320 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x324 "ILF3_IPB_n_349,Input buffer bank" bitfld.long 0x324 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x324 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x328 "ILF3_IPB_n_350,Input buffer bank" bitfld.long 0x328 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x328 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x32C "ILF3_IPB_n_351,Input buffer bank" bitfld.long 0x32C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x32C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x330 "ILF3_IPB_n_352,Input buffer bank" bitfld.long 0x330 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x330 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x334 "ILF3_IPB_n_353,Input buffer bank" bitfld.long 0x334 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x334 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x338 "ILF3_IPB_n_354,Input buffer bank" bitfld.long 0x338 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x338 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x33C "ILF3_IPB_n_355,Input buffer bank" bitfld.long 0x33C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x33C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x340 "ILF3_IPB_n_356,Input buffer bank" bitfld.long 0x340 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x340 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x344 "ILF3_IPB_n_357,Input buffer bank" bitfld.long 0x344 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x344 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x348 "ILF3_IPB_n_358,Input buffer bank" bitfld.long 0x348 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x348 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x34C "ILF3_IPB_n_359,Input buffer bank" bitfld.long 0x34C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x350 "ILF3_IPB_n_360,Input buffer bank" bitfld.long 0x350 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x350 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x354 "ILF3_IPB_n_361,Input buffer bank" bitfld.long 0x354 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x354 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x358 "ILF3_IPB_n_362,Input buffer bank" bitfld.long 0x358 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x358 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x35C "ILF3_IPB_n_363,Input buffer bank" bitfld.long 0x35C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x35C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x360 "ILF3_IPB_n_364,Input buffer bank" bitfld.long 0x360 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x360 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x364 "ILF3_IPB_n_365,Input buffer bank" bitfld.long 0x364 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x364 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x368 "ILF3_IPB_n_366,Input buffer bank" bitfld.long 0x368 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x368 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x36C "ILF3_IPB_n_367,Input buffer bank" bitfld.long 0x36C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x36C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x370 "ILF3_IPB_n_368,Input buffer bank" bitfld.long 0x370 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x370 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x374 "ILF3_IPB_n_369,Input buffer bank" bitfld.long 0x374 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x374 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x378 "ILF3_IPB_n_370,Input buffer bank" bitfld.long 0x378 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x378 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x37C "ILF3_IPB_n_371,Input buffer bank" bitfld.long 0x37C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x37C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x380 "ILF3_IPB_n_372,Input buffer bank" bitfld.long 0x380 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x380 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x384 "ILF3_IPB_n_373,Input buffer bank" bitfld.long 0x384 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x384 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x388 "ILF3_IPB_n_374,Input buffer bank" bitfld.long 0x388 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x388 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x38C "ILF3_IPB_n_375,Input buffer bank" bitfld.long 0x38C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x390 "ILF3_IPB_n_376,Input buffer bank" bitfld.long 0x390 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x390 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x394 "ILF3_IPB_n_377,Input buffer bank" bitfld.long 0x394 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x394 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x398 "ILF3_IPB_n_378,Input buffer bank" bitfld.long 0x398 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x398 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x39C "ILF3_IPB_n_379,Input buffer bank" bitfld.long 0x39C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x39C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A0 "ILF3_IPB_n_380,Input buffer bank" bitfld.long 0x3A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A4 "ILF3_IPB_n_381,Input buffer bank" bitfld.long 0x3A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3A8 "ILF3_IPB_n_382,Input buffer bank" bitfld.long 0x3A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3AC "ILF3_IPB_n_383,Input buffer bank" bitfld.long 0x3AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B0 "ILF3_IPB_n_384,Input buffer bank" bitfld.long 0x3B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B4 "ILF3_IPB_n_385,Input buffer bank" bitfld.long 0x3B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3B8 "ILF3_IPB_n_386,Input buffer bank" bitfld.long 0x3B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3BC "ILF3_IPB_n_387,Input buffer bank" bitfld.long 0x3BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C0 "ILF3_IPB_n_388,Input buffer bank" bitfld.long 0x3C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C4 "ILF3_IPB_n_389,Input buffer bank" bitfld.long 0x3C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3C8 "ILF3_IPB_n_390,Input buffer bank" bitfld.long 0x3C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3CC "ILF3_IPB_n_391,Input buffer bank" bitfld.long 0x3CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D0 "ILF3_IPB_n_392,Input buffer bank" bitfld.long 0x3D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D4 "ILF3_IPB_n_393,Input buffer bank" bitfld.long 0x3D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3D8 "ILF3_IPB_n_394,Input buffer bank" bitfld.long 0x3D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3DC "ILF3_IPB_n_395,Input buffer bank" bitfld.long 0x3DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E0 "ILF3_IPB_n_396,Input buffer bank" bitfld.long 0x3E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E4 "ILF3_IPB_n_397,Input buffer bank" bitfld.long 0x3E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3E8 "ILF3_IPB_n_398,Input buffer bank" bitfld.long 0x3E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3EC "ILF3_IPB_n_399,Input buffer bank" bitfld.long 0x3EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F0 "ILF3_IPB_n_400,Input buffer bank" bitfld.long 0x3F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F4 "ILF3_IPB_n_401,Input buffer bank" bitfld.long 0x3F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3F8 "ILF3_IPB_n_402,Input buffer bank" bitfld.long 0x3F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x3FC "ILF3_IPB_n_403,Input buffer bank" bitfld.long 0x3FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x400 "ILF3_IPB_n_404,Input buffer bank" bitfld.long 0x400 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x400 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x404 "ILF3_IPB_n_405,Input buffer bank" bitfld.long 0x404 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x404 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x408 "ILF3_IPB_n_406,Input buffer bank" bitfld.long 0x408 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x408 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x40C "ILF3_IPB_n_407,Input buffer bank" bitfld.long 0x40C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x40C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x410 "ILF3_IPB_n_408,Input buffer bank" bitfld.long 0x410 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x410 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x414 "ILF3_IPB_n_409,Input buffer bank" bitfld.long 0x414 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x414 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x418 "ILF3_IPB_n_410,Input buffer bank" bitfld.long 0x418 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x418 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x41C "ILF3_IPB_n_411,Input buffer bank" bitfld.long 0x41C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x41C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x420 "ILF3_IPB_n_412,Input buffer bank" bitfld.long 0x420 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x420 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x424 "ILF3_IPB_n_413,Input buffer bank" bitfld.long 0x424 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x424 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x428 "ILF3_IPB_n_414,Input buffer bank" bitfld.long 0x428 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x428 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x42C "ILF3_IPB_n_415,Input buffer bank" bitfld.long 0x42C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x42C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x430 "ILF3_IPB_n_416,Input buffer bank" bitfld.long 0x430 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x430 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x434 "ILF3_IPB_n_417,Input buffer bank" bitfld.long 0x434 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x434 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x438 "ILF3_IPB_n_418,Input buffer bank" bitfld.long 0x438 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x438 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x43C "ILF3_IPB_n_419,Input buffer bank" bitfld.long 0x43C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x43C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x440 "ILF3_IPB_n_420,Input buffer bank" bitfld.long 0x440 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x440 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x444 "ILF3_IPB_n_421,Input buffer bank" bitfld.long 0x444 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x444 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x448 "ILF3_IPB_n_422,Input buffer bank" bitfld.long 0x448 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x448 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x44C "ILF3_IPB_n_423,Input buffer bank" bitfld.long 0x44C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x44C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x450 "ILF3_IPB_n_424,Input buffer bank" bitfld.long 0x450 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x450 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x454 "ILF3_IPB_n_425,Input buffer bank" bitfld.long 0x454 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x454 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x458 "ILF3_IPB_n_426,Input buffer bank" bitfld.long 0x458 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x458 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x45C "ILF3_IPB_n_427,Input buffer bank" bitfld.long 0x45C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x45C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x460 "ILF3_IPB_n_428,Input buffer bank" bitfld.long 0x460 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x460 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x464 "ILF3_IPB_n_429,Input buffer bank" bitfld.long 0x464 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x464 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x468 "ILF3_IPB_n_430,Input buffer bank" bitfld.long 0x468 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x468 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x46C "ILF3_IPB_n_431,Input buffer bank" bitfld.long 0x46C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x46C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x470 "ILF3_IPB_n_432,Input buffer bank" bitfld.long 0x470 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x470 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x474 "ILF3_IPB_n_433,Input buffer bank" bitfld.long 0x474 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x474 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x478 "ILF3_IPB_n_434,Input buffer bank" bitfld.long 0x478 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x478 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x47C "ILF3_IPB_n_435,Input buffer bank" bitfld.long 0x47C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x47C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x480 "ILF3_IPB_n_436,Input buffer bank" bitfld.long 0x480 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x480 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x484 "ILF3_IPB_n_437,Input buffer bank" bitfld.long 0x484 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x484 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x488 "ILF3_IPB_n_438,Input buffer bank" bitfld.long 0x488 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x488 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x48C "ILF3_IPB_n_439,Input buffer bank" bitfld.long 0x48C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x48C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x490 "ILF3_IPB_n_440,Input buffer bank" bitfld.long 0x490 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x490 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x494 "ILF3_IPB_n_441,Input buffer bank" bitfld.long 0x494 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x494 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x498 "ILF3_IPB_n_442,Input buffer bank" bitfld.long 0x498 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x498 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x49C "ILF3_IPB_n_443,Input buffer bank" bitfld.long 0x49C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x49C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A0 "ILF3_IPB_n_444,Input buffer bank" bitfld.long 0x4A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A4 "ILF3_IPB_n_445,Input buffer bank" bitfld.long 0x4A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4A8 "ILF3_IPB_n_446,Input buffer bank" bitfld.long 0x4A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4AC "ILF3_IPB_n_447,Input buffer bank" bitfld.long 0x4AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B0 "ILF3_IPB_n_448,Input buffer bank" bitfld.long 0x4B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B4 "ILF3_IPB_n_449,Input buffer bank" bitfld.long 0x4B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4B8 "ILF3_IPB_n_450,Input buffer bank" bitfld.long 0x4B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4BC "ILF3_IPB_n_451,Input buffer bank" bitfld.long 0x4BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C0 "ILF3_IPB_n_452,Input buffer bank" bitfld.long 0x4C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C4 "ILF3_IPB_n_453,Input buffer bank" bitfld.long 0x4C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4C8 "ILF3_IPB_n_454,Input buffer bank" bitfld.long 0x4C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4CC "ILF3_IPB_n_455,Input buffer bank" bitfld.long 0x4CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D0 "ILF3_IPB_n_456,Input buffer bank" bitfld.long 0x4D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D4 "ILF3_IPB_n_457,Input buffer bank" bitfld.long 0x4D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4D8 "ILF3_IPB_n_458,Input buffer bank" bitfld.long 0x4D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4DC "ILF3_IPB_n_459,Input buffer bank" bitfld.long 0x4DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E0 "ILF3_IPB_n_460,Input buffer bank" bitfld.long 0x4E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E4 "ILF3_IPB_n_461,Input buffer bank" bitfld.long 0x4E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4E8 "ILF3_IPB_n_462,Input buffer bank" bitfld.long 0x4E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4EC "ILF3_IPB_n_463,Input buffer bank" bitfld.long 0x4EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F0 "ILF3_IPB_n_464,Input buffer bank" bitfld.long 0x4F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F4 "ILF3_IPB_n_465,Input buffer bank" bitfld.long 0x4F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4F8 "ILF3_IPB_n_466,Input buffer bank" bitfld.long 0x4F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x4FC "ILF3_IPB_n_467,Input buffer bank" bitfld.long 0x4FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x500 "ILF3_IPB_n_468,Input buffer bank" bitfld.long 0x500 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x500 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x504 "ILF3_IPB_n_469,Input buffer bank" bitfld.long 0x504 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x504 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x508 "ILF3_IPB_n_470,Input buffer bank" bitfld.long 0x508 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x508 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x50C "ILF3_IPB_n_471,Input buffer bank" bitfld.long 0x50C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x50C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x510 "ILF3_IPB_n_472,Input buffer bank" bitfld.long 0x510 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x510 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x514 "ILF3_IPB_n_473,Input buffer bank" bitfld.long 0x514 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x514 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x518 "ILF3_IPB_n_474,Input buffer bank" bitfld.long 0x518 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x518 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x51C "ILF3_IPB_n_475,Input buffer bank" bitfld.long 0x51C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x51C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x520 "ILF3_IPB_n_476,Input buffer bank" bitfld.long 0x520 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x520 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x524 "ILF3_IPB_n_477,Input buffer bank" bitfld.long 0x524 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x524 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x528 "ILF3_IPB_n_478,Input buffer bank" bitfld.long 0x528 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x528 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x52C "ILF3_IPB_n_479,Input buffer bank" bitfld.long 0x52C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x52C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x530 "ILF3_IPB_n_480,Input buffer bank" bitfld.long 0x530 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x530 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x534 "ILF3_IPB_n_481,Input buffer bank" bitfld.long 0x534 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x534 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x538 "ILF3_IPB_n_482,Input buffer bank" bitfld.long 0x538 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x538 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x53C "ILF3_IPB_n_483,Input buffer bank" bitfld.long 0x53C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x53C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x540 "ILF3_IPB_n_484,Input buffer bank" bitfld.long 0x540 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x540 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x544 "ILF3_IPB_n_485,Input buffer bank" bitfld.long 0x544 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x544 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x548 "ILF3_IPB_n_486,Input buffer bank" bitfld.long 0x548 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x548 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x54C "ILF3_IPB_n_487,Input buffer bank" bitfld.long 0x54C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x54C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x550 "ILF3_IPB_n_488,Input buffer bank" bitfld.long 0x550 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x550 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x554 "ILF3_IPB_n_489,Input buffer bank" bitfld.long 0x554 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x554 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x558 "ILF3_IPB_n_490,Input buffer bank" bitfld.long 0x558 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x558 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x55C "ILF3_IPB_n_491,Input buffer bank" bitfld.long 0x55C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x55C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x560 "ILF3_IPB_n_492,Input buffer bank" bitfld.long 0x560 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x560 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x564 "ILF3_IPB_n_493,Input buffer bank" bitfld.long 0x564 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x564 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x568 "ILF3_IPB_n_494,Input buffer bank" bitfld.long 0x568 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x568 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x56C "ILF3_IPB_n_495,Input buffer bank" bitfld.long 0x56C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x56C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x570 "ILF3_IPB_n_496,Input buffer bank" bitfld.long 0x570 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x570 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x574 "ILF3_IPB_n_497,Input buffer bank" bitfld.long 0x574 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x574 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x578 "ILF3_IPB_n_498,Input buffer bank" bitfld.long 0x578 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x578 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x57C "ILF3_IPB_n_499,Input buffer bank" bitfld.long 0x57C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x57C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x580 "ILF3_IPB_n_500,Input buffer bank" bitfld.long 0x580 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x580 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x584 "ILF3_IPB_n_501,Input buffer bank" bitfld.long 0x584 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x584 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x588 "ILF3_IPB_n_502,Input buffer bank" bitfld.long 0x588 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x588 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x58C "ILF3_IPB_n_503,Input buffer bank" bitfld.long 0x58C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x58C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x590 "ILF3_IPB_n_504,Input buffer bank" bitfld.long 0x590 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x590 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x594 "ILF3_IPB_n_505,Input buffer bank" bitfld.long 0x594 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x594 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x598 "ILF3_IPB_n_506,Input buffer bank" bitfld.long 0x598 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x598 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x59C "ILF3_IPB_n_507,Input buffer bank" bitfld.long 0x59C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x59C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A0 "ILF3_IPB_n_508,Input buffer bank" bitfld.long 0x5A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A4 "ILF3_IPB_n_509,Input buffer bank" bitfld.long 0x5A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5A8 "ILF3_IPB_n_510,Input buffer bank" bitfld.long 0x5A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5AC "ILF3_IPB_n_511,Input buffer bank" bitfld.long 0x5AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B0 "ILF3_IPB_n_512,Input buffer bank" bitfld.long 0x5B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B4 "ILF3_IPB_n_513,Input buffer bank" bitfld.long 0x5B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5B8 "ILF3_IPB_n_514,Input buffer bank" bitfld.long 0x5B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5BC "ILF3_IPB_n_515,Input buffer bank" bitfld.long 0x5BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C0 "ILF3_IPB_n_516,Input buffer bank" bitfld.long 0x5C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C4 "ILF3_IPB_n_517,Input buffer bank" bitfld.long 0x5C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5C8 "ILF3_IPB_n_518,Input buffer bank" bitfld.long 0x5C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5CC "ILF3_IPB_n_519,Input buffer bank" bitfld.long 0x5CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D0 "ILF3_IPB_n_520,Input buffer bank" bitfld.long 0x5D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D4 "ILF3_IPB_n_521,Input buffer bank" bitfld.long 0x5D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5D8 "ILF3_IPB_n_522,Input buffer bank" bitfld.long 0x5D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5DC "ILF3_IPB_n_523,Input buffer bank" bitfld.long 0x5DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E0 "ILF3_IPB_n_524,Input buffer bank" bitfld.long 0x5E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E4 "ILF3_IPB_n_525,Input buffer bank" bitfld.long 0x5E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5E8 "ILF3_IPB_n_526,Input buffer bank" bitfld.long 0x5E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5EC "ILF3_IPB_n_527,Input buffer bank" bitfld.long 0x5EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F0 "ILF3_IPB_n_528,Input buffer bank" bitfld.long 0x5F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F4 "ILF3_IPB_n_529,Input buffer bank" bitfld.long 0x5F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5F8 "ILF3_IPB_n_530,Input buffer bank" bitfld.long 0x5F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x5FC "ILF3_IPB_n_531,Input buffer bank" bitfld.long 0x5FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x5FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x600 "ILF3_IPB_n_532,Input buffer bank" bitfld.long 0x600 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x600 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x604 "ILF3_IPB_n_533,Input buffer bank" bitfld.long 0x604 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x604 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x608 "ILF3_IPB_n_534,Input buffer bank" bitfld.long 0x608 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x608 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x60C "ILF3_IPB_n_535,Input buffer bank" bitfld.long 0x60C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x60C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x610 "ILF3_IPB_n_536,Input buffer bank" bitfld.long 0x610 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x610 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x614 "ILF3_IPB_n_537,Input buffer bank" bitfld.long 0x614 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x614 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x618 "ILF3_IPB_n_538,Input buffer bank" bitfld.long 0x618 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x618 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x61C "ILF3_IPB_n_539,Input buffer bank" bitfld.long 0x61C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x61C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x620 "ILF3_IPB_n_540,Input buffer bank" bitfld.long 0x620 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x620 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x624 "ILF3_IPB_n_541,Input buffer bank" bitfld.long 0x624 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x624 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x628 "ILF3_IPB_n_542,Input buffer bank" bitfld.long 0x628 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x628 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x62C "ILF3_IPB_n_543,Input buffer bank" bitfld.long 0x62C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x62C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x630 "ILF3_IPB_n_544,Input buffer bank" bitfld.long 0x630 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x630 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x634 "ILF3_IPB_n_545,Input buffer bank" bitfld.long 0x634 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x634 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x638 "ILF3_IPB_n_546,Input buffer bank" bitfld.long 0x638 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x638 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x63C "ILF3_IPB_n_547,Input buffer bank" bitfld.long 0x63C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x63C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x640 "ILF3_IPB_n_548,Input buffer bank" bitfld.long 0x640 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x640 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x644 "ILF3_IPB_n_549,Input buffer bank" bitfld.long 0x644 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x644 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x648 "ILF3_IPB_n_550,Input buffer bank" bitfld.long 0x648 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x648 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x64C "ILF3_IPB_n_551,Input buffer bank" bitfld.long 0x64C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x64C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x650 "ILF3_IPB_n_552,Input buffer bank" bitfld.long 0x650 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x650 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x654 "ILF3_IPB_n_553,Input buffer bank" bitfld.long 0x654 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x654 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x658 "ILF3_IPB_n_554,Input buffer bank" bitfld.long 0x658 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x658 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x65C "ILF3_IPB_n_555,Input buffer bank" bitfld.long 0x65C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x65C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x660 "ILF3_IPB_n_556,Input buffer bank" bitfld.long 0x660 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x660 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x664 "ILF3_IPB_n_557,Input buffer bank" bitfld.long 0x664 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x664 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x668 "ILF3_IPB_n_558,Input buffer bank" bitfld.long 0x668 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x668 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x66C "ILF3_IPB_n_559,Input buffer bank" bitfld.long 0x66C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x66C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x670 "ILF3_IPB_n_560,Input buffer bank" bitfld.long 0x670 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x670 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x674 "ILF3_IPB_n_561,Input buffer bank" bitfld.long 0x674 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x674 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x678 "ILF3_IPB_n_562,Input buffer bank" bitfld.long 0x678 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x678 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x67C "ILF3_IPB_n_563,Input buffer bank" bitfld.long 0x67C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x67C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x680 "ILF3_IPB_n_564,Input buffer bank" bitfld.long 0x680 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x680 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x684 "ILF3_IPB_n_565,Input buffer bank" bitfld.long 0x684 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x684 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x688 "ILF3_IPB_n_566,Input buffer bank" bitfld.long 0x688 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x688 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x68C "ILF3_IPB_n_567,Input buffer bank" bitfld.long 0x68C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x68C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x690 "ILF3_IPB_n_568,Input buffer bank" bitfld.long 0x690 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x690 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x694 "ILF3_IPB_n_569,Input buffer bank" bitfld.long 0x694 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x694 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x698 "ILF3_IPB_n_570,Input buffer bank" bitfld.long 0x698 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x698 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x69C "ILF3_IPB_n_571,Input buffer bank" bitfld.long 0x69C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x69C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A0 "ILF3_IPB_n_572,Input buffer bank" bitfld.long 0x6A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A4 "ILF3_IPB_n_573,Input buffer bank" bitfld.long 0x6A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6A8 "ILF3_IPB_n_574,Input buffer bank" bitfld.long 0x6A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6AC "ILF3_IPB_n_575,Input buffer bank" bitfld.long 0x6AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B0 "ILF3_IPB_n_576,Input buffer bank" bitfld.long 0x6B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B4 "ILF3_IPB_n_577,Input buffer bank" bitfld.long 0x6B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6B8 "ILF3_IPB_n_578,Input buffer bank" bitfld.long 0x6B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6BC "ILF3_IPB_n_579,Input buffer bank" bitfld.long 0x6BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C0 "ILF3_IPB_n_580,Input buffer bank" bitfld.long 0x6C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C4 "ILF3_IPB_n_581,Input buffer bank" bitfld.long 0x6C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6C8 "ILF3_IPB_n_582,Input buffer bank" bitfld.long 0x6C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6CC "ILF3_IPB_n_583,Input buffer bank" bitfld.long 0x6CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D0 "ILF3_IPB_n_584,Input buffer bank" bitfld.long 0x6D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D4 "ILF3_IPB_n_585,Input buffer bank" bitfld.long 0x6D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6D8 "ILF3_IPB_n_586,Input buffer bank" bitfld.long 0x6D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6DC "ILF3_IPB_n_587,Input buffer bank" bitfld.long 0x6DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E0 "ILF3_IPB_n_588,Input buffer bank" bitfld.long 0x6E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E4 "ILF3_IPB_n_589,Input buffer bank" bitfld.long 0x6E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6E8 "ILF3_IPB_n_590,Input buffer bank" bitfld.long 0x6E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6EC "ILF3_IPB_n_591,Input buffer bank" bitfld.long 0x6EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F0 "ILF3_IPB_n_592,Input buffer bank" bitfld.long 0x6F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F4 "ILF3_IPB_n_593,Input buffer bank" bitfld.long 0x6F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6F8 "ILF3_IPB_n_594,Input buffer bank" bitfld.long 0x6F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x6FC "ILF3_IPB_n_595,Input buffer bank" bitfld.long 0x6FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x6FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x700 "ILF3_IPB_n_596,Input buffer bank" bitfld.long 0x700 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x700 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x704 "ILF3_IPB_n_597,Input buffer bank" bitfld.long 0x704 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x704 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x708 "ILF3_IPB_n_598,Input buffer bank" bitfld.long 0x708 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x708 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x70C "ILF3_IPB_n_599,Input buffer bank" bitfld.long 0x70C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x70C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x710 "ILF3_IPB_n_600,Input buffer bank" bitfld.long 0x710 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x710 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x714 "ILF3_IPB_n_601,Input buffer bank" bitfld.long 0x714 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x714 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x718 "ILF3_IPB_n_602,Input buffer bank" bitfld.long 0x718 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x718 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x71C "ILF3_IPB_n_603,Input buffer bank" bitfld.long 0x71C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x71C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x720 "ILF3_IPB_n_604,Input buffer bank" bitfld.long 0x720 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x720 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x724 "ILF3_IPB_n_605,Input buffer bank" bitfld.long 0x724 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x724 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x728 "ILF3_IPB_n_606,Input buffer bank" bitfld.long 0x728 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x728 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x72C "ILF3_IPB_n_607,Input buffer bank" bitfld.long 0x72C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x72C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x730 "ILF3_IPB_n_608,Input buffer bank" bitfld.long 0x730 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x730 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x734 "ILF3_IPB_n_609,Input buffer bank" bitfld.long 0x734 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x734 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x738 "ILF3_IPB_n_610,Input buffer bank" bitfld.long 0x738 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x738 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x73C "ILF3_IPB_n_611,Input buffer bank" bitfld.long 0x73C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x73C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x740 "ILF3_IPB_n_612,Input buffer bank" bitfld.long 0x740 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x740 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x744 "ILF3_IPB_n_613,Input buffer bank" bitfld.long 0x744 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x744 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x748 "ILF3_IPB_n_614,Input buffer bank" bitfld.long 0x748 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x748 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x74C "ILF3_IPB_n_615,Input buffer bank" bitfld.long 0x74C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x74C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x750 "ILF3_IPB_n_616,Input buffer bank" bitfld.long 0x750 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x750 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x754 "ILF3_IPB_n_617,Input buffer bank" bitfld.long 0x754 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x754 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x758 "ILF3_IPB_n_618,Input buffer bank" bitfld.long 0x758 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x758 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x75C "ILF3_IPB_n_619,Input buffer bank" bitfld.long 0x75C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x75C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x760 "ILF3_IPB_n_620,Input buffer bank" bitfld.long 0x760 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x760 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x764 "ILF3_IPB_n_621,Input buffer bank" bitfld.long 0x764 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x764 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x768 "ILF3_IPB_n_622,Input buffer bank" bitfld.long 0x768 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x768 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x76C "ILF3_IPB_n_623,Input buffer bank" bitfld.long 0x76C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x76C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x770 "ILF3_IPB_n_624,Input buffer bank" bitfld.long 0x770 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x770 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x774 "ILF3_IPB_n_625,Input buffer bank" bitfld.long 0x774 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x774 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x778 "ILF3_IPB_n_626,Input buffer bank" bitfld.long 0x778 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x778 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x77C "ILF3_IPB_n_627,Input buffer bank" bitfld.long 0x77C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x77C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x780 "ILF3_IPB_n_628,Input buffer bank" bitfld.long 0x780 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x780 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x784 "ILF3_IPB_n_629,Input buffer bank" bitfld.long 0x784 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x784 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x788 "ILF3_IPB_n_630,Input buffer bank" bitfld.long 0x788 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x788 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x78C "ILF3_IPB_n_631,Input buffer bank" bitfld.long 0x78C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x78C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x790 "ILF3_IPB_n_632,Input buffer bank" bitfld.long 0x790 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x790 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x794 "ILF3_IPB_n_633,Input buffer bank" bitfld.long 0x794 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x794 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x798 "ILF3_IPB_n_634,Input buffer bank" bitfld.long 0x798 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x798 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x79C "ILF3_IPB_n_635,Input buffer bank" bitfld.long 0x79C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x79C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A0 "ILF3_IPB_n_636,Input buffer bank" bitfld.long 0x7A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A4 "ILF3_IPB_n_637,Input buffer bank" bitfld.long 0x7A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7A8 "ILF3_IPB_n_638,Input buffer bank" bitfld.long 0x7A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7AC "ILF3_IPB_n_639,Input buffer bank" bitfld.long 0x7AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B0 "ILF3_IPB_n_640,Input buffer bank" bitfld.long 0x7B0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B4 "ILF3_IPB_n_641,Input buffer bank" bitfld.long 0x7B4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7B8 "ILF3_IPB_n_642,Input buffer bank" bitfld.long 0x7B8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7B8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7BC "ILF3_IPB_n_643,Input buffer bank" bitfld.long 0x7BC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7BC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C0 "ILF3_IPB_n_644,Input buffer bank" bitfld.long 0x7C0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C4 "ILF3_IPB_n_645,Input buffer bank" bitfld.long 0x7C4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7C8 "ILF3_IPB_n_646,Input buffer bank" bitfld.long 0x7C8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7C8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7CC "ILF3_IPB_n_647,Input buffer bank" bitfld.long 0x7CC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7CC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D0 "ILF3_IPB_n_648,Input buffer bank" bitfld.long 0x7D0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D4 "ILF3_IPB_n_649,Input buffer bank" bitfld.long 0x7D4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7D8 "ILF3_IPB_n_650,Input buffer bank" bitfld.long 0x7D8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7D8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7DC "ILF3_IPB_n_651,Input buffer bank" bitfld.long 0x7DC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7DC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E0 "ILF3_IPB_n_652,Input buffer bank" bitfld.long 0x7E0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E4 "ILF3_IPB_n_653,Input buffer bank" bitfld.long 0x7E4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7E8 "ILF3_IPB_n_654,Input buffer bank" bitfld.long 0x7E8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7E8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7EC "ILF3_IPB_n_655,Input buffer bank" bitfld.long 0x7EC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7EC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F0 "ILF3_IPB_n_656,Input buffer bank" bitfld.long 0x7F0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F4 "ILF3_IPB_n_657,Input buffer bank" bitfld.long 0x7F4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7F8 "ILF3_IPB_n_658,Input buffer bank" bitfld.long 0x7F8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7F8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x7FC "ILF3_IPB_n_659,Input buffer bank" bitfld.long 0x7FC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x7FC 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x800 "ILF3_IPB_n_660,Input buffer bank" bitfld.long 0x800 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x800 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x804 "ILF3_IPB_n_661,Input buffer bank" bitfld.long 0x804 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x804 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x808 "ILF3_IPB_n_662,Input buffer bank" bitfld.long 0x808 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x808 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x80C "ILF3_IPB_n_663,Input buffer bank" bitfld.long 0x80C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x80C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x810 "ILF3_IPB_n_664,Input buffer bank" bitfld.long 0x810 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x810 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x814 "ILF3_IPB_n_665,Input buffer bank" bitfld.long 0x814 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x814 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x818 "ILF3_IPB_n_666,Input buffer bank" bitfld.long 0x818 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x818 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x81C "ILF3_IPB_n_667,Input buffer bank" bitfld.long 0x81C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x81C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x820 "ILF3_IPB_n_668,Input buffer bank" bitfld.long 0x820 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x820 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x824 "ILF3_IPB_n_669,Input buffer bank" bitfld.long 0x824 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x824 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x828 "ILF3_IPB_n_670,Input buffer bank" bitfld.long 0x828 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x828 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x82C "ILF3_IPB_n_671,Input buffer bank" bitfld.long 0x82C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x82C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x830 "ILF3_IPB_n_672,Input buffer bank" bitfld.long 0x830 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x830 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x834 "ILF3_IPB_n_673,Input buffer bank" bitfld.long 0x834 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x834 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x838 "ILF3_IPB_n_674,Input buffer bank" bitfld.long 0x838 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x838 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x83C "ILF3_IPB_n_675,Input buffer bank" bitfld.long 0x83C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x83C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x840 "ILF3_IPB_n_676,Input buffer bank" bitfld.long 0x840 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x840 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x844 "ILF3_IPB_n_677,Input buffer bank" bitfld.long 0x844 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x844 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x848 "ILF3_IPB_n_678,Input buffer bank" bitfld.long 0x848 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x848 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x84C "ILF3_IPB_n_679,Input buffer bank" bitfld.long 0x84C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x84C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x850 "ILF3_IPB_n_680,Input buffer bank" bitfld.long 0x850 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x850 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x854 "ILF3_IPB_n_681,Input buffer bank" bitfld.long 0x854 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x854 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x858 "ILF3_IPB_n_682,Input buffer bank" bitfld.long 0x858 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x858 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x85C "ILF3_IPB_n_683,Input buffer bank" bitfld.long 0x85C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x85C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x860 "ILF3_IPB_n_684,Input buffer bank" bitfld.long 0x860 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x860 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x864 "ILF3_IPB_n_685,Input buffer bank" bitfld.long 0x864 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x864 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x868 "ILF3_IPB_n_686,Input buffer bank" bitfld.long 0x868 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x868 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x86C "ILF3_IPB_n_687,Input buffer bank" bitfld.long 0x86C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x86C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x870 "ILF3_IPB_n_688,Input buffer bank" bitfld.long 0x870 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x870 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x874 "ILF3_IPB_n_689,Input buffer bank" bitfld.long 0x874 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x874 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x878 "ILF3_IPB_n_690,Input buffer bank" bitfld.long 0x878 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x878 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x87C "ILF3_IPB_n_691,Input buffer bank" bitfld.long 0x87C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x87C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x880 "ILF3_IPB_n_692,Input buffer bank" bitfld.long 0x880 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x880 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x884 "ILF3_IPB_n_693,Input buffer bank" bitfld.long 0x884 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x884 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x888 "ILF3_IPB_n_694,Input buffer bank" bitfld.long 0x888 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x888 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x88C "ILF3_IPB_n_695,Input buffer bank" bitfld.long 0x88C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x88C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x890 "ILF3_IPB_n_696,Input buffer bank" bitfld.long 0x890 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x890 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x894 "ILF3_IPB_n_697,Input buffer bank" bitfld.long 0x894 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x894 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x898 "ILF3_IPB_n_698,Input buffer bank" bitfld.long 0x898 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x898 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x89C "ILF3_IPB_n_699,Input buffer bank" bitfld.long 0x89C 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x89C 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A0 "ILF3_IPB_n_700,Input buffer bank" bitfld.long 0x8A0 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A0 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A4 "ILF3_IPB_n_701,Input buffer bank" bitfld.long 0x8A4 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A4 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8A8 "ILF3_IPB_n_702,Input buffer bank" bitfld.long 0x8A8 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8A8 0.--7. 1. "IPB_BYTE,Byte element of IPB" line.long 0x8AC "ILF3_IPB_n_703,Input buffer bank" bitfld.long 0x8AC 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8AC 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_15" group.long 0x204++0x03 line.long 0x00 "ILF3_BS_l_15,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x458++0x03 line.long 0x00 "ILF3_IPB_n_15,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x88++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_15,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x164++0x03 line.long 0x00 "ILF3_QP_IDX_j_15,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x11C++0x03 line.long 0x00 "ILF3_QP_m_15,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_16" group.long 0x208++0x03 line.long 0x00 "ILF3_BS_l_16,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x45C++0x03 line.long 0x00 "ILF3_IPB_n_16,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x168++0x03 line.long 0x00 "ILF3_QP_IDX_j_16,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "ILF3_QP_m_16,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_17" group.long 0x20C++0x03 line.long 0x00 "ILF3_BS_l_17,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x460++0x03 line.long 0x00 "ILF3_IPB_n_17,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x16C++0x03 line.long 0x00 "ILF3_QP_IDX_j_17,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "ILF3_QP_m_17,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_18" group.long 0x210++0x03 line.long 0x00 "ILF3_BS_l_18,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x464++0x03 line.long 0x00 "ILF3_IPB_n_18,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x170++0x03 line.long 0x00 "ILF3_QP_IDX_j_18,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_19" group.long 0x214++0x03 line.long 0x00 "ILF3_BS_l_19,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x468++0x03 line.long 0x00 "ILF3_IPB_n_19,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x174++0x03 line.long 0x00 "ILF3_QP_IDX_j_19,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_2" group.long 0x1D0++0x03 line.long 0x00 "ILF3_BS_l_2,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x424++0x03 line.long 0x00 "ILF3_IPB_n_2,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x9C++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_2,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_2,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x54++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_2,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x130++0x03 line.long 0x00 "ILF3_QP_IDX_j_2,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE8++0x03 line.long 0x00 "ILF3_QP_m_2,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC4++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_2,MBConfig table contains pointers used by program to control the ILF3 units" tree.end tree "Channel_20" group.long 0x218++0x03 line.long 0x00 "ILF3_BS_l_20,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x46C++0x03 line.long 0x00 "ILF3_IPB_n_20,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x178++0x03 line.long 0x00 "ILF3_QP_IDX_j_20,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_21" group.long 0x21C++0x03 line.long 0x00 "ILF3_BS_l_21,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x470++0x03 line.long 0x00 "ILF3_IPB_n_21,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x17C++0x03 line.long 0x00 "ILF3_QP_IDX_j_21,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_22" group.long 0x220++0x03 line.long 0x00 "ILF3_BS_l_22,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x474++0x03 line.long 0x00 "ILF3_IPB_n_22,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x180++0x03 line.long 0x00 "ILF3_QP_IDX_j_22,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_23" group.long 0x224++0x03 line.long 0x00 "ILF3_BS_l_23,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x478++0x03 line.long 0x00 "ILF3_IPB_n_23,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x184++0x03 line.long 0x00 "ILF3_QP_IDX_j_23,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_24" group.long 0x228++0x03 line.long 0x00 "ILF3_BS_l_24,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x47C++0x03 line.long 0x00 "ILF3_IPB_n_24,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x188++0x03 line.long 0x00 "ILF3_QP_IDX_j_24,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_25" group.long 0x22C++0x03 line.long 0x00 "ILF3_BS_l_25,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x480++0x03 line.long 0x00 "ILF3_IPB_n_25,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x18C++0x03 line.long 0x00 "ILF3_QP_IDX_j_25,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_26" group.long 0x230++0x03 line.long 0x00 "ILF3_BS_l_26,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x484++0x03 line.long 0x00 "ILF3_IPB_n_26,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x190++0x03 line.long 0x00 "ILF3_QP_IDX_j_26,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_27" group.long 0x234++0x03 line.long 0x00 "ILF3_BS_l_27,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x488++0x03 line.long 0x00 "ILF3_IPB_n_27,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x194++0x03 line.long 0x00 "ILF3_QP_IDX_j_27,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_28" group.long 0x238++0x03 line.long 0x00 "ILF3_BS_l_28,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48C++0x03 line.long 0x00 "ILF3_IPB_n_28,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x198++0x03 line.long 0x00 "ILF3_QP_IDX_j_28,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_29" group.long 0x23C++0x03 line.long 0x00 "ILF3_BS_l_29,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x490++0x03 line.long 0x00 "ILF3_IPB_n_29,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x19C++0x03 line.long 0x00 "ILF3_QP_IDX_j_29,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_3" group.long 0x1D4++0x03 line.long 0x00 "ILF3_BS_l_3,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x03 line.long 0x00 "ILF3_IPB_n_3,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0xA0++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x58++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x134++0x03 line.long 0x00 "ILF3_QP_IDX_j_3,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "ILF3_QP_m_3,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_30" group.long 0x240++0x03 line.long 0x00 "ILF3_BS_l_30,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x494++0x03 line.long 0x00 "ILF3_IPB_n_30,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A0++0x03 line.long 0x00 "ILF3_QP_IDX_j_30,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_31" group.long 0x244++0x03 line.long 0x00 "ILF3_BS_l_31,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x498++0x03 line.long 0x00 "ILF3_IPB_n_31,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A4++0x03 line.long 0x00 "ILF3_QP_IDX_j_31,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_32" group.long 0x248++0x03 line.long 0x00 "ILF3_BS_l_32,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x49C++0x03 line.long 0x00 "ILF3_IPB_n_32,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1A8++0x03 line.long 0x00 "ILF3_QP_IDX_j_32,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_33" group.long 0x24C++0x03 line.long 0x00 "ILF3_BS_l_33,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A0++0x03 line.long 0x00 "ILF3_IPB_n_33,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1AC++0x03 line.long 0x00 "ILF3_QP_IDX_j_33,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_34" group.long 0x250++0x03 line.long 0x00 "ILF3_BS_l_34,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A4++0x03 line.long 0x00 "ILF3_IPB_n_34,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B0++0x03 line.long 0x00 "ILF3_QP_IDX_j_34,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_35" group.long 0x254++0x03 line.long 0x00 "ILF3_BS_l_35,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A8++0x03 line.long 0x00 "ILF3_IPB_n_35,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B4++0x03 line.long 0x00 "ILF3_QP_IDX_j_35,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_36" group.long 0x258++0x03 line.long 0x00 "ILF3_BS_l_36,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4AC++0x03 line.long 0x00 "ILF3_IPB_n_36,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B8++0x03 line.long 0x00 "ILF3_QP_IDX_j_36,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_37" group.long 0x25C++0x03 line.long 0x00 "ILF3_BS_l_37,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B0++0x03 line.long 0x00 "ILF3_IPB_n_37,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1BC++0x03 line.long 0x00 "ILF3_QP_IDX_j_37,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_38" group.long 0x260++0x03 line.long 0x00 "ILF3_BS_l_38,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B4++0x03 line.long 0x00 "ILF3_IPB_n_38,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1C0++0x03 line.long 0x00 "ILF3_QP_IDX_j_38,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_39" group.long 0x264++0x03 line.long 0x00 "ILF3_BS_l_39,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B8++0x03 line.long 0x00 "ILF3_IPB_n_39,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1C4++0x03 line.long 0x00 "ILF3_QP_IDX_j_39,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end tree "Channel_4" group.long 0x1D8++0x03 line.long 0x00 "ILF3_BS_l_4,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x03 line.long 0x00 "ILF3_IPB_n_4,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x5C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_4,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x138++0x03 line.long 0x00 "ILF3_QP_IDX_j_4,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF0++0x03 line.long 0x00 "ILF3_QP_m_4,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_40" group.long 0x268++0x03 line.long 0x00 "ILF3_BS_l_40,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4BC++0x03 line.long 0x00 "ILF3_IPB_n_40,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_41" group.long 0x26C++0x03 line.long 0x00 "ILF3_BS_l_41,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C0++0x03 line.long 0x00 "ILF3_IPB_n_41,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_42" group.long 0x270++0x03 line.long 0x00 "ILF3_BS_l_42,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C4++0x03 line.long 0x00 "ILF3_IPB_n_42,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_43" group.long 0x274++0x03 line.long 0x00 "ILF3_BS_l_43,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C8++0x03 line.long 0x00 "ILF3_IPB_n_43,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_44" group.long 0x278++0x03 line.long 0x00 "ILF3_BS_l_44,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4CC++0x03 line.long 0x00 "ILF3_IPB_n_44,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_45" group.long 0x27C++0x03 line.long 0x00 "ILF3_BS_l_45,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D0++0x03 line.long 0x00 "ILF3_IPB_n_45,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_46" group.long 0x280++0x03 line.long 0x00 "ILF3_BS_l_46,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D4++0x03 line.long 0x00 "ILF3_IPB_n_46,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_47" group.long 0x284++0x03 line.long 0x00 "ILF3_BS_l_47,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D8++0x03 line.long 0x00 "ILF3_IPB_n_47,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_48" group.long 0x288++0x03 line.long 0x00 "ILF3_BS_l_48,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4DC++0x03 line.long 0x00 "ILF3_IPB_n_48,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_49" group.long 0x28C++0x03 line.long 0x00 "ILF3_BS_l_49,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E0++0x03 line.long 0x00 "ILF3_IPB_n_49,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_5" group.long 0x1DC++0x03 line.long 0x00 "ILF3_BS_l_5,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x430++0x03 line.long 0x00 "ILF3_IPB_n_5,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x60++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_5,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x13C++0x03 line.long 0x00 "ILF3_QP_IDX_j_5,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF4++0x03 line.long 0x00 "ILF3_QP_m_5,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_50" group.long 0x290++0x03 line.long 0x00 "ILF3_BS_l_50,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E4++0x03 line.long 0x00 "ILF3_IPB_n_50,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_51" group.long 0x294++0x03 line.long 0x00 "ILF3_BS_l_51,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E8++0x03 line.long 0x00 "ILF3_IPB_n_51,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_52" group.long 0x298++0x03 line.long 0x00 "ILF3_BS_l_52,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4EC++0x03 line.long 0x00 "ILF3_IPB_n_52,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_53" group.long 0x29C++0x03 line.long 0x00 "ILF3_BS_l_53,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F0++0x03 line.long 0x00 "ILF3_IPB_n_53,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_54" group.long 0x2A0++0x03 line.long 0x00 "ILF3_BS_l_54,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F4++0x03 line.long 0x00 "ILF3_IPB_n_54,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_55" group.long 0x2A4++0x03 line.long 0x00 "ILF3_BS_l_55,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4F8++0x03 line.long 0x00 "ILF3_IPB_n_55,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_56" group.long 0x2A8++0x03 line.long 0x00 "ILF3_BS_l_56,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4FC++0x03 line.long 0x00 "ILF3_IPB_n_56,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_57" group.long 0x2AC++0x03 line.long 0x00 "ILF3_BS_l_57,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x500++0x03 line.long 0x00 "ILF3_IPB_n_57,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_58" group.long 0x2B0++0x03 line.long 0x00 "ILF3_BS_l_58,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x504++0x03 line.long 0x00 "ILF3_IPB_n_58,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_59" group.long 0x2B4++0x03 line.long 0x00 "ILF3_BS_l_59,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x508++0x03 line.long 0x00 "ILF3_IPB_n_59,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_6" group.long 0x1E0++0x03 line.long 0x00 "ILF3_BS_l_6,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x434++0x03 line.long 0x00 "ILF3_IPB_n_6,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x64++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_6,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x140++0x03 line.long 0x00 "ILF3_QP_IDX_j_6,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xF8++0x03 line.long 0x00 "ILF3_QP_m_6,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_60" group.long 0x2B8++0x03 line.long 0x00 "ILF3_BS_l_60,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50C++0x03 line.long 0x00 "ILF3_IPB_n_60,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_61" group.long 0x2BC++0x03 line.long 0x00 "ILF3_BS_l_61,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x510++0x03 line.long 0x00 "ILF3_IPB_n_61,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_62" group.long 0x2C0++0x03 line.long 0x00 "ILF3_BS_l_62,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x514++0x03 line.long 0x00 "ILF3_IPB_n_62,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_63" group.long 0x2C4++0x03 line.long 0x00 "ILF3_BS_l_63,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x518++0x03 line.long 0x00 "ILF3_IPB_n_63,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_64" group.long 0x2C8++0x03 line.long 0x00 "ILF3_BS_l_64,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x51C++0x03 line.long 0x00 "ILF3_IPB_n_64,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_65" group.long 0x2CC++0x03 line.long 0x00 "ILF3_BS_l_65,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x520++0x03 line.long 0x00 "ILF3_IPB_n_65,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_66" group.long 0x2D0++0x03 line.long 0x00 "ILF3_BS_l_66,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x524++0x03 line.long 0x00 "ILF3_IPB_n_66,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_67" group.long 0x2D4++0x03 line.long 0x00 "ILF3_BS_l_67,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x528++0x03 line.long 0x00 "ILF3_IPB_n_67,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_68" group.long 0x2D8++0x03 line.long 0x00 "ILF3_BS_l_68,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x52C++0x03 line.long 0x00 "ILF3_IPB_n_68,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_69" group.long 0x2DC++0x03 line.long 0x00 "ILF3_BS_l_69,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x530++0x03 line.long 0x00 "ILF3_IPB_n_69,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_7" group.long 0x1E4++0x03 line.long 0x00 "ILF3_BS_l_7,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x438++0x03 line.long 0x00 "ILF3_IPB_n_7,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x68++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_7,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x144++0x03 line.long 0x00 "ILF3_QP_IDX_j_7,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xFC++0x03 line.long 0x00 "ILF3_QP_m_7,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_70" group.long 0x2E0++0x03 line.long 0x00 "ILF3_BS_l_70,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x534++0x03 line.long 0x00 "ILF3_IPB_n_70,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_71" group.long 0x2E4++0x03 line.long 0x00 "ILF3_BS_l_71,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x538++0x03 line.long 0x00 "ILF3_IPB_n_71,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_72" group.long 0x2E8++0x03 line.long 0x00 "ILF3_BS_l_72,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x53C++0x03 line.long 0x00 "ILF3_IPB_n_72,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_73" group.long 0x2EC++0x03 line.long 0x00 "ILF3_BS_l_73,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x540++0x03 line.long 0x00 "ILF3_IPB_n_73,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_74" group.long 0x2F0++0x03 line.long 0x00 "ILF3_BS_l_74,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x544++0x03 line.long 0x00 "ILF3_IPB_n_74,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_75" group.long 0x2F4++0x03 line.long 0x00 "ILF3_BS_l_75,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x548++0x03 line.long 0x00 "ILF3_IPB_n_75,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_76" group.long 0x2F8++0x03 line.long 0x00 "ILF3_BS_l_76,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54C++0x03 line.long 0x00 "ILF3_IPB_n_76,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_77" group.long 0x2FC++0x03 line.long 0x00 "ILF3_BS_l_77,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x550++0x03 line.long 0x00 "ILF3_IPB_n_77,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_78" group.long 0x300++0x03 line.long 0x00 "ILF3_BS_l_78,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x554++0x03 line.long 0x00 "ILF3_IPB_n_78,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_79" group.long 0x304++0x03 line.long 0x00 "ILF3_BS_l_79,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x558++0x03 line.long 0x00 "ILF3_IPB_n_79,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_8" group.long 0x1E8++0x03 line.long 0x00 "ILF3_BS_l_8,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43C++0x03 line.long 0x00 "ILF3_IPB_n_8,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x6C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_8,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x148++0x03 line.long 0x00 "ILF3_QP_IDX_j_8,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x100++0x03 line.long 0x00 "ILF3_QP_m_8,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_80" group.long 0x308++0x03 line.long 0x00 "ILF3_BS_l_80,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x55C++0x03 line.long 0x00 "ILF3_IPB_n_80,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_81" group.long 0x30C++0x03 line.long 0x00 "ILF3_BS_l_81,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x560++0x03 line.long 0x00 "ILF3_IPB_n_81,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_82" group.long 0x310++0x03 line.long 0x00 "ILF3_BS_l_82,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x564++0x03 line.long 0x00 "ILF3_IPB_n_82,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_83" group.long 0x314++0x03 line.long 0x00 "ILF3_BS_l_83,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x568++0x03 line.long 0x00 "ILF3_IPB_n_83,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_84" group.long 0x318++0x03 line.long 0x00 "ILF3_BS_l_84,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x56C++0x03 line.long 0x00 "ILF3_IPB_n_84,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_85" group.long 0x31C++0x03 line.long 0x00 "ILF3_BS_l_85,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x570++0x03 line.long 0x00 "ILF3_IPB_n_85,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_86" group.long 0x320++0x03 line.long 0x00 "ILF3_BS_l_86,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x574++0x03 line.long 0x00 "ILF3_IPB_n_86,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_87" group.long 0x324++0x03 line.long 0x00 "ILF3_BS_l_87,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x578++0x03 line.long 0x00 "ILF3_IPB_n_87,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_88" group.long 0x328++0x03 line.long 0x00 "ILF3_BS_l_88,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x57C++0x03 line.long 0x00 "ILF3_IPB_n_88,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_89" group.long 0x32C++0x03 line.long 0x00 "ILF3_BS_l_89,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x580++0x03 line.long 0x00 "ILF3_IPB_n_89,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_9" group.long 0x1EC++0x03 line.long 0x00 "ILF3_BS_l_9,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x440++0x03 line.long 0x00 "ILF3_IPB_n_9,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x70++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_9,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x14C++0x03 line.long 0x00 "ILF3_QP_IDX_j_9,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x104++0x03 line.long 0x00 "ILF3_QP_m_9,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Channel_90" group.long 0x330++0x03 line.long 0x00 "ILF3_BS_l_90,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x584++0x03 line.long 0x00 "ILF3_IPB_n_90,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_91" group.long 0x334++0x03 line.long 0x00 "ILF3_BS_l_91,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x588++0x03 line.long 0x00 "ILF3_IPB_n_91,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_92" group.long 0x338++0x03 line.long 0x00 "ILF3_BS_l_92,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x58C++0x03 line.long 0x00 "ILF3_IPB_n_92,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_93" group.long 0x33C++0x03 line.long 0x00 "ILF3_BS_l_93,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x590++0x03 line.long 0x00 "ILF3_IPB_n_93,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_94" group.long 0x340++0x03 line.long 0x00 "ILF3_BS_l_94,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x594++0x03 line.long 0x00 "ILF3_IPB_n_94,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_95" group.long 0x344++0x03 line.long 0x00 "ILF3_BS_l_95,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x598++0x03 line.long 0x00 "ILF3_IPB_n_95,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_96" group.long 0x348++0x03 line.long 0x00 "ILF3_BS_l_96,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x59C++0x03 line.long 0x00 "ILF3_IPB_n_96,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_97" group.long 0x34C++0x03 line.long 0x00 "ILF3_BS_l_97,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A0++0x03 line.long 0x00 "ILF3_IPB_n_97,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_98" group.long 0x350++0x03 line.long 0x00 "ILF3_BS_l_98,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A4++0x03 line.long 0x00 "ILF3_IPB_n_98,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end tree "Channel_99" group.long 0x354++0x03 line.long 0x00 "ILF3_BS_l_99,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5A8++0x03 line.long 0x00 "ILF3_IPB_n_99,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end group.long 0xFFC++0x03 line.long 0x00 "ILF3_COMMAND,ILF3 command register: A write to this register decodes a command" bitfld.long 0x00 0.--2. "CMD,DATA/COMMAND 0x1 -> Start() 0x2 -> Stop() 0x3 -> DbgEn() 0x4 -> DbgDis() 0x5 -> DbgStep()" "0,1,2,3,4,5,6,7" group.long 0x30++0x03 line.long 0x00 "ILF3_CONFIG,Configuration register" hexmask.long.byte 0x00 24.--31. 1. "AUTOINCCOUNTER,This field indicates the current increment in MB for the auto-increment mechanism" bitfld.long 0x00 17.--18. "MBINFO_SIZE,Selects one of the three different MBinfo sizes to be loaded" "MBINFO_SIZE_0,MBINFO_SIZE_1,MBINFO_SIZE_2,MBINFO_SIZE_3" newline bitfld.long 0x00 16. "IRQAUTOCLEAR_EN," "0,1" hexmask.long.byte 0x00 8.--15. 1. "CODEC,Indicates the codec to be used" newline bitfld.long 0x00 0.--4. "PPA_TASK,Bit" "Load MB info Bit,Compute BS,Load MB,Filter MB,Store MB,?..." group.long 0x18++0x03 line.long 0x00 "ILF3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x28++0x03 line.long 0x00 "ILF3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x24++0x03 line.long 0x00 "ILF3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x20++0x03 line.long 0x00 "ILF3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0x1C++0x03 line.long 0x00 "ILF3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0xB0++0x03 line.long 0x00 "ILF3_MBCONFIG_AUTOINC,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 11. "AUTOINC,This bit must set to 1 to activate the auto-increment scheme" "0,1" bitfld.long 0x00 8.--10. "PIXEL_FORMAT,This field indicates the number of pixel rows in the top-row buffer and also the number of rows of 8-bit pixels and 16-bit pixels (VC-1 case with OVT activated)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_COUNT,Maximum value of Counter for auto-increment" repeat 2. (list 0123. 4567. )(list 0x00 0x04 ) group.long ($2+0x8C)++0x03 line.long 0x00 "ILF3_MBCONFIG_COEFFICIENTS$1,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.byte 0x00 24.--31. 1. "COEFF3,GDP coefficient 3" hexmask.long.byte 0x00 16.--23. 1. "COEFF2,GDP coefficient 2" newline hexmask.long.byte 0x00 8.--15. 1. "COEFF1,GDP coefficient 1" hexmask.long.byte 0x00 0.--7. 1. "COEFF0,GDP coefficient 0" repeat.end group.long 0xB4++0x03 line.long 0x00 "ILF3_MBCONFIG_NEXTMBCONFIG,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 0.--15. 1. "NEXTMBCONFIGADDRESS,Contains the next MB address" group.long 0x38++0x07 line.long 0x00 "ILF3_MBCONFIG_SLICEINFO01,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "SLICEINFO1,Parameter" hexmask.long.word 0x00 0.--15. 1. "SLICEINFO0,Parameter" line.long 0x04 "ILF3_MBCONFIG_SLICEINFO2,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x04 0.--15. 1. "MBCONFIG_ADDRESS_SLICEINFO2,Parameter" group.long 0xB8++0x03 line.long 0x00 "ILF3_MBSTATUS,Provides MB properties" bitfld.long 0x00 25. "ISFIRSTMB,Indicates which MB of the MB pair is being processed" "ISFIRSTMB_0,ISFIRSTMB_1" bitfld.long 0x00 23.--24. "COMPONENT,Indicates if IPB contains Luma or Chroma pixels" "Luma pixels,Chroma pixels,?..." newline bitfld.long 0x00 22. "TOP_LEFT_FIELD,Indicates the type of the top-left MB pair" "TOP_LEFT_FIELD_0_r,TOP_LEFT_FIELD_1_r" bitfld.long 0x00 21. "TOP_FIELD,Indicates the type of the top MB pair" "TOP_FIELD_0_r,TOP_FIELD_1_r" newline bitfld.long 0x00 20. "LEFT_FIELD,Indicates the type of the left MB pair" "LEFT_FIELD_0_r,LEFT_FIELD_1_r" bitfld.long 0x00 19. "CUR_FIELD,Indicates the type of the current MB" "CUR_FIELD_0_r,CUR_FIELD_1_r" newline bitfld.long 0x00 17.--18. "ALT_V,Indicates the type of left edge" "ALT_V_0_r,ALT_V_1_r,ALT_V_2_r,ALT_V_3_r" bitfld.long 0x00 16. "ALT_H,Indicates the type of the top horizontal edge" "ALT_H_0_r,ALT_H_1_r" newline bitfld.long 0x00 8. "LOAD_SLICEINFO,This flag indicates if the slice information must be updated or not" "LOAD_SLICEINFO_0_r,LOAD_SLICEINFO_1_r" bitfld.long 0x00 0.--4. "PPA_TASK_STATUS,1 means which elementary task has been executed" "Load MB info Bit,Compute BS Bit,Load MB Bit,Filter MB Bit,Store MB,?..." rgroup.long 0x00++0x03 line.long 0x00 "ILF3_REVISION,IP revision identifier (X.Y.R) Used by software to track features. bugs. and compatibility" rgroup.long 0x34++0x03 line.long 0x00 "ILF3_STATUS,Provides information on the progress of the ILF3 execution" bitfld.long 0x00 27. "WRITEREGERROR,This bit is cleared by a Start() command when in INITIALIZED or COMPLETED state" "WRITEREGERROR_0_r,WRITEREGERROR_1_r" bitfld.long 0x00 24.--25. "EXECSTATE,Execution states" "EXECSTATE_0_r,EXECSTATE_1_r,EXECSTATE_2_r,EXECSTATE_3_r" newline hexmask.long.word 0x00 0.--15. 1. "CYCLECOUNT,Total number of cycles executed" group.long 0x10++0x03 line.long 0x00 "ILF3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset (optional)" "SOFTRESET_0_w,SOFTRESET_1_r" width 0x0B tree.end tree.end tree "IVA_Motion_Compensation" sif (cpuis("TDA2PXIVA*")) tree "MC3_BFSW_ICONT" base ad:0xD9200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_YBUF,View mode selection for Y buffer" "Full view mode is selected,Ping-pong view mode is selected" bitfld.long 0x00 0. "VIEW_XBUF,View mode selection for X buffer" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "MSTID1,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_YBUF_B,Master selection for Y buffer B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 2. "MST_YBUF_A,Master selection for Y buffer A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" newline bitfld.long 0x04 1. "MST_XBUF_B,Master selection for X buffer B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 0. "MST_XBUF_A,Master selection for X buffer A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" line.long 0x08 "MSTID2,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_JBUF,Master selection for J buffer" "Buffer is assigned to DMA,Buffer is assigned to HWA" bitfld.long 0x08 0. "MST_IBUF,Master selection for I buffer" "Buffer is assigned to DMA,Buffer is assigned to HWA" width 0x0B tree.end endif tree "MC3_BFSW_L3_MAINInterconnect" base ad:0x5A059200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_YBUF,View mode selection for Y buffer" "Full view mode is selected,Ping-pong view mode is selected" bitfld.long 0x00 0. "VIEW_XBUF,View mode selection for X buffer" "Full view mode is selected,Ping-pong view mode is selected" line.long 0x04 "MSTID1,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_YBUF_B,Master selection for Y buffer B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 2. "MST_YBUF_A,Master selection for Y buffer A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" newline bitfld.long 0x04 1. "MST_XBUF_B,Master selection for X buffer B" "Buffer B is assigned to DMA,Buffer B is assigned to HWA" bitfld.long 0x04 0. "MST_XBUF_A,Master selection for X buffer A" "Buffer A is assigned to DMA,Buffer A is assigned to HWA" line.long 0x08 "MSTID2,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_JBUF,Master selection for J buffer" "Buffer is assigned to DMA,Buffer is assigned to HWA" bitfld.long 0x08 0. "MST_IBUF,Master selection for I buffer" "Buffer is assigned to DMA,Buffer is assigned to HWA" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "MC3_IPGW_ICONT" base ad:0xD9400 group.long 0x08++0x07 line.long 0x00 "MC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "MC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "MC3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x04 "MC3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x08 "MC3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x0C "MC3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" group.long 0x30++0x0F line.long 0x00 "MC3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "MC3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "MC3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "MC3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "MC3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "MC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "MC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrup..t" line.long 0x0C "MC3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "MC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "MC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "MC3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "MC3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line 2" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "MC3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end endif tree "MC3_IPGW_L3_MAINInterconnect" base ad:0x5A059400 group.long 0x08++0x07 line.long 0x00 "MC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "MC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "MC3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x04 "MC3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x08 "MC3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" line.long 0x0C "MC3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Settable raw status for event 0" "No event pending,Set event (debug)" group.long 0x30++0x0F line.long 0x00 "MC3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x04 "MC3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x08 "MC3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" line.long 0x0C "MC3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "No (enabled) event pending,Clear (raw) event" group.long 0x4C++0x0F line.long 0x00 "MC3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x04 "MC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" line.long 0x08 "MC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrup..t" line.long 0x0C "MC3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Enable interrupt" group.long 0x68++0x0F line.long 0x00 "MC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x04 "MC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x08 "MC3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x08 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" line.long 0x0C "MC3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. line 2" bitfld.long 0x0C 0. "ENABLE0,Enable for event 0" "Interrupt disabled (masked),Disable interrupt" group.long 0xC0++0x03 line.long 0x00 "MC3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" width 0x0B tree.end tree "MC3_LSE_ICONT" base ad:0xD9300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9]: OCP CFG IP_CORE side" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr = 1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to understand prologue(first MB) as below: -token status signal -token start/end signal -DMA pointer" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single step mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command status" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on bypass mode Target ParamAddr_ld_byps need to set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on bypass mode" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on bypass mode Target ParamAddr_st_byps needs to set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SYNCBOX_MC3 bypass mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in bypass mode" width 0x0B tree.end tree "MC3_LSE_L3_MAINInterconnect" base ad:0x5A059300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9]: OCP CFG IP_CORE side" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr = 1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to understand prologue(first MB) as below: -token status signal -token start/end signal -DMA pointer" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single step mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command status" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on bypass mode Target ParamAddr_ld_byps need to set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on bypass mode" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on bypass mode Target ParamAddr_st_byps needs to set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SYNCBOX_MC3 bypass mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in bypass mode" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "MC3_MMR_ICONT" base ad:0xD9000 rgroup.long 0x00++0x0F line.long 0x00 "MC_PID,PID register" line.long 0x04 "MC_CNT,Benchmark counter register" bitfld.long 0x04 31. "MC_CNT_EN,Counter enable (MC_CNT_EN)" "The benchmark counter is disabled,The benchmark counter is enabled" bitfld.long 0x04 30. "MC_CNT_RST,Counter reset (MC_CNT_RST) Writing 0 results in no effect" "MC_CNT_RST_0,MC_CNT_RST_1" hexmask.long.word 0x04 0.--15. 1. "MC_COUNT,Counter value (MC_COUNT)" line.long 0x08 "MC_CTRL,Control register" bitfld.long 0x08 2. "MC_DBG,H.264 MBAFF debug mode bit (MC_DBG)" "Normal mode,Debug mode(1MB prediction/step)" bitfld.long 0x08 0. "MC_EN,Module start and status (MC_EN)" "Idle,Busy" line.long 0x0C "MC_PARAM0,Motion compression parameter register" bitfld.long 0x0C 29. "VC1_SMP_MOD,VC-1 sample mode" "Bilinear Interpolation,Bicubic Interpolation" bitfld.long 0x0C 28. "VC1_RND_CTRL,VC-1 round control bit" "VC1_RND_CTRL_0,VC1_RND_CTRL_1" bitfld.long 0x0C 10.--11. "H264_WGT_BIPRD_IDC,H.264 weighted_bipred_idc" "H264_WGT_BIPRD_IDC_0,H264_WGT_BIPRD_IDC_1,H264_WGT_BIPRD_IDC_2,H264_WGT_BIPRD_IDC_3" newline bitfld.long 0x0C 9. "H264_WGT_PRD,H.264 weighted_pred_flag" "H264_WGT_PRD_0,H264_WGT_PRD_1" bitfld.long 0x0C 0.--3. "CODEC_TYPE,Codec_type select" "H.264,?,VC-1,?,MPEG-4,MPEG-2,AVS-1.0,?,RealVideo-8/9/10,On2 VP6,On2 VP7,?..." hgroup.long 0x10++0x03 hide.long 0x00 "MC_PARAM1,Motion compression parameter register" group.long 0x18++0x0F line.long 0x00 "MC_ADDR_0,Base address of reference data Luma L0" hexmask.long.word 0x00 16.--31. 1. "BASE_YREF_BOT_L0_ADD,Base address of reference data Y L0 bottom (BASE_YREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x00 0.--15. 1. "BASE_YREF_TOP_L0_ADD,Base address of reference data Y L0 top (BASE_YREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x04 "MC_ADDR_1,Base address of reference data Luma L1" hexmask.long.word 0x04 16.--31. 1. "BASE_YREF_BOT_L1_ADD,Base address of reference data Y L1 bottom (BASE_YREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x04 0.--15. 1. "BASE_YREF_TOP_L1_ADD,Base address of reference data Y L1 top (BASE_YREF_TOP_L1_ADD) (Reference for progressive/top field)" line.long 0x08 "MC_ADDR_2,Base address of reference data chroma L0" hexmask.long.word 0x08 16.--31. 1. "BASE_CREF_BOT_L0_ADD,Base address of reference data C L0 bottom (BASE_CREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x08 0.--15. 1. "BASE_CREF_TOP_L0_ADD,Base address of reference data C L0 top (BASE_CREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x0C "MC_ADDR_3," hexmask.long.word 0x0C 16.--31. 1. "BASE_CREF_BOT_L1_ADD,Base address of reference data C L1 bottom (BASE_CREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x0C 0.--15. 1. "BASE_CREF_TOP_L1_ADD,Base address of reference data C L1 top (BASE_CREF_TOP_L1_ADD) (Reference for progressive/top field)" width 0x0B tree.end endif tree "MC3_MMR_L3_MAINInterconnect" base ad:0x5A059000 rgroup.long 0x00++0x0F line.long 0x00 "MC_PID,PID register" line.long 0x04 "MC_CNT,Benchmark counter register" bitfld.long 0x04 31. "MC_CNT_EN,Counter enable (MC_CNT_EN)" "The benchmark counter is disabled,The benchmark counter is enabled" bitfld.long 0x04 30. "MC_CNT_RST,Counter reset (MC_CNT_RST) Writing 0 results in no effect" "MC_CNT_RST_0,MC_CNT_RST_1" hexmask.long.word 0x04 0.--15. 1. "MC_COUNT,Counter value (MC_COUNT)" line.long 0x08 "MC_CTRL,Control register" bitfld.long 0x08 2. "MC_DBG,H.264 MBAFF debug mode bit (MC_DBG)" "Normal mode,Debug mode(1MB prediction/step)" bitfld.long 0x08 0. "MC_EN,Module start and status (MC_EN)" "Idle,Busy" line.long 0x0C "MC_PARAM0,Motion compression parameter register" bitfld.long 0x0C 29. "VC1_SMP_MOD,VC-1 sample mode" "Bilinear Interpolation,Bicubic Interpolation" bitfld.long 0x0C 28. "VC1_RND_CTRL,VC-1 round control bit" "VC1_RND_CTRL_0,VC1_RND_CTRL_1" bitfld.long 0x0C 10.--11. "H264_WGT_BIPRD_IDC,H.264 weighted_bipred_idc" "H264_WGT_BIPRD_IDC_0,H264_WGT_BIPRD_IDC_1,H264_WGT_BIPRD_IDC_2,H264_WGT_BIPRD_IDC_3" newline bitfld.long 0x0C 9. "H264_WGT_PRD,H.264 weighted_pred_flag" "H264_WGT_PRD_0,H264_WGT_PRD_1" bitfld.long 0x0C 0.--3. "CODEC_TYPE,Codec_type select" "H.264,?,VC-1,?,MPEG-4,MPEG-2,AVS-1.0,?,RealVideo-8/9/10,On2 VP6,On2 VP7,?..." hgroup.long 0x10++0x03 hide.long 0x00 "MC_PARAM1,Motion compression parameter register" group.long 0x18++0x0F line.long 0x00 "MC_ADDR_0,Base address of reference data Luma L0" hexmask.long.word 0x00 16.--31. 1. "BASE_YREF_BOT_L0_ADD,Base address of reference data Y L0 bottom (BASE_YREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x00 0.--15. 1. "BASE_YREF_TOP_L0_ADD,Base address of reference data Y L0 top (BASE_YREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x04 "MC_ADDR_1,Base address of reference data Luma L1" hexmask.long.word 0x04 16.--31. 1. "BASE_YREF_BOT_L1_ADD,Base address of reference data Y L1 bottom (BASE_YREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x04 0.--15. 1. "BASE_YREF_TOP_L1_ADD,Base address of reference data Y L1 top (BASE_YREF_TOP_L1_ADD) (Reference for progressive/top field)" line.long 0x08 "MC_ADDR_2,Base address of reference data chroma L0" hexmask.long.word 0x08 16.--31. 1. "BASE_CREF_BOT_L0_ADD,Base address of reference data C L0 bottom (BASE_CREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x08 0.--15. 1. "BASE_CREF_TOP_L0_ADD,Base address of reference data C L0 top (BASE_CREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x0C "MC_ADDR_3," hexmask.long.word 0x0C 16.--31. 1. "BASE_CREF_BOT_L1_ADD,Base address of reference data C L1 bottom (BASE_CREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x0C 0.--15. 1. "BASE_CREF_TOP_L1_ADD,Base address of reference data C L1 top (BASE_CREF_TOP_L1_ADD) (Reference for progressive/top field)" width 0x0B tree.end tree.end tree "IVA_Motion_Estimation" tree "IME3_ICONT" base ad:0xD4000 tree "Channel_0" group.long 0x300++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x380++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x304++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x384++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x100++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_0,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x200++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x40++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_0,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_0,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2000++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_0,Program Memory 32-bit word" tree.end tree "Channel_1" group.long 0x308++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x388++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_1,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x30C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x38C++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x104++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_1,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x208++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_1,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_1,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x44++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_1,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_1,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2004++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_1,Program Memory 32-bit word" tree.end tree "Channel_10" group.long 0x350++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3D0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x354++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3D4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x128++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_10,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x250++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_10,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2028++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_10,Program Memory 32-bit word" tree.end tree "Channel_11" group.long 0x358++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3D8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_11,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x35C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3DC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x12C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_11,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x258++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_11,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_11,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xAC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_11,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x202C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_11,Program Memory 32-bit word" tree.end tree "Channel_12" group.long 0x360++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3E0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_12,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x364++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3E4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x130++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_12,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x260++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_12,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_12,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_12,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2030++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_12,Program Memory 32-bit word" tree.end tree "Channel_13" group.long 0x368++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3E8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_13,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x36C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3EC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x134++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_13,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x268++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_13,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_13,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_13,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2034++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_13,Program Memory 32-bit word" tree.end tree "Channel_14" group.long 0x370++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3F0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_14,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x374++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3F4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x138++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_14,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x270++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_14,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_14,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_14,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2038++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_14,Program Memory 32-bit word" tree.end tree "Channel_15" group.long 0x378++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3F8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_15,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x37C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3FC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x13C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_15,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x278++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_15,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_15,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xBC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_15,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x203C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_15,Program Memory 32-bit word" tree.end tree "Channel_16" group.long 0x140++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_16,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x280++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_16,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2040++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_16,Program Memory 32-bit word" tree.end tree "Channel_17" group.long 0x144++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_17,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x288++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_17,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_17,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_17,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2044++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_17,Program Memory 32-bit word" tree.end tree "Channel_18" group.long 0x148++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_18,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x290++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_18,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_18,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_18,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2048++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_18,Program Memory 32-bit word" tree.end tree "Channel_19" group.long 0x14C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_19,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x298++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_19,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_19,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xCC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_19,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x204C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_19,Program Memory 32-bit word" tree.end tree "Channel_2" group.long 0x310++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x390++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_2,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x314++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x394++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x108++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_2,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x210++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_2,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_2,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x48++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_2,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_2,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2008++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_2,Program Memory 32-bit word" tree.end tree "Channel_20" group.long 0x150++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_20,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2A0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_20,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_20,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_20,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2050++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_20,Program Memory 32-bit word" tree.end tree "Channel_21" group.long 0x154++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_21,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2A8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_21,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_21,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_21,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2054++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_21,Program Memory 32-bit word" tree.end tree "Channel_22" group.long 0x158++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_22,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2B0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_22,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_22,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_22,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2058++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_22,Program Memory 32-bit word" tree.end tree "Channel_23" group.long 0x15C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_23,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2B8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_23,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_23,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xDC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_23,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x205C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_23,Program Memory 32-bit word" tree.end tree "Channel_24" group.long 0x160++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_24,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2C0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_24,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_24,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_24,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2060++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_24,Program Memory 32-bit word" tree.end tree "Channel_25" group.long 0x164++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_25,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2C8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_25,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_25,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_25,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2064++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_25,Program Memory 32-bit word" tree.end tree "Channel_26" group.long 0x168++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_26,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2D0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_26,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_26,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_26,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2068++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_26,Program Memory 32-bit word" tree.end tree "Channel_27" group.long 0x16C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_27,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2D8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_27,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_27,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xEC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_27,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x206C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_27,Program Memory 32-bit word" tree.end tree "Channel_28" group.long 0x170++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_28,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2E0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_28,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_28,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_28,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2070++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_28,Program Memory 32-bit word" tree.end tree "Channel_29" group.long 0x174++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_29,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2E8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_29,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_29,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_29,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2074++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_29,Program Memory 32-bit word" tree.end tree "Channel_3" group.long 0x318++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x398++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_3,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x31C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x39C++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x10C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_3,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x218++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_3,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_3,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x4C++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_3,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_3,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x200C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_3,Program Memory 32-bit word" tree.end tree "Channel_30" group.long 0x178++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_30,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2F0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_30,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_30,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_30,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2078++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_30,Program Memory 32-bit word" tree.end tree "Channel_31" group.long 0x17C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_31,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2F8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_31,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_31,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xFC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_31,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x207C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_31,Program Memory 32-bit word" tree.end tree "Channel_32" group.long 0x180++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_32,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2080++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_32,Program Memory 32-bit word" tree.end tree "Channel_33" group.long 0x184++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_33,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2084++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_33,Program Memory 32-bit word" tree.end tree "Channel_34" group.long 0x188++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_34,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2088++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_34,Program Memory 32-bit word" tree.end tree "Channel_35" group.long 0x18C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_35,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x208C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_35,Program Memory 32-bit word" tree.end tree "Channel_36" group.long 0x190++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_36,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2090++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_36,Program Memory 32-bit word" tree.end tree "Channel_37" group.long 0x194++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_37,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2094++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_37,Program Memory 32-bit word" tree.end tree "Channel_38" group.long 0x198++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_38,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2098++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_38,Program Memory 32-bit word" tree.end tree "Channel_39" group.long 0x19C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_39,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x209C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_39,Program Memory 32-bit word" tree.end tree "Channel_4" group.long 0x320++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3A0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_4,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x324++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3A4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x110++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_4,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x220++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_4,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_4,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x90++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_4,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2010++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_4,Program Memory 32-bit word" tree.end tree "Channel_40" group.long 0x1A0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_40,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_40,Program Memory 32-bit word" tree.end tree "Channel_41" group.long 0x1A4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_41,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_41,Program Memory 32-bit word" tree.end tree "Channel_42" group.long 0x1A8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_42,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_42,Program Memory 32-bit word" tree.end tree "Channel_43" group.long 0x1AC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_43,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20AC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_43,Program Memory 32-bit word" tree.end tree "Channel_44" group.long 0x1B0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_44,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_44,Program Memory 32-bit word" tree.end tree "Channel_45" group.long 0x1B4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_45,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_45,Program Memory 32-bit word" tree.end tree "Channel_46" group.long 0x1B8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_46,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_46,Program Memory 32-bit word" tree.end tree "Channel_47" group.long 0x1BC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_47,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20BC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_47,Program Memory 32-bit word" tree.end tree "Channel_48" group.long 0x1C0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_48,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_48,Program Memory 32-bit word" tree.end tree "Channel_49" group.long 0x1C4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_49,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_49,Program Memory 32-bit word" tree.end tree "Channel_5" group.long 0x328++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3A8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_5,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x32C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3AC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x114++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_5,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x228++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_5,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_5,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x94++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_5,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2014++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_5,Program Memory 32-bit word" tree.end tree "Channel_50" group.long 0x1C8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_50,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_50,Program Memory 32-bit word" tree.end tree "Channel_51" group.long 0x1CC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_51,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20CC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_51,Program Memory 32-bit word" tree.end tree "Channel_52" group.long 0x1D0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_52,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_52,Program Memory 32-bit word" tree.end tree "Channel_53" group.long 0x1D4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_53,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_53,Program Memory 32-bit word" tree.end tree "Channel_54" group.long 0x1D8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_54,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_54,Program Memory 32-bit word" tree.end tree "Channel_55" group.long 0x1DC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_55,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20DC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_55,Program Memory 32-bit word" tree.end tree "Channel_56" group.long 0x1E0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_56,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_56,Program Memory 32-bit word" tree.end tree "Channel_57" group.long 0x1E4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_57,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_57,Program Memory 32-bit word" tree.end tree "Channel_58" group.long 0x1E8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_58,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_58,Program Memory 32-bit word" tree.end tree "Channel_59" group.long 0x1EC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_59,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20EC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_59,Program Memory 32-bit word" tree.end tree "Channel_6" group.long 0x330++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3B0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_6,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x334++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3B4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x118++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_6,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x230++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_6,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_6,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x98++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_6,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2018++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_6,Program Memory 32-bit word" tree.end tree "Channel_60" group.long 0x1F0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_60,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_60,Program Memory 32-bit word" tree.end tree "Channel_61" group.long 0x1F4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_61,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_61,Program Memory 32-bit word" tree.end tree "Channel_62" group.long 0x1F8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_62,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_62,Program Memory 32-bit word" tree.end tree "Channel_63" group.long 0x1FC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_63,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20FC++0xFFF line.long 0x00 "IME3_PROGRAMBUFFER_m_63,Program Memory 32-bit word" line.long 0x04 "IME3_PROGRAMBUFFER_m_64,Program Memory 32-bit word" line.long 0x08 "IME3_PROGRAMBUFFER_m_65,Program Memory 32-bit word" line.long 0x0C "IME3_PROGRAMBUFFER_m_66,Program Memory 32-bit word" line.long 0x10 "IME3_PROGRAMBUFFER_m_67,Program Memory 32-bit word" line.long 0x14 "IME3_PROGRAMBUFFER_m_68,Program Memory 32-bit word" line.long 0x18 "IME3_PROGRAMBUFFER_m_69,Program Memory 32-bit word" line.long 0x1C "IME3_PROGRAMBUFFER_m_70,Program Memory 32-bit word" line.long 0x20 "IME3_PROGRAMBUFFER_m_71,Program Memory 32-bit word" line.long 0x24 "IME3_PROGRAMBUFFER_m_72,Program Memory 32-bit word" line.long 0x28 "IME3_PROGRAMBUFFER_m_73,Program Memory 32-bit word" line.long 0x2C "IME3_PROGRAMBUFFER_m_74,Program Memory 32-bit word" line.long 0x30 "IME3_PROGRAMBUFFER_m_75,Program Memory 32-bit word" line.long 0x34 "IME3_PROGRAMBUFFER_m_76,Program Memory 32-bit word" line.long 0x38 "IME3_PROGRAMBUFFER_m_77,Program Memory 32-bit word" line.long 0x3C "IME3_PROGRAMBUFFER_m_78,Program Memory 32-bit word" line.long 0x40 "IME3_PROGRAMBUFFER_m_79,Program Memory 32-bit word" line.long 0x44 "IME3_PROGRAMBUFFER_m_80,Program Memory 32-bit word" line.long 0x48 "IME3_PROGRAMBUFFER_m_81,Program Memory 32-bit word" line.long 0x4C "IME3_PROGRAMBUFFER_m_82,Program Memory 32-bit word" line.long 0x50 "IME3_PROGRAMBUFFER_m_83,Program Memory 32-bit word" line.long 0x54 "IME3_PROGRAMBUFFER_m_84,Program Memory 32-bit word" line.long 0x58 "IME3_PROGRAMBUFFER_m_85,Program Memory 32-bit word" line.long 0x5C "IME3_PROGRAMBUFFER_m_86,Program Memory 32-bit word" line.long 0x60 "IME3_PROGRAMBUFFER_m_87,Program Memory 32-bit word" line.long 0x64 "IME3_PROGRAMBUFFER_m_88,Program Memory 32-bit word" line.long 0x68 "IME3_PROGRAMBUFFER_m_89,Program Memory 32-bit word" line.long 0x6C "IME3_PROGRAMBUFFER_m_90,Program Memory 32-bit word" line.long 0x70 "IME3_PROGRAMBUFFER_m_91,Program Memory 32-bit word" line.long 0x74 "IME3_PROGRAMBUFFER_m_92,Program Memory 32-bit word" line.long 0x78 "IME3_PROGRAMBUFFER_m_93,Program Memory 32-bit word" line.long 0x7C "IME3_PROGRAMBUFFER_m_94,Program Memory 32-bit word" line.long 0x80 "IME3_PROGRAMBUFFER_m_95,Program Memory 32-bit word" line.long 0x84 "IME3_PROGRAMBUFFER_m_96,Program Memory 32-bit word" line.long 0x88 "IME3_PROGRAMBUFFER_m_97,Program Memory 32-bit word" line.long 0x8C "IME3_PROGRAMBUFFER_m_98,Program Memory 32-bit word" line.long 0x90 "IME3_PROGRAMBUFFER_m_99,Program Memory 32-bit word" line.long 0x94 "IME3_PROGRAMBUFFER_m_100,Program Memory 32-bit word" line.long 0x98 "IME3_PROGRAMBUFFER_m_101,Program Memory 32-bit word" line.long 0x9C "IME3_PROGRAMBUFFER_m_102,Program Memory 32-bit word" line.long 0xA0 "IME3_PROGRAMBUFFER_m_103,Program Memory 32-bit word" line.long 0xA4 "IME3_PROGRAMBUFFER_m_104,Program Memory 32-bit word" line.long 0xA8 "IME3_PROGRAMBUFFER_m_105,Program Memory 32-bit word" line.long 0xAC "IME3_PROGRAMBUFFER_m_106,Program Memory 32-bit word" line.long 0xB0 "IME3_PROGRAMBUFFER_m_107,Program Memory 32-bit word" line.long 0xB4 "IME3_PROGRAMBUFFER_m_108,Program Memory 32-bit word" line.long 0xB8 "IME3_PROGRAMBUFFER_m_109,Program Memory 32-bit word" line.long 0xBC "IME3_PROGRAMBUFFER_m_110,Program Memory 32-bit word" line.long 0xC0 "IME3_PROGRAMBUFFER_m_111,Program Memory 32-bit word" line.long 0xC4 "IME3_PROGRAMBUFFER_m_112,Program Memory 32-bit word" line.long 0xC8 "IME3_PROGRAMBUFFER_m_113,Program Memory 32-bit word" line.long 0xCC "IME3_PROGRAMBUFFER_m_114,Program Memory 32-bit word" line.long 0xD0 "IME3_PROGRAMBUFFER_m_115,Program Memory 32-bit word" line.long 0xD4 "IME3_PROGRAMBUFFER_m_116,Program Memory 32-bit word" line.long 0xD8 "IME3_PROGRAMBUFFER_m_117,Program Memory 32-bit word" line.long 0xDC "IME3_PROGRAMBUFFER_m_118,Program Memory 32-bit word" line.long 0xE0 "IME3_PROGRAMBUFFER_m_119,Program Memory 32-bit word" line.long 0xE4 "IME3_PROGRAMBUFFER_m_120,Program Memory 32-bit word" line.long 0xE8 "IME3_PROGRAMBUFFER_m_121,Program Memory 32-bit word" line.long 0xEC "IME3_PROGRAMBUFFER_m_122,Program Memory 32-bit word" line.long 0xF0 "IME3_PROGRAMBUFFER_m_123,Program Memory 32-bit word" line.long 0xF4 "IME3_PROGRAMBUFFER_m_124,Program Memory 32-bit word" line.long 0xF8 "IME3_PROGRAMBUFFER_m_125,Program Memory 32-bit word" line.long 0xFC "IME3_PROGRAMBUFFER_m_126,Program Memory 32-bit word" line.long 0x100 "IME3_PROGRAMBUFFER_m_127,Program Memory 32-bit word" line.long 0x104 "IME3_PROGRAMBUFFER_m_128,Program Memory 32-bit word" line.long 0x108 "IME3_PROGRAMBUFFER_m_129,Program Memory 32-bit word" line.long 0x10C "IME3_PROGRAMBUFFER_m_130,Program Memory 32-bit word" line.long 0x110 "IME3_PROGRAMBUFFER_m_131,Program Memory 32-bit word" line.long 0x114 "IME3_PROGRAMBUFFER_m_132,Program Memory 32-bit word" line.long 0x118 "IME3_PROGRAMBUFFER_m_133,Program Memory 32-bit word" line.long 0x11C "IME3_PROGRAMBUFFER_m_134,Program Memory 32-bit word" line.long 0x120 "IME3_PROGRAMBUFFER_m_135,Program Memory 32-bit word" line.long 0x124 "IME3_PROGRAMBUFFER_m_136,Program Memory 32-bit word" line.long 0x128 "IME3_PROGRAMBUFFER_m_137,Program Memory 32-bit word" line.long 0x12C "IME3_PROGRAMBUFFER_m_138,Program Memory 32-bit word" line.long 0x130 "IME3_PROGRAMBUFFER_m_139,Program Memory 32-bit word" line.long 0x134 "IME3_PROGRAMBUFFER_m_140,Program Memory 32-bit word" line.long 0x138 "IME3_PROGRAMBUFFER_m_141,Program Memory 32-bit word" line.long 0x13C "IME3_PROGRAMBUFFER_m_142,Program Memory 32-bit word" line.long 0x140 "IME3_PROGRAMBUFFER_m_143,Program Memory 32-bit word" line.long 0x144 "IME3_PROGRAMBUFFER_m_144,Program Memory 32-bit word" line.long 0x148 "IME3_PROGRAMBUFFER_m_145,Program Memory 32-bit word" line.long 0x14C "IME3_PROGRAMBUFFER_m_146,Program Memory 32-bit word" line.long 0x150 "IME3_PROGRAMBUFFER_m_147,Program Memory 32-bit word" line.long 0x154 "IME3_PROGRAMBUFFER_m_148,Program Memory 32-bit word" line.long 0x158 "IME3_PROGRAMBUFFER_m_149,Program Memory 32-bit word" line.long 0x15C "IME3_PROGRAMBUFFER_m_150,Program Memory 32-bit word" line.long 0x160 "IME3_PROGRAMBUFFER_m_151,Program Memory 32-bit word" line.long 0x164 "IME3_PROGRAMBUFFER_m_152,Program Memory 32-bit word" line.long 0x168 "IME3_PROGRAMBUFFER_m_153,Program Memory 32-bit word" line.long 0x16C "IME3_PROGRAMBUFFER_m_154,Program Memory 32-bit word" line.long 0x170 "IME3_PROGRAMBUFFER_m_155,Program Memory 32-bit word" line.long 0x174 "IME3_PROGRAMBUFFER_m_156,Program Memory 32-bit word" line.long 0x178 "IME3_PROGRAMBUFFER_m_157,Program Memory 32-bit word" line.long 0x17C "IME3_PROGRAMBUFFER_m_158,Program Memory 32-bit word" line.long 0x180 "IME3_PROGRAMBUFFER_m_159,Program Memory 32-bit word" line.long 0x184 "IME3_PROGRAMBUFFER_m_160,Program Memory 32-bit word" line.long 0x188 "IME3_PROGRAMBUFFER_m_161,Program Memory 32-bit word" line.long 0x18C "IME3_PROGRAMBUFFER_m_162,Program Memory 32-bit word" line.long 0x190 "IME3_PROGRAMBUFFER_m_163,Program Memory 32-bit word" line.long 0x194 "IME3_PROGRAMBUFFER_m_164,Program Memory 32-bit word" line.long 0x198 "IME3_PROGRAMBUFFER_m_165,Program Memory 32-bit word" line.long 0x19C "IME3_PROGRAMBUFFER_m_166,Program Memory 32-bit word" line.long 0x1A0 "IME3_PROGRAMBUFFER_m_167,Program Memory 32-bit word" line.long 0x1A4 "IME3_PROGRAMBUFFER_m_168,Program Memory 32-bit word" line.long 0x1A8 "IME3_PROGRAMBUFFER_m_169,Program Memory 32-bit word" line.long 0x1AC "IME3_PROGRAMBUFFER_m_170,Program Memory 32-bit word" line.long 0x1B0 "IME3_PROGRAMBUFFER_m_171,Program Memory 32-bit word" line.long 0x1B4 "IME3_PROGRAMBUFFER_m_172,Program Memory 32-bit word" line.long 0x1B8 "IME3_PROGRAMBUFFER_m_173,Program Memory 32-bit word" line.long 0x1BC "IME3_PROGRAMBUFFER_m_174,Program Memory 32-bit word" line.long 0x1C0 "IME3_PROGRAMBUFFER_m_175,Program Memory 32-bit word" line.long 0x1C4 "IME3_PROGRAMBUFFER_m_176,Program Memory 32-bit word" line.long 0x1C8 "IME3_PROGRAMBUFFER_m_177,Program Memory 32-bit word" line.long 0x1CC "IME3_PROGRAMBUFFER_m_178,Program Memory 32-bit word" line.long 0x1D0 "IME3_PROGRAMBUFFER_m_179,Program Memory 32-bit word" line.long 0x1D4 "IME3_PROGRAMBUFFER_m_180,Program Memory 32-bit word" line.long 0x1D8 "IME3_PROGRAMBUFFER_m_181,Program Memory 32-bit word" line.long 0x1DC "IME3_PROGRAMBUFFER_m_182,Program Memory 32-bit word" line.long 0x1E0 "IME3_PROGRAMBUFFER_m_183,Program Memory 32-bit word" line.long 0x1E4 "IME3_PROGRAMBUFFER_m_184,Program Memory 32-bit word" line.long 0x1E8 "IME3_PROGRAMBUFFER_m_185,Program Memory 32-bit word" line.long 0x1EC "IME3_PROGRAMBUFFER_m_186,Program Memory 32-bit word" line.long 0x1F0 "IME3_PROGRAMBUFFER_m_187,Program Memory 32-bit word" line.long 0x1F4 "IME3_PROGRAMBUFFER_m_188,Program Memory 32-bit word" line.long 0x1F8 "IME3_PROGRAMBUFFER_m_189,Program Memory 32-bit word" line.long 0x1FC "IME3_PROGRAMBUFFER_m_190,Program Memory 32-bit word" line.long 0x200 "IME3_PROGRAMBUFFER_m_191,Program Memory 32-bit word" line.long 0x204 "IME3_PROGRAMBUFFER_m_192,Program Memory 32-bit word" line.long 0x208 "IME3_PROGRAMBUFFER_m_193,Program Memory 32-bit word" line.long 0x20C "IME3_PROGRAMBUFFER_m_194,Program Memory 32-bit word" line.long 0x210 "IME3_PROGRAMBUFFER_m_195,Program Memory 32-bit word" line.long 0x214 "IME3_PROGRAMBUFFER_m_196,Program Memory 32-bit word" line.long 0x218 "IME3_PROGRAMBUFFER_m_197,Program Memory 32-bit word" line.long 0x21C "IME3_PROGRAMBUFFER_m_198,Program Memory 32-bit word" line.long 0x220 "IME3_PROGRAMBUFFER_m_199,Program Memory 32-bit word" line.long 0x224 "IME3_PROGRAMBUFFER_m_200,Program Memory 32-bit word" line.long 0x228 "IME3_PROGRAMBUFFER_m_201,Program Memory 32-bit word" line.long 0x22C "IME3_PROGRAMBUFFER_m_202,Program Memory 32-bit word" line.long 0x230 "IME3_PROGRAMBUFFER_m_203,Program Memory 32-bit word" line.long 0x234 "IME3_PROGRAMBUFFER_m_204,Program Memory 32-bit word" line.long 0x238 "IME3_PROGRAMBUFFER_m_205,Program Memory 32-bit word" line.long 0x23C "IME3_PROGRAMBUFFER_m_206,Program Memory 32-bit word" line.long 0x240 "IME3_PROGRAMBUFFER_m_207,Program Memory 32-bit word" line.long 0x244 "IME3_PROGRAMBUFFER_m_208,Program Memory 32-bit word" line.long 0x248 "IME3_PROGRAMBUFFER_m_209,Program Memory 32-bit word" line.long 0x24C "IME3_PROGRAMBUFFER_m_210,Program Memory 32-bit word" line.long 0x250 "IME3_PROGRAMBUFFER_m_211,Program Memory 32-bit word" line.long 0x254 "IME3_PROGRAMBUFFER_m_212,Program Memory 32-bit word" line.long 0x258 "IME3_PROGRAMBUFFER_m_213,Program Memory 32-bit word" line.long 0x25C "IME3_PROGRAMBUFFER_m_214,Program Memory 32-bit word" line.long 0x260 "IME3_PROGRAMBUFFER_m_215,Program Memory 32-bit word" line.long 0x264 "IME3_PROGRAMBUFFER_m_216,Program Memory 32-bit word" line.long 0x268 "IME3_PROGRAMBUFFER_m_217,Program Memory 32-bit word" line.long 0x26C "IME3_PROGRAMBUFFER_m_218,Program Memory 32-bit word" line.long 0x270 "IME3_PROGRAMBUFFER_m_219,Program Memory 32-bit word" line.long 0x274 "IME3_PROGRAMBUFFER_m_220,Program Memory 32-bit word" line.long 0x278 "IME3_PROGRAMBUFFER_m_221,Program Memory 32-bit word" line.long 0x27C "IME3_PROGRAMBUFFER_m_222,Program Memory 32-bit word" line.long 0x280 "IME3_PROGRAMBUFFER_m_223,Program Memory 32-bit word" line.long 0x284 "IME3_PROGRAMBUFFER_m_224,Program Memory 32-bit word" line.long 0x288 "IME3_PROGRAMBUFFER_m_225,Program Memory 32-bit word" line.long 0x28C "IME3_PROGRAMBUFFER_m_226,Program Memory 32-bit word" line.long 0x290 "IME3_PROGRAMBUFFER_m_227,Program Memory 32-bit word" line.long 0x294 "IME3_PROGRAMBUFFER_m_228,Program Memory 32-bit word" line.long 0x298 "IME3_PROGRAMBUFFER_m_229,Program Memory 32-bit word" line.long 0x29C "IME3_PROGRAMBUFFER_m_230,Program Memory 32-bit word" line.long 0x2A0 "IME3_PROGRAMBUFFER_m_231,Program Memory 32-bit word" line.long 0x2A4 "IME3_PROGRAMBUFFER_m_232,Program Memory 32-bit word" line.long 0x2A8 "IME3_PROGRAMBUFFER_m_233,Program Memory 32-bit word" line.long 0x2AC "IME3_PROGRAMBUFFER_m_234,Program Memory 32-bit word" line.long 0x2B0 "IME3_PROGRAMBUFFER_m_235,Program Memory 32-bit word" line.long 0x2B4 "IME3_PROGRAMBUFFER_m_236,Program Memory 32-bit word" line.long 0x2B8 "IME3_PROGRAMBUFFER_m_237,Program Memory 32-bit word" line.long 0x2BC "IME3_PROGRAMBUFFER_m_238,Program Memory 32-bit word" line.long 0x2C0 "IME3_PROGRAMBUFFER_m_239,Program Memory 32-bit word" line.long 0x2C4 "IME3_PROGRAMBUFFER_m_240,Program Memory 32-bit word" line.long 0x2C8 "IME3_PROGRAMBUFFER_m_241,Program Memory 32-bit word" line.long 0x2CC "IME3_PROGRAMBUFFER_m_242,Program Memory 32-bit word" line.long 0x2D0 "IME3_PROGRAMBUFFER_m_243,Program Memory 32-bit word" line.long 0x2D4 "IME3_PROGRAMBUFFER_m_244,Program Memory 32-bit word" line.long 0x2D8 "IME3_PROGRAMBUFFER_m_245,Program Memory 32-bit word" line.long 0x2DC "IME3_PROGRAMBUFFER_m_246,Program Memory 32-bit word" line.long 0x2E0 "IME3_PROGRAMBUFFER_m_247,Program Memory 32-bit word" line.long 0x2E4 "IME3_PROGRAMBUFFER_m_248,Program Memory 32-bit word" line.long 0x2E8 "IME3_PROGRAMBUFFER_m_249,Program Memory 32-bit word" line.long 0x2EC "IME3_PROGRAMBUFFER_m_250,Program Memory 32-bit word" line.long 0x2F0 "IME3_PROGRAMBUFFER_m_251,Program Memory 32-bit word" line.long 0x2F4 "IME3_PROGRAMBUFFER_m_252,Program Memory 32-bit word" line.long 0x2F8 "IME3_PROGRAMBUFFER_m_253,Program Memory 32-bit word" line.long 0x2FC "IME3_PROGRAMBUFFER_m_254,Program Memory 32-bit word" line.long 0x300 "IME3_PROGRAMBUFFER_m_255,Program Memory 32-bit word" line.long 0x304 "IME3_PROGRAMBUFFER_m_256,Program Memory 32-bit word" line.long 0x308 "IME3_PROGRAMBUFFER_m_257,Program Memory 32-bit word" line.long 0x30C "IME3_PROGRAMBUFFER_m_258,Program Memory 32-bit word" line.long 0x310 "IME3_PROGRAMBUFFER_m_259,Program Memory 32-bit word" line.long 0x314 "IME3_PROGRAMBUFFER_m_260,Program Memory 32-bit word" line.long 0x318 "IME3_PROGRAMBUFFER_m_261,Program Memory 32-bit word" line.long 0x31C "IME3_PROGRAMBUFFER_m_262,Program Memory 32-bit word" line.long 0x320 "IME3_PROGRAMBUFFER_m_263,Program Memory 32-bit word" line.long 0x324 "IME3_PROGRAMBUFFER_m_264,Program Memory 32-bit word" line.long 0x328 "IME3_PROGRAMBUFFER_m_265,Program Memory 32-bit word" line.long 0x32C "IME3_PROGRAMBUFFER_m_266,Program Memory 32-bit word" line.long 0x330 "IME3_PROGRAMBUFFER_m_267,Program Memory 32-bit word" line.long 0x334 "IME3_PROGRAMBUFFER_m_268,Program Memory 32-bit word" line.long 0x338 "IME3_PROGRAMBUFFER_m_269,Program Memory 32-bit word" line.long 0x33C "IME3_PROGRAMBUFFER_m_270,Program Memory 32-bit word" line.long 0x340 "IME3_PROGRAMBUFFER_m_271,Program Memory 32-bit word" line.long 0x344 "IME3_PROGRAMBUFFER_m_272,Program Memory 32-bit word" line.long 0x348 "IME3_PROGRAMBUFFER_m_273,Program Memory 32-bit word" line.long 0x34C "IME3_PROGRAMBUFFER_m_274,Program Memory 32-bit word" line.long 0x350 "IME3_PROGRAMBUFFER_m_275,Program Memory 32-bit word" line.long 0x354 "IME3_PROGRAMBUFFER_m_276,Program Memory 32-bit word" line.long 0x358 "IME3_PROGRAMBUFFER_m_277,Program Memory 32-bit word" line.long 0x35C "IME3_PROGRAMBUFFER_m_278,Program Memory 32-bit word" line.long 0x360 "IME3_PROGRAMBUFFER_m_279,Program Memory 32-bit word" line.long 0x364 "IME3_PROGRAMBUFFER_m_280,Program Memory 32-bit word" line.long 0x368 "IME3_PROGRAMBUFFER_m_281,Program Memory 32-bit word" line.long 0x36C "IME3_PROGRAMBUFFER_m_282,Program Memory 32-bit word" line.long 0x370 "IME3_PROGRAMBUFFER_m_283,Program Memory 32-bit word" line.long 0x374 "IME3_PROGRAMBUFFER_m_284,Program Memory 32-bit word" line.long 0x378 "IME3_PROGRAMBUFFER_m_285,Program Memory 32-bit word" line.long 0x37C "IME3_PROGRAMBUFFER_m_286,Program Memory 32-bit word" line.long 0x380 "IME3_PROGRAMBUFFER_m_287,Program Memory 32-bit word" line.long 0x384 "IME3_PROGRAMBUFFER_m_288,Program Memory 32-bit word" line.long 0x388 "IME3_PROGRAMBUFFER_m_289,Program Memory 32-bit word" line.long 0x38C "IME3_PROGRAMBUFFER_m_290,Program Memory 32-bit word" line.long 0x390 "IME3_PROGRAMBUFFER_m_291,Program Memory 32-bit word" line.long 0x394 "IME3_PROGRAMBUFFER_m_292,Program Memory 32-bit word" line.long 0x398 "IME3_PROGRAMBUFFER_m_293,Program Memory 32-bit word" line.long 0x39C "IME3_PROGRAMBUFFER_m_294,Program Memory 32-bit word" line.long 0x3A0 "IME3_PROGRAMBUFFER_m_295,Program Memory 32-bit word" line.long 0x3A4 "IME3_PROGRAMBUFFER_m_296,Program Memory 32-bit word" line.long 0x3A8 "IME3_PROGRAMBUFFER_m_297,Program Memory 32-bit word" line.long 0x3AC "IME3_PROGRAMBUFFER_m_298,Program Memory 32-bit word" line.long 0x3B0 "IME3_PROGRAMBUFFER_m_299,Program Memory 32-bit word" line.long 0x3B4 "IME3_PROGRAMBUFFER_m_300,Program Memory 32-bit word" line.long 0x3B8 "IME3_PROGRAMBUFFER_m_301,Program Memory 32-bit word" line.long 0x3BC "IME3_PROGRAMBUFFER_m_302,Program Memory 32-bit word" line.long 0x3C0 "IME3_PROGRAMBUFFER_m_303,Program Memory 32-bit word" line.long 0x3C4 "IME3_PROGRAMBUFFER_m_304,Program Memory 32-bit word" line.long 0x3C8 "IME3_PROGRAMBUFFER_m_305,Program Memory 32-bit word" line.long 0x3CC "IME3_PROGRAMBUFFER_m_306,Program Memory 32-bit word" line.long 0x3D0 "IME3_PROGRAMBUFFER_m_307,Program Memory 32-bit word" line.long 0x3D4 "IME3_PROGRAMBUFFER_m_308,Program Memory 32-bit word" line.long 0x3D8 "IME3_PROGRAMBUFFER_m_309,Program Memory 32-bit word" line.long 0x3DC "IME3_PROGRAMBUFFER_m_310,Program Memory 32-bit word" line.long 0x3E0 "IME3_PROGRAMBUFFER_m_311,Program Memory 32-bit word" line.long 0x3E4 "IME3_PROGRAMBUFFER_m_312,Program Memory 32-bit word" line.long 0x3E8 "IME3_PROGRAMBUFFER_m_313,Program Memory 32-bit word" line.long 0x3EC "IME3_PROGRAMBUFFER_m_314,Program Memory 32-bit word" line.long 0x3F0 "IME3_PROGRAMBUFFER_m_315,Program Memory 32-bit word" line.long 0x3F4 "IME3_PROGRAMBUFFER_m_316,Program Memory 32-bit word" line.long 0x3F8 "IME3_PROGRAMBUFFER_m_317,Program Memory 32-bit word" line.long 0x3FC "IME3_PROGRAMBUFFER_m_318,Program Memory 32-bit word" line.long 0x400 "IME3_PROGRAMBUFFER_m_319,Program Memory 32-bit word" line.long 0x404 "IME3_PROGRAMBUFFER_m_320,Program Memory 32-bit word" line.long 0x408 "IME3_PROGRAMBUFFER_m_321,Program Memory 32-bit word" line.long 0x40C "IME3_PROGRAMBUFFER_m_322,Program Memory 32-bit word" line.long 0x410 "IME3_PROGRAMBUFFER_m_323,Program Memory 32-bit word" line.long 0x414 "IME3_PROGRAMBUFFER_m_324,Program Memory 32-bit word" line.long 0x418 "IME3_PROGRAMBUFFER_m_325,Program Memory 32-bit word" line.long 0x41C "IME3_PROGRAMBUFFER_m_326,Program Memory 32-bit word" line.long 0x420 "IME3_PROGRAMBUFFER_m_327,Program Memory 32-bit word" line.long 0x424 "IME3_PROGRAMBUFFER_m_328,Program Memory 32-bit word" line.long 0x428 "IME3_PROGRAMBUFFER_m_329,Program Memory 32-bit word" line.long 0x42C "IME3_PROGRAMBUFFER_m_330,Program Memory 32-bit word" line.long 0x430 "IME3_PROGRAMBUFFER_m_331,Program Memory 32-bit word" line.long 0x434 "IME3_PROGRAMBUFFER_m_332,Program Memory 32-bit word" line.long 0x438 "IME3_PROGRAMBUFFER_m_333,Program Memory 32-bit word" line.long 0x43C "IME3_PROGRAMBUFFER_m_334,Program Memory 32-bit word" line.long 0x440 "IME3_PROGRAMBUFFER_m_335,Program Memory 32-bit word" line.long 0x444 "IME3_PROGRAMBUFFER_m_336,Program Memory 32-bit word" line.long 0x448 "IME3_PROGRAMBUFFER_m_337,Program Memory 32-bit word" line.long 0x44C "IME3_PROGRAMBUFFER_m_338,Program Memory 32-bit word" line.long 0x450 "IME3_PROGRAMBUFFER_m_339,Program Memory 32-bit word" line.long 0x454 "IME3_PROGRAMBUFFER_m_340,Program Memory 32-bit word" line.long 0x458 "IME3_PROGRAMBUFFER_m_341,Program Memory 32-bit word" line.long 0x45C "IME3_PROGRAMBUFFER_m_342,Program Memory 32-bit word" line.long 0x460 "IME3_PROGRAMBUFFER_m_343,Program Memory 32-bit word" line.long 0x464 "IME3_PROGRAMBUFFER_m_344,Program Memory 32-bit word" line.long 0x468 "IME3_PROGRAMBUFFER_m_345,Program Memory 32-bit word" line.long 0x46C "IME3_PROGRAMBUFFER_m_346,Program Memory 32-bit word" line.long 0x470 "IME3_PROGRAMBUFFER_m_347,Program Memory 32-bit word" line.long 0x474 "IME3_PROGRAMBUFFER_m_348,Program Memory 32-bit word" line.long 0x478 "IME3_PROGRAMBUFFER_m_349,Program Memory 32-bit word" line.long 0x47C "IME3_PROGRAMBUFFER_m_350,Program Memory 32-bit word" line.long 0x480 "IME3_PROGRAMBUFFER_m_351,Program Memory 32-bit word" line.long 0x484 "IME3_PROGRAMBUFFER_m_352,Program Memory 32-bit word" line.long 0x488 "IME3_PROGRAMBUFFER_m_353,Program Memory 32-bit word" line.long 0x48C "IME3_PROGRAMBUFFER_m_354,Program Memory 32-bit word" line.long 0x490 "IME3_PROGRAMBUFFER_m_355,Program Memory 32-bit word" line.long 0x494 "IME3_PROGRAMBUFFER_m_356,Program Memory 32-bit word" line.long 0x498 "IME3_PROGRAMBUFFER_m_357,Program Memory 32-bit word" line.long 0x49C "IME3_PROGRAMBUFFER_m_358,Program Memory 32-bit word" line.long 0x4A0 "IME3_PROGRAMBUFFER_m_359,Program Memory 32-bit word" line.long 0x4A4 "IME3_PROGRAMBUFFER_m_360,Program Memory 32-bit word" line.long 0x4A8 "IME3_PROGRAMBUFFER_m_361,Program Memory 32-bit word" line.long 0x4AC "IME3_PROGRAMBUFFER_m_362,Program Memory 32-bit word" line.long 0x4B0 "IME3_PROGRAMBUFFER_m_363,Program Memory 32-bit word" line.long 0x4B4 "IME3_PROGRAMBUFFER_m_364,Program Memory 32-bit word" line.long 0x4B8 "IME3_PROGRAMBUFFER_m_365,Program Memory 32-bit word" line.long 0x4BC "IME3_PROGRAMBUFFER_m_366,Program Memory 32-bit word" line.long 0x4C0 "IME3_PROGRAMBUFFER_m_367,Program Memory 32-bit word" line.long 0x4C4 "IME3_PROGRAMBUFFER_m_368,Program Memory 32-bit word" line.long 0x4C8 "IME3_PROGRAMBUFFER_m_369,Program Memory 32-bit word" line.long 0x4CC "IME3_PROGRAMBUFFER_m_370,Program Memory 32-bit word" line.long 0x4D0 "IME3_PROGRAMBUFFER_m_371,Program Memory 32-bit word" line.long 0x4D4 "IME3_PROGRAMBUFFER_m_372,Program Memory 32-bit word" line.long 0x4D8 "IME3_PROGRAMBUFFER_m_373,Program Memory 32-bit word" line.long 0x4DC "IME3_PROGRAMBUFFER_m_374,Program Memory 32-bit word" line.long 0x4E0 "IME3_PROGRAMBUFFER_m_375,Program Memory 32-bit word" line.long 0x4E4 "IME3_PROGRAMBUFFER_m_376,Program Memory 32-bit word" line.long 0x4E8 "IME3_PROGRAMBUFFER_m_377,Program Memory 32-bit word" line.long 0x4EC "IME3_PROGRAMBUFFER_m_378,Program Memory 32-bit word" line.long 0x4F0 "IME3_PROGRAMBUFFER_m_379,Program Memory 32-bit word" line.long 0x4F4 "IME3_PROGRAMBUFFER_m_380,Program Memory 32-bit word" line.long 0x4F8 "IME3_PROGRAMBUFFER_m_381,Program Memory 32-bit word" line.long 0x4FC "IME3_PROGRAMBUFFER_m_382,Program Memory 32-bit word" line.long 0x500 "IME3_PROGRAMBUFFER_m_383,Program Memory 32-bit word" line.long 0x504 "IME3_PROGRAMBUFFER_m_384,Program Memory 32-bit word" line.long 0x508 "IME3_PROGRAMBUFFER_m_385,Program Memory 32-bit word" line.long 0x50C "IME3_PROGRAMBUFFER_m_386,Program Memory 32-bit word" line.long 0x510 "IME3_PROGRAMBUFFER_m_387,Program Memory 32-bit word" line.long 0x514 "IME3_PROGRAMBUFFER_m_388,Program Memory 32-bit word" line.long 0x518 "IME3_PROGRAMBUFFER_m_389,Program Memory 32-bit word" line.long 0x51C "IME3_PROGRAMBUFFER_m_390,Program Memory 32-bit word" line.long 0x520 "IME3_PROGRAMBUFFER_m_391,Program Memory 32-bit word" line.long 0x524 "IME3_PROGRAMBUFFER_m_392,Program Memory 32-bit word" line.long 0x528 "IME3_PROGRAMBUFFER_m_393,Program Memory 32-bit word" line.long 0x52C "IME3_PROGRAMBUFFER_m_394,Program Memory 32-bit word" line.long 0x530 "IME3_PROGRAMBUFFER_m_395,Program Memory 32-bit word" line.long 0x534 "IME3_PROGRAMBUFFER_m_396,Program Memory 32-bit word" line.long 0x538 "IME3_PROGRAMBUFFER_m_397,Program Memory 32-bit word" line.long 0x53C "IME3_PROGRAMBUFFER_m_398,Program Memory 32-bit word" line.long 0x540 "IME3_PROGRAMBUFFER_m_399,Program Memory 32-bit word" line.long 0x544 "IME3_PROGRAMBUFFER_m_400,Program Memory 32-bit word" line.long 0x548 "IME3_PROGRAMBUFFER_m_401,Program Memory 32-bit word" line.long 0x54C "IME3_PROGRAMBUFFER_m_402,Program Memory 32-bit word" line.long 0x550 "IME3_PROGRAMBUFFER_m_403,Program Memory 32-bit word" line.long 0x554 "IME3_PROGRAMBUFFER_m_404,Program Memory 32-bit word" line.long 0x558 "IME3_PROGRAMBUFFER_m_405,Program Memory 32-bit word" line.long 0x55C "IME3_PROGRAMBUFFER_m_406,Program Memory 32-bit word" line.long 0x560 "IME3_PROGRAMBUFFER_m_407,Program Memory 32-bit word" line.long 0x564 "IME3_PROGRAMBUFFER_m_408,Program Memory 32-bit word" line.long 0x568 "IME3_PROGRAMBUFFER_m_409,Program Memory 32-bit word" line.long 0x56C "IME3_PROGRAMBUFFER_m_410,Program Memory 32-bit word" line.long 0x570 "IME3_PROGRAMBUFFER_m_411,Program Memory 32-bit word" line.long 0x574 "IME3_PROGRAMBUFFER_m_412,Program Memory 32-bit word" line.long 0x578 "IME3_PROGRAMBUFFER_m_413,Program Memory 32-bit word" line.long 0x57C "IME3_PROGRAMBUFFER_m_414,Program Memory 32-bit word" line.long 0x580 "IME3_PROGRAMBUFFER_m_415,Program Memory 32-bit word" line.long 0x584 "IME3_PROGRAMBUFFER_m_416,Program Memory 32-bit word" line.long 0x588 "IME3_PROGRAMBUFFER_m_417,Program Memory 32-bit word" line.long 0x58C "IME3_PROGRAMBUFFER_m_418,Program Memory 32-bit word" line.long 0x590 "IME3_PROGRAMBUFFER_m_419,Program Memory 32-bit word" line.long 0x594 "IME3_PROGRAMBUFFER_m_420,Program Memory 32-bit word" line.long 0x598 "IME3_PROGRAMBUFFER_m_421,Program Memory 32-bit word" line.long 0x59C "IME3_PROGRAMBUFFER_m_422,Program Memory 32-bit word" line.long 0x5A0 "IME3_PROGRAMBUFFER_m_423,Program Memory 32-bit word" line.long 0x5A4 "IME3_PROGRAMBUFFER_m_424,Program Memory 32-bit word" line.long 0x5A8 "IME3_PROGRAMBUFFER_m_425,Program Memory 32-bit word" line.long 0x5AC "IME3_PROGRAMBUFFER_m_426,Program Memory 32-bit word" line.long 0x5B0 "IME3_PROGRAMBUFFER_m_427,Program Memory 32-bit word" line.long 0x5B4 "IME3_PROGRAMBUFFER_m_428,Program Memory 32-bit word" line.long 0x5B8 "IME3_PROGRAMBUFFER_m_429,Program Memory 32-bit word" line.long 0x5BC "IME3_PROGRAMBUFFER_m_430,Program Memory 32-bit word" line.long 0x5C0 "IME3_PROGRAMBUFFER_m_431,Program Memory 32-bit word" line.long 0x5C4 "IME3_PROGRAMBUFFER_m_432,Program Memory 32-bit word" line.long 0x5C8 "IME3_PROGRAMBUFFER_m_433,Program Memory 32-bit word" line.long 0x5CC "IME3_PROGRAMBUFFER_m_434,Program Memory 32-bit word" line.long 0x5D0 "IME3_PROGRAMBUFFER_m_435,Program Memory 32-bit word" line.long 0x5D4 "IME3_PROGRAMBUFFER_m_436,Program Memory 32-bit word" line.long 0x5D8 "IME3_PROGRAMBUFFER_m_437,Program Memory 32-bit word" line.long 0x5DC "IME3_PROGRAMBUFFER_m_438,Program Memory 32-bit word" line.long 0x5E0 "IME3_PROGRAMBUFFER_m_439,Program Memory 32-bit word" line.long 0x5E4 "IME3_PROGRAMBUFFER_m_440,Program Memory 32-bit word" line.long 0x5E8 "IME3_PROGRAMBUFFER_m_441,Program Memory 32-bit word" line.long 0x5EC "IME3_PROGRAMBUFFER_m_442,Program Memory 32-bit word" line.long 0x5F0 "IME3_PROGRAMBUFFER_m_443,Program Memory 32-bit word" line.long 0x5F4 "IME3_PROGRAMBUFFER_m_444,Program Memory 32-bit word" line.long 0x5F8 "IME3_PROGRAMBUFFER_m_445,Program Memory 32-bit word" line.long 0x5FC "IME3_PROGRAMBUFFER_m_446,Program Memory 32-bit word" line.long 0x600 "IME3_PROGRAMBUFFER_m_447,Program Memory 32-bit word" line.long 0x604 "IME3_PROGRAMBUFFER_m_448,Program Memory 32-bit word" line.long 0x608 "IME3_PROGRAMBUFFER_m_449,Program Memory 32-bit word" line.long 0x60C "IME3_PROGRAMBUFFER_m_450,Program Memory 32-bit word" line.long 0x610 "IME3_PROGRAMBUFFER_m_451,Program Memory 32-bit word" line.long 0x614 "IME3_PROGRAMBUFFER_m_452,Program Memory 32-bit word" line.long 0x618 "IME3_PROGRAMBUFFER_m_453,Program Memory 32-bit word" line.long 0x61C "IME3_PROGRAMBUFFER_m_454,Program Memory 32-bit word" line.long 0x620 "IME3_PROGRAMBUFFER_m_455,Program Memory 32-bit word" line.long 0x624 "IME3_PROGRAMBUFFER_m_456,Program Memory 32-bit word" line.long 0x628 "IME3_PROGRAMBUFFER_m_457,Program Memory 32-bit word" line.long 0x62C "IME3_PROGRAMBUFFER_m_458,Program Memory 32-bit word" line.long 0x630 "IME3_PROGRAMBUFFER_m_459,Program Memory 32-bit word" line.long 0x634 "IME3_PROGRAMBUFFER_m_460,Program Memory 32-bit word" line.long 0x638 "IME3_PROGRAMBUFFER_m_461,Program Memory 32-bit word" line.long 0x63C "IME3_PROGRAMBUFFER_m_462,Program Memory 32-bit word" line.long 0x640 "IME3_PROGRAMBUFFER_m_463,Program Memory 32-bit word" line.long 0x644 "IME3_PROGRAMBUFFER_m_464,Program Memory 32-bit word" line.long 0x648 "IME3_PROGRAMBUFFER_m_465,Program Memory 32-bit word" line.long 0x64C "IME3_PROGRAMBUFFER_m_466,Program Memory 32-bit word" line.long 0x650 "IME3_PROGRAMBUFFER_m_467,Program Memory 32-bit word" line.long 0x654 "IME3_PROGRAMBUFFER_m_468,Program Memory 32-bit word" line.long 0x658 "IME3_PROGRAMBUFFER_m_469,Program Memory 32-bit word" line.long 0x65C "IME3_PROGRAMBUFFER_m_470,Program Memory 32-bit word" line.long 0x660 "IME3_PROGRAMBUFFER_m_471,Program Memory 32-bit word" line.long 0x664 "IME3_PROGRAMBUFFER_m_472,Program Memory 32-bit word" line.long 0x668 "IME3_PROGRAMBUFFER_m_473,Program Memory 32-bit word" line.long 0x66C "IME3_PROGRAMBUFFER_m_474,Program Memory 32-bit word" line.long 0x670 "IME3_PROGRAMBUFFER_m_475,Program Memory 32-bit word" line.long 0x674 "IME3_PROGRAMBUFFER_m_476,Program Memory 32-bit word" line.long 0x678 "IME3_PROGRAMBUFFER_m_477,Program Memory 32-bit word" line.long 0x67C "IME3_PROGRAMBUFFER_m_478,Program Memory 32-bit word" line.long 0x680 "IME3_PROGRAMBUFFER_m_479,Program Memory 32-bit word" line.long 0x684 "IME3_PROGRAMBUFFER_m_480,Program Memory 32-bit word" line.long 0x688 "IME3_PROGRAMBUFFER_m_481,Program Memory 32-bit word" line.long 0x68C "IME3_PROGRAMBUFFER_m_482,Program Memory 32-bit word" line.long 0x690 "IME3_PROGRAMBUFFER_m_483,Program Memory 32-bit word" line.long 0x694 "IME3_PROGRAMBUFFER_m_484,Program Memory 32-bit word" line.long 0x698 "IME3_PROGRAMBUFFER_m_485,Program Memory 32-bit word" line.long 0x69C "IME3_PROGRAMBUFFER_m_486,Program Memory 32-bit word" line.long 0x6A0 "IME3_PROGRAMBUFFER_m_487,Program Memory 32-bit word" line.long 0x6A4 "IME3_PROGRAMBUFFER_m_488,Program Memory 32-bit word" line.long 0x6A8 "IME3_PROGRAMBUFFER_m_489,Program Memory 32-bit word" line.long 0x6AC "IME3_PROGRAMBUFFER_m_490,Program Memory 32-bit word" line.long 0x6B0 "IME3_PROGRAMBUFFER_m_491,Program Memory 32-bit word" line.long 0x6B4 "IME3_PROGRAMBUFFER_m_492,Program Memory 32-bit word" line.long 0x6B8 "IME3_PROGRAMBUFFER_m_493,Program Memory 32-bit word" line.long 0x6BC "IME3_PROGRAMBUFFER_m_494,Program Memory 32-bit word" line.long 0x6C0 "IME3_PROGRAMBUFFER_m_495,Program Memory 32-bit word" line.long 0x6C4 "IME3_PROGRAMBUFFER_m_496,Program Memory 32-bit word" line.long 0x6C8 "IME3_PROGRAMBUFFER_m_497,Program Memory 32-bit word" line.long 0x6CC "IME3_PROGRAMBUFFER_m_498,Program Memory 32-bit word" line.long 0x6D0 "IME3_PROGRAMBUFFER_m_499,Program Memory 32-bit word" line.long 0x6D4 "IME3_PROGRAMBUFFER_m_500,Program Memory 32-bit word" line.long 0x6D8 "IME3_PROGRAMBUFFER_m_501,Program Memory 32-bit word" line.long 0x6DC "IME3_PROGRAMBUFFER_m_502,Program Memory 32-bit word" line.long 0x6E0 "IME3_PROGRAMBUFFER_m_503,Program Memory 32-bit word" line.long 0x6E4 "IME3_PROGRAMBUFFER_m_504,Program Memory 32-bit word" line.long 0x6E8 "IME3_PROGRAMBUFFER_m_505,Program Memory 32-bit word" line.long 0x6EC "IME3_PROGRAMBUFFER_m_506,Program Memory 32-bit word" line.long 0x6F0 "IME3_PROGRAMBUFFER_m_507,Program Memory 32-bit word" line.long 0x6F4 "IME3_PROGRAMBUFFER_m_508,Program Memory 32-bit word" line.long 0x6F8 "IME3_PROGRAMBUFFER_m_509,Program Memory 32-bit word" line.long 0x6FC "IME3_PROGRAMBUFFER_m_510,Program Memory 32-bit word" line.long 0x700 "IME3_PROGRAMBUFFER_m_511,Program Memory 32-bit word" line.long 0x704 "IME3_PROGRAMBUFFER_m_512,Program Memory 32-bit word" line.long 0x708 "IME3_PROGRAMBUFFER_m_513,Program Memory 32-bit word" line.long 0x70C "IME3_PROGRAMBUFFER_m_514,Program Memory 32-bit word" line.long 0x710 "IME3_PROGRAMBUFFER_m_515,Program Memory 32-bit word" line.long 0x714 "IME3_PROGRAMBUFFER_m_516,Program Memory 32-bit word" line.long 0x718 "IME3_PROGRAMBUFFER_m_517,Program Memory 32-bit word" line.long 0x71C "IME3_PROGRAMBUFFER_m_518,Program Memory 32-bit word" line.long 0x720 "IME3_PROGRAMBUFFER_m_519,Program Memory 32-bit word" line.long 0x724 "IME3_PROGRAMBUFFER_m_520,Program Memory 32-bit word" line.long 0x728 "IME3_PROGRAMBUFFER_m_521,Program Memory 32-bit word" line.long 0x72C "IME3_PROGRAMBUFFER_m_522,Program Memory 32-bit word" line.long 0x730 "IME3_PROGRAMBUFFER_m_523,Program Memory 32-bit word" line.long 0x734 "IME3_PROGRAMBUFFER_m_524,Program Memory 32-bit word" line.long 0x738 "IME3_PROGRAMBUFFER_m_525,Program Memory 32-bit word" line.long 0x73C "IME3_PROGRAMBUFFER_m_526,Program Memory 32-bit word" line.long 0x740 "IME3_PROGRAMBUFFER_m_527,Program Memory 32-bit word" line.long 0x744 "IME3_PROGRAMBUFFER_m_528,Program Memory 32-bit word" line.long 0x748 "IME3_PROGRAMBUFFER_m_529,Program Memory 32-bit word" line.long 0x74C "IME3_PROGRAMBUFFER_m_530,Program Memory 32-bit word" line.long 0x750 "IME3_PROGRAMBUFFER_m_531,Program Memory 32-bit word" line.long 0x754 "IME3_PROGRAMBUFFER_m_532,Program Memory 32-bit word" line.long 0x758 "IME3_PROGRAMBUFFER_m_533,Program Memory 32-bit word" line.long 0x75C "IME3_PROGRAMBUFFER_m_534,Program Memory 32-bit word" line.long 0x760 "IME3_PROGRAMBUFFER_m_535,Program Memory 32-bit word" line.long 0x764 "IME3_PROGRAMBUFFER_m_536,Program Memory 32-bit word" line.long 0x768 "IME3_PROGRAMBUFFER_m_537,Program Memory 32-bit word" line.long 0x76C "IME3_PROGRAMBUFFER_m_538,Program Memory 32-bit word" line.long 0x770 "IME3_PROGRAMBUFFER_m_539,Program Memory 32-bit word" line.long 0x774 "IME3_PROGRAMBUFFER_m_540,Program Memory 32-bit word" line.long 0x778 "IME3_PROGRAMBUFFER_m_541,Program Memory 32-bit word" line.long 0x77C "IME3_PROGRAMBUFFER_m_542,Program Memory 32-bit word" line.long 0x780 "IME3_PROGRAMBUFFER_m_543,Program Memory 32-bit word" line.long 0x784 "IME3_PROGRAMBUFFER_m_544,Program Memory 32-bit word" line.long 0x788 "IME3_PROGRAMBUFFER_m_545,Program Memory 32-bit word" line.long 0x78C "IME3_PROGRAMBUFFER_m_546,Program Memory 32-bit word" line.long 0x790 "IME3_PROGRAMBUFFER_m_547,Program Memory 32-bit word" line.long 0x794 "IME3_PROGRAMBUFFER_m_548,Program Memory 32-bit word" line.long 0x798 "IME3_PROGRAMBUFFER_m_549,Program Memory 32-bit word" line.long 0x79C "IME3_PROGRAMBUFFER_m_550,Program Memory 32-bit word" line.long 0x7A0 "IME3_PROGRAMBUFFER_m_551,Program Memory 32-bit word" line.long 0x7A4 "IME3_PROGRAMBUFFER_m_552,Program Memory 32-bit word" line.long 0x7A8 "IME3_PROGRAMBUFFER_m_553,Program Memory 32-bit word" line.long 0x7AC "IME3_PROGRAMBUFFER_m_554,Program Memory 32-bit word" line.long 0x7B0 "IME3_PROGRAMBUFFER_m_555,Program Memory 32-bit word" line.long 0x7B4 "IME3_PROGRAMBUFFER_m_556,Program Memory 32-bit word" line.long 0x7B8 "IME3_PROGRAMBUFFER_m_557,Program Memory 32-bit word" line.long 0x7BC "IME3_PROGRAMBUFFER_m_558,Program Memory 32-bit word" line.long 0x7C0 "IME3_PROGRAMBUFFER_m_559,Program Memory 32-bit word" line.long 0x7C4 "IME3_PROGRAMBUFFER_m_560,Program Memory 32-bit word" line.long 0x7C8 "IME3_PROGRAMBUFFER_m_561,Program Memory 32-bit word" line.long 0x7CC "IME3_PROGRAMBUFFER_m_562,Program Memory 32-bit word" line.long 0x7D0 "IME3_PROGRAMBUFFER_m_563,Program Memory 32-bit word" line.long 0x7D4 "IME3_PROGRAMBUFFER_m_564,Program Memory 32-bit word" line.long 0x7D8 "IME3_PROGRAMBUFFER_m_565,Program Memory 32-bit word" line.long 0x7DC "IME3_PROGRAMBUFFER_m_566,Program Memory 32-bit word" line.long 0x7E0 "IME3_PROGRAMBUFFER_m_567,Program Memory 32-bit word" line.long 0x7E4 "IME3_PROGRAMBUFFER_m_568,Program Memory 32-bit word" line.long 0x7E8 "IME3_PROGRAMBUFFER_m_569,Program Memory 32-bit word" line.long 0x7EC "IME3_PROGRAMBUFFER_m_570,Program Memory 32-bit word" line.long 0x7F0 "IME3_PROGRAMBUFFER_m_571,Program Memory 32-bit word" line.long 0x7F4 "IME3_PROGRAMBUFFER_m_572,Program Memory 32-bit word" line.long 0x7F8 "IME3_PROGRAMBUFFER_m_573,Program Memory 32-bit word" line.long 0x7FC "IME3_PROGRAMBUFFER_m_574,Program Memory 32-bit word" line.long 0x800 "IME3_PROGRAMBUFFER_m_575,Program Memory 32-bit word" line.long 0x804 "IME3_PROGRAMBUFFER_m_576,Program Memory 32-bit word" line.long 0x808 "IME3_PROGRAMBUFFER_m_577,Program Memory 32-bit word" line.long 0x80C "IME3_PROGRAMBUFFER_m_578,Program Memory 32-bit word" line.long 0x810 "IME3_PROGRAMBUFFER_m_579,Program Memory 32-bit word" line.long 0x814 "IME3_PROGRAMBUFFER_m_580,Program Memory 32-bit word" line.long 0x818 "IME3_PROGRAMBUFFER_m_581,Program Memory 32-bit word" line.long 0x81C "IME3_PROGRAMBUFFER_m_582,Program Memory 32-bit word" line.long 0x820 "IME3_PROGRAMBUFFER_m_583,Program Memory 32-bit word" line.long 0x824 "IME3_PROGRAMBUFFER_m_584,Program Memory 32-bit word" line.long 0x828 "IME3_PROGRAMBUFFER_m_585,Program Memory 32-bit word" line.long 0x82C "IME3_PROGRAMBUFFER_m_586,Program Memory 32-bit word" line.long 0x830 "IME3_PROGRAMBUFFER_m_587,Program Memory 32-bit word" line.long 0x834 "IME3_PROGRAMBUFFER_m_588,Program Memory 32-bit word" line.long 0x838 "IME3_PROGRAMBUFFER_m_589,Program Memory 32-bit word" line.long 0x83C "IME3_PROGRAMBUFFER_m_590,Program Memory 32-bit word" line.long 0x840 "IME3_PROGRAMBUFFER_m_591,Program Memory 32-bit word" line.long 0x844 "IME3_PROGRAMBUFFER_m_592,Program Memory 32-bit word" line.long 0x848 "IME3_PROGRAMBUFFER_m_593,Program Memory 32-bit word" line.long 0x84C "IME3_PROGRAMBUFFER_m_594,Program Memory 32-bit word" line.long 0x850 "IME3_PROGRAMBUFFER_m_595,Program Memory 32-bit word" line.long 0x854 "IME3_PROGRAMBUFFER_m_596,Program Memory 32-bit word" line.long 0x858 "IME3_PROGRAMBUFFER_m_597,Program Memory 32-bit word" line.long 0x85C "IME3_PROGRAMBUFFER_m_598,Program Memory 32-bit word" line.long 0x860 "IME3_PROGRAMBUFFER_m_599,Program Memory 32-bit word" line.long 0x864 "IME3_PROGRAMBUFFER_m_600,Program Memory 32-bit word" line.long 0x868 "IME3_PROGRAMBUFFER_m_601,Program Memory 32-bit word" line.long 0x86C "IME3_PROGRAMBUFFER_m_602,Program Memory 32-bit word" line.long 0x870 "IME3_PROGRAMBUFFER_m_603,Program Memory 32-bit word" line.long 0x874 "IME3_PROGRAMBUFFER_m_604,Program Memory 32-bit word" line.long 0x878 "IME3_PROGRAMBUFFER_m_605,Program Memory 32-bit word" line.long 0x87C "IME3_PROGRAMBUFFER_m_606,Program Memory 32-bit word" line.long 0x880 "IME3_PROGRAMBUFFER_m_607,Program Memory 32-bit word" line.long 0x884 "IME3_PROGRAMBUFFER_m_608,Program Memory 32-bit word" line.long 0x888 "IME3_PROGRAMBUFFER_m_609,Program Memory 32-bit word" line.long 0x88C "IME3_PROGRAMBUFFER_m_610,Program Memory 32-bit word" line.long 0x890 "IME3_PROGRAMBUFFER_m_611,Program Memory 32-bit word" line.long 0x894 "IME3_PROGRAMBUFFER_m_612,Program Memory 32-bit word" line.long 0x898 "IME3_PROGRAMBUFFER_m_613,Program Memory 32-bit word" line.long 0x89C "IME3_PROGRAMBUFFER_m_614,Program Memory 32-bit word" line.long 0x8A0 "IME3_PROGRAMBUFFER_m_615,Program Memory 32-bit word" line.long 0x8A4 "IME3_PROGRAMBUFFER_m_616,Program Memory 32-bit word" line.long 0x8A8 "IME3_PROGRAMBUFFER_m_617,Program Memory 32-bit word" line.long 0x8AC "IME3_PROGRAMBUFFER_m_618,Program Memory 32-bit word" line.long 0x8B0 "IME3_PROGRAMBUFFER_m_619,Program Memory 32-bit word" line.long 0x8B4 "IME3_PROGRAMBUFFER_m_620,Program Memory 32-bit word" line.long 0x8B8 "IME3_PROGRAMBUFFER_m_621,Program Memory 32-bit word" line.long 0x8BC "IME3_PROGRAMBUFFER_m_622,Program Memory 32-bit word" line.long 0x8C0 "IME3_PROGRAMBUFFER_m_623,Program Memory 32-bit word" line.long 0x8C4 "IME3_PROGRAMBUFFER_m_624,Program Memory 32-bit word" line.long 0x8C8 "IME3_PROGRAMBUFFER_m_625,Program Memory 32-bit word" line.long 0x8CC "IME3_PROGRAMBUFFER_m_626,Program Memory 32-bit word" line.long 0x8D0 "IME3_PROGRAMBUFFER_m_627,Program Memory 32-bit word" line.long 0x8D4 "IME3_PROGRAMBUFFER_m_628,Program Memory 32-bit word" line.long 0x8D8 "IME3_PROGRAMBUFFER_m_629,Program Memory 32-bit word" line.long 0x8DC "IME3_PROGRAMBUFFER_m_630,Program Memory 32-bit word" line.long 0x8E0 "IME3_PROGRAMBUFFER_m_631,Program Memory 32-bit word" line.long 0x8E4 "IME3_PROGRAMBUFFER_m_632,Program Memory 32-bit word" line.long 0x8E8 "IME3_PROGRAMBUFFER_m_633,Program Memory 32-bit word" line.long 0x8EC "IME3_PROGRAMBUFFER_m_634,Program Memory 32-bit word" line.long 0x8F0 "IME3_PROGRAMBUFFER_m_635,Program Memory 32-bit word" line.long 0x8F4 "IME3_PROGRAMBUFFER_m_636,Program Memory 32-bit word" line.long 0x8F8 "IME3_PROGRAMBUFFER_m_637,Program Memory 32-bit word" line.long 0x8FC "IME3_PROGRAMBUFFER_m_638,Program Memory 32-bit word" line.long 0x900 "IME3_PROGRAMBUFFER_m_639,Program Memory 32-bit word" line.long 0x904 "IME3_PROGRAMBUFFER_m_640,Program Memory 32-bit word" line.long 0x908 "IME3_PROGRAMBUFFER_m_641,Program Memory 32-bit word" line.long 0x90C "IME3_PROGRAMBUFFER_m_642,Program Memory 32-bit word" line.long 0x910 "IME3_PROGRAMBUFFER_m_643,Program Memory 32-bit word" line.long 0x914 "IME3_PROGRAMBUFFER_m_644,Program Memory 32-bit word" line.long 0x918 "IME3_PROGRAMBUFFER_m_645,Program Memory 32-bit word" line.long 0x91C "IME3_PROGRAMBUFFER_m_646,Program Memory 32-bit word" line.long 0x920 "IME3_PROGRAMBUFFER_m_647,Program Memory 32-bit word" line.long 0x924 "IME3_PROGRAMBUFFER_m_648,Program Memory 32-bit word" line.long 0x928 "IME3_PROGRAMBUFFER_m_649,Program Memory 32-bit word" line.long 0x92C "IME3_PROGRAMBUFFER_m_650,Program Memory 32-bit word" line.long 0x930 "IME3_PROGRAMBUFFER_m_651,Program Memory 32-bit word" line.long 0x934 "IME3_PROGRAMBUFFER_m_652,Program Memory 32-bit word" line.long 0x938 "IME3_PROGRAMBUFFER_m_653,Program Memory 32-bit word" line.long 0x93C "IME3_PROGRAMBUFFER_m_654,Program Memory 32-bit word" line.long 0x940 "IME3_PROGRAMBUFFER_m_655,Program Memory 32-bit word" line.long 0x944 "IME3_PROGRAMBUFFER_m_656,Program Memory 32-bit word" line.long 0x948 "IME3_PROGRAMBUFFER_m_657,Program Memory 32-bit word" line.long 0x94C "IME3_PROGRAMBUFFER_m_658,Program Memory 32-bit word" line.long 0x950 "IME3_PROGRAMBUFFER_m_659,Program Memory 32-bit word" line.long 0x954 "IME3_PROGRAMBUFFER_m_660,Program Memory 32-bit word" line.long 0x958 "IME3_PROGRAMBUFFER_m_661,Program Memory 32-bit word" line.long 0x95C "IME3_PROGRAMBUFFER_m_662,Program Memory 32-bit word" line.long 0x960 "IME3_PROGRAMBUFFER_m_663,Program Memory 32-bit word" line.long 0x964 "IME3_PROGRAMBUFFER_m_664,Program Memory 32-bit word" line.long 0x968 "IME3_PROGRAMBUFFER_m_665,Program Memory 32-bit word" line.long 0x96C "IME3_PROGRAMBUFFER_m_666,Program Memory 32-bit word" line.long 0x970 "IME3_PROGRAMBUFFER_m_667,Program Memory 32-bit word" line.long 0x974 "IME3_PROGRAMBUFFER_m_668,Program Memory 32-bit word" line.long 0x978 "IME3_PROGRAMBUFFER_m_669,Program Memory 32-bit word" line.long 0x97C "IME3_PROGRAMBUFFER_m_670,Program Memory 32-bit word" line.long 0x980 "IME3_PROGRAMBUFFER_m_671,Program Memory 32-bit word" line.long 0x984 "IME3_PROGRAMBUFFER_m_672,Program Memory 32-bit word" line.long 0x988 "IME3_PROGRAMBUFFER_m_673,Program Memory 32-bit word" line.long 0x98C "IME3_PROGRAMBUFFER_m_674,Program Memory 32-bit word" line.long 0x990 "IME3_PROGRAMBUFFER_m_675,Program Memory 32-bit word" line.long 0x994 "IME3_PROGRAMBUFFER_m_676,Program Memory 32-bit word" line.long 0x998 "IME3_PROGRAMBUFFER_m_677,Program Memory 32-bit word" line.long 0x99C "IME3_PROGRAMBUFFER_m_678,Program Memory 32-bit word" line.long 0x9A0 "IME3_PROGRAMBUFFER_m_679,Program Memory 32-bit word" line.long 0x9A4 "IME3_PROGRAMBUFFER_m_680,Program Memory 32-bit word" line.long 0x9A8 "IME3_PROGRAMBUFFER_m_681,Program Memory 32-bit word" line.long 0x9AC "IME3_PROGRAMBUFFER_m_682,Program Memory 32-bit word" line.long 0x9B0 "IME3_PROGRAMBUFFER_m_683,Program Memory 32-bit word" line.long 0x9B4 "IME3_PROGRAMBUFFER_m_684,Program Memory 32-bit word" line.long 0x9B8 "IME3_PROGRAMBUFFER_m_685,Program Memory 32-bit word" line.long 0x9BC "IME3_PROGRAMBUFFER_m_686,Program Memory 32-bit word" line.long 0x9C0 "IME3_PROGRAMBUFFER_m_687,Program Memory 32-bit word" line.long 0x9C4 "IME3_PROGRAMBUFFER_m_688,Program Memory 32-bit word" line.long 0x9C8 "IME3_PROGRAMBUFFER_m_689,Program Memory 32-bit word" line.long 0x9CC "IME3_PROGRAMBUFFER_m_690,Program Memory 32-bit word" line.long 0x9D0 "IME3_PROGRAMBUFFER_m_691,Program Memory 32-bit word" line.long 0x9D4 "IME3_PROGRAMBUFFER_m_692,Program Memory 32-bit word" line.long 0x9D8 "IME3_PROGRAMBUFFER_m_693,Program Memory 32-bit word" line.long 0x9DC "IME3_PROGRAMBUFFER_m_694,Program Memory 32-bit word" line.long 0x9E0 "IME3_PROGRAMBUFFER_m_695,Program Memory 32-bit word" line.long 0x9E4 "IME3_PROGRAMBUFFER_m_696,Program Memory 32-bit word" line.long 0x9E8 "IME3_PROGRAMBUFFER_m_697,Program Memory 32-bit word" line.long 0x9EC "IME3_PROGRAMBUFFER_m_698,Program Memory 32-bit word" line.long 0x9F0 "IME3_PROGRAMBUFFER_m_699,Program Memory 32-bit word" line.long 0x9F4 "IME3_PROGRAMBUFFER_m_700,Program Memory 32-bit word" line.long 0x9F8 "IME3_PROGRAMBUFFER_m_701,Program Memory 32-bit word" line.long 0x9FC "IME3_PROGRAMBUFFER_m_702,Program Memory 32-bit word" line.long 0xA00 "IME3_PROGRAMBUFFER_m_703,Program Memory 32-bit word" line.long 0xA04 "IME3_PROGRAMBUFFER_m_704,Program Memory 32-bit word" line.long 0xA08 "IME3_PROGRAMBUFFER_m_705,Program Memory 32-bit word" line.long 0xA0C "IME3_PROGRAMBUFFER_m_706,Program Memory 32-bit word" line.long 0xA10 "IME3_PROGRAMBUFFER_m_707,Program Memory 32-bit word" line.long 0xA14 "IME3_PROGRAMBUFFER_m_708,Program Memory 32-bit word" line.long 0xA18 "IME3_PROGRAMBUFFER_m_709,Program Memory 32-bit word" line.long 0xA1C "IME3_PROGRAMBUFFER_m_710,Program Memory 32-bit word" line.long 0xA20 "IME3_PROGRAMBUFFER_m_711,Program Memory 32-bit word" line.long 0xA24 "IME3_PROGRAMBUFFER_m_712,Program Memory 32-bit word" line.long 0xA28 "IME3_PROGRAMBUFFER_m_713,Program Memory 32-bit word" line.long 0xA2C "IME3_PROGRAMBUFFER_m_714,Program Memory 32-bit word" line.long 0xA30 "IME3_PROGRAMBUFFER_m_715,Program Memory 32-bit word" line.long 0xA34 "IME3_PROGRAMBUFFER_m_716,Program Memory 32-bit word" line.long 0xA38 "IME3_PROGRAMBUFFER_m_717,Program Memory 32-bit word" line.long 0xA3C "IME3_PROGRAMBUFFER_m_718,Program Memory 32-bit word" line.long 0xA40 "IME3_PROGRAMBUFFER_m_719,Program Memory 32-bit word" line.long 0xA44 "IME3_PROGRAMBUFFER_m_720,Program Memory 32-bit word" line.long 0xA48 "IME3_PROGRAMBUFFER_m_721,Program Memory 32-bit word" line.long 0xA4C "IME3_PROGRAMBUFFER_m_722,Program Memory 32-bit word" line.long 0xA50 "IME3_PROGRAMBUFFER_m_723,Program Memory 32-bit word" line.long 0xA54 "IME3_PROGRAMBUFFER_m_724,Program Memory 32-bit word" line.long 0xA58 "IME3_PROGRAMBUFFER_m_725,Program Memory 32-bit word" line.long 0xA5C "IME3_PROGRAMBUFFER_m_726,Program Memory 32-bit word" line.long 0xA60 "IME3_PROGRAMBUFFER_m_727,Program Memory 32-bit word" line.long 0xA64 "IME3_PROGRAMBUFFER_m_728,Program Memory 32-bit word" line.long 0xA68 "IME3_PROGRAMBUFFER_m_729,Program Memory 32-bit word" line.long 0xA6C "IME3_PROGRAMBUFFER_m_730,Program Memory 32-bit word" line.long 0xA70 "IME3_PROGRAMBUFFER_m_731,Program Memory 32-bit word" line.long 0xA74 "IME3_PROGRAMBUFFER_m_732,Program Memory 32-bit word" line.long 0xA78 "IME3_PROGRAMBUFFER_m_733,Program Memory 32-bit word" line.long 0xA7C "IME3_PROGRAMBUFFER_m_734,Program Memory 32-bit word" line.long 0xA80 "IME3_PROGRAMBUFFER_m_735,Program Memory 32-bit word" line.long 0xA84 "IME3_PROGRAMBUFFER_m_736,Program Memory 32-bit word" line.long 0xA88 "IME3_PROGRAMBUFFER_m_737,Program Memory 32-bit word" line.long 0xA8C "IME3_PROGRAMBUFFER_m_738,Program Memory 32-bit word" line.long 0xA90 "IME3_PROGRAMBUFFER_m_739,Program Memory 32-bit word" line.long 0xA94 "IME3_PROGRAMBUFFER_m_740,Program Memory 32-bit word" line.long 0xA98 "IME3_PROGRAMBUFFER_m_741,Program Memory 32-bit word" line.long 0xA9C "IME3_PROGRAMBUFFER_m_742,Program Memory 32-bit word" line.long 0xAA0 "IME3_PROGRAMBUFFER_m_743,Program Memory 32-bit word" line.long 0xAA4 "IME3_PROGRAMBUFFER_m_744,Program Memory 32-bit word" line.long 0xAA8 "IME3_PROGRAMBUFFER_m_745,Program Memory 32-bit word" line.long 0xAAC "IME3_PROGRAMBUFFER_m_746,Program Memory 32-bit word" line.long 0xAB0 "IME3_PROGRAMBUFFER_m_747,Program Memory 32-bit word" line.long 0xAB4 "IME3_PROGRAMBUFFER_m_748,Program Memory 32-bit word" line.long 0xAB8 "IME3_PROGRAMBUFFER_m_749,Program Memory 32-bit word" line.long 0xABC "IME3_PROGRAMBUFFER_m_750,Program Memory 32-bit word" line.long 0xAC0 "IME3_PROGRAMBUFFER_m_751,Program Memory 32-bit word" line.long 0xAC4 "IME3_PROGRAMBUFFER_m_752,Program Memory 32-bit word" line.long 0xAC8 "IME3_PROGRAMBUFFER_m_753,Program Memory 32-bit word" line.long 0xACC "IME3_PROGRAMBUFFER_m_754,Program Memory 32-bit word" line.long 0xAD0 "IME3_PROGRAMBUFFER_m_755,Program Memory 32-bit word" line.long 0xAD4 "IME3_PROGRAMBUFFER_m_756,Program Memory 32-bit word" line.long 0xAD8 "IME3_PROGRAMBUFFER_m_757,Program Memory 32-bit word" line.long 0xADC "IME3_PROGRAMBUFFER_m_758,Program Memory 32-bit word" line.long 0xAE0 "IME3_PROGRAMBUFFER_m_759,Program Memory 32-bit word" line.long 0xAE4 "IME3_PROGRAMBUFFER_m_760,Program Memory 32-bit word" line.long 0xAE8 "IME3_PROGRAMBUFFER_m_761,Program Memory 32-bit word" line.long 0xAEC "IME3_PROGRAMBUFFER_m_762,Program Memory 32-bit word" line.long 0xAF0 "IME3_PROGRAMBUFFER_m_763,Program Memory 32-bit word" line.long 0xAF4 "IME3_PROGRAMBUFFER_m_764,Program Memory 32-bit word" line.long 0xAF8 "IME3_PROGRAMBUFFER_m_765,Program Memory 32-bit word" line.long 0xAFC "IME3_PROGRAMBUFFER_m_766,Program Memory 32-bit word" line.long 0xB00 "IME3_PROGRAMBUFFER_m_767,Program Memory 32-bit word" line.long 0xB04 "IME3_PROGRAMBUFFER_m_768,Program Memory 32-bit word" line.long 0xB08 "IME3_PROGRAMBUFFER_m_769,Program Memory 32-bit word" line.long 0xB0C "IME3_PROGRAMBUFFER_m_770,Program Memory 32-bit word" line.long 0xB10 "IME3_PROGRAMBUFFER_m_771,Program Memory 32-bit word" line.long 0xB14 "IME3_PROGRAMBUFFER_m_772,Program Memory 32-bit word" line.long 0xB18 "IME3_PROGRAMBUFFER_m_773,Program Memory 32-bit word" line.long 0xB1C "IME3_PROGRAMBUFFER_m_774,Program Memory 32-bit word" line.long 0xB20 "IME3_PROGRAMBUFFER_m_775,Program Memory 32-bit word" line.long 0xB24 "IME3_PROGRAMBUFFER_m_776,Program Memory 32-bit word" line.long 0xB28 "IME3_PROGRAMBUFFER_m_777,Program Memory 32-bit word" line.long 0xB2C "IME3_PROGRAMBUFFER_m_778,Program Memory 32-bit word" line.long 0xB30 "IME3_PROGRAMBUFFER_m_779,Program Memory 32-bit word" line.long 0xB34 "IME3_PROGRAMBUFFER_m_780,Program Memory 32-bit word" line.long 0xB38 "IME3_PROGRAMBUFFER_m_781,Program Memory 32-bit word" line.long 0xB3C "IME3_PROGRAMBUFFER_m_782,Program Memory 32-bit word" line.long 0xB40 "IME3_PROGRAMBUFFER_m_783,Program Memory 32-bit word" line.long 0xB44 "IME3_PROGRAMBUFFER_m_784,Program Memory 32-bit word" line.long 0xB48 "IME3_PROGRAMBUFFER_m_785,Program Memory 32-bit word" line.long 0xB4C "IME3_PROGRAMBUFFER_m_786,Program Memory 32-bit word" line.long 0xB50 "IME3_PROGRAMBUFFER_m_787,Program Memory 32-bit word" line.long 0xB54 "IME3_PROGRAMBUFFER_m_788,Program Memory 32-bit word" line.long 0xB58 "IME3_PROGRAMBUFFER_m_789,Program Memory 32-bit word" line.long 0xB5C "IME3_PROGRAMBUFFER_m_790,Program Memory 32-bit word" line.long 0xB60 "IME3_PROGRAMBUFFER_m_791,Program Memory 32-bit word" line.long 0xB64 "IME3_PROGRAMBUFFER_m_792,Program Memory 32-bit word" line.long 0xB68 "IME3_PROGRAMBUFFER_m_793,Program Memory 32-bit word" line.long 0xB6C "IME3_PROGRAMBUFFER_m_794,Program Memory 32-bit word" line.long 0xB70 "IME3_PROGRAMBUFFER_m_795,Program Memory 32-bit word" line.long 0xB74 "IME3_PROGRAMBUFFER_m_796,Program Memory 32-bit word" line.long 0xB78 "IME3_PROGRAMBUFFER_m_797,Program Memory 32-bit word" line.long 0xB7C "IME3_PROGRAMBUFFER_m_798,Program Memory 32-bit word" line.long 0xB80 "IME3_PROGRAMBUFFER_m_799,Program Memory 32-bit word" line.long 0xB84 "IME3_PROGRAMBUFFER_m_800,Program Memory 32-bit word" line.long 0xB88 "IME3_PROGRAMBUFFER_m_801,Program Memory 32-bit word" line.long 0xB8C "IME3_PROGRAMBUFFER_m_802,Program Memory 32-bit word" line.long 0xB90 "IME3_PROGRAMBUFFER_m_803,Program Memory 32-bit word" line.long 0xB94 "IME3_PROGRAMBUFFER_m_804,Program Memory 32-bit word" line.long 0xB98 "IME3_PROGRAMBUFFER_m_805,Program Memory 32-bit word" line.long 0xB9C "IME3_PROGRAMBUFFER_m_806,Program Memory 32-bit word" line.long 0xBA0 "IME3_PROGRAMBUFFER_m_807,Program Memory 32-bit word" line.long 0xBA4 "IME3_PROGRAMBUFFER_m_808,Program Memory 32-bit word" line.long 0xBA8 "IME3_PROGRAMBUFFER_m_809,Program Memory 32-bit word" line.long 0xBAC "IME3_PROGRAMBUFFER_m_810,Program Memory 32-bit word" line.long 0xBB0 "IME3_PROGRAMBUFFER_m_811,Program Memory 32-bit word" line.long 0xBB4 "IME3_PROGRAMBUFFER_m_812,Program Memory 32-bit word" line.long 0xBB8 "IME3_PROGRAMBUFFER_m_813,Program Memory 32-bit word" line.long 0xBBC "IME3_PROGRAMBUFFER_m_814,Program Memory 32-bit word" line.long 0xBC0 "IME3_PROGRAMBUFFER_m_815,Program Memory 32-bit word" line.long 0xBC4 "IME3_PROGRAMBUFFER_m_816,Program Memory 32-bit word" line.long 0xBC8 "IME3_PROGRAMBUFFER_m_817,Program Memory 32-bit word" line.long 0xBCC "IME3_PROGRAMBUFFER_m_818,Program Memory 32-bit word" line.long 0xBD0 "IME3_PROGRAMBUFFER_m_819,Program Memory 32-bit word" line.long 0xBD4 "IME3_PROGRAMBUFFER_m_820,Program Memory 32-bit word" line.long 0xBD8 "IME3_PROGRAMBUFFER_m_821,Program Memory 32-bit word" line.long 0xBDC "IME3_PROGRAMBUFFER_m_822,Program Memory 32-bit word" line.long 0xBE0 "IME3_PROGRAMBUFFER_m_823,Program Memory 32-bit word" line.long 0xBE4 "IME3_PROGRAMBUFFER_m_824,Program Memory 32-bit word" line.long 0xBE8 "IME3_PROGRAMBUFFER_m_825,Program Memory 32-bit word" line.long 0xBEC "IME3_PROGRAMBUFFER_m_826,Program Memory 32-bit word" line.long 0xBF0 "IME3_PROGRAMBUFFER_m_827,Program Memory 32-bit word" line.long 0xBF4 "IME3_PROGRAMBUFFER_m_828,Program Memory 32-bit word" line.long 0xBF8 "IME3_PROGRAMBUFFER_m_829,Program Memory 32-bit word" line.long 0xBFC "IME3_PROGRAMBUFFER_m_830,Program Memory 32-bit word" line.long 0xC00 "IME3_PROGRAMBUFFER_m_831,Program Memory 32-bit word" line.long 0xC04 "IME3_PROGRAMBUFFER_m_832,Program Memory 32-bit word" line.long 0xC08 "IME3_PROGRAMBUFFER_m_833,Program Memory 32-bit word" line.long 0xC0C "IME3_PROGRAMBUFFER_m_834,Program Memory 32-bit word" line.long 0xC10 "IME3_PROGRAMBUFFER_m_835,Program Memory 32-bit word" line.long 0xC14 "IME3_PROGRAMBUFFER_m_836,Program Memory 32-bit word" line.long 0xC18 "IME3_PROGRAMBUFFER_m_837,Program Memory 32-bit word" line.long 0xC1C "IME3_PROGRAMBUFFER_m_838,Program Memory 32-bit word" line.long 0xC20 "IME3_PROGRAMBUFFER_m_839,Program Memory 32-bit word" line.long 0xC24 "IME3_PROGRAMBUFFER_m_840,Program Memory 32-bit word" line.long 0xC28 "IME3_PROGRAMBUFFER_m_841,Program Memory 32-bit word" line.long 0xC2C "IME3_PROGRAMBUFFER_m_842,Program Memory 32-bit word" line.long 0xC30 "IME3_PROGRAMBUFFER_m_843,Program Memory 32-bit word" line.long 0xC34 "IME3_PROGRAMBUFFER_m_844,Program Memory 32-bit word" line.long 0xC38 "IME3_PROGRAMBUFFER_m_845,Program Memory 32-bit word" line.long 0xC3C "IME3_PROGRAMBUFFER_m_846,Program Memory 32-bit word" line.long 0xC40 "IME3_PROGRAMBUFFER_m_847,Program Memory 32-bit word" line.long 0xC44 "IME3_PROGRAMBUFFER_m_848,Program Memory 32-bit word" line.long 0xC48 "IME3_PROGRAMBUFFER_m_849,Program Memory 32-bit word" line.long 0xC4C "IME3_PROGRAMBUFFER_m_850,Program Memory 32-bit word" line.long 0xC50 "IME3_PROGRAMBUFFER_m_851,Program Memory 32-bit word" line.long 0xC54 "IME3_PROGRAMBUFFER_m_852,Program Memory 32-bit word" line.long 0xC58 "IME3_PROGRAMBUFFER_m_853,Program Memory 32-bit word" line.long 0xC5C "IME3_PROGRAMBUFFER_m_854,Program Memory 32-bit word" line.long 0xC60 "IME3_PROGRAMBUFFER_m_855,Program Memory 32-bit word" line.long 0xC64 "IME3_PROGRAMBUFFER_m_856,Program Memory 32-bit word" line.long 0xC68 "IME3_PROGRAMBUFFER_m_857,Program Memory 32-bit word" line.long 0xC6C "IME3_PROGRAMBUFFER_m_858,Program Memory 32-bit word" line.long 0xC70 "IME3_PROGRAMBUFFER_m_859,Program Memory 32-bit word" line.long 0xC74 "IME3_PROGRAMBUFFER_m_860,Program Memory 32-bit word" line.long 0xC78 "IME3_PROGRAMBUFFER_m_861,Program Memory 32-bit word" line.long 0xC7C "IME3_PROGRAMBUFFER_m_862,Program Memory 32-bit word" line.long 0xC80 "IME3_PROGRAMBUFFER_m_863,Program Memory 32-bit word" line.long 0xC84 "IME3_PROGRAMBUFFER_m_864,Program Memory 32-bit word" line.long 0xC88 "IME3_PROGRAMBUFFER_m_865,Program Memory 32-bit word" line.long 0xC8C "IME3_PROGRAMBUFFER_m_866,Program Memory 32-bit word" line.long 0xC90 "IME3_PROGRAMBUFFER_m_867,Program Memory 32-bit word" line.long 0xC94 "IME3_PROGRAMBUFFER_m_868,Program Memory 32-bit word" line.long 0xC98 "IME3_PROGRAMBUFFER_m_869,Program Memory 32-bit word" line.long 0xC9C "IME3_PROGRAMBUFFER_m_870,Program Memory 32-bit word" line.long 0xCA0 "IME3_PROGRAMBUFFER_m_871,Program Memory 32-bit word" line.long 0xCA4 "IME3_PROGRAMBUFFER_m_872,Program Memory 32-bit word" line.long 0xCA8 "IME3_PROGRAMBUFFER_m_873,Program Memory 32-bit word" line.long 0xCAC "IME3_PROGRAMBUFFER_m_874,Program Memory 32-bit word" line.long 0xCB0 "IME3_PROGRAMBUFFER_m_875,Program Memory 32-bit word" line.long 0xCB4 "IME3_PROGRAMBUFFER_m_876,Program Memory 32-bit word" line.long 0xCB8 "IME3_PROGRAMBUFFER_m_877,Program Memory 32-bit word" line.long 0xCBC "IME3_PROGRAMBUFFER_m_878,Program Memory 32-bit word" line.long 0xCC0 "IME3_PROGRAMBUFFER_m_879,Program Memory 32-bit word" line.long 0xCC4 "IME3_PROGRAMBUFFER_m_880,Program Memory 32-bit word" line.long 0xCC8 "IME3_PROGRAMBUFFER_m_881,Program Memory 32-bit word" line.long 0xCCC "IME3_PROGRAMBUFFER_m_882,Program Memory 32-bit word" line.long 0xCD0 "IME3_PROGRAMBUFFER_m_883,Program Memory 32-bit word" line.long 0xCD4 "IME3_PROGRAMBUFFER_m_884,Program Memory 32-bit word" line.long 0xCD8 "IME3_PROGRAMBUFFER_m_885,Program Memory 32-bit word" line.long 0xCDC "IME3_PROGRAMBUFFER_m_886,Program Memory 32-bit word" line.long 0xCE0 "IME3_PROGRAMBUFFER_m_887,Program Memory 32-bit word" line.long 0xCE4 "IME3_PROGRAMBUFFER_m_888,Program Memory 32-bit word" line.long 0xCE8 "IME3_PROGRAMBUFFER_m_889,Program Memory 32-bit word" line.long 0xCEC "IME3_PROGRAMBUFFER_m_890,Program Memory 32-bit word" line.long 0xCF0 "IME3_PROGRAMBUFFER_m_891,Program Memory 32-bit word" line.long 0xCF4 "IME3_PROGRAMBUFFER_m_892,Program Memory 32-bit word" line.long 0xCF8 "IME3_PROGRAMBUFFER_m_893,Program Memory 32-bit word" line.long 0xCFC "IME3_PROGRAMBUFFER_m_894,Program Memory 32-bit word" line.long 0xD00 "IME3_PROGRAMBUFFER_m_895,Program Memory 32-bit word" line.long 0xD04 "IME3_PROGRAMBUFFER_m_896,Program Memory 32-bit word" line.long 0xD08 "IME3_PROGRAMBUFFER_m_897,Program Memory 32-bit word" line.long 0xD0C "IME3_PROGRAMBUFFER_m_898,Program Memory 32-bit word" line.long 0xD10 "IME3_PROGRAMBUFFER_m_899,Program Memory 32-bit word" line.long 0xD14 "IME3_PROGRAMBUFFER_m_900,Program Memory 32-bit word" line.long 0xD18 "IME3_PROGRAMBUFFER_m_901,Program Memory 32-bit word" line.long 0xD1C "IME3_PROGRAMBUFFER_m_902,Program Memory 32-bit word" line.long 0xD20 "IME3_PROGRAMBUFFER_m_903,Program Memory 32-bit word" line.long 0xD24 "IME3_PROGRAMBUFFER_m_904,Program Memory 32-bit word" line.long 0xD28 "IME3_PROGRAMBUFFER_m_905,Program Memory 32-bit word" line.long 0xD2C "IME3_PROGRAMBUFFER_m_906,Program Memory 32-bit word" line.long 0xD30 "IME3_PROGRAMBUFFER_m_907,Program Memory 32-bit word" line.long 0xD34 "IME3_PROGRAMBUFFER_m_908,Program Memory 32-bit word" line.long 0xD38 "IME3_PROGRAMBUFFER_m_909,Program Memory 32-bit word" line.long 0xD3C "IME3_PROGRAMBUFFER_m_910,Program Memory 32-bit word" line.long 0xD40 "IME3_PROGRAMBUFFER_m_911,Program Memory 32-bit word" line.long 0xD44 "IME3_PROGRAMBUFFER_m_912,Program Memory 32-bit word" line.long 0xD48 "IME3_PROGRAMBUFFER_m_913,Program Memory 32-bit word" line.long 0xD4C "IME3_PROGRAMBUFFER_m_914,Program Memory 32-bit word" line.long 0xD50 "IME3_PROGRAMBUFFER_m_915,Program Memory 32-bit word" line.long 0xD54 "IME3_PROGRAMBUFFER_m_916,Program Memory 32-bit word" line.long 0xD58 "IME3_PROGRAMBUFFER_m_917,Program Memory 32-bit word" line.long 0xD5C "IME3_PROGRAMBUFFER_m_918,Program Memory 32-bit word" line.long 0xD60 "IME3_PROGRAMBUFFER_m_919,Program Memory 32-bit word" line.long 0xD64 "IME3_PROGRAMBUFFER_m_920,Program Memory 32-bit word" line.long 0xD68 "IME3_PROGRAMBUFFER_m_921,Program Memory 32-bit word" line.long 0xD6C "IME3_PROGRAMBUFFER_m_922,Program Memory 32-bit word" line.long 0xD70 "IME3_PROGRAMBUFFER_m_923,Program Memory 32-bit word" line.long 0xD74 "IME3_PROGRAMBUFFER_m_924,Program Memory 32-bit word" line.long 0xD78 "IME3_PROGRAMBUFFER_m_925,Program Memory 32-bit word" line.long 0xD7C "IME3_PROGRAMBUFFER_m_926,Program Memory 32-bit word" line.long 0xD80 "IME3_PROGRAMBUFFER_m_927,Program Memory 32-bit word" line.long 0xD84 "IME3_PROGRAMBUFFER_m_928,Program Memory 32-bit word" line.long 0xD88 "IME3_PROGRAMBUFFER_m_929,Program Memory 32-bit word" line.long 0xD8C "IME3_PROGRAMBUFFER_m_930,Program Memory 32-bit word" line.long 0xD90 "IME3_PROGRAMBUFFER_m_931,Program Memory 32-bit word" line.long 0xD94 "IME3_PROGRAMBUFFER_m_932,Program Memory 32-bit word" line.long 0xD98 "IME3_PROGRAMBUFFER_m_933,Program Memory 32-bit word" line.long 0xD9C "IME3_PROGRAMBUFFER_m_934,Program Memory 32-bit word" line.long 0xDA0 "IME3_PROGRAMBUFFER_m_935,Program Memory 32-bit word" line.long 0xDA4 "IME3_PROGRAMBUFFER_m_936,Program Memory 32-bit word" line.long 0xDA8 "IME3_PROGRAMBUFFER_m_937,Program Memory 32-bit word" line.long 0xDAC "IME3_PROGRAMBUFFER_m_938,Program Memory 32-bit word" line.long 0xDB0 "IME3_PROGRAMBUFFER_m_939,Program Memory 32-bit word" line.long 0xDB4 "IME3_PROGRAMBUFFER_m_940,Program Memory 32-bit word" line.long 0xDB8 "IME3_PROGRAMBUFFER_m_941,Program Memory 32-bit word" line.long 0xDBC "IME3_PROGRAMBUFFER_m_942,Program Memory 32-bit word" line.long 0xDC0 "IME3_PROGRAMBUFFER_m_943,Program Memory 32-bit word" line.long 0xDC4 "IME3_PROGRAMBUFFER_m_944,Program Memory 32-bit word" line.long 0xDC8 "IME3_PROGRAMBUFFER_m_945,Program Memory 32-bit word" line.long 0xDCC "IME3_PROGRAMBUFFER_m_946,Program Memory 32-bit word" line.long 0xDD0 "IME3_PROGRAMBUFFER_m_947,Program Memory 32-bit word" line.long 0xDD4 "IME3_PROGRAMBUFFER_m_948,Program Memory 32-bit word" line.long 0xDD8 "IME3_PROGRAMBUFFER_m_949,Program Memory 32-bit word" line.long 0xDDC "IME3_PROGRAMBUFFER_m_950,Program Memory 32-bit word" line.long 0xDE0 "IME3_PROGRAMBUFFER_m_951,Program Memory 32-bit word" line.long 0xDE4 "IME3_PROGRAMBUFFER_m_952,Program Memory 32-bit word" line.long 0xDE8 "IME3_PROGRAMBUFFER_m_953,Program Memory 32-bit word" line.long 0xDEC "IME3_PROGRAMBUFFER_m_954,Program Memory 32-bit word" line.long 0xDF0 "IME3_PROGRAMBUFFER_m_955,Program Memory 32-bit word" line.long 0xDF4 "IME3_PROGRAMBUFFER_m_956,Program Memory 32-bit word" line.long 0xDF8 "IME3_PROGRAMBUFFER_m_957,Program Memory 32-bit word" line.long 0xDFC "IME3_PROGRAMBUFFER_m_958,Program Memory 32-bit word" line.long 0xE00 "IME3_PROGRAMBUFFER_m_959,Program Memory 32-bit word" line.long 0xE04 "IME3_PROGRAMBUFFER_m_960,Program Memory 32-bit word" line.long 0xE08 "IME3_PROGRAMBUFFER_m_961,Program Memory 32-bit word" line.long 0xE0C "IME3_PROGRAMBUFFER_m_962,Program Memory 32-bit word" line.long 0xE10 "IME3_PROGRAMBUFFER_m_963,Program Memory 32-bit word" line.long 0xE14 "IME3_PROGRAMBUFFER_m_964,Program Memory 32-bit word" line.long 0xE18 "IME3_PROGRAMBUFFER_m_965,Program Memory 32-bit word" line.long 0xE1C "IME3_PROGRAMBUFFER_m_966,Program Memory 32-bit word" line.long 0xE20 "IME3_PROGRAMBUFFER_m_967,Program Memory 32-bit word" line.long 0xE24 "IME3_PROGRAMBUFFER_m_968,Program Memory 32-bit word" line.long 0xE28 "IME3_PROGRAMBUFFER_m_969,Program Memory 32-bit word" line.long 0xE2C "IME3_PROGRAMBUFFER_m_970,Program Memory 32-bit word" line.long 0xE30 "IME3_PROGRAMBUFFER_m_971,Program Memory 32-bit word" line.long 0xE34 "IME3_PROGRAMBUFFER_m_972,Program Memory 32-bit word" line.long 0xE38 "IME3_PROGRAMBUFFER_m_973,Program Memory 32-bit word" line.long 0xE3C "IME3_PROGRAMBUFFER_m_974,Program Memory 32-bit word" line.long 0xE40 "IME3_PROGRAMBUFFER_m_975,Program Memory 32-bit word" line.long 0xE44 "IME3_PROGRAMBUFFER_m_976,Program Memory 32-bit word" line.long 0xE48 "IME3_PROGRAMBUFFER_m_977,Program Memory 32-bit word" line.long 0xE4C "IME3_PROGRAMBUFFER_m_978,Program Memory 32-bit word" line.long 0xE50 "IME3_PROGRAMBUFFER_m_979,Program Memory 32-bit word" line.long 0xE54 "IME3_PROGRAMBUFFER_m_980,Program Memory 32-bit word" line.long 0xE58 "IME3_PROGRAMBUFFER_m_981,Program Memory 32-bit word" line.long 0xE5C "IME3_PROGRAMBUFFER_m_982,Program Memory 32-bit word" line.long 0xE60 "IME3_PROGRAMBUFFER_m_983,Program Memory 32-bit word" line.long 0xE64 "IME3_PROGRAMBUFFER_m_984,Program Memory 32-bit word" line.long 0xE68 "IME3_PROGRAMBUFFER_m_985,Program Memory 32-bit word" line.long 0xE6C "IME3_PROGRAMBUFFER_m_986,Program Memory 32-bit word" line.long 0xE70 "IME3_PROGRAMBUFFER_m_987,Program Memory 32-bit word" line.long 0xE74 "IME3_PROGRAMBUFFER_m_988,Program Memory 32-bit word" line.long 0xE78 "IME3_PROGRAMBUFFER_m_989,Program Memory 32-bit word" line.long 0xE7C "IME3_PROGRAMBUFFER_m_990,Program Memory 32-bit word" line.long 0xE80 "IME3_PROGRAMBUFFER_m_991,Program Memory 32-bit word" line.long 0xE84 "IME3_PROGRAMBUFFER_m_992,Program Memory 32-bit word" line.long 0xE88 "IME3_PROGRAMBUFFER_m_993,Program Memory 32-bit word" line.long 0xE8C "IME3_PROGRAMBUFFER_m_994,Program Memory 32-bit word" line.long 0xE90 "IME3_PROGRAMBUFFER_m_995,Program Memory 32-bit word" line.long 0xE94 "IME3_PROGRAMBUFFER_m_996,Program Memory 32-bit word" line.long 0xE98 "IME3_PROGRAMBUFFER_m_997,Program Memory 32-bit word" line.long 0xE9C "IME3_PROGRAMBUFFER_m_998,Program Memory 32-bit word" line.long 0xEA0 "IME3_PROGRAMBUFFER_m_999,Program Memory 32-bit word" line.long 0xEA4 "IME3_PROGRAMBUFFER_m_1000,Program Memory 32-bit word" line.long 0xEA8 "IME3_PROGRAMBUFFER_m_1001,Program Memory 32-bit word" line.long 0xEAC "IME3_PROGRAMBUFFER_m_1002,Program Memory 32-bit word" line.long 0xEB0 "IME3_PROGRAMBUFFER_m_1003,Program Memory 32-bit word" line.long 0xEB4 "IME3_PROGRAMBUFFER_m_1004,Program Memory 32-bit word" line.long 0xEB8 "IME3_PROGRAMBUFFER_m_1005,Program Memory 32-bit word" line.long 0xEBC "IME3_PROGRAMBUFFER_m_1006,Program Memory 32-bit word" line.long 0xEC0 "IME3_PROGRAMBUFFER_m_1007,Program Memory 32-bit word" line.long 0xEC4 "IME3_PROGRAMBUFFER_m_1008,Program Memory 32-bit word" line.long 0xEC8 "IME3_PROGRAMBUFFER_m_1009,Program Memory 32-bit word" line.long 0xECC "IME3_PROGRAMBUFFER_m_1010,Program Memory 32-bit word" line.long 0xED0 "IME3_PROGRAMBUFFER_m_1011,Program Memory 32-bit word" line.long 0xED4 "IME3_PROGRAMBUFFER_m_1012,Program Memory 32-bit word" line.long 0xED8 "IME3_PROGRAMBUFFER_m_1013,Program Memory 32-bit word" line.long 0xEDC "IME3_PROGRAMBUFFER_m_1014,Program Memory 32-bit word" line.long 0xEE0 "IME3_PROGRAMBUFFER_m_1015,Program Memory 32-bit word" line.long 0xEE4 "IME3_PROGRAMBUFFER_m_1016,Program Memory 32-bit word" line.long 0xEE8 "IME3_PROGRAMBUFFER_m_1017,Program Memory 32-bit word" line.long 0xEEC "IME3_PROGRAMBUFFER_m_1018,Program Memory 32-bit word" line.long 0xEF0 "IME3_PROGRAMBUFFER_m_1019,Program Memory 32-bit word" line.long 0xEF4 "IME3_PROGRAMBUFFER_m_1020,Program Memory 32-bit word" line.long 0xEF8 "IME3_PROGRAMBUFFER_m_1021,Program Memory 32-bit word" line.long 0xEFC "IME3_PROGRAMBUFFER_m_1022,Program Memory 32-bit word" line.long 0xF00 "IME3_PROGRAMBUFFER_m_1023,Program Memory 32-bit word" line.long 0xF04 "IME3_PROGRAMBUFFER_m_1024,Program Memory 32-bit word" line.long 0xF08 "IME3_PROGRAMBUFFER_m_1025,Program Memory 32-bit word" line.long 0xF0C "IME3_PROGRAMBUFFER_m_1026,Program Memory 32-bit word" line.long 0xF10 "IME3_PROGRAMBUFFER_m_1027,Program Memory 32-bit word" line.long 0xF14 "IME3_PROGRAMBUFFER_m_1028,Program Memory 32-bit word" line.long 0xF18 "IME3_PROGRAMBUFFER_m_1029,Program Memory 32-bit word" line.long 0xF1C "IME3_PROGRAMBUFFER_m_1030,Program Memory 32-bit word" line.long 0xF20 "IME3_PROGRAMBUFFER_m_1031,Program Memory 32-bit word" line.long 0xF24 "IME3_PROGRAMBUFFER_m_1032,Program Memory 32-bit word" line.long 0xF28 "IME3_PROGRAMBUFFER_m_1033,Program Memory 32-bit word" line.long 0xF2C "IME3_PROGRAMBUFFER_m_1034,Program Memory 32-bit word" line.long 0xF30 "IME3_PROGRAMBUFFER_m_1035,Program Memory 32-bit word" line.long 0xF34 "IME3_PROGRAMBUFFER_m_1036,Program Memory 32-bit word" line.long 0xF38 "IME3_PROGRAMBUFFER_m_1037,Program Memory 32-bit word" line.long 0xF3C "IME3_PROGRAMBUFFER_m_1038,Program Memory 32-bit word" line.long 0xF40 "IME3_PROGRAMBUFFER_m_1039,Program Memory 32-bit word" line.long 0xF44 "IME3_PROGRAMBUFFER_m_1040,Program Memory 32-bit word" line.long 0xF48 "IME3_PROGRAMBUFFER_m_1041,Program Memory 32-bit word" line.long 0xF4C "IME3_PROGRAMBUFFER_m_1042,Program Memory 32-bit word" line.long 0xF50 "IME3_PROGRAMBUFFER_m_1043,Program Memory 32-bit word" line.long 0xF54 "IME3_PROGRAMBUFFER_m_1044,Program Memory 32-bit word" line.long 0xF58 "IME3_PROGRAMBUFFER_m_1045,Program Memory 32-bit word" line.long 0xF5C "IME3_PROGRAMBUFFER_m_1046,Program Memory 32-bit word" line.long 0xF60 "IME3_PROGRAMBUFFER_m_1047,Program Memory 32-bit word" line.long 0xF64 "IME3_PROGRAMBUFFER_m_1048,Program Memory 32-bit word" line.long 0xF68 "IME3_PROGRAMBUFFER_m_1049,Program Memory 32-bit word" line.long 0xF6C "IME3_PROGRAMBUFFER_m_1050,Program Memory 32-bit word" line.long 0xF70 "IME3_PROGRAMBUFFER_m_1051,Program Memory 32-bit word" line.long 0xF74 "IME3_PROGRAMBUFFER_m_1052,Program Memory 32-bit word" line.long 0xF78 "IME3_PROGRAMBUFFER_m_1053,Program Memory 32-bit word" line.long 0xF7C "IME3_PROGRAMBUFFER_m_1054,Program Memory 32-bit word" line.long 0xF80 "IME3_PROGRAMBUFFER_m_1055,Program Memory 32-bit word" line.long 0xF84 "IME3_PROGRAMBUFFER_m_1056,Program Memory 32-bit word" line.long 0xF88 "IME3_PROGRAMBUFFER_m_1057,Program Memory 32-bit word" line.long 0xF8C "IME3_PROGRAMBUFFER_m_1058,Program Memory 32-bit word" line.long 0xF90 "IME3_PROGRAMBUFFER_m_1059,Program Memory 32-bit word" line.long 0xF94 "IME3_PROGRAMBUFFER_m_1060,Program Memory 32-bit word" line.long 0xF98 "IME3_PROGRAMBUFFER_m_1061,Program Memory 32-bit word" line.long 0xF9C "IME3_PROGRAMBUFFER_m_1062,Program Memory 32-bit word" line.long 0xFA0 "IME3_PROGRAMBUFFER_m_1063,Program Memory 32-bit word" line.long 0xFA4 "IME3_PROGRAMBUFFER_m_1064,Program Memory 32-bit word" line.long 0xFA8 "IME3_PROGRAMBUFFER_m_1065,Program Memory 32-bit word" line.long 0xFAC "IME3_PROGRAMBUFFER_m_1066,Program Memory 32-bit word" line.long 0xFB0 "IME3_PROGRAMBUFFER_m_1067,Program Memory 32-bit word" line.long 0xFB4 "IME3_PROGRAMBUFFER_m_1068,Program Memory 32-bit word" line.long 0xFB8 "IME3_PROGRAMBUFFER_m_1069,Program Memory 32-bit word" line.long 0xFBC "IME3_PROGRAMBUFFER_m_1070,Program Memory 32-bit word" line.long 0xFC0 "IME3_PROGRAMBUFFER_m_1071,Program Memory 32-bit word" line.long 0xFC4 "IME3_PROGRAMBUFFER_m_1072,Program Memory 32-bit word" line.long 0xFC8 "IME3_PROGRAMBUFFER_m_1073,Program Memory 32-bit word" line.long 0xFCC "IME3_PROGRAMBUFFER_m_1074,Program Memory 32-bit word" line.long 0xFD0 "IME3_PROGRAMBUFFER_m_1075,Program Memory 32-bit word" line.long 0xFD4 "IME3_PROGRAMBUFFER_m_1076,Program Memory 32-bit word" line.long 0xFD8 "IME3_PROGRAMBUFFER_m_1077,Program Memory 32-bit word" line.long 0xFDC "IME3_PROGRAMBUFFER_m_1078,Program Memory 32-bit word" line.long 0xFE0 "IME3_PROGRAMBUFFER_m_1079,Program Memory 32-bit word" line.long 0xFE4 "IME3_PROGRAMBUFFER_m_1080,Program Memory 32-bit word" line.long 0xFE8 "IME3_PROGRAMBUFFER_m_1081,Program Memory 32-bit word" line.long 0xFEC "IME3_PROGRAMBUFFER_m_1082,Program Memory 32-bit word" line.long 0xFF0 "IME3_PROGRAMBUFFER_m_1083,Program Memory 32-bit word" line.long 0xFF4 "IME3_PROGRAMBUFFER_m_1084,Program Memory 32-bit word" line.long 0xFF8 "IME3_PROGRAMBUFFER_m_1085,Program Memory 32-bit word" line.long 0xFFC "IME3_PROGRAMBUFFER_m_1086,Program Memory 32-bit word" group.long 0x30FC++0xF03 line.long 0x00 "IME3_PROGRAMBUFFER_m_1087,Program Memory 32-bit word" line.long 0x04 "IME3_PROGRAMBUFFER_m_1088,Program Memory 32-bit word" line.long 0x08 "IME3_PROGRAMBUFFER_m_1089,Program Memory 32-bit word" line.long 0x0C "IME3_PROGRAMBUFFER_m_1090,Program Memory 32-bit word" line.long 0x10 "IME3_PROGRAMBUFFER_m_1091,Program Memory 32-bit word" line.long 0x14 "IME3_PROGRAMBUFFER_m_1092,Program Memory 32-bit word" line.long 0x18 "IME3_PROGRAMBUFFER_m_1093,Program Memory 32-bit word" line.long 0x1C "IME3_PROGRAMBUFFER_m_1094,Program Memory 32-bit word" line.long 0x20 "IME3_PROGRAMBUFFER_m_1095,Program Memory 32-bit word" line.long 0x24 "IME3_PROGRAMBUFFER_m_1096,Program Memory 32-bit word" line.long 0x28 "IME3_PROGRAMBUFFER_m_1097,Program Memory 32-bit word" line.long 0x2C "IME3_PROGRAMBUFFER_m_1098,Program Memory 32-bit word" line.long 0x30 "IME3_PROGRAMBUFFER_m_1099,Program Memory 32-bit word" line.long 0x34 "IME3_PROGRAMBUFFER_m_1100,Program Memory 32-bit word" line.long 0x38 "IME3_PROGRAMBUFFER_m_1101,Program Memory 32-bit word" line.long 0x3C "IME3_PROGRAMBUFFER_m_1102,Program Memory 32-bit word" line.long 0x40 "IME3_PROGRAMBUFFER_m_1103,Program Memory 32-bit word" line.long 0x44 "IME3_PROGRAMBUFFER_m_1104,Program Memory 32-bit word" line.long 0x48 "IME3_PROGRAMBUFFER_m_1105,Program Memory 32-bit word" line.long 0x4C "IME3_PROGRAMBUFFER_m_1106,Program Memory 32-bit word" line.long 0x50 "IME3_PROGRAMBUFFER_m_1107,Program Memory 32-bit word" line.long 0x54 "IME3_PROGRAMBUFFER_m_1108,Program Memory 32-bit word" line.long 0x58 "IME3_PROGRAMBUFFER_m_1109,Program Memory 32-bit word" line.long 0x5C "IME3_PROGRAMBUFFER_m_1110,Program Memory 32-bit word" line.long 0x60 "IME3_PROGRAMBUFFER_m_1111,Program Memory 32-bit word" line.long 0x64 "IME3_PROGRAMBUFFER_m_1112,Program Memory 32-bit word" line.long 0x68 "IME3_PROGRAMBUFFER_m_1113,Program Memory 32-bit word" line.long 0x6C "IME3_PROGRAMBUFFER_m_1114,Program Memory 32-bit word" line.long 0x70 "IME3_PROGRAMBUFFER_m_1115,Program Memory 32-bit word" line.long 0x74 "IME3_PROGRAMBUFFER_m_1116,Program Memory 32-bit word" line.long 0x78 "IME3_PROGRAMBUFFER_m_1117,Program Memory 32-bit word" line.long 0x7C "IME3_PROGRAMBUFFER_m_1118,Program Memory 32-bit word" line.long 0x80 "IME3_PROGRAMBUFFER_m_1119,Program Memory 32-bit word" line.long 0x84 "IME3_PROGRAMBUFFER_m_1120,Program Memory 32-bit word" line.long 0x88 "IME3_PROGRAMBUFFER_m_1121,Program Memory 32-bit word" line.long 0x8C "IME3_PROGRAMBUFFER_m_1122,Program Memory 32-bit word" line.long 0x90 "IME3_PROGRAMBUFFER_m_1123,Program Memory 32-bit word" line.long 0x94 "IME3_PROGRAMBUFFER_m_1124,Program Memory 32-bit word" line.long 0x98 "IME3_PROGRAMBUFFER_m_1125,Program Memory 32-bit word" line.long 0x9C "IME3_PROGRAMBUFFER_m_1126,Program Memory 32-bit word" line.long 0xA0 "IME3_PROGRAMBUFFER_m_1127,Program Memory 32-bit word" line.long 0xA4 "IME3_PROGRAMBUFFER_m_1128,Program Memory 32-bit word" line.long 0xA8 "IME3_PROGRAMBUFFER_m_1129,Program Memory 32-bit word" line.long 0xAC "IME3_PROGRAMBUFFER_m_1130,Program Memory 32-bit word" line.long 0xB0 "IME3_PROGRAMBUFFER_m_1131,Program Memory 32-bit word" line.long 0xB4 "IME3_PROGRAMBUFFER_m_1132,Program Memory 32-bit word" line.long 0xB8 "IME3_PROGRAMBUFFER_m_1133,Program Memory 32-bit word" line.long 0xBC "IME3_PROGRAMBUFFER_m_1134,Program Memory 32-bit word" line.long 0xC0 "IME3_PROGRAMBUFFER_m_1135,Program Memory 32-bit word" line.long 0xC4 "IME3_PROGRAMBUFFER_m_1136,Program Memory 32-bit word" line.long 0xC8 "IME3_PROGRAMBUFFER_m_1137,Program Memory 32-bit word" line.long 0xCC "IME3_PROGRAMBUFFER_m_1138,Program Memory 32-bit word" line.long 0xD0 "IME3_PROGRAMBUFFER_m_1139,Program Memory 32-bit word" line.long 0xD4 "IME3_PROGRAMBUFFER_m_1140,Program Memory 32-bit word" line.long 0xD8 "IME3_PROGRAMBUFFER_m_1141,Program Memory 32-bit word" line.long 0xDC "IME3_PROGRAMBUFFER_m_1142,Program Memory 32-bit word" line.long 0xE0 "IME3_PROGRAMBUFFER_m_1143,Program Memory 32-bit word" line.long 0xE4 "IME3_PROGRAMBUFFER_m_1144,Program Memory 32-bit word" line.long 0xE8 "IME3_PROGRAMBUFFER_m_1145,Program Memory 32-bit word" line.long 0xEC "IME3_PROGRAMBUFFER_m_1146,Program Memory 32-bit word" line.long 0xF0 "IME3_PROGRAMBUFFER_m_1147,Program Memory 32-bit word" line.long 0xF4 "IME3_PROGRAMBUFFER_m_1148,Program Memory 32-bit word" line.long 0xF8 "IME3_PROGRAMBUFFER_m_1149,Program Memory 32-bit word" line.long 0xFC "IME3_PROGRAMBUFFER_m_1150,Program Memory 32-bit word" line.long 0x100 "IME3_PROGRAMBUFFER_m_1151,Program Memory 32-bit word" line.long 0x104 "IME3_PROGRAMBUFFER_m_1152,Program Memory 32-bit word" line.long 0x108 "IME3_PROGRAMBUFFER_m_1153,Program Memory 32-bit word" line.long 0x10C "IME3_PROGRAMBUFFER_m_1154,Program Memory 32-bit word" line.long 0x110 "IME3_PROGRAMBUFFER_m_1155,Program Memory 32-bit word" line.long 0x114 "IME3_PROGRAMBUFFER_m_1156,Program Memory 32-bit word" line.long 0x118 "IME3_PROGRAMBUFFER_m_1157,Program Memory 32-bit word" line.long 0x11C "IME3_PROGRAMBUFFER_m_1158,Program Memory 32-bit word" line.long 0x120 "IME3_PROGRAMBUFFER_m_1159,Program Memory 32-bit word" line.long 0x124 "IME3_PROGRAMBUFFER_m_1160,Program Memory 32-bit word" line.long 0x128 "IME3_PROGRAMBUFFER_m_1161,Program Memory 32-bit word" line.long 0x12C "IME3_PROGRAMBUFFER_m_1162,Program Memory 32-bit word" line.long 0x130 "IME3_PROGRAMBUFFER_m_1163,Program Memory 32-bit word" line.long 0x134 "IME3_PROGRAMBUFFER_m_1164,Program Memory 32-bit word" line.long 0x138 "IME3_PROGRAMBUFFER_m_1165,Program Memory 32-bit word" line.long 0x13C "IME3_PROGRAMBUFFER_m_1166,Program Memory 32-bit word" line.long 0x140 "IME3_PROGRAMBUFFER_m_1167,Program Memory 32-bit word" line.long 0x144 "IME3_PROGRAMBUFFER_m_1168,Program Memory 32-bit word" line.long 0x148 "IME3_PROGRAMBUFFER_m_1169,Program Memory 32-bit word" line.long 0x14C "IME3_PROGRAMBUFFER_m_1170,Program Memory 32-bit word" line.long 0x150 "IME3_PROGRAMBUFFER_m_1171,Program Memory 32-bit word" line.long 0x154 "IME3_PROGRAMBUFFER_m_1172,Program Memory 32-bit word" line.long 0x158 "IME3_PROGRAMBUFFER_m_1173,Program Memory 32-bit word" line.long 0x15C "IME3_PROGRAMBUFFER_m_1174,Program Memory 32-bit word" line.long 0x160 "IME3_PROGRAMBUFFER_m_1175,Program Memory 32-bit word" line.long 0x164 "IME3_PROGRAMBUFFER_m_1176,Program Memory 32-bit word" line.long 0x168 "IME3_PROGRAMBUFFER_m_1177,Program Memory 32-bit word" line.long 0x16C "IME3_PROGRAMBUFFER_m_1178,Program Memory 32-bit word" line.long 0x170 "IME3_PROGRAMBUFFER_m_1179,Program Memory 32-bit word" line.long 0x174 "IME3_PROGRAMBUFFER_m_1180,Program Memory 32-bit word" line.long 0x178 "IME3_PROGRAMBUFFER_m_1181,Program Memory 32-bit word" line.long 0x17C "IME3_PROGRAMBUFFER_m_1182,Program Memory 32-bit word" line.long 0x180 "IME3_PROGRAMBUFFER_m_1183,Program Memory 32-bit word" line.long 0x184 "IME3_PROGRAMBUFFER_m_1184,Program Memory 32-bit word" line.long 0x188 "IME3_PROGRAMBUFFER_m_1185,Program Memory 32-bit word" line.long 0x18C "IME3_PROGRAMBUFFER_m_1186,Program Memory 32-bit word" line.long 0x190 "IME3_PROGRAMBUFFER_m_1187,Program Memory 32-bit word" line.long 0x194 "IME3_PROGRAMBUFFER_m_1188,Program Memory 32-bit word" line.long 0x198 "IME3_PROGRAMBUFFER_m_1189,Program Memory 32-bit word" line.long 0x19C "IME3_PROGRAMBUFFER_m_1190,Program Memory 32-bit word" line.long 0x1A0 "IME3_PROGRAMBUFFER_m_1191,Program Memory 32-bit word" line.long 0x1A4 "IME3_PROGRAMBUFFER_m_1192,Program Memory 32-bit word" line.long 0x1A8 "IME3_PROGRAMBUFFER_m_1193,Program Memory 32-bit word" line.long 0x1AC "IME3_PROGRAMBUFFER_m_1194,Program Memory 32-bit word" line.long 0x1B0 "IME3_PROGRAMBUFFER_m_1195,Program Memory 32-bit word" line.long 0x1B4 "IME3_PROGRAMBUFFER_m_1196,Program Memory 32-bit word" line.long 0x1B8 "IME3_PROGRAMBUFFER_m_1197,Program Memory 32-bit word" line.long 0x1BC "IME3_PROGRAMBUFFER_m_1198,Program Memory 32-bit word" line.long 0x1C0 "IME3_PROGRAMBUFFER_m_1199,Program Memory 32-bit word" line.long 0x1C4 "IME3_PROGRAMBUFFER_m_1200,Program Memory 32-bit word" line.long 0x1C8 "IME3_PROGRAMBUFFER_m_1201,Program Memory 32-bit word" line.long 0x1CC "IME3_PROGRAMBUFFER_m_1202,Program Memory 32-bit word" line.long 0x1D0 "IME3_PROGRAMBUFFER_m_1203,Program Memory 32-bit word" line.long 0x1D4 "IME3_PROGRAMBUFFER_m_1204,Program Memory 32-bit word" line.long 0x1D8 "IME3_PROGRAMBUFFER_m_1205,Program Memory 32-bit word" line.long 0x1DC "IME3_PROGRAMBUFFER_m_1206,Program Memory 32-bit word" line.long 0x1E0 "IME3_PROGRAMBUFFER_m_1207,Program Memory 32-bit word" line.long 0x1E4 "IME3_PROGRAMBUFFER_m_1208,Program Memory 32-bit word" line.long 0x1E8 "IME3_PROGRAMBUFFER_m_1209,Program Memory 32-bit word" line.long 0x1EC "IME3_PROGRAMBUFFER_m_1210,Program Memory 32-bit word" line.long 0x1F0 "IME3_PROGRAMBUFFER_m_1211,Program Memory 32-bit word" line.long 0x1F4 "IME3_PROGRAMBUFFER_m_1212,Program Memory 32-bit word" line.long 0x1F8 "IME3_PROGRAMBUFFER_m_1213,Program Memory 32-bit word" line.long 0x1FC "IME3_PROGRAMBUFFER_m_1214,Program Memory 32-bit word" line.long 0x200 "IME3_PROGRAMBUFFER_m_1215,Program Memory 32-bit word" line.long 0x204 "IME3_PROGRAMBUFFER_m_1216,Program Memory 32-bit word" line.long 0x208 "IME3_PROGRAMBUFFER_m_1217,Program Memory 32-bit word" line.long 0x20C "IME3_PROGRAMBUFFER_m_1218,Program Memory 32-bit word" line.long 0x210 "IME3_PROGRAMBUFFER_m_1219,Program Memory 32-bit word" line.long 0x214 "IME3_PROGRAMBUFFER_m_1220,Program Memory 32-bit word" line.long 0x218 "IME3_PROGRAMBUFFER_m_1221,Program Memory 32-bit word" line.long 0x21C "IME3_PROGRAMBUFFER_m_1222,Program Memory 32-bit word" line.long 0x220 "IME3_PROGRAMBUFFER_m_1223,Program Memory 32-bit word" line.long 0x224 "IME3_PROGRAMBUFFER_m_1224,Program Memory 32-bit word" line.long 0x228 "IME3_PROGRAMBUFFER_m_1225,Program Memory 32-bit word" line.long 0x22C "IME3_PROGRAMBUFFER_m_1226,Program Memory 32-bit word" line.long 0x230 "IME3_PROGRAMBUFFER_m_1227,Program Memory 32-bit word" line.long 0x234 "IME3_PROGRAMBUFFER_m_1228,Program Memory 32-bit word" line.long 0x238 "IME3_PROGRAMBUFFER_m_1229,Program Memory 32-bit word" line.long 0x23C "IME3_PROGRAMBUFFER_m_1230,Program Memory 32-bit word" line.long 0x240 "IME3_PROGRAMBUFFER_m_1231,Program Memory 32-bit word" line.long 0x244 "IME3_PROGRAMBUFFER_m_1232,Program Memory 32-bit word" line.long 0x248 "IME3_PROGRAMBUFFER_m_1233,Program Memory 32-bit word" line.long 0x24C "IME3_PROGRAMBUFFER_m_1234,Program Memory 32-bit word" line.long 0x250 "IME3_PROGRAMBUFFER_m_1235,Program Memory 32-bit word" line.long 0x254 "IME3_PROGRAMBUFFER_m_1236,Program Memory 32-bit word" line.long 0x258 "IME3_PROGRAMBUFFER_m_1237,Program Memory 32-bit word" line.long 0x25C "IME3_PROGRAMBUFFER_m_1238,Program Memory 32-bit word" line.long 0x260 "IME3_PROGRAMBUFFER_m_1239,Program Memory 32-bit word" line.long 0x264 "IME3_PROGRAMBUFFER_m_1240,Program Memory 32-bit word" line.long 0x268 "IME3_PROGRAMBUFFER_m_1241,Program Memory 32-bit word" line.long 0x26C "IME3_PROGRAMBUFFER_m_1242,Program Memory 32-bit word" line.long 0x270 "IME3_PROGRAMBUFFER_m_1243,Program Memory 32-bit word" line.long 0x274 "IME3_PROGRAMBUFFER_m_1244,Program Memory 32-bit word" line.long 0x278 "IME3_PROGRAMBUFFER_m_1245,Program Memory 32-bit word" line.long 0x27C "IME3_PROGRAMBUFFER_m_1246,Program Memory 32-bit word" line.long 0x280 "IME3_PROGRAMBUFFER_m_1247,Program Memory 32-bit word" line.long 0x284 "IME3_PROGRAMBUFFER_m_1248,Program Memory 32-bit word" line.long 0x288 "IME3_PROGRAMBUFFER_m_1249,Program Memory 32-bit word" line.long 0x28C "IME3_PROGRAMBUFFER_m_1250,Program Memory 32-bit word" line.long 0x290 "IME3_PROGRAMBUFFER_m_1251,Program Memory 32-bit word" line.long 0x294 "IME3_PROGRAMBUFFER_m_1252,Program Memory 32-bit word" line.long 0x298 "IME3_PROGRAMBUFFER_m_1253,Program Memory 32-bit word" line.long 0x29C "IME3_PROGRAMBUFFER_m_1254,Program Memory 32-bit word" line.long 0x2A0 "IME3_PROGRAMBUFFER_m_1255,Program Memory 32-bit word" line.long 0x2A4 "IME3_PROGRAMBUFFER_m_1256,Program Memory 32-bit word" line.long 0x2A8 "IME3_PROGRAMBUFFER_m_1257,Program Memory 32-bit word" line.long 0x2AC "IME3_PROGRAMBUFFER_m_1258,Program Memory 32-bit word" line.long 0x2B0 "IME3_PROGRAMBUFFER_m_1259,Program Memory 32-bit word" line.long 0x2B4 "IME3_PROGRAMBUFFER_m_1260,Program Memory 32-bit word" line.long 0x2B8 "IME3_PROGRAMBUFFER_m_1261,Program Memory 32-bit word" line.long 0x2BC "IME3_PROGRAMBUFFER_m_1262,Program Memory 32-bit word" line.long 0x2C0 "IME3_PROGRAMBUFFER_m_1263,Program Memory 32-bit word" line.long 0x2C4 "IME3_PROGRAMBUFFER_m_1264,Program Memory 32-bit word" line.long 0x2C8 "IME3_PROGRAMBUFFER_m_1265,Program Memory 32-bit word" line.long 0x2CC "IME3_PROGRAMBUFFER_m_1266,Program Memory 32-bit word" line.long 0x2D0 "IME3_PROGRAMBUFFER_m_1267,Program Memory 32-bit word" line.long 0x2D4 "IME3_PROGRAMBUFFER_m_1268,Program Memory 32-bit word" line.long 0x2D8 "IME3_PROGRAMBUFFER_m_1269,Program Memory 32-bit word" line.long 0x2DC "IME3_PROGRAMBUFFER_m_1270,Program Memory 32-bit word" line.long 0x2E0 "IME3_PROGRAMBUFFER_m_1271,Program Memory 32-bit word" line.long 0x2E4 "IME3_PROGRAMBUFFER_m_1272,Program Memory 32-bit word" line.long 0x2E8 "IME3_PROGRAMBUFFER_m_1273,Program Memory 32-bit word" line.long 0x2EC "IME3_PROGRAMBUFFER_m_1274,Program Memory 32-bit word" line.long 0x2F0 "IME3_PROGRAMBUFFER_m_1275,Program Memory 32-bit word" line.long 0x2F4 "IME3_PROGRAMBUFFER_m_1276,Program Memory 32-bit word" line.long 0x2F8 "IME3_PROGRAMBUFFER_m_1277,Program Memory 32-bit word" line.long 0x2FC "IME3_PROGRAMBUFFER_m_1278,Program Memory 32-bit word" line.long 0x300 "IME3_PROGRAMBUFFER_m_1279,Program Memory 32-bit word" line.long 0x304 "IME3_PROGRAMBUFFER_m_1280,Program Memory 32-bit word" line.long 0x308 "IME3_PROGRAMBUFFER_m_1281,Program Memory 32-bit word" line.long 0x30C "IME3_PROGRAMBUFFER_m_1282,Program Memory 32-bit word" line.long 0x310 "IME3_PROGRAMBUFFER_m_1283,Program Memory 32-bit word" line.long 0x314 "IME3_PROGRAMBUFFER_m_1284,Program Memory 32-bit word" line.long 0x318 "IME3_PROGRAMBUFFER_m_1285,Program Memory 32-bit word" line.long 0x31C "IME3_PROGRAMBUFFER_m_1286,Program Memory 32-bit word" line.long 0x320 "IME3_PROGRAMBUFFER_m_1287,Program Memory 32-bit word" line.long 0x324 "IME3_PROGRAMBUFFER_m_1288,Program Memory 32-bit word" line.long 0x328 "IME3_PROGRAMBUFFER_m_1289,Program Memory 32-bit word" line.long 0x32C "IME3_PROGRAMBUFFER_m_1290,Program Memory 32-bit word" line.long 0x330 "IME3_PROGRAMBUFFER_m_1291,Program Memory 32-bit word" line.long 0x334 "IME3_PROGRAMBUFFER_m_1292,Program Memory 32-bit word" line.long 0x338 "IME3_PROGRAMBUFFER_m_1293,Program Memory 32-bit word" line.long 0x33C "IME3_PROGRAMBUFFER_m_1294,Program Memory 32-bit word" line.long 0x340 "IME3_PROGRAMBUFFER_m_1295,Program Memory 32-bit word" line.long 0x344 "IME3_PROGRAMBUFFER_m_1296,Program Memory 32-bit word" line.long 0x348 "IME3_PROGRAMBUFFER_m_1297,Program Memory 32-bit word" line.long 0x34C "IME3_PROGRAMBUFFER_m_1298,Program Memory 32-bit word" line.long 0x350 "IME3_PROGRAMBUFFER_m_1299,Program Memory 32-bit word" line.long 0x354 "IME3_PROGRAMBUFFER_m_1300,Program Memory 32-bit word" line.long 0x358 "IME3_PROGRAMBUFFER_m_1301,Program Memory 32-bit word" line.long 0x35C "IME3_PROGRAMBUFFER_m_1302,Program Memory 32-bit word" line.long 0x360 "IME3_PROGRAMBUFFER_m_1303,Program Memory 32-bit word" line.long 0x364 "IME3_PROGRAMBUFFER_m_1304,Program Memory 32-bit word" line.long 0x368 "IME3_PROGRAMBUFFER_m_1305,Program Memory 32-bit word" line.long 0x36C "IME3_PROGRAMBUFFER_m_1306,Program Memory 32-bit word" line.long 0x370 "IME3_PROGRAMBUFFER_m_1307,Program Memory 32-bit word" line.long 0x374 "IME3_PROGRAMBUFFER_m_1308,Program Memory 32-bit word" line.long 0x378 "IME3_PROGRAMBUFFER_m_1309,Program Memory 32-bit word" line.long 0x37C "IME3_PROGRAMBUFFER_m_1310,Program Memory 32-bit word" line.long 0x380 "IME3_PROGRAMBUFFER_m_1311,Program Memory 32-bit word" line.long 0x384 "IME3_PROGRAMBUFFER_m_1312,Program Memory 32-bit word" line.long 0x388 "IME3_PROGRAMBUFFER_m_1313,Program Memory 32-bit word" line.long 0x38C "IME3_PROGRAMBUFFER_m_1314,Program Memory 32-bit word" line.long 0x390 "IME3_PROGRAMBUFFER_m_1315,Program Memory 32-bit word" line.long 0x394 "IME3_PROGRAMBUFFER_m_1316,Program Memory 32-bit word" line.long 0x398 "IME3_PROGRAMBUFFER_m_1317,Program Memory 32-bit word" line.long 0x39C "IME3_PROGRAMBUFFER_m_1318,Program Memory 32-bit word" line.long 0x3A0 "IME3_PROGRAMBUFFER_m_1319,Program Memory 32-bit word" line.long 0x3A4 "IME3_PROGRAMBUFFER_m_1320,Program Memory 32-bit word" line.long 0x3A8 "IME3_PROGRAMBUFFER_m_1321,Program Memory 32-bit word" line.long 0x3AC "IME3_PROGRAMBUFFER_m_1322,Program Memory 32-bit word" line.long 0x3B0 "IME3_PROGRAMBUFFER_m_1323,Program Memory 32-bit word" line.long 0x3B4 "IME3_PROGRAMBUFFER_m_1324,Program Memory 32-bit word" line.long 0x3B8 "IME3_PROGRAMBUFFER_m_1325,Program Memory 32-bit word" line.long 0x3BC "IME3_PROGRAMBUFFER_m_1326,Program Memory 32-bit word" line.long 0x3C0 "IME3_PROGRAMBUFFER_m_1327,Program Memory 32-bit word" line.long 0x3C4 "IME3_PROGRAMBUFFER_m_1328,Program Memory 32-bit word" line.long 0x3C8 "IME3_PROGRAMBUFFER_m_1329,Program Memory 32-bit word" line.long 0x3CC "IME3_PROGRAMBUFFER_m_1330,Program Memory 32-bit word" line.long 0x3D0 "IME3_PROGRAMBUFFER_m_1331,Program Memory 32-bit word" line.long 0x3D4 "IME3_PROGRAMBUFFER_m_1332,Program Memory 32-bit word" line.long 0x3D8 "IME3_PROGRAMBUFFER_m_1333,Program Memory 32-bit word" line.long 0x3DC "IME3_PROGRAMBUFFER_m_1334,Program Memory 32-bit word" line.long 0x3E0 "IME3_PROGRAMBUFFER_m_1335,Program Memory 32-bit word" line.long 0x3E4 "IME3_PROGRAMBUFFER_m_1336,Program Memory 32-bit word" line.long 0x3E8 "IME3_PROGRAMBUFFER_m_1337,Program Memory 32-bit word" line.long 0x3EC "IME3_PROGRAMBUFFER_m_1338,Program Memory 32-bit word" line.long 0x3F0 "IME3_PROGRAMBUFFER_m_1339,Program Memory 32-bit word" line.long 0x3F4 "IME3_PROGRAMBUFFER_m_1340,Program Memory 32-bit word" line.long 0x3F8 "IME3_PROGRAMBUFFER_m_1341,Program Memory 32-bit word" line.long 0x3FC "IME3_PROGRAMBUFFER_m_1342,Program Memory 32-bit word" line.long 0x400 "IME3_PROGRAMBUFFER_m_1343,Program Memory 32-bit word" line.long 0x404 "IME3_PROGRAMBUFFER_m_1344,Program Memory 32-bit word" line.long 0x408 "IME3_PROGRAMBUFFER_m_1345,Program Memory 32-bit word" line.long 0x40C "IME3_PROGRAMBUFFER_m_1346,Program Memory 32-bit word" line.long 0x410 "IME3_PROGRAMBUFFER_m_1347,Program Memory 32-bit word" line.long 0x414 "IME3_PROGRAMBUFFER_m_1348,Program Memory 32-bit word" line.long 0x418 "IME3_PROGRAMBUFFER_m_1349,Program Memory 32-bit word" line.long 0x41C "IME3_PROGRAMBUFFER_m_1350,Program Memory 32-bit word" line.long 0x420 "IME3_PROGRAMBUFFER_m_1351,Program Memory 32-bit word" line.long 0x424 "IME3_PROGRAMBUFFER_m_1352,Program Memory 32-bit word" line.long 0x428 "IME3_PROGRAMBUFFER_m_1353,Program Memory 32-bit word" line.long 0x42C "IME3_PROGRAMBUFFER_m_1354,Program Memory 32-bit word" line.long 0x430 "IME3_PROGRAMBUFFER_m_1355,Program Memory 32-bit word" line.long 0x434 "IME3_PROGRAMBUFFER_m_1356,Program Memory 32-bit word" line.long 0x438 "IME3_PROGRAMBUFFER_m_1357,Program Memory 32-bit word" line.long 0x43C "IME3_PROGRAMBUFFER_m_1358,Program Memory 32-bit word" line.long 0x440 "IME3_PROGRAMBUFFER_m_1359,Program Memory 32-bit word" line.long 0x444 "IME3_PROGRAMBUFFER_m_1360,Program Memory 32-bit word" line.long 0x448 "IME3_PROGRAMBUFFER_m_1361,Program Memory 32-bit word" line.long 0x44C "IME3_PROGRAMBUFFER_m_1362,Program Memory 32-bit word" line.long 0x450 "IME3_PROGRAMBUFFER_m_1363,Program Memory 32-bit word" line.long 0x454 "IME3_PROGRAMBUFFER_m_1364,Program Memory 32-bit word" line.long 0x458 "IME3_PROGRAMBUFFER_m_1365,Program Memory 32-bit word" line.long 0x45C "IME3_PROGRAMBUFFER_m_1366,Program Memory 32-bit word" line.long 0x460 "IME3_PROGRAMBUFFER_m_1367,Program Memory 32-bit word" line.long 0x464 "IME3_PROGRAMBUFFER_m_1368,Program Memory 32-bit word" line.long 0x468 "IME3_PROGRAMBUFFER_m_1369,Program Memory 32-bit word" line.long 0x46C "IME3_PROGRAMBUFFER_m_1370,Program Memory 32-bit word" line.long 0x470 "IME3_PROGRAMBUFFER_m_1371,Program Memory 32-bit word" line.long 0x474 "IME3_PROGRAMBUFFER_m_1372,Program Memory 32-bit word" line.long 0x478 "IME3_PROGRAMBUFFER_m_1373,Program Memory 32-bit word" line.long 0x47C "IME3_PROGRAMBUFFER_m_1374,Program Memory 32-bit word" line.long 0x480 "IME3_PROGRAMBUFFER_m_1375,Program Memory 32-bit word" line.long 0x484 "IME3_PROGRAMBUFFER_m_1376,Program Memory 32-bit word" line.long 0x488 "IME3_PROGRAMBUFFER_m_1377,Program Memory 32-bit word" line.long 0x48C "IME3_PROGRAMBUFFER_m_1378,Program Memory 32-bit word" line.long 0x490 "IME3_PROGRAMBUFFER_m_1379,Program Memory 32-bit word" line.long 0x494 "IME3_PROGRAMBUFFER_m_1380,Program Memory 32-bit word" line.long 0x498 "IME3_PROGRAMBUFFER_m_1381,Program Memory 32-bit word" line.long 0x49C "IME3_PROGRAMBUFFER_m_1382,Program Memory 32-bit word" line.long 0x4A0 "IME3_PROGRAMBUFFER_m_1383,Program Memory 32-bit word" line.long 0x4A4 "IME3_PROGRAMBUFFER_m_1384,Program Memory 32-bit word" line.long 0x4A8 "IME3_PROGRAMBUFFER_m_1385,Program Memory 32-bit word" line.long 0x4AC "IME3_PROGRAMBUFFER_m_1386,Program Memory 32-bit word" line.long 0x4B0 "IME3_PROGRAMBUFFER_m_1387,Program Memory 32-bit word" line.long 0x4B4 "IME3_PROGRAMBUFFER_m_1388,Program Memory 32-bit word" line.long 0x4B8 "IME3_PROGRAMBUFFER_m_1389,Program Memory 32-bit word" line.long 0x4BC "IME3_PROGRAMBUFFER_m_1390,Program Memory 32-bit word" line.long 0x4C0 "IME3_PROGRAMBUFFER_m_1391,Program Memory 32-bit word" line.long 0x4C4 "IME3_PROGRAMBUFFER_m_1392,Program Memory 32-bit word" line.long 0x4C8 "IME3_PROGRAMBUFFER_m_1393,Program Memory 32-bit word" line.long 0x4CC "IME3_PROGRAMBUFFER_m_1394,Program Memory 32-bit word" line.long 0x4D0 "IME3_PROGRAMBUFFER_m_1395,Program Memory 32-bit word" line.long 0x4D4 "IME3_PROGRAMBUFFER_m_1396,Program Memory 32-bit word" line.long 0x4D8 "IME3_PROGRAMBUFFER_m_1397,Program Memory 32-bit word" line.long 0x4DC "IME3_PROGRAMBUFFER_m_1398,Program Memory 32-bit word" line.long 0x4E0 "IME3_PROGRAMBUFFER_m_1399,Program Memory 32-bit word" line.long 0x4E4 "IME3_PROGRAMBUFFER_m_1400,Program Memory 32-bit word" line.long 0x4E8 "IME3_PROGRAMBUFFER_m_1401,Program Memory 32-bit word" line.long 0x4EC "IME3_PROGRAMBUFFER_m_1402,Program Memory 32-bit word" line.long 0x4F0 "IME3_PROGRAMBUFFER_m_1403,Program Memory 32-bit word" line.long 0x4F4 "IME3_PROGRAMBUFFER_m_1404,Program Memory 32-bit word" line.long 0x4F8 "IME3_PROGRAMBUFFER_m_1405,Program Memory 32-bit word" line.long 0x4FC "IME3_PROGRAMBUFFER_m_1406,Program Memory 32-bit word" line.long 0x500 "IME3_PROGRAMBUFFER_m_1407,Program Memory 32-bit word" line.long 0x504 "IME3_PROGRAMBUFFER_m_1408,Program Memory 32-bit word" line.long 0x508 "IME3_PROGRAMBUFFER_m_1409,Program Memory 32-bit word" line.long 0x50C "IME3_PROGRAMBUFFER_m_1410,Program Memory 32-bit word" line.long 0x510 "IME3_PROGRAMBUFFER_m_1411,Program Memory 32-bit word" line.long 0x514 "IME3_PROGRAMBUFFER_m_1412,Program Memory 32-bit word" line.long 0x518 "IME3_PROGRAMBUFFER_m_1413,Program Memory 32-bit word" line.long 0x51C "IME3_PROGRAMBUFFER_m_1414,Program Memory 32-bit word" line.long 0x520 "IME3_PROGRAMBUFFER_m_1415,Program Memory 32-bit word" line.long 0x524 "IME3_PROGRAMBUFFER_m_1416,Program Memory 32-bit word" line.long 0x528 "IME3_PROGRAMBUFFER_m_1417,Program Memory 32-bit word" line.long 0x52C "IME3_PROGRAMBUFFER_m_1418,Program Memory 32-bit word" line.long 0x530 "IME3_PROGRAMBUFFER_m_1419,Program Memory 32-bit word" line.long 0x534 "IME3_PROGRAMBUFFER_m_1420,Program Memory 32-bit word" line.long 0x538 "IME3_PROGRAMBUFFER_m_1421,Program Memory 32-bit word" line.long 0x53C "IME3_PROGRAMBUFFER_m_1422,Program Memory 32-bit word" line.long 0x540 "IME3_PROGRAMBUFFER_m_1423,Program Memory 32-bit word" line.long 0x544 "IME3_PROGRAMBUFFER_m_1424,Program Memory 32-bit word" line.long 0x548 "IME3_PROGRAMBUFFER_m_1425,Program Memory 32-bit word" line.long 0x54C "IME3_PROGRAMBUFFER_m_1426,Program Memory 32-bit word" line.long 0x550 "IME3_PROGRAMBUFFER_m_1427,Program Memory 32-bit word" line.long 0x554 "IME3_PROGRAMBUFFER_m_1428,Program Memory 32-bit word" line.long 0x558 "IME3_PROGRAMBUFFER_m_1429,Program Memory 32-bit word" line.long 0x55C "IME3_PROGRAMBUFFER_m_1430,Program Memory 32-bit word" line.long 0x560 "IME3_PROGRAMBUFFER_m_1431,Program Memory 32-bit word" line.long 0x564 "IME3_PROGRAMBUFFER_m_1432,Program Memory 32-bit word" line.long 0x568 "IME3_PROGRAMBUFFER_m_1433,Program Memory 32-bit word" line.long 0x56C "IME3_PROGRAMBUFFER_m_1434,Program Memory 32-bit word" line.long 0x570 "IME3_PROGRAMBUFFER_m_1435,Program Memory 32-bit word" line.long 0x574 "IME3_PROGRAMBUFFER_m_1436,Program Memory 32-bit word" line.long 0x578 "IME3_PROGRAMBUFFER_m_1437,Program Memory 32-bit word" line.long 0x57C "IME3_PROGRAMBUFFER_m_1438,Program Memory 32-bit word" line.long 0x580 "IME3_PROGRAMBUFFER_m_1439,Program Memory 32-bit word" line.long 0x584 "IME3_PROGRAMBUFFER_m_1440,Program Memory 32-bit word" line.long 0x588 "IME3_PROGRAMBUFFER_m_1441,Program Memory 32-bit word" line.long 0x58C "IME3_PROGRAMBUFFER_m_1442,Program Memory 32-bit word" line.long 0x590 "IME3_PROGRAMBUFFER_m_1443,Program Memory 32-bit word" line.long 0x594 "IME3_PROGRAMBUFFER_m_1444,Program Memory 32-bit word" line.long 0x598 "IME3_PROGRAMBUFFER_m_1445,Program Memory 32-bit word" line.long 0x59C "IME3_PROGRAMBUFFER_m_1446,Program Memory 32-bit word" line.long 0x5A0 "IME3_PROGRAMBUFFER_m_1447,Program Memory 32-bit word" line.long 0x5A4 "IME3_PROGRAMBUFFER_m_1448,Program Memory 32-bit word" line.long 0x5A8 "IME3_PROGRAMBUFFER_m_1449,Program Memory 32-bit word" line.long 0x5AC "IME3_PROGRAMBUFFER_m_1450,Program Memory 32-bit word" line.long 0x5B0 "IME3_PROGRAMBUFFER_m_1451,Program Memory 32-bit word" line.long 0x5B4 "IME3_PROGRAMBUFFER_m_1452,Program Memory 32-bit word" line.long 0x5B8 "IME3_PROGRAMBUFFER_m_1453,Program Memory 32-bit word" line.long 0x5BC "IME3_PROGRAMBUFFER_m_1454,Program Memory 32-bit word" line.long 0x5C0 "IME3_PROGRAMBUFFER_m_1455,Program Memory 32-bit word" line.long 0x5C4 "IME3_PROGRAMBUFFER_m_1456,Program Memory 32-bit word" line.long 0x5C8 "IME3_PROGRAMBUFFER_m_1457,Program Memory 32-bit word" line.long 0x5CC "IME3_PROGRAMBUFFER_m_1458,Program Memory 32-bit word" line.long 0x5D0 "IME3_PROGRAMBUFFER_m_1459,Program Memory 32-bit word" line.long 0x5D4 "IME3_PROGRAMBUFFER_m_1460,Program Memory 32-bit word" line.long 0x5D8 "IME3_PROGRAMBUFFER_m_1461,Program Memory 32-bit word" line.long 0x5DC "IME3_PROGRAMBUFFER_m_1462,Program Memory 32-bit word" line.long 0x5E0 "IME3_PROGRAMBUFFER_m_1463,Program Memory 32-bit word" line.long 0x5E4 "IME3_PROGRAMBUFFER_m_1464,Program Memory 32-bit word" line.long 0x5E8 "IME3_PROGRAMBUFFER_m_1465,Program Memory 32-bit word" line.long 0x5EC "IME3_PROGRAMBUFFER_m_1466,Program Memory 32-bit word" line.long 0x5F0 "IME3_PROGRAMBUFFER_m_1467,Program Memory 32-bit word" line.long 0x5F4 "IME3_PROGRAMBUFFER_m_1468,Program Memory 32-bit word" line.long 0x5F8 "IME3_PROGRAMBUFFER_m_1469,Program Memory 32-bit word" line.long 0x5FC "IME3_PROGRAMBUFFER_m_1470,Program Memory 32-bit word" line.long 0x600 "IME3_PROGRAMBUFFER_m_1471,Program Memory 32-bit word" line.long 0x604 "IME3_PROGRAMBUFFER_m_1472,Program Memory 32-bit word" line.long 0x608 "IME3_PROGRAMBUFFER_m_1473,Program Memory 32-bit word" line.long 0x60C "IME3_PROGRAMBUFFER_m_1474,Program Memory 32-bit word" line.long 0x610 "IME3_PROGRAMBUFFER_m_1475,Program Memory 32-bit word" line.long 0x614 "IME3_PROGRAMBUFFER_m_1476,Program Memory 32-bit word" line.long 0x618 "IME3_PROGRAMBUFFER_m_1477,Program Memory 32-bit word" line.long 0x61C "IME3_PROGRAMBUFFER_m_1478,Program Memory 32-bit word" line.long 0x620 "IME3_PROGRAMBUFFER_m_1479,Program Memory 32-bit word" line.long 0x624 "IME3_PROGRAMBUFFER_m_1480,Program Memory 32-bit word" line.long 0x628 "IME3_PROGRAMBUFFER_m_1481,Program Memory 32-bit word" line.long 0x62C "IME3_PROGRAMBUFFER_m_1482,Program Memory 32-bit word" line.long 0x630 "IME3_PROGRAMBUFFER_m_1483,Program Memory 32-bit word" line.long 0x634 "IME3_PROGRAMBUFFER_m_1484,Program Memory 32-bit word" line.long 0x638 "IME3_PROGRAMBUFFER_m_1485,Program Memory 32-bit word" line.long 0x63C "IME3_PROGRAMBUFFER_m_1486,Program Memory 32-bit word" line.long 0x640 "IME3_PROGRAMBUFFER_m_1487,Program Memory 32-bit word" line.long 0x644 "IME3_PROGRAMBUFFER_m_1488,Program Memory 32-bit word" line.long 0x648 "IME3_PROGRAMBUFFER_m_1489,Program Memory 32-bit word" line.long 0x64C "IME3_PROGRAMBUFFER_m_1490,Program Memory 32-bit word" line.long 0x650 "IME3_PROGRAMBUFFER_m_1491,Program Memory 32-bit word" line.long 0x654 "IME3_PROGRAMBUFFER_m_1492,Program Memory 32-bit word" line.long 0x658 "IME3_PROGRAMBUFFER_m_1493,Program Memory 32-bit word" line.long 0x65C "IME3_PROGRAMBUFFER_m_1494,Program Memory 32-bit word" line.long 0x660 "IME3_PROGRAMBUFFER_m_1495,Program Memory 32-bit word" line.long 0x664 "IME3_PROGRAMBUFFER_m_1496,Program Memory 32-bit word" line.long 0x668 "IME3_PROGRAMBUFFER_m_1497,Program Memory 32-bit word" line.long 0x66C "IME3_PROGRAMBUFFER_m_1498,Program Memory 32-bit word" line.long 0x670 "IME3_PROGRAMBUFFER_m_1499,Program Memory 32-bit word" line.long 0x674 "IME3_PROGRAMBUFFER_m_1500,Program Memory 32-bit word" line.long 0x678 "IME3_PROGRAMBUFFER_m_1501,Program Memory 32-bit word" line.long 0x67C "IME3_PROGRAMBUFFER_m_1502,Program Memory 32-bit word" line.long 0x680 "IME3_PROGRAMBUFFER_m_1503,Program Memory 32-bit word" line.long 0x684 "IME3_PROGRAMBUFFER_m_1504,Program Memory 32-bit word" line.long 0x688 "IME3_PROGRAMBUFFER_m_1505,Program Memory 32-bit word" line.long 0x68C "IME3_PROGRAMBUFFER_m_1506,Program Memory 32-bit word" line.long 0x690 "IME3_PROGRAMBUFFER_m_1507,Program Memory 32-bit word" line.long 0x694 "IME3_PROGRAMBUFFER_m_1508,Program Memory 32-bit word" line.long 0x698 "IME3_PROGRAMBUFFER_m_1509,Program Memory 32-bit word" line.long 0x69C "IME3_PROGRAMBUFFER_m_1510,Program Memory 32-bit word" line.long 0x6A0 "IME3_PROGRAMBUFFER_m_1511,Program Memory 32-bit word" line.long 0x6A4 "IME3_PROGRAMBUFFER_m_1512,Program Memory 32-bit word" line.long 0x6A8 "IME3_PROGRAMBUFFER_m_1513,Program Memory 32-bit word" line.long 0x6AC "IME3_PROGRAMBUFFER_m_1514,Program Memory 32-bit word" line.long 0x6B0 "IME3_PROGRAMBUFFER_m_1515,Program Memory 32-bit word" line.long 0x6B4 "IME3_PROGRAMBUFFER_m_1516,Program Memory 32-bit word" line.long 0x6B8 "IME3_PROGRAMBUFFER_m_1517,Program Memory 32-bit word" line.long 0x6BC "IME3_PROGRAMBUFFER_m_1518,Program Memory 32-bit word" line.long 0x6C0 "IME3_PROGRAMBUFFER_m_1519,Program Memory 32-bit word" line.long 0x6C4 "IME3_PROGRAMBUFFER_m_1520,Program Memory 32-bit word" line.long 0x6C8 "IME3_PROGRAMBUFFER_m_1521,Program Memory 32-bit word" line.long 0x6CC "IME3_PROGRAMBUFFER_m_1522,Program Memory 32-bit word" line.long 0x6D0 "IME3_PROGRAMBUFFER_m_1523,Program Memory 32-bit word" line.long 0x6D4 "IME3_PROGRAMBUFFER_m_1524,Program Memory 32-bit word" line.long 0x6D8 "IME3_PROGRAMBUFFER_m_1525,Program Memory 32-bit word" line.long 0x6DC "IME3_PROGRAMBUFFER_m_1526,Program Memory 32-bit word" line.long 0x6E0 "IME3_PROGRAMBUFFER_m_1527,Program Memory 32-bit word" line.long 0x6E4 "IME3_PROGRAMBUFFER_m_1528,Program Memory 32-bit word" line.long 0x6E8 "IME3_PROGRAMBUFFER_m_1529,Program Memory 32-bit word" line.long 0x6EC "IME3_PROGRAMBUFFER_m_1530,Program Memory 32-bit word" line.long 0x6F0 "IME3_PROGRAMBUFFER_m_1531,Program Memory 32-bit word" line.long 0x6F4 "IME3_PROGRAMBUFFER_m_1532,Program Memory 32-bit word" line.long 0x6F8 "IME3_PROGRAMBUFFER_m_1533,Program Memory 32-bit word" line.long 0x6FC "IME3_PROGRAMBUFFER_m_1534,Program Memory 32-bit word" line.long 0x700 "IME3_PROGRAMBUFFER_m_1535,Program Memory 32-bit word" line.long 0x704 "IME3_PROGRAMBUFFER_m_1536,Program Memory 32-bit word" line.long 0x708 "IME3_PROGRAMBUFFER_m_1537,Program Memory 32-bit word" line.long 0x70C "IME3_PROGRAMBUFFER_m_1538,Program Memory 32-bit word" line.long 0x710 "IME3_PROGRAMBUFFER_m_1539,Program Memory 32-bit word" line.long 0x714 "IME3_PROGRAMBUFFER_m_1540,Program Memory 32-bit word" line.long 0x718 "IME3_PROGRAMBUFFER_m_1541,Program Memory 32-bit word" line.long 0x71C "IME3_PROGRAMBUFFER_m_1542,Program Memory 32-bit word" line.long 0x720 "IME3_PROGRAMBUFFER_m_1543,Program Memory 32-bit word" line.long 0x724 "IME3_PROGRAMBUFFER_m_1544,Program Memory 32-bit word" line.long 0x728 "IME3_PROGRAMBUFFER_m_1545,Program Memory 32-bit word" line.long 0x72C "IME3_PROGRAMBUFFER_m_1546,Program Memory 32-bit word" line.long 0x730 "IME3_PROGRAMBUFFER_m_1547,Program Memory 32-bit word" line.long 0x734 "IME3_PROGRAMBUFFER_m_1548,Program Memory 32-bit word" line.long 0x738 "IME3_PROGRAMBUFFER_m_1549,Program Memory 32-bit word" line.long 0x73C "IME3_PROGRAMBUFFER_m_1550,Program Memory 32-bit word" line.long 0x740 "IME3_PROGRAMBUFFER_m_1551,Program Memory 32-bit word" line.long 0x744 "IME3_PROGRAMBUFFER_m_1552,Program Memory 32-bit word" line.long 0x748 "IME3_PROGRAMBUFFER_m_1553,Program Memory 32-bit word" line.long 0x74C "IME3_PROGRAMBUFFER_m_1554,Program Memory 32-bit word" line.long 0x750 "IME3_PROGRAMBUFFER_m_1555,Program Memory 32-bit word" line.long 0x754 "IME3_PROGRAMBUFFER_m_1556,Program Memory 32-bit word" line.long 0x758 "IME3_PROGRAMBUFFER_m_1557,Program Memory 32-bit word" line.long 0x75C "IME3_PROGRAMBUFFER_m_1558,Program Memory 32-bit word" line.long 0x760 "IME3_PROGRAMBUFFER_m_1559,Program Memory 32-bit word" line.long 0x764 "IME3_PROGRAMBUFFER_m_1560,Program Memory 32-bit word" line.long 0x768 "IME3_PROGRAMBUFFER_m_1561,Program Memory 32-bit word" line.long 0x76C "IME3_PROGRAMBUFFER_m_1562,Program Memory 32-bit word" line.long 0x770 "IME3_PROGRAMBUFFER_m_1563,Program Memory 32-bit word" line.long 0x774 "IME3_PROGRAMBUFFER_m_1564,Program Memory 32-bit word" line.long 0x778 "IME3_PROGRAMBUFFER_m_1565,Program Memory 32-bit word" line.long 0x77C "IME3_PROGRAMBUFFER_m_1566,Program Memory 32-bit word" line.long 0x780 "IME3_PROGRAMBUFFER_m_1567,Program Memory 32-bit word" line.long 0x784 "IME3_PROGRAMBUFFER_m_1568,Program Memory 32-bit word" line.long 0x788 "IME3_PROGRAMBUFFER_m_1569,Program Memory 32-bit word" line.long 0x78C "IME3_PROGRAMBUFFER_m_1570,Program Memory 32-bit word" line.long 0x790 "IME3_PROGRAMBUFFER_m_1571,Program Memory 32-bit word" line.long 0x794 "IME3_PROGRAMBUFFER_m_1572,Program Memory 32-bit word" line.long 0x798 "IME3_PROGRAMBUFFER_m_1573,Program Memory 32-bit word" line.long 0x79C "IME3_PROGRAMBUFFER_m_1574,Program Memory 32-bit word" line.long 0x7A0 "IME3_PROGRAMBUFFER_m_1575,Program Memory 32-bit word" line.long 0x7A4 "IME3_PROGRAMBUFFER_m_1576,Program Memory 32-bit word" line.long 0x7A8 "IME3_PROGRAMBUFFER_m_1577,Program Memory 32-bit word" line.long 0x7AC "IME3_PROGRAMBUFFER_m_1578,Program Memory 32-bit word" line.long 0x7B0 "IME3_PROGRAMBUFFER_m_1579,Program Memory 32-bit word" line.long 0x7B4 "IME3_PROGRAMBUFFER_m_1580,Program Memory 32-bit word" line.long 0x7B8 "IME3_PROGRAMBUFFER_m_1581,Program Memory 32-bit word" line.long 0x7BC "IME3_PROGRAMBUFFER_m_1582,Program Memory 32-bit word" line.long 0x7C0 "IME3_PROGRAMBUFFER_m_1583,Program Memory 32-bit word" line.long 0x7C4 "IME3_PROGRAMBUFFER_m_1584,Program Memory 32-bit word" line.long 0x7C8 "IME3_PROGRAMBUFFER_m_1585,Program Memory 32-bit word" line.long 0x7CC "IME3_PROGRAMBUFFER_m_1586,Program Memory 32-bit word" line.long 0x7D0 "IME3_PROGRAMBUFFER_m_1587,Program Memory 32-bit word" line.long 0x7D4 "IME3_PROGRAMBUFFER_m_1588,Program Memory 32-bit word" line.long 0x7D8 "IME3_PROGRAMBUFFER_m_1589,Program Memory 32-bit word" line.long 0x7DC "IME3_PROGRAMBUFFER_m_1590,Program Memory 32-bit word" line.long 0x7E0 "IME3_PROGRAMBUFFER_m_1591,Program Memory 32-bit word" line.long 0x7E4 "IME3_PROGRAMBUFFER_m_1592,Program Memory 32-bit word" line.long 0x7E8 "IME3_PROGRAMBUFFER_m_1593,Program Memory 32-bit word" line.long 0x7EC "IME3_PROGRAMBUFFER_m_1594,Program Memory 32-bit word" line.long 0x7F0 "IME3_PROGRAMBUFFER_m_1595,Program Memory 32-bit word" line.long 0x7F4 "IME3_PROGRAMBUFFER_m_1596,Program Memory 32-bit word" line.long 0x7F8 "IME3_PROGRAMBUFFER_m_1597,Program Memory 32-bit word" line.long 0x7FC "IME3_PROGRAMBUFFER_m_1598,Program Memory 32-bit word" line.long 0x800 "IME3_PROGRAMBUFFER_m_1599,Program Memory 32-bit word" line.long 0x804 "IME3_PROGRAMBUFFER_m_1600,Program Memory 32-bit word" line.long 0x808 "IME3_PROGRAMBUFFER_m_1601,Program Memory 32-bit word" line.long 0x80C "IME3_PROGRAMBUFFER_m_1602,Program Memory 32-bit word" line.long 0x810 "IME3_PROGRAMBUFFER_m_1603,Program Memory 32-bit word" line.long 0x814 "IME3_PROGRAMBUFFER_m_1604,Program Memory 32-bit word" line.long 0x818 "IME3_PROGRAMBUFFER_m_1605,Program Memory 32-bit word" line.long 0x81C "IME3_PROGRAMBUFFER_m_1606,Program Memory 32-bit word" line.long 0x820 "IME3_PROGRAMBUFFER_m_1607,Program Memory 32-bit word" line.long 0x824 "IME3_PROGRAMBUFFER_m_1608,Program Memory 32-bit word" line.long 0x828 "IME3_PROGRAMBUFFER_m_1609,Program Memory 32-bit word" line.long 0x82C "IME3_PROGRAMBUFFER_m_1610,Program Memory 32-bit word" line.long 0x830 "IME3_PROGRAMBUFFER_m_1611,Program Memory 32-bit word" line.long 0x834 "IME3_PROGRAMBUFFER_m_1612,Program Memory 32-bit word" line.long 0x838 "IME3_PROGRAMBUFFER_m_1613,Program Memory 32-bit word" line.long 0x83C "IME3_PROGRAMBUFFER_m_1614,Program Memory 32-bit word" line.long 0x840 "IME3_PROGRAMBUFFER_m_1615,Program Memory 32-bit word" line.long 0x844 "IME3_PROGRAMBUFFER_m_1616,Program Memory 32-bit word" line.long 0x848 "IME3_PROGRAMBUFFER_m_1617,Program Memory 32-bit word" line.long 0x84C "IME3_PROGRAMBUFFER_m_1618,Program Memory 32-bit word" line.long 0x850 "IME3_PROGRAMBUFFER_m_1619,Program Memory 32-bit word" line.long 0x854 "IME3_PROGRAMBUFFER_m_1620,Program Memory 32-bit word" line.long 0x858 "IME3_PROGRAMBUFFER_m_1621,Program Memory 32-bit word" line.long 0x85C "IME3_PROGRAMBUFFER_m_1622,Program Memory 32-bit word" line.long 0x860 "IME3_PROGRAMBUFFER_m_1623,Program Memory 32-bit word" line.long 0x864 "IME3_PROGRAMBUFFER_m_1624,Program Memory 32-bit word" line.long 0x868 "IME3_PROGRAMBUFFER_m_1625,Program Memory 32-bit word" line.long 0x86C "IME3_PROGRAMBUFFER_m_1626,Program Memory 32-bit word" line.long 0x870 "IME3_PROGRAMBUFFER_m_1627,Program Memory 32-bit word" line.long 0x874 "IME3_PROGRAMBUFFER_m_1628,Program Memory 32-bit word" line.long 0x878 "IME3_PROGRAMBUFFER_m_1629,Program Memory 32-bit word" line.long 0x87C "IME3_PROGRAMBUFFER_m_1630,Program Memory 32-bit word" line.long 0x880 "IME3_PROGRAMBUFFER_m_1631,Program Memory 32-bit word" line.long 0x884 "IME3_PROGRAMBUFFER_m_1632,Program Memory 32-bit word" line.long 0x888 "IME3_PROGRAMBUFFER_m_1633,Program Memory 32-bit word" line.long 0x88C "IME3_PROGRAMBUFFER_m_1634,Program Memory 32-bit word" line.long 0x890 "IME3_PROGRAMBUFFER_m_1635,Program Memory 32-bit word" line.long 0x894 "IME3_PROGRAMBUFFER_m_1636,Program Memory 32-bit word" line.long 0x898 "IME3_PROGRAMBUFFER_m_1637,Program Memory 32-bit word" line.long 0x89C "IME3_PROGRAMBUFFER_m_1638,Program Memory 32-bit word" line.long 0x8A0 "IME3_PROGRAMBUFFER_m_1639,Program Memory 32-bit word" line.long 0x8A4 "IME3_PROGRAMBUFFER_m_1640,Program Memory 32-bit word" line.long 0x8A8 "IME3_PROGRAMBUFFER_m_1641,Program Memory 32-bit word" line.long 0x8AC "IME3_PROGRAMBUFFER_m_1642,Program Memory 32-bit word" line.long 0x8B0 "IME3_PROGRAMBUFFER_m_1643,Program Memory 32-bit word" line.long 0x8B4 "IME3_PROGRAMBUFFER_m_1644,Program Memory 32-bit word" line.long 0x8B8 "IME3_PROGRAMBUFFER_m_1645,Program Memory 32-bit word" line.long 0x8BC "IME3_PROGRAMBUFFER_m_1646,Program Memory 32-bit word" line.long 0x8C0 "IME3_PROGRAMBUFFER_m_1647,Program Memory 32-bit word" line.long 0x8C4 "IME3_PROGRAMBUFFER_m_1648,Program Memory 32-bit word" line.long 0x8C8 "IME3_PROGRAMBUFFER_m_1649,Program Memory 32-bit word" line.long 0x8CC "IME3_PROGRAMBUFFER_m_1650,Program Memory 32-bit word" line.long 0x8D0 "IME3_PROGRAMBUFFER_m_1651,Program Memory 32-bit word" line.long 0x8D4 "IME3_PROGRAMBUFFER_m_1652,Program Memory 32-bit word" line.long 0x8D8 "IME3_PROGRAMBUFFER_m_1653,Program Memory 32-bit word" line.long 0x8DC "IME3_PROGRAMBUFFER_m_1654,Program Memory 32-bit word" line.long 0x8E0 "IME3_PROGRAMBUFFER_m_1655,Program Memory 32-bit word" line.long 0x8E4 "IME3_PROGRAMBUFFER_m_1656,Program Memory 32-bit word" line.long 0x8E8 "IME3_PROGRAMBUFFER_m_1657,Program Memory 32-bit word" line.long 0x8EC "IME3_PROGRAMBUFFER_m_1658,Program Memory 32-bit word" line.long 0x8F0 "IME3_PROGRAMBUFFER_m_1659,Program Memory 32-bit word" line.long 0x8F4 "IME3_PROGRAMBUFFER_m_1660,Program Memory 32-bit word" line.long 0x8F8 "IME3_PROGRAMBUFFER_m_1661,Program Memory 32-bit word" line.long 0x8FC "IME3_PROGRAMBUFFER_m_1662,Program Memory 32-bit word" line.long 0x900 "IME3_PROGRAMBUFFER_m_1663,Program Memory 32-bit word" line.long 0x904 "IME3_PROGRAMBUFFER_m_1664,Program Memory 32-bit word" line.long 0x908 "IME3_PROGRAMBUFFER_m_1665,Program Memory 32-bit word" line.long 0x90C "IME3_PROGRAMBUFFER_m_1666,Program Memory 32-bit word" line.long 0x910 "IME3_PROGRAMBUFFER_m_1667,Program Memory 32-bit word" line.long 0x914 "IME3_PROGRAMBUFFER_m_1668,Program Memory 32-bit word" line.long 0x918 "IME3_PROGRAMBUFFER_m_1669,Program Memory 32-bit word" line.long 0x91C "IME3_PROGRAMBUFFER_m_1670,Program Memory 32-bit word" line.long 0x920 "IME3_PROGRAMBUFFER_m_1671,Program Memory 32-bit word" line.long 0x924 "IME3_PROGRAMBUFFER_m_1672,Program Memory 32-bit word" line.long 0x928 "IME3_PROGRAMBUFFER_m_1673,Program Memory 32-bit word" line.long 0x92C "IME3_PROGRAMBUFFER_m_1674,Program Memory 32-bit word" line.long 0x930 "IME3_PROGRAMBUFFER_m_1675,Program Memory 32-bit word" line.long 0x934 "IME3_PROGRAMBUFFER_m_1676,Program Memory 32-bit word" line.long 0x938 "IME3_PROGRAMBUFFER_m_1677,Program Memory 32-bit word" line.long 0x93C "IME3_PROGRAMBUFFER_m_1678,Program Memory 32-bit word" line.long 0x940 "IME3_PROGRAMBUFFER_m_1679,Program Memory 32-bit word" line.long 0x944 "IME3_PROGRAMBUFFER_m_1680,Program Memory 32-bit word" line.long 0x948 "IME3_PROGRAMBUFFER_m_1681,Program Memory 32-bit word" line.long 0x94C "IME3_PROGRAMBUFFER_m_1682,Program Memory 32-bit word" line.long 0x950 "IME3_PROGRAMBUFFER_m_1683,Program Memory 32-bit word" line.long 0x954 "IME3_PROGRAMBUFFER_m_1684,Program Memory 32-bit word" line.long 0x958 "IME3_PROGRAMBUFFER_m_1685,Program Memory 32-bit word" line.long 0x95C "IME3_PROGRAMBUFFER_m_1686,Program Memory 32-bit word" line.long 0x960 "IME3_PROGRAMBUFFER_m_1687,Program Memory 32-bit word" line.long 0x964 "IME3_PROGRAMBUFFER_m_1688,Program Memory 32-bit word" line.long 0x968 "IME3_PROGRAMBUFFER_m_1689,Program Memory 32-bit word" line.long 0x96C "IME3_PROGRAMBUFFER_m_1690,Program Memory 32-bit word" line.long 0x970 "IME3_PROGRAMBUFFER_m_1691,Program Memory 32-bit word" line.long 0x974 "IME3_PROGRAMBUFFER_m_1692,Program Memory 32-bit word" line.long 0x978 "IME3_PROGRAMBUFFER_m_1693,Program Memory 32-bit word" line.long 0x97C "IME3_PROGRAMBUFFER_m_1694,Program Memory 32-bit word" line.long 0x980 "IME3_PROGRAMBUFFER_m_1695,Program Memory 32-bit word" line.long 0x984 "IME3_PROGRAMBUFFER_m_1696,Program Memory 32-bit word" line.long 0x988 "IME3_PROGRAMBUFFER_m_1697,Program Memory 32-bit word" line.long 0x98C "IME3_PROGRAMBUFFER_m_1698,Program Memory 32-bit word" line.long 0x990 "IME3_PROGRAMBUFFER_m_1699,Program Memory 32-bit word" line.long 0x994 "IME3_PROGRAMBUFFER_m_1700,Program Memory 32-bit word" line.long 0x998 "IME3_PROGRAMBUFFER_m_1701,Program Memory 32-bit word" line.long 0x99C "IME3_PROGRAMBUFFER_m_1702,Program Memory 32-bit word" line.long 0x9A0 "IME3_PROGRAMBUFFER_m_1703,Program Memory 32-bit word" line.long 0x9A4 "IME3_PROGRAMBUFFER_m_1704,Program Memory 32-bit word" line.long 0x9A8 "IME3_PROGRAMBUFFER_m_1705,Program Memory 32-bit word" line.long 0x9AC "IME3_PROGRAMBUFFER_m_1706,Program Memory 32-bit word" line.long 0x9B0 "IME3_PROGRAMBUFFER_m_1707,Program Memory 32-bit word" line.long 0x9B4 "IME3_PROGRAMBUFFER_m_1708,Program Memory 32-bit word" line.long 0x9B8 "IME3_PROGRAMBUFFER_m_1709,Program Memory 32-bit word" line.long 0x9BC "IME3_PROGRAMBUFFER_m_1710,Program Memory 32-bit word" line.long 0x9C0 "IME3_PROGRAMBUFFER_m_1711,Program Memory 32-bit word" line.long 0x9C4 "IME3_PROGRAMBUFFER_m_1712,Program Memory 32-bit word" line.long 0x9C8 "IME3_PROGRAMBUFFER_m_1713,Program Memory 32-bit word" line.long 0x9CC "IME3_PROGRAMBUFFER_m_1714,Program Memory 32-bit word" line.long 0x9D0 "IME3_PROGRAMBUFFER_m_1715,Program Memory 32-bit word" line.long 0x9D4 "IME3_PROGRAMBUFFER_m_1716,Program Memory 32-bit word" line.long 0x9D8 "IME3_PROGRAMBUFFER_m_1717,Program Memory 32-bit word" line.long 0x9DC "IME3_PROGRAMBUFFER_m_1718,Program Memory 32-bit word" line.long 0x9E0 "IME3_PROGRAMBUFFER_m_1719,Program Memory 32-bit word" line.long 0x9E4 "IME3_PROGRAMBUFFER_m_1720,Program Memory 32-bit word" line.long 0x9E8 "IME3_PROGRAMBUFFER_m_1721,Program Memory 32-bit word" line.long 0x9EC "IME3_PROGRAMBUFFER_m_1722,Program Memory 32-bit word" line.long 0x9F0 "IME3_PROGRAMBUFFER_m_1723,Program Memory 32-bit word" line.long 0x9F4 "IME3_PROGRAMBUFFER_m_1724,Program Memory 32-bit word" line.long 0x9F8 "IME3_PROGRAMBUFFER_m_1725,Program Memory 32-bit word" line.long 0x9FC "IME3_PROGRAMBUFFER_m_1726,Program Memory 32-bit word" line.long 0xA00 "IME3_PROGRAMBUFFER_m_1727,Program Memory 32-bit word" line.long 0xA04 "IME3_PROGRAMBUFFER_m_1728,Program Memory 32-bit word" line.long 0xA08 "IME3_PROGRAMBUFFER_m_1729,Program Memory 32-bit word" line.long 0xA0C "IME3_PROGRAMBUFFER_m_1730,Program Memory 32-bit word" line.long 0xA10 "IME3_PROGRAMBUFFER_m_1731,Program Memory 32-bit word" line.long 0xA14 "IME3_PROGRAMBUFFER_m_1732,Program Memory 32-bit word" line.long 0xA18 "IME3_PROGRAMBUFFER_m_1733,Program Memory 32-bit word" line.long 0xA1C "IME3_PROGRAMBUFFER_m_1734,Program Memory 32-bit word" line.long 0xA20 "IME3_PROGRAMBUFFER_m_1735,Program Memory 32-bit word" line.long 0xA24 "IME3_PROGRAMBUFFER_m_1736,Program Memory 32-bit word" line.long 0xA28 "IME3_PROGRAMBUFFER_m_1737,Program Memory 32-bit word" line.long 0xA2C "IME3_PROGRAMBUFFER_m_1738,Program Memory 32-bit word" line.long 0xA30 "IME3_PROGRAMBUFFER_m_1739,Program Memory 32-bit word" line.long 0xA34 "IME3_PROGRAMBUFFER_m_1740,Program Memory 32-bit word" line.long 0xA38 "IME3_PROGRAMBUFFER_m_1741,Program Memory 32-bit word" line.long 0xA3C "IME3_PROGRAMBUFFER_m_1742,Program Memory 32-bit word" line.long 0xA40 "IME3_PROGRAMBUFFER_m_1743,Program Memory 32-bit word" line.long 0xA44 "IME3_PROGRAMBUFFER_m_1744,Program Memory 32-bit word" line.long 0xA48 "IME3_PROGRAMBUFFER_m_1745,Program Memory 32-bit word" line.long 0xA4C "IME3_PROGRAMBUFFER_m_1746,Program Memory 32-bit word" line.long 0xA50 "IME3_PROGRAMBUFFER_m_1747,Program Memory 32-bit word" line.long 0xA54 "IME3_PROGRAMBUFFER_m_1748,Program Memory 32-bit word" line.long 0xA58 "IME3_PROGRAMBUFFER_m_1749,Program Memory 32-bit word" line.long 0xA5C "IME3_PROGRAMBUFFER_m_1750,Program Memory 32-bit word" line.long 0xA60 "IME3_PROGRAMBUFFER_m_1751,Program Memory 32-bit word" line.long 0xA64 "IME3_PROGRAMBUFFER_m_1752,Program Memory 32-bit word" line.long 0xA68 "IME3_PROGRAMBUFFER_m_1753,Program Memory 32-bit word" line.long 0xA6C "IME3_PROGRAMBUFFER_m_1754,Program Memory 32-bit word" line.long 0xA70 "IME3_PROGRAMBUFFER_m_1755,Program Memory 32-bit word" line.long 0xA74 "IME3_PROGRAMBUFFER_m_1756,Program Memory 32-bit word" line.long 0xA78 "IME3_PROGRAMBUFFER_m_1757,Program Memory 32-bit word" line.long 0xA7C "IME3_PROGRAMBUFFER_m_1758,Program Memory 32-bit word" line.long 0xA80 "IME3_PROGRAMBUFFER_m_1759,Program Memory 32-bit word" line.long 0xA84 "IME3_PROGRAMBUFFER_m_1760,Program Memory 32-bit word" line.long 0xA88 "IME3_PROGRAMBUFFER_m_1761,Program Memory 32-bit word" line.long 0xA8C "IME3_PROGRAMBUFFER_m_1762,Program Memory 32-bit word" line.long 0xA90 "IME3_PROGRAMBUFFER_m_1763,Program Memory 32-bit word" line.long 0xA94 "IME3_PROGRAMBUFFER_m_1764,Program Memory 32-bit word" line.long 0xA98 "IME3_PROGRAMBUFFER_m_1765,Program Memory 32-bit word" line.long 0xA9C "IME3_PROGRAMBUFFER_m_1766,Program Memory 32-bit word" line.long 0xAA0 "IME3_PROGRAMBUFFER_m_1767,Program Memory 32-bit word" line.long 0xAA4 "IME3_PROGRAMBUFFER_m_1768,Program Memory 32-bit word" line.long 0xAA8 "IME3_PROGRAMBUFFER_m_1769,Program Memory 32-bit word" line.long 0xAAC "IME3_PROGRAMBUFFER_m_1770,Program Memory 32-bit word" line.long 0xAB0 "IME3_PROGRAMBUFFER_m_1771,Program Memory 32-bit word" line.long 0xAB4 "IME3_PROGRAMBUFFER_m_1772,Program Memory 32-bit word" line.long 0xAB8 "IME3_PROGRAMBUFFER_m_1773,Program Memory 32-bit word" line.long 0xABC "IME3_PROGRAMBUFFER_m_1774,Program Memory 32-bit word" line.long 0xAC0 "IME3_PROGRAMBUFFER_m_1775,Program Memory 32-bit word" line.long 0xAC4 "IME3_PROGRAMBUFFER_m_1776,Program Memory 32-bit word" line.long 0xAC8 "IME3_PROGRAMBUFFER_m_1777,Program Memory 32-bit word" line.long 0xACC "IME3_PROGRAMBUFFER_m_1778,Program Memory 32-bit word" line.long 0xAD0 "IME3_PROGRAMBUFFER_m_1779,Program Memory 32-bit word" line.long 0xAD4 "IME3_PROGRAMBUFFER_m_1780,Program Memory 32-bit word" line.long 0xAD8 "IME3_PROGRAMBUFFER_m_1781,Program Memory 32-bit word" line.long 0xADC "IME3_PROGRAMBUFFER_m_1782,Program Memory 32-bit word" line.long 0xAE0 "IME3_PROGRAMBUFFER_m_1783,Program Memory 32-bit word" line.long 0xAE4 "IME3_PROGRAMBUFFER_m_1784,Program Memory 32-bit word" line.long 0xAE8 "IME3_PROGRAMBUFFER_m_1785,Program Memory 32-bit word" line.long 0xAEC "IME3_PROGRAMBUFFER_m_1786,Program Memory 32-bit word" line.long 0xAF0 "IME3_PROGRAMBUFFER_m_1787,Program Memory 32-bit word" line.long 0xAF4 "IME3_PROGRAMBUFFER_m_1788,Program Memory 32-bit word" line.long 0xAF8 "IME3_PROGRAMBUFFER_m_1789,Program Memory 32-bit word" line.long 0xAFC "IME3_PROGRAMBUFFER_m_1790,Program Memory 32-bit word" line.long 0xB00 "IME3_PROGRAMBUFFER_m_1791,Program Memory 32-bit word" line.long 0xB04 "IME3_PROGRAMBUFFER_m_1792,Program Memory 32-bit word" line.long 0xB08 "IME3_PROGRAMBUFFER_m_1793,Program Memory 32-bit word" line.long 0xB0C "IME3_PROGRAMBUFFER_m_1794,Program Memory 32-bit word" line.long 0xB10 "IME3_PROGRAMBUFFER_m_1795,Program Memory 32-bit word" line.long 0xB14 "IME3_PROGRAMBUFFER_m_1796,Program Memory 32-bit word" line.long 0xB18 "IME3_PROGRAMBUFFER_m_1797,Program Memory 32-bit word" line.long 0xB1C "IME3_PROGRAMBUFFER_m_1798,Program Memory 32-bit word" line.long 0xB20 "IME3_PROGRAMBUFFER_m_1799,Program Memory 32-bit word" line.long 0xB24 "IME3_PROGRAMBUFFER_m_1800,Program Memory 32-bit word" line.long 0xB28 "IME3_PROGRAMBUFFER_m_1801,Program Memory 32-bit word" line.long 0xB2C "IME3_PROGRAMBUFFER_m_1802,Program Memory 32-bit word" line.long 0xB30 "IME3_PROGRAMBUFFER_m_1803,Program Memory 32-bit word" line.long 0xB34 "IME3_PROGRAMBUFFER_m_1804,Program Memory 32-bit word" line.long 0xB38 "IME3_PROGRAMBUFFER_m_1805,Program Memory 32-bit word" line.long 0xB3C "IME3_PROGRAMBUFFER_m_1806,Program Memory 32-bit word" line.long 0xB40 "IME3_PROGRAMBUFFER_m_1807,Program Memory 32-bit word" line.long 0xB44 "IME3_PROGRAMBUFFER_m_1808,Program Memory 32-bit word" line.long 0xB48 "IME3_PROGRAMBUFFER_m_1809,Program Memory 32-bit word" line.long 0xB4C "IME3_PROGRAMBUFFER_m_1810,Program Memory 32-bit word" line.long 0xB50 "IME3_PROGRAMBUFFER_m_1811,Program Memory 32-bit word" line.long 0xB54 "IME3_PROGRAMBUFFER_m_1812,Program Memory 32-bit word" line.long 0xB58 "IME3_PROGRAMBUFFER_m_1813,Program Memory 32-bit word" line.long 0xB5C "IME3_PROGRAMBUFFER_m_1814,Program Memory 32-bit word" line.long 0xB60 "IME3_PROGRAMBUFFER_m_1815,Program Memory 32-bit word" line.long 0xB64 "IME3_PROGRAMBUFFER_m_1816,Program Memory 32-bit word" line.long 0xB68 "IME3_PROGRAMBUFFER_m_1817,Program Memory 32-bit word" line.long 0xB6C "IME3_PROGRAMBUFFER_m_1818,Program Memory 32-bit word" line.long 0xB70 "IME3_PROGRAMBUFFER_m_1819,Program Memory 32-bit word" line.long 0xB74 "IME3_PROGRAMBUFFER_m_1820,Program Memory 32-bit word" line.long 0xB78 "IME3_PROGRAMBUFFER_m_1821,Program Memory 32-bit word" line.long 0xB7C "IME3_PROGRAMBUFFER_m_1822,Program Memory 32-bit word" line.long 0xB80 "IME3_PROGRAMBUFFER_m_1823,Program Memory 32-bit word" line.long 0xB84 "IME3_PROGRAMBUFFER_m_1824,Program Memory 32-bit word" line.long 0xB88 "IME3_PROGRAMBUFFER_m_1825,Program Memory 32-bit word" line.long 0xB8C "IME3_PROGRAMBUFFER_m_1826,Program Memory 32-bit word" line.long 0xB90 "IME3_PROGRAMBUFFER_m_1827,Program Memory 32-bit word" line.long 0xB94 "IME3_PROGRAMBUFFER_m_1828,Program Memory 32-bit word" line.long 0xB98 "IME3_PROGRAMBUFFER_m_1829,Program Memory 32-bit word" line.long 0xB9C "IME3_PROGRAMBUFFER_m_1830,Program Memory 32-bit word" line.long 0xBA0 "IME3_PROGRAMBUFFER_m_1831,Program Memory 32-bit word" line.long 0xBA4 "IME3_PROGRAMBUFFER_m_1832,Program Memory 32-bit word" line.long 0xBA8 "IME3_PROGRAMBUFFER_m_1833,Program Memory 32-bit word" line.long 0xBAC "IME3_PROGRAMBUFFER_m_1834,Program Memory 32-bit word" line.long 0xBB0 "IME3_PROGRAMBUFFER_m_1835,Program Memory 32-bit word" line.long 0xBB4 "IME3_PROGRAMBUFFER_m_1836,Program Memory 32-bit word" line.long 0xBB8 "IME3_PROGRAMBUFFER_m_1837,Program Memory 32-bit word" line.long 0xBBC "IME3_PROGRAMBUFFER_m_1838,Program Memory 32-bit word" line.long 0xBC0 "IME3_PROGRAMBUFFER_m_1839,Program Memory 32-bit word" line.long 0xBC4 "IME3_PROGRAMBUFFER_m_1840,Program Memory 32-bit word" line.long 0xBC8 "IME3_PROGRAMBUFFER_m_1841,Program Memory 32-bit word" line.long 0xBCC "IME3_PROGRAMBUFFER_m_1842,Program Memory 32-bit word" line.long 0xBD0 "IME3_PROGRAMBUFFER_m_1843,Program Memory 32-bit word" line.long 0xBD4 "IME3_PROGRAMBUFFER_m_1844,Program Memory 32-bit word" line.long 0xBD8 "IME3_PROGRAMBUFFER_m_1845,Program Memory 32-bit word" line.long 0xBDC "IME3_PROGRAMBUFFER_m_1846,Program Memory 32-bit word" line.long 0xBE0 "IME3_PROGRAMBUFFER_m_1847,Program Memory 32-bit word" line.long 0xBE4 "IME3_PROGRAMBUFFER_m_1848,Program Memory 32-bit word" line.long 0xBE8 "IME3_PROGRAMBUFFER_m_1849,Program Memory 32-bit word" line.long 0xBEC "IME3_PROGRAMBUFFER_m_1850,Program Memory 32-bit word" line.long 0xBF0 "IME3_PROGRAMBUFFER_m_1851,Program Memory 32-bit word" line.long 0xBF4 "IME3_PROGRAMBUFFER_m_1852,Program Memory 32-bit word" line.long 0xBF8 "IME3_PROGRAMBUFFER_m_1853,Program Memory 32-bit word" line.long 0xBFC "IME3_PROGRAMBUFFER_m_1854,Program Memory 32-bit word" line.long 0xC00 "IME3_PROGRAMBUFFER_m_1855,Program Memory 32-bit word" line.long 0xC04 "IME3_PROGRAMBUFFER_m_1856,Program Memory 32-bit word" line.long 0xC08 "IME3_PROGRAMBUFFER_m_1857,Program Memory 32-bit word" line.long 0xC0C "IME3_PROGRAMBUFFER_m_1858,Program Memory 32-bit word" line.long 0xC10 "IME3_PROGRAMBUFFER_m_1859,Program Memory 32-bit word" line.long 0xC14 "IME3_PROGRAMBUFFER_m_1860,Program Memory 32-bit word" line.long 0xC18 "IME3_PROGRAMBUFFER_m_1861,Program Memory 32-bit word" line.long 0xC1C "IME3_PROGRAMBUFFER_m_1862,Program Memory 32-bit word" line.long 0xC20 "IME3_PROGRAMBUFFER_m_1863,Program Memory 32-bit word" line.long 0xC24 "IME3_PROGRAMBUFFER_m_1864,Program Memory 32-bit word" line.long 0xC28 "IME3_PROGRAMBUFFER_m_1865,Program Memory 32-bit word" line.long 0xC2C "IME3_PROGRAMBUFFER_m_1866,Program Memory 32-bit word" line.long 0xC30 "IME3_PROGRAMBUFFER_m_1867,Program Memory 32-bit word" line.long 0xC34 "IME3_PROGRAMBUFFER_m_1868,Program Memory 32-bit word" line.long 0xC38 "IME3_PROGRAMBUFFER_m_1869,Program Memory 32-bit word" line.long 0xC3C "IME3_PROGRAMBUFFER_m_1870,Program Memory 32-bit word" line.long 0xC40 "IME3_PROGRAMBUFFER_m_1871,Program Memory 32-bit word" line.long 0xC44 "IME3_PROGRAMBUFFER_m_1872,Program Memory 32-bit word" line.long 0xC48 "IME3_PROGRAMBUFFER_m_1873,Program Memory 32-bit word" line.long 0xC4C "IME3_PROGRAMBUFFER_m_1874,Program Memory 32-bit word" line.long 0xC50 "IME3_PROGRAMBUFFER_m_1875,Program Memory 32-bit word" line.long 0xC54 "IME3_PROGRAMBUFFER_m_1876,Program Memory 32-bit word" line.long 0xC58 "IME3_PROGRAMBUFFER_m_1877,Program Memory 32-bit word" line.long 0xC5C "IME3_PROGRAMBUFFER_m_1878,Program Memory 32-bit word" line.long 0xC60 "IME3_PROGRAMBUFFER_m_1879,Program Memory 32-bit word" line.long 0xC64 "IME3_PROGRAMBUFFER_m_1880,Program Memory 32-bit word" line.long 0xC68 "IME3_PROGRAMBUFFER_m_1881,Program Memory 32-bit word" line.long 0xC6C "IME3_PROGRAMBUFFER_m_1882,Program Memory 32-bit word" line.long 0xC70 "IME3_PROGRAMBUFFER_m_1883,Program Memory 32-bit word" line.long 0xC74 "IME3_PROGRAMBUFFER_m_1884,Program Memory 32-bit word" line.long 0xC78 "IME3_PROGRAMBUFFER_m_1885,Program Memory 32-bit word" line.long 0xC7C "IME3_PROGRAMBUFFER_m_1886,Program Memory 32-bit word" line.long 0xC80 "IME3_PROGRAMBUFFER_m_1887,Program Memory 32-bit word" line.long 0xC84 "IME3_PROGRAMBUFFER_m_1888,Program Memory 32-bit word" line.long 0xC88 "IME3_PROGRAMBUFFER_m_1889,Program Memory 32-bit word" line.long 0xC8C "IME3_PROGRAMBUFFER_m_1890,Program Memory 32-bit word" line.long 0xC90 "IME3_PROGRAMBUFFER_m_1891,Program Memory 32-bit word" line.long 0xC94 "IME3_PROGRAMBUFFER_m_1892,Program Memory 32-bit word" line.long 0xC98 "IME3_PROGRAMBUFFER_m_1893,Program Memory 32-bit word" line.long 0xC9C "IME3_PROGRAMBUFFER_m_1894,Program Memory 32-bit word" line.long 0xCA0 "IME3_PROGRAMBUFFER_m_1895,Program Memory 32-bit word" line.long 0xCA4 "IME3_PROGRAMBUFFER_m_1896,Program Memory 32-bit word" line.long 0xCA8 "IME3_PROGRAMBUFFER_m_1897,Program Memory 32-bit word" line.long 0xCAC "IME3_PROGRAMBUFFER_m_1898,Program Memory 32-bit word" line.long 0xCB0 "IME3_PROGRAMBUFFER_m_1899,Program Memory 32-bit word" line.long 0xCB4 "IME3_PROGRAMBUFFER_m_1900,Program Memory 32-bit word" line.long 0xCB8 "IME3_PROGRAMBUFFER_m_1901,Program Memory 32-bit word" line.long 0xCBC "IME3_PROGRAMBUFFER_m_1902,Program Memory 32-bit word" line.long 0xCC0 "IME3_PROGRAMBUFFER_m_1903,Program Memory 32-bit word" line.long 0xCC4 "IME3_PROGRAMBUFFER_m_1904,Program Memory 32-bit word" line.long 0xCC8 "IME3_PROGRAMBUFFER_m_1905,Program Memory 32-bit word" line.long 0xCCC "IME3_PROGRAMBUFFER_m_1906,Program Memory 32-bit word" line.long 0xCD0 "IME3_PROGRAMBUFFER_m_1907,Program Memory 32-bit word" line.long 0xCD4 "IME3_PROGRAMBUFFER_m_1908,Program Memory 32-bit word" line.long 0xCD8 "IME3_PROGRAMBUFFER_m_1909,Program Memory 32-bit word" line.long 0xCDC "IME3_PROGRAMBUFFER_m_1910,Program Memory 32-bit word" line.long 0xCE0 "IME3_PROGRAMBUFFER_m_1911,Program Memory 32-bit word" line.long 0xCE4 "IME3_PROGRAMBUFFER_m_1912,Program Memory 32-bit word" line.long 0xCE8 "IME3_PROGRAMBUFFER_m_1913,Program Memory 32-bit word" line.long 0xCEC "IME3_PROGRAMBUFFER_m_1914,Program Memory 32-bit word" line.long 0xCF0 "IME3_PROGRAMBUFFER_m_1915,Program Memory 32-bit word" line.long 0xCF4 "IME3_PROGRAMBUFFER_m_1916,Program Memory 32-bit word" line.long 0xCF8 "IME3_PROGRAMBUFFER_m_1917,Program Memory 32-bit word" line.long 0xCFC "IME3_PROGRAMBUFFER_m_1918,Program Memory 32-bit word" line.long 0xD00 "IME3_PROGRAMBUFFER_m_1919,Program Memory 32-bit word" line.long 0xD04 "IME3_PROGRAMBUFFER_m_1920,Program Memory 32-bit word" line.long 0xD08 "IME3_PROGRAMBUFFER_m_1921,Program Memory 32-bit word" line.long 0xD0C "IME3_PROGRAMBUFFER_m_1922,Program Memory 32-bit word" line.long 0xD10 "IME3_PROGRAMBUFFER_m_1923,Program Memory 32-bit word" line.long 0xD14 "IME3_PROGRAMBUFFER_m_1924,Program Memory 32-bit word" line.long 0xD18 "IME3_PROGRAMBUFFER_m_1925,Program Memory 32-bit word" line.long 0xD1C "IME3_PROGRAMBUFFER_m_1926,Program Memory 32-bit word" line.long 0xD20 "IME3_PROGRAMBUFFER_m_1927,Program Memory 32-bit word" line.long 0xD24 "IME3_PROGRAMBUFFER_m_1928,Program Memory 32-bit word" line.long 0xD28 "IME3_PROGRAMBUFFER_m_1929,Program Memory 32-bit word" line.long 0xD2C "IME3_PROGRAMBUFFER_m_1930,Program Memory 32-bit word" line.long 0xD30 "IME3_PROGRAMBUFFER_m_1931,Program Memory 32-bit word" line.long 0xD34 "IME3_PROGRAMBUFFER_m_1932,Program Memory 32-bit word" line.long 0xD38 "IME3_PROGRAMBUFFER_m_1933,Program Memory 32-bit word" line.long 0xD3C "IME3_PROGRAMBUFFER_m_1934,Program Memory 32-bit word" line.long 0xD40 "IME3_PROGRAMBUFFER_m_1935,Program Memory 32-bit word" line.long 0xD44 "IME3_PROGRAMBUFFER_m_1936,Program Memory 32-bit word" line.long 0xD48 "IME3_PROGRAMBUFFER_m_1937,Program Memory 32-bit word" line.long 0xD4C "IME3_PROGRAMBUFFER_m_1938,Program Memory 32-bit word" line.long 0xD50 "IME3_PROGRAMBUFFER_m_1939,Program Memory 32-bit word" line.long 0xD54 "IME3_PROGRAMBUFFER_m_1940,Program Memory 32-bit word" line.long 0xD58 "IME3_PROGRAMBUFFER_m_1941,Program Memory 32-bit word" line.long 0xD5C "IME3_PROGRAMBUFFER_m_1942,Program Memory 32-bit word" line.long 0xD60 "IME3_PROGRAMBUFFER_m_1943,Program Memory 32-bit word" line.long 0xD64 "IME3_PROGRAMBUFFER_m_1944,Program Memory 32-bit word" line.long 0xD68 "IME3_PROGRAMBUFFER_m_1945,Program Memory 32-bit word" line.long 0xD6C "IME3_PROGRAMBUFFER_m_1946,Program Memory 32-bit word" line.long 0xD70 "IME3_PROGRAMBUFFER_m_1947,Program Memory 32-bit word" line.long 0xD74 "IME3_PROGRAMBUFFER_m_1948,Program Memory 32-bit word" line.long 0xD78 "IME3_PROGRAMBUFFER_m_1949,Program Memory 32-bit word" line.long 0xD7C "IME3_PROGRAMBUFFER_m_1950,Program Memory 32-bit word" line.long 0xD80 "IME3_PROGRAMBUFFER_m_1951,Program Memory 32-bit word" line.long 0xD84 "IME3_PROGRAMBUFFER_m_1952,Program Memory 32-bit word" line.long 0xD88 "IME3_PROGRAMBUFFER_m_1953,Program Memory 32-bit word" line.long 0xD8C "IME3_PROGRAMBUFFER_m_1954,Program Memory 32-bit word" line.long 0xD90 "IME3_PROGRAMBUFFER_m_1955,Program Memory 32-bit word" line.long 0xD94 "IME3_PROGRAMBUFFER_m_1956,Program Memory 32-bit word" line.long 0xD98 "IME3_PROGRAMBUFFER_m_1957,Program Memory 32-bit word" line.long 0xD9C "IME3_PROGRAMBUFFER_m_1958,Program Memory 32-bit word" line.long 0xDA0 "IME3_PROGRAMBUFFER_m_1959,Program Memory 32-bit word" line.long 0xDA4 "IME3_PROGRAMBUFFER_m_1960,Program Memory 32-bit word" line.long 0xDA8 "IME3_PROGRAMBUFFER_m_1961,Program Memory 32-bit word" line.long 0xDAC "IME3_PROGRAMBUFFER_m_1962,Program Memory 32-bit word" line.long 0xDB0 "IME3_PROGRAMBUFFER_m_1963,Program Memory 32-bit word" line.long 0xDB4 "IME3_PROGRAMBUFFER_m_1964,Program Memory 32-bit word" line.long 0xDB8 "IME3_PROGRAMBUFFER_m_1965,Program Memory 32-bit word" line.long 0xDBC "IME3_PROGRAMBUFFER_m_1966,Program Memory 32-bit word" line.long 0xDC0 "IME3_PROGRAMBUFFER_m_1967,Program Memory 32-bit word" line.long 0xDC4 "IME3_PROGRAMBUFFER_m_1968,Program Memory 32-bit word" line.long 0xDC8 "IME3_PROGRAMBUFFER_m_1969,Program Memory 32-bit word" line.long 0xDCC "IME3_PROGRAMBUFFER_m_1970,Program Memory 32-bit word" line.long 0xDD0 "IME3_PROGRAMBUFFER_m_1971,Program Memory 32-bit word" line.long 0xDD4 "IME3_PROGRAMBUFFER_m_1972,Program Memory 32-bit word" line.long 0xDD8 "IME3_PROGRAMBUFFER_m_1973,Program Memory 32-bit word" line.long 0xDDC "IME3_PROGRAMBUFFER_m_1974,Program Memory 32-bit word" line.long 0xDE0 "IME3_PROGRAMBUFFER_m_1975,Program Memory 32-bit word" line.long 0xDE4 "IME3_PROGRAMBUFFER_m_1976,Program Memory 32-bit word" line.long 0xDE8 "IME3_PROGRAMBUFFER_m_1977,Program Memory 32-bit word" line.long 0xDEC "IME3_PROGRAMBUFFER_m_1978,Program Memory 32-bit word" line.long 0xDF0 "IME3_PROGRAMBUFFER_m_1979,Program Memory 32-bit word" line.long 0xDF4 "IME3_PROGRAMBUFFER_m_1980,Program Memory 32-bit word" line.long 0xDF8 "IME3_PROGRAMBUFFER_m_1981,Program Memory 32-bit word" line.long 0xDFC "IME3_PROGRAMBUFFER_m_1982,Program Memory 32-bit word" line.long 0xE00 "IME3_PROGRAMBUFFER_m_1983,Program Memory 32-bit word" line.long 0xE04 "IME3_PROGRAMBUFFER_m_1984,Program Memory 32-bit word" line.long 0xE08 "IME3_PROGRAMBUFFER_m_1985,Program Memory 32-bit word" line.long 0xE0C "IME3_PROGRAMBUFFER_m_1986,Program Memory 32-bit word" line.long 0xE10 "IME3_PROGRAMBUFFER_m_1987,Program Memory 32-bit word" line.long 0xE14 "IME3_PROGRAMBUFFER_m_1988,Program Memory 32-bit word" line.long 0xE18 "IME3_PROGRAMBUFFER_m_1989,Program Memory 32-bit word" line.long 0xE1C "IME3_PROGRAMBUFFER_m_1990,Program Memory 32-bit word" line.long 0xE20 "IME3_PROGRAMBUFFER_m_1991,Program Memory 32-bit word" line.long 0xE24 "IME3_PROGRAMBUFFER_m_1992,Program Memory 32-bit word" line.long 0xE28 "IME3_PROGRAMBUFFER_m_1993,Program Memory 32-bit word" line.long 0xE2C "IME3_PROGRAMBUFFER_m_1994,Program Memory 32-bit word" line.long 0xE30 "IME3_PROGRAMBUFFER_m_1995,Program Memory 32-bit word" line.long 0xE34 "IME3_PROGRAMBUFFER_m_1996,Program Memory 32-bit word" line.long 0xE38 "IME3_PROGRAMBUFFER_m_1997,Program Memory 32-bit word" line.long 0xE3C "IME3_PROGRAMBUFFER_m_1998,Program Memory 32-bit word" line.long 0xE40 "IME3_PROGRAMBUFFER_m_1999,Program Memory 32-bit word" line.long 0xE44 "IME3_PROGRAMBUFFER_m_2000,Program Memory 32-bit word" line.long 0xE48 "IME3_PROGRAMBUFFER_m_2001,Program Memory 32-bit word" line.long 0xE4C "IME3_PROGRAMBUFFER_m_2002,Program Memory 32-bit word" line.long 0xE50 "IME3_PROGRAMBUFFER_m_2003,Program Memory 32-bit word" line.long 0xE54 "IME3_PROGRAMBUFFER_m_2004,Program Memory 32-bit word" line.long 0xE58 "IME3_PROGRAMBUFFER_m_2005,Program Memory 32-bit word" line.long 0xE5C "IME3_PROGRAMBUFFER_m_2006,Program Memory 32-bit word" line.long 0xE60 "IME3_PROGRAMBUFFER_m_2007,Program Memory 32-bit word" line.long 0xE64 "IME3_PROGRAMBUFFER_m_2008,Program Memory 32-bit word" line.long 0xE68 "IME3_PROGRAMBUFFER_m_2009,Program Memory 32-bit word" line.long 0xE6C "IME3_PROGRAMBUFFER_m_2010,Program Memory 32-bit word" line.long 0xE70 "IME3_PROGRAMBUFFER_m_2011,Program Memory 32-bit word" line.long 0xE74 "IME3_PROGRAMBUFFER_m_2012,Program Memory 32-bit word" line.long 0xE78 "IME3_PROGRAMBUFFER_m_2013,Program Memory 32-bit word" line.long 0xE7C "IME3_PROGRAMBUFFER_m_2014,Program Memory 32-bit word" line.long 0xE80 "IME3_PROGRAMBUFFER_m_2015,Program Memory 32-bit word" line.long 0xE84 "IME3_PROGRAMBUFFER_m_2016,Program Memory 32-bit word" line.long 0xE88 "IME3_PROGRAMBUFFER_m_2017,Program Memory 32-bit word" line.long 0xE8C "IME3_PROGRAMBUFFER_m_2018,Program Memory 32-bit word" line.long 0xE90 "IME3_PROGRAMBUFFER_m_2019,Program Memory 32-bit word" line.long 0xE94 "IME3_PROGRAMBUFFER_m_2020,Program Memory 32-bit word" line.long 0xE98 "IME3_PROGRAMBUFFER_m_2021,Program Memory 32-bit word" line.long 0xE9C "IME3_PROGRAMBUFFER_m_2022,Program Memory 32-bit word" line.long 0xEA0 "IME3_PROGRAMBUFFER_m_2023,Program Memory 32-bit word" line.long 0xEA4 "IME3_PROGRAMBUFFER_m_2024,Program Memory 32-bit word" line.long 0xEA8 "IME3_PROGRAMBUFFER_m_2025,Program Memory 32-bit word" line.long 0xEAC "IME3_PROGRAMBUFFER_m_2026,Program Memory 32-bit word" line.long 0xEB0 "IME3_PROGRAMBUFFER_m_2027,Program Memory 32-bit word" line.long 0xEB4 "IME3_PROGRAMBUFFER_m_2028,Program Memory 32-bit word" line.long 0xEB8 "IME3_PROGRAMBUFFER_m_2029,Program Memory 32-bit word" line.long 0xEBC "IME3_PROGRAMBUFFER_m_2030,Program Memory 32-bit word" line.long 0xEC0 "IME3_PROGRAMBUFFER_m_2031,Program Memory 32-bit word" line.long 0xEC4 "IME3_PROGRAMBUFFER_m_2032,Program Memory 32-bit word" line.long 0xEC8 "IME3_PROGRAMBUFFER_m_2033,Program Memory 32-bit word" line.long 0xECC "IME3_PROGRAMBUFFER_m_2034,Program Memory 32-bit word" line.long 0xED0 "IME3_PROGRAMBUFFER_m_2035,Program Memory 32-bit word" line.long 0xED4 "IME3_PROGRAMBUFFER_m_2036,Program Memory 32-bit word" line.long 0xED8 "IME3_PROGRAMBUFFER_m_2037,Program Memory 32-bit word" line.long 0xEDC "IME3_PROGRAMBUFFER_m_2038,Program Memory 32-bit word" line.long 0xEE0 "IME3_PROGRAMBUFFER_m_2039,Program Memory 32-bit word" line.long 0xEE4 "IME3_PROGRAMBUFFER_m_2040,Program Memory 32-bit word" line.long 0xEE8 "IME3_PROGRAMBUFFER_m_2041,Program Memory 32-bit word" line.long 0xEEC "IME3_PROGRAMBUFFER_m_2042,Program Memory 32-bit word" line.long 0xEF0 "IME3_PROGRAMBUFFER_m_2043,Program Memory 32-bit word" line.long 0xEF4 "IME3_PROGRAMBUFFER_m_2044,Program Memory 32-bit word" line.long 0xEF8 "IME3_PROGRAMBUFFER_m_2045,Program Memory 32-bit word" line.long 0xEFC "IME3_PROGRAMBUFFER_m_2046,Program Memory 32-bit word" line.long 0xF00 "IME3_PROGRAMBUFFER_m_2047,Program Memory 32-bit word" tree.end tree "Channel_7" group.long 0x338++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3B8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_7,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x33C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3BC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x11C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_7,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x238++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_7,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_7,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x9C++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_7,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x201C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_7,Program Memory 32-bit word" tree.end tree "Channel_8" group.long 0x340++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3C0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_8,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x344++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3C4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x120++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_8,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x240++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_8,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_8,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_8,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2020++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_8,Program Memory 32-bit word" tree.end tree "Channel_9" group.long 0x348++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3C8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_9,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x34C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3CC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x124++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_9,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x248++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_9,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_9,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_9,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2024++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_9,Program Memory 32-bit word" tree.end group.long 0x450++0x07 line.long 0x00 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION0,Current position in the circular buffer" hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" line.long 0x04 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION1," hexmask.long.word 0x04 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x04 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" group.long 0x428++0x07 line.long 0x00 "IME3_CIRCULAR_BUFFER_DESC0,Circular Buffer 0" bitfld.long 0x00 24. "DIRECTION,Horizontal or Vertical Circularity" "DIRECTION_0,DIRECTION_1" hexmask.long.byte 0x00 16.--23. 1. "OFFSET,In MBs" newline hexmask.long.byte 0x00 8.--15. 1. "CBW,Circular Buffer Width in MBs" hexmask.long.byte 0x00 0.--7. 1. "CBH,Circular Buffer Height in MBs" line.long 0x04 "IME3_CIRCULAR_BUFFER_DESC1,Circular Buffer 1" bitfld.long 0x04 24. "DIRECTION,Horizontal or Vertical Circularity" "DIRECTION_0,DIRECTION_1" hexmask.long.byte 0x04 16.--23. 1. "OFFSET,In MBs" newline hexmask.long.byte 0x04 8.--15. 1. "CBW,Circular Buffer Width in MBs" hexmask.long.byte 0x04 0.--7. 1. "CBH,Circular Buffer Height in MBs" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x474)++0x03 line.long 0x00 "IME3_CIRCULAR_BUFFER_SLIDING_POSITION$1," hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer (X coordinate pixel precision)" repeat.end group.long 0x1FFC++0x03 line.long 0x00 "IME3_COMMANDREG,IME3 command register: a write to this register decodes a command. a read returns 0" group.long 0x440++0x03 line.long 0x00 "IME3_CONDITIONREGISTER,Absolute Minimum Reached bit register. used in Mcomp() operator" hexmask.long.byte 0x00 24.--31. 1. "APPLICATIONCOUNTER1,Counter 1" hexmask.long.byte 0x00 16.--23. 1. "APPLICATIONCOUNTER0,Counter 0" newline bitfld.long 0x00 11. "PARTITIONVALID,Reset by ClearStatus()" "PARTITIONVALID_0,PARTITIONVALID_1" bitfld.long 0x00 9.--10. "BOTTOMRIGHTREFERENCE,L0 L1 Bi" "BOTTOMRIGHTREFERENCE_0,BOTTOMRIGHTREFERENCE_1,BOTTOMRIGHTREFERENCE_2,BOTTOMRIGHTREFERENCE_3" newline bitfld.long 0x00 7.--8. "BOTTOMLEFTREFERENCE,L0 L1 Bi" "BOTTOMLEFTREFERENCE_0,BOTTOMLEFTREFERENCE_1,BOTTOMLEFTREFERENCE_2,BOTTOMLEFTREFERENCE_3" bitfld.long 0x00 5.--6. "TOPRIGHTREFERENCE,L0 L1 Bi" "TOPRIGHTREFERENCE_0,TOPRIGHTREFERENCE_1,TOPRIGHTREFERENCE_2,TOPRIGHTREFERENCE_3" newline bitfld.long 0x00 3.--4. "TOPLEFTREFERENCE,L0 L1 Bi" "TOPLEFTREFERENCE_0,TOPLEFTREFERENCE_1,TOPLEFTREFERENCE_2,TOPLEFTREFERENCE_3" bitfld.long 0x00 1.--2. "PARTITIONTYPE,16x16 16x8 8x16 8x8" "PARTITIONTYPE_0,PARTITIONTYPE_1,PARTITIONTYPE_2,PARTITIONTYPE_3" newline bitfld.long 0x00 0. "ABSMINREACHED,Abs Min Reached bit in Mcomp block" "ABSMINREACHED_0,ABSMINREACHED_1" group.long 0x430++0x07 line.long 0x00 "IME3_CPUSTATUSREG,CPU Status Register provides information on the progress of the CPU execution" bitfld.long 0x00 31. "START_OR_STEP_TAKEN,Set to 1 when Step() Local Interconnect command is received" "START_OR_STEP_TAKEN_0,START_OR_STEP_TAKEN_1" rbitfld.long 0x00 30. "DETECTEDENDOFPGM,This bit is set to '1' when in Debug mode an EndOfPgm instruction or the last instruction of ProgramBuffer has been reached" "DETECTEDENDOFPGM_0,DETECTEDENDOFPGM_1" newline rbitfld.long 0x00 29. "DETECTEDSTOP,This bit is set to '1' when a Stop() command is received" "DETECTEDSTOP_0,DETECTEDSTOP_1" rbitfld.long 0x00 28. "REJECTED_ACCESS,Set when a Local Interconnect read to the Program Memory or an Local Interconnect write are perfromed while the IME3 is still in the EXECUTING state" "0,1" newline bitfld.long 0x00 24.--25. "EXECSTATE," "?,> Halted,> Exectuting,> Completed" rbitfld.long 0x00 19. "RECEIVEDSIGNAL1,Indicates that module has received a Local Interconnect Signal1 Command" "RECEIVEDSIGNAL1_0,RECEIVEDSIGNAL1_1" newline rbitfld.long 0x00 18. "WAITINGONSIGNAL1,Indicates that module is waiting for Local Interconnect Signal1 Command" "WAITINGONSIGNAL1_0,WAITINGONSIGNAL1_1" rbitfld.long 0x00 17. "RECEIVEDSIGNAL0,Indicates that module has received a Local Interconnect Signal0 Command" "RECEIVEDSIGNAL0_0,RECEIVEDSIGNAL0_1" newline rbitfld.long 0x00 16. "WAITINGONSIGNAL0,Indicates that module is waiting for Local Interconnect Signal0 Command" "WAITINGONSIGNAL0_0,WAITINGONSIGNAL0_1" hexmask.long.word 0x00 0.--15. 1. "PC,Address of the instruction currently issued" line.long 0x04 "IME3_CYCLECOUNT,Cycle count register" bitfld.long 0x04 31. "CYCLECOUNTENABLE,When set to 1 cycle counting is enabled" "CYCLECOUNTENABLE_0,CYCLECOUNTENABLE_1" bitfld.long 0x04 30. "CYCLECOUNTRESET,Writing 0 results in no effect" "CYCLECOUNTRESET_0,CYCLECOUNTRESET_1" newline hexmask.long.word 0x04 0.--15. 1. "CYCLECOUNT,Incremets at each cycle if cycleCountEnable equals 1 and if CpuState is EXECUTING" group.long 0x470++0x03 line.long 0x00 "IME3_INTERPOLATION_REFERENCE,The Interpol Reference is the MV based on which the last interpolation has been performed" hexmask.long.word 0x00 16.--31. 1. "Y,This is the 'y' coordinate of the {0 0} point of the interpol planes" hexmask.long.word 0x00 0.--15. 1. "X,x coordinate for the origin point of the interpolation" hgroup.long 0x20++0x03 hide.long 0x00 "IME3_IRQ_EOI,End Of Interrupt number specification" group.long 0x30++0x03 line.long 0x00 "IME3_IRQENABLE_CLR,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x2C++0x03 line.long 0x00 "IME3_IRQENABLE_SET,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x28++0x03 line.long 0x00 "IME3_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Clearable enabled status for event #1 (Gen_it) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x24++0x03 line.long 0x00 "IME3_IRQSTATUS_RAW,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Settable raw status for event #1 (Gen_It) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Settable raw status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x44C++0x03 line.long 0x00 "IME3_MINERRORTHRESHOLD,Minimum Error Threshold register. used in Mcomp() operator" hexmask.long.word 0x00 0.--15. 1. "MINTHRESHOLD,Min Threshold value in Mcomp() block" group.long 0x400++0x03 line.long 0x00 "IME3_MVCT0_3,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_3,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_2,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_1,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_0,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40C++0x03 line.long 0x00 "IME3_MVCT12_14,MV Cost Table" bitfld.long 0x00 16.--20. "MVCT_14,MV Cost Table 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "MVCT_13,MV Cost Table 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "MVCT_12,MV Cost Table 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x404++0x07 line.long 0x00 "IME3_MVCT4_7,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_7,MV Cost Table 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_6,MV Cost Table 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_5,MV Cost Table 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_4,MV Cost Table 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IME3_MVCT8_11,MV Cost Table" bitfld.long 0x04 24.--28. "MVCT_11,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "MVCT_10,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. "MVCT_9,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. "MVCT_8,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x00++0x03 line.long 0x00 "IME3_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "IME3_SYSCONFIG,Clock management configuration" rbitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0_r,?,?,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "?,FREEEMU_1_r" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_r" group.long 0x45C++0x03 line.long 0x00 "IME3_VALID_AREA0_BOTTOM_RIGHT_COORDINATES,Bottom right coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x458++0x03 line.long 0x00 "IME3_VALID_AREA0_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area top left limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x460++0x03 line.long 0x00 "IME3_VALID_AREA1_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x414++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_HI,horizontal vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x410++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_LO,horizontal vector variable (lower bits)" group.long 0x41C++0x03 line.long 0x00 "IME3_VEC_VAR_VER_HI,vertical vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x418++0x03 line.long 0x00 "IME3_VEC_VAR_VER_LO,vertical vector variable (lower bits)" group.long 0x420++0x07 line.long 0x00 "IME3_VECABSMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_ABS_MEAN_HOR,Accumulates |BMT0[0].dx|" line.long 0x04 "IME3_VECABSMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_ABS_MEAN_VER,Accumulates |BMT0[0].dy|" group.long 0x468++0x07 line.long 0x00 "IME3_VECMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_MEAN_HOR,Accumulates BMT0[0].dx" line.long 0x04 "IME3_VECMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_MEAN_VER,Accumulates BMT0[0].dy" width 0x0B tree.end tree "IME3_L3Interconnect" base ad:0x5A054000 tree "Channel_0" group.long 0x300++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x380++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x304++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x384++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x100++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_0,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x200++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x40++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_0,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_0,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2000++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_0,Program Memory 32-bit word" tree.end tree "Channel_1" group.long 0x308++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x388++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_1,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x30C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x38C++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_1,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x104++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_1,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x208++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_1,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_1,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x44++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_1,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x84++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_1,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2004++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_1,Program Memory 32-bit word" tree.end tree "Channel_10" group.long 0x350++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3D0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x354++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3D4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x128++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_10,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x250++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_10,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2028++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_10,Program Memory 32-bit word" tree.end tree "Channel_11" group.long 0x358++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3D8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_11,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x35C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3DC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_11,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x12C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_11,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x258++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_11,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_11,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xAC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_11,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x202C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_11,Program Memory 32-bit word" tree.end tree "Channel_12" group.long 0x360++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3E0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_12,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x364++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3E4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_12,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x130++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_12,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x260++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_12,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_12,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_12,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2030++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_12,Program Memory 32-bit word" tree.end tree "Channel_13" group.long 0x368++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3E8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_13,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x36C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3EC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_13,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x134++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_13,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x268++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_13,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_13,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_13,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2034++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_13,Program Memory 32-bit word" tree.end tree "Channel_14" group.long 0x370++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3F0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_14,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x374++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3F4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_14,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x138++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_14,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x270++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_14,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_14,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xB8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_14,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2038++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_14,Program Memory 32-bit word" tree.end tree "Channel_15" group.long 0x378++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3F8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_15,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x37C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3FC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_15,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x13C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_15,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x278++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_15,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_15,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xBC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_15,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x203C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_15,Program Memory 32-bit word" tree.end tree "Channel_16" group.long 0x140++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_16,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x280++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_16,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2040++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_16,Program Memory 32-bit word" tree.end tree "Channel_17" group.long 0x144++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_17,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x288++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_17,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_17,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_17,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2044++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_17,Program Memory 32-bit word" tree.end tree "Channel_18" group.long 0x148++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_18,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x290++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_18,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_18,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_18,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2048++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_18,Program Memory 32-bit word" tree.end tree "Channel_19" group.long 0x14C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_19,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x298++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_19,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_19,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xCC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_19,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x204C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_19,Program Memory 32-bit word" tree.end tree "Channel_2" group.long 0x310++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x390++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_2,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x314++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x394++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_2,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x108++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_2,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x210++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_2,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_2,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x48++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_2,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_2,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2008++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_2,Program Memory 32-bit word" tree.end tree "Channel_20" group.long 0x150++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_20,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2A0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_20,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_20,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_20,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2050++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_20,Program Memory 32-bit word" tree.end tree "Channel_21" group.long 0x154++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_21,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2A8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_21,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_21,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_21,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2054++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_21,Program Memory 32-bit word" tree.end tree "Channel_22" group.long 0x158++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_22,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2B0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_22,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_22,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xD8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_22,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2058++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_22,Program Memory 32-bit word" tree.end tree "Channel_23" group.long 0x15C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_23,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2B8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_23,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_23,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xDC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_23,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x205C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_23,Program Memory 32-bit word" tree.end tree "Channel_24" group.long 0x160++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_24,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2C0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_24,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_24,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_24,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2060++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_24,Program Memory 32-bit word" tree.end tree "Channel_25" group.long 0x164++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_25,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2C8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_25,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_25,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_25,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2064++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_25,Program Memory 32-bit word" tree.end tree "Channel_26" group.long 0x168++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_26,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2D0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_26,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_26,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xE8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_26,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2068++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_26,Program Memory 32-bit word" tree.end tree "Channel_27" group.long 0x16C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_27,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2D8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_27,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_27,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xEC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_27,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x206C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_27,Program Memory 32-bit word" tree.end tree "Channel_28" group.long 0x170++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_28,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2E0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_28,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_28,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_28,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2070++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_28,Program Memory 32-bit word" tree.end tree "Channel_29" group.long 0x174++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_29,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2E8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_29,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_29,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_29,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2074++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_29,Program Memory 32-bit word" tree.end tree "Channel_3" group.long 0x318++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x398++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_3,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x31C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x39C++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_3,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x10C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_3,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x218++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_3,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_3,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x4C++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_3,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8C++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_3,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x200C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_3,Program Memory 32-bit word" tree.end tree "Channel_30" group.long 0x178++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_30,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2F0++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_30,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_30,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xF8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_30,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2078++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_30,Program Memory 32-bit word" tree.end tree "Channel_31" group.long 0x17C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_31,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2F8++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_31,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_31,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xFC++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_31,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x207C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_31,Program Memory 32-bit word" tree.end tree "Channel_32" group.long 0x180++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_32,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2080++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_32,Program Memory 32-bit word" tree.end tree "Channel_33" group.long 0x184++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_33,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2084++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_33,Program Memory 32-bit word" tree.end tree "Channel_34" group.long 0x188++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_34,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2088++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_34,Program Memory 32-bit word" tree.end tree "Channel_35" group.long 0x18C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_35,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x208C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_35,Program Memory 32-bit word" tree.end tree "Channel_36" group.long 0x190++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_36,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2090++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_36,Program Memory 32-bit word" tree.end tree "Channel_37" group.long 0x194++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_37,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2094++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_37,Program Memory 32-bit word" tree.end tree "Channel_38" group.long 0x198++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_38,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2098++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_38,Program Memory 32-bit word" tree.end tree "Channel_39" group.long 0x19C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_39,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x209C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_39,Program Memory 32-bit word" tree.end tree "Channel_4" group.long 0x320++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3A0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_4,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x324++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3A4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_4,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x110++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_4,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x220++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_4,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_4,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x90++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_4,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2010++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_4,Program Memory 32-bit word" tree.end tree "Channel_40" group.long 0x1A0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_40,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_40,Program Memory 32-bit word" tree.end tree "Channel_41" group.long 0x1A4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_41,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_41,Program Memory 32-bit word" tree.end tree "Channel_42" group.long 0x1A8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_42,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20A8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_42,Program Memory 32-bit word" tree.end tree "Channel_43" group.long 0x1AC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_43,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20AC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_43,Program Memory 32-bit word" tree.end tree "Channel_44" group.long 0x1B0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_44,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_44,Program Memory 32-bit word" tree.end tree "Channel_45" group.long 0x1B4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_45,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_45,Program Memory 32-bit word" tree.end tree "Channel_46" group.long 0x1B8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_46,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20B8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_46,Program Memory 32-bit word" tree.end tree "Channel_47" group.long 0x1BC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_47,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20BC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_47,Program Memory 32-bit word" tree.end tree "Channel_48" group.long 0x1C0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_48,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_48,Program Memory 32-bit word" tree.end tree "Channel_49" group.long 0x1C4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_49,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_49,Program Memory 32-bit word" tree.end tree "Channel_5" group.long 0x328++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3A8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_5,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x32C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3AC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_5,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x114++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_5,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x228++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_5,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_5,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x94++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_5,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2014++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_5,Program Memory 32-bit word" tree.end tree "Channel_50" group.long 0x1C8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_50,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_50,Program Memory 32-bit word" tree.end tree "Channel_51" group.long 0x1CC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_51,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20CC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_51,Program Memory 32-bit word" tree.end tree "Channel_52" group.long 0x1D0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_52,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_52,Program Memory 32-bit word" tree.end tree "Channel_53" group.long 0x1D4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_53,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_53,Program Memory 32-bit word" tree.end tree "Channel_54" group.long 0x1D8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_54,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20D8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_54,Program Memory 32-bit word" tree.end tree "Channel_55" group.long 0x1DC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_55,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20DC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_55,Program Memory 32-bit word" tree.end tree "Channel_56" group.long 0x1E0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_56,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_56,Program Memory 32-bit word" tree.end tree "Channel_57" group.long 0x1E4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_57,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_57,Program Memory 32-bit word" tree.end tree "Channel_58" group.long 0x1E8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_58,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20E8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_58,Program Memory 32-bit word" tree.end tree "Channel_59" group.long 0x1EC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_59,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20EC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_59,Program Memory 32-bit word" tree.end tree "Channel_6" group.long 0x330++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3B0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_6,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x334++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3B4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_6,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x118++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_6,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x230++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_6,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_6,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x98++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_6,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2018++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_6,Program Memory 32-bit word" tree.end tree "Channel_60" group.long 0x1F0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_60,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_60,Program Memory 32-bit word" tree.end tree "Channel_61" group.long 0x1F4++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_61,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F4++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_61,Program Memory 32-bit word" tree.end tree "Channel_62" group.long 0x1F8++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_62,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20F8++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_62,Program Memory 32-bit word" tree.end tree "Channel_63" group.long 0x1FC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_63,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20FC++0xFFF line.long 0x00 "IME3_PROGRAMBUFFER_m_63,Program Memory 32-bit word" line.long 0x04 "IME3_PROGRAMBUFFER_m_64,Program Memory 32-bit word" line.long 0x08 "IME3_PROGRAMBUFFER_m_65,Program Memory 32-bit word" line.long 0x0C "IME3_PROGRAMBUFFER_m_66,Program Memory 32-bit word" line.long 0x10 "IME3_PROGRAMBUFFER_m_67,Program Memory 32-bit word" line.long 0x14 "IME3_PROGRAMBUFFER_m_68,Program Memory 32-bit word" line.long 0x18 "IME3_PROGRAMBUFFER_m_69,Program Memory 32-bit word" line.long 0x1C "IME3_PROGRAMBUFFER_m_70,Program Memory 32-bit word" line.long 0x20 "IME3_PROGRAMBUFFER_m_71,Program Memory 32-bit word" line.long 0x24 "IME3_PROGRAMBUFFER_m_72,Program Memory 32-bit word" line.long 0x28 "IME3_PROGRAMBUFFER_m_73,Program Memory 32-bit word" line.long 0x2C "IME3_PROGRAMBUFFER_m_74,Program Memory 32-bit word" line.long 0x30 "IME3_PROGRAMBUFFER_m_75,Program Memory 32-bit word" line.long 0x34 "IME3_PROGRAMBUFFER_m_76,Program Memory 32-bit word" line.long 0x38 "IME3_PROGRAMBUFFER_m_77,Program Memory 32-bit word" line.long 0x3C "IME3_PROGRAMBUFFER_m_78,Program Memory 32-bit word" line.long 0x40 "IME3_PROGRAMBUFFER_m_79,Program Memory 32-bit word" line.long 0x44 "IME3_PROGRAMBUFFER_m_80,Program Memory 32-bit word" line.long 0x48 "IME3_PROGRAMBUFFER_m_81,Program Memory 32-bit word" line.long 0x4C "IME3_PROGRAMBUFFER_m_82,Program Memory 32-bit word" line.long 0x50 "IME3_PROGRAMBUFFER_m_83,Program Memory 32-bit word" line.long 0x54 "IME3_PROGRAMBUFFER_m_84,Program Memory 32-bit word" line.long 0x58 "IME3_PROGRAMBUFFER_m_85,Program Memory 32-bit word" line.long 0x5C "IME3_PROGRAMBUFFER_m_86,Program Memory 32-bit word" line.long 0x60 "IME3_PROGRAMBUFFER_m_87,Program Memory 32-bit word" line.long 0x64 "IME3_PROGRAMBUFFER_m_88,Program Memory 32-bit word" line.long 0x68 "IME3_PROGRAMBUFFER_m_89,Program Memory 32-bit word" line.long 0x6C "IME3_PROGRAMBUFFER_m_90,Program Memory 32-bit word" line.long 0x70 "IME3_PROGRAMBUFFER_m_91,Program Memory 32-bit word" line.long 0x74 "IME3_PROGRAMBUFFER_m_92,Program Memory 32-bit word" line.long 0x78 "IME3_PROGRAMBUFFER_m_93,Program Memory 32-bit word" line.long 0x7C "IME3_PROGRAMBUFFER_m_94,Program Memory 32-bit word" line.long 0x80 "IME3_PROGRAMBUFFER_m_95,Program Memory 32-bit word" line.long 0x84 "IME3_PROGRAMBUFFER_m_96,Program Memory 32-bit word" line.long 0x88 "IME3_PROGRAMBUFFER_m_97,Program Memory 32-bit word" line.long 0x8C "IME3_PROGRAMBUFFER_m_98,Program Memory 32-bit word" line.long 0x90 "IME3_PROGRAMBUFFER_m_99,Program Memory 32-bit word" line.long 0x94 "IME3_PROGRAMBUFFER_m_100,Program Memory 32-bit word" line.long 0x98 "IME3_PROGRAMBUFFER_m_101,Program Memory 32-bit word" line.long 0x9C "IME3_PROGRAMBUFFER_m_102,Program Memory 32-bit word" line.long 0xA0 "IME3_PROGRAMBUFFER_m_103,Program Memory 32-bit word" line.long 0xA4 "IME3_PROGRAMBUFFER_m_104,Program Memory 32-bit word" line.long 0xA8 "IME3_PROGRAMBUFFER_m_105,Program Memory 32-bit word" line.long 0xAC "IME3_PROGRAMBUFFER_m_106,Program Memory 32-bit word" line.long 0xB0 "IME3_PROGRAMBUFFER_m_107,Program Memory 32-bit word" line.long 0xB4 "IME3_PROGRAMBUFFER_m_108,Program Memory 32-bit word" line.long 0xB8 "IME3_PROGRAMBUFFER_m_109,Program Memory 32-bit word" line.long 0xBC "IME3_PROGRAMBUFFER_m_110,Program Memory 32-bit word" line.long 0xC0 "IME3_PROGRAMBUFFER_m_111,Program Memory 32-bit word" line.long 0xC4 "IME3_PROGRAMBUFFER_m_112,Program Memory 32-bit word" line.long 0xC8 "IME3_PROGRAMBUFFER_m_113,Program Memory 32-bit word" line.long 0xCC "IME3_PROGRAMBUFFER_m_114,Program Memory 32-bit word" line.long 0xD0 "IME3_PROGRAMBUFFER_m_115,Program Memory 32-bit word" line.long 0xD4 "IME3_PROGRAMBUFFER_m_116,Program Memory 32-bit word" line.long 0xD8 "IME3_PROGRAMBUFFER_m_117,Program Memory 32-bit word" line.long 0xDC "IME3_PROGRAMBUFFER_m_118,Program Memory 32-bit word" line.long 0xE0 "IME3_PROGRAMBUFFER_m_119,Program Memory 32-bit word" line.long 0xE4 "IME3_PROGRAMBUFFER_m_120,Program Memory 32-bit word" line.long 0xE8 "IME3_PROGRAMBUFFER_m_121,Program Memory 32-bit word" line.long 0xEC "IME3_PROGRAMBUFFER_m_122,Program Memory 32-bit word" line.long 0xF0 "IME3_PROGRAMBUFFER_m_123,Program Memory 32-bit word" line.long 0xF4 "IME3_PROGRAMBUFFER_m_124,Program Memory 32-bit word" line.long 0xF8 "IME3_PROGRAMBUFFER_m_125,Program Memory 32-bit word" line.long 0xFC "IME3_PROGRAMBUFFER_m_126,Program Memory 32-bit word" line.long 0x100 "IME3_PROGRAMBUFFER_m_127,Program Memory 32-bit word" line.long 0x104 "IME3_PROGRAMBUFFER_m_128,Program Memory 32-bit word" line.long 0x108 "IME3_PROGRAMBUFFER_m_129,Program Memory 32-bit word" line.long 0x10C "IME3_PROGRAMBUFFER_m_130,Program Memory 32-bit word" line.long 0x110 "IME3_PROGRAMBUFFER_m_131,Program Memory 32-bit word" line.long 0x114 "IME3_PROGRAMBUFFER_m_132,Program Memory 32-bit word" line.long 0x118 "IME3_PROGRAMBUFFER_m_133,Program Memory 32-bit word" line.long 0x11C "IME3_PROGRAMBUFFER_m_134,Program Memory 32-bit word" line.long 0x120 "IME3_PROGRAMBUFFER_m_135,Program Memory 32-bit word" line.long 0x124 "IME3_PROGRAMBUFFER_m_136,Program Memory 32-bit word" line.long 0x128 "IME3_PROGRAMBUFFER_m_137,Program Memory 32-bit word" line.long 0x12C "IME3_PROGRAMBUFFER_m_138,Program Memory 32-bit word" line.long 0x130 "IME3_PROGRAMBUFFER_m_139,Program Memory 32-bit word" line.long 0x134 "IME3_PROGRAMBUFFER_m_140,Program Memory 32-bit word" line.long 0x138 "IME3_PROGRAMBUFFER_m_141,Program Memory 32-bit word" line.long 0x13C "IME3_PROGRAMBUFFER_m_142,Program Memory 32-bit word" line.long 0x140 "IME3_PROGRAMBUFFER_m_143,Program Memory 32-bit word" line.long 0x144 "IME3_PROGRAMBUFFER_m_144,Program Memory 32-bit word" line.long 0x148 "IME3_PROGRAMBUFFER_m_145,Program Memory 32-bit word" line.long 0x14C "IME3_PROGRAMBUFFER_m_146,Program Memory 32-bit word" line.long 0x150 "IME3_PROGRAMBUFFER_m_147,Program Memory 32-bit word" line.long 0x154 "IME3_PROGRAMBUFFER_m_148,Program Memory 32-bit word" line.long 0x158 "IME3_PROGRAMBUFFER_m_149,Program Memory 32-bit word" line.long 0x15C "IME3_PROGRAMBUFFER_m_150,Program Memory 32-bit word" line.long 0x160 "IME3_PROGRAMBUFFER_m_151,Program Memory 32-bit word" line.long 0x164 "IME3_PROGRAMBUFFER_m_152,Program Memory 32-bit word" line.long 0x168 "IME3_PROGRAMBUFFER_m_153,Program Memory 32-bit word" line.long 0x16C "IME3_PROGRAMBUFFER_m_154,Program Memory 32-bit word" line.long 0x170 "IME3_PROGRAMBUFFER_m_155,Program Memory 32-bit word" line.long 0x174 "IME3_PROGRAMBUFFER_m_156,Program Memory 32-bit word" line.long 0x178 "IME3_PROGRAMBUFFER_m_157,Program Memory 32-bit word" line.long 0x17C "IME3_PROGRAMBUFFER_m_158,Program Memory 32-bit word" line.long 0x180 "IME3_PROGRAMBUFFER_m_159,Program Memory 32-bit word" line.long 0x184 "IME3_PROGRAMBUFFER_m_160,Program Memory 32-bit word" line.long 0x188 "IME3_PROGRAMBUFFER_m_161,Program Memory 32-bit word" line.long 0x18C "IME3_PROGRAMBUFFER_m_162,Program Memory 32-bit word" line.long 0x190 "IME3_PROGRAMBUFFER_m_163,Program Memory 32-bit word" line.long 0x194 "IME3_PROGRAMBUFFER_m_164,Program Memory 32-bit word" line.long 0x198 "IME3_PROGRAMBUFFER_m_165,Program Memory 32-bit word" line.long 0x19C "IME3_PROGRAMBUFFER_m_166,Program Memory 32-bit word" line.long 0x1A0 "IME3_PROGRAMBUFFER_m_167,Program Memory 32-bit word" line.long 0x1A4 "IME3_PROGRAMBUFFER_m_168,Program Memory 32-bit word" line.long 0x1A8 "IME3_PROGRAMBUFFER_m_169,Program Memory 32-bit word" line.long 0x1AC "IME3_PROGRAMBUFFER_m_170,Program Memory 32-bit word" line.long 0x1B0 "IME3_PROGRAMBUFFER_m_171,Program Memory 32-bit word" line.long 0x1B4 "IME3_PROGRAMBUFFER_m_172,Program Memory 32-bit word" line.long 0x1B8 "IME3_PROGRAMBUFFER_m_173,Program Memory 32-bit word" line.long 0x1BC "IME3_PROGRAMBUFFER_m_174,Program Memory 32-bit word" line.long 0x1C0 "IME3_PROGRAMBUFFER_m_175,Program Memory 32-bit word" line.long 0x1C4 "IME3_PROGRAMBUFFER_m_176,Program Memory 32-bit word" line.long 0x1C8 "IME3_PROGRAMBUFFER_m_177,Program Memory 32-bit word" line.long 0x1CC "IME3_PROGRAMBUFFER_m_178,Program Memory 32-bit word" line.long 0x1D0 "IME3_PROGRAMBUFFER_m_179,Program Memory 32-bit word" line.long 0x1D4 "IME3_PROGRAMBUFFER_m_180,Program Memory 32-bit word" line.long 0x1D8 "IME3_PROGRAMBUFFER_m_181,Program Memory 32-bit word" line.long 0x1DC "IME3_PROGRAMBUFFER_m_182,Program Memory 32-bit word" line.long 0x1E0 "IME3_PROGRAMBUFFER_m_183,Program Memory 32-bit word" line.long 0x1E4 "IME3_PROGRAMBUFFER_m_184,Program Memory 32-bit word" line.long 0x1E8 "IME3_PROGRAMBUFFER_m_185,Program Memory 32-bit word" line.long 0x1EC "IME3_PROGRAMBUFFER_m_186,Program Memory 32-bit word" line.long 0x1F0 "IME3_PROGRAMBUFFER_m_187,Program Memory 32-bit word" line.long 0x1F4 "IME3_PROGRAMBUFFER_m_188,Program Memory 32-bit word" line.long 0x1F8 "IME3_PROGRAMBUFFER_m_189,Program Memory 32-bit word" line.long 0x1FC "IME3_PROGRAMBUFFER_m_190,Program Memory 32-bit word" line.long 0x200 "IME3_PROGRAMBUFFER_m_191,Program Memory 32-bit word" line.long 0x204 "IME3_PROGRAMBUFFER_m_192,Program Memory 32-bit word" line.long 0x208 "IME3_PROGRAMBUFFER_m_193,Program Memory 32-bit word" line.long 0x20C "IME3_PROGRAMBUFFER_m_194,Program Memory 32-bit word" line.long 0x210 "IME3_PROGRAMBUFFER_m_195,Program Memory 32-bit word" line.long 0x214 "IME3_PROGRAMBUFFER_m_196,Program Memory 32-bit word" line.long 0x218 "IME3_PROGRAMBUFFER_m_197,Program Memory 32-bit word" line.long 0x21C "IME3_PROGRAMBUFFER_m_198,Program Memory 32-bit word" line.long 0x220 "IME3_PROGRAMBUFFER_m_199,Program Memory 32-bit word" line.long 0x224 "IME3_PROGRAMBUFFER_m_200,Program Memory 32-bit word" line.long 0x228 "IME3_PROGRAMBUFFER_m_201,Program Memory 32-bit word" line.long 0x22C "IME3_PROGRAMBUFFER_m_202,Program Memory 32-bit word" line.long 0x230 "IME3_PROGRAMBUFFER_m_203,Program Memory 32-bit word" line.long 0x234 "IME3_PROGRAMBUFFER_m_204,Program Memory 32-bit word" line.long 0x238 "IME3_PROGRAMBUFFER_m_205,Program Memory 32-bit word" line.long 0x23C "IME3_PROGRAMBUFFER_m_206,Program Memory 32-bit word" line.long 0x240 "IME3_PROGRAMBUFFER_m_207,Program Memory 32-bit word" line.long 0x244 "IME3_PROGRAMBUFFER_m_208,Program Memory 32-bit word" line.long 0x248 "IME3_PROGRAMBUFFER_m_209,Program Memory 32-bit word" line.long 0x24C "IME3_PROGRAMBUFFER_m_210,Program Memory 32-bit word" line.long 0x250 "IME3_PROGRAMBUFFER_m_211,Program Memory 32-bit word" line.long 0x254 "IME3_PROGRAMBUFFER_m_212,Program Memory 32-bit word" line.long 0x258 "IME3_PROGRAMBUFFER_m_213,Program Memory 32-bit word" line.long 0x25C "IME3_PROGRAMBUFFER_m_214,Program Memory 32-bit word" line.long 0x260 "IME3_PROGRAMBUFFER_m_215,Program Memory 32-bit word" line.long 0x264 "IME3_PROGRAMBUFFER_m_216,Program Memory 32-bit word" line.long 0x268 "IME3_PROGRAMBUFFER_m_217,Program Memory 32-bit word" line.long 0x26C "IME3_PROGRAMBUFFER_m_218,Program Memory 32-bit word" line.long 0x270 "IME3_PROGRAMBUFFER_m_219,Program Memory 32-bit word" line.long 0x274 "IME3_PROGRAMBUFFER_m_220,Program Memory 32-bit word" line.long 0x278 "IME3_PROGRAMBUFFER_m_221,Program Memory 32-bit word" line.long 0x27C "IME3_PROGRAMBUFFER_m_222,Program Memory 32-bit word" line.long 0x280 "IME3_PROGRAMBUFFER_m_223,Program Memory 32-bit word" line.long 0x284 "IME3_PROGRAMBUFFER_m_224,Program Memory 32-bit word" line.long 0x288 "IME3_PROGRAMBUFFER_m_225,Program Memory 32-bit word" line.long 0x28C "IME3_PROGRAMBUFFER_m_226,Program Memory 32-bit word" line.long 0x290 "IME3_PROGRAMBUFFER_m_227,Program Memory 32-bit word" line.long 0x294 "IME3_PROGRAMBUFFER_m_228,Program Memory 32-bit word" line.long 0x298 "IME3_PROGRAMBUFFER_m_229,Program Memory 32-bit word" line.long 0x29C "IME3_PROGRAMBUFFER_m_230,Program Memory 32-bit word" line.long 0x2A0 "IME3_PROGRAMBUFFER_m_231,Program Memory 32-bit word" line.long 0x2A4 "IME3_PROGRAMBUFFER_m_232,Program Memory 32-bit word" line.long 0x2A8 "IME3_PROGRAMBUFFER_m_233,Program Memory 32-bit word" line.long 0x2AC "IME3_PROGRAMBUFFER_m_234,Program Memory 32-bit word" line.long 0x2B0 "IME3_PROGRAMBUFFER_m_235,Program Memory 32-bit word" line.long 0x2B4 "IME3_PROGRAMBUFFER_m_236,Program Memory 32-bit word" line.long 0x2B8 "IME3_PROGRAMBUFFER_m_237,Program Memory 32-bit word" line.long 0x2BC "IME3_PROGRAMBUFFER_m_238,Program Memory 32-bit word" line.long 0x2C0 "IME3_PROGRAMBUFFER_m_239,Program Memory 32-bit word" line.long 0x2C4 "IME3_PROGRAMBUFFER_m_240,Program Memory 32-bit word" line.long 0x2C8 "IME3_PROGRAMBUFFER_m_241,Program Memory 32-bit word" line.long 0x2CC "IME3_PROGRAMBUFFER_m_242,Program Memory 32-bit word" line.long 0x2D0 "IME3_PROGRAMBUFFER_m_243,Program Memory 32-bit word" line.long 0x2D4 "IME3_PROGRAMBUFFER_m_244,Program Memory 32-bit word" line.long 0x2D8 "IME3_PROGRAMBUFFER_m_245,Program Memory 32-bit word" line.long 0x2DC "IME3_PROGRAMBUFFER_m_246,Program Memory 32-bit word" line.long 0x2E0 "IME3_PROGRAMBUFFER_m_247,Program Memory 32-bit word" line.long 0x2E4 "IME3_PROGRAMBUFFER_m_248,Program Memory 32-bit word" line.long 0x2E8 "IME3_PROGRAMBUFFER_m_249,Program Memory 32-bit word" line.long 0x2EC "IME3_PROGRAMBUFFER_m_250,Program Memory 32-bit word" line.long 0x2F0 "IME3_PROGRAMBUFFER_m_251,Program Memory 32-bit word" line.long 0x2F4 "IME3_PROGRAMBUFFER_m_252,Program Memory 32-bit word" line.long 0x2F8 "IME3_PROGRAMBUFFER_m_253,Program Memory 32-bit word" line.long 0x2FC "IME3_PROGRAMBUFFER_m_254,Program Memory 32-bit word" line.long 0x300 "IME3_PROGRAMBUFFER_m_255,Program Memory 32-bit word" line.long 0x304 "IME3_PROGRAMBUFFER_m_256,Program Memory 32-bit word" line.long 0x308 "IME3_PROGRAMBUFFER_m_257,Program Memory 32-bit word" line.long 0x30C "IME3_PROGRAMBUFFER_m_258,Program Memory 32-bit word" line.long 0x310 "IME3_PROGRAMBUFFER_m_259,Program Memory 32-bit word" line.long 0x314 "IME3_PROGRAMBUFFER_m_260,Program Memory 32-bit word" line.long 0x318 "IME3_PROGRAMBUFFER_m_261,Program Memory 32-bit word" line.long 0x31C "IME3_PROGRAMBUFFER_m_262,Program Memory 32-bit word" line.long 0x320 "IME3_PROGRAMBUFFER_m_263,Program Memory 32-bit word" line.long 0x324 "IME3_PROGRAMBUFFER_m_264,Program Memory 32-bit word" line.long 0x328 "IME3_PROGRAMBUFFER_m_265,Program Memory 32-bit word" line.long 0x32C "IME3_PROGRAMBUFFER_m_266,Program Memory 32-bit word" line.long 0x330 "IME3_PROGRAMBUFFER_m_267,Program Memory 32-bit word" line.long 0x334 "IME3_PROGRAMBUFFER_m_268,Program Memory 32-bit word" line.long 0x338 "IME3_PROGRAMBUFFER_m_269,Program Memory 32-bit word" line.long 0x33C "IME3_PROGRAMBUFFER_m_270,Program Memory 32-bit word" line.long 0x340 "IME3_PROGRAMBUFFER_m_271,Program Memory 32-bit word" line.long 0x344 "IME3_PROGRAMBUFFER_m_272,Program Memory 32-bit word" line.long 0x348 "IME3_PROGRAMBUFFER_m_273,Program Memory 32-bit word" line.long 0x34C "IME3_PROGRAMBUFFER_m_274,Program Memory 32-bit word" line.long 0x350 "IME3_PROGRAMBUFFER_m_275,Program Memory 32-bit word" line.long 0x354 "IME3_PROGRAMBUFFER_m_276,Program Memory 32-bit word" line.long 0x358 "IME3_PROGRAMBUFFER_m_277,Program Memory 32-bit word" line.long 0x35C "IME3_PROGRAMBUFFER_m_278,Program Memory 32-bit word" line.long 0x360 "IME3_PROGRAMBUFFER_m_279,Program Memory 32-bit word" line.long 0x364 "IME3_PROGRAMBUFFER_m_280,Program Memory 32-bit word" line.long 0x368 "IME3_PROGRAMBUFFER_m_281,Program Memory 32-bit word" line.long 0x36C "IME3_PROGRAMBUFFER_m_282,Program Memory 32-bit word" line.long 0x370 "IME3_PROGRAMBUFFER_m_283,Program Memory 32-bit word" line.long 0x374 "IME3_PROGRAMBUFFER_m_284,Program Memory 32-bit word" line.long 0x378 "IME3_PROGRAMBUFFER_m_285,Program Memory 32-bit word" line.long 0x37C "IME3_PROGRAMBUFFER_m_286,Program Memory 32-bit word" line.long 0x380 "IME3_PROGRAMBUFFER_m_287,Program Memory 32-bit word" line.long 0x384 "IME3_PROGRAMBUFFER_m_288,Program Memory 32-bit word" line.long 0x388 "IME3_PROGRAMBUFFER_m_289,Program Memory 32-bit word" line.long 0x38C "IME3_PROGRAMBUFFER_m_290,Program Memory 32-bit word" line.long 0x390 "IME3_PROGRAMBUFFER_m_291,Program Memory 32-bit word" line.long 0x394 "IME3_PROGRAMBUFFER_m_292,Program Memory 32-bit word" line.long 0x398 "IME3_PROGRAMBUFFER_m_293,Program Memory 32-bit word" line.long 0x39C "IME3_PROGRAMBUFFER_m_294,Program Memory 32-bit word" line.long 0x3A0 "IME3_PROGRAMBUFFER_m_295,Program Memory 32-bit word" line.long 0x3A4 "IME3_PROGRAMBUFFER_m_296,Program Memory 32-bit word" line.long 0x3A8 "IME3_PROGRAMBUFFER_m_297,Program Memory 32-bit word" line.long 0x3AC "IME3_PROGRAMBUFFER_m_298,Program Memory 32-bit word" line.long 0x3B0 "IME3_PROGRAMBUFFER_m_299,Program Memory 32-bit word" line.long 0x3B4 "IME3_PROGRAMBUFFER_m_300,Program Memory 32-bit word" line.long 0x3B8 "IME3_PROGRAMBUFFER_m_301,Program Memory 32-bit word" line.long 0x3BC "IME3_PROGRAMBUFFER_m_302,Program Memory 32-bit word" line.long 0x3C0 "IME3_PROGRAMBUFFER_m_303,Program Memory 32-bit word" line.long 0x3C4 "IME3_PROGRAMBUFFER_m_304,Program Memory 32-bit word" line.long 0x3C8 "IME3_PROGRAMBUFFER_m_305,Program Memory 32-bit word" line.long 0x3CC "IME3_PROGRAMBUFFER_m_306,Program Memory 32-bit word" line.long 0x3D0 "IME3_PROGRAMBUFFER_m_307,Program Memory 32-bit word" line.long 0x3D4 "IME3_PROGRAMBUFFER_m_308,Program Memory 32-bit word" line.long 0x3D8 "IME3_PROGRAMBUFFER_m_309,Program Memory 32-bit word" line.long 0x3DC "IME3_PROGRAMBUFFER_m_310,Program Memory 32-bit word" line.long 0x3E0 "IME3_PROGRAMBUFFER_m_311,Program Memory 32-bit word" line.long 0x3E4 "IME3_PROGRAMBUFFER_m_312,Program Memory 32-bit word" line.long 0x3E8 "IME3_PROGRAMBUFFER_m_313,Program Memory 32-bit word" line.long 0x3EC "IME3_PROGRAMBUFFER_m_314,Program Memory 32-bit word" line.long 0x3F0 "IME3_PROGRAMBUFFER_m_315,Program Memory 32-bit word" line.long 0x3F4 "IME3_PROGRAMBUFFER_m_316,Program Memory 32-bit word" line.long 0x3F8 "IME3_PROGRAMBUFFER_m_317,Program Memory 32-bit word" line.long 0x3FC "IME3_PROGRAMBUFFER_m_318,Program Memory 32-bit word" line.long 0x400 "IME3_PROGRAMBUFFER_m_319,Program Memory 32-bit word" line.long 0x404 "IME3_PROGRAMBUFFER_m_320,Program Memory 32-bit word" line.long 0x408 "IME3_PROGRAMBUFFER_m_321,Program Memory 32-bit word" line.long 0x40C "IME3_PROGRAMBUFFER_m_322,Program Memory 32-bit word" line.long 0x410 "IME3_PROGRAMBUFFER_m_323,Program Memory 32-bit word" line.long 0x414 "IME3_PROGRAMBUFFER_m_324,Program Memory 32-bit word" line.long 0x418 "IME3_PROGRAMBUFFER_m_325,Program Memory 32-bit word" line.long 0x41C "IME3_PROGRAMBUFFER_m_326,Program Memory 32-bit word" line.long 0x420 "IME3_PROGRAMBUFFER_m_327,Program Memory 32-bit word" line.long 0x424 "IME3_PROGRAMBUFFER_m_328,Program Memory 32-bit word" line.long 0x428 "IME3_PROGRAMBUFFER_m_329,Program Memory 32-bit word" line.long 0x42C "IME3_PROGRAMBUFFER_m_330,Program Memory 32-bit word" line.long 0x430 "IME3_PROGRAMBUFFER_m_331,Program Memory 32-bit word" line.long 0x434 "IME3_PROGRAMBUFFER_m_332,Program Memory 32-bit word" line.long 0x438 "IME3_PROGRAMBUFFER_m_333,Program Memory 32-bit word" line.long 0x43C "IME3_PROGRAMBUFFER_m_334,Program Memory 32-bit word" line.long 0x440 "IME3_PROGRAMBUFFER_m_335,Program Memory 32-bit word" line.long 0x444 "IME3_PROGRAMBUFFER_m_336,Program Memory 32-bit word" line.long 0x448 "IME3_PROGRAMBUFFER_m_337,Program Memory 32-bit word" line.long 0x44C "IME3_PROGRAMBUFFER_m_338,Program Memory 32-bit word" line.long 0x450 "IME3_PROGRAMBUFFER_m_339,Program Memory 32-bit word" line.long 0x454 "IME3_PROGRAMBUFFER_m_340,Program Memory 32-bit word" line.long 0x458 "IME3_PROGRAMBUFFER_m_341,Program Memory 32-bit word" line.long 0x45C "IME3_PROGRAMBUFFER_m_342,Program Memory 32-bit word" line.long 0x460 "IME3_PROGRAMBUFFER_m_343,Program Memory 32-bit word" line.long 0x464 "IME3_PROGRAMBUFFER_m_344,Program Memory 32-bit word" line.long 0x468 "IME3_PROGRAMBUFFER_m_345,Program Memory 32-bit word" line.long 0x46C "IME3_PROGRAMBUFFER_m_346,Program Memory 32-bit word" line.long 0x470 "IME3_PROGRAMBUFFER_m_347,Program Memory 32-bit word" line.long 0x474 "IME3_PROGRAMBUFFER_m_348,Program Memory 32-bit word" line.long 0x478 "IME3_PROGRAMBUFFER_m_349,Program Memory 32-bit word" line.long 0x47C "IME3_PROGRAMBUFFER_m_350,Program Memory 32-bit word" line.long 0x480 "IME3_PROGRAMBUFFER_m_351,Program Memory 32-bit word" line.long 0x484 "IME3_PROGRAMBUFFER_m_352,Program Memory 32-bit word" line.long 0x488 "IME3_PROGRAMBUFFER_m_353,Program Memory 32-bit word" line.long 0x48C "IME3_PROGRAMBUFFER_m_354,Program Memory 32-bit word" line.long 0x490 "IME3_PROGRAMBUFFER_m_355,Program Memory 32-bit word" line.long 0x494 "IME3_PROGRAMBUFFER_m_356,Program Memory 32-bit word" line.long 0x498 "IME3_PROGRAMBUFFER_m_357,Program Memory 32-bit word" line.long 0x49C "IME3_PROGRAMBUFFER_m_358,Program Memory 32-bit word" line.long 0x4A0 "IME3_PROGRAMBUFFER_m_359,Program Memory 32-bit word" line.long 0x4A4 "IME3_PROGRAMBUFFER_m_360,Program Memory 32-bit word" line.long 0x4A8 "IME3_PROGRAMBUFFER_m_361,Program Memory 32-bit word" line.long 0x4AC "IME3_PROGRAMBUFFER_m_362,Program Memory 32-bit word" line.long 0x4B0 "IME3_PROGRAMBUFFER_m_363,Program Memory 32-bit word" line.long 0x4B4 "IME3_PROGRAMBUFFER_m_364,Program Memory 32-bit word" line.long 0x4B8 "IME3_PROGRAMBUFFER_m_365,Program Memory 32-bit word" line.long 0x4BC "IME3_PROGRAMBUFFER_m_366,Program Memory 32-bit word" line.long 0x4C0 "IME3_PROGRAMBUFFER_m_367,Program Memory 32-bit word" line.long 0x4C4 "IME3_PROGRAMBUFFER_m_368,Program Memory 32-bit word" line.long 0x4C8 "IME3_PROGRAMBUFFER_m_369,Program Memory 32-bit word" line.long 0x4CC "IME3_PROGRAMBUFFER_m_370,Program Memory 32-bit word" line.long 0x4D0 "IME3_PROGRAMBUFFER_m_371,Program Memory 32-bit word" line.long 0x4D4 "IME3_PROGRAMBUFFER_m_372,Program Memory 32-bit word" line.long 0x4D8 "IME3_PROGRAMBUFFER_m_373,Program Memory 32-bit word" line.long 0x4DC "IME3_PROGRAMBUFFER_m_374,Program Memory 32-bit word" line.long 0x4E0 "IME3_PROGRAMBUFFER_m_375,Program Memory 32-bit word" line.long 0x4E4 "IME3_PROGRAMBUFFER_m_376,Program Memory 32-bit word" line.long 0x4E8 "IME3_PROGRAMBUFFER_m_377,Program Memory 32-bit word" line.long 0x4EC "IME3_PROGRAMBUFFER_m_378,Program Memory 32-bit word" line.long 0x4F0 "IME3_PROGRAMBUFFER_m_379,Program Memory 32-bit word" line.long 0x4F4 "IME3_PROGRAMBUFFER_m_380,Program Memory 32-bit word" line.long 0x4F8 "IME3_PROGRAMBUFFER_m_381,Program Memory 32-bit word" line.long 0x4FC "IME3_PROGRAMBUFFER_m_382,Program Memory 32-bit word" line.long 0x500 "IME3_PROGRAMBUFFER_m_383,Program Memory 32-bit word" line.long 0x504 "IME3_PROGRAMBUFFER_m_384,Program Memory 32-bit word" line.long 0x508 "IME3_PROGRAMBUFFER_m_385,Program Memory 32-bit word" line.long 0x50C "IME3_PROGRAMBUFFER_m_386,Program Memory 32-bit word" line.long 0x510 "IME3_PROGRAMBUFFER_m_387,Program Memory 32-bit word" line.long 0x514 "IME3_PROGRAMBUFFER_m_388,Program Memory 32-bit word" line.long 0x518 "IME3_PROGRAMBUFFER_m_389,Program Memory 32-bit word" line.long 0x51C "IME3_PROGRAMBUFFER_m_390,Program Memory 32-bit word" line.long 0x520 "IME3_PROGRAMBUFFER_m_391,Program Memory 32-bit word" line.long 0x524 "IME3_PROGRAMBUFFER_m_392,Program Memory 32-bit word" line.long 0x528 "IME3_PROGRAMBUFFER_m_393,Program Memory 32-bit word" line.long 0x52C "IME3_PROGRAMBUFFER_m_394,Program Memory 32-bit word" line.long 0x530 "IME3_PROGRAMBUFFER_m_395,Program Memory 32-bit word" line.long 0x534 "IME3_PROGRAMBUFFER_m_396,Program Memory 32-bit word" line.long 0x538 "IME3_PROGRAMBUFFER_m_397,Program Memory 32-bit word" line.long 0x53C "IME3_PROGRAMBUFFER_m_398,Program Memory 32-bit word" line.long 0x540 "IME3_PROGRAMBUFFER_m_399,Program Memory 32-bit word" line.long 0x544 "IME3_PROGRAMBUFFER_m_400,Program Memory 32-bit word" line.long 0x548 "IME3_PROGRAMBUFFER_m_401,Program Memory 32-bit word" line.long 0x54C "IME3_PROGRAMBUFFER_m_402,Program Memory 32-bit word" line.long 0x550 "IME3_PROGRAMBUFFER_m_403,Program Memory 32-bit word" line.long 0x554 "IME3_PROGRAMBUFFER_m_404,Program Memory 32-bit word" line.long 0x558 "IME3_PROGRAMBUFFER_m_405,Program Memory 32-bit word" line.long 0x55C "IME3_PROGRAMBUFFER_m_406,Program Memory 32-bit word" line.long 0x560 "IME3_PROGRAMBUFFER_m_407,Program Memory 32-bit word" line.long 0x564 "IME3_PROGRAMBUFFER_m_408,Program Memory 32-bit word" line.long 0x568 "IME3_PROGRAMBUFFER_m_409,Program Memory 32-bit word" line.long 0x56C "IME3_PROGRAMBUFFER_m_410,Program Memory 32-bit word" line.long 0x570 "IME3_PROGRAMBUFFER_m_411,Program Memory 32-bit word" line.long 0x574 "IME3_PROGRAMBUFFER_m_412,Program Memory 32-bit word" line.long 0x578 "IME3_PROGRAMBUFFER_m_413,Program Memory 32-bit word" line.long 0x57C "IME3_PROGRAMBUFFER_m_414,Program Memory 32-bit word" line.long 0x580 "IME3_PROGRAMBUFFER_m_415,Program Memory 32-bit word" line.long 0x584 "IME3_PROGRAMBUFFER_m_416,Program Memory 32-bit word" line.long 0x588 "IME3_PROGRAMBUFFER_m_417,Program Memory 32-bit word" line.long 0x58C "IME3_PROGRAMBUFFER_m_418,Program Memory 32-bit word" line.long 0x590 "IME3_PROGRAMBUFFER_m_419,Program Memory 32-bit word" line.long 0x594 "IME3_PROGRAMBUFFER_m_420,Program Memory 32-bit word" line.long 0x598 "IME3_PROGRAMBUFFER_m_421,Program Memory 32-bit word" line.long 0x59C "IME3_PROGRAMBUFFER_m_422,Program Memory 32-bit word" line.long 0x5A0 "IME3_PROGRAMBUFFER_m_423,Program Memory 32-bit word" line.long 0x5A4 "IME3_PROGRAMBUFFER_m_424,Program Memory 32-bit word" line.long 0x5A8 "IME3_PROGRAMBUFFER_m_425,Program Memory 32-bit word" line.long 0x5AC "IME3_PROGRAMBUFFER_m_426,Program Memory 32-bit word" line.long 0x5B0 "IME3_PROGRAMBUFFER_m_427,Program Memory 32-bit word" line.long 0x5B4 "IME3_PROGRAMBUFFER_m_428,Program Memory 32-bit word" line.long 0x5B8 "IME3_PROGRAMBUFFER_m_429,Program Memory 32-bit word" line.long 0x5BC "IME3_PROGRAMBUFFER_m_430,Program Memory 32-bit word" line.long 0x5C0 "IME3_PROGRAMBUFFER_m_431,Program Memory 32-bit word" line.long 0x5C4 "IME3_PROGRAMBUFFER_m_432,Program Memory 32-bit word" line.long 0x5C8 "IME3_PROGRAMBUFFER_m_433,Program Memory 32-bit word" line.long 0x5CC "IME3_PROGRAMBUFFER_m_434,Program Memory 32-bit word" line.long 0x5D0 "IME3_PROGRAMBUFFER_m_435,Program Memory 32-bit word" line.long 0x5D4 "IME3_PROGRAMBUFFER_m_436,Program Memory 32-bit word" line.long 0x5D8 "IME3_PROGRAMBUFFER_m_437,Program Memory 32-bit word" line.long 0x5DC "IME3_PROGRAMBUFFER_m_438,Program Memory 32-bit word" line.long 0x5E0 "IME3_PROGRAMBUFFER_m_439,Program Memory 32-bit word" line.long 0x5E4 "IME3_PROGRAMBUFFER_m_440,Program Memory 32-bit word" line.long 0x5E8 "IME3_PROGRAMBUFFER_m_441,Program Memory 32-bit word" line.long 0x5EC "IME3_PROGRAMBUFFER_m_442,Program Memory 32-bit word" line.long 0x5F0 "IME3_PROGRAMBUFFER_m_443,Program Memory 32-bit word" line.long 0x5F4 "IME3_PROGRAMBUFFER_m_444,Program Memory 32-bit word" line.long 0x5F8 "IME3_PROGRAMBUFFER_m_445,Program Memory 32-bit word" line.long 0x5FC "IME3_PROGRAMBUFFER_m_446,Program Memory 32-bit word" line.long 0x600 "IME3_PROGRAMBUFFER_m_447,Program Memory 32-bit word" line.long 0x604 "IME3_PROGRAMBUFFER_m_448,Program Memory 32-bit word" line.long 0x608 "IME3_PROGRAMBUFFER_m_449,Program Memory 32-bit word" line.long 0x60C "IME3_PROGRAMBUFFER_m_450,Program Memory 32-bit word" line.long 0x610 "IME3_PROGRAMBUFFER_m_451,Program Memory 32-bit word" line.long 0x614 "IME3_PROGRAMBUFFER_m_452,Program Memory 32-bit word" line.long 0x618 "IME3_PROGRAMBUFFER_m_453,Program Memory 32-bit word" line.long 0x61C "IME3_PROGRAMBUFFER_m_454,Program Memory 32-bit word" line.long 0x620 "IME3_PROGRAMBUFFER_m_455,Program Memory 32-bit word" line.long 0x624 "IME3_PROGRAMBUFFER_m_456,Program Memory 32-bit word" line.long 0x628 "IME3_PROGRAMBUFFER_m_457,Program Memory 32-bit word" line.long 0x62C "IME3_PROGRAMBUFFER_m_458,Program Memory 32-bit word" line.long 0x630 "IME3_PROGRAMBUFFER_m_459,Program Memory 32-bit word" line.long 0x634 "IME3_PROGRAMBUFFER_m_460,Program Memory 32-bit word" line.long 0x638 "IME3_PROGRAMBUFFER_m_461,Program Memory 32-bit word" line.long 0x63C "IME3_PROGRAMBUFFER_m_462,Program Memory 32-bit word" line.long 0x640 "IME3_PROGRAMBUFFER_m_463,Program Memory 32-bit word" line.long 0x644 "IME3_PROGRAMBUFFER_m_464,Program Memory 32-bit word" line.long 0x648 "IME3_PROGRAMBUFFER_m_465,Program Memory 32-bit word" line.long 0x64C "IME3_PROGRAMBUFFER_m_466,Program Memory 32-bit word" line.long 0x650 "IME3_PROGRAMBUFFER_m_467,Program Memory 32-bit word" line.long 0x654 "IME3_PROGRAMBUFFER_m_468,Program Memory 32-bit word" line.long 0x658 "IME3_PROGRAMBUFFER_m_469,Program Memory 32-bit word" line.long 0x65C "IME3_PROGRAMBUFFER_m_470,Program Memory 32-bit word" line.long 0x660 "IME3_PROGRAMBUFFER_m_471,Program Memory 32-bit word" line.long 0x664 "IME3_PROGRAMBUFFER_m_472,Program Memory 32-bit word" line.long 0x668 "IME3_PROGRAMBUFFER_m_473,Program Memory 32-bit word" line.long 0x66C "IME3_PROGRAMBUFFER_m_474,Program Memory 32-bit word" line.long 0x670 "IME3_PROGRAMBUFFER_m_475,Program Memory 32-bit word" line.long 0x674 "IME3_PROGRAMBUFFER_m_476,Program Memory 32-bit word" line.long 0x678 "IME3_PROGRAMBUFFER_m_477,Program Memory 32-bit word" line.long 0x67C "IME3_PROGRAMBUFFER_m_478,Program Memory 32-bit word" line.long 0x680 "IME3_PROGRAMBUFFER_m_479,Program Memory 32-bit word" line.long 0x684 "IME3_PROGRAMBUFFER_m_480,Program Memory 32-bit word" line.long 0x688 "IME3_PROGRAMBUFFER_m_481,Program Memory 32-bit word" line.long 0x68C "IME3_PROGRAMBUFFER_m_482,Program Memory 32-bit word" line.long 0x690 "IME3_PROGRAMBUFFER_m_483,Program Memory 32-bit word" line.long 0x694 "IME3_PROGRAMBUFFER_m_484,Program Memory 32-bit word" line.long 0x698 "IME3_PROGRAMBUFFER_m_485,Program Memory 32-bit word" line.long 0x69C "IME3_PROGRAMBUFFER_m_486,Program Memory 32-bit word" line.long 0x6A0 "IME3_PROGRAMBUFFER_m_487,Program Memory 32-bit word" line.long 0x6A4 "IME3_PROGRAMBUFFER_m_488,Program Memory 32-bit word" line.long 0x6A8 "IME3_PROGRAMBUFFER_m_489,Program Memory 32-bit word" line.long 0x6AC "IME3_PROGRAMBUFFER_m_490,Program Memory 32-bit word" line.long 0x6B0 "IME3_PROGRAMBUFFER_m_491,Program Memory 32-bit word" line.long 0x6B4 "IME3_PROGRAMBUFFER_m_492,Program Memory 32-bit word" line.long 0x6B8 "IME3_PROGRAMBUFFER_m_493,Program Memory 32-bit word" line.long 0x6BC "IME3_PROGRAMBUFFER_m_494,Program Memory 32-bit word" line.long 0x6C0 "IME3_PROGRAMBUFFER_m_495,Program Memory 32-bit word" line.long 0x6C4 "IME3_PROGRAMBUFFER_m_496,Program Memory 32-bit word" line.long 0x6C8 "IME3_PROGRAMBUFFER_m_497,Program Memory 32-bit word" line.long 0x6CC "IME3_PROGRAMBUFFER_m_498,Program Memory 32-bit word" line.long 0x6D0 "IME3_PROGRAMBUFFER_m_499,Program Memory 32-bit word" line.long 0x6D4 "IME3_PROGRAMBUFFER_m_500,Program Memory 32-bit word" line.long 0x6D8 "IME3_PROGRAMBUFFER_m_501,Program Memory 32-bit word" line.long 0x6DC "IME3_PROGRAMBUFFER_m_502,Program Memory 32-bit word" line.long 0x6E0 "IME3_PROGRAMBUFFER_m_503,Program Memory 32-bit word" line.long 0x6E4 "IME3_PROGRAMBUFFER_m_504,Program Memory 32-bit word" line.long 0x6E8 "IME3_PROGRAMBUFFER_m_505,Program Memory 32-bit word" line.long 0x6EC "IME3_PROGRAMBUFFER_m_506,Program Memory 32-bit word" line.long 0x6F0 "IME3_PROGRAMBUFFER_m_507,Program Memory 32-bit word" line.long 0x6F4 "IME3_PROGRAMBUFFER_m_508,Program Memory 32-bit word" line.long 0x6F8 "IME3_PROGRAMBUFFER_m_509,Program Memory 32-bit word" line.long 0x6FC "IME3_PROGRAMBUFFER_m_510,Program Memory 32-bit word" line.long 0x700 "IME3_PROGRAMBUFFER_m_511,Program Memory 32-bit word" line.long 0x704 "IME3_PROGRAMBUFFER_m_512,Program Memory 32-bit word" line.long 0x708 "IME3_PROGRAMBUFFER_m_513,Program Memory 32-bit word" line.long 0x70C "IME3_PROGRAMBUFFER_m_514,Program Memory 32-bit word" line.long 0x710 "IME3_PROGRAMBUFFER_m_515,Program Memory 32-bit word" line.long 0x714 "IME3_PROGRAMBUFFER_m_516,Program Memory 32-bit word" line.long 0x718 "IME3_PROGRAMBUFFER_m_517,Program Memory 32-bit word" line.long 0x71C "IME3_PROGRAMBUFFER_m_518,Program Memory 32-bit word" line.long 0x720 "IME3_PROGRAMBUFFER_m_519,Program Memory 32-bit word" line.long 0x724 "IME3_PROGRAMBUFFER_m_520,Program Memory 32-bit word" line.long 0x728 "IME3_PROGRAMBUFFER_m_521,Program Memory 32-bit word" line.long 0x72C "IME3_PROGRAMBUFFER_m_522,Program Memory 32-bit word" line.long 0x730 "IME3_PROGRAMBUFFER_m_523,Program Memory 32-bit word" line.long 0x734 "IME3_PROGRAMBUFFER_m_524,Program Memory 32-bit word" line.long 0x738 "IME3_PROGRAMBUFFER_m_525,Program Memory 32-bit word" line.long 0x73C "IME3_PROGRAMBUFFER_m_526,Program Memory 32-bit word" line.long 0x740 "IME3_PROGRAMBUFFER_m_527,Program Memory 32-bit word" line.long 0x744 "IME3_PROGRAMBUFFER_m_528,Program Memory 32-bit word" line.long 0x748 "IME3_PROGRAMBUFFER_m_529,Program Memory 32-bit word" line.long 0x74C "IME3_PROGRAMBUFFER_m_530,Program Memory 32-bit word" line.long 0x750 "IME3_PROGRAMBUFFER_m_531,Program Memory 32-bit word" line.long 0x754 "IME3_PROGRAMBUFFER_m_532,Program Memory 32-bit word" line.long 0x758 "IME3_PROGRAMBUFFER_m_533,Program Memory 32-bit word" line.long 0x75C "IME3_PROGRAMBUFFER_m_534,Program Memory 32-bit word" line.long 0x760 "IME3_PROGRAMBUFFER_m_535,Program Memory 32-bit word" line.long 0x764 "IME3_PROGRAMBUFFER_m_536,Program Memory 32-bit word" line.long 0x768 "IME3_PROGRAMBUFFER_m_537,Program Memory 32-bit word" line.long 0x76C "IME3_PROGRAMBUFFER_m_538,Program Memory 32-bit word" line.long 0x770 "IME3_PROGRAMBUFFER_m_539,Program Memory 32-bit word" line.long 0x774 "IME3_PROGRAMBUFFER_m_540,Program Memory 32-bit word" line.long 0x778 "IME3_PROGRAMBUFFER_m_541,Program Memory 32-bit word" line.long 0x77C "IME3_PROGRAMBUFFER_m_542,Program Memory 32-bit word" line.long 0x780 "IME3_PROGRAMBUFFER_m_543,Program Memory 32-bit word" line.long 0x784 "IME3_PROGRAMBUFFER_m_544,Program Memory 32-bit word" line.long 0x788 "IME3_PROGRAMBUFFER_m_545,Program Memory 32-bit word" line.long 0x78C "IME3_PROGRAMBUFFER_m_546,Program Memory 32-bit word" line.long 0x790 "IME3_PROGRAMBUFFER_m_547,Program Memory 32-bit word" line.long 0x794 "IME3_PROGRAMBUFFER_m_548,Program Memory 32-bit word" line.long 0x798 "IME3_PROGRAMBUFFER_m_549,Program Memory 32-bit word" line.long 0x79C "IME3_PROGRAMBUFFER_m_550,Program Memory 32-bit word" line.long 0x7A0 "IME3_PROGRAMBUFFER_m_551,Program Memory 32-bit word" line.long 0x7A4 "IME3_PROGRAMBUFFER_m_552,Program Memory 32-bit word" line.long 0x7A8 "IME3_PROGRAMBUFFER_m_553,Program Memory 32-bit word" line.long 0x7AC "IME3_PROGRAMBUFFER_m_554,Program Memory 32-bit word" line.long 0x7B0 "IME3_PROGRAMBUFFER_m_555,Program Memory 32-bit word" line.long 0x7B4 "IME3_PROGRAMBUFFER_m_556,Program Memory 32-bit word" line.long 0x7B8 "IME3_PROGRAMBUFFER_m_557,Program Memory 32-bit word" line.long 0x7BC "IME3_PROGRAMBUFFER_m_558,Program Memory 32-bit word" line.long 0x7C0 "IME3_PROGRAMBUFFER_m_559,Program Memory 32-bit word" line.long 0x7C4 "IME3_PROGRAMBUFFER_m_560,Program Memory 32-bit word" line.long 0x7C8 "IME3_PROGRAMBUFFER_m_561,Program Memory 32-bit word" line.long 0x7CC "IME3_PROGRAMBUFFER_m_562,Program Memory 32-bit word" line.long 0x7D0 "IME3_PROGRAMBUFFER_m_563,Program Memory 32-bit word" line.long 0x7D4 "IME3_PROGRAMBUFFER_m_564,Program Memory 32-bit word" line.long 0x7D8 "IME3_PROGRAMBUFFER_m_565,Program Memory 32-bit word" line.long 0x7DC "IME3_PROGRAMBUFFER_m_566,Program Memory 32-bit word" line.long 0x7E0 "IME3_PROGRAMBUFFER_m_567,Program Memory 32-bit word" line.long 0x7E4 "IME3_PROGRAMBUFFER_m_568,Program Memory 32-bit word" line.long 0x7E8 "IME3_PROGRAMBUFFER_m_569,Program Memory 32-bit word" line.long 0x7EC "IME3_PROGRAMBUFFER_m_570,Program Memory 32-bit word" line.long 0x7F0 "IME3_PROGRAMBUFFER_m_571,Program Memory 32-bit word" line.long 0x7F4 "IME3_PROGRAMBUFFER_m_572,Program Memory 32-bit word" line.long 0x7F8 "IME3_PROGRAMBUFFER_m_573,Program Memory 32-bit word" line.long 0x7FC "IME3_PROGRAMBUFFER_m_574,Program Memory 32-bit word" line.long 0x800 "IME3_PROGRAMBUFFER_m_575,Program Memory 32-bit word" line.long 0x804 "IME3_PROGRAMBUFFER_m_576,Program Memory 32-bit word" line.long 0x808 "IME3_PROGRAMBUFFER_m_577,Program Memory 32-bit word" line.long 0x80C "IME3_PROGRAMBUFFER_m_578,Program Memory 32-bit word" line.long 0x810 "IME3_PROGRAMBUFFER_m_579,Program Memory 32-bit word" line.long 0x814 "IME3_PROGRAMBUFFER_m_580,Program Memory 32-bit word" line.long 0x818 "IME3_PROGRAMBUFFER_m_581,Program Memory 32-bit word" line.long 0x81C "IME3_PROGRAMBUFFER_m_582,Program Memory 32-bit word" line.long 0x820 "IME3_PROGRAMBUFFER_m_583,Program Memory 32-bit word" line.long 0x824 "IME3_PROGRAMBUFFER_m_584,Program Memory 32-bit word" line.long 0x828 "IME3_PROGRAMBUFFER_m_585,Program Memory 32-bit word" line.long 0x82C "IME3_PROGRAMBUFFER_m_586,Program Memory 32-bit word" line.long 0x830 "IME3_PROGRAMBUFFER_m_587,Program Memory 32-bit word" line.long 0x834 "IME3_PROGRAMBUFFER_m_588,Program Memory 32-bit word" line.long 0x838 "IME3_PROGRAMBUFFER_m_589,Program Memory 32-bit word" line.long 0x83C "IME3_PROGRAMBUFFER_m_590,Program Memory 32-bit word" line.long 0x840 "IME3_PROGRAMBUFFER_m_591,Program Memory 32-bit word" line.long 0x844 "IME3_PROGRAMBUFFER_m_592,Program Memory 32-bit word" line.long 0x848 "IME3_PROGRAMBUFFER_m_593,Program Memory 32-bit word" line.long 0x84C "IME3_PROGRAMBUFFER_m_594,Program Memory 32-bit word" line.long 0x850 "IME3_PROGRAMBUFFER_m_595,Program Memory 32-bit word" line.long 0x854 "IME3_PROGRAMBUFFER_m_596,Program Memory 32-bit word" line.long 0x858 "IME3_PROGRAMBUFFER_m_597,Program Memory 32-bit word" line.long 0x85C "IME3_PROGRAMBUFFER_m_598,Program Memory 32-bit word" line.long 0x860 "IME3_PROGRAMBUFFER_m_599,Program Memory 32-bit word" line.long 0x864 "IME3_PROGRAMBUFFER_m_600,Program Memory 32-bit word" line.long 0x868 "IME3_PROGRAMBUFFER_m_601,Program Memory 32-bit word" line.long 0x86C "IME3_PROGRAMBUFFER_m_602,Program Memory 32-bit word" line.long 0x870 "IME3_PROGRAMBUFFER_m_603,Program Memory 32-bit word" line.long 0x874 "IME3_PROGRAMBUFFER_m_604,Program Memory 32-bit word" line.long 0x878 "IME3_PROGRAMBUFFER_m_605,Program Memory 32-bit word" line.long 0x87C "IME3_PROGRAMBUFFER_m_606,Program Memory 32-bit word" line.long 0x880 "IME3_PROGRAMBUFFER_m_607,Program Memory 32-bit word" line.long 0x884 "IME3_PROGRAMBUFFER_m_608,Program Memory 32-bit word" line.long 0x888 "IME3_PROGRAMBUFFER_m_609,Program Memory 32-bit word" line.long 0x88C "IME3_PROGRAMBUFFER_m_610,Program Memory 32-bit word" line.long 0x890 "IME3_PROGRAMBUFFER_m_611,Program Memory 32-bit word" line.long 0x894 "IME3_PROGRAMBUFFER_m_612,Program Memory 32-bit word" line.long 0x898 "IME3_PROGRAMBUFFER_m_613,Program Memory 32-bit word" line.long 0x89C "IME3_PROGRAMBUFFER_m_614,Program Memory 32-bit word" line.long 0x8A0 "IME3_PROGRAMBUFFER_m_615,Program Memory 32-bit word" line.long 0x8A4 "IME3_PROGRAMBUFFER_m_616,Program Memory 32-bit word" line.long 0x8A8 "IME3_PROGRAMBUFFER_m_617,Program Memory 32-bit word" line.long 0x8AC "IME3_PROGRAMBUFFER_m_618,Program Memory 32-bit word" line.long 0x8B0 "IME3_PROGRAMBUFFER_m_619,Program Memory 32-bit word" line.long 0x8B4 "IME3_PROGRAMBUFFER_m_620,Program Memory 32-bit word" line.long 0x8B8 "IME3_PROGRAMBUFFER_m_621,Program Memory 32-bit word" line.long 0x8BC "IME3_PROGRAMBUFFER_m_622,Program Memory 32-bit word" line.long 0x8C0 "IME3_PROGRAMBUFFER_m_623,Program Memory 32-bit word" line.long 0x8C4 "IME3_PROGRAMBUFFER_m_624,Program Memory 32-bit word" line.long 0x8C8 "IME3_PROGRAMBUFFER_m_625,Program Memory 32-bit word" line.long 0x8CC "IME3_PROGRAMBUFFER_m_626,Program Memory 32-bit word" line.long 0x8D0 "IME3_PROGRAMBUFFER_m_627,Program Memory 32-bit word" line.long 0x8D4 "IME3_PROGRAMBUFFER_m_628,Program Memory 32-bit word" line.long 0x8D8 "IME3_PROGRAMBUFFER_m_629,Program Memory 32-bit word" line.long 0x8DC "IME3_PROGRAMBUFFER_m_630,Program Memory 32-bit word" line.long 0x8E0 "IME3_PROGRAMBUFFER_m_631,Program Memory 32-bit word" line.long 0x8E4 "IME3_PROGRAMBUFFER_m_632,Program Memory 32-bit word" line.long 0x8E8 "IME3_PROGRAMBUFFER_m_633,Program Memory 32-bit word" line.long 0x8EC "IME3_PROGRAMBUFFER_m_634,Program Memory 32-bit word" line.long 0x8F0 "IME3_PROGRAMBUFFER_m_635,Program Memory 32-bit word" line.long 0x8F4 "IME3_PROGRAMBUFFER_m_636,Program Memory 32-bit word" line.long 0x8F8 "IME3_PROGRAMBUFFER_m_637,Program Memory 32-bit word" line.long 0x8FC "IME3_PROGRAMBUFFER_m_638,Program Memory 32-bit word" line.long 0x900 "IME3_PROGRAMBUFFER_m_639,Program Memory 32-bit word" line.long 0x904 "IME3_PROGRAMBUFFER_m_640,Program Memory 32-bit word" line.long 0x908 "IME3_PROGRAMBUFFER_m_641,Program Memory 32-bit word" line.long 0x90C "IME3_PROGRAMBUFFER_m_642,Program Memory 32-bit word" line.long 0x910 "IME3_PROGRAMBUFFER_m_643,Program Memory 32-bit word" line.long 0x914 "IME3_PROGRAMBUFFER_m_644,Program Memory 32-bit word" line.long 0x918 "IME3_PROGRAMBUFFER_m_645,Program Memory 32-bit word" line.long 0x91C "IME3_PROGRAMBUFFER_m_646,Program Memory 32-bit word" line.long 0x920 "IME3_PROGRAMBUFFER_m_647,Program Memory 32-bit word" line.long 0x924 "IME3_PROGRAMBUFFER_m_648,Program Memory 32-bit word" line.long 0x928 "IME3_PROGRAMBUFFER_m_649,Program Memory 32-bit word" line.long 0x92C "IME3_PROGRAMBUFFER_m_650,Program Memory 32-bit word" line.long 0x930 "IME3_PROGRAMBUFFER_m_651,Program Memory 32-bit word" line.long 0x934 "IME3_PROGRAMBUFFER_m_652,Program Memory 32-bit word" line.long 0x938 "IME3_PROGRAMBUFFER_m_653,Program Memory 32-bit word" line.long 0x93C "IME3_PROGRAMBUFFER_m_654,Program Memory 32-bit word" line.long 0x940 "IME3_PROGRAMBUFFER_m_655,Program Memory 32-bit word" line.long 0x944 "IME3_PROGRAMBUFFER_m_656,Program Memory 32-bit word" line.long 0x948 "IME3_PROGRAMBUFFER_m_657,Program Memory 32-bit word" line.long 0x94C "IME3_PROGRAMBUFFER_m_658,Program Memory 32-bit word" line.long 0x950 "IME3_PROGRAMBUFFER_m_659,Program Memory 32-bit word" line.long 0x954 "IME3_PROGRAMBUFFER_m_660,Program Memory 32-bit word" line.long 0x958 "IME3_PROGRAMBUFFER_m_661,Program Memory 32-bit word" line.long 0x95C "IME3_PROGRAMBUFFER_m_662,Program Memory 32-bit word" line.long 0x960 "IME3_PROGRAMBUFFER_m_663,Program Memory 32-bit word" line.long 0x964 "IME3_PROGRAMBUFFER_m_664,Program Memory 32-bit word" line.long 0x968 "IME3_PROGRAMBUFFER_m_665,Program Memory 32-bit word" line.long 0x96C "IME3_PROGRAMBUFFER_m_666,Program Memory 32-bit word" line.long 0x970 "IME3_PROGRAMBUFFER_m_667,Program Memory 32-bit word" line.long 0x974 "IME3_PROGRAMBUFFER_m_668,Program Memory 32-bit word" line.long 0x978 "IME3_PROGRAMBUFFER_m_669,Program Memory 32-bit word" line.long 0x97C "IME3_PROGRAMBUFFER_m_670,Program Memory 32-bit word" line.long 0x980 "IME3_PROGRAMBUFFER_m_671,Program Memory 32-bit word" line.long 0x984 "IME3_PROGRAMBUFFER_m_672,Program Memory 32-bit word" line.long 0x988 "IME3_PROGRAMBUFFER_m_673,Program Memory 32-bit word" line.long 0x98C "IME3_PROGRAMBUFFER_m_674,Program Memory 32-bit word" line.long 0x990 "IME3_PROGRAMBUFFER_m_675,Program Memory 32-bit word" line.long 0x994 "IME3_PROGRAMBUFFER_m_676,Program Memory 32-bit word" line.long 0x998 "IME3_PROGRAMBUFFER_m_677,Program Memory 32-bit word" line.long 0x99C "IME3_PROGRAMBUFFER_m_678,Program Memory 32-bit word" line.long 0x9A0 "IME3_PROGRAMBUFFER_m_679,Program Memory 32-bit word" line.long 0x9A4 "IME3_PROGRAMBUFFER_m_680,Program Memory 32-bit word" line.long 0x9A8 "IME3_PROGRAMBUFFER_m_681,Program Memory 32-bit word" line.long 0x9AC "IME3_PROGRAMBUFFER_m_682,Program Memory 32-bit word" line.long 0x9B0 "IME3_PROGRAMBUFFER_m_683,Program Memory 32-bit word" line.long 0x9B4 "IME3_PROGRAMBUFFER_m_684,Program Memory 32-bit word" line.long 0x9B8 "IME3_PROGRAMBUFFER_m_685,Program Memory 32-bit word" line.long 0x9BC "IME3_PROGRAMBUFFER_m_686,Program Memory 32-bit word" line.long 0x9C0 "IME3_PROGRAMBUFFER_m_687,Program Memory 32-bit word" line.long 0x9C4 "IME3_PROGRAMBUFFER_m_688,Program Memory 32-bit word" line.long 0x9C8 "IME3_PROGRAMBUFFER_m_689,Program Memory 32-bit word" line.long 0x9CC "IME3_PROGRAMBUFFER_m_690,Program Memory 32-bit word" line.long 0x9D0 "IME3_PROGRAMBUFFER_m_691,Program Memory 32-bit word" line.long 0x9D4 "IME3_PROGRAMBUFFER_m_692,Program Memory 32-bit word" line.long 0x9D8 "IME3_PROGRAMBUFFER_m_693,Program Memory 32-bit word" line.long 0x9DC "IME3_PROGRAMBUFFER_m_694,Program Memory 32-bit word" line.long 0x9E0 "IME3_PROGRAMBUFFER_m_695,Program Memory 32-bit word" line.long 0x9E4 "IME3_PROGRAMBUFFER_m_696,Program Memory 32-bit word" line.long 0x9E8 "IME3_PROGRAMBUFFER_m_697,Program Memory 32-bit word" line.long 0x9EC "IME3_PROGRAMBUFFER_m_698,Program Memory 32-bit word" line.long 0x9F0 "IME3_PROGRAMBUFFER_m_699,Program Memory 32-bit word" line.long 0x9F4 "IME3_PROGRAMBUFFER_m_700,Program Memory 32-bit word" line.long 0x9F8 "IME3_PROGRAMBUFFER_m_701,Program Memory 32-bit word" line.long 0x9FC "IME3_PROGRAMBUFFER_m_702,Program Memory 32-bit word" line.long 0xA00 "IME3_PROGRAMBUFFER_m_703,Program Memory 32-bit word" line.long 0xA04 "IME3_PROGRAMBUFFER_m_704,Program Memory 32-bit word" line.long 0xA08 "IME3_PROGRAMBUFFER_m_705,Program Memory 32-bit word" line.long 0xA0C "IME3_PROGRAMBUFFER_m_706,Program Memory 32-bit word" line.long 0xA10 "IME3_PROGRAMBUFFER_m_707,Program Memory 32-bit word" line.long 0xA14 "IME3_PROGRAMBUFFER_m_708,Program Memory 32-bit word" line.long 0xA18 "IME3_PROGRAMBUFFER_m_709,Program Memory 32-bit word" line.long 0xA1C "IME3_PROGRAMBUFFER_m_710,Program Memory 32-bit word" line.long 0xA20 "IME3_PROGRAMBUFFER_m_711,Program Memory 32-bit word" line.long 0xA24 "IME3_PROGRAMBUFFER_m_712,Program Memory 32-bit word" line.long 0xA28 "IME3_PROGRAMBUFFER_m_713,Program Memory 32-bit word" line.long 0xA2C "IME3_PROGRAMBUFFER_m_714,Program Memory 32-bit word" line.long 0xA30 "IME3_PROGRAMBUFFER_m_715,Program Memory 32-bit word" line.long 0xA34 "IME3_PROGRAMBUFFER_m_716,Program Memory 32-bit word" line.long 0xA38 "IME3_PROGRAMBUFFER_m_717,Program Memory 32-bit word" line.long 0xA3C "IME3_PROGRAMBUFFER_m_718,Program Memory 32-bit word" line.long 0xA40 "IME3_PROGRAMBUFFER_m_719,Program Memory 32-bit word" line.long 0xA44 "IME3_PROGRAMBUFFER_m_720,Program Memory 32-bit word" line.long 0xA48 "IME3_PROGRAMBUFFER_m_721,Program Memory 32-bit word" line.long 0xA4C "IME3_PROGRAMBUFFER_m_722,Program Memory 32-bit word" line.long 0xA50 "IME3_PROGRAMBUFFER_m_723,Program Memory 32-bit word" line.long 0xA54 "IME3_PROGRAMBUFFER_m_724,Program Memory 32-bit word" line.long 0xA58 "IME3_PROGRAMBUFFER_m_725,Program Memory 32-bit word" line.long 0xA5C "IME3_PROGRAMBUFFER_m_726,Program Memory 32-bit word" line.long 0xA60 "IME3_PROGRAMBUFFER_m_727,Program Memory 32-bit word" line.long 0xA64 "IME3_PROGRAMBUFFER_m_728,Program Memory 32-bit word" line.long 0xA68 "IME3_PROGRAMBUFFER_m_729,Program Memory 32-bit word" line.long 0xA6C "IME3_PROGRAMBUFFER_m_730,Program Memory 32-bit word" line.long 0xA70 "IME3_PROGRAMBUFFER_m_731,Program Memory 32-bit word" line.long 0xA74 "IME3_PROGRAMBUFFER_m_732,Program Memory 32-bit word" line.long 0xA78 "IME3_PROGRAMBUFFER_m_733,Program Memory 32-bit word" line.long 0xA7C "IME3_PROGRAMBUFFER_m_734,Program Memory 32-bit word" line.long 0xA80 "IME3_PROGRAMBUFFER_m_735,Program Memory 32-bit word" line.long 0xA84 "IME3_PROGRAMBUFFER_m_736,Program Memory 32-bit word" line.long 0xA88 "IME3_PROGRAMBUFFER_m_737,Program Memory 32-bit word" line.long 0xA8C "IME3_PROGRAMBUFFER_m_738,Program Memory 32-bit word" line.long 0xA90 "IME3_PROGRAMBUFFER_m_739,Program Memory 32-bit word" line.long 0xA94 "IME3_PROGRAMBUFFER_m_740,Program Memory 32-bit word" line.long 0xA98 "IME3_PROGRAMBUFFER_m_741,Program Memory 32-bit word" line.long 0xA9C "IME3_PROGRAMBUFFER_m_742,Program Memory 32-bit word" line.long 0xAA0 "IME3_PROGRAMBUFFER_m_743,Program Memory 32-bit word" line.long 0xAA4 "IME3_PROGRAMBUFFER_m_744,Program Memory 32-bit word" line.long 0xAA8 "IME3_PROGRAMBUFFER_m_745,Program Memory 32-bit word" line.long 0xAAC "IME3_PROGRAMBUFFER_m_746,Program Memory 32-bit word" line.long 0xAB0 "IME3_PROGRAMBUFFER_m_747,Program Memory 32-bit word" line.long 0xAB4 "IME3_PROGRAMBUFFER_m_748,Program Memory 32-bit word" line.long 0xAB8 "IME3_PROGRAMBUFFER_m_749,Program Memory 32-bit word" line.long 0xABC "IME3_PROGRAMBUFFER_m_750,Program Memory 32-bit word" line.long 0xAC0 "IME3_PROGRAMBUFFER_m_751,Program Memory 32-bit word" line.long 0xAC4 "IME3_PROGRAMBUFFER_m_752,Program Memory 32-bit word" line.long 0xAC8 "IME3_PROGRAMBUFFER_m_753,Program Memory 32-bit word" line.long 0xACC "IME3_PROGRAMBUFFER_m_754,Program Memory 32-bit word" line.long 0xAD0 "IME3_PROGRAMBUFFER_m_755,Program Memory 32-bit word" line.long 0xAD4 "IME3_PROGRAMBUFFER_m_756,Program Memory 32-bit word" line.long 0xAD8 "IME3_PROGRAMBUFFER_m_757,Program Memory 32-bit word" line.long 0xADC "IME3_PROGRAMBUFFER_m_758,Program Memory 32-bit word" line.long 0xAE0 "IME3_PROGRAMBUFFER_m_759,Program Memory 32-bit word" line.long 0xAE4 "IME3_PROGRAMBUFFER_m_760,Program Memory 32-bit word" line.long 0xAE8 "IME3_PROGRAMBUFFER_m_761,Program Memory 32-bit word" line.long 0xAEC "IME3_PROGRAMBUFFER_m_762,Program Memory 32-bit word" line.long 0xAF0 "IME3_PROGRAMBUFFER_m_763,Program Memory 32-bit word" line.long 0xAF4 "IME3_PROGRAMBUFFER_m_764,Program Memory 32-bit word" line.long 0xAF8 "IME3_PROGRAMBUFFER_m_765,Program Memory 32-bit word" line.long 0xAFC "IME3_PROGRAMBUFFER_m_766,Program Memory 32-bit word" line.long 0xB00 "IME3_PROGRAMBUFFER_m_767,Program Memory 32-bit word" line.long 0xB04 "IME3_PROGRAMBUFFER_m_768,Program Memory 32-bit word" line.long 0xB08 "IME3_PROGRAMBUFFER_m_769,Program Memory 32-bit word" line.long 0xB0C "IME3_PROGRAMBUFFER_m_770,Program Memory 32-bit word" line.long 0xB10 "IME3_PROGRAMBUFFER_m_771,Program Memory 32-bit word" line.long 0xB14 "IME3_PROGRAMBUFFER_m_772,Program Memory 32-bit word" line.long 0xB18 "IME3_PROGRAMBUFFER_m_773,Program Memory 32-bit word" line.long 0xB1C "IME3_PROGRAMBUFFER_m_774,Program Memory 32-bit word" line.long 0xB20 "IME3_PROGRAMBUFFER_m_775,Program Memory 32-bit word" line.long 0xB24 "IME3_PROGRAMBUFFER_m_776,Program Memory 32-bit word" line.long 0xB28 "IME3_PROGRAMBUFFER_m_777,Program Memory 32-bit word" line.long 0xB2C "IME3_PROGRAMBUFFER_m_778,Program Memory 32-bit word" line.long 0xB30 "IME3_PROGRAMBUFFER_m_779,Program Memory 32-bit word" line.long 0xB34 "IME3_PROGRAMBUFFER_m_780,Program Memory 32-bit word" line.long 0xB38 "IME3_PROGRAMBUFFER_m_781,Program Memory 32-bit word" line.long 0xB3C "IME3_PROGRAMBUFFER_m_782,Program Memory 32-bit word" line.long 0xB40 "IME3_PROGRAMBUFFER_m_783,Program Memory 32-bit word" line.long 0xB44 "IME3_PROGRAMBUFFER_m_784,Program Memory 32-bit word" line.long 0xB48 "IME3_PROGRAMBUFFER_m_785,Program Memory 32-bit word" line.long 0xB4C "IME3_PROGRAMBUFFER_m_786,Program Memory 32-bit word" line.long 0xB50 "IME3_PROGRAMBUFFER_m_787,Program Memory 32-bit word" line.long 0xB54 "IME3_PROGRAMBUFFER_m_788,Program Memory 32-bit word" line.long 0xB58 "IME3_PROGRAMBUFFER_m_789,Program Memory 32-bit word" line.long 0xB5C "IME3_PROGRAMBUFFER_m_790,Program Memory 32-bit word" line.long 0xB60 "IME3_PROGRAMBUFFER_m_791,Program Memory 32-bit word" line.long 0xB64 "IME3_PROGRAMBUFFER_m_792,Program Memory 32-bit word" line.long 0xB68 "IME3_PROGRAMBUFFER_m_793,Program Memory 32-bit word" line.long 0xB6C "IME3_PROGRAMBUFFER_m_794,Program Memory 32-bit word" line.long 0xB70 "IME3_PROGRAMBUFFER_m_795,Program Memory 32-bit word" line.long 0xB74 "IME3_PROGRAMBUFFER_m_796,Program Memory 32-bit word" line.long 0xB78 "IME3_PROGRAMBUFFER_m_797,Program Memory 32-bit word" line.long 0xB7C "IME3_PROGRAMBUFFER_m_798,Program Memory 32-bit word" line.long 0xB80 "IME3_PROGRAMBUFFER_m_799,Program Memory 32-bit word" line.long 0xB84 "IME3_PROGRAMBUFFER_m_800,Program Memory 32-bit word" line.long 0xB88 "IME3_PROGRAMBUFFER_m_801,Program Memory 32-bit word" line.long 0xB8C "IME3_PROGRAMBUFFER_m_802,Program Memory 32-bit word" line.long 0xB90 "IME3_PROGRAMBUFFER_m_803,Program Memory 32-bit word" line.long 0xB94 "IME3_PROGRAMBUFFER_m_804,Program Memory 32-bit word" line.long 0xB98 "IME3_PROGRAMBUFFER_m_805,Program Memory 32-bit word" line.long 0xB9C "IME3_PROGRAMBUFFER_m_806,Program Memory 32-bit word" line.long 0xBA0 "IME3_PROGRAMBUFFER_m_807,Program Memory 32-bit word" line.long 0xBA4 "IME3_PROGRAMBUFFER_m_808,Program Memory 32-bit word" line.long 0xBA8 "IME3_PROGRAMBUFFER_m_809,Program Memory 32-bit word" line.long 0xBAC "IME3_PROGRAMBUFFER_m_810,Program Memory 32-bit word" line.long 0xBB0 "IME3_PROGRAMBUFFER_m_811,Program Memory 32-bit word" line.long 0xBB4 "IME3_PROGRAMBUFFER_m_812,Program Memory 32-bit word" line.long 0xBB8 "IME3_PROGRAMBUFFER_m_813,Program Memory 32-bit word" line.long 0xBBC "IME3_PROGRAMBUFFER_m_814,Program Memory 32-bit word" line.long 0xBC0 "IME3_PROGRAMBUFFER_m_815,Program Memory 32-bit word" line.long 0xBC4 "IME3_PROGRAMBUFFER_m_816,Program Memory 32-bit word" line.long 0xBC8 "IME3_PROGRAMBUFFER_m_817,Program Memory 32-bit word" line.long 0xBCC "IME3_PROGRAMBUFFER_m_818,Program Memory 32-bit word" line.long 0xBD0 "IME3_PROGRAMBUFFER_m_819,Program Memory 32-bit word" line.long 0xBD4 "IME3_PROGRAMBUFFER_m_820,Program Memory 32-bit word" line.long 0xBD8 "IME3_PROGRAMBUFFER_m_821,Program Memory 32-bit word" line.long 0xBDC "IME3_PROGRAMBUFFER_m_822,Program Memory 32-bit word" line.long 0xBE0 "IME3_PROGRAMBUFFER_m_823,Program Memory 32-bit word" line.long 0xBE4 "IME3_PROGRAMBUFFER_m_824,Program Memory 32-bit word" line.long 0xBE8 "IME3_PROGRAMBUFFER_m_825,Program Memory 32-bit word" line.long 0xBEC "IME3_PROGRAMBUFFER_m_826,Program Memory 32-bit word" line.long 0xBF0 "IME3_PROGRAMBUFFER_m_827,Program Memory 32-bit word" line.long 0xBF4 "IME3_PROGRAMBUFFER_m_828,Program Memory 32-bit word" line.long 0xBF8 "IME3_PROGRAMBUFFER_m_829,Program Memory 32-bit word" line.long 0xBFC "IME3_PROGRAMBUFFER_m_830,Program Memory 32-bit word" line.long 0xC00 "IME3_PROGRAMBUFFER_m_831,Program Memory 32-bit word" line.long 0xC04 "IME3_PROGRAMBUFFER_m_832,Program Memory 32-bit word" line.long 0xC08 "IME3_PROGRAMBUFFER_m_833,Program Memory 32-bit word" line.long 0xC0C "IME3_PROGRAMBUFFER_m_834,Program Memory 32-bit word" line.long 0xC10 "IME3_PROGRAMBUFFER_m_835,Program Memory 32-bit word" line.long 0xC14 "IME3_PROGRAMBUFFER_m_836,Program Memory 32-bit word" line.long 0xC18 "IME3_PROGRAMBUFFER_m_837,Program Memory 32-bit word" line.long 0xC1C "IME3_PROGRAMBUFFER_m_838,Program Memory 32-bit word" line.long 0xC20 "IME3_PROGRAMBUFFER_m_839,Program Memory 32-bit word" line.long 0xC24 "IME3_PROGRAMBUFFER_m_840,Program Memory 32-bit word" line.long 0xC28 "IME3_PROGRAMBUFFER_m_841,Program Memory 32-bit word" line.long 0xC2C "IME3_PROGRAMBUFFER_m_842,Program Memory 32-bit word" line.long 0xC30 "IME3_PROGRAMBUFFER_m_843,Program Memory 32-bit word" line.long 0xC34 "IME3_PROGRAMBUFFER_m_844,Program Memory 32-bit word" line.long 0xC38 "IME3_PROGRAMBUFFER_m_845,Program Memory 32-bit word" line.long 0xC3C "IME3_PROGRAMBUFFER_m_846,Program Memory 32-bit word" line.long 0xC40 "IME3_PROGRAMBUFFER_m_847,Program Memory 32-bit word" line.long 0xC44 "IME3_PROGRAMBUFFER_m_848,Program Memory 32-bit word" line.long 0xC48 "IME3_PROGRAMBUFFER_m_849,Program Memory 32-bit word" line.long 0xC4C "IME3_PROGRAMBUFFER_m_850,Program Memory 32-bit word" line.long 0xC50 "IME3_PROGRAMBUFFER_m_851,Program Memory 32-bit word" line.long 0xC54 "IME3_PROGRAMBUFFER_m_852,Program Memory 32-bit word" line.long 0xC58 "IME3_PROGRAMBUFFER_m_853,Program Memory 32-bit word" line.long 0xC5C "IME3_PROGRAMBUFFER_m_854,Program Memory 32-bit word" line.long 0xC60 "IME3_PROGRAMBUFFER_m_855,Program Memory 32-bit word" line.long 0xC64 "IME3_PROGRAMBUFFER_m_856,Program Memory 32-bit word" line.long 0xC68 "IME3_PROGRAMBUFFER_m_857,Program Memory 32-bit word" line.long 0xC6C "IME3_PROGRAMBUFFER_m_858,Program Memory 32-bit word" line.long 0xC70 "IME3_PROGRAMBUFFER_m_859,Program Memory 32-bit word" line.long 0xC74 "IME3_PROGRAMBUFFER_m_860,Program Memory 32-bit word" line.long 0xC78 "IME3_PROGRAMBUFFER_m_861,Program Memory 32-bit word" line.long 0xC7C "IME3_PROGRAMBUFFER_m_862,Program Memory 32-bit word" line.long 0xC80 "IME3_PROGRAMBUFFER_m_863,Program Memory 32-bit word" line.long 0xC84 "IME3_PROGRAMBUFFER_m_864,Program Memory 32-bit word" line.long 0xC88 "IME3_PROGRAMBUFFER_m_865,Program Memory 32-bit word" line.long 0xC8C "IME3_PROGRAMBUFFER_m_866,Program Memory 32-bit word" line.long 0xC90 "IME3_PROGRAMBUFFER_m_867,Program Memory 32-bit word" line.long 0xC94 "IME3_PROGRAMBUFFER_m_868,Program Memory 32-bit word" line.long 0xC98 "IME3_PROGRAMBUFFER_m_869,Program Memory 32-bit word" line.long 0xC9C "IME3_PROGRAMBUFFER_m_870,Program Memory 32-bit word" line.long 0xCA0 "IME3_PROGRAMBUFFER_m_871,Program Memory 32-bit word" line.long 0xCA4 "IME3_PROGRAMBUFFER_m_872,Program Memory 32-bit word" line.long 0xCA8 "IME3_PROGRAMBUFFER_m_873,Program Memory 32-bit word" line.long 0xCAC "IME3_PROGRAMBUFFER_m_874,Program Memory 32-bit word" line.long 0xCB0 "IME3_PROGRAMBUFFER_m_875,Program Memory 32-bit word" line.long 0xCB4 "IME3_PROGRAMBUFFER_m_876,Program Memory 32-bit word" line.long 0xCB8 "IME3_PROGRAMBUFFER_m_877,Program Memory 32-bit word" line.long 0xCBC "IME3_PROGRAMBUFFER_m_878,Program Memory 32-bit word" line.long 0xCC0 "IME3_PROGRAMBUFFER_m_879,Program Memory 32-bit word" line.long 0xCC4 "IME3_PROGRAMBUFFER_m_880,Program Memory 32-bit word" line.long 0xCC8 "IME3_PROGRAMBUFFER_m_881,Program Memory 32-bit word" line.long 0xCCC "IME3_PROGRAMBUFFER_m_882,Program Memory 32-bit word" line.long 0xCD0 "IME3_PROGRAMBUFFER_m_883,Program Memory 32-bit word" line.long 0xCD4 "IME3_PROGRAMBUFFER_m_884,Program Memory 32-bit word" line.long 0xCD8 "IME3_PROGRAMBUFFER_m_885,Program Memory 32-bit word" line.long 0xCDC "IME3_PROGRAMBUFFER_m_886,Program Memory 32-bit word" line.long 0xCE0 "IME3_PROGRAMBUFFER_m_887,Program Memory 32-bit word" line.long 0xCE4 "IME3_PROGRAMBUFFER_m_888,Program Memory 32-bit word" line.long 0xCE8 "IME3_PROGRAMBUFFER_m_889,Program Memory 32-bit word" line.long 0xCEC "IME3_PROGRAMBUFFER_m_890,Program Memory 32-bit word" line.long 0xCF0 "IME3_PROGRAMBUFFER_m_891,Program Memory 32-bit word" line.long 0xCF4 "IME3_PROGRAMBUFFER_m_892,Program Memory 32-bit word" line.long 0xCF8 "IME3_PROGRAMBUFFER_m_893,Program Memory 32-bit word" line.long 0xCFC "IME3_PROGRAMBUFFER_m_894,Program Memory 32-bit word" line.long 0xD00 "IME3_PROGRAMBUFFER_m_895,Program Memory 32-bit word" line.long 0xD04 "IME3_PROGRAMBUFFER_m_896,Program Memory 32-bit word" line.long 0xD08 "IME3_PROGRAMBUFFER_m_897,Program Memory 32-bit word" line.long 0xD0C "IME3_PROGRAMBUFFER_m_898,Program Memory 32-bit word" line.long 0xD10 "IME3_PROGRAMBUFFER_m_899,Program Memory 32-bit word" line.long 0xD14 "IME3_PROGRAMBUFFER_m_900,Program Memory 32-bit word" line.long 0xD18 "IME3_PROGRAMBUFFER_m_901,Program Memory 32-bit word" line.long 0xD1C "IME3_PROGRAMBUFFER_m_902,Program Memory 32-bit word" line.long 0xD20 "IME3_PROGRAMBUFFER_m_903,Program Memory 32-bit word" line.long 0xD24 "IME3_PROGRAMBUFFER_m_904,Program Memory 32-bit word" line.long 0xD28 "IME3_PROGRAMBUFFER_m_905,Program Memory 32-bit word" line.long 0xD2C "IME3_PROGRAMBUFFER_m_906,Program Memory 32-bit word" line.long 0xD30 "IME3_PROGRAMBUFFER_m_907,Program Memory 32-bit word" line.long 0xD34 "IME3_PROGRAMBUFFER_m_908,Program Memory 32-bit word" line.long 0xD38 "IME3_PROGRAMBUFFER_m_909,Program Memory 32-bit word" line.long 0xD3C "IME3_PROGRAMBUFFER_m_910,Program Memory 32-bit word" line.long 0xD40 "IME3_PROGRAMBUFFER_m_911,Program Memory 32-bit word" line.long 0xD44 "IME3_PROGRAMBUFFER_m_912,Program Memory 32-bit word" line.long 0xD48 "IME3_PROGRAMBUFFER_m_913,Program Memory 32-bit word" line.long 0xD4C "IME3_PROGRAMBUFFER_m_914,Program Memory 32-bit word" line.long 0xD50 "IME3_PROGRAMBUFFER_m_915,Program Memory 32-bit word" line.long 0xD54 "IME3_PROGRAMBUFFER_m_916,Program Memory 32-bit word" line.long 0xD58 "IME3_PROGRAMBUFFER_m_917,Program Memory 32-bit word" line.long 0xD5C "IME3_PROGRAMBUFFER_m_918,Program Memory 32-bit word" line.long 0xD60 "IME3_PROGRAMBUFFER_m_919,Program Memory 32-bit word" line.long 0xD64 "IME3_PROGRAMBUFFER_m_920,Program Memory 32-bit word" line.long 0xD68 "IME3_PROGRAMBUFFER_m_921,Program Memory 32-bit word" line.long 0xD6C "IME3_PROGRAMBUFFER_m_922,Program Memory 32-bit word" line.long 0xD70 "IME3_PROGRAMBUFFER_m_923,Program Memory 32-bit word" line.long 0xD74 "IME3_PROGRAMBUFFER_m_924,Program Memory 32-bit word" line.long 0xD78 "IME3_PROGRAMBUFFER_m_925,Program Memory 32-bit word" line.long 0xD7C "IME3_PROGRAMBUFFER_m_926,Program Memory 32-bit word" line.long 0xD80 "IME3_PROGRAMBUFFER_m_927,Program Memory 32-bit word" line.long 0xD84 "IME3_PROGRAMBUFFER_m_928,Program Memory 32-bit word" line.long 0xD88 "IME3_PROGRAMBUFFER_m_929,Program Memory 32-bit word" line.long 0xD8C "IME3_PROGRAMBUFFER_m_930,Program Memory 32-bit word" line.long 0xD90 "IME3_PROGRAMBUFFER_m_931,Program Memory 32-bit word" line.long 0xD94 "IME3_PROGRAMBUFFER_m_932,Program Memory 32-bit word" line.long 0xD98 "IME3_PROGRAMBUFFER_m_933,Program Memory 32-bit word" line.long 0xD9C "IME3_PROGRAMBUFFER_m_934,Program Memory 32-bit word" line.long 0xDA0 "IME3_PROGRAMBUFFER_m_935,Program Memory 32-bit word" line.long 0xDA4 "IME3_PROGRAMBUFFER_m_936,Program Memory 32-bit word" line.long 0xDA8 "IME3_PROGRAMBUFFER_m_937,Program Memory 32-bit word" line.long 0xDAC "IME3_PROGRAMBUFFER_m_938,Program Memory 32-bit word" line.long 0xDB0 "IME3_PROGRAMBUFFER_m_939,Program Memory 32-bit word" line.long 0xDB4 "IME3_PROGRAMBUFFER_m_940,Program Memory 32-bit word" line.long 0xDB8 "IME3_PROGRAMBUFFER_m_941,Program Memory 32-bit word" line.long 0xDBC "IME3_PROGRAMBUFFER_m_942,Program Memory 32-bit word" line.long 0xDC0 "IME3_PROGRAMBUFFER_m_943,Program Memory 32-bit word" line.long 0xDC4 "IME3_PROGRAMBUFFER_m_944,Program Memory 32-bit word" line.long 0xDC8 "IME3_PROGRAMBUFFER_m_945,Program Memory 32-bit word" line.long 0xDCC "IME3_PROGRAMBUFFER_m_946,Program Memory 32-bit word" line.long 0xDD0 "IME3_PROGRAMBUFFER_m_947,Program Memory 32-bit word" line.long 0xDD4 "IME3_PROGRAMBUFFER_m_948,Program Memory 32-bit word" line.long 0xDD8 "IME3_PROGRAMBUFFER_m_949,Program Memory 32-bit word" line.long 0xDDC "IME3_PROGRAMBUFFER_m_950,Program Memory 32-bit word" line.long 0xDE0 "IME3_PROGRAMBUFFER_m_951,Program Memory 32-bit word" line.long 0xDE4 "IME3_PROGRAMBUFFER_m_952,Program Memory 32-bit word" line.long 0xDE8 "IME3_PROGRAMBUFFER_m_953,Program Memory 32-bit word" line.long 0xDEC "IME3_PROGRAMBUFFER_m_954,Program Memory 32-bit word" line.long 0xDF0 "IME3_PROGRAMBUFFER_m_955,Program Memory 32-bit word" line.long 0xDF4 "IME3_PROGRAMBUFFER_m_956,Program Memory 32-bit word" line.long 0xDF8 "IME3_PROGRAMBUFFER_m_957,Program Memory 32-bit word" line.long 0xDFC "IME3_PROGRAMBUFFER_m_958,Program Memory 32-bit word" line.long 0xE00 "IME3_PROGRAMBUFFER_m_959,Program Memory 32-bit word" line.long 0xE04 "IME3_PROGRAMBUFFER_m_960,Program Memory 32-bit word" line.long 0xE08 "IME3_PROGRAMBUFFER_m_961,Program Memory 32-bit word" line.long 0xE0C "IME3_PROGRAMBUFFER_m_962,Program Memory 32-bit word" line.long 0xE10 "IME3_PROGRAMBUFFER_m_963,Program Memory 32-bit word" line.long 0xE14 "IME3_PROGRAMBUFFER_m_964,Program Memory 32-bit word" line.long 0xE18 "IME3_PROGRAMBUFFER_m_965,Program Memory 32-bit word" line.long 0xE1C "IME3_PROGRAMBUFFER_m_966,Program Memory 32-bit word" line.long 0xE20 "IME3_PROGRAMBUFFER_m_967,Program Memory 32-bit word" line.long 0xE24 "IME3_PROGRAMBUFFER_m_968,Program Memory 32-bit word" line.long 0xE28 "IME3_PROGRAMBUFFER_m_969,Program Memory 32-bit word" line.long 0xE2C "IME3_PROGRAMBUFFER_m_970,Program Memory 32-bit word" line.long 0xE30 "IME3_PROGRAMBUFFER_m_971,Program Memory 32-bit word" line.long 0xE34 "IME3_PROGRAMBUFFER_m_972,Program Memory 32-bit word" line.long 0xE38 "IME3_PROGRAMBUFFER_m_973,Program Memory 32-bit word" line.long 0xE3C "IME3_PROGRAMBUFFER_m_974,Program Memory 32-bit word" line.long 0xE40 "IME3_PROGRAMBUFFER_m_975,Program Memory 32-bit word" line.long 0xE44 "IME3_PROGRAMBUFFER_m_976,Program Memory 32-bit word" line.long 0xE48 "IME3_PROGRAMBUFFER_m_977,Program Memory 32-bit word" line.long 0xE4C "IME3_PROGRAMBUFFER_m_978,Program Memory 32-bit word" line.long 0xE50 "IME3_PROGRAMBUFFER_m_979,Program Memory 32-bit word" line.long 0xE54 "IME3_PROGRAMBUFFER_m_980,Program Memory 32-bit word" line.long 0xE58 "IME3_PROGRAMBUFFER_m_981,Program Memory 32-bit word" line.long 0xE5C "IME3_PROGRAMBUFFER_m_982,Program Memory 32-bit word" line.long 0xE60 "IME3_PROGRAMBUFFER_m_983,Program Memory 32-bit word" line.long 0xE64 "IME3_PROGRAMBUFFER_m_984,Program Memory 32-bit word" line.long 0xE68 "IME3_PROGRAMBUFFER_m_985,Program Memory 32-bit word" line.long 0xE6C "IME3_PROGRAMBUFFER_m_986,Program Memory 32-bit word" line.long 0xE70 "IME3_PROGRAMBUFFER_m_987,Program Memory 32-bit word" line.long 0xE74 "IME3_PROGRAMBUFFER_m_988,Program Memory 32-bit word" line.long 0xE78 "IME3_PROGRAMBUFFER_m_989,Program Memory 32-bit word" line.long 0xE7C "IME3_PROGRAMBUFFER_m_990,Program Memory 32-bit word" line.long 0xE80 "IME3_PROGRAMBUFFER_m_991,Program Memory 32-bit word" line.long 0xE84 "IME3_PROGRAMBUFFER_m_992,Program Memory 32-bit word" line.long 0xE88 "IME3_PROGRAMBUFFER_m_993,Program Memory 32-bit word" line.long 0xE8C "IME3_PROGRAMBUFFER_m_994,Program Memory 32-bit word" line.long 0xE90 "IME3_PROGRAMBUFFER_m_995,Program Memory 32-bit word" line.long 0xE94 "IME3_PROGRAMBUFFER_m_996,Program Memory 32-bit word" line.long 0xE98 "IME3_PROGRAMBUFFER_m_997,Program Memory 32-bit word" line.long 0xE9C "IME3_PROGRAMBUFFER_m_998,Program Memory 32-bit word" line.long 0xEA0 "IME3_PROGRAMBUFFER_m_999,Program Memory 32-bit word" line.long 0xEA4 "IME3_PROGRAMBUFFER_m_1000,Program Memory 32-bit word" line.long 0xEA8 "IME3_PROGRAMBUFFER_m_1001,Program Memory 32-bit word" line.long 0xEAC "IME3_PROGRAMBUFFER_m_1002,Program Memory 32-bit word" line.long 0xEB0 "IME3_PROGRAMBUFFER_m_1003,Program Memory 32-bit word" line.long 0xEB4 "IME3_PROGRAMBUFFER_m_1004,Program Memory 32-bit word" line.long 0xEB8 "IME3_PROGRAMBUFFER_m_1005,Program Memory 32-bit word" line.long 0xEBC "IME3_PROGRAMBUFFER_m_1006,Program Memory 32-bit word" line.long 0xEC0 "IME3_PROGRAMBUFFER_m_1007,Program Memory 32-bit word" line.long 0xEC4 "IME3_PROGRAMBUFFER_m_1008,Program Memory 32-bit word" line.long 0xEC8 "IME3_PROGRAMBUFFER_m_1009,Program Memory 32-bit word" line.long 0xECC "IME3_PROGRAMBUFFER_m_1010,Program Memory 32-bit word" line.long 0xED0 "IME3_PROGRAMBUFFER_m_1011,Program Memory 32-bit word" line.long 0xED4 "IME3_PROGRAMBUFFER_m_1012,Program Memory 32-bit word" line.long 0xED8 "IME3_PROGRAMBUFFER_m_1013,Program Memory 32-bit word" line.long 0xEDC "IME3_PROGRAMBUFFER_m_1014,Program Memory 32-bit word" line.long 0xEE0 "IME3_PROGRAMBUFFER_m_1015,Program Memory 32-bit word" line.long 0xEE4 "IME3_PROGRAMBUFFER_m_1016,Program Memory 32-bit word" line.long 0xEE8 "IME3_PROGRAMBUFFER_m_1017,Program Memory 32-bit word" line.long 0xEEC "IME3_PROGRAMBUFFER_m_1018,Program Memory 32-bit word" line.long 0xEF0 "IME3_PROGRAMBUFFER_m_1019,Program Memory 32-bit word" line.long 0xEF4 "IME3_PROGRAMBUFFER_m_1020,Program Memory 32-bit word" line.long 0xEF8 "IME3_PROGRAMBUFFER_m_1021,Program Memory 32-bit word" line.long 0xEFC "IME3_PROGRAMBUFFER_m_1022,Program Memory 32-bit word" line.long 0xF00 "IME3_PROGRAMBUFFER_m_1023,Program Memory 32-bit word" line.long 0xF04 "IME3_PROGRAMBUFFER_m_1024,Program Memory 32-bit word" line.long 0xF08 "IME3_PROGRAMBUFFER_m_1025,Program Memory 32-bit word" line.long 0xF0C "IME3_PROGRAMBUFFER_m_1026,Program Memory 32-bit word" line.long 0xF10 "IME3_PROGRAMBUFFER_m_1027,Program Memory 32-bit word" line.long 0xF14 "IME3_PROGRAMBUFFER_m_1028,Program Memory 32-bit word" line.long 0xF18 "IME3_PROGRAMBUFFER_m_1029,Program Memory 32-bit word" line.long 0xF1C "IME3_PROGRAMBUFFER_m_1030,Program Memory 32-bit word" line.long 0xF20 "IME3_PROGRAMBUFFER_m_1031,Program Memory 32-bit word" line.long 0xF24 "IME3_PROGRAMBUFFER_m_1032,Program Memory 32-bit word" line.long 0xF28 "IME3_PROGRAMBUFFER_m_1033,Program Memory 32-bit word" line.long 0xF2C "IME3_PROGRAMBUFFER_m_1034,Program Memory 32-bit word" line.long 0xF30 "IME3_PROGRAMBUFFER_m_1035,Program Memory 32-bit word" line.long 0xF34 "IME3_PROGRAMBUFFER_m_1036,Program Memory 32-bit word" line.long 0xF38 "IME3_PROGRAMBUFFER_m_1037,Program Memory 32-bit word" line.long 0xF3C "IME3_PROGRAMBUFFER_m_1038,Program Memory 32-bit word" line.long 0xF40 "IME3_PROGRAMBUFFER_m_1039,Program Memory 32-bit word" line.long 0xF44 "IME3_PROGRAMBUFFER_m_1040,Program Memory 32-bit word" line.long 0xF48 "IME3_PROGRAMBUFFER_m_1041,Program Memory 32-bit word" line.long 0xF4C "IME3_PROGRAMBUFFER_m_1042,Program Memory 32-bit word" line.long 0xF50 "IME3_PROGRAMBUFFER_m_1043,Program Memory 32-bit word" line.long 0xF54 "IME3_PROGRAMBUFFER_m_1044,Program Memory 32-bit word" line.long 0xF58 "IME3_PROGRAMBUFFER_m_1045,Program Memory 32-bit word" line.long 0xF5C "IME3_PROGRAMBUFFER_m_1046,Program Memory 32-bit word" line.long 0xF60 "IME3_PROGRAMBUFFER_m_1047,Program Memory 32-bit word" line.long 0xF64 "IME3_PROGRAMBUFFER_m_1048,Program Memory 32-bit word" line.long 0xF68 "IME3_PROGRAMBUFFER_m_1049,Program Memory 32-bit word" line.long 0xF6C "IME3_PROGRAMBUFFER_m_1050,Program Memory 32-bit word" line.long 0xF70 "IME3_PROGRAMBUFFER_m_1051,Program Memory 32-bit word" line.long 0xF74 "IME3_PROGRAMBUFFER_m_1052,Program Memory 32-bit word" line.long 0xF78 "IME3_PROGRAMBUFFER_m_1053,Program Memory 32-bit word" line.long 0xF7C "IME3_PROGRAMBUFFER_m_1054,Program Memory 32-bit word" line.long 0xF80 "IME3_PROGRAMBUFFER_m_1055,Program Memory 32-bit word" line.long 0xF84 "IME3_PROGRAMBUFFER_m_1056,Program Memory 32-bit word" line.long 0xF88 "IME3_PROGRAMBUFFER_m_1057,Program Memory 32-bit word" line.long 0xF8C "IME3_PROGRAMBUFFER_m_1058,Program Memory 32-bit word" line.long 0xF90 "IME3_PROGRAMBUFFER_m_1059,Program Memory 32-bit word" line.long 0xF94 "IME3_PROGRAMBUFFER_m_1060,Program Memory 32-bit word" line.long 0xF98 "IME3_PROGRAMBUFFER_m_1061,Program Memory 32-bit word" line.long 0xF9C "IME3_PROGRAMBUFFER_m_1062,Program Memory 32-bit word" line.long 0xFA0 "IME3_PROGRAMBUFFER_m_1063,Program Memory 32-bit word" line.long 0xFA4 "IME3_PROGRAMBUFFER_m_1064,Program Memory 32-bit word" line.long 0xFA8 "IME3_PROGRAMBUFFER_m_1065,Program Memory 32-bit word" line.long 0xFAC "IME3_PROGRAMBUFFER_m_1066,Program Memory 32-bit word" line.long 0xFB0 "IME3_PROGRAMBUFFER_m_1067,Program Memory 32-bit word" line.long 0xFB4 "IME3_PROGRAMBUFFER_m_1068,Program Memory 32-bit word" line.long 0xFB8 "IME3_PROGRAMBUFFER_m_1069,Program Memory 32-bit word" line.long 0xFBC "IME3_PROGRAMBUFFER_m_1070,Program Memory 32-bit word" line.long 0xFC0 "IME3_PROGRAMBUFFER_m_1071,Program Memory 32-bit word" line.long 0xFC4 "IME3_PROGRAMBUFFER_m_1072,Program Memory 32-bit word" line.long 0xFC8 "IME3_PROGRAMBUFFER_m_1073,Program Memory 32-bit word" line.long 0xFCC "IME3_PROGRAMBUFFER_m_1074,Program Memory 32-bit word" line.long 0xFD0 "IME3_PROGRAMBUFFER_m_1075,Program Memory 32-bit word" line.long 0xFD4 "IME3_PROGRAMBUFFER_m_1076,Program Memory 32-bit word" line.long 0xFD8 "IME3_PROGRAMBUFFER_m_1077,Program Memory 32-bit word" line.long 0xFDC "IME3_PROGRAMBUFFER_m_1078,Program Memory 32-bit word" line.long 0xFE0 "IME3_PROGRAMBUFFER_m_1079,Program Memory 32-bit word" line.long 0xFE4 "IME3_PROGRAMBUFFER_m_1080,Program Memory 32-bit word" line.long 0xFE8 "IME3_PROGRAMBUFFER_m_1081,Program Memory 32-bit word" line.long 0xFEC "IME3_PROGRAMBUFFER_m_1082,Program Memory 32-bit word" line.long 0xFF0 "IME3_PROGRAMBUFFER_m_1083,Program Memory 32-bit word" line.long 0xFF4 "IME3_PROGRAMBUFFER_m_1084,Program Memory 32-bit word" line.long 0xFF8 "IME3_PROGRAMBUFFER_m_1085,Program Memory 32-bit word" line.long 0xFFC "IME3_PROGRAMBUFFER_m_1086,Program Memory 32-bit word" group.long 0x30FC++0xF03 line.long 0x00 "IME3_PROGRAMBUFFER_m_1087,Program Memory 32-bit word" line.long 0x04 "IME3_PROGRAMBUFFER_m_1088,Program Memory 32-bit word" line.long 0x08 "IME3_PROGRAMBUFFER_m_1089,Program Memory 32-bit word" line.long 0x0C "IME3_PROGRAMBUFFER_m_1090,Program Memory 32-bit word" line.long 0x10 "IME3_PROGRAMBUFFER_m_1091,Program Memory 32-bit word" line.long 0x14 "IME3_PROGRAMBUFFER_m_1092,Program Memory 32-bit word" line.long 0x18 "IME3_PROGRAMBUFFER_m_1093,Program Memory 32-bit word" line.long 0x1C "IME3_PROGRAMBUFFER_m_1094,Program Memory 32-bit word" line.long 0x20 "IME3_PROGRAMBUFFER_m_1095,Program Memory 32-bit word" line.long 0x24 "IME3_PROGRAMBUFFER_m_1096,Program Memory 32-bit word" line.long 0x28 "IME3_PROGRAMBUFFER_m_1097,Program Memory 32-bit word" line.long 0x2C "IME3_PROGRAMBUFFER_m_1098,Program Memory 32-bit word" line.long 0x30 "IME3_PROGRAMBUFFER_m_1099,Program Memory 32-bit word" line.long 0x34 "IME3_PROGRAMBUFFER_m_1100,Program Memory 32-bit word" line.long 0x38 "IME3_PROGRAMBUFFER_m_1101,Program Memory 32-bit word" line.long 0x3C "IME3_PROGRAMBUFFER_m_1102,Program Memory 32-bit word" line.long 0x40 "IME3_PROGRAMBUFFER_m_1103,Program Memory 32-bit word" line.long 0x44 "IME3_PROGRAMBUFFER_m_1104,Program Memory 32-bit word" line.long 0x48 "IME3_PROGRAMBUFFER_m_1105,Program Memory 32-bit word" line.long 0x4C "IME3_PROGRAMBUFFER_m_1106,Program Memory 32-bit word" line.long 0x50 "IME3_PROGRAMBUFFER_m_1107,Program Memory 32-bit word" line.long 0x54 "IME3_PROGRAMBUFFER_m_1108,Program Memory 32-bit word" line.long 0x58 "IME3_PROGRAMBUFFER_m_1109,Program Memory 32-bit word" line.long 0x5C "IME3_PROGRAMBUFFER_m_1110,Program Memory 32-bit word" line.long 0x60 "IME3_PROGRAMBUFFER_m_1111,Program Memory 32-bit word" line.long 0x64 "IME3_PROGRAMBUFFER_m_1112,Program Memory 32-bit word" line.long 0x68 "IME3_PROGRAMBUFFER_m_1113,Program Memory 32-bit word" line.long 0x6C "IME3_PROGRAMBUFFER_m_1114,Program Memory 32-bit word" line.long 0x70 "IME3_PROGRAMBUFFER_m_1115,Program Memory 32-bit word" line.long 0x74 "IME3_PROGRAMBUFFER_m_1116,Program Memory 32-bit word" line.long 0x78 "IME3_PROGRAMBUFFER_m_1117,Program Memory 32-bit word" line.long 0x7C "IME3_PROGRAMBUFFER_m_1118,Program Memory 32-bit word" line.long 0x80 "IME3_PROGRAMBUFFER_m_1119,Program Memory 32-bit word" line.long 0x84 "IME3_PROGRAMBUFFER_m_1120,Program Memory 32-bit word" line.long 0x88 "IME3_PROGRAMBUFFER_m_1121,Program Memory 32-bit word" line.long 0x8C "IME3_PROGRAMBUFFER_m_1122,Program Memory 32-bit word" line.long 0x90 "IME3_PROGRAMBUFFER_m_1123,Program Memory 32-bit word" line.long 0x94 "IME3_PROGRAMBUFFER_m_1124,Program Memory 32-bit word" line.long 0x98 "IME3_PROGRAMBUFFER_m_1125,Program Memory 32-bit word" line.long 0x9C "IME3_PROGRAMBUFFER_m_1126,Program Memory 32-bit word" line.long 0xA0 "IME3_PROGRAMBUFFER_m_1127,Program Memory 32-bit word" line.long 0xA4 "IME3_PROGRAMBUFFER_m_1128,Program Memory 32-bit word" line.long 0xA8 "IME3_PROGRAMBUFFER_m_1129,Program Memory 32-bit word" line.long 0xAC "IME3_PROGRAMBUFFER_m_1130,Program Memory 32-bit word" line.long 0xB0 "IME3_PROGRAMBUFFER_m_1131,Program Memory 32-bit word" line.long 0xB4 "IME3_PROGRAMBUFFER_m_1132,Program Memory 32-bit word" line.long 0xB8 "IME3_PROGRAMBUFFER_m_1133,Program Memory 32-bit word" line.long 0xBC "IME3_PROGRAMBUFFER_m_1134,Program Memory 32-bit word" line.long 0xC0 "IME3_PROGRAMBUFFER_m_1135,Program Memory 32-bit word" line.long 0xC4 "IME3_PROGRAMBUFFER_m_1136,Program Memory 32-bit word" line.long 0xC8 "IME3_PROGRAMBUFFER_m_1137,Program Memory 32-bit word" line.long 0xCC "IME3_PROGRAMBUFFER_m_1138,Program Memory 32-bit word" line.long 0xD0 "IME3_PROGRAMBUFFER_m_1139,Program Memory 32-bit word" line.long 0xD4 "IME3_PROGRAMBUFFER_m_1140,Program Memory 32-bit word" line.long 0xD8 "IME3_PROGRAMBUFFER_m_1141,Program Memory 32-bit word" line.long 0xDC "IME3_PROGRAMBUFFER_m_1142,Program Memory 32-bit word" line.long 0xE0 "IME3_PROGRAMBUFFER_m_1143,Program Memory 32-bit word" line.long 0xE4 "IME3_PROGRAMBUFFER_m_1144,Program Memory 32-bit word" line.long 0xE8 "IME3_PROGRAMBUFFER_m_1145,Program Memory 32-bit word" line.long 0xEC "IME3_PROGRAMBUFFER_m_1146,Program Memory 32-bit word" line.long 0xF0 "IME3_PROGRAMBUFFER_m_1147,Program Memory 32-bit word" line.long 0xF4 "IME3_PROGRAMBUFFER_m_1148,Program Memory 32-bit word" line.long 0xF8 "IME3_PROGRAMBUFFER_m_1149,Program Memory 32-bit word" line.long 0xFC "IME3_PROGRAMBUFFER_m_1150,Program Memory 32-bit word" line.long 0x100 "IME3_PROGRAMBUFFER_m_1151,Program Memory 32-bit word" line.long 0x104 "IME3_PROGRAMBUFFER_m_1152,Program Memory 32-bit word" line.long 0x108 "IME3_PROGRAMBUFFER_m_1153,Program Memory 32-bit word" line.long 0x10C "IME3_PROGRAMBUFFER_m_1154,Program Memory 32-bit word" line.long 0x110 "IME3_PROGRAMBUFFER_m_1155,Program Memory 32-bit word" line.long 0x114 "IME3_PROGRAMBUFFER_m_1156,Program Memory 32-bit word" line.long 0x118 "IME3_PROGRAMBUFFER_m_1157,Program Memory 32-bit word" line.long 0x11C "IME3_PROGRAMBUFFER_m_1158,Program Memory 32-bit word" line.long 0x120 "IME3_PROGRAMBUFFER_m_1159,Program Memory 32-bit word" line.long 0x124 "IME3_PROGRAMBUFFER_m_1160,Program Memory 32-bit word" line.long 0x128 "IME3_PROGRAMBUFFER_m_1161,Program Memory 32-bit word" line.long 0x12C "IME3_PROGRAMBUFFER_m_1162,Program Memory 32-bit word" line.long 0x130 "IME3_PROGRAMBUFFER_m_1163,Program Memory 32-bit word" line.long 0x134 "IME3_PROGRAMBUFFER_m_1164,Program Memory 32-bit word" line.long 0x138 "IME3_PROGRAMBUFFER_m_1165,Program Memory 32-bit word" line.long 0x13C "IME3_PROGRAMBUFFER_m_1166,Program Memory 32-bit word" line.long 0x140 "IME3_PROGRAMBUFFER_m_1167,Program Memory 32-bit word" line.long 0x144 "IME3_PROGRAMBUFFER_m_1168,Program Memory 32-bit word" line.long 0x148 "IME3_PROGRAMBUFFER_m_1169,Program Memory 32-bit word" line.long 0x14C "IME3_PROGRAMBUFFER_m_1170,Program Memory 32-bit word" line.long 0x150 "IME3_PROGRAMBUFFER_m_1171,Program Memory 32-bit word" line.long 0x154 "IME3_PROGRAMBUFFER_m_1172,Program Memory 32-bit word" line.long 0x158 "IME3_PROGRAMBUFFER_m_1173,Program Memory 32-bit word" line.long 0x15C "IME3_PROGRAMBUFFER_m_1174,Program Memory 32-bit word" line.long 0x160 "IME3_PROGRAMBUFFER_m_1175,Program Memory 32-bit word" line.long 0x164 "IME3_PROGRAMBUFFER_m_1176,Program Memory 32-bit word" line.long 0x168 "IME3_PROGRAMBUFFER_m_1177,Program Memory 32-bit word" line.long 0x16C "IME3_PROGRAMBUFFER_m_1178,Program Memory 32-bit word" line.long 0x170 "IME3_PROGRAMBUFFER_m_1179,Program Memory 32-bit word" line.long 0x174 "IME3_PROGRAMBUFFER_m_1180,Program Memory 32-bit word" line.long 0x178 "IME3_PROGRAMBUFFER_m_1181,Program Memory 32-bit word" line.long 0x17C "IME3_PROGRAMBUFFER_m_1182,Program Memory 32-bit word" line.long 0x180 "IME3_PROGRAMBUFFER_m_1183,Program Memory 32-bit word" line.long 0x184 "IME3_PROGRAMBUFFER_m_1184,Program Memory 32-bit word" line.long 0x188 "IME3_PROGRAMBUFFER_m_1185,Program Memory 32-bit word" line.long 0x18C "IME3_PROGRAMBUFFER_m_1186,Program Memory 32-bit word" line.long 0x190 "IME3_PROGRAMBUFFER_m_1187,Program Memory 32-bit word" line.long 0x194 "IME3_PROGRAMBUFFER_m_1188,Program Memory 32-bit word" line.long 0x198 "IME3_PROGRAMBUFFER_m_1189,Program Memory 32-bit word" line.long 0x19C "IME3_PROGRAMBUFFER_m_1190,Program Memory 32-bit word" line.long 0x1A0 "IME3_PROGRAMBUFFER_m_1191,Program Memory 32-bit word" line.long 0x1A4 "IME3_PROGRAMBUFFER_m_1192,Program Memory 32-bit word" line.long 0x1A8 "IME3_PROGRAMBUFFER_m_1193,Program Memory 32-bit word" line.long 0x1AC "IME3_PROGRAMBUFFER_m_1194,Program Memory 32-bit word" line.long 0x1B0 "IME3_PROGRAMBUFFER_m_1195,Program Memory 32-bit word" line.long 0x1B4 "IME3_PROGRAMBUFFER_m_1196,Program Memory 32-bit word" line.long 0x1B8 "IME3_PROGRAMBUFFER_m_1197,Program Memory 32-bit word" line.long 0x1BC "IME3_PROGRAMBUFFER_m_1198,Program Memory 32-bit word" line.long 0x1C0 "IME3_PROGRAMBUFFER_m_1199,Program Memory 32-bit word" line.long 0x1C4 "IME3_PROGRAMBUFFER_m_1200,Program Memory 32-bit word" line.long 0x1C8 "IME3_PROGRAMBUFFER_m_1201,Program Memory 32-bit word" line.long 0x1CC "IME3_PROGRAMBUFFER_m_1202,Program Memory 32-bit word" line.long 0x1D0 "IME3_PROGRAMBUFFER_m_1203,Program Memory 32-bit word" line.long 0x1D4 "IME3_PROGRAMBUFFER_m_1204,Program Memory 32-bit word" line.long 0x1D8 "IME3_PROGRAMBUFFER_m_1205,Program Memory 32-bit word" line.long 0x1DC "IME3_PROGRAMBUFFER_m_1206,Program Memory 32-bit word" line.long 0x1E0 "IME3_PROGRAMBUFFER_m_1207,Program Memory 32-bit word" line.long 0x1E4 "IME3_PROGRAMBUFFER_m_1208,Program Memory 32-bit word" line.long 0x1E8 "IME3_PROGRAMBUFFER_m_1209,Program Memory 32-bit word" line.long 0x1EC "IME3_PROGRAMBUFFER_m_1210,Program Memory 32-bit word" line.long 0x1F0 "IME3_PROGRAMBUFFER_m_1211,Program Memory 32-bit word" line.long 0x1F4 "IME3_PROGRAMBUFFER_m_1212,Program Memory 32-bit word" line.long 0x1F8 "IME3_PROGRAMBUFFER_m_1213,Program Memory 32-bit word" line.long 0x1FC "IME3_PROGRAMBUFFER_m_1214,Program Memory 32-bit word" line.long 0x200 "IME3_PROGRAMBUFFER_m_1215,Program Memory 32-bit word" line.long 0x204 "IME3_PROGRAMBUFFER_m_1216,Program Memory 32-bit word" line.long 0x208 "IME3_PROGRAMBUFFER_m_1217,Program Memory 32-bit word" line.long 0x20C "IME3_PROGRAMBUFFER_m_1218,Program Memory 32-bit word" line.long 0x210 "IME3_PROGRAMBUFFER_m_1219,Program Memory 32-bit word" line.long 0x214 "IME3_PROGRAMBUFFER_m_1220,Program Memory 32-bit word" line.long 0x218 "IME3_PROGRAMBUFFER_m_1221,Program Memory 32-bit word" line.long 0x21C "IME3_PROGRAMBUFFER_m_1222,Program Memory 32-bit word" line.long 0x220 "IME3_PROGRAMBUFFER_m_1223,Program Memory 32-bit word" line.long 0x224 "IME3_PROGRAMBUFFER_m_1224,Program Memory 32-bit word" line.long 0x228 "IME3_PROGRAMBUFFER_m_1225,Program Memory 32-bit word" line.long 0x22C "IME3_PROGRAMBUFFER_m_1226,Program Memory 32-bit word" line.long 0x230 "IME3_PROGRAMBUFFER_m_1227,Program Memory 32-bit word" line.long 0x234 "IME3_PROGRAMBUFFER_m_1228,Program Memory 32-bit word" line.long 0x238 "IME3_PROGRAMBUFFER_m_1229,Program Memory 32-bit word" line.long 0x23C "IME3_PROGRAMBUFFER_m_1230,Program Memory 32-bit word" line.long 0x240 "IME3_PROGRAMBUFFER_m_1231,Program Memory 32-bit word" line.long 0x244 "IME3_PROGRAMBUFFER_m_1232,Program Memory 32-bit word" line.long 0x248 "IME3_PROGRAMBUFFER_m_1233,Program Memory 32-bit word" line.long 0x24C "IME3_PROGRAMBUFFER_m_1234,Program Memory 32-bit word" line.long 0x250 "IME3_PROGRAMBUFFER_m_1235,Program Memory 32-bit word" line.long 0x254 "IME3_PROGRAMBUFFER_m_1236,Program Memory 32-bit word" line.long 0x258 "IME3_PROGRAMBUFFER_m_1237,Program Memory 32-bit word" line.long 0x25C "IME3_PROGRAMBUFFER_m_1238,Program Memory 32-bit word" line.long 0x260 "IME3_PROGRAMBUFFER_m_1239,Program Memory 32-bit word" line.long 0x264 "IME3_PROGRAMBUFFER_m_1240,Program Memory 32-bit word" line.long 0x268 "IME3_PROGRAMBUFFER_m_1241,Program Memory 32-bit word" line.long 0x26C "IME3_PROGRAMBUFFER_m_1242,Program Memory 32-bit word" line.long 0x270 "IME3_PROGRAMBUFFER_m_1243,Program Memory 32-bit word" line.long 0x274 "IME3_PROGRAMBUFFER_m_1244,Program Memory 32-bit word" line.long 0x278 "IME3_PROGRAMBUFFER_m_1245,Program Memory 32-bit word" line.long 0x27C "IME3_PROGRAMBUFFER_m_1246,Program Memory 32-bit word" line.long 0x280 "IME3_PROGRAMBUFFER_m_1247,Program Memory 32-bit word" line.long 0x284 "IME3_PROGRAMBUFFER_m_1248,Program Memory 32-bit word" line.long 0x288 "IME3_PROGRAMBUFFER_m_1249,Program Memory 32-bit word" line.long 0x28C "IME3_PROGRAMBUFFER_m_1250,Program Memory 32-bit word" line.long 0x290 "IME3_PROGRAMBUFFER_m_1251,Program Memory 32-bit word" line.long 0x294 "IME3_PROGRAMBUFFER_m_1252,Program Memory 32-bit word" line.long 0x298 "IME3_PROGRAMBUFFER_m_1253,Program Memory 32-bit word" line.long 0x29C "IME3_PROGRAMBUFFER_m_1254,Program Memory 32-bit word" line.long 0x2A0 "IME3_PROGRAMBUFFER_m_1255,Program Memory 32-bit word" line.long 0x2A4 "IME3_PROGRAMBUFFER_m_1256,Program Memory 32-bit word" line.long 0x2A8 "IME3_PROGRAMBUFFER_m_1257,Program Memory 32-bit word" line.long 0x2AC "IME3_PROGRAMBUFFER_m_1258,Program Memory 32-bit word" line.long 0x2B0 "IME3_PROGRAMBUFFER_m_1259,Program Memory 32-bit word" line.long 0x2B4 "IME3_PROGRAMBUFFER_m_1260,Program Memory 32-bit word" line.long 0x2B8 "IME3_PROGRAMBUFFER_m_1261,Program Memory 32-bit word" line.long 0x2BC "IME3_PROGRAMBUFFER_m_1262,Program Memory 32-bit word" line.long 0x2C0 "IME3_PROGRAMBUFFER_m_1263,Program Memory 32-bit word" line.long 0x2C4 "IME3_PROGRAMBUFFER_m_1264,Program Memory 32-bit word" line.long 0x2C8 "IME3_PROGRAMBUFFER_m_1265,Program Memory 32-bit word" line.long 0x2CC "IME3_PROGRAMBUFFER_m_1266,Program Memory 32-bit word" line.long 0x2D0 "IME3_PROGRAMBUFFER_m_1267,Program Memory 32-bit word" line.long 0x2D4 "IME3_PROGRAMBUFFER_m_1268,Program Memory 32-bit word" line.long 0x2D8 "IME3_PROGRAMBUFFER_m_1269,Program Memory 32-bit word" line.long 0x2DC "IME3_PROGRAMBUFFER_m_1270,Program Memory 32-bit word" line.long 0x2E0 "IME3_PROGRAMBUFFER_m_1271,Program Memory 32-bit word" line.long 0x2E4 "IME3_PROGRAMBUFFER_m_1272,Program Memory 32-bit word" line.long 0x2E8 "IME3_PROGRAMBUFFER_m_1273,Program Memory 32-bit word" line.long 0x2EC "IME3_PROGRAMBUFFER_m_1274,Program Memory 32-bit word" line.long 0x2F0 "IME3_PROGRAMBUFFER_m_1275,Program Memory 32-bit word" line.long 0x2F4 "IME3_PROGRAMBUFFER_m_1276,Program Memory 32-bit word" line.long 0x2F8 "IME3_PROGRAMBUFFER_m_1277,Program Memory 32-bit word" line.long 0x2FC "IME3_PROGRAMBUFFER_m_1278,Program Memory 32-bit word" line.long 0x300 "IME3_PROGRAMBUFFER_m_1279,Program Memory 32-bit word" line.long 0x304 "IME3_PROGRAMBUFFER_m_1280,Program Memory 32-bit word" line.long 0x308 "IME3_PROGRAMBUFFER_m_1281,Program Memory 32-bit word" line.long 0x30C "IME3_PROGRAMBUFFER_m_1282,Program Memory 32-bit word" line.long 0x310 "IME3_PROGRAMBUFFER_m_1283,Program Memory 32-bit word" line.long 0x314 "IME3_PROGRAMBUFFER_m_1284,Program Memory 32-bit word" line.long 0x318 "IME3_PROGRAMBUFFER_m_1285,Program Memory 32-bit word" line.long 0x31C "IME3_PROGRAMBUFFER_m_1286,Program Memory 32-bit word" line.long 0x320 "IME3_PROGRAMBUFFER_m_1287,Program Memory 32-bit word" line.long 0x324 "IME3_PROGRAMBUFFER_m_1288,Program Memory 32-bit word" line.long 0x328 "IME3_PROGRAMBUFFER_m_1289,Program Memory 32-bit word" line.long 0x32C "IME3_PROGRAMBUFFER_m_1290,Program Memory 32-bit word" line.long 0x330 "IME3_PROGRAMBUFFER_m_1291,Program Memory 32-bit word" line.long 0x334 "IME3_PROGRAMBUFFER_m_1292,Program Memory 32-bit word" line.long 0x338 "IME3_PROGRAMBUFFER_m_1293,Program Memory 32-bit word" line.long 0x33C "IME3_PROGRAMBUFFER_m_1294,Program Memory 32-bit word" line.long 0x340 "IME3_PROGRAMBUFFER_m_1295,Program Memory 32-bit word" line.long 0x344 "IME3_PROGRAMBUFFER_m_1296,Program Memory 32-bit word" line.long 0x348 "IME3_PROGRAMBUFFER_m_1297,Program Memory 32-bit word" line.long 0x34C "IME3_PROGRAMBUFFER_m_1298,Program Memory 32-bit word" line.long 0x350 "IME3_PROGRAMBUFFER_m_1299,Program Memory 32-bit word" line.long 0x354 "IME3_PROGRAMBUFFER_m_1300,Program Memory 32-bit word" line.long 0x358 "IME3_PROGRAMBUFFER_m_1301,Program Memory 32-bit word" line.long 0x35C "IME3_PROGRAMBUFFER_m_1302,Program Memory 32-bit word" line.long 0x360 "IME3_PROGRAMBUFFER_m_1303,Program Memory 32-bit word" line.long 0x364 "IME3_PROGRAMBUFFER_m_1304,Program Memory 32-bit word" line.long 0x368 "IME3_PROGRAMBUFFER_m_1305,Program Memory 32-bit word" line.long 0x36C "IME3_PROGRAMBUFFER_m_1306,Program Memory 32-bit word" line.long 0x370 "IME3_PROGRAMBUFFER_m_1307,Program Memory 32-bit word" line.long 0x374 "IME3_PROGRAMBUFFER_m_1308,Program Memory 32-bit word" line.long 0x378 "IME3_PROGRAMBUFFER_m_1309,Program Memory 32-bit word" line.long 0x37C "IME3_PROGRAMBUFFER_m_1310,Program Memory 32-bit word" line.long 0x380 "IME3_PROGRAMBUFFER_m_1311,Program Memory 32-bit word" line.long 0x384 "IME3_PROGRAMBUFFER_m_1312,Program Memory 32-bit word" line.long 0x388 "IME3_PROGRAMBUFFER_m_1313,Program Memory 32-bit word" line.long 0x38C "IME3_PROGRAMBUFFER_m_1314,Program Memory 32-bit word" line.long 0x390 "IME3_PROGRAMBUFFER_m_1315,Program Memory 32-bit word" line.long 0x394 "IME3_PROGRAMBUFFER_m_1316,Program Memory 32-bit word" line.long 0x398 "IME3_PROGRAMBUFFER_m_1317,Program Memory 32-bit word" line.long 0x39C "IME3_PROGRAMBUFFER_m_1318,Program Memory 32-bit word" line.long 0x3A0 "IME3_PROGRAMBUFFER_m_1319,Program Memory 32-bit word" line.long 0x3A4 "IME3_PROGRAMBUFFER_m_1320,Program Memory 32-bit word" line.long 0x3A8 "IME3_PROGRAMBUFFER_m_1321,Program Memory 32-bit word" line.long 0x3AC "IME3_PROGRAMBUFFER_m_1322,Program Memory 32-bit word" line.long 0x3B0 "IME3_PROGRAMBUFFER_m_1323,Program Memory 32-bit word" line.long 0x3B4 "IME3_PROGRAMBUFFER_m_1324,Program Memory 32-bit word" line.long 0x3B8 "IME3_PROGRAMBUFFER_m_1325,Program Memory 32-bit word" line.long 0x3BC "IME3_PROGRAMBUFFER_m_1326,Program Memory 32-bit word" line.long 0x3C0 "IME3_PROGRAMBUFFER_m_1327,Program Memory 32-bit word" line.long 0x3C4 "IME3_PROGRAMBUFFER_m_1328,Program Memory 32-bit word" line.long 0x3C8 "IME3_PROGRAMBUFFER_m_1329,Program Memory 32-bit word" line.long 0x3CC "IME3_PROGRAMBUFFER_m_1330,Program Memory 32-bit word" line.long 0x3D0 "IME3_PROGRAMBUFFER_m_1331,Program Memory 32-bit word" line.long 0x3D4 "IME3_PROGRAMBUFFER_m_1332,Program Memory 32-bit word" line.long 0x3D8 "IME3_PROGRAMBUFFER_m_1333,Program Memory 32-bit word" line.long 0x3DC "IME3_PROGRAMBUFFER_m_1334,Program Memory 32-bit word" line.long 0x3E0 "IME3_PROGRAMBUFFER_m_1335,Program Memory 32-bit word" line.long 0x3E4 "IME3_PROGRAMBUFFER_m_1336,Program Memory 32-bit word" line.long 0x3E8 "IME3_PROGRAMBUFFER_m_1337,Program Memory 32-bit word" line.long 0x3EC "IME3_PROGRAMBUFFER_m_1338,Program Memory 32-bit word" line.long 0x3F0 "IME3_PROGRAMBUFFER_m_1339,Program Memory 32-bit word" line.long 0x3F4 "IME3_PROGRAMBUFFER_m_1340,Program Memory 32-bit word" line.long 0x3F8 "IME3_PROGRAMBUFFER_m_1341,Program Memory 32-bit word" line.long 0x3FC "IME3_PROGRAMBUFFER_m_1342,Program Memory 32-bit word" line.long 0x400 "IME3_PROGRAMBUFFER_m_1343,Program Memory 32-bit word" line.long 0x404 "IME3_PROGRAMBUFFER_m_1344,Program Memory 32-bit word" line.long 0x408 "IME3_PROGRAMBUFFER_m_1345,Program Memory 32-bit word" line.long 0x40C "IME3_PROGRAMBUFFER_m_1346,Program Memory 32-bit word" line.long 0x410 "IME3_PROGRAMBUFFER_m_1347,Program Memory 32-bit word" line.long 0x414 "IME3_PROGRAMBUFFER_m_1348,Program Memory 32-bit word" line.long 0x418 "IME3_PROGRAMBUFFER_m_1349,Program Memory 32-bit word" line.long 0x41C "IME3_PROGRAMBUFFER_m_1350,Program Memory 32-bit word" line.long 0x420 "IME3_PROGRAMBUFFER_m_1351,Program Memory 32-bit word" line.long 0x424 "IME3_PROGRAMBUFFER_m_1352,Program Memory 32-bit word" line.long 0x428 "IME3_PROGRAMBUFFER_m_1353,Program Memory 32-bit word" line.long 0x42C "IME3_PROGRAMBUFFER_m_1354,Program Memory 32-bit word" line.long 0x430 "IME3_PROGRAMBUFFER_m_1355,Program Memory 32-bit word" line.long 0x434 "IME3_PROGRAMBUFFER_m_1356,Program Memory 32-bit word" line.long 0x438 "IME3_PROGRAMBUFFER_m_1357,Program Memory 32-bit word" line.long 0x43C "IME3_PROGRAMBUFFER_m_1358,Program Memory 32-bit word" line.long 0x440 "IME3_PROGRAMBUFFER_m_1359,Program Memory 32-bit word" line.long 0x444 "IME3_PROGRAMBUFFER_m_1360,Program Memory 32-bit word" line.long 0x448 "IME3_PROGRAMBUFFER_m_1361,Program Memory 32-bit word" line.long 0x44C "IME3_PROGRAMBUFFER_m_1362,Program Memory 32-bit word" line.long 0x450 "IME3_PROGRAMBUFFER_m_1363,Program Memory 32-bit word" line.long 0x454 "IME3_PROGRAMBUFFER_m_1364,Program Memory 32-bit word" line.long 0x458 "IME3_PROGRAMBUFFER_m_1365,Program Memory 32-bit word" line.long 0x45C "IME3_PROGRAMBUFFER_m_1366,Program Memory 32-bit word" line.long 0x460 "IME3_PROGRAMBUFFER_m_1367,Program Memory 32-bit word" line.long 0x464 "IME3_PROGRAMBUFFER_m_1368,Program Memory 32-bit word" line.long 0x468 "IME3_PROGRAMBUFFER_m_1369,Program Memory 32-bit word" line.long 0x46C "IME3_PROGRAMBUFFER_m_1370,Program Memory 32-bit word" line.long 0x470 "IME3_PROGRAMBUFFER_m_1371,Program Memory 32-bit word" line.long 0x474 "IME3_PROGRAMBUFFER_m_1372,Program Memory 32-bit word" line.long 0x478 "IME3_PROGRAMBUFFER_m_1373,Program Memory 32-bit word" line.long 0x47C "IME3_PROGRAMBUFFER_m_1374,Program Memory 32-bit word" line.long 0x480 "IME3_PROGRAMBUFFER_m_1375,Program Memory 32-bit word" line.long 0x484 "IME3_PROGRAMBUFFER_m_1376,Program Memory 32-bit word" line.long 0x488 "IME3_PROGRAMBUFFER_m_1377,Program Memory 32-bit word" line.long 0x48C "IME3_PROGRAMBUFFER_m_1378,Program Memory 32-bit word" line.long 0x490 "IME3_PROGRAMBUFFER_m_1379,Program Memory 32-bit word" line.long 0x494 "IME3_PROGRAMBUFFER_m_1380,Program Memory 32-bit word" line.long 0x498 "IME3_PROGRAMBUFFER_m_1381,Program Memory 32-bit word" line.long 0x49C "IME3_PROGRAMBUFFER_m_1382,Program Memory 32-bit word" line.long 0x4A0 "IME3_PROGRAMBUFFER_m_1383,Program Memory 32-bit word" line.long 0x4A4 "IME3_PROGRAMBUFFER_m_1384,Program Memory 32-bit word" line.long 0x4A8 "IME3_PROGRAMBUFFER_m_1385,Program Memory 32-bit word" line.long 0x4AC "IME3_PROGRAMBUFFER_m_1386,Program Memory 32-bit word" line.long 0x4B0 "IME3_PROGRAMBUFFER_m_1387,Program Memory 32-bit word" line.long 0x4B4 "IME3_PROGRAMBUFFER_m_1388,Program Memory 32-bit word" line.long 0x4B8 "IME3_PROGRAMBUFFER_m_1389,Program Memory 32-bit word" line.long 0x4BC "IME3_PROGRAMBUFFER_m_1390,Program Memory 32-bit word" line.long 0x4C0 "IME3_PROGRAMBUFFER_m_1391,Program Memory 32-bit word" line.long 0x4C4 "IME3_PROGRAMBUFFER_m_1392,Program Memory 32-bit word" line.long 0x4C8 "IME3_PROGRAMBUFFER_m_1393,Program Memory 32-bit word" line.long 0x4CC "IME3_PROGRAMBUFFER_m_1394,Program Memory 32-bit word" line.long 0x4D0 "IME3_PROGRAMBUFFER_m_1395,Program Memory 32-bit word" line.long 0x4D4 "IME3_PROGRAMBUFFER_m_1396,Program Memory 32-bit word" line.long 0x4D8 "IME3_PROGRAMBUFFER_m_1397,Program Memory 32-bit word" line.long 0x4DC "IME3_PROGRAMBUFFER_m_1398,Program Memory 32-bit word" line.long 0x4E0 "IME3_PROGRAMBUFFER_m_1399,Program Memory 32-bit word" line.long 0x4E4 "IME3_PROGRAMBUFFER_m_1400,Program Memory 32-bit word" line.long 0x4E8 "IME3_PROGRAMBUFFER_m_1401,Program Memory 32-bit word" line.long 0x4EC "IME3_PROGRAMBUFFER_m_1402,Program Memory 32-bit word" line.long 0x4F0 "IME3_PROGRAMBUFFER_m_1403,Program Memory 32-bit word" line.long 0x4F4 "IME3_PROGRAMBUFFER_m_1404,Program Memory 32-bit word" line.long 0x4F8 "IME3_PROGRAMBUFFER_m_1405,Program Memory 32-bit word" line.long 0x4FC "IME3_PROGRAMBUFFER_m_1406,Program Memory 32-bit word" line.long 0x500 "IME3_PROGRAMBUFFER_m_1407,Program Memory 32-bit word" line.long 0x504 "IME3_PROGRAMBUFFER_m_1408,Program Memory 32-bit word" line.long 0x508 "IME3_PROGRAMBUFFER_m_1409,Program Memory 32-bit word" line.long 0x50C "IME3_PROGRAMBUFFER_m_1410,Program Memory 32-bit word" line.long 0x510 "IME3_PROGRAMBUFFER_m_1411,Program Memory 32-bit word" line.long 0x514 "IME3_PROGRAMBUFFER_m_1412,Program Memory 32-bit word" line.long 0x518 "IME3_PROGRAMBUFFER_m_1413,Program Memory 32-bit word" line.long 0x51C "IME3_PROGRAMBUFFER_m_1414,Program Memory 32-bit word" line.long 0x520 "IME3_PROGRAMBUFFER_m_1415,Program Memory 32-bit word" line.long 0x524 "IME3_PROGRAMBUFFER_m_1416,Program Memory 32-bit word" line.long 0x528 "IME3_PROGRAMBUFFER_m_1417,Program Memory 32-bit word" line.long 0x52C "IME3_PROGRAMBUFFER_m_1418,Program Memory 32-bit word" line.long 0x530 "IME3_PROGRAMBUFFER_m_1419,Program Memory 32-bit word" line.long 0x534 "IME3_PROGRAMBUFFER_m_1420,Program Memory 32-bit word" line.long 0x538 "IME3_PROGRAMBUFFER_m_1421,Program Memory 32-bit word" line.long 0x53C "IME3_PROGRAMBUFFER_m_1422,Program Memory 32-bit word" line.long 0x540 "IME3_PROGRAMBUFFER_m_1423,Program Memory 32-bit word" line.long 0x544 "IME3_PROGRAMBUFFER_m_1424,Program Memory 32-bit word" line.long 0x548 "IME3_PROGRAMBUFFER_m_1425,Program Memory 32-bit word" line.long 0x54C "IME3_PROGRAMBUFFER_m_1426,Program Memory 32-bit word" line.long 0x550 "IME3_PROGRAMBUFFER_m_1427,Program Memory 32-bit word" line.long 0x554 "IME3_PROGRAMBUFFER_m_1428,Program Memory 32-bit word" line.long 0x558 "IME3_PROGRAMBUFFER_m_1429,Program Memory 32-bit word" line.long 0x55C "IME3_PROGRAMBUFFER_m_1430,Program Memory 32-bit word" line.long 0x560 "IME3_PROGRAMBUFFER_m_1431,Program Memory 32-bit word" line.long 0x564 "IME3_PROGRAMBUFFER_m_1432,Program Memory 32-bit word" line.long 0x568 "IME3_PROGRAMBUFFER_m_1433,Program Memory 32-bit word" line.long 0x56C "IME3_PROGRAMBUFFER_m_1434,Program Memory 32-bit word" line.long 0x570 "IME3_PROGRAMBUFFER_m_1435,Program Memory 32-bit word" line.long 0x574 "IME3_PROGRAMBUFFER_m_1436,Program Memory 32-bit word" line.long 0x578 "IME3_PROGRAMBUFFER_m_1437,Program Memory 32-bit word" line.long 0x57C "IME3_PROGRAMBUFFER_m_1438,Program Memory 32-bit word" line.long 0x580 "IME3_PROGRAMBUFFER_m_1439,Program Memory 32-bit word" line.long 0x584 "IME3_PROGRAMBUFFER_m_1440,Program Memory 32-bit word" line.long 0x588 "IME3_PROGRAMBUFFER_m_1441,Program Memory 32-bit word" line.long 0x58C "IME3_PROGRAMBUFFER_m_1442,Program Memory 32-bit word" line.long 0x590 "IME3_PROGRAMBUFFER_m_1443,Program Memory 32-bit word" line.long 0x594 "IME3_PROGRAMBUFFER_m_1444,Program Memory 32-bit word" line.long 0x598 "IME3_PROGRAMBUFFER_m_1445,Program Memory 32-bit word" line.long 0x59C "IME3_PROGRAMBUFFER_m_1446,Program Memory 32-bit word" line.long 0x5A0 "IME3_PROGRAMBUFFER_m_1447,Program Memory 32-bit word" line.long 0x5A4 "IME3_PROGRAMBUFFER_m_1448,Program Memory 32-bit word" line.long 0x5A8 "IME3_PROGRAMBUFFER_m_1449,Program Memory 32-bit word" line.long 0x5AC "IME3_PROGRAMBUFFER_m_1450,Program Memory 32-bit word" line.long 0x5B0 "IME3_PROGRAMBUFFER_m_1451,Program Memory 32-bit word" line.long 0x5B4 "IME3_PROGRAMBUFFER_m_1452,Program Memory 32-bit word" line.long 0x5B8 "IME3_PROGRAMBUFFER_m_1453,Program Memory 32-bit word" line.long 0x5BC "IME3_PROGRAMBUFFER_m_1454,Program Memory 32-bit word" line.long 0x5C0 "IME3_PROGRAMBUFFER_m_1455,Program Memory 32-bit word" line.long 0x5C4 "IME3_PROGRAMBUFFER_m_1456,Program Memory 32-bit word" line.long 0x5C8 "IME3_PROGRAMBUFFER_m_1457,Program Memory 32-bit word" line.long 0x5CC "IME3_PROGRAMBUFFER_m_1458,Program Memory 32-bit word" line.long 0x5D0 "IME3_PROGRAMBUFFER_m_1459,Program Memory 32-bit word" line.long 0x5D4 "IME3_PROGRAMBUFFER_m_1460,Program Memory 32-bit word" line.long 0x5D8 "IME3_PROGRAMBUFFER_m_1461,Program Memory 32-bit word" line.long 0x5DC "IME3_PROGRAMBUFFER_m_1462,Program Memory 32-bit word" line.long 0x5E0 "IME3_PROGRAMBUFFER_m_1463,Program Memory 32-bit word" line.long 0x5E4 "IME3_PROGRAMBUFFER_m_1464,Program Memory 32-bit word" line.long 0x5E8 "IME3_PROGRAMBUFFER_m_1465,Program Memory 32-bit word" line.long 0x5EC "IME3_PROGRAMBUFFER_m_1466,Program Memory 32-bit word" line.long 0x5F0 "IME3_PROGRAMBUFFER_m_1467,Program Memory 32-bit word" line.long 0x5F4 "IME3_PROGRAMBUFFER_m_1468,Program Memory 32-bit word" line.long 0x5F8 "IME3_PROGRAMBUFFER_m_1469,Program Memory 32-bit word" line.long 0x5FC "IME3_PROGRAMBUFFER_m_1470,Program Memory 32-bit word" line.long 0x600 "IME3_PROGRAMBUFFER_m_1471,Program Memory 32-bit word" line.long 0x604 "IME3_PROGRAMBUFFER_m_1472,Program Memory 32-bit word" line.long 0x608 "IME3_PROGRAMBUFFER_m_1473,Program Memory 32-bit word" line.long 0x60C "IME3_PROGRAMBUFFER_m_1474,Program Memory 32-bit word" line.long 0x610 "IME3_PROGRAMBUFFER_m_1475,Program Memory 32-bit word" line.long 0x614 "IME3_PROGRAMBUFFER_m_1476,Program Memory 32-bit word" line.long 0x618 "IME3_PROGRAMBUFFER_m_1477,Program Memory 32-bit word" line.long 0x61C "IME3_PROGRAMBUFFER_m_1478,Program Memory 32-bit word" line.long 0x620 "IME3_PROGRAMBUFFER_m_1479,Program Memory 32-bit word" line.long 0x624 "IME3_PROGRAMBUFFER_m_1480,Program Memory 32-bit word" line.long 0x628 "IME3_PROGRAMBUFFER_m_1481,Program Memory 32-bit word" line.long 0x62C "IME3_PROGRAMBUFFER_m_1482,Program Memory 32-bit word" line.long 0x630 "IME3_PROGRAMBUFFER_m_1483,Program Memory 32-bit word" line.long 0x634 "IME3_PROGRAMBUFFER_m_1484,Program Memory 32-bit word" line.long 0x638 "IME3_PROGRAMBUFFER_m_1485,Program Memory 32-bit word" line.long 0x63C "IME3_PROGRAMBUFFER_m_1486,Program Memory 32-bit word" line.long 0x640 "IME3_PROGRAMBUFFER_m_1487,Program Memory 32-bit word" line.long 0x644 "IME3_PROGRAMBUFFER_m_1488,Program Memory 32-bit word" line.long 0x648 "IME3_PROGRAMBUFFER_m_1489,Program Memory 32-bit word" line.long 0x64C "IME3_PROGRAMBUFFER_m_1490,Program Memory 32-bit word" line.long 0x650 "IME3_PROGRAMBUFFER_m_1491,Program Memory 32-bit word" line.long 0x654 "IME3_PROGRAMBUFFER_m_1492,Program Memory 32-bit word" line.long 0x658 "IME3_PROGRAMBUFFER_m_1493,Program Memory 32-bit word" line.long 0x65C "IME3_PROGRAMBUFFER_m_1494,Program Memory 32-bit word" line.long 0x660 "IME3_PROGRAMBUFFER_m_1495,Program Memory 32-bit word" line.long 0x664 "IME3_PROGRAMBUFFER_m_1496,Program Memory 32-bit word" line.long 0x668 "IME3_PROGRAMBUFFER_m_1497,Program Memory 32-bit word" line.long 0x66C "IME3_PROGRAMBUFFER_m_1498,Program Memory 32-bit word" line.long 0x670 "IME3_PROGRAMBUFFER_m_1499,Program Memory 32-bit word" line.long 0x674 "IME3_PROGRAMBUFFER_m_1500,Program Memory 32-bit word" line.long 0x678 "IME3_PROGRAMBUFFER_m_1501,Program Memory 32-bit word" line.long 0x67C "IME3_PROGRAMBUFFER_m_1502,Program Memory 32-bit word" line.long 0x680 "IME3_PROGRAMBUFFER_m_1503,Program Memory 32-bit word" line.long 0x684 "IME3_PROGRAMBUFFER_m_1504,Program Memory 32-bit word" line.long 0x688 "IME3_PROGRAMBUFFER_m_1505,Program Memory 32-bit word" line.long 0x68C "IME3_PROGRAMBUFFER_m_1506,Program Memory 32-bit word" line.long 0x690 "IME3_PROGRAMBUFFER_m_1507,Program Memory 32-bit word" line.long 0x694 "IME3_PROGRAMBUFFER_m_1508,Program Memory 32-bit word" line.long 0x698 "IME3_PROGRAMBUFFER_m_1509,Program Memory 32-bit word" line.long 0x69C "IME3_PROGRAMBUFFER_m_1510,Program Memory 32-bit word" line.long 0x6A0 "IME3_PROGRAMBUFFER_m_1511,Program Memory 32-bit word" line.long 0x6A4 "IME3_PROGRAMBUFFER_m_1512,Program Memory 32-bit word" line.long 0x6A8 "IME3_PROGRAMBUFFER_m_1513,Program Memory 32-bit word" line.long 0x6AC "IME3_PROGRAMBUFFER_m_1514,Program Memory 32-bit word" line.long 0x6B0 "IME3_PROGRAMBUFFER_m_1515,Program Memory 32-bit word" line.long 0x6B4 "IME3_PROGRAMBUFFER_m_1516,Program Memory 32-bit word" line.long 0x6B8 "IME3_PROGRAMBUFFER_m_1517,Program Memory 32-bit word" line.long 0x6BC "IME3_PROGRAMBUFFER_m_1518,Program Memory 32-bit word" line.long 0x6C0 "IME3_PROGRAMBUFFER_m_1519,Program Memory 32-bit word" line.long 0x6C4 "IME3_PROGRAMBUFFER_m_1520,Program Memory 32-bit word" line.long 0x6C8 "IME3_PROGRAMBUFFER_m_1521,Program Memory 32-bit word" line.long 0x6CC "IME3_PROGRAMBUFFER_m_1522,Program Memory 32-bit word" line.long 0x6D0 "IME3_PROGRAMBUFFER_m_1523,Program Memory 32-bit word" line.long 0x6D4 "IME3_PROGRAMBUFFER_m_1524,Program Memory 32-bit word" line.long 0x6D8 "IME3_PROGRAMBUFFER_m_1525,Program Memory 32-bit word" line.long 0x6DC "IME3_PROGRAMBUFFER_m_1526,Program Memory 32-bit word" line.long 0x6E0 "IME3_PROGRAMBUFFER_m_1527,Program Memory 32-bit word" line.long 0x6E4 "IME3_PROGRAMBUFFER_m_1528,Program Memory 32-bit word" line.long 0x6E8 "IME3_PROGRAMBUFFER_m_1529,Program Memory 32-bit word" line.long 0x6EC "IME3_PROGRAMBUFFER_m_1530,Program Memory 32-bit word" line.long 0x6F0 "IME3_PROGRAMBUFFER_m_1531,Program Memory 32-bit word" line.long 0x6F4 "IME3_PROGRAMBUFFER_m_1532,Program Memory 32-bit word" line.long 0x6F8 "IME3_PROGRAMBUFFER_m_1533,Program Memory 32-bit word" line.long 0x6FC "IME3_PROGRAMBUFFER_m_1534,Program Memory 32-bit word" line.long 0x700 "IME3_PROGRAMBUFFER_m_1535,Program Memory 32-bit word" line.long 0x704 "IME3_PROGRAMBUFFER_m_1536,Program Memory 32-bit word" line.long 0x708 "IME3_PROGRAMBUFFER_m_1537,Program Memory 32-bit word" line.long 0x70C "IME3_PROGRAMBUFFER_m_1538,Program Memory 32-bit word" line.long 0x710 "IME3_PROGRAMBUFFER_m_1539,Program Memory 32-bit word" line.long 0x714 "IME3_PROGRAMBUFFER_m_1540,Program Memory 32-bit word" line.long 0x718 "IME3_PROGRAMBUFFER_m_1541,Program Memory 32-bit word" line.long 0x71C "IME3_PROGRAMBUFFER_m_1542,Program Memory 32-bit word" line.long 0x720 "IME3_PROGRAMBUFFER_m_1543,Program Memory 32-bit word" line.long 0x724 "IME3_PROGRAMBUFFER_m_1544,Program Memory 32-bit word" line.long 0x728 "IME3_PROGRAMBUFFER_m_1545,Program Memory 32-bit word" line.long 0x72C "IME3_PROGRAMBUFFER_m_1546,Program Memory 32-bit word" line.long 0x730 "IME3_PROGRAMBUFFER_m_1547,Program Memory 32-bit word" line.long 0x734 "IME3_PROGRAMBUFFER_m_1548,Program Memory 32-bit word" line.long 0x738 "IME3_PROGRAMBUFFER_m_1549,Program Memory 32-bit word" line.long 0x73C "IME3_PROGRAMBUFFER_m_1550,Program Memory 32-bit word" line.long 0x740 "IME3_PROGRAMBUFFER_m_1551,Program Memory 32-bit word" line.long 0x744 "IME3_PROGRAMBUFFER_m_1552,Program Memory 32-bit word" line.long 0x748 "IME3_PROGRAMBUFFER_m_1553,Program Memory 32-bit word" line.long 0x74C "IME3_PROGRAMBUFFER_m_1554,Program Memory 32-bit word" line.long 0x750 "IME3_PROGRAMBUFFER_m_1555,Program Memory 32-bit word" line.long 0x754 "IME3_PROGRAMBUFFER_m_1556,Program Memory 32-bit word" line.long 0x758 "IME3_PROGRAMBUFFER_m_1557,Program Memory 32-bit word" line.long 0x75C "IME3_PROGRAMBUFFER_m_1558,Program Memory 32-bit word" line.long 0x760 "IME3_PROGRAMBUFFER_m_1559,Program Memory 32-bit word" line.long 0x764 "IME3_PROGRAMBUFFER_m_1560,Program Memory 32-bit word" line.long 0x768 "IME3_PROGRAMBUFFER_m_1561,Program Memory 32-bit word" line.long 0x76C "IME3_PROGRAMBUFFER_m_1562,Program Memory 32-bit word" line.long 0x770 "IME3_PROGRAMBUFFER_m_1563,Program Memory 32-bit word" line.long 0x774 "IME3_PROGRAMBUFFER_m_1564,Program Memory 32-bit word" line.long 0x778 "IME3_PROGRAMBUFFER_m_1565,Program Memory 32-bit word" line.long 0x77C "IME3_PROGRAMBUFFER_m_1566,Program Memory 32-bit word" line.long 0x780 "IME3_PROGRAMBUFFER_m_1567,Program Memory 32-bit word" line.long 0x784 "IME3_PROGRAMBUFFER_m_1568,Program Memory 32-bit word" line.long 0x788 "IME3_PROGRAMBUFFER_m_1569,Program Memory 32-bit word" line.long 0x78C "IME3_PROGRAMBUFFER_m_1570,Program Memory 32-bit word" line.long 0x790 "IME3_PROGRAMBUFFER_m_1571,Program Memory 32-bit word" line.long 0x794 "IME3_PROGRAMBUFFER_m_1572,Program Memory 32-bit word" line.long 0x798 "IME3_PROGRAMBUFFER_m_1573,Program Memory 32-bit word" line.long 0x79C "IME3_PROGRAMBUFFER_m_1574,Program Memory 32-bit word" line.long 0x7A0 "IME3_PROGRAMBUFFER_m_1575,Program Memory 32-bit word" line.long 0x7A4 "IME3_PROGRAMBUFFER_m_1576,Program Memory 32-bit word" line.long 0x7A8 "IME3_PROGRAMBUFFER_m_1577,Program Memory 32-bit word" line.long 0x7AC "IME3_PROGRAMBUFFER_m_1578,Program Memory 32-bit word" line.long 0x7B0 "IME3_PROGRAMBUFFER_m_1579,Program Memory 32-bit word" line.long 0x7B4 "IME3_PROGRAMBUFFER_m_1580,Program Memory 32-bit word" line.long 0x7B8 "IME3_PROGRAMBUFFER_m_1581,Program Memory 32-bit word" line.long 0x7BC "IME3_PROGRAMBUFFER_m_1582,Program Memory 32-bit word" line.long 0x7C0 "IME3_PROGRAMBUFFER_m_1583,Program Memory 32-bit word" line.long 0x7C4 "IME3_PROGRAMBUFFER_m_1584,Program Memory 32-bit word" line.long 0x7C8 "IME3_PROGRAMBUFFER_m_1585,Program Memory 32-bit word" line.long 0x7CC "IME3_PROGRAMBUFFER_m_1586,Program Memory 32-bit word" line.long 0x7D0 "IME3_PROGRAMBUFFER_m_1587,Program Memory 32-bit word" line.long 0x7D4 "IME3_PROGRAMBUFFER_m_1588,Program Memory 32-bit word" line.long 0x7D8 "IME3_PROGRAMBUFFER_m_1589,Program Memory 32-bit word" line.long 0x7DC "IME3_PROGRAMBUFFER_m_1590,Program Memory 32-bit word" line.long 0x7E0 "IME3_PROGRAMBUFFER_m_1591,Program Memory 32-bit word" line.long 0x7E4 "IME3_PROGRAMBUFFER_m_1592,Program Memory 32-bit word" line.long 0x7E8 "IME3_PROGRAMBUFFER_m_1593,Program Memory 32-bit word" line.long 0x7EC "IME3_PROGRAMBUFFER_m_1594,Program Memory 32-bit word" line.long 0x7F0 "IME3_PROGRAMBUFFER_m_1595,Program Memory 32-bit word" line.long 0x7F4 "IME3_PROGRAMBUFFER_m_1596,Program Memory 32-bit word" line.long 0x7F8 "IME3_PROGRAMBUFFER_m_1597,Program Memory 32-bit word" line.long 0x7FC "IME3_PROGRAMBUFFER_m_1598,Program Memory 32-bit word" line.long 0x800 "IME3_PROGRAMBUFFER_m_1599,Program Memory 32-bit word" line.long 0x804 "IME3_PROGRAMBUFFER_m_1600,Program Memory 32-bit word" line.long 0x808 "IME3_PROGRAMBUFFER_m_1601,Program Memory 32-bit word" line.long 0x80C "IME3_PROGRAMBUFFER_m_1602,Program Memory 32-bit word" line.long 0x810 "IME3_PROGRAMBUFFER_m_1603,Program Memory 32-bit word" line.long 0x814 "IME3_PROGRAMBUFFER_m_1604,Program Memory 32-bit word" line.long 0x818 "IME3_PROGRAMBUFFER_m_1605,Program Memory 32-bit word" line.long 0x81C "IME3_PROGRAMBUFFER_m_1606,Program Memory 32-bit word" line.long 0x820 "IME3_PROGRAMBUFFER_m_1607,Program Memory 32-bit word" line.long 0x824 "IME3_PROGRAMBUFFER_m_1608,Program Memory 32-bit word" line.long 0x828 "IME3_PROGRAMBUFFER_m_1609,Program Memory 32-bit word" line.long 0x82C "IME3_PROGRAMBUFFER_m_1610,Program Memory 32-bit word" line.long 0x830 "IME3_PROGRAMBUFFER_m_1611,Program Memory 32-bit word" line.long 0x834 "IME3_PROGRAMBUFFER_m_1612,Program Memory 32-bit word" line.long 0x838 "IME3_PROGRAMBUFFER_m_1613,Program Memory 32-bit word" line.long 0x83C "IME3_PROGRAMBUFFER_m_1614,Program Memory 32-bit word" line.long 0x840 "IME3_PROGRAMBUFFER_m_1615,Program Memory 32-bit word" line.long 0x844 "IME3_PROGRAMBUFFER_m_1616,Program Memory 32-bit word" line.long 0x848 "IME3_PROGRAMBUFFER_m_1617,Program Memory 32-bit word" line.long 0x84C "IME3_PROGRAMBUFFER_m_1618,Program Memory 32-bit word" line.long 0x850 "IME3_PROGRAMBUFFER_m_1619,Program Memory 32-bit word" line.long 0x854 "IME3_PROGRAMBUFFER_m_1620,Program Memory 32-bit word" line.long 0x858 "IME3_PROGRAMBUFFER_m_1621,Program Memory 32-bit word" line.long 0x85C "IME3_PROGRAMBUFFER_m_1622,Program Memory 32-bit word" line.long 0x860 "IME3_PROGRAMBUFFER_m_1623,Program Memory 32-bit word" line.long 0x864 "IME3_PROGRAMBUFFER_m_1624,Program Memory 32-bit word" line.long 0x868 "IME3_PROGRAMBUFFER_m_1625,Program Memory 32-bit word" line.long 0x86C "IME3_PROGRAMBUFFER_m_1626,Program Memory 32-bit word" line.long 0x870 "IME3_PROGRAMBUFFER_m_1627,Program Memory 32-bit word" line.long 0x874 "IME3_PROGRAMBUFFER_m_1628,Program Memory 32-bit word" line.long 0x878 "IME3_PROGRAMBUFFER_m_1629,Program Memory 32-bit word" line.long 0x87C "IME3_PROGRAMBUFFER_m_1630,Program Memory 32-bit word" line.long 0x880 "IME3_PROGRAMBUFFER_m_1631,Program Memory 32-bit word" line.long 0x884 "IME3_PROGRAMBUFFER_m_1632,Program Memory 32-bit word" line.long 0x888 "IME3_PROGRAMBUFFER_m_1633,Program Memory 32-bit word" line.long 0x88C "IME3_PROGRAMBUFFER_m_1634,Program Memory 32-bit word" line.long 0x890 "IME3_PROGRAMBUFFER_m_1635,Program Memory 32-bit word" line.long 0x894 "IME3_PROGRAMBUFFER_m_1636,Program Memory 32-bit word" line.long 0x898 "IME3_PROGRAMBUFFER_m_1637,Program Memory 32-bit word" line.long 0x89C "IME3_PROGRAMBUFFER_m_1638,Program Memory 32-bit word" line.long 0x8A0 "IME3_PROGRAMBUFFER_m_1639,Program Memory 32-bit word" line.long 0x8A4 "IME3_PROGRAMBUFFER_m_1640,Program Memory 32-bit word" line.long 0x8A8 "IME3_PROGRAMBUFFER_m_1641,Program Memory 32-bit word" line.long 0x8AC "IME3_PROGRAMBUFFER_m_1642,Program Memory 32-bit word" line.long 0x8B0 "IME3_PROGRAMBUFFER_m_1643,Program Memory 32-bit word" line.long 0x8B4 "IME3_PROGRAMBUFFER_m_1644,Program Memory 32-bit word" line.long 0x8B8 "IME3_PROGRAMBUFFER_m_1645,Program Memory 32-bit word" line.long 0x8BC "IME3_PROGRAMBUFFER_m_1646,Program Memory 32-bit word" line.long 0x8C0 "IME3_PROGRAMBUFFER_m_1647,Program Memory 32-bit word" line.long 0x8C4 "IME3_PROGRAMBUFFER_m_1648,Program Memory 32-bit word" line.long 0x8C8 "IME3_PROGRAMBUFFER_m_1649,Program Memory 32-bit word" line.long 0x8CC "IME3_PROGRAMBUFFER_m_1650,Program Memory 32-bit word" line.long 0x8D0 "IME3_PROGRAMBUFFER_m_1651,Program Memory 32-bit word" line.long 0x8D4 "IME3_PROGRAMBUFFER_m_1652,Program Memory 32-bit word" line.long 0x8D8 "IME3_PROGRAMBUFFER_m_1653,Program Memory 32-bit word" line.long 0x8DC "IME3_PROGRAMBUFFER_m_1654,Program Memory 32-bit word" line.long 0x8E0 "IME3_PROGRAMBUFFER_m_1655,Program Memory 32-bit word" line.long 0x8E4 "IME3_PROGRAMBUFFER_m_1656,Program Memory 32-bit word" line.long 0x8E8 "IME3_PROGRAMBUFFER_m_1657,Program Memory 32-bit word" line.long 0x8EC "IME3_PROGRAMBUFFER_m_1658,Program Memory 32-bit word" line.long 0x8F0 "IME3_PROGRAMBUFFER_m_1659,Program Memory 32-bit word" line.long 0x8F4 "IME3_PROGRAMBUFFER_m_1660,Program Memory 32-bit word" line.long 0x8F8 "IME3_PROGRAMBUFFER_m_1661,Program Memory 32-bit word" line.long 0x8FC "IME3_PROGRAMBUFFER_m_1662,Program Memory 32-bit word" line.long 0x900 "IME3_PROGRAMBUFFER_m_1663,Program Memory 32-bit word" line.long 0x904 "IME3_PROGRAMBUFFER_m_1664,Program Memory 32-bit word" line.long 0x908 "IME3_PROGRAMBUFFER_m_1665,Program Memory 32-bit word" line.long 0x90C "IME3_PROGRAMBUFFER_m_1666,Program Memory 32-bit word" line.long 0x910 "IME3_PROGRAMBUFFER_m_1667,Program Memory 32-bit word" line.long 0x914 "IME3_PROGRAMBUFFER_m_1668,Program Memory 32-bit word" line.long 0x918 "IME3_PROGRAMBUFFER_m_1669,Program Memory 32-bit word" line.long 0x91C "IME3_PROGRAMBUFFER_m_1670,Program Memory 32-bit word" line.long 0x920 "IME3_PROGRAMBUFFER_m_1671,Program Memory 32-bit word" line.long 0x924 "IME3_PROGRAMBUFFER_m_1672,Program Memory 32-bit word" line.long 0x928 "IME3_PROGRAMBUFFER_m_1673,Program Memory 32-bit word" line.long 0x92C "IME3_PROGRAMBUFFER_m_1674,Program Memory 32-bit word" line.long 0x930 "IME3_PROGRAMBUFFER_m_1675,Program Memory 32-bit word" line.long 0x934 "IME3_PROGRAMBUFFER_m_1676,Program Memory 32-bit word" line.long 0x938 "IME3_PROGRAMBUFFER_m_1677,Program Memory 32-bit word" line.long 0x93C "IME3_PROGRAMBUFFER_m_1678,Program Memory 32-bit word" line.long 0x940 "IME3_PROGRAMBUFFER_m_1679,Program Memory 32-bit word" line.long 0x944 "IME3_PROGRAMBUFFER_m_1680,Program Memory 32-bit word" line.long 0x948 "IME3_PROGRAMBUFFER_m_1681,Program Memory 32-bit word" line.long 0x94C "IME3_PROGRAMBUFFER_m_1682,Program Memory 32-bit word" line.long 0x950 "IME3_PROGRAMBUFFER_m_1683,Program Memory 32-bit word" line.long 0x954 "IME3_PROGRAMBUFFER_m_1684,Program Memory 32-bit word" line.long 0x958 "IME3_PROGRAMBUFFER_m_1685,Program Memory 32-bit word" line.long 0x95C "IME3_PROGRAMBUFFER_m_1686,Program Memory 32-bit word" line.long 0x960 "IME3_PROGRAMBUFFER_m_1687,Program Memory 32-bit word" line.long 0x964 "IME3_PROGRAMBUFFER_m_1688,Program Memory 32-bit word" line.long 0x968 "IME3_PROGRAMBUFFER_m_1689,Program Memory 32-bit word" line.long 0x96C "IME3_PROGRAMBUFFER_m_1690,Program Memory 32-bit word" line.long 0x970 "IME3_PROGRAMBUFFER_m_1691,Program Memory 32-bit word" line.long 0x974 "IME3_PROGRAMBUFFER_m_1692,Program Memory 32-bit word" line.long 0x978 "IME3_PROGRAMBUFFER_m_1693,Program Memory 32-bit word" line.long 0x97C "IME3_PROGRAMBUFFER_m_1694,Program Memory 32-bit word" line.long 0x980 "IME3_PROGRAMBUFFER_m_1695,Program Memory 32-bit word" line.long 0x984 "IME3_PROGRAMBUFFER_m_1696,Program Memory 32-bit word" line.long 0x988 "IME3_PROGRAMBUFFER_m_1697,Program Memory 32-bit word" line.long 0x98C "IME3_PROGRAMBUFFER_m_1698,Program Memory 32-bit word" line.long 0x990 "IME3_PROGRAMBUFFER_m_1699,Program Memory 32-bit word" line.long 0x994 "IME3_PROGRAMBUFFER_m_1700,Program Memory 32-bit word" line.long 0x998 "IME3_PROGRAMBUFFER_m_1701,Program Memory 32-bit word" line.long 0x99C "IME3_PROGRAMBUFFER_m_1702,Program Memory 32-bit word" line.long 0x9A0 "IME3_PROGRAMBUFFER_m_1703,Program Memory 32-bit word" line.long 0x9A4 "IME3_PROGRAMBUFFER_m_1704,Program Memory 32-bit word" line.long 0x9A8 "IME3_PROGRAMBUFFER_m_1705,Program Memory 32-bit word" line.long 0x9AC "IME3_PROGRAMBUFFER_m_1706,Program Memory 32-bit word" line.long 0x9B0 "IME3_PROGRAMBUFFER_m_1707,Program Memory 32-bit word" line.long 0x9B4 "IME3_PROGRAMBUFFER_m_1708,Program Memory 32-bit word" line.long 0x9B8 "IME3_PROGRAMBUFFER_m_1709,Program Memory 32-bit word" line.long 0x9BC "IME3_PROGRAMBUFFER_m_1710,Program Memory 32-bit word" line.long 0x9C0 "IME3_PROGRAMBUFFER_m_1711,Program Memory 32-bit word" line.long 0x9C4 "IME3_PROGRAMBUFFER_m_1712,Program Memory 32-bit word" line.long 0x9C8 "IME3_PROGRAMBUFFER_m_1713,Program Memory 32-bit word" line.long 0x9CC "IME3_PROGRAMBUFFER_m_1714,Program Memory 32-bit word" line.long 0x9D0 "IME3_PROGRAMBUFFER_m_1715,Program Memory 32-bit word" line.long 0x9D4 "IME3_PROGRAMBUFFER_m_1716,Program Memory 32-bit word" line.long 0x9D8 "IME3_PROGRAMBUFFER_m_1717,Program Memory 32-bit word" line.long 0x9DC "IME3_PROGRAMBUFFER_m_1718,Program Memory 32-bit word" line.long 0x9E0 "IME3_PROGRAMBUFFER_m_1719,Program Memory 32-bit word" line.long 0x9E4 "IME3_PROGRAMBUFFER_m_1720,Program Memory 32-bit word" line.long 0x9E8 "IME3_PROGRAMBUFFER_m_1721,Program Memory 32-bit word" line.long 0x9EC "IME3_PROGRAMBUFFER_m_1722,Program Memory 32-bit word" line.long 0x9F0 "IME3_PROGRAMBUFFER_m_1723,Program Memory 32-bit word" line.long 0x9F4 "IME3_PROGRAMBUFFER_m_1724,Program Memory 32-bit word" line.long 0x9F8 "IME3_PROGRAMBUFFER_m_1725,Program Memory 32-bit word" line.long 0x9FC "IME3_PROGRAMBUFFER_m_1726,Program Memory 32-bit word" line.long 0xA00 "IME3_PROGRAMBUFFER_m_1727,Program Memory 32-bit word" line.long 0xA04 "IME3_PROGRAMBUFFER_m_1728,Program Memory 32-bit word" line.long 0xA08 "IME3_PROGRAMBUFFER_m_1729,Program Memory 32-bit word" line.long 0xA0C "IME3_PROGRAMBUFFER_m_1730,Program Memory 32-bit word" line.long 0xA10 "IME3_PROGRAMBUFFER_m_1731,Program Memory 32-bit word" line.long 0xA14 "IME3_PROGRAMBUFFER_m_1732,Program Memory 32-bit word" line.long 0xA18 "IME3_PROGRAMBUFFER_m_1733,Program Memory 32-bit word" line.long 0xA1C "IME3_PROGRAMBUFFER_m_1734,Program Memory 32-bit word" line.long 0xA20 "IME3_PROGRAMBUFFER_m_1735,Program Memory 32-bit word" line.long 0xA24 "IME3_PROGRAMBUFFER_m_1736,Program Memory 32-bit word" line.long 0xA28 "IME3_PROGRAMBUFFER_m_1737,Program Memory 32-bit word" line.long 0xA2C "IME3_PROGRAMBUFFER_m_1738,Program Memory 32-bit word" line.long 0xA30 "IME3_PROGRAMBUFFER_m_1739,Program Memory 32-bit word" line.long 0xA34 "IME3_PROGRAMBUFFER_m_1740,Program Memory 32-bit word" line.long 0xA38 "IME3_PROGRAMBUFFER_m_1741,Program Memory 32-bit word" line.long 0xA3C "IME3_PROGRAMBUFFER_m_1742,Program Memory 32-bit word" line.long 0xA40 "IME3_PROGRAMBUFFER_m_1743,Program Memory 32-bit word" line.long 0xA44 "IME3_PROGRAMBUFFER_m_1744,Program Memory 32-bit word" line.long 0xA48 "IME3_PROGRAMBUFFER_m_1745,Program Memory 32-bit word" line.long 0xA4C "IME3_PROGRAMBUFFER_m_1746,Program Memory 32-bit word" line.long 0xA50 "IME3_PROGRAMBUFFER_m_1747,Program Memory 32-bit word" line.long 0xA54 "IME3_PROGRAMBUFFER_m_1748,Program Memory 32-bit word" line.long 0xA58 "IME3_PROGRAMBUFFER_m_1749,Program Memory 32-bit word" line.long 0xA5C "IME3_PROGRAMBUFFER_m_1750,Program Memory 32-bit word" line.long 0xA60 "IME3_PROGRAMBUFFER_m_1751,Program Memory 32-bit word" line.long 0xA64 "IME3_PROGRAMBUFFER_m_1752,Program Memory 32-bit word" line.long 0xA68 "IME3_PROGRAMBUFFER_m_1753,Program Memory 32-bit word" line.long 0xA6C "IME3_PROGRAMBUFFER_m_1754,Program Memory 32-bit word" line.long 0xA70 "IME3_PROGRAMBUFFER_m_1755,Program Memory 32-bit word" line.long 0xA74 "IME3_PROGRAMBUFFER_m_1756,Program Memory 32-bit word" line.long 0xA78 "IME3_PROGRAMBUFFER_m_1757,Program Memory 32-bit word" line.long 0xA7C "IME3_PROGRAMBUFFER_m_1758,Program Memory 32-bit word" line.long 0xA80 "IME3_PROGRAMBUFFER_m_1759,Program Memory 32-bit word" line.long 0xA84 "IME3_PROGRAMBUFFER_m_1760,Program Memory 32-bit word" line.long 0xA88 "IME3_PROGRAMBUFFER_m_1761,Program Memory 32-bit word" line.long 0xA8C "IME3_PROGRAMBUFFER_m_1762,Program Memory 32-bit word" line.long 0xA90 "IME3_PROGRAMBUFFER_m_1763,Program Memory 32-bit word" line.long 0xA94 "IME3_PROGRAMBUFFER_m_1764,Program Memory 32-bit word" line.long 0xA98 "IME3_PROGRAMBUFFER_m_1765,Program Memory 32-bit word" line.long 0xA9C "IME3_PROGRAMBUFFER_m_1766,Program Memory 32-bit word" line.long 0xAA0 "IME3_PROGRAMBUFFER_m_1767,Program Memory 32-bit word" line.long 0xAA4 "IME3_PROGRAMBUFFER_m_1768,Program Memory 32-bit word" line.long 0xAA8 "IME3_PROGRAMBUFFER_m_1769,Program Memory 32-bit word" line.long 0xAAC "IME3_PROGRAMBUFFER_m_1770,Program Memory 32-bit word" line.long 0xAB0 "IME3_PROGRAMBUFFER_m_1771,Program Memory 32-bit word" line.long 0xAB4 "IME3_PROGRAMBUFFER_m_1772,Program Memory 32-bit word" line.long 0xAB8 "IME3_PROGRAMBUFFER_m_1773,Program Memory 32-bit word" line.long 0xABC "IME3_PROGRAMBUFFER_m_1774,Program Memory 32-bit word" line.long 0xAC0 "IME3_PROGRAMBUFFER_m_1775,Program Memory 32-bit word" line.long 0xAC4 "IME3_PROGRAMBUFFER_m_1776,Program Memory 32-bit word" line.long 0xAC8 "IME3_PROGRAMBUFFER_m_1777,Program Memory 32-bit word" line.long 0xACC "IME3_PROGRAMBUFFER_m_1778,Program Memory 32-bit word" line.long 0xAD0 "IME3_PROGRAMBUFFER_m_1779,Program Memory 32-bit word" line.long 0xAD4 "IME3_PROGRAMBUFFER_m_1780,Program Memory 32-bit word" line.long 0xAD8 "IME3_PROGRAMBUFFER_m_1781,Program Memory 32-bit word" line.long 0xADC "IME3_PROGRAMBUFFER_m_1782,Program Memory 32-bit word" line.long 0xAE0 "IME3_PROGRAMBUFFER_m_1783,Program Memory 32-bit word" line.long 0xAE4 "IME3_PROGRAMBUFFER_m_1784,Program Memory 32-bit word" line.long 0xAE8 "IME3_PROGRAMBUFFER_m_1785,Program Memory 32-bit word" line.long 0xAEC "IME3_PROGRAMBUFFER_m_1786,Program Memory 32-bit word" line.long 0xAF0 "IME3_PROGRAMBUFFER_m_1787,Program Memory 32-bit word" line.long 0xAF4 "IME3_PROGRAMBUFFER_m_1788,Program Memory 32-bit word" line.long 0xAF8 "IME3_PROGRAMBUFFER_m_1789,Program Memory 32-bit word" line.long 0xAFC "IME3_PROGRAMBUFFER_m_1790,Program Memory 32-bit word" line.long 0xB00 "IME3_PROGRAMBUFFER_m_1791,Program Memory 32-bit word" line.long 0xB04 "IME3_PROGRAMBUFFER_m_1792,Program Memory 32-bit word" line.long 0xB08 "IME3_PROGRAMBUFFER_m_1793,Program Memory 32-bit word" line.long 0xB0C "IME3_PROGRAMBUFFER_m_1794,Program Memory 32-bit word" line.long 0xB10 "IME3_PROGRAMBUFFER_m_1795,Program Memory 32-bit word" line.long 0xB14 "IME3_PROGRAMBUFFER_m_1796,Program Memory 32-bit word" line.long 0xB18 "IME3_PROGRAMBUFFER_m_1797,Program Memory 32-bit word" line.long 0xB1C "IME3_PROGRAMBUFFER_m_1798,Program Memory 32-bit word" line.long 0xB20 "IME3_PROGRAMBUFFER_m_1799,Program Memory 32-bit word" line.long 0xB24 "IME3_PROGRAMBUFFER_m_1800,Program Memory 32-bit word" line.long 0xB28 "IME3_PROGRAMBUFFER_m_1801,Program Memory 32-bit word" line.long 0xB2C "IME3_PROGRAMBUFFER_m_1802,Program Memory 32-bit word" line.long 0xB30 "IME3_PROGRAMBUFFER_m_1803,Program Memory 32-bit word" line.long 0xB34 "IME3_PROGRAMBUFFER_m_1804,Program Memory 32-bit word" line.long 0xB38 "IME3_PROGRAMBUFFER_m_1805,Program Memory 32-bit word" line.long 0xB3C "IME3_PROGRAMBUFFER_m_1806,Program Memory 32-bit word" line.long 0xB40 "IME3_PROGRAMBUFFER_m_1807,Program Memory 32-bit word" line.long 0xB44 "IME3_PROGRAMBUFFER_m_1808,Program Memory 32-bit word" line.long 0xB48 "IME3_PROGRAMBUFFER_m_1809,Program Memory 32-bit word" line.long 0xB4C "IME3_PROGRAMBUFFER_m_1810,Program Memory 32-bit word" line.long 0xB50 "IME3_PROGRAMBUFFER_m_1811,Program Memory 32-bit word" line.long 0xB54 "IME3_PROGRAMBUFFER_m_1812,Program Memory 32-bit word" line.long 0xB58 "IME3_PROGRAMBUFFER_m_1813,Program Memory 32-bit word" line.long 0xB5C "IME3_PROGRAMBUFFER_m_1814,Program Memory 32-bit word" line.long 0xB60 "IME3_PROGRAMBUFFER_m_1815,Program Memory 32-bit word" line.long 0xB64 "IME3_PROGRAMBUFFER_m_1816,Program Memory 32-bit word" line.long 0xB68 "IME3_PROGRAMBUFFER_m_1817,Program Memory 32-bit word" line.long 0xB6C "IME3_PROGRAMBUFFER_m_1818,Program Memory 32-bit word" line.long 0xB70 "IME3_PROGRAMBUFFER_m_1819,Program Memory 32-bit word" line.long 0xB74 "IME3_PROGRAMBUFFER_m_1820,Program Memory 32-bit word" line.long 0xB78 "IME3_PROGRAMBUFFER_m_1821,Program Memory 32-bit word" line.long 0xB7C "IME3_PROGRAMBUFFER_m_1822,Program Memory 32-bit word" line.long 0xB80 "IME3_PROGRAMBUFFER_m_1823,Program Memory 32-bit word" line.long 0xB84 "IME3_PROGRAMBUFFER_m_1824,Program Memory 32-bit word" line.long 0xB88 "IME3_PROGRAMBUFFER_m_1825,Program Memory 32-bit word" line.long 0xB8C "IME3_PROGRAMBUFFER_m_1826,Program Memory 32-bit word" line.long 0xB90 "IME3_PROGRAMBUFFER_m_1827,Program Memory 32-bit word" line.long 0xB94 "IME3_PROGRAMBUFFER_m_1828,Program Memory 32-bit word" line.long 0xB98 "IME3_PROGRAMBUFFER_m_1829,Program Memory 32-bit word" line.long 0xB9C "IME3_PROGRAMBUFFER_m_1830,Program Memory 32-bit word" line.long 0xBA0 "IME3_PROGRAMBUFFER_m_1831,Program Memory 32-bit word" line.long 0xBA4 "IME3_PROGRAMBUFFER_m_1832,Program Memory 32-bit word" line.long 0xBA8 "IME3_PROGRAMBUFFER_m_1833,Program Memory 32-bit word" line.long 0xBAC "IME3_PROGRAMBUFFER_m_1834,Program Memory 32-bit word" line.long 0xBB0 "IME3_PROGRAMBUFFER_m_1835,Program Memory 32-bit word" line.long 0xBB4 "IME3_PROGRAMBUFFER_m_1836,Program Memory 32-bit word" line.long 0xBB8 "IME3_PROGRAMBUFFER_m_1837,Program Memory 32-bit word" line.long 0xBBC "IME3_PROGRAMBUFFER_m_1838,Program Memory 32-bit word" line.long 0xBC0 "IME3_PROGRAMBUFFER_m_1839,Program Memory 32-bit word" line.long 0xBC4 "IME3_PROGRAMBUFFER_m_1840,Program Memory 32-bit word" line.long 0xBC8 "IME3_PROGRAMBUFFER_m_1841,Program Memory 32-bit word" line.long 0xBCC "IME3_PROGRAMBUFFER_m_1842,Program Memory 32-bit word" line.long 0xBD0 "IME3_PROGRAMBUFFER_m_1843,Program Memory 32-bit word" line.long 0xBD4 "IME3_PROGRAMBUFFER_m_1844,Program Memory 32-bit word" line.long 0xBD8 "IME3_PROGRAMBUFFER_m_1845,Program Memory 32-bit word" line.long 0xBDC "IME3_PROGRAMBUFFER_m_1846,Program Memory 32-bit word" line.long 0xBE0 "IME3_PROGRAMBUFFER_m_1847,Program Memory 32-bit word" line.long 0xBE4 "IME3_PROGRAMBUFFER_m_1848,Program Memory 32-bit word" line.long 0xBE8 "IME3_PROGRAMBUFFER_m_1849,Program Memory 32-bit word" line.long 0xBEC "IME3_PROGRAMBUFFER_m_1850,Program Memory 32-bit word" line.long 0xBF0 "IME3_PROGRAMBUFFER_m_1851,Program Memory 32-bit word" line.long 0xBF4 "IME3_PROGRAMBUFFER_m_1852,Program Memory 32-bit word" line.long 0xBF8 "IME3_PROGRAMBUFFER_m_1853,Program Memory 32-bit word" line.long 0xBFC "IME3_PROGRAMBUFFER_m_1854,Program Memory 32-bit word" line.long 0xC00 "IME3_PROGRAMBUFFER_m_1855,Program Memory 32-bit word" line.long 0xC04 "IME3_PROGRAMBUFFER_m_1856,Program Memory 32-bit word" line.long 0xC08 "IME3_PROGRAMBUFFER_m_1857,Program Memory 32-bit word" line.long 0xC0C "IME3_PROGRAMBUFFER_m_1858,Program Memory 32-bit word" line.long 0xC10 "IME3_PROGRAMBUFFER_m_1859,Program Memory 32-bit word" line.long 0xC14 "IME3_PROGRAMBUFFER_m_1860,Program Memory 32-bit word" line.long 0xC18 "IME3_PROGRAMBUFFER_m_1861,Program Memory 32-bit word" line.long 0xC1C "IME3_PROGRAMBUFFER_m_1862,Program Memory 32-bit word" line.long 0xC20 "IME3_PROGRAMBUFFER_m_1863,Program Memory 32-bit word" line.long 0xC24 "IME3_PROGRAMBUFFER_m_1864,Program Memory 32-bit word" line.long 0xC28 "IME3_PROGRAMBUFFER_m_1865,Program Memory 32-bit word" line.long 0xC2C "IME3_PROGRAMBUFFER_m_1866,Program Memory 32-bit word" line.long 0xC30 "IME3_PROGRAMBUFFER_m_1867,Program Memory 32-bit word" line.long 0xC34 "IME3_PROGRAMBUFFER_m_1868,Program Memory 32-bit word" line.long 0xC38 "IME3_PROGRAMBUFFER_m_1869,Program Memory 32-bit word" line.long 0xC3C "IME3_PROGRAMBUFFER_m_1870,Program Memory 32-bit word" line.long 0xC40 "IME3_PROGRAMBUFFER_m_1871,Program Memory 32-bit word" line.long 0xC44 "IME3_PROGRAMBUFFER_m_1872,Program Memory 32-bit word" line.long 0xC48 "IME3_PROGRAMBUFFER_m_1873,Program Memory 32-bit word" line.long 0xC4C "IME3_PROGRAMBUFFER_m_1874,Program Memory 32-bit word" line.long 0xC50 "IME3_PROGRAMBUFFER_m_1875,Program Memory 32-bit word" line.long 0xC54 "IME3_PROGRAMBUFFER_m_1876,Program Memory 32-bit word" line.long 0xC58 "IME3_PROGRAMBUFFER_m_1877,Program Memory 32-bit word" line.long 0xC5C "IME3_PROGRAMBUFFER_m_1878,Program Memory 32-bit word" line.long 0xC60 "IME3_PROGRAMBUFFER_m_1879,Program Memory 32-bit word" line.long 0xC64 "IME3_PROGRAMBUFFER_m_1880,Program Memory 32-bit word" line.long 0xC68 "IME3_PROGRAMBUFFER_m_1881,Program Memory 32-bit word" line.long 0xC6C "IME3_PROGRAMBUFFER_m_1882,Program Memory 32-bit word" line.long 0xC70 "IME3_PROGRAMBUFFER_m_1883,Program Memory 32-bit word" line.long 0xC74 "IME3_PROGRAMBUFFER_m_1884,Program Memory 32-bit word" line.long 0xC78 "IME3_PROGRAMBUFFER_m_1885,Program Memory 32-bit word" line.long 0xC7C "IME3_PROGRAMBUFFER_m_1886,Program Memory 32-bit word" line.long 0xC80 "IME3_PROGRAMBUFFER_m_1887,Program Memory 32-bit word" line.long 0xC84 "IME3_PROGRAMBUFFER_m_1888,Program Memory 32-bit word" line.long 0xC88 "IME3_PROGRAMBUFFER_m_1889,Program Memory 32-bit word" line.long 0xC8C "IME3_PROGRAMBUFFER_m_1890,Program Memory 32-bit word" line.long 0xC90 "IME3_PROGRAMBUFFER_m_1891,Program Memory 32-bit word" line.long 0xC94 "IME3_PROGRAMBUFFER_m_1892,Program Memory 32-bit word" line.long 0xC98 "IME3_PROGRAMBUFFER_m_1893,Program Memory 32-bit word" line.long 0xC9C "IME3_PROGRAMBUFFER_m_1894,Program Memory 32-bit word" line.long 0xCA0 "IME3_PROGRAMBUFFER_m_1895,Program Memory 32-bit word" line.long 0xCA4 "IME3_PROGRAMBUFFER_m_1896,Program Memory 32-bit word" line.long 0xCA8 "IME3_PROGRAMBUFFER_m_1897,Program Memory 32-bit word" line.long 0xCAC "IME3_PROGRAMBUFFER_m_1898,Program Memory 32-bit word" line.long 0xCB0 "IME3_PROGRAMBUFFER_m_1899,Program Memory 32-bit word" line.long 0xCB4 "IME3_PROGRAMBUFFER_m_1900,Program Memory 32-bit word" line.long 0xCB8 "IME3_PROGRAMBUFFER_m_1901,Program Memory 32-bit word" line.long 0xCBC "IME3_PROGRAMBUFFER_m_1902,Program Memory 32-bit word" line.long 0xCC0 "IME3_PROGRAMBUFFER_m_1903,Program Memory 32-bit word" line.long 0xCC4 "IME3_PROGRAMBUFFER_m_1904,Program Memory 32-bit word" line.long 0xCC8 "IME3_PROGRAMBUFFER_m_1905,Program Memory 32-bit word" line.long 0xCCC "IME3_PROGRAMBUFFER_m_1906,Program Memory 32-bit word" line.long 0xCD0 "IME3_PROGRAMBUFFER_m_1907,Program Memory 32-bit word" line.long 0xCD4 "IME3_PROGRAMBUFFER_m_1908,Program Memory 32-bit word" line.long 0xCD8 "IME3_PROGRAMBUFFER_m_1909,Program Memory 32-bit word" line.long 0xCDC "IME3_PROGRAMBUFFER_m_1910,Program Memory 32-bit word" line.long 0xCE0 "IME3_PROGRAMBUFFER_m_1911,Program Memory 32-bit word" line.long 0xCE4 "IME3_PROGRAMBUFFER_m_1912,Program Memory 32-bit word" line.long 0xCE8 "IME3_PROGRAMBUFFER_m_1913,Program Memory 32-bit word" line.long 0xCEC "IME3_PROGRAMBUFFER_m_1914,Program Memory 32-bit word" line.long 0xCF0 "IME3_PROGRAMBUFFER_m_1915,Program Memory 32-bit word" line.long 0xCF4 "IME3_PROGRAMBUFFER_m_1916,Program Memory 32-bit word" line.long 0xCF8 "IME3_PROGRAMBUFFER_m_1917,Program Memory 32-bit word" line.long 0xCFC "IME3_PROGRAMBUFFER_m_1918,Program Memory 32-bit word" line.long 0xD00 "IME3_PROGRAMBUFFER_m_1919,Program Memory 32-bit word" line.long 0xD04 "IME3_PROGRAMBUFFER_m_1920,Program Memory 32-bit word" line.long 0xD08 "IME3_PROGRAMBUFFER_m_1921,Program Memory 32-bit word" line.long 0xD0C "IME3_PROGRAMBUFFER_m_1922,Program Memory 32-bit word" line.long 0xD10 "IME3_PROGRAMBUFFER_m_1923,Program Memory 32-bit word" line.long 0xD14 "IME3_PROGRAMBUFFER_m_1924,Program Memory 32-bit word" line.long 0xD18 "IME3_PROGRAMBUFFER_m_1925,Program Memory 32-bit word" line.long 0xD1C "IME3_PROGRAMBUFFER_m_1926,Program Memory 32-bit word" line.long 0xD20 "IME3_PROGRAMBUFFER_m_1927,Program Memory 32-bit word" line.long 0xD24 "IME3_PROGRAMBUFFER_m_1928,Program Memory 32-bit word" line.long 0xD28 "IME3_PROGRAMBUFFER_m_1929,Program Memory 32-bit word" line.long 0xD2C "IME3_PROGRAMBUFFER_m_1930,Program Memory 32-bit word" line.long 0xD30 "IME3_PROGRAMBUFFER_m_1931,Program Memory 32-bit word" line.long 0xD34 "IME3_PROGRAMBUFFER_m_1932,Program Memory 32-bit word" line.long 0xD38 "IME3_PROGRAMBUFFER_m_1933,Program Memory 32-bit word" line.long 0xD3C "IME3_PROGRAMBUFFER_m_1934,Program Memory 32-bit word" line.long 0xD40 "IME3_PROGRAMBUFFER_m_1935,Program Memory 32-bit word" line.long 0xD44 "IME3_PROGRAMBUFFER_m_1936,Program Memory 32-bit word" line.long 0xD48 "IME3_PROGRAMBUFFER_m_1937,Program Memory 32-bit word" line.long 0xD4C "IME3_PROGRAMBUFFER_m_1938,Program Memory 32-bit word" line.long 0xD50 "IME3_PROGRAMBUFFER_m_1939,Program Memory 32-bit word" line.long 0xD54 "IME3_PROGRAMBUFFER_m_1940,Program Memory 32-bit word" line.long 0xD58 "IME3_PROGRAMBUFFER_m_1941,Program Memory 32-bit word" line.long 0xD5C "IME3_PROGRAMBUFFER_m_1942,Program Memory 32-bit word" line.long 0xD60 "IME3_PROGRAMBUFFER_m_1943,Program Memory 32-bit word" line.long 0xD64 "IME3_PROGRAMBUFFER_m_1944,Program Memory 32-bit word" line.long 0xD68 "IME3_PROGRAMBUFFER_m_1945,Program Memory 32-bit word" line.long 0xD6C "IME3_PROGRAMBUFFER_m_1946,Program Memory 32-bit word" line.long 0xD70 "IME3_PROGRAMBUFFER_m_1947,Program Memory 32-bit word" line.long 0xD74 "IME3_PROGRAMBUFFER_m_1948,Program Memory 32-bit word" line.long 0xD78 "IME3_PROGRAMBUFFER_m_1949,Program Memory 32-bit word" line.long 0xD7C "IME3_PROGRAMBUFFER_m_1950,Program Memory 32-bit word" line.long 0xD80 "IME3_PROGRAMBUFFER_m_1951,Program Memory 32-bit word" line.long 0xD84 "IME3_PROGRAMBUFFER_m_1952,Program Memory 32-bit word" line.long 0xD88 "IME3_PROGRAMBUFFER_m_1953,Program Memory 32-bit word" line.long 0xD8C "IME3_PROGRAMBUFFER_m_1954,Program Memory 32-bit word" line.long 0xD90 "IME3_PROGRAMBUFFER_m_1955,Program Memory 32-bit word" line.long 0xD94 "IME3_PROGRAMBUFFER_m_1956,Program Memory 32-bit word" line.long 0xD98 "IME3_PROGRAMBUFFER_m_1957,Program Memory 32-bit word" line.long 0xD9C "IME3_PROGRAMBUFFER_m_1958,Program Memory 32-bit word" line.long 0xDA0 "IME3_PROGRAMBUFFER_m_1959,Program Memory 32-bit word" line.long 0xDA4 "IME3_PROGRAMBUFFER_m_1960,Program Memory 32-bit word" line.long 0xDA8 "IME3_PROGRAMBUFFER_m_1961,Program Memory 32-bit word" line.long 0xDAC "IME3_PROGRAMBUFFER_m_1962,Program Memory 32-bit word" line.long 0xDB0 "IME3_PROGRAMBUFFER_m_1963,Program Memory 32-bit word" line.long 0xDB4 "IME3_PROGRAMBUFFER_m_1964,Program Memory 32-bit word" line.long 0xDB8 "IME3_PROGRAMBUFFER_m_1965,Program Memory 32-bit word" line.long 0xDBC "IME3_PROGRAMBUFFER_m_1966,Program Memory 32-bit word" line.long 0xDC0 "IME3_PROGRAMBUFFER_m_1967,Program Memory 32-bit word" line.long 0xDC4 "IME3_PROGRAMBUFFER_m_1968,Program Memory 32-bit word" line.long 0xDC8 "IME3_PROGRAMBUFFER_m_1969,Program Memory 32-bit word" line.long 0xDCC "IME3_PROGRAMBUFFER_m_1970,Program Memory 32-bit word" line.long 0xDD0 "IME3_PROGRAMBUFFER_m_1971,Program Memory 32-bit word" line.long 0xDD4 "IME3_PROGRAMBUFFER_m_1972,Program Memory 32-bit word" line.long 0xDD8 "IME3_PROGRAMBUFFER_m_1973,Program Memory 32-bit word" line.long 0xDDC "IME3_PROGRAMBUFFER_m_1974,Program Memory 32-bit word" line.long 0xDE0 "IME3_PROGRAMBUFFER_m_1975,Program Memory 32-bit word" line.long 0xDE4 "IME3_PROGRAMBUFFER_m_1976,Program Memory 32-bit word" line.long 0xDE8 "IME3_PROGRAMBUFFER_m_1977,Program Memory 32-bit word" line.long 0xDEC "IME3_PROGRAMBUFFER_m_1978,Program Memory 32-bit word" line.long 0xDF0 "IME3_PROGRAMBUFFER_m_1979,Program Memory 32-bit word" line.long 0xDF4 "IME3_PROGRAMBUFFER_m_1980,Program Memory 32-bit word" line.long 0xDF8 "IME3_PROGRAMBUFFER_m_1981,Program Memory 32-bit word" line.long 0xDFC "IME3_PROGRAMBUFFER_m_1982,Program Memory 32-bit word" line.long 0xE00 "IME3_PROGRAMBUFFER_m_1983,Program Memory 32-bit word" line.long 0xE04 "IME3_PROGRAMBUFFER_m_1984,Program Memory 32-bit word" line.long 0xE08 "IME3_PROGRAMBUFFER_m_1985,Program Memory 32-bit word" line.long 0xE0C "IME3_PROGRAMBUFFER_m_1986,Program Memory 32-bit word" line.long 0xE10 "IME3_PROGRAMBUFFER_m_1987,Program Memory 32-bit word" line.long 0xE14 "IME3_PROGRAMBUFFER_m_1988,Program Memory 32-bit word" line.long 0xE18 "IME3_PROGRAMBUFFER_m_1989,Program Memory 32-bit word" line.long 0xE1C "IME3_PROGRAMBUFFER_m_1990,Program Memory 32-bit word" line.long 0xE20 "IME3_PROGRAMBUFFER_m_1991,Program Memory 32-bit word" line.long 0xE24 "IME3_PROGRAMBUFFER_m_1992,Program Memory 32-bit word" line.long 0xE28 "IME3_PROGRAMBUFFER_m_1993,Program Memory 32-bit word" line.long 0xE2C "IME3_PROGRAMBUFFER_m_1994,Program Memory 32-bit word" line.long 0xE30 "IME3_PROGRAMBUFFER_m_1995,Program Memory 32-bit word" line.long 0xE34 "IME3_PROGRAMBUFFER_m_1996,Program Memory 32-bit word" line.long 0xE38 "IME3_PROGRAMBUFFER_m_1997,Program Memory 32-bit word" line.long 0xE3C "IME3_PROGRAMBUFFER_m_1998,Program Memory 32-bit word" line.long 0xE40 "IME3_PROGRAMBUFFER_m_1999,Program Memory 32-bit word" line.long 0xE44 "IME3_PROGRAMBUFFER_m_2000,Program Memory 32-bit word" line.long 0xE48 "IME3_PROGRAMBUFFER_m_2001,Program Memory 32-bit word" line.long 0xE4C "IME3_PROGRAMBUFFER_m_2002,Program Memory 32-bit word" line.long 0xE50 "IME3_PROGRAMBUFFER_m_2003,Program Memory 32-bit word" line.long 0xE54 "IME3_PROGRAMBUFFER_m_2004,Program Memory 32-bit word" line.long 0xE58 "IME3_PROGRAMBUFFER_m_2005,Program Memory 32-bit word" line.long 0xE5C "IME3_PROGRAMBUFFER_m_2006,Program Memory 32-bit word" line.long 0xE60 "IME3_PROGRAMBUFFER_m_2007,Program Memory 32-bit word" line.long 0xE64 "IME3_PROGRAMBUFFER_m_2008,Program Memory 32-bit word" line.long 0xE68 "IME3_PROGRAMBUFFER_m_2009,Program Memory 32-bit word" line.long 0xE6C "IME3_PROGRAMBUFFER_m_2010,Program Memory 32-bit word" line.long 0xE70 "IME3_PROGRAMBUFFER_m_2011,Program Memory 32-bit word" line.long 0xE74 "IME3_PROGRAMBUFFER_m_2012,Program Memory 32-bit word" line.long 0xE78 "IME3_PROGRAMBUFFER_m_2013,Program Memory 32-bit word" line.long 0xE7C "IME3_PROGRAMBUFFER_m_2014,Program Memory 32-bit word" line.long 0xE80 "IME3_PROGRAMBUFFER_m_2015,Program Memory 32-bit word" line.long 0xE84 "IME3_PROGRAMBUFFER_m_2016,Program Memory 32-bit word" line.long 0xE88 "IME3_PROGRAMBUFFER_m_2017,Program Memory 32-bit word" line.long 0xE8C "IME3_PROGRAMBUFFER_m_2018,Program Memory 32-bit word" line.long 0xE90 "IME3_PROGRAMBUFFER_m_2019,Program Memory 32-bit word" line.long 0xE94 "IME3_PROGRAMBUFFER_m_2020,Program Memory 32-bit word" line.long 0xE98 "IME3_PROGRAMBUFFER_m_2021,Program Memory 32-bit word" line.long 0xE9C "IME3_PROGRAMBUFFER_m_2022,Program Memory 32-bit word" line.long 0xEA0 "IME3_PROGRAMBUFFER_m_2023,Program Memory 32-bit word" line.long 0xEA4 "IME3_PROGRAMBUFFER_m_2024,Program Memory 32-bit word" line.long 0xEA8 "IME3_PROGRAMBUFFER_m_2025,Program Memory 32-bit word" line.long 0xEAC "IME3_PROGRAMBUFFER_m_2026,Program Memory 32-bit word" line.long 0xEB0 "IME3_PROGRAMBUFFER_m_2027,Program Memory 32-bit word" line.long 0xEB4 "IME3_PROGRAMBUFFER_m_2028,Program Memory 32-bit word" line.long 0xEB8 "IME3_PROGRAMBUFFER_m_2029,Program Memory 32-bit word" line.long 0xEBC "IME3_PROGRAMBUFFER_m_2030,Program Memory 32-bit word" line.long 0xEC0 "IME3_PROGRAMBUFFER_m_2031,Program Memory 32-bit word" line.long 0xEC4 "IME3_PROGRAMBUFFER_m_2032,Program Memory 32-bit word" line.long 0xEC8 "IME3_PROGRAMBUFFER_m_2033,Program Memory 32-bit word" line.long 0xECC "IME3_PROGRAMBUFFER_m_2034,Program Memory 32-bit word" line.long 0xED0 "IME3_PROGRAMBUFFER_m_2035,Program Memory 32-bit word" line.long 0xED4 "IME3_PROGRAMBUFFER_m_2036,Program Memory 32-bit word" line.long 0xED8 "IME3_PROGRAMBUFFER_m_2037,Program Memory 32-bit word" line.long 0xEDC "IME3_PROGRAMBUFFER_m_2038,Program Memory 32-bit word" line.long 0xEE0 "IME3_PROGRAMBUFFER_m_2039,Program Memory 32-bit word" line.long 0xEE4 "IME3_PROGRAMBUFFER_m_2040,Program Memory 32-bit word" line.long 0xEE8 "IME3_PROGRAMBUFFER_m_2041,Program Memory 32-bit word" line.long 0xEEC "IME3_PROGRAMBUFFER_m_2042,Program Memory 32-bit word" line.long 0xEF0 "IME3_PROGRAMBUFFER_m_2043,Program Memory 32-bit word" line.long 0xEF4 "IME3_PROGRAMBUFFER_m_2044,Program Memory 32-bit word" line.long 0xEF8 "IME3_PROGRAMBUFFER_m_2045,Program Memory 32-bit word" line.long 0xEFC "IME3_PROGRAMBUFFER_m_2046,Program Memory 32-bit word" line.long 0xF00 "IME3_PROGRAMBUFFER_m_2047,Program Memory 32-bit word" tree.end tree "Channel_7" group.long 0x338++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3B8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_7,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x33C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3BC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_7,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x11C++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_7,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x238++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_7,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_7,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x9C++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_7,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x201C++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_7,Program Memory 32-bit word" tree.end tree "Channel_8" group.long 0x340++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3C0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_8,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x344++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3C4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_8,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x120++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_8,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x240++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_8,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_8,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_8,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2020++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_8,Program Memory 32-bit word" tree.end tree "Channel_9" group.long 0x348++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3C8++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_9,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x34C++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3CC++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_9,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x124++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_9,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x248++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_9,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_9,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA4++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_9,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2024++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_9,Program Memory 32-bit word" tree.end group.long 0x450++0x07 line.long 0x00 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION0,Current position in the circular buffer" hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" line.long 0x04 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION1," hexmask.long.word 0x04 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x04 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" group.long 0x428++0x07 line.long 0x00 "IME3_CIRCULAR_BUFFER_DESC0,Circular Buffer 0" bitfld.long 0x00 24. "DIRECTION,Horizontal or Vertical Circularity" "DIRECTION_0,DIRECTION_1" hexmask.long.byte 0x00 16.--23. 1. "OFFSET,In MBs" newline hexmask.long.byte 0x00 8.--15. 1. "CBW,Circular Buffer Width in MBs" hexmask.long.byte 0x00 0.--7. 1. "CBH,Circular Buffer Height in MBs" line.long 0x04 "IME3_CIRCULAR_BUFFER_DESC1,Circular Buffer 1" bitfld.long 0x04 24. "DIRECTION,Horizontal or Vertical Circularity" "DIRECTION_0,DIRECTION_1" hexmask.long.byte 0x04 16.--23. 1. "OFFSET,In MBs" newline hexmask.long.byte 0x04 8.--15. 1. "CBW,Circular Buffer Width in MBs" hexmask.long.byte 0x04 0.--7. 1. "CBH,Circular Buffer Height in MBs" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x474)++0x03 line.long 0x00 "IME3_CIRCULAR_BUFFER_SLIDING_POSITION$1," hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer (X coordinate pixel precision)" repeat.end group.long 0x1FFC++0x03 line.long 0x00 "IME3_COMMANDREG,IME3 command register: a write to this register decodes a command. a read returns 0" group.long 0x440++0x03 line.long 0x00 "IME3_CONDITIONREGISTER,Absolute Minimum Reached bit register. used in Mcomp() operator" hexmask.long.byte 0x00 24.--31. 1. "APPLICATIONCOUNTER1,Counter 1" hexmask.long.byte 0x00 16.--23. 1. "APPLICATIONCOUNTER0,Counter 0" newline bitfld.long 0x00 11. "PARTITIONVALID,Reset by ClearStatus()" "PARTITIONVALID_0,PARTITIONVALID_1" bitfld.long 0x00 9.--10. "BOTTOMRIGHTREFERENCE,L0 L1 Bi" "BOTTOMRIGHTREFERENCE_0,BOTTOMRIGHTREFERENCE_1,BOTTOMRIGHTREFERENCE_2,BOTTOMRIGHTREFERENCE_3" newline bitfld.long 0x00 7.--8. "BOTTOMLEFTREFERENCE,L0 L1 Bi" "BOTTOMLEFTREFERENCE_0,BOTTOMLEFTREFERENCE_1,BOTTOMLEFTREFERENCE_2,BOTTOMLEFTREFERENCE_3" bitfld.long 0x00 5.--6. "TOPRIGHTREFERENCE,L0 L1 Bi" "TOPRIGHTREFERENCE_0,TOPRIGHTREFERENCE_1,TOPRIGHTREFERENCE_2,TOPRIGHTREFERENCE_3" newline bitfld.long 0x00 3.--4. "TOPLEFTREFERENCE,L0 L1 Bi" "TOPLEFTREFERENCE_0,TOPLEFTREFERENCE_1,TOPLEFTREFERENCE_2,TOPLEFTREFERENCE_3" bitfld.long 0x00 1.--2. "PARTITIONTYPE,16x16 16x8 8x16 8x8" "PARTITIONTYPE_0,PARTITIONTYPE_1,PARTITIONTYPE_2,PARTITIONTYPE_3" newline bitfld.long 0x00 0. "ABSMINREACHED,Abs Min Reached bit in Mcomp block" "ABSMINREACHED_0,ABSMINREACHED_1" group.long 0x430++0x07 line.long 0x00 "IME3_CPUSTATUSREG,CPU Status Register provides information on the progress of the CPU execution" bitfld.long 0x00 31. "START_OR_STEP_TAKEN,Set to 1 when Step() Local Interconnect command is received" "START_OR_STEP_TAKEN_0,START_OR_STEP_TAKEN_1" rbitfld.long 0x00 30. "DETECTEDENDOFPGM,This bit is set to '1' when in Debug mode an EndOfPgm instruction or the last instruction of ProgramBuffer has been reached" "DETECTEDENDOFPGM_0,DETECTEDENDOFPGM_1" newline rbitfld.long 0x00 29. "DETECTEDSTOP,This bit is set to '1' when a Stop() command is received" "DETECTEDSTOP_0,DETECTEDSTOP_1" rbitfld.long 0x00 28. "REJECTED_ACCESS,Set when a Local Interconnect read to the Program Memory or an Local Interconnect write are perfromed while the IME3 is still in the EXECUTING state" "0,1" newline bitfld.long 0x00 24.--25. "EXECSTATE," "?,> Halted,> Exectuting,> Completed" rbitfld.long 0x00 19. "RECEIVEDSIGNAL1,Indicates that module has received a Local Interconnect Signal1 Command" "RECEIVEDSIGNAL1_0,RECEIVEDSIGNAL1_1" newline rbitfld.long 0x00 18. "WAITINGONSIGNAL1,Indicates that module is waiting for Local Interconnect Signal1 Command" "WAITINGONSIGNAL1_0,WAITINGONSIGNAL1_1" rbitfld.long 0x00 17. "RECEIVEDSIGNAL0,Indicates that module has received a Local Interconnect Signal0 Command" "RECEIVEDSIGNAL0_0,RECEIVEDSIGNAL0_1" newline rbitfld.long 0x00 16. "WAITINGONSIGNAL0,Indicates that module is waiting for Local Interconnect Signal0 Command" "WAITINGONSIGNAL0_0,WAITINGONSIGNAL0_1" hexmask.long.word 0x00 0.--15. 1. "PC,Address of the instruction currently issued" line.long 0x04 "IME3_CYCLECOUNT,Cycle count register" bitfld.long 0x04 31. "CYCLECOUNTENABLE,When set to 1 cycle counting is enabled" "CYCLECOUNTENABLE_0,CYCLECOUNTENABLE_1" bitfld.long 0x04 30. "CYCLECOUNTRESET,Writing 0 results in no effect" "CYCLECOUNTRESET_0,CYCLECOUNTRESET_1" newline hexmask.long.word 0x04 0.--15. 1. "CYCLECOUNT,Incremets at each cycle if cycleCountEnable equals 1 and if CpuState is EXECUTING" group.long 0x470++0x03 line.long 0x00 "IME3_INTERPOLATION_REFERENCE,The Interpol Reference is the MV based on which the last interpolation has been performed" hexmask.long.word 0x00 16.--31. 1. "Y,This is the 'y' coordinate of the {0 0} point of the interpol planes" hexmask.long.word 0x00 0.--15. 1. "X,x coordinate for the origin point of the interpolation" hgroup.long 0x20++0x03 hide.long 0x00 "IME3_IRQ_EOI,End Of Interrupt number specification" group.long 0x30++0x03 line.long 0x00 "IME3_IRQENABLE_CLR,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x2C++0x03 line.long 0x00 "IME3_IRQENABLE_SET,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x28++0x03 line.long 0x00 "IME3_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Clearable enabled status for event #1 (Gen_it) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x24++0x03 line.long 0x00 "IME3_IRQSTATUS_RAW,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Settable raw status for event #1 (Gen_It) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Settable raw status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x44C++0x03 line.long 0x00 "IME3_MINERRORTHRESHOLD,Minimum Error Threshold register. used in Mcomp() operator" hexmask.long.word 0x00 0.--15. 1. "MINTHRESHOLD,Min Threshold value in Mcomp() block" group.long 0x400++0x03 line.long 0x00 "IME3_MVCT0_3,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_3,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_2,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_1,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_0,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40C++0x03 line.long 0x00 "IME3_MVCT12_14,MV Cost Table" bitfld.long 0x00 16.--20. "MVCT_14,MV Cost Table 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "MVCT_13,MV Cost Table 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "MVCT_12,MV Cost Table 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x404++0x07 line.long 0x00 "IME3_MVCT4_7,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_7,MV Cost Table 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_6,MV Cost Table 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_5,MV Cost Table 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_4,MV Cost Table 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IME3_MVCT8_11,MV Cost Table" bitfld.long 0x04 24.--28. "MVCT_11,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "MVCT_10,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. "MVCT_9,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. "MVCT_8,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x00++0x03 line.long 0x00 "IME3_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "IME3_SYSCONFIG,Clock management configuration" rbitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0_r,?,?,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "?,FREEEMU_1_r" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_r" group.long 0x45C++0x03 line.long 0x00 "IME3_VALID_AREA0_BOTTOM_RIGHT_COORDINATES,Bottom right coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x458++0x03 line.long 0x00 "IME3_VALID_AREA0_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area top left limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x460++0x03 line.long 0x00 "IME3_VALID_AREA1_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x414++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_HI,horizontal vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x410++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_LO,horizontal vector variable (lower bits)" group.long 0x41C++0x03 line.long 0x00 "IME3_VEC_VAR_VER_HI,vertical vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x418++0x03 line.long 0x00 "IME3_VEC_VAR_VER_LO,vertical vector variable (lower bits)" group.long 0x420++0x07 line.long 0x00 "IME3_VECABSMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_ABS_MEAN_HOR,Accumulates |BMT0[0].dx|" line.long 0x04 "IME3_VECABSMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_ABS_MEAN_VER,Accumulates |BMT0[0].dy|" group.long 0x468++0x07 line.long 0x00 "IME3_VECMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_MEAN_HOR,Accumulates BMT0[0].dx" line.long 0x04 "IME3_VECMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_MEAN_VER,Accumulates BMT0[0].dy" width 0x0B tree.end tree.end tree "IVA_Synchronization_Box" sif (cpuis("TDA2PXIVA*")) tree "SYNCBOX_CALC3_ICONT" base ad:0xE2000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_ECD3_ICONT" base ad:0xE3800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_IPE3_ICONT" base ad:0xE2800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_MC3_ICONT" base ad:0xE3000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end endif tree "SYNCBOX_CALC3_L3_MAINInterconnect" base ad:0x5A062000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_ECD3_L3_MAINInterconnect" base ad:0x5A063800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_IPE3_L3_MAINInterconnect" base ad:0x5A062800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end tree "SYNCBOX_MC3_L3_MAINInterconnect" base ad:0x5A063000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC4++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC8++0x07 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_2,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTEASYNCACTMSG_j_3,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" width 0x0B tree.end sif (cpuis("TDA2PXIVA*")) tree "SYNCBOX_ICONT1_ICONT" base ad:0xE0000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_2" rgroup.long 0x214++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_2,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_2,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x218++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_2,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x200++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_3" rgroup.long 0x294++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_3,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x290++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_3,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x298++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_3,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x280++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_4" rgroup.long 0x314++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_4,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_4,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x318++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_4,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x300++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_5" rgroup.long 0x394++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_5,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x390++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_5,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x398++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_5,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x380++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x58++0x03 line.long 0x00 "SYNCBOX_TASKSYNCTYPE,This register is used to code the task synchronous type: Bit =" bitfld.long 0x00 5. "T5,Task synchronous or" "T5_0,T5_1" bitfld.long 0x00 4. "T4,Task synchronous or" "T4_0,T4_1" bitfld.long 0x00 3. "T3,Task synchronous or" "T3_0,T3_1" bitfld.long 0x00 2. "T2,Task synchronous or" "T2_0,T2_1" bitfld.long 0x00 1. "T1,Task synchronous or" "T1_0,T1_1" newline bitfld.long 0x00 0. "T0,Task synchronous or" "T0_0,T0_1" width 0x0B tree.end tree "SYNCBOX_ICONT1_L3_MAINInterconnect" base ad:0x5A060000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_2" rgroup.long 0x214++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_2,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_2,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x218++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_2,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x200++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_3" rgroup.long 0x294++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_3,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x290++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_3,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x298++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_3,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x280++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_4" rgroup.long 0x314++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_4,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_4,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x318++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_4,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x300++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_5" rgroup.long 0x394++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_5,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x390++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_5,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x398++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_5,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x380++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x58++0x03 line.long 0x00 "SYNCBOX_TASKSYNCTYPE,This register is used to code the task synchronous type: Bit =" bitfld.long 0x00 5. "T5,Task synchronous or" "T5_0,T5_1" bitfld.long 0x00 4. "T4,Task synchronous or" "T4_0,T4_1" bitfld.long 0x00 3. "T3,Task synchronous or" "T3_0,T3_1" bitfld.long 0x00 2. "T2,Task synchronous or" "T2_0,T2_1" bitfld.long 0x00 1. "T1,Task synchronous or" "T1_0,T1_1" newline bitfld.long 0x00 0. "T0,Task synchronous or" "T0_0,T0_1" width 0x0B tree.end tree "SYNCBOX_ICONT2_ICONT" base ad:0xE0800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_2" rgroup.long 0x214++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_2,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_2,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x218++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_2,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x200++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_3" rgroup.long 0x294++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_3,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x290++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_3,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x298++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_3,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x280++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_4" rgroup.long 0x314++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_4,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_4,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x318++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_4,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x300++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_5" rgroup.long 0x394++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_5,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x390++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_5,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x398++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_5,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x380++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x58++0x03 line.long 0x00 "SYNCBOX_TASKSYNCTYPE,This register is used to code the task synchronous type: Bit =" bitfld.long 0x00 5. "T5,Task synchronous or" "T5_0,T5_1" bitfld.long 0x00 4. "T4,Task synchronous or" "T4_0,T4_1" bitfld.long 0x00 3. "T3,Task synchronous or" "T3_0,T3_1" bitfld.long 0x00 2. "T2,Task synchronous or" "T2_0,T2_1" bitfld.long 0x00 1. "T1,Task synchronous or" "T1_0,T1_1" newline bitfld.long 0x00 0. "T0,Task synchronous or" "T0_0,T0_1" width 0x0B tree.end tree "SYNCBOX_ICONT2_L3_MAINInterconnect" base ad:0x5A060800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_2" rgroup.long 0x214++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_2,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_2,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x218++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_2,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x200++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_2,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_3" rgroup.long 0x294++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_3,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x290++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_3,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x298++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_3,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x280++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_3,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_4" rgroup.long 0x314++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_4,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_4,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x318++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_4,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x300++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_4,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_5" rgroup.long 0x394++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_5,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x390++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_5,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x398++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_5,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x380++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_5,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x58++0x03 line.long 0x00 "SYNCBOX_TASKSYNCTYPE,This register is used to code the task synchronous type: Bit =" bitfld.long 0x00 5. "T5,Task synchronous or" "T5_0,T5_1" bitfld.long 0x00 4. "T4,Task synchronous or" "T4_0,T4_1" bitfld.long 0x00 3. "T3,Task synchronous or" "T3_0,T3_1" bitfld.long 0x00 2. "T2,Task synchronous or" "T2_0,T2_1" bitfld.long 0x00 1. "T1,Task synchronous or" "T1_0,T1_1" newline bitfld.long 0x00 0. "T0,Task synchronous or" "T0_0,T0_1" width 0x0B tree.end tree "SYNCBOX_ILF3_ICONT" base ad:0xE1000 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" width 0x0B tree.end tree "SYNCBOX_IME3_ICONT" base ad:0xE1800 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" width 0x0B tree.end endif tree "SYNCBOX_ILF3_L3_MAINInterconnect" base ad:0x5A061000 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" width 0x0B tree.end tree "SYNCBOX_IME3_L3_MAINInterconnect" base ad:0x5A061800 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "Acknowledge message,Activation message" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" width 0x0B tree.end tree.end tree "IVA_Video_Direct_Memory_Access" sif (cpuis("TDA2PXIVA*")) tree "VDMA_ICONT" base ad:0xD0000 tree "DMA_Channel_0" group.long 0xF8++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_0,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x78++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_0," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x101C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1010++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x100C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1000++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x178++0x03 line.long 0x00 "VDMA_NON_DETERM_k_0,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x800++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_0," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_1" group.long 0xFC++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_1,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x7C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_1," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x103C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_1,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1030++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_1,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_1,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_1,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x102C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_1,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1020++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_1,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_1,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_1,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17C++0x03 line.long 0x00 "VDMA_NON_DETERM_k_1,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x804++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_1," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_10" group.long 0x120++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_10,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_10," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x115C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1150++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x114C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1140++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x828++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_10," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_100" group.long 0x1C9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x990++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_100," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_101" group.long 0x1CBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_101,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_101,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_101,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_101,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_101,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_101,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_101,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_101,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x994++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_101," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_102" group.long 0x1CDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_102,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_102,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_102,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_102,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_102,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_102,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_102,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_102,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x998++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_102," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_103" group.long 0x1CFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_103,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_103,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_103,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_103,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_103,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_103,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_103,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_103,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x99C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_103," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_104" group.long 0x1D1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_104,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_104,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_104,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_104,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_104,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_104,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_104,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_104,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_104," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_105" group.long 0x1D3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_105,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_105,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_105,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_105,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_105,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_105,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_105,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_105,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_105," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_106" group.long 0x1D5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_106,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_106,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_106,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_106,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_106,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_106,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_106,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_106,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_106," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_107" group.long 0x1D7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_107,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_107,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_107,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_107,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_107,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_107,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_107,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_107,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9AC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_107," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_108" group.long 0x1D9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_108,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_108,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_108,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_108,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_108,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_108,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_108,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_108,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_108," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_109" group.long 0x1DBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_109,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_109,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_109,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_109,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_109,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_109,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_109,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_109,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_109," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_11" group.long 0x124++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_11,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_11," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x117C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_11,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1170++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_11,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_11,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_11,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x116C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_11,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1160++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_11,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_11,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_11,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x82C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_11," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_110" group.long 0x1DDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_110,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_110,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_110,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_110,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_110,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_110,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_110,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_110,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_110," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_111" group.long 0x1DFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_111,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_111,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_111,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_111,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_111,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_111,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_111,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_111,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9BC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_111," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_112" group.long 0x1E1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_112," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_113" group.long 0x1E3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_113,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_113,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_113,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_113,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_113,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_113,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_113,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_113,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_113," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_114" group.long 0x1E5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_114,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_114,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_114,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_114,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_114,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_114,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_114,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_114,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_114," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_115" group.long 0x1E7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_115,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_115,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_115,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_115,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_115,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_115,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_115,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_115,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9CC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_115," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_116" group.long 0x1E9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_116,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_116,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_116,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_116,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_116,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_116,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_116,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_116,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_116," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_117" group.long 0x1EBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_117,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_117,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_117,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_117,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_117,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_117,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_117,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_117,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_117," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_118" group.long 0x1EDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_118,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ED0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_118,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_118,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_118,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ECC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_118,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_118,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_118,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_118,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_118," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_119" group.long 0x1EFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_119,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_119,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_119,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_119,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_119,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_119,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_119,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_119,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9DC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_119," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_12" group.long 0x128++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_12,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_12," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x119C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_12,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1190++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_12,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_12,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_12,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x118C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_12,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1180++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_12,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_12,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_12,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x830++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_12," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_120" group.long 0x1F1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_120,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_120,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_120,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_120,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_120,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_120,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_120,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_120,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_120," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_121" group.long 0x1F3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_121,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_121,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_121,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_121,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_121,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_121,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_121,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_121,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_121," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_122" group.long 0x1F5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_122,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_122,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_122,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_122,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_122,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_122,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_122,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_122,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_122," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_123" group.long 0x1F7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_123,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_123,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_123,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_123,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_123,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_123,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_123,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_123,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9EC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_123," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_124" group.long 0x1F9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_124,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_124,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_124,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_124,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_124,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_124,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_124,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_124,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_124," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_125" group.long 0x1FBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_125,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_125,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_125,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_125,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_125,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_125,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_125,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_125,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_125," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_126" group.long 0x1FDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_126,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_126,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_126,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_126,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_126,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_126,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_126,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_126,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_126," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_127" group.long 0x1FFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_127,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_127,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_127,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_127,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_127,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_127,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_127,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_127,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9FC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_127," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_13" group.long 0x12C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_13,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xAC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_13," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_13,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_13,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_13,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_13,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_13,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_13,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_13,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_13,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x834++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_13," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_14" group.long 0x130++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_14,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_14," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_14,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_14,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_14,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_14,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_14,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_14,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_14,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_14,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x838++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_14," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_15" group.long 0x134++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_15,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_15," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_15,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_15,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_15,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_15,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_15,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_15,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_15,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_15,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x83C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_15," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_16" group.long 0x138++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_16,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_16," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x121C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_16,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1210++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_16,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_16,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_16,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x120C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_16,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1200++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_16,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_16,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_16,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x840++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_16," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_17" group.long 0x13C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_17,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xBC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_17," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x123C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_17,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1230++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_17,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_17,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_17,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x122C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_17,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1220++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_17,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_17,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_17,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x844++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_17," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_18" group.long 0x140++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_18,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_18," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x125C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_18,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1250++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_18,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_18,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_18,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x124C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_18,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1240++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_18,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_18,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_18,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x848++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_18," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_19" group.long 0x144++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_19,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_19," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x127C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_19,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1270++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_19,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_19,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_19,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x126C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_19,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1260++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_19,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_19,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_19,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x84C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_19," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_2" group.long 0x100++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_2,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x80++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_2," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x105C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_2,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1050++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_2,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_2,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_2,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x104C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_2,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1040++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_2,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_2,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_2,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x180++0x03 line.long 0x00 "VDMA_NON_DETERM_k_2,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x808++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_2," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_20" group.long 0x148++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_20,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_20," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x129C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1290++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x128C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1280++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x850++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_20," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_21" group.long 0x14C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_21,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xCC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_21," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_21,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_21,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_21,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_21,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_21,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_21,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_21,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_21,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x854++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_21," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_22" group.long 0x150++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_22,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_22," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_22,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_22,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_22,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_22,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_22,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_22,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_22,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_22,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x858++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_22," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_23" group.long 0x154++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_23,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_23," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_23,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_23,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_23,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_23,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_23,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_23,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_23,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_23,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x85C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_23," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_24" group.long 0x158++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_24,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_24," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x131C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_24,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1310++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_24,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_24,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_24,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x130C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_24,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1300++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_24,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_24,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_24,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x860++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_24," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_25" group.long 0x15C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_25,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xDC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_25," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x133C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_25,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1330++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_25,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_25,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_25,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x132C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_25,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1320++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_25,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_25,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_25,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x864++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_25," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_26" group.long 0x160++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_26,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_26," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x135C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_26,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1350++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_26,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_26,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_26,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x134C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_26,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1340++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_26,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_26,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_26,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x868++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_26," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_27" group.long 0x164++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_27,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_27," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x137C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_27,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1370++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_27,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_27,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_27,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x136C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_27,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1360++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_27,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_27,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_27,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x86C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_27," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_28" group.long 0x168++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_28,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_28," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x139C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_28,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1390++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_28,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_28,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_28,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x138C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_28,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1380++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_28,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_28,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_28,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x870++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_28," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_29" group.long 0x16C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_29,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xEC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_29," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_29,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_29,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_29,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_29,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_29,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_29,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_29,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_29,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x874++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_29," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_3" group.long 0x104++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_3,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x84++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_3," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x107C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_3,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1070++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_3,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_3,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_3,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x106C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_3,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1060++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_3,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_3,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_3,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x184++0x03 line.long 0x00 "VDMA_NON_DETERM_k_3,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x80C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_3," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_30" group.long 0x170++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_30,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xF0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_30," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_30,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_30,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_30,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_30,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_30,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_30,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_30,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_30,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x878++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_30," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_31" group.long 0x174++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_31,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xF4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_31," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_31,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_31,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_31,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_31,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_31,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_31,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_31,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_31,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x87C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_31," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_32" group.long 0x141C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1410++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x140C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1400++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x880++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_32," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_33" group.long 0x143C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_33,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1430++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_33,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_33,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_33,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x142C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_33,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1420++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_33,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_33,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_33,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x884++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_33," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_34" group.long 0x145C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_34,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1450++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_34,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_34,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_34,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x144C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_34,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1440++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_34,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_34,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_34,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x888++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_34," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_35" group.long 0x147C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_35,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1470++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_35,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_35,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_35,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x146C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_35,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1460++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_35,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_35,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_35,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x88C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_35," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_36" group.long 0x149C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_36,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1490++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_36,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_36,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_36,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x148C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_36,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1480++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_36,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_36,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_36,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x890++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_36," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_37" group.long 0x14BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_37,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_37,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_37,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_37,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_37,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_37,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_37,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_37,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x894++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_37," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_38" group.long 0x14DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_38,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_38,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_38,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_38,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_38,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_38,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_38,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_38,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x898++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_38," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_39" group.long 0x14FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_39,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_39,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_39,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_39,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_39,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_39,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_39,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_39,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x89C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_39," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_4" group.long 0x108++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_4,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x88++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_4," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x109C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_4,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1090++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_4,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_4,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_4,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x108C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_4,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1080++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_4,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_4,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_4,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x810++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_4," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_40" group.long 0x151C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_40,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1510++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_40,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_40,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_40,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x150C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_40,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1500++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_40,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_40,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_40,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_40," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_41" group.long 0x153C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_41,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1530++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_41,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_41,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_41,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x152C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_41,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1520++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_41,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_41,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_41,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_41," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_42" group.long 0x155C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_42,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1550++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_42,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_42,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_42,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x154C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_42,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1540++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_42,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_42,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_42,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_42," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_43" group.long 0x157C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_43,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1570++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_43,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_43,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_43,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x156C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_43,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1560++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_43,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_43,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_43,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8AC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_43," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_44" group.long 0x159C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_44,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1590++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_44,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_44,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_44,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x158C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_44,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1580++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_44,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_44,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_44,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_44," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_45" group.long 0x15BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_45,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_45,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_45,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_45,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_45,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_45,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_45,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_45,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_45," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_46" group.long 0x15DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_46,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_46,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_46,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_46,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_46,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_46,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_46,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_46,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_46," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_47" group.long 0x15FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_47,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_47,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_47,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_47,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_47,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_47,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_47,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_47,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8BC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_47," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_48" group.long 0x161C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1610++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x160C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1600++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_48," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_49" group.long 0x163C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_49,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1630++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_49,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_49,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_49,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x162C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_49,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1620++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_49,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_49,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_49,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_49," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_5" group.long 0x10C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_5,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x8C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_5," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_5,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_5,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_5,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_5,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_5,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_5,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_5,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_5,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x814++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_5," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_50" group.long 0x165C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_50,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1650++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_50,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_50,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_50,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x164C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_50,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1640++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_50,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_50,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_50,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_50," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_51" group.long 0x167C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_51,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1670++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_51,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_51,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_51,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x166C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_51,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1660++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_51,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_51,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_51,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8CC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_51," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_52" group.long 0x169C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_52,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1690++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_52,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_52,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_52,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x168C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_52,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1680++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_52,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_52,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_52,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_52," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_53" group.long 0x16BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_53,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_53,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_53,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_53,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_53,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_53,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_53,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_53,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_53," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_54" group.long 0x16DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_54,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_54,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_54,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_54,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_54,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_54,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_54,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_54,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_54," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_55" group.long 0x16FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_55,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_55,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_55,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_55,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_55,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_55,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_55,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_55,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8DC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_55," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_56" group.long 0x171C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_56,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1710++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_56,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_56,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_56,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x170C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_56,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1700++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_56,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_56,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_56,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_56," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_57" group.long 0x173C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_57,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1730++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_57,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_57,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_57,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x172C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_57,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1720++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_57,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_57,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_57,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_57," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_58" group.long 0x175C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_58,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1750++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_58,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_58,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_58,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x174C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_58,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1740++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_58,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_58,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_58,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_58," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_59" group.long 0x177C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_59,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1770++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_59,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_59,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_59,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x176C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_59,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1760++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_59,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_59,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_59,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8EC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_59," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_6" group.long 0x110++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_6,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x90++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_6," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_6,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_6,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_6,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_6,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_6,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_6,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_6,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_6,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x818++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_6," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_60" group.long 0x179C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_60,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1790++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_60,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_60,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_60,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x178C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_60,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1780++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_60,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_60,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_60,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_60," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_61" group.long 0x17BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_61,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_61,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_61,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_61,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_61,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_61,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_61,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_61,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_61," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_62" group.long 0x17DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_62,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_62,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_62,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_62,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_62,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_62,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_62,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_62,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_62," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_63" group.long 0x17FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_63,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_63,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_63,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_63,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_63,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_63,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_63,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_63,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8FC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_63," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_64" group.long 0x181C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1810++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x180C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1800++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x900++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_64," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_65" group.long 0x183C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_65,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1830++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_65,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_65,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_65,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x182C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_65,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1820++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_65,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_65,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_65,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x904++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_65," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_66" group.long 0x185C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_66,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1850++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_66,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_66,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_66,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x184C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_66,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1840++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_66,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_66,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_66,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x908++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_66," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_67" group.long 0x187C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_67,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1870++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_67,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_67,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_67,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x186C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_67,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1860++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_67,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_67,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_67,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x90C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_67," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_68" group.long 0x189C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_68,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1890++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_68,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_68,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_68,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x188C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_68,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1880++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_68,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_68,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_68,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x910++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_68," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_69" group.long 0x18BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_69,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_69,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_69,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_69,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_69,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_69,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_69,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_69,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x914++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_69," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_7" group.long 0x114++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_7,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x94++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_7," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_7,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_7,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_7,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_7,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_7,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_7,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_7,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_7,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x81C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_7," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_70" group.long 0x18DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_70,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_70,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_70,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_70,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_70,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_70,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_70,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_70,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x918++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_70," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_71" group.long 0x18FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_71,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_71,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_71,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_71,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_71,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_71,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_71,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_71,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x91C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_71," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_72" group.long 0x191C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_72,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1910++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_72,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_72,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_72,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x190C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_72,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1900++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_72,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_72,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_72,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x920++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_72," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_73" group.long 0x193C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_73,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1930++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_73,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_73,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_73,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x192C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_73,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1920++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_73,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_73,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_73,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x924++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_73," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_74" group.long 0x195C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_74,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1950++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_74,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_74,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_74,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x194C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_74,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1940++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_74,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_74,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_74,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x928++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_74," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_75" group.long 0x197C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_75,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1970++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_75,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_75,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_75,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x196C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_75,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1960++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_75,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_75,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_75,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x92C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_75," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_76" group.long 0x199C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_76,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1990++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_76,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_76,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_76,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x198C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_76,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1980++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_76,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_76,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_76,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x930++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_76," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_77" group.long 0x19BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_77,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_77,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_77,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_77,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_77,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_77,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_77,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_77,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x934++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_77," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_78" group.long 0x19DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_78,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_78,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_78,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_78,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_78,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_78,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_78,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_78,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x938++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_78," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_79" group.long 0x19FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_79,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_79,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_79,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_79,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_79,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_79,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_79,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_79,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x93C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_79," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_8" group.long 0x118++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_8,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x98++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_8," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x111C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_8,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1110++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_8,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_8,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_8,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x110C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_8,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1100++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_8,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_8,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_8,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x820++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_8," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_80" group.long 0x1A1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x940++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_80," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_81" group.long 0x1A3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_81,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_81,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_81,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_81,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_81,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_81,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_81,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_81,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x944++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_81," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_82" group.long 0x1A5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_82,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_82,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_82,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_82,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_82,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_82,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_82,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_82,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x948++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_82," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_83" group.long 0x1A7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_83,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_83,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_83,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_83,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_83,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_83,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_83,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_83,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x94C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_83," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_84" group.long 0x1A9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_84,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_84,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_84,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_84,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_84,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_84,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_84,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_84,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x950++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_84," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_85" group.long 0x1ABC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_85,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_85,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_85,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_85,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_85,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_85,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_85,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_85,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x954++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_85," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_86" group.long 0x1ADC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_86,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_86,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_86,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_86,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ACC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_86,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_86,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_86,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_86,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x958++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_86," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_87" group.long 0x1AFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_87,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_87,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_87,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_87,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_87,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_87,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_87,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_87,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x95C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_87," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_88" group.long 0x1B1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_88,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_88,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_88,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_88,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_88,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_88,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_88,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_88,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x960++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_88," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_89" group.long 0x1B3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_89,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_89,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_89,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_89,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_89,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_89,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_89,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_89,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x964++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_89," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_9" group.long 0x11C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_9,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x9C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_9," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x113C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_9,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1130++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_9,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_9,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_9,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x112C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_9,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1120++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_9,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_9,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_9,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x824++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_9," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_90" group.long 0x1B5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_90,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_90,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_90,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_90,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_90,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_90,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_90,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_90,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x968++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_90," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_91" group.long 0x1B7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_91,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_91,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_91,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_91,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_91,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_91,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_91,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_91,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x96C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_91," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_92" group.long 0x1B9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_92,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_92,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_92,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_92,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_92,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_92,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_92,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_92,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x970++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_92," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_93" group.long 0x1BBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_93,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_93,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_93,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_93,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_93,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_93,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_93,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_93,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x974++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_93," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_94" group.long 0x1BDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_94,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_94,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_94,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_94,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_94,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_94,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_94,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_94,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x978++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_94," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_95" group.long 0x1BFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_95,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_95,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_95,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_95,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_95,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_95,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_95,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_95,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x97C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_95," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_96" group.long 0x1C1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_96,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_96,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_96,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_96,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_96,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_96,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_96,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_96,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x980++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_96," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_97" group.long 0x1C3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_97,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_97,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_97,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_97,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_97,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_97,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_97,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_97,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x984++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_97," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_98" group.long 0x1C5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_98,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_98,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_98,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_98,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_98,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_98,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_98,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_98,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x988++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_98," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_99" group.long 0x1C7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_99,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_99,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_99,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_99,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_99,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_99,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_99,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_99,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x98C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_99," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end rgroup.long 0x58++0x03 line.long 0x00 "VDMA_ASYNCHR_LIST_LEVEL," bitfld.long 0x00 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of asynchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" rgroup.long 0x64++0x07 line.long 0x00 "VDMA_CONTEXT_STATUS,When individual bit is reset. corresponding context is available" bitfld.long 0x00 15. "CONTEXT15," "CONTEXT15_0,CONTEXT15_1" bitfld.long 0x00 14. "CONTEXT14," "CONTEXT14_0,CONTEXT14_1" newline bitfld.long 0x00 13. "CONTEXT13," "CONTEXT13_0,CONTEXT13_1" bitfld.long 0x00 12. "CONTEXT12," "CONTEXT12_0,CONTEXT12_1" newline bitfld.long 0x00 11. "CONTEXT11," "CONTEXT11_0,CONTEXT11_1" bitfld.long 0x00 10. "CONTEXT10," "CONTEXT10_0,CONTEXT10_1" newline bitfld.long 0x00 9. "CONTEXT9," "CONTEXT9_0,CONTEXT9_1" bitfld.long 0x00 8. "CONTEXT8," "CONTEXT8_0,CONTEXT8_1" newline bitfld.long 0x00 7. "CONTEXT7," "CONTEXT7_0,CONTEXT7_1" bitfld.long 0x00 6. "CONTEXT6," "CONTEXT6_0,CONTEXT6_1" newline bitfld.long 0x00 5. "CONTEXT5," "CONTEXT5_0,CONTEXT5_1" bitfld.long 0x00 4. "CONTEXT4," "CONTEXT4_0,CONTEXT4_1" newline bitfld.long 0x00 3. "CONTEXT3," "CONTEXT3_0,CONTEXT3_1" bitfld.long 0x00 2. "CONTEXT2," "CONTEXT2_0,CONTEXT2_1" newline bitfld.long 0x00 1. "CONTEXT1," "CONTEXT1_0,CONTEXT1_1" bitfld.long 0x00 0. "CONTEXT0," "CONTEXT0_0,CONTEXT0_1" line.long 0x04 "VDMA_GROUP_TRIGGER,Register entry for software user to trigger deterministic (only) groups through CPU writes" group.long 0x20++0x03 line.long 0x00 "VDMA_IRQ_EOI,End Of Interrupt number specification" abitfld.long 0x00 0.--7. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0x00=EOI for interrupt..,0x01=EOI for interrupt..,0x02=EOI for interrupt..,0x03=N/A,0x04=N/A,0x05=N/A,0x06=N/A,0x07=N/A" group.long 0x74++0x03 line.long 0x00 "VDMA_IRQ_NEOG,Sets whether end of group signaling should be set through external hardware lines (like the deterministic group triggers) or wrap into interrupt line" group.long 0x30++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" group.long 0x40++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" group.long 0x50++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x2C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" group.long 0x3C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" group.long 0x4C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x28++0x03 line.long 0x00 "VDMA_IRQSTATUS_0,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #0" group.long 0x38++0x03 line.long 0x00 "VDMA_IRQSTATUS_1,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #1" group.long 0x48++0x03 line.long 0x00 "VDMA_IRQSTATUS_2,Per-error event 'enabled' interrupt status vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x24++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_0,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #0" group.long 0x34++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_1,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #1" group.long 0x44++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_2,Per-error event raw interrupt status vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x70++0x03 line.long 0x00 "VDMA_MAX_CONTEXT_ASYNCHR,Software user configurable maximum number of context asynchronous list can get benefit of" bitfld.long 0x00 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to asynchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" group.long 0x6C++0x03 line.long 0x00 "VDMA_MAX_CONTEXT_SYNCHR,Software user configurable maximum number of context synchronous list can get benefit of" bitfld.long 0x00 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to synchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" rgroup.long 0x5C++0x03 line.long 0x00 "VDMA_NON_DETERM_FIFO_LEVEL," hexmask.long.byte 0x00 0.--7. 1. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for read address generator to pick them from list) entries of nondeterministic object descriptor FIFO" rgroup.long 0x00++0x03 line.long 0x00 "VDMA_REVISION,IP revision identifier" rgroup.long 0x54++0x03 line.long 0x00 "VDMA_SYNCHR_LIST_LEVEL," bitfld.long 0x00 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of synchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" group.long 0x10++0x03 line.long 0x00 "VDMA_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Software reset ongoing" group.long 0x60++0x03 line.long 0x00 "VDMA_TBA,TILER address mapping" bitfld.long 0x00 0.--2. "OCP_3MSB," "OCP_3MSB_0,OCP_3MSB_1,OCP_3MSB_2,OCP_3MSB_3,OCP_3MSB_4,OCP_3MSB_5,OCP_3MSB_6,OCP_3MSB_7" width 0x0B tree.end endif tree "VDMA_L3_MAINInterconnect" base ad:0x5A050000 tree "DMA_Channel_0" group.long 0xF8++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_0,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x78++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_0," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x101C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1010++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x100C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1000++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x178++0x03 line.long 0x00 "VDMA_NON_DETERM_k_0,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x800++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_0," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_1" group.long 0xFC++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_1,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x7C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_1," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x103C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_1,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1030++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_1,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_1,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_1,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x102C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_1,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1020++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_1,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_1,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_1,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17C++0x03 line.long 0x00 "VDMA_NON_DETERM_k_1,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x804++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_1," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_10" group.long 0x120++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_10,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_10," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x115C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1150++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x114C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1140++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x828++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_10," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_100" group.long 0x1C9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x990++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_100," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_101" group.long 0x1CBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_101,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_101,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_101,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_101,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_101,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_101,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_101,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_101,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x994++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_101," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_102" group.long 0x1CDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_102,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_102,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_102,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_102,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_102,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_102,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_102,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_102,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x998++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_102," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_103" group.long 0x1CFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_103,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_103,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_103,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_103,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1CEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_103,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1CE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_103,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_103,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_103,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x99C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_103," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_104" group.long 0x1D1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_104,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_104,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_104,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_104,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_104,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_104,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_104,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_104,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_104," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_105" group.long 0x1D3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_105,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_105,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_105,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_105,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_105,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_105,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_105,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_105,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_105," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_106" group.long 0x1D5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_106,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_106,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_106,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_106,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_106,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_106,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_106,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_106,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9A8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_106," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_107" group.long 0x1D7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_107,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_107,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_107,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_107,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_107,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_107,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_107,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_107,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9AC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_107," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_108" group.long 0x1D9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_108,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_108,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_108,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_108,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1D8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_108,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1D80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_108,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_108,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_108,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_108," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_109" group.long 0x1DBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_109,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_109,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_109,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_109,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_109,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_109,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_109,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_109,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_109," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_11" group.long 0x124++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_11,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_11," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x117C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_11,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1170++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_11,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_11,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_11,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x116C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_11,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1160++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_11,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_11,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_11,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x82C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_11," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_110" group.long 0x1DDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_110,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_110,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_110,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_110,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_110,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_110,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_110,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_110,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9B8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_110," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_111" group.long 0x1DFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_111,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_111,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_111,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_111,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1DEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_111,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1DE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_111,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_111,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_111,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9BC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_111," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_112" group.long 0x1E1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_112," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_113" group.long 0x1E3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_113,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_113,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_113,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_113,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_113,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_113,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_113,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_113,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_113," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_114" group.long 0x1E5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_114,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_114,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_114,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_114,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_114,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_114,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_114,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_114,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_114," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_115" group.long 0x1E7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_115,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_115,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_115,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_115,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_115,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_115,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_115,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_115,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9CC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_115," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_116" group.long 0x1E9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_116,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_116,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_116,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_116,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_116,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_116,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_116,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_116,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_116," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_117" group.long 0x1EBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_117,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_117,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_117,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_117,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_117,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_117,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_117,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_117,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_117," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_118" group.long 0x1EDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_118,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ED0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_118,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_118,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_118,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ECC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_118,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_118,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_118,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_118,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9D8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_118," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_119" group.long 0x1EFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_119,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_119,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_119,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_119,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1EEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_119,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1EE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_119,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_119,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_119,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9DC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_119," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_12" group.long 0x128++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_12,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_12," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x119C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_12,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1190++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_12,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_12,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_12,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x118C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_12,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1180++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_12,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_12,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_12,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x830++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_12," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_120" group.long 0x1F1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_120,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_120,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_120,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_120,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_120,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_120,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_120,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_120,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_120," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_121" group.long 0x1F3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_121,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_121,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_121,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_121,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_121,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_121,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_121,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_121,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_121," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_122" group.long 0x1F5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_122,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_122,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_122,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_122,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_122,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_122,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_122,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_122,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9E8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_122," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_123" group.long 0x1F7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_123,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_123,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_123,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_123,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_123,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_123,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_123,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_123,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9EC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_123," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_124" group.long 0x1F9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_124,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_124,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_124,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_124,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1F8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_124,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1F80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_124,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_124,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_124,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_124," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_125" group.long 0x1FBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_125,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_125,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_125,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_125,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_125,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_125,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_125,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_125,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_125," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_126" group.long 0x1FDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_126,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_126,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_126,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_126,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_126,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_126,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_126,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_126,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9F8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_126," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_127" group.long 0x1FFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_127,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_127,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_127,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_127,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1FEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_127,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1FE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_127,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_127,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_127,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9FC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_127," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_13" group.long 0x12C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_13,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xAC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_13," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_13,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_13,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_13,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_13,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_13,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_13,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_13,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_13,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x834++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_13," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_14" group.long 0x130++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_14,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_14," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_14,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_14,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_14,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_14,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_14,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_14,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_14,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_14,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x838++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_14," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_15" group.long 0x134++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_15,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_15," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x11FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_15,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_15,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_15,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_15,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x11EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_15,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x11E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_15,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_15,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_15,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x83C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_15," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_16" group.long 0x138++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_16,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xB8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_16," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x121C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_16,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1210++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_16,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_16,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_16,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x120C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_16,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1200++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_16,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_16,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_16,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x840++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_16," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_17" group.long 0x13C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_17,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xBC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_17," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x123C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_17,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1230++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_17,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_17,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_17,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x122C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_17,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1220++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_17,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_17,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_17,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x844++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_17," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_18" group.long 0x140++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_18,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_18," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x125C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_18,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1250++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_18,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_18,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_18,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x124C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_18,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1240++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_18,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_18,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_18,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x848++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_18," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_19" group.long 0x144++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_19,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_19," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x127C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_19,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1270++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_19,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_19,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_19,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x126C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_19,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1260++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_19,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_19,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_19,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x84C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_19," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_2" group.long 0x100++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_2,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x80++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_2," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x105C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_2,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1050++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_2,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_2,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_2,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x104C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_2,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1040++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_2,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_2,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_2,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x180++0x03 line.long 0x00 "VDMA_NON_DETERM_k_2,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x808++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_2," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_20" group.long 0x148++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_20,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_20," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x129C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1290++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x128C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1280++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x850++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_20," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_21" group.long 0x14C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_21,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xCC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_21," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_21,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_21,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_21,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_21,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_21,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_21,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_21,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_21,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x854++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_21," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_22" group.long 0x150++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_22,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_22," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_22,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_22,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_22,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_22,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_22,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_22,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_22,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_22,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x858++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_22," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_23" group.long 0x154++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_23,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_23," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_23,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_23,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_23,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_23,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x12EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_23,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x12E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_23,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_23,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_23,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x85C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_23," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_24" group.long 0x158++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_24,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xD8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_24," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x131C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_24,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1310++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_24,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_24,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_24,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x130C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_24,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1300++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_24,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_24,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_24,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x860++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_24," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_25" group.long 0x15C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_25,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xDC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_25," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x133C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_25,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1330++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_25,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_25,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_25,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x132C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_25,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1320++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_25,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_25,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_25,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x864++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_25," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_26" group.long 0x160++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_26,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_26," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x135C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_26,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1350++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_26,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_26,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_26,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x134C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_26,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1340++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_26,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_26,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_26,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x868++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_26," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_27" group.long 0x164++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_27,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_27," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x137C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_27,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1370++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_27,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_27,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_27,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x136C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_27,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1360++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_27,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_27,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_27,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x86C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_27," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_28" group.long 0x168++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_28,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xE8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_28," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x139C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_28,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1390++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_28,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_28,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_28,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x138C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_28,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1380++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_28,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_28,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_28,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x870++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_28," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_29" group.long 0x16C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_29,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xEC++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_29," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_29,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_29,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_29,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_29,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_29,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_29,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_29,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_29,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x874++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_29," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_3" group.long 0x104++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_3,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x84++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_3," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x107C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_3,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1070++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_3,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_3,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_3,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x106C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_3,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1060++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_3,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_3,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_3,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x184++0x03 line.long 0x00 "VDMA_NON_DETERM_k_3,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x80C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_3," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_30" group.long 0x170++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_30,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xF0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_30," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_30,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_30,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_30,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_30,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_30,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_30,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_30,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_30,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x878++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_30," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_31" group.long 0x174++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_31,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xF4++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_31," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_31,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_31,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_31,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_31,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x13EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_31,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x13E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_31,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_31,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_31,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x87C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_31," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_32" group.long 0x141C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1410++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x140C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1400++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x880++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_32," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_33" group.long 0x143C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_33,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1430++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_33,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_33,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_33,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x142C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_33,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1420++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_33,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_33,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_33,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x884++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_33," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_34" group.long 0x145C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_34,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1450++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_34,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_34,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_34,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x144C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_34,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1440++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_34,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_34,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_34,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x888++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_34," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_35" group.long 0x147C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_35,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1470++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_35,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_35,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_35,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x146C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_35,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1460++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_35,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_35,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_35,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x88C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_35," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_36" group.long 0x149C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_36,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1490++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_36,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_36,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_36,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x148C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_36,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1480++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_36,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_36,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_36,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x890++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_36," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_37" group.long 0x14BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_37,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_37,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_37,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_37,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_37,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_37,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_37,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_37,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x894++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_37," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_38" group.long 0x14DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_38,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_38,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_38,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_38,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_38,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_38,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_38,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_38,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x898++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_38," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_39" group.long 0x14FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_39,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_39,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_39,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_39,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x14EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_39,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x14E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_39,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_39,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_39,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x89C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_39," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_4" group.long 0x108++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_4,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x88++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_4," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x109C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_4,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1090++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_4,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_4,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_4,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x108C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_4,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1080++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_4,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_4,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_4,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x810++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_4," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_40" group.long 0x151C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_40,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1510++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_40,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_40,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_40,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x150C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_40,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1500++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_40,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_40,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_40,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_40," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_41" group.long 0x153C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_41,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1530++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_41,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_41,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_41,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x152C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_41,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1520++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_41,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_41,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_41,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_41," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_42" group.long 0x155C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_42,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1550++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_42,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_42,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_42,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x154C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_42,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1540++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_42,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_42,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_42,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8A8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_42," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_43" group.long 0x157C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_43,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1570++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_43,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_43,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_43,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x156C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_43,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1560++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_43,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_43,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_43,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8AC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_43," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_44" group.long 0x159C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_44,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1590++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_44,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_44,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_44,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x158C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_44,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1580++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_44,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_44,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_44,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_44," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_45" group.long 0x15BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_45,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_45,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_45,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_45,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_45,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_45,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_45,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_45,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_45," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_46" group.long 0x15DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_46,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_46,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_46,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_46,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_46,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_46,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_46,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_46,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8B8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_46," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_47" group.long 0x15FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_47,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_47,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_47,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_47,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x15EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_47,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x15E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_47,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_47,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_47,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8BC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_47," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_48" group.long 0x161C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1610++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x160C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1600++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_48," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_49" group.long 0x163C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_49,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1630++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_49,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_49,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_49,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x162C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_49,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1620++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_49,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_49,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_49,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_49," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_5" group.long 0x10C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_5,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x8C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_5," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_5,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_5,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_5,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_5,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_5,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_5,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_5,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_5,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x814++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_5," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_50" group.long 0x165C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_50,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1650++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_50,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_50,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_50,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x164C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_50,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1640++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_50,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_50,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_50,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_50," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_51" group.long 0x167C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_51,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1670++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_51,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_51,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_51,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x166C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_51,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1660++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_51,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_51,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_51,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8CC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_51," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_52" group.long 0x169C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_52,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1690++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_52,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_52,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_52,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x168C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_52,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1680++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_52,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_52,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_52,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_52," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_53" group.long 0x16BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_53,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_53,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_53,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_53,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_53,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_53,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_53,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_53,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_53," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_54" group.long 0x16DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_54,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_54,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_54,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_54,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_54,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_54,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_54,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_54,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8D8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_54," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_55" group.long 0x16FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_55,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_55,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_55,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_55,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x16EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_55,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x16E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_55,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_55,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_55,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8DC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_55," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_56" group.long 0x171C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_56,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1710++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_56,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_56,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_56,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x170C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_56,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1700++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_56,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_56,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_56,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_56," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_57" group.long 0x173C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_57,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1730++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_57,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_57,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_57,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x172C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_57,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1720++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_57,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_57,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_57,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_57," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_58" group.long 0x175C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_58,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1750++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_58,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_58,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_58,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x174C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_58,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1740++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_58,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_58,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_58,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8E8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_58," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_59" group.long 0x177C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_59,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1770++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_59,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_59,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_59,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x176C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_59,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1760++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_59,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_59,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_59,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8EC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_59," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_6" group.long 0x110++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_6,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x90++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_6," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_6,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_6,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_6,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_6,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_6,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_6,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_6,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_6,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x818++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_6," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_60" group.long 0x179C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_60,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1790++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_60,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_60,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_60,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x178C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_60,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1780++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_60,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_60,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_60,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_60," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_61" group.long 0x17BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_61,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_61,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_61,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_61,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_61,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_61,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_61,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_61,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F4++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_61," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_62" group.long 0x17DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_62,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_62,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_62,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_62,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_62,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_62,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_62,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_62,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8F8++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_62," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_63" group.long 0x17FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_63,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_63,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_63,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_63,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x17EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_63,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x17E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_63,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_63,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_63,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8FC++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_63," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_64" group.long 0x181C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1810++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x180C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1800++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x900++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_64," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_65" group.long 0x183C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_65,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1830++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_65,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_65,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_65,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x182C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_65,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1820++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_65,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_65,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_65,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x904++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_65," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_66" group.long 0x185C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_66,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1850++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_66,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_66,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_66,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x184C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_66,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1840++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_66,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_66,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_66,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x908++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_66," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_67" group.long 0x187C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_67,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1870++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_67,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_67,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_67,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x186C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_67,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1860++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_67,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_67,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_67,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x90C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_67," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_68" group.long 0x189C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_68,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1890++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_68,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_68,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_68,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x188C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_68,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1880++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_68,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_68,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_68,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x910++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_68," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_69" group.long 0x18BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_69,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_69,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_69,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_69,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_69,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_69,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_69,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_69,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x914++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_69," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_7" group.long 0x114++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_7,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x94++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_7," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_7,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_7,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_7,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_7,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x10EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_7,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x10E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_7,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_7,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_7,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x81C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_7," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_70" group.long 0x18DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_70,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_70,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_70,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_70,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_70,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_70,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_70,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_70,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x918++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_70," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_71" group.long 0x18FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_71,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_71,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_71,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_71,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x18EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_71,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x18E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_71,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_71,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_71,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x91C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_71," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_72" group.long 0x191C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_72,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1910++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_72,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_72,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_72,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x190C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_72,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1900++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_72,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_72,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_72,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x920++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_72," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_73" group.long 0x193C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_73,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1930++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_73,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_73,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_73,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x192C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_73,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1920++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_73,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_73,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_73,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x924++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_73," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_74" group.long 0x195C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_74,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1950++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_74,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_74,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_74,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x194C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_74,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1940++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_74,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_74,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_74,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x928++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_74," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_75" group.long 0x197C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_75,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1970++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_75,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_75,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_75,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x196C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_75,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1960++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_75,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_75,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_75,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x92C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_75," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_76" group.long 0x199C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_76,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1990++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_76,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_76,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_76,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x198C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_76,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1980++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_76,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_76,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_76,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x930++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_76," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_77" group.long 0x19BC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_77,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19B0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_77,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_77,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_77,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19AC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_77,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19A0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_77,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_77,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_77,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x934++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_77," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_78" group.long 0x19DC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_78,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19D0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_78,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_78,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_78,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19CC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_78,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19C0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_78,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_78,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_78,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x938++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_78," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_79" group.long 0x19FC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_79,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19F0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_79,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_79,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_79,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x19EC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_79,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x19E0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_79,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_79,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_79,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x93C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_79," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_8" group.long 0x118++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_8,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x98++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_8," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x111C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_8,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1110++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_8,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_8,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_8,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x110C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_8,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1100++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_8,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_8,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_8,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x820++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_8," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_80" group.long 0x1A1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x940++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_80," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_81" group.long 0x1A3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_81,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_81,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_81,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_81,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_81,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_81,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_81,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_81,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x944++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_81," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_82" group.long 0x1A5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_82,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_82,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_82,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_82,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_82,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_82,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_82,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_82,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x948++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_82," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_83" group.long 0x1A7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_83,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_83,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_83,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_83,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_83,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_83,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_83,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_83,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x94C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_83," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_84" group.long 0x1A9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_84,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_84,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_84,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_84,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_84,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_84,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_84,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_84,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x950++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_84," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_85" group.long 0x1ABC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_85,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_85,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_85,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_85,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_85,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_85,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_85,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_85,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x954++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_85," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_86" group.long 0x1ADC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_86,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_86,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_86,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_86,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1ACC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_86,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_86,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_86,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_86,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x958++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_86," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_87" group.long 0x1AFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_87,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_87,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_87,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_87,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1AEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_87,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1AE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_87,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_87,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_87,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x95C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_87," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_88" group.long 0x1B1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_88,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_88,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_88,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_88,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_88,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_88,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_88,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_88,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x960++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_88," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_89" group.long 0x1B3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_89,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_89,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_89,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_89,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_89,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_89,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_89,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_89,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x964++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_89," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_9" group.long 0x11C++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_9,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x9C++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_9," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x113C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_9,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1130++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_9,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_9,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_9,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x112C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_9,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1120++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_9,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_9,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_9,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x824++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_9," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_90" group.long 0x1B5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_90,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_90,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_90,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_90,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_90,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_90,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_90,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_90,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x968++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_90," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_91" group.long 0x1B7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_91,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_91,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_91,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_91,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_91,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_91,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_91,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_91,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x96C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_91," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_92" group.long 0x1B9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_92,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_92,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_92,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_92,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1B8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_92,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1B80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_92,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_92,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_92,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x970++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_92," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_93" group.long 0x1BBC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_93,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BB0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_93,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_93,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_93,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BAC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_93,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BA0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_93,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_93,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_93,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x974++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_93," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_94" group.long 0x1BDC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_94,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BD0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_94,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_94,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_94,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BCC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_94,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BC0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_94,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_94,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_94,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x978++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_94," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_95" group.long 0x1BFC++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_95,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BF0++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_95,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_95,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_95,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1BEC++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_95,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1BE0++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_95,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_95,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_95,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x97C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_95," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_96" group.long 0x1C1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_96,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_96,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_96,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_96,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_96,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_96,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_96,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_96,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x980++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_96," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_97" group.long 0x1C3C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_97,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C30++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_97,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_97,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_97,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C2C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_97,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C20++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_97,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_97,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_97,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x984++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_97," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_98" group.long 0x1C5C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_98,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C50++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_98,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_98,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_98,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C4C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_98,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C40++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_98,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_98,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_98,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x988++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_98," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end tree "DMA_Channel_99" group.long 0x1C7C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_99,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C70++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_99,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_99,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_99,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C6C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_99,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C60++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_99,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_99,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_99,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x98C++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_99," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end rgroup.long 0x58++0x03 line.long 0x00 "VDMA_ASYNCHR_LIST_LEVEL," bitfld.long 0x00 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of asynchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" rgroup.long 0x64++0x07 line.long 0x00 "VDMA_CONTEXT_STATUS,When individual bit is reset. corresponding context is available" bitfld.long 0x00 15. "CONTEXT15," "CONTEXT15_0,CONTEXT15_1" bitfld.long 0x00 14. "CONTEXT14," "CONTEXT14_0,CONTEXT14_1" newline bitfld.long 0x00 13. "CONTEXT13," "CONTEXT13_0,CONTEXT13_1" bitfld.long 0x00 12. "CONTEXT12," "CONTEXT12_0,CONTEXT12_1" newline bitfld.long 0x00 11. "CONTEXT11," "CONTEXT11_0,CONTEXT11_1" bitfld.long 0x00 10. "CONTEXT10," "CONTEXT10_0,CONTEXT10_1" newline bitfld.long 0x00 9. "CONTEXT9," "CONTEXT9_0,CONTEXT9_1" bitfld.long 0x00 8. "CONTEXT8," "CONTEXT8_0,CONTEXT8_1" newline bitfld.long 0x00 7. "CONTEXT7," "CONTEXT7_0,CONTEXT7_1" bitfld.long 0x00 6. "CONTEXT6," "CONTEXT6_0,CONTEXT6_1" newline bitfld.long 0x00 5. "CONTEXT5," "CONTEXT5_0,CONTEXT5_1" bitfld.long 0x00 4. "CONTEXT4," "CONTEXT4_0,CONTEXT4_1" newline bitfld.long 0x00 3. "CONTEXT3," "CONTEXT3_0,CONTEXT3_1" bitfld.long 0x00 2. "CONTEXT2," "CONTEXT2_0,CONTEXT2_1" newline bitfld.long 0x00 1. "CONTEXT1," "CONTEXT1_0,CONTEXT1_1" bitfld.long 0x00 0. "CONTEXT0," "CONTEXT0_0,CONTEXT0_1" line.long 0x04 "VDMA_GROUP_TRIGGER,Register entry for software user to trigger deterministic (only) groups through CPU writes" group.long 0x20++0x03 line.long 0x00 "VDMA_IRQ_EOI,End Of Interrupt number specification" abitfld.long 0x00 0.--7. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0x00=EOI for interrupt..,0x01=EOI for interrupt..,0x02=EOI for interrupt..,0x03=N/A,0x04=N/A,0x05=N/A,0x06=N/A,0x07=N/A" group.long 0x74++0x03 line.long 0x00 "VDMA_IRQ_NEOG,Sets whether end of group signaling should be set through external hardware lines (like the deterministic group triggers) or wrap into interrupt line" group.long 0x30++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" group.long 0x40++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" group.long 0x50++0x03 line.long 0x00 "VDMA_IRQENABLE_CLR_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x2C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" group.long 0x3C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" group.long 0x4C++0x03 line.long 0x00 "VDMA_IRQENABLE_SET_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x28++0x03 line.long 0x00 "VDMA_IRQSTATUS_0,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #0" group.long 0x38++0x03 line.long 0x00 "VDMA_IRQSTATUS_1,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #1" group.long 0x48++0x03 line.long 0x00 "VDMA_IRQSTATUS_2,Per-error event 'enabled' interrupt status vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x24++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_0,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #0" group.long 0x34++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_1,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #1" group.long 0x44++0x03 line.long 0x00 "VDMA_IRQSTATUS_RAW_2,Per-error event raw interrupt status vector. line #2" bitfld.long 0x00 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x00 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x00 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x00 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" group.long 0x70++0x03 line.long 0x00 "VDMA_MAX_CONTEXT_ASYNCHR,Software user configurable maximum number of context asynchronous list can get benefit of" bitfld.long 0x00 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to asynchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" group.long 0x6C++0x03 line.long 0x00 "VDMA_MAX_CONTEXT_SYNCHR,Software user configurable maximum number of context synchronous list can get benefit of" bitfld.long 0x00 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to synchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" rgroup.long 0x5C++0x03 line.long 0x00 "VDMA_NON_DETERM_FIFO_LEVEL," hexmask.long.byte 0x00 0.--7. 1. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for read address generator to pick them from list) entries of nondeterministic object descriptor FIFO" rgroup.long 0x00++0x03 line.long 0x00 "VDMA_REVISION,IP revision identifier" rgroup.long 0x54++0x03 line.long 0x00 "VDMA_SYNCHR_LIST_LEVEL," bitfld.long 0x00 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of synchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" group.long 0x10++0x03 line.long 0x00 "VDMA_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "No action Write,Software reset ongoing" group.long 0x60++0x03 line.long 0x00 "VDMA_TBA,TILER address mapping" bitfld.long 0x00 0.--2. "OCP_3MSB," "OCP_3MSB_0,OCP_3MSB_1,OCP_3MSB_2,OCP_3MSB_3,OCP_3MSB_4,OCP_3MSB_5,OCP_3MSB_6,OCP_3MSB_7" width 0x0B tree.end tree.end tree "Keyboard_Controller" base ad:0x4AE1C000 rgroup.long 0x00++0x03 line.long 0x00 "KBD_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "KBD_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 5. "EMUFREE,Emulation mode - module_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 3.--4. "IDLEMODE,Power Management req/ack control - force_idle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x1C++0x53 line.long 0x00 "KBD_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "KBD_IRQSTATUS_RAW,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x04 3. "MISS_EVENT,IRQ status for Miss event" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 2. "IT_TIMEOUT,IRQ status for Timeout" "No action Read,Trigger IRQ event by software" newline bitfld.long 0x04 1. "IT_LONG_KEY,IRQ status for Long key" "No action Read,Trigger IRQ event by software" bitfld.long 0x04 0. "IT_EVENT,IRQ status for Event" "No action Read,Trigger IRQ event by software" line.long 0x08 "KBD_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x08 3. "MISS_EVENT,IRQ status for Miss event Read always returns zero" "No action Write,Clear pending event if any" bitfld.long 0x08 2. "IT_TIMEOUT,IRQ status for Timeout" "No action Read,Clear pending event if any" newline bitfld.long 0x08 1. "IT_LONG_KEY,IRQ status for Long key" "No action Read,Clear pending event if any" bitfld.long 0x08 0. "IT_EVENT,IRQ status for Event" "No action Read,Clear pending event if any" line.long 0x0C "KBD_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x0C 2. "IT_TIMEOUT_EN,IRQ enable for Timeout" "No action Read,Set IRQ enable" bitfld.long 0x0C 1. "IT_LONG_KEY_EN,IRQ enable for Long key" "No action Read,Set IRQ enable" newline bitfld.long 0x0C 0. "IT_EVENT_EN,IRQ enable for Event" "No action Read,Set IRQ enable" line.long 0x10 "KBD_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x10 2. "IT_TIMEOUT_EN,IRQ enable for Timeout" "No action Read,Clear IRQ enable" bitfld.long 0x10 1. "IT_LONG_KEY_EN,IRQ enable for Long key" "No action Read,Clear IRQ enable" newline bitfld.long 0x10 0. "IT_EVENT_EN,IRQ enable for Event" "No action Read,Clear IRQ enable" line.long 0x14 "KBD_IRQWAKEEN,The Keyboard Wake-up Enable Register allows the user to mask the expected source of wake-up event that will generate a wake-up request" bitfld.long 0x14 2. "WUP_TIMEOUT_ENA,Timeout wakeup enable" "WUP_TIMEOUT_ENA_0,WUP_TIMEOUT_ENA_1" bitfld.long 0x14 1. "WUP_LONG_KEY_ENA,Long key wakeup enable" "WUP_LONG_KEY_ENA_0,WUP_LONG_KEY_ENA_1" newline bitfld.long 0x14 0. "WUP_EVENT_ENA,Event wakeup enable" "WUP_EVENT_ENA_0,WUP_EVENT_ENA_1" line.long 0x18 "KBD_PENDING,The software must read the pending write bits to insure that following write access will not be discarded due to on going write synchronization process" bitfld.long 0x18 3. "PEND_TIMEOUT,Write pending bit forKBD_TIMEOUT register - PEND_TIMEOUT_1" "PEND_TIMEOUT_0_r,PEND_TIMEOUT_1_r" bitfld.long 0x18 2. "PEND_LONG_KEY,Write pending bit forKBD_KEYLONGTIME register - PEND_LONGKEY_1" "PEND_LONG_KEY_0_r,PEND_LONG_KEY_1_r" newline bitfld.long 0x18 1. "PEND_DEBOUNCING,Write pending bit forKBD_DEBOUNCINGTIME register - PEND_DEBOUNCING_1" "PEND_DEBOUNCING_0_r,PEND_DEBOUNCING_1_r" bitfld.long 0x18 0. "PEND_CTRL,Write pending bit forKBD_CTRL register - PEND_CTRL_1" "PEND_CTRL_0_r,PEND_CTRL_1_r" line.long 0x1C "KBD_CTRL,This register sets the functional configuration of the module" bitfld.long 0x1C 8. "REPEAT_MODE,Repeat mode enable" "REPEAT_MODE_0,REPEAT_MODE_1" bitfld.long 0x1C 7. "TIMEOUT_LONG_KEY,Timeout long key mode enable" "TIMEOUT_LONG_KEY_0,TIMEOUT_LONG_KEY_1" newline bitfld.long 0x1C 6. "TIMEOUT_EMPTY,Timeout empty mode enable" "TIMEOUT_EMPTY_0,TIMEOUT_EMPTY_1" bitfld.long 0x1C 5. "LONG_KEY,Long key mode enable" "LONG_KEY_0,LONG_KEY_1" newline bitfld.long 0x1C 2.--4. "PTV,Pre-scale clock timer value" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x1C 1. "NSOFTWARE_MODE,Select hardware or software mode for key decoding" "NSOFTWARE_MODE_0,NSOFTWARE_MODE_1" line.long 0x20 "KBD_DEBOUNCINGTIME,This register is used to filter glitches on the press key or release key" bitfld.long 0x20 0.--5. "DEBOUNCING_VALUE,This value correspond to the desired value of debouncing time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "KBD_KEYLONGTIME,This register is used to measure duration of a key press. to allow. shortcut detection" hexmask.long.word 0x24 0.--11. 1. "LONG_KEY_VALUE,This value correspond to the desired value of the long key interrupt or repeat mode value" line.long 0x28 "KBD_TIMEOUT,This register is used to detect a long inactivity on the keyboard" hexmask.long.word 0x28 0.--15. 1. "TIMEOUT_VALUE,This value correspond to the desired value of the time out interrupt" line.long 0x2C "KBD_STATEMACHINE,This register indicates the state of the sequencer" bitfld.long 0x2C 0.--3. "STATE_MACHINE,The state of internal state machine" "STATE_MACHINE_0,STATE_MACHINE_1,STATE_MACHINE_2,STATE_MACHINE_3,STATE_MACHINE_4,STATE_MACHINE_5,STATE_MACHINE_6,STATE_MACHINE_7,STATE_MACHINE_8,STATE_MACHINE_9,STATE_MACHINE_10,STATE_MACHINE_11,STATE_MACHINE_12,STATE_MACHINE_13,STATE_MACHINE_14,STATE_MACHINE_15" line.long 0x30 "KBD_ROWINPUTS,This register stores the value of the rows input" hexmask.long.word 0x30 0.--8. 1. "KBR_LATCH,The value of the rows input" line.long 0x34 "KBD_COLUMNOUTPUTS,This register holds the value of the columns output" hexmask.long.word 0x34 0.--8. 1. "KBC_REG,The value of the columns output" line.long 0x38 "KBD_FULLCODE31_0,The register codes the row 0. row 1. row 2 and row 3" line.long 0x3C "KBD_FULLCODE63_32,The register codes the row 4. row 5. row 6 and row 7" line.long 0x40 "KBD_FULLCODE17_0,The register codes the row 0 and row 1" hexmask.long.word 0x40 16.--24. 1. "ROW1,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x40 0.--8. 1. "ROW0,A bit at one indicate that the corresponding key is pressed" line.long 0x44 "KBD_FULLCODE35_18,The register codes the row 2 and row 3" hexmask.long.word 0x44 16.--24. 1. "ROW3,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x44 0.--8. 1. "ROW2,A bit at one indicate that the corresponding key is pressed" line.long 0x48 "KBD_FULLCODE53_36,The register codes the row 4 and row 5" hexmask.long.word 0x48 16.--24. 1. "ROW5,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x48 0.--8. 1. "ROW4,A bit at one indicate that the corresponding key is pressed" line.long 0x4C "KBD_FULLCODE71_54,The register codes the row 6 and row 7" hexmask.long.word 0x4C 16.--24. 1. "ROW7,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x4C 0.--8. 1. "ROW6,A bit at one indicate that the corresponding key is pressed" line.long 0x50 "KBD_FULLCODE80_72,The register codes the row 8" hexmask.long.word 0x50 0.--8. 1. "ROW8,A bit at one indicate that the corresponding key is pressed" width 0x0B tree.end tree "L3_Interconnect" tree "CLK1_2_BB2D_P1_BW_LIMITER" base ad:0x44805900 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_BB2D_P2_BW_LIMITER" base ad:0x44805A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_GPU_P1_BW_LIMITER" base ad:0x44805B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_GPU_P2_BW_LIMITER" base ad:0x44805C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_MMU1_BW_LIMITER" base ad:0x44803A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_TPTC1_RD_BW_LIMITER" base ad:0x44803C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_TPTC1_WR_BW_LIMITER" base ad:0x44803E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_TPTC2_RD_BW_LIMITER" base ad:0x44803D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_TPTC2_WR_BW_LIMITER" base ad:0x44803F00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_VPE_P1_BW_LIMITER" base ad:0x44804100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_VPE_P2_BW_LIMITER" base ad:0x44804000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_BB2D_P1_BW_REGULATOR" base ad:0x44804E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_BB2D_P2_BW_REGULATOR" base ad:0x44805100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_DSP1_EDMA_BW_REGULATOR" base ad:0x44804B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_DSP1_MDMA_BW_REGULATOR" base ad:0x44804C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_DSP2_EDMA_BW_REGULATOR" base ad:0x44804A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_DSP2_MDMA_BW_REGULATOR" base ad:0x44804D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_EVE1_TC0_BW_REGULATOR" base ad:0x44804200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_EVE1_TC1_BW_REGULATOR" base ad:0x44804600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_EVE2_TC0_BW_REGULATOR" base ad:0x44804300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_EVE2_TC1_BW_REGULATOR" base ad:0x44804700 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_GMAC_SW_BW_REGULATOR" base ad:0x44805600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_GPU_P1_BW_REGULATOR" base ad:0x44805200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_GPU_P2_BW_REGULATOR" base ad:0x44805300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_ISS_NRT1_BW_REGULATOR" base ad:0x44804900 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_ISS_NRT2_BW_REGULATOR" base ad:0x44804800 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_ISS_RT_BW_REGULATOR" base ad:0x44804500 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_IVA_BW_REGULATOR" base ad:0x44805000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_MMU2_BW_REGULATOR" base ad:0x44803B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_PCIESS1_BW_REGULATOR" base ad:0x44805500 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_2_PCIESS2_BW_REGULATOR" base ad:0x44805400 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 2.--3. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1,2,3" bitfld.long 0x10 0.--1. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1,2,3" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1" base ad:0x44000000 rgroup.long 0x805700++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT1_MASK0," hexmask.long 0x08 0.--29. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT1_REGERR0," hexmask.long 0x0C 0.--24. 1. "REGERR0,flag inputs 0 Type: Status" rgroup.long 0x805800++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT2_MASK0," hexmask.long.tbyte 0x08 0.--20. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT2_REGERR0," hexmask.long.tbyte 0x0C 0.--20. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_1" base ad:0x44803500 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_2" base ad:0x44803600 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2_1" base ad:0x45000200 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," line.long 0x14 "L3_FLAGMUX_REGERR1," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1MERGE" base ad:0x44000000 rgroup.long 0x800400++0x17 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_CLK1MERGE_MASK0," bitfld.long 0x08 0.--1. "MASK0,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_CLK1MERGE_REGERR0," bitfld.long 0x0C 0.--1. "REGERR0,Flag inputs 0 Type: Control" "0,1,2,3" line.long 0x10 "L3_FLAGMUX_CLK1MERGE_MASK1," bitfld.long 0x10 0.--1. "MASK1,Mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x14 "L3_FLAGMUX_CLK1MERGE_REGERR1," bitfld.long 0x14 0.--1. "REGERR1,Flag inputs 0 Type: Control" "0,1,2,3" width 0x0B tree.end tree "CLK1_HOST_CLK1_1" base ad:0x44000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_2" base ad:0x44800000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK2_HOST_CLK2_1" base ad:0x45000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x45000000 rgroup.long 0x400++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT_MASK0," bitfld.long 0x08 0.--1. "MASK0,mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_TIMEOUT_REGERR0," bitfld.long 0x0C 0.--1. "REGERR0,flag inputs 0 Type: Status" "0,1,2,3" width 0x0B tree.end tree "CLK2_FLAGMUX_STATCOLL" base ad:0x45000500 group.long 0x00++0x0F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_MASK0," hexmask.long.word 0x08 0.--9. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_STCOL_REGERR0," hexmask.long.word 0x0C 0.--9. 1. "REGERR0,flag inputs 0 Type: Status" width 0x0B tree.end tree "CLK2_STATCOLL0" base ad:0x45001000 tree "Channel_0" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_0," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_0," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_1," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x22C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_1," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x24C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_1," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x350++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_1," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_2" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_2," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x384++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_2," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x3A4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_2," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4A8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_2," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_3" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_3," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4DC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_3," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4FC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_3," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x600++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_3," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_4" group.long 0x618++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_4," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x614++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x610++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x61C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_4," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x60C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_4," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x630++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x628++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x620++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x634++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_4," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x624++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x650++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x648++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x640++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x654++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_4," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x644++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x758++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_4," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_4," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x754++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x750++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_5" group.long 0x770++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_5," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x76C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x768++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x774++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_5," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x764++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_5," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x788++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x780++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x778++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x78C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_5," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x77C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x7A8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x7A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x798++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x7AC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_5," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x79C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x8B0++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_5," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_5," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x8AC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x8A8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_6" group.long 0x8C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_6," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x8C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_6," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x8C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_6," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x8CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_6," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x8BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_6," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x8E0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x8D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_6," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x8D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x8E4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_6," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x8D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x900++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x8F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x8F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x904++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_6," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0x8F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xA08++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_6," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_6," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0xA04++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_6," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0xA00++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_6," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_7" group.long 0xA20++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_7," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xA1C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_7," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xA18++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_7," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xA24++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_7," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xA14++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_7," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xA38++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xA30++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_7," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xA28++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xA3C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_7," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xA2C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xA58++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xA50++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xA48++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xA5C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_7," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xA4C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xB60++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_7," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_7," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0xB5C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_7," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0xB58++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_7," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end group.long 0x68++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MAXVAL," group.long 0x64++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MINVAL," group.long 0x6C++0x1F line.long 0x00 "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x00 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x04 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x04 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x08 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x08 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x0C "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x0C 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x10 "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x10 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x14 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x14 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" line.long 0x18 "L3_STCOL_DUMP_ALARM_MODE6," bitfld.long 0x18 0.--1. "DUMP_ALARM_MODE6,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE6_0,DUMP_ALARM_MODE6_1,DUMP_ALARM_MODE6_2,DUMP_ALARM_MODE6_3" line.long 0x1C "L3_STCOL_DUMP_ALARM_MODE7," bitfld.long 0x1C 0.--1. "DUMP_ALARM_MODE7,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE7_0,DUMP_ALARM_MODE7_1,DUMP_ALARM_MODE7_2,DUMP_ALARM_MODE7_3" group.long 0x60++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x00 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end group.long 0x44++0x03 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," group.long 0x5C++0x03 line.long 0x00 "L3_STCOL_DUMP_DISABLE," bitfld.long 0x00 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" rgroup.long 0x40++0x03 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "L3_STCOL_DUMP_MODE," bitfld.long 0x00 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x00 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" rgroup.long 0x4C++0x03 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" group.long 0x58++0x03 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x00 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" group.long 0x50++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," group.long 0x08++0x03 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" group.long 0x20++0x1F line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x04 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x04 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x08 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x08 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x0C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x0C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x10 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x10 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x14 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x14 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x18 "L3_STCOL_EVTMUX_SEL6," bitfld.long 0x18 0.--2. "EVTMUX_SEL6,The select of the mux 6 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x1C "L3_STCOL_EVTMUX_SEL7," bitfld.long 0x1C 0.--2. "EVTMUX_SEL7,The select of the mux 7 Type: Control" "0,1,2,3,4,5,6,7" group.long 0x10++0x03 line.long 0x00 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x00 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" group.long 0x18++0x07 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x04 "L3_STCOL_RSPEVT," bitfld.long 0x04 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" group.long 0x0C++0x03 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" group.long 0x00++0x07 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" group.long 0x14++0x03 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" width 0x0B tree.end tree "CLK2_STATCOLL1" base ad:0x45002000 tree "Channel_0" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_1," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x22C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x224++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x24C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x244++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x350++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_1," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_2" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_2," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x384++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x3A4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x39C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4A8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_2," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_3" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_3," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4DC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4FC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x600++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_3," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_4" group.long 0x618++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_4," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x614++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x610++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x61C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_4," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x60C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_4," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x630++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x628++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x620++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x634++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x62C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_4," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x624++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x650++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x648++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x640++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x654++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x64C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x644++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x758++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_4," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_4," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x754++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x750++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_5" group.long 0x770++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_5," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x76C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x768++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x774++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_5," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x764++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_5," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x788++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x780++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x778++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x78C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x784++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_5," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x77C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x7A8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x7A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x798++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x7AC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x7A4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x79C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x8B0++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_5," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_5," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x8AC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x8A8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end group.long 0x68++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MAXVAL," group.long 0x64++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MINVAL," group.long 0x6C++0x17 line.long 0x00 "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x00 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x04 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x04 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x08 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x08 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x0C "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x0C 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x10 "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x10 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x14 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x14 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" group.long 0x60++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x00 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end group.long 0x44++0x03 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," group.long 0x5C++0x03 line.long 0x00 "L3_STCOL_DUMP_DISABLE," bitfld.long 0x00 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" rgroup.long 0x40++0x03 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "L3_STCOL_DUMP_MODE," bitfld.long 0x00 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x00 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" rgroup.long 0x4C++0x03 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" group.long 0x58++0x03 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x00 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" group.long 0x50++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," group.long 0x08++0x03 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" group.long 0x20++0x17 line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x04 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x04 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x08 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x08 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x0C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x0C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x10 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x10 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x14 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x14 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" group.long 0x10++0x03 line.long 0x00 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x00 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" group.long 0x18++0x07 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x04 "L3_STCOL_RSPEVT," bitfld.long 0x04 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" group.long 0x0C++0x03 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" group.long 0x00++0x07 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" group.long 0x14++0x03 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" width 0x0B tree.end repeat 7. (list 2. 4. 6. 7. 8. 9. 5. )(list ad:0x45003000 ad:0x45005000 ad:0x45007000 ad:0x45008000 ad:0x45009000 ad:0x4500A000 ad:0x45006000 ) tree "CLK2_STATCOLL$1" base $2 tree "Channel_0" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_1," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x22C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x224++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x24C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x244++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x350++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_1," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_2" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_2," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x384++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x3A4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x39C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4A8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_2," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_3" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_3," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4DC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4FC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x600++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_3," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end group.long 0x68++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MAXVAL," group.long 0x64++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MINVAL," group.long 0x6C++0x0F line.long 0x00 "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x00 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x04 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x04 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x08 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x08 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x0C "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x0C 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" group.long 0x60++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x00 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end group.long 0x44++0x03 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," group.long 0x5C++0x03 line.long 0x00 "L3_STCOL_DUMP_DISABLE," bitfld.long 0x00 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" rgroup.long 0x40++0x03 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "L3_STCOL_DUMP_MODE," bitfld.long 0x00 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x00 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" rgroup.long 0x4C++0x03 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" group.long 0x58++0x03 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x00 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" group.long 0x50++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," group.long 0x08++0x03 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" group.long 0x20++0x0F line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x04 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x04 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x08 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x08 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x0C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x0C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" group.long 0x10++0x03 line.long 0x00 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x00 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" group.long 0x18++0x07 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x04 "L3_STCOL_RSPEVT," bitfld.long 0x04 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" group.long 0x0C++0x03 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" group.long 0x00++0x07 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" group.long 0x14++0x03 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" width 0x0B tree.end repeat.end tree "CLK2_STATCOLL3" base ad:0x45004000 tree "Channel_0" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_1" group.long 0x210++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_1," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x20C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x208++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_1," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x214++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_1," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x204++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_1," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x228++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x220++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x218++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x22C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x224++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x21C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x248++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x240++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x238++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x24C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x244++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x23C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_1," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x350++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_1," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_1," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x34C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x348++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_2" group.long 0x368++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_2," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x364++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x360++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_2," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x36C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_2," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x35C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_2," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x380++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x378++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x370++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x384++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x37C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x374++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x3A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x398++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x390++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x3A4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x39C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x394++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_2," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4A8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_2," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_2," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x4A4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x4A0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_3" group.long 0x4C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_3," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x4BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x4B8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_3," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x4C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_3," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x4B4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_3," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x4D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4DC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x4CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x4F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x4F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x4E8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x4FC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x4F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4EC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_3," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x600++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_3," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_3," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x5FC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x5F8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_4" group.long 0x618++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_4," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x614++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x610++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_4," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x61C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_4," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x60C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_4," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x630++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x628++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x620++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x634++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x62C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_4," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x624++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x650++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x648++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x640++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x654++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x64C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x644++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_4," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x758++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_4," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_4," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x754++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x750++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_5" group.long 0x770++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_5," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x76C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x768++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_5," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x774++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_5," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x764++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_5," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x788++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x780++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x778++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x78C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x784++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_5," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x77C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x7A8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x7A0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x798++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x7AC++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x7A4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x79C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_5," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x8B0++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_5," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_5," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x8AC++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x8A8++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_6" group.long 0x8C8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_6," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0x8C4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_6," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0x8C0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_6," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0x8CC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_6," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0x8BC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_6," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0x8E0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x8D8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_6," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x8D0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x8E4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_6," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_6," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x8DC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_6," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0x8D4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_6," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x900++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0x8F8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0x8F0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x904++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_6," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_6," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0x8FC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_6," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_6," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xA08++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_6," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_6," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0xA04++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_6," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0xA00++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_6," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end tree "Channel_7" group.long 0xA20++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_7," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xA1C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_7," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xA18++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_7," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xA24++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_7," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xA14++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_7," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xA38++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xA30++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_7," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xA28++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xA3C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_7," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_7," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xA34++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_7," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xA2C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_7," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xA58++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xA50++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xA48++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xA5C++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_7," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_7," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xA54++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_7," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA4C++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_7," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xB60++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_7," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_7," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0xB5C++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_7," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0xB58++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_7," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end group.long 0x68++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MAXVAL," group.long 0x64++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_MINVAL," group.long 0x6C++0x1F line.long 0x00 "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x00 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x04 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x04 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x08 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x08 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x0C "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x0C 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x10 "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x10 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x14 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x14 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" line.long 0x18 "L3_STCOL_DUMP_ALARM_MODE6," bitfld.long 0x18 0.--1. "DUMP_ALARM_MODE6,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE6_0,DUMP_ALARM_MODE6_1,DUMP_ALARM_MODE6_2,DUMP_ALARM_MODE6_3" line.long 0x1C "L3_STCOL_DUMP_ALARM_MODE7," bitfld.long 0x1C 0.--1. "DUMP_ALARM_MODE7,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE7_0,DUMP_ALARM_MODE7_1,DUMP_ALARM_MODE7_2,DUMP_ALARM_MODE7_3" group.long 0x60++0x03 line.long 0x00 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x00 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end group.long 0x44++0x03 line.long 0x00 "L3_STCOL_DUMP_COLLECTTIME," group.long 0x5C++0x03 line.long 0x00 "L3_STCOL_DUMP_DISABLE," bitfld.long 0x00 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" rgroup.long 0x40++0x03 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "L3_STCOL_DUMP_MODE," bitfld.long 0x00 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x00 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" rgroup.long 0x4C++0x03 line.long 0x00 "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x00 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" group.long 0x58++0x03 line.long 0x00 "L3_STCOL_DUMP_SEND," bitfld.long 0x00 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" rgroup.long 0x48++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x00 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" group.long 0x50++0x03 line.long 0x00 "L3_STCOL_DUMP_SLVOFS," group.long 0x08++0x03 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" group.long 0x20++0x1F line.long 0x00 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x00 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x04 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x04 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x08 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x08 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x0C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x0C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x10 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x10 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x14 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x14 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x18 "L3_STCOL_EVTMUX_SEL6," bitfld.long 0x18 0.--2. "EVTMUX_SEL6,The select of the mux 6 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x1C "L3_STCOL_EVTMUX_SEL7," bitfld.long 0x1C 0.--2. "EVTMUX_SEL7,The select of the mux 7 Type: Control" "0,1,2,3,4,5,6,7" group.long 0x10++0x03 line.long 0x00 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x00 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" group.long 0x18++0x07 line.long 0x00 "L3_STCOL_REQEVT," bitfld.long 0x00 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x04 "L3_STCOL_RSPEVT," bitfld.long 0x04 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" group.long 0x0C++0x03 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" group.long 0x00++0x07 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" group.long 0x14++0x03 line.long 0x00 "L3_STCOL_TRIGEN," bitfld.long 0x00 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" width 0x0B tree.end tree "BB2D_FW" base ad:0x4A21A000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW" base ad:0x4A224000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP1_SDMA_FW" base ad:0x4A171000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "DSP2_SDMA_FW" base ad:0x4A173000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EDMA_TPCC_FW" base ad:0x4A161000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EVE1_FW" base ad:0x4A151000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "EVE2_FW" base ad:0x4A153000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "GPU_FW" base ad:0x4A214000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "ISS_FW" base ad:0x4A155000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "IVA_CONFIG_FW" base ad:0x4A220000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "L3_INSTR_FW" base ad:0x4A226000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCAN_FW" base ad:0x4A16D000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCASP1_FW" base ad:0x4A167000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCASP2_FW" base ad:0x4A169000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "MCASP3_FW" base ad:0x4A16B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "PRUSS1_FW" base ad:0x4A175000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "QSPI_FW" base ad:0x4A179000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" newline bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" newline bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" newline bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" newline bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" newline bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" newline bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" width 0x0B tree.end tree "BB2D_TARG" base ad:0x44000900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DEBUGSS_CT_TBR_TARG" base ad:0x45000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DMM_P1_TARG" base ad:0x44000200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DMM_P2_TARG" base ad:0x44001300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP1_SDMA_TARG" base ad:0x44000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSP2_SDMA_TARG" base ad:0x44000600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "DSS_TARG" base ad:0x44002900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EVE1_TARG" base ad:0x44000A00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "EVE2_TARG" base ad:0x44000B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "GPMC_TARG" base ad:0x44000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "GPU_TARG" base ad:0x44001200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IPU1_TARG" base ad:0x44001000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IPU2_TARG" base ad:0x44001100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "ISS_TARG" base ad:0x44000C00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IVA_CONFIG_TARG" base ad:0x44001600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IVA_SL2IF_TARG" base ad:0x44001800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L3_INSTR" base ad:0x45000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_CFG_TARG" base ad:0x44000500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_P1_TARG" base ad:0x44001C00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_P2_TARG" base ad:0x44001F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER1_P3_TARG" base ad:0x44002100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER2_P1_TARG" base ad:0x44002300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER2_P2_TARG" base ad:0x44002400 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER2_P3_TARG" base ad:0x44002500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_P1_TARG" base ad:0x44002600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_P2_TARG" base ad:0x44002700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_PER3_P3_TARG" base ad:0x44000E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "L4_WKUP_TARG" base ad:0x44001D00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCAN_TARG" base ad:0x44003200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCASP1_TARG" base ad:0x44002F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCASP2_TARG" base ad:0x44003000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MCASP3_TARG" base ad:0x44003100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMU1_TARG" base ad:0x44002200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "MMU2_TARG" base ad:0x44002800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "OCMC_RAM1_TARG" base ad:0x44000F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "OCMC_RAM2_TARG" base ad:0x44001700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "OCMC_RAM3_TARG" base ad:0x44001900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PCIE1_TARG" base ad:0x44003700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PCIE2_TARG" base ad:0x44003800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PRUSS1_TARG" base ad:0x44001400 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "QSPI_TARG" base ad:0x44003900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPCC_TARG" base ad:0x44002000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC1_TARG" base ad:0x44002E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "TPTC2_TARG" base ad:0x44002B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Shows the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst..,Store with acknowledge incrementing burst..,Store with acknowledge wrapping burst non-atomic..,Load incrementing burst non-atomic request,Load wrapping burst non-atomic request,Control packet,Flush,Store without acknowledge incrementing burst..,Store without acknowledge wrapping burst atomic..,Store with acknowledge incrementing burst atomic..,Store with acknowledge wrapping burst atomic..,Load incrementing burst atomic request,Load wrapping burst atomic request,Reserved,Reserved" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "Logged request is,Logged request is,Logged request is,Reserved" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "IPU1_FW" base ad:0x4A15B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "IPU2_FW" base ad:0x4A218000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "IVA_SL2IF_FW" base ad:0x4A21E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "EMIF_OCP_FW" base ad:0x4A20C000 tree "Channel_0" group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" newline bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" newline bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" newline bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10++0x07 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "MA_MPU_NTTP_FW" base ad:0x4A20A000 tree "Channel_0" group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" newline bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" newline bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" newline bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10++0x07 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "OCMC_RAM1_FW" base ad:0x4A212000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_10" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_11" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_12" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_13" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_14" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_15" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_8" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_9" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "OCMC_RAM2_FW" base ad:0x4A20E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_10" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_11" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_12" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_13" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_14" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_15" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_8" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_9" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "OCMC_RAM3_FW" base ad:0x4A22A000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_10" group.long 0x124++0x03 line.long 0x00 "END_REGION_i_10,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x12C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x128++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x120++0x03 line.long 0x00 "START_REGION_i_10,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_11" group.long 0x134++0x03 line.long 0x00 "END_REGION_i_11,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x13C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x138++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x130++0x03 line.long 0x00 "START_REGION_i_11,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_12" group.long 0x144++0x03 line.long 0x00 "END_REGION_i_12,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x14C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x148++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x140++0x03 line.long 0x00 "START_REGION_i_12,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_13" group.long 0x154++0x03 line.long 0x00 "END_REGION_i_13,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x15C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x158++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x150++0x03 line.long 0x00 "START_REGION_i_13,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_14" group.long 0x164++0x03 line.long 0x00 "END_REGION_i_14,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x16C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x168++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x160++0x03 line.long 0x00 "START_REGION_i_14,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_15" group.long 0x174++0x03 line.long 0x00 "END_REGION_i_15,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x17C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x178++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x170++0x03 line.long 0x00 "START_REGION_i_15,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_8" group.long 0x104++0x03 line.long 0x00 "END_REGION_i_8,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x108++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x100++0x03 line.long 0x00 "START_REGION_i_8,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_9" group.long 0x114++0x03 line.long 0x00 "END_REGION_i_9,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x11C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x118++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x110++0x03 line.long 0x00 "START_REGION_i_9,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "DSS_FW" base ad:0x4A21C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "GPMC_FW" base ad:0x4A210000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "PCIE1_FW" base ad:0x4A165000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "PCIESS2_FW" base ad:0x4A159000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_2" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_3" group.long 0xB4++0x03 line.long 0x00 "END_REGION_i_3,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xBC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xB8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xB0++0x03 line.long 0x00 "START_REGION_i_3,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_4" group.long 0xC4++0x03 line.long 0x00 "END_REGION_i_4,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xCC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xC8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xC0++0x03 line.long 0x00 "START_REGION_i_4,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_5" group.long 0xD4++0x03 line.long 0x00 "END_REGION_i_5,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xD8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xD0++0x03 line.long 0x00 "START_REGION_i_5,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_6" group.long 0xE4++0x03 line.long 0x00 "END_REGION_i_6,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xEC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xE8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xE0++0x03 line.long 0x00 "START_REGION_i_6,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end tree "REG_Bundle_7" group.long 0xF4++0x03 line.long 0x00 "END_REGION_i_7,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xF8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xF0++0x03 line.long 0x00 "START_REGION_i_7,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree "TPTC_FW" base ad:0x4A163000 tree "Channel_0" group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" newline bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" newline bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" newline bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10++0x07 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region iUpdated L3 firewall description for START_REGION_i and END_REGION_i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "FW_LOAD_REQ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "Allow transactions to reach the slave NIU (resume),No transaction can reach the slave NIU (suspend)" width 0x0B tree.end tree.end tree "L4_Interconnects" tree "CFG_AP" base ad:0x4A000000 tree "Channel_0" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end tree "Channel_1" rgroup.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group" rgroup.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" tree.end tree "Channel_2" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Define the base address of each segments" tree.end tree "Channel_3" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_4" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_5" rgroup.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group" rgroup.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_6" rgroup.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group" rgroup.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_7" rgroup.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group" rgroup.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" tree "REG_Bundle_10" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_100" group.long 0x624++0x03 line.long 0x00 "L4_AP_REGION_l_H_100,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x620++0x03 line.long 0x00 "L4_AP_REGION_l_L_100,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_101" group.long 0x62C++0x03 line.long 0x00 "L4_AP_REGION_l_H_101,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x628++0x03 line.long 0x00 "L4_AP_REGION_l_L_101,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_102" group.long 0x634++0x03 line.long 0x00 "L4_AP_REGION_l_H_102,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x630++0x03 line.long 0x00 "L4_AP_REGION_l_L_102,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_103" group.long 0x63C++0x03 line.long 0x00 "L4_AP_REGION_l_H_103,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x638++0x03 line.long 0x00 "L4_AP_REGION_l_L_103,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_104" group.long 0x644++0x03 line.long 0x00 "L4_AP_REGION_l_H_104,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x640++0x03 line.long 0x00 "L4_AP_REGION_l_L_104,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_105" group.long 0x64C++0x03 line.long 0x00 "L4_AP_REGION_l_H_105,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x648++0x03 line.long 0x00 "L4_AP_REGION_l_L_105,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_106" group.long 0x654++0x03 line.long 0x00 "L4_AP_REGION_l_H_106,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x650++0x03 line.long 0x00 "L4_AP_REGION_l_L_106,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_107" group.long 0x65C++0x03 line.long 0x00 "L4_AP_REGION_l_H_107,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x658++0x03 line.long 0x00 "L4_AP_REGION_l_L_107,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_108" group.long 0x664++0x03 line.long 0x00 "L4_AP_REGION_l_H_108,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x660++0x03 line.long 0x00 "L4_AP_REGION_l_L_108,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_109" group.long 0x66C++0x03 line.long 0x00 "L4_AP_REGION_l_H_109,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x668++0x03 line.long 0x00 "L4_AP_REGION_l_L_109,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_11" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_110" group.long 0x674++0x03 line.long 0x00 "L4_AP_REGION_l_H_110,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x670++0x03 line.long 0x00 "L4_AP_REGION_l_L_110,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_111" group.long 0x67C++0x03 line.long 0x00 "L4_AP_REGION_l_H_111,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x678++0x03 line.long 0x00 "L4_AP_REGION_l_L_111,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_112" group.long 0x684++0x03 line.long 0x00 "L4_AP_REGION_l_H_112,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x680++0x03 line.long 0x00 "L4_AP_REGION_l_L_112,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_113" group.long 0x68C++0x03 line.long 0x00 "L4_AP_REGION_l_H_113,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x688++0x03 line.long 0x00 "L4_AP_REGION_l_L_113,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_114" group.long 0x694++0x03 line.long 0x00 "L4_AP_REGION_l_H_114,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x690++0x03 line.long 0x00 "L4_AP_REGION_l_L_114,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_115" group.long 0x69C++0x03 line.long 0x00 "L4_AP_REGION_l_H_115,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x698++0x03 line.long 0x00 "L4_AP_REGION_l_L_115,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_116" group.long 0x6A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_116,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_116,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_117" group.long 0x6AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_117,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_117,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_118" group.long 0x6B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_118,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_118,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_119" group.long 0x6BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_119,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_119,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_12" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_120" group.long 0x6C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_120,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_120,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_121" group.long 0x6CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_121,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_121,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_122" group.long 0x6D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_122,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_122,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_123" group.long 0x6DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_123,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_123,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_124" group.long 0x6E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_124,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_124,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_125" group.long 0x6EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_125,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_125,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_126" group.long 0x6F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_126,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_126,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_127" group.long 0x6FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_127,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_127,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_128" group.long 0x704++0x03 line.long 0x00 "L4_AP_REGION_l_H_128,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x700++0x03 line.long 0x00 "L4_AP_REGION_l_L_128,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_13" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_14" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_15" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_16" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_17" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_18" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_19" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_20" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_21" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_22" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_23" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_24" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_25" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_26" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_27" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_28" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_29" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_30" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_31" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_32" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_33" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_34" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_35" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_36" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_37" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_38" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_39" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_40" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_41" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_42" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_43" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_44" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_45" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_46" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_47" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_48" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_49" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_50" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_51" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_52" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_53" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_54" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_55" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_56" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_57" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_58" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_59" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_60" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_61" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_62" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_63" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_64" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_65" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_66" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_67" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_68" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_69" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_70" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_71" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_72" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_73" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_74" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_75" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_76" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_77" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_78" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_79" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_8" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_80" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_81" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_82" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_83" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_84" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_85" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_86" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_87" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_88" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_89" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_9" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_90" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_91" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_92" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_93" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_94" group.long 0x5F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_95" group.long 0x5FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_96" group.long 0x604++0x03 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x600++0x03 line.long 0x00 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_97" group.long 0x60C++0x03 line.long 0x00 "L4_AP_REGION_l_H_97,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x608++0x03 line.long 0x00 "L4_AP_REGION_l_L_97,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_98" group.long 0x614++0x03 line.long 0x00 "L4_AP_REGION_l_H_98,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x610++0x03 line.long 0x00 "L4_AP_REGION_l_L_98,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_99" group.long 0x61C++0x03 line.long 0x00 "L4_AP_REGION_l_H_99,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x618++0x03 line.long 0x00 "L4_AP_REGION_l_L_99,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end width 0x0B tree.end tree "CFG_LA" base ad:0x4A000800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" abitfld.long 0x04 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved maximum regions is listed in" newline bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" newline rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" width 0x0B tree.end tree "WKUP_LA" base ad:0x4AE00800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" abitfld.long 0x04 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved maximum regions is listed in" newline bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" newline rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" width 0x0B tree.end tree "MAILBOX_TARG" base ad:0x4A0F5000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "OCP_WP_NOC_TARG" base ad:0x4A103000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "SPINLOCK_TARG" base ad:0x4A0F7000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" width 0x0B tree.end tree "MCASP8_CFG_TARG" base ad:0x4847E000 rgroup.long 0xA000++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0xA004++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0xA018++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0xA02C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM3_TARG" base ad:0x48811000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x2004++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x2018++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x202C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PER1_AP" base ad:0x48000000 tree "Channel_0" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end tree "Channel_1" rgroup.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group" rgroup.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" tree.end tree "Channel_2" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_3" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_4" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_5" rgroup.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group" rgroup.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_6" rgroup.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group" rgroup.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_7" rgroup.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group" rgroup.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" tree "REG_Bundle_10" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_11" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_12" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_13" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_14" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_15" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_16" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_17" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_18" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_19" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_20" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_21" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_22" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_23" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_24" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_25" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_26" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_27" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_28" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_29" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_30" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_31" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_32" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_33" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_34" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_35" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_36" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_37" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_38" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_39" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_40" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_41" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_42" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_43" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_44" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_45" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_46" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_47" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_48" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_49" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_50" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_51" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_52" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_53" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_54" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_55" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_56" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_57" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_58" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_59" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_60" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_61" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_62" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_63" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_64" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_65" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_66" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_67" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_68" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_69" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_70" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_71" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_72" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_73" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_74" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_75" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_76" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_77" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_78" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_79" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_8" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_80" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_81" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_82" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_83" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_84" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_9" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end width 0x0B tree.end tree "CFG_IA_IP0" base ad:0x4A001000 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Reserved,?..." rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat 3. (list 0. 1. 2. )(list ad:0x48001000 ad:0x48001400 ad:0x48001800 ) tree "PER1_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Reserved,?..." rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end repeat 3. (list 0. 1. 2. )(list ad:0x48401000 ad:0x48401400 ad:0x48401800 ) tree "PER2_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Reserved,?..." rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end repeat 3. (list 0. 1. 2. )(list ad:0x48801000 ad:0x48801400 ad:0x48801800 ) tree "PER3_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Reserved,?..." rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end repeat.end tree "WKUP_IA_IP0" base ad:0x4AE01000 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "No errors,Reserved,?..." rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" width 0x0B tree.end tree "PER1_LA" base ad:0x48000800 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" rgroup.long 0x1C++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x00 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." bitfld.long 0x00 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x18++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x00 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" abitfld.long 0x00 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved maximum regions is listed in" newline bitfld.long 0x00 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." group.long 0x24++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x00 20. "THREAD0_PRI,Sets thread priority" "0,1" newline rbitfld.long 0x00 8. "EXT_CLOCK,Global external clock control" "0,1" group.long 0x20++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x00 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." rgroup.long 0x14++0x03 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" width 0x0B tree.end tree "PER2_LA" base ad:0x48400800 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" rgroup.long 0x1C++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x00 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." bitfld.long 0x00 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x18++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x00 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" abitfld.long 0x00 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved maximum regions is listed in" newline bitfld.long 0x00 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." group.long 0x24++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x00 20. "THREAD0_PRI,Sets thread priority" "0,1" newline rbitfld.long 0x00 8. "EXT_CLOCK,Global external clock control" "0,1" group.long 0x20++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x00 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." rgroup.long 0x14++0x03 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" width 0x0B tree.end tree "PER3_LA" base ad:0x48800800 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" group.long 0x120++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" rgroup.long 0x1C++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x00 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "?,16-bit data width is specified,32-bit data width is specified,?..." bitfld.long 0x00 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x18++0x03 line.long 0x00 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x00 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "No protection group,1 protection group,2 protection groups,?,?,?,?,?,8 protection groups 0x9 to,?,?,?,?,?,?,Reserved" abitfld.long 0x00 16.--23. "NUMBER_REGIONS,Number of regions in the current L4" "0x00=Reserved,0x01=1 region,0x02=2 regions,0xFF=Reserved maximum regions is listed in" newline bitfld.long 0x00 0.--3. "SEGMENTS,Number of segments in the current L4" "Reserved,1 segment,2 segments,?,?,?,?,?,8 segments,?..." group.long 0x24++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x00 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x00 20. "THREAD0_PRI,Sets thread priority" "0,1" newline rbitfld.long 0x00 8. "EXT_CLOCK,Global external clock control" "0,1" group.long 0x20++0x03 line.long 0x00 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x00 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "Time-out disabled,L4 interconnect clock cycles divided by 64,L4 interconnect clock cycles divided by 256,L4 interconnect clock cycles divided by 1024,L4 interconnect clock cycles divided by 4096,?..." rgroup.long 0x14++0x03 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" width 0x0B tree.end tree "PER2_AP" base ad:0x48400000 tree "Channel_0" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_1" rgroup.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group" rgroup.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_2" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_3" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_4" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_5" rgroup.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group" rgroup.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_6" rgroup.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group" rgroup.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_7" rgroup.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group" rgroup.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L,Define the base address of each segments" tree "REG_Bundle_10" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_11" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_12" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_13" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_14" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_15" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_16" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_17" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_18" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_19" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_20" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_21" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_22" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_23" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_24" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_25" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_26" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_27" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_28" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_29" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_30" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_31" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_32" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_33" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_34" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_35" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_36" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_37" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_38" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_39" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_40" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_41" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_42" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_43" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_44" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_45" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_46" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_47" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_48" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_49" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_50" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_51" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_52" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_53" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_54" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_55" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_56" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_8" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_9" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end width 0x0B tree.end tree "PER3_AP" base ad:0x48800000 tree "Channel_0" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_1" rgroup.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group" rgroup.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_2" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_3" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_4" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_5" rgroup.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group" rgroup.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_6" rgroup.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group" rgroup.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_7" rgroup.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group" rgroup.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L,Define the base address of each segments" tree "REG_Bundle_10" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_11" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_12" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_13" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_14" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_15" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_16" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_17" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_18" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_19" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_20" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_21" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_22" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_23" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_24" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_25" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_26" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_27" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_28" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_29" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_30" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_31" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_32" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_33" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_34" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_35" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_36" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_37" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_38" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_39" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_40" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_41" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_42" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_43" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_44" group.long 0x464++0x03 line.long 0x00 "L4_AP_REGION_l_H_44,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x460++0x03 line.long 0x00 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_45" group.long 0x46C++0x03 line.long 0x00 "L4_AP_REGION_l_H_45,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x468++0x03 line.long 0x00 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_46" group.long 0x474++0x03 line.long 0x00 "L4_AP_REGION_l_H_46,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x470++0x03 line.long 0x00 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_47" group.long 0x47C++0x03 line.long 0x00 "L4_AP_REGION_l_H_47,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x478++0x03 line.long 0x00 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_48" group.long 0x484++0x03 line.long 0x00 "L4_AP_REGION_l_H_48,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x480++0x03 line.long 0x00 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_49" group.long 0x48C++0x03 line.long 0x00 "L4_AP_REGION_l_H_49,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x488++0x03 line.long 0x00 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_50" group.long 0x494++0x03 line.long 0x00 "L4_AP_REGION_l_H_50,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x490++0x03 line.long 0x00 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_51" group.long 0x49C++0x03 line.long 0x00 "L4_AP_REGION_l_H_51,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x498++0x03 line.long 0x00 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_52" group.long 0x4A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_52,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_53" group.long 0x4AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_53,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_54" group.long 0x4B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_54,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_55" group.long 0x4BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_55,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_56" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_57" group.long 0x4CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_57,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_58" group.long 0x4D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_58,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_59" group.long 0x4DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_59,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_60" group.long 0x4E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_60,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_61" group.long 0x4EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_61,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_62" group.long 0x4F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_62,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_63" group.long 0x4FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_63,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_64" group.long 0x504++0x03 line.long 0x00 "L4_AP_REGION_l_H_64,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x500++0x03 line.long 0x00 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_65" group.long 0x50C++0x03 line.long 0x00 "L4_AP_REGION_l_H_65,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x508++0x03 line.long 0x00 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_66" group.long 0x514++0x03 line.long 0x00 "L4_AP_REGION_l_H_66,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x510++0x03 line.long 0x00 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_67" group.long 0x51C++0x03 line.long 0x00 "L4_AP_REGION_l_H_67,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x518++0x03 line.long 0x00 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_68" group.long 0x524++0x03 line.long 0x00 "L4_AP_REGION_l_H_68,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x520++0x03 line.long 0x00 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_69" group.long 0x52C++0x03 line.long 0x00 "L4_AP_REGION_l_H_69,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x528++0x03 line.long 0x00 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_70" group.long 0x534++0x03 line.long 0x00 "L4_AP_REGION_l_H_70,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x530++0x03 line.long 0x00 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_71" group.long 0x53C++0x03 line.long 0x00 "L4_AP_REGION_l_H_71,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x538++0x03 line.long 0x00 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_72" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_73" group.long 0x54C++0x03 line.long 0x00 "L4_AP_REGION_l_H_73,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x548++0x03 line.long 0x00 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_74" group.long 0x554++0x03 line.long 0x00 "L4_AP_REGION_l_H_74,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x550++0x03 line.long 0x00 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_75" group.long 0x55C++0x03 line.long 0x00 "L4_AP_REGION_l_H_75,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x558++0x03 line.long 0x00 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_76" group.long 0x564++0x03 line.long 0x00 "L4_AP_REGION_l_H_76,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x560++0x03 line.long 0x00 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_77" group.long 0x56C++0x03 line.long 0x00 "L4_AP_REGION_l_H_77,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x568++0x03 line.long 0x00 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_78" group.long 0x574++0x03 line.long 0x00 "L4_AP_REGION_l_H_78,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x570++0x03 line.long 0x00 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_79" group.long 0x57C++0x03 line.long 0x00 "L4_AP_REGION_l_H_79,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x578++0x03 line.long 0x00 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_8" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_80" group.long 0x584++0x03 line.long 0x00 "L4_AP_REGION_l_H_80,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x580++0x03 line.long 0x00 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_81" group.long 0x58C++0x03 line.long 0x00 "L4_AP_REGION_l_H_81,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x588++0x03 line.long 0x00 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_82" group.long 0x594++0x03 line.long 0x00 "L4_AP_REGION_l_H_82,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x590++0x03 line.long 0x00 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_83" group.long 0x59C++0x03 line.long 0x00 "L4_AP_REGION_l_H_83,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x598++0x03 line.long 0x00 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_84" group.long 0x5A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_84,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_85" group.long 0x5AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_85,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_86" group.long 0x5B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_86,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_87" group.long 0x5BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_87,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_88" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_89" group.long 0x5CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_89,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_9" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_90" group.long 0x5D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_90,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_91" group.long 0x5DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_91,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_92" group.long 0x5E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_92,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_93" group.long 0x5EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_93,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_94" group.long 0x5F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_94,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_95" group.long 0x5FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_95,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_96" group.long 0x604++0x03 line.long 0x00 "L4_AP_REGION_l_H_96,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x600++0x03 line.long 0x00 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end width 0x0B tree.end tree "CAL_TARG" base ad:0x489C0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CM_CORE_AON_TARG" base ad:0x4A006000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CM_CORE_TARG" base ad:0x4A00A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "COUNTER_32K_TARG" base ad:0x4AE05000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CTRL_MODULE_CORE_TARG" base ad:0x4A004000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "CTRL_MODULE_WKUP_TARG" base ad:0x4AE0D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCAN1_TARG" base ad:0x4AE3E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DCAN2_TARG" base ad:0x48482000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW_CFG_TARG" base ad:0x4A225000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DMA_SYSTEM_TARG" base ad:0x4A057000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP1_SDMA_FW_CFG_TARG" base ad:0x4A172000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSP2_SDMA_FW_CFG_TARG" base ad:0x4A174000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "DSS_FW_CFG_TARG" base ad:0x4A21D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "ELM_TARG" base ad:0x48079000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EMIF_OCP_FW_CFG_TARG" base ad:0x4A20D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE1_FW_CFG_TARG" base ad:0x4A152000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "EVE2_FW_CFG_TARG" base ad:0x4A154000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GMAC_TARG" base ad:0x48488000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO1_TARG" base ad:0x4AE11000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO2_TARG" base ad:0x48056000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO3_TARG" base ad:0x48058000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO4_TARG" base ad:0x4805A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO5_TARG" base ad:0x4805C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO6_TARG" base ad:0x4805E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO7_TARG" base ad:0x48052000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPIO8_TARG" base ad:0x48054000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPMC_FW_CFG_TARG" base ad:0x4A211000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "GPU_FW_CFG_TARG" base ad:0x4A215000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C1_TARG" base ad:0x48071000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C2_TARG" base ad:0x48073000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C3_TARG" base ad:0x48061000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C4_TARG" base ad:0x4807B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "I2C5_TARG" base ad:0x4807D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IPU1_FW_CFG_TARG" base ad:0x4A15C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IPU2_FW_CFG_TARG" base ad:0x4A219000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "ISS_FW_CFG_TARG" base ad:0x4A156000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IVA_CONFIG_FW_CFG_TARG" base ad:0x4A221000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "IVA_SL2IF_FW_CFG_TARG" base ad:0x4A21F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "L3_INSTR_FW_CFG_TARG" base ad:0x4A227000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MA_MPU_NTTP_FW_CFG_TARG" base ad:0x4A20B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX10_TARG" base ad:0x48861000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX11_TARG" base ad:0x48863000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX12_TARG" base ad:0x48865000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX13_TARG" base ad:0x48803000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX2_TARG" base ad:0x4883B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX3_TARG" base ad:0x4883D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX4_TARG" base ad:0x4883F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX5_TARG" base ad:0x48841000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX6_TARG" base ad:0x48843000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX7_TARG" base ad:0x48845000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX8_TARG" base ad:0x48847000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MBX9_TARG" base ad:0x4885F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCAN_FW_CFG_TARG" base ad:0x4A16E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_CFG_TARG" base ad:0x48462000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP1_FW_CFG_TARG" base ad:0x4A168000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP2_CFG_TARG" base ad:0x48466000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP2_FW_CFG_TARG" base ad:0x4A16A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP3_CFG_TARG" base ad:0x4846A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP3_FW_CFG_TARG" base ad:0x4A16C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP4_CFG_TARG" base ad:0x4846E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP4_DAT_TARG" base ad:0x48437000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP5_CFG_TARG" base ad:0x48472000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP5_DAT_TARG" base ad:0x4843B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP6_CFG_TARG" base ad:0x48476000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP6_DAT_TARG" base ad:0x4844D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP7_CFG_TARG" base ad:0x4847A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP7_DAT_TARG" base ad:0x48451000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCASP8_DAT_TARG" base ad:0x48455000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI1_TARG" base ad:0x48099000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI2_TARG" base ad:0x4809B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI3_TARG" base ad:0x480B9000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MCSPI4_TARG" base ad:0x480BB000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMC1_TARG" base ad:0x4809D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMC2_TARG" base ad:0x480B5000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMC3_TARG" base ad:0x480AE000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMC4_TARG" base ad:0x480D2000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMU1_TARG" base ad:0x4881D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "MMU2_TARG" base ad:0x4881F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM1_FW_CFG_TARG" base ad:0x4A213000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM1_TARG" base ad:0x48805000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM2_FW_CFG_TARG" base ad:0x4A20F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM2_TARG" base ad:0x4880B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "OCMC_RAM3_FW_CFG_TARG" base ad:0x4A22B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PCIESS1_FW_CFG_TARG" base ad:0x4A166000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PCIESS2_FW_CFG_TARG" base ad:0x4A15A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PRM_TARG" base ad:0x4AE08000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PRUSS1_FW_CFG_TARG" base ad:0x4A176000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PWM1_TARG" base ad:0x4843F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PWM2_TARG" base ad:0x48441000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "PWM3_TARG" base ad:0x48443000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "QSPI_FW_CFG_TARG" base ad:0x4A17A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "RTC_TARG" base ad:0x48839000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "SCP1_TARG" base ad:0x4A088000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "SCP2_TARG" base ad:0x4A0A8000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "SCP3_TARG" base ad:0x4A098000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER10_TARG" base ad:0x48087000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER11_TARG" base ad:0x48089000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER12_TARG" base ad:0x4AE21000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER13_TARG" base ad:0x48829000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER14_TARG" base ad:0x4882B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER15_TARG" base ad:0x4882D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER16_TARG" base ad:0x4882F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER1_TARG" base ad:0x4AE19000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER2_TARG" base ad:0x48033000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER3_TARG" base ad:0x48035000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER4_TARG" base ad:0x48037000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER5_TARG" base ad:0x48821000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER6_TARG" base ad:0x48823000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER7_TARG" base ad:0x48825000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER8_TARG" base ad:0x48827000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TIMER9_TARG" base ad:0x4803F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TPCC_FW_CFG_TARG" base ad:0x4A162000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "TPTC_FW_CFG_TARG" base ad:0x4A164000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART10_TARG" base ad:0x4AE2C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART1_TARG" base ad:0x4806B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART2_TARG" base ad:0x4806D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART3_TARG" base ad:0x48021000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART4_TARG" base ad:0x4806F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART5_TARG" base ad:0x48067000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART6_TARG" base ad:0x48069000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART7_TARG" base ad:0x48421000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART8_TARG" base ad:0x48423000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "UART9_TARG" base ad:0x48425000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "USB1_TARG" base ad:0x488A0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "USB2_TARG" base ad:0x488E0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "USB3_TARG" base ad:0x48920000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "USB4_TARG" base ad:0x48960000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VIP1_TARG" base ad:0x48980000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VIP2_TARG" base ad:0x489A0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "VPE_TARG" base ad:0x489E0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "WD_TIMER2_TARG" base ad:0x4AE15000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "No request time-out,A request time-out has occurred" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" width 0x0B tree.end tree "WKUP_AP" base ad:0x4AE00000 tree "Channel_0" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.long 0x280++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end tree "Channel_1" rgroup.long 0x208++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x28C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group" rgroup.long 0x288++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group" group.long 0x30C++0x03 line.long 0x00 "L4_AP_REGION_l_H_1,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x308++0x03 line.long 0x00 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x10C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x108++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" tree.end tree "Channel_2" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.long 0x290++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x114++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_2,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x110++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_2,Define the base address of each segments" tree.end tree "Channel_3" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.long 0x298++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x11C++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_3,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x118++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_3,Define the base address of each segments" tree.end tree "Channel_4" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.long 0x2A0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_5" rgroup.long 0x228++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2AC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group" rgroup.long 0x2A8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group" group.long 0x32C++0x03 line.long 0x00 "L4_AP_REGION_l_H_5,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x328++0x03 line.long 0x00 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_6" rgroup.long 0x230++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2B4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group" rgroup.long 0x2B0++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group" group.long 0x334++0x03 line.long 0x00 "L4_AP_REGION_l_H_6,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x330++0x03 line.long 0x00 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "Channel_7" rgroup.long 0x238++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2BC++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group" rgroup.long 0x2B8++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group" group.long 0x33C++0x03 line.long 0x00 "L4_AP_REGION_l_H_7,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x338++0x03 line.long 0x00 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" tree "REG_Bundle_10" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_11" group.long 0x35C++0x03 line.long 0x00 "L4_AP_REGION_l_H_11,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x358++0x03 line.long 0x00 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_12" group.long 0x364++0x03 line.long 0x00 "L4_AP_REGION_l_H_12,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_13" group.long 0x36C++0x03 line.long 0x00 "L4_AP_REGION_l_H_13,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x368++0x03 line.long 0x00 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_14" group.long 0x374++0x03 line.long 0x00 "L4_AP_REGION_l_H_14,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x370++0x03 line.long 0x00 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_15" group.long 0x37C++0x03 line.long 0x00 "L4_AP_REGION_l_H_15,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x378++0x03 line.long 0x00 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_16" group.long 0x384++0x03 line.long 0x00 "L4_AP_REGION_l_H_16,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x380++0x03 line.long 0x00 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_17" group.long 0x38C++0x03 line.long 0x00 "L4_AP_REGION_l_H_17,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x388++0x03 line.long 0x00 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_18" group.long 0x394++0x03 line.long 0x00 "L4_AP_REGION_l_H_18,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x390++0x03 line.long 0x00 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_19" group.long 0x39C++0x03 line.long 0x00 "L4_AP_REGION_l_H_19,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x398++0x03 line.long 0x00 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_20" group.long 0x3A4++0x03 line.long 0x00 "L4_AP_REGION_l_H_20,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A0++0x03 line.long 0x00 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_21" group.long 0x3AC++0x03 line.long 0x00 "L4_AP_REGION_l_H_21,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3A8++0x03 line.long 0x00 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_22" group.long 0x3B4++0x03 line.long 0x00 "L4_AP_REGION_l_H_22,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B0++0x03 line.long 0x00 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_23" group.long 0x3BC++0x03 line.long 0x00 "L4_AP_REGION_l_H_23,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3B8++0x03 line.long 0x00 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_24" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_25" group.long 0x3CC++0x03 line.long 0x00 "L4_AP_REGION_l_H_25,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C8++0x03 line.long 0x00 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_26" group.long 0x3D4++0x03 line.long 0x00 "L4_AP_REGION_l_H_26,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D0++0x03 line.long 0x00 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_27" group.long 0x3DC++0x03 line.long 0x00 "L4_AP_REGION_l_H_27,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3D8++0x03 line.long 0x00 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_28" group.long 0x3E4++0x03 line.long 0x00 "L4_AP_REGION_l_H_28,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E0++0x03 line.long 0x00 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_29" group.long 0x3EC++0x03 line.long 0x00 "L4_AP_REGION_l_H_29,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3E8++0x03 line.long 0x00 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_30" group.long 0x3F4++0x03 line.long 0x00 "L4_AP_REGION_l_H_30,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F0++0x03 line.long 0x00 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_31" group.long 0x3FC++0x03 line.long 0x00 "L4_AP_REGION_l_H_31,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3F8++0x03 line.long 0x00 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_32" group.long 0x404++0x03 line.long 0x00 "L4_AP_REGION_l_H_32,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x400++0x03 line.long 0x00 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_33" group.long 0x40C++0x03 line.long 0x00 "L4_AP_REGION_l_H_33,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x408++0x03 line.long 0x00 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_34" group.long 0x414++0x03 line.long 0x00 "L4_AP_REGION_l_H_34,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x410++0x03 line.long 0x00 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_35" group.long 0x41C++0x03 line.long 0x00 "L4_AP_REGION_l_H_35,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x418++0x03 line.long 0x00 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_36" group.long 0x424++0x03 line.long 0x00 "L4_AP_REGION_l_H_36,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x420++0x03 line.long 0x00 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_37" group.long 0x42C++0x03 line.long 0x00 "L4_AP_REGION_l_H_37,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x428++0x03 line.long 0x00 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_38" group.long 0x434++0x03 line.long 0x00 "L4_AP_REGION_l_H_38,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x430++0x03 line.long 0x00 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_39" group.long 0x43C++0x03 line.long 0x00 "L4_AP_REGION_l_H_39,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x438++0x03 line.long 0x00 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_40" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_41" group.long 0x44C++0x03 line.long 0x00 "L4_AP_REGION_l_H_41,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x448++0x03 line.long 0x00 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_42" group.long 0x454++0x03 line.long 0x00 "L4_AP_REGION_l_H_42,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x450++0x03 line.long 0x00 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_43" group.long 0x45C++0x03 line.long 0x00 "L4_AP_REGION_l_H_43,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x458++0x03 line.long 0x00 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_8" group.long 0x344++0x03 line.long 0x00 "L4_AP_REGION_l_H_8,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x340++0x03 line.long 0x00 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end tree "REG_Bundle_9" group.long 0x34C++0x03 line.long 0x00 "L4_AP_REGION_l_H_9,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x348++0x03 line.long 0x00 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end width 0x0B tree.end tree.end tree "MCAN" tree "MCAN" base ad:0x42C00000 rgroup.long 0x1900++0x2B line.long 0x00 "MCANSS_PID,Revision Register The Revision Register contains the major and minor revisions for the module" line.long 0x04 "MCANSS_CTRL,Control Register The Control Register contains general control bits for the MCAN module" bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External Timestamp Counter Enable" "0,1" newline bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" newline bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x04 3. "FREE," "0,1" newline bitfld.long 0x04 2. "SOFT,If FREE =" "debug suspend doesn't wait for Idle,debug suspend waits for Idle" newline bitfld.long 0x04 1. "CLKFACK,Clock Fast Ack" "0,1" newline bitfld.long 0x04 0. "RESET,Initiates a Soft Reset Note: Software application should complete all pending MCAN services before applying the soft reset" "0,1" line.long 0x08 "MCANSS_STAT,Status Regsiter The Status register provide general status bits for the MCAN module" bitfld.long 0x08 3.--5. "STATE," "?,In transition to Idle,Idle,In transition to Active,?..." newline bitfld.long 0x08 2. "ENABLE_FDOE,Enable CAN FD configuration" "0,1" newline bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1" newline bitfld.long 0x08 0. "RESET," "0,1" line.long 0x0C "MCANSS_ICS,Interrupt Clear Shadow Register Write to clear interrupt bits" bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x10 "MCANSS_IRS,Interrupt Raw Status Register Read raw interrupt status" bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt status" "0,1" line.long 0x14 "MCANSS_IECS,Interrupt Enable Clear Shadow Register Write to clear interrupt enable bits" bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x18 "MCANSS_IE,Interrupt Enable Register Read interrupt Enable" bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x1C "MCANSS_IES,Interrupt Enable Status Read Enabled Interrupts" bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt" "0,1" line.long 0x20 "MCANSS_EOI,End Of Interrupt End of Interrupt Register" hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targetted interrupt (example: External TS is bit 0)" line.long 0x24 "MCANSS_EXT_TS_PRESCALER,External Timestamp PreScaler 0 External TImeStamp PreScaler" hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value" line.long 0x28 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External Timestamp PreScaler 0 Unserviced Interrupts Counter External TImeStamp Unserviced Interrupts Counter" bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1980++0x03 line.long 0x00 "MCANSS_ECC_EOI,ECC EOI End Of Interrupt for ECC interrupt" bitfld.long 0x00 8. "ECC_EOI,ECC EOI" "0,1" rgroup.long 0x1A00++0x07 line.long 0x00 "MCAN_CREL,Core Release Register Release dependent constant (version + date)" bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded" newline hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded" line.long 0x04 "MCAN_ENDN,Endian Register Constant 0x8765 4321" group.long 0x1A0C++0x23 line.long 0x00 "MCAN_DBTP,Data Bit Timing & Prescaler Register Configuration of data phase bit timing. transmitter delay compensation enable" bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "Transmitter Delay Compensation disabled,Transmitter Delay Compensation enabled" newline bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point Valid values are 0 to 31 (0x00-0x1F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width Valid values are 0 to 15 (0x0-0xF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "MCAN_TEST,Test Register Test mode selection" bitfld.long 0x04 7. "RX,Receive Pin Monitors the actual value of the MCAN_RX pin" "The CAN bus is dominant (MCAN_RX = 0),The CAN bus is recessive (MCAN_RX = 1)" newline bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "Reset value the MCAN_TX pin controlled by the..,Sample Point can be monitored at the MCAN_TX pin,Dominant (0) level at the MCAN_TX pin,Recessive (1) at the MCAN_TX pin" newline bitfld.long 0x04 4. "LBCK,Loop Back Mode" "Reset value Loop Back Mode is disabled,Loop Back Mode is enabled" line.long 0x08 "MCAN_RWD,RAM Watchdog Monitors the READY output of the Message RAM" hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value" newline hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter" line.long 0x0C "MCAN_CCCR,CC Control Register Operation mode configuration" bitfld.long 0x0C 14. "TXP,Transmit Pause If this bit is set the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame" "Transmit pause disabled,Transmit pause enabled" newline bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "Edge filtering disabled,Two consecutive dominant t" newline bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "Protocol exception handling enabled,Protocol exception handling disabled" newline bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "Bit rate switching for transmissions disabled,Bit rate switching for transmissions enabled" newline bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "FD operation disabled,FD operation enabled" newline bitfld.long 0x0C 7. "TEST,Test Mode Enable" "Normal operation,Test Mode" newline bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "Automatic retransmission of messages not..,Automatic retransmission disabled" newline bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "Bus Monitoring Mode is disabled,Bus Monitoring Mode is enabled" newline bitfld.long 0x0C 4. "CSR,Clock Stop Request" "No clock stop is requested,Clock stop requested" newline bitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "No clock stop acknowledged,The MCAN module may be set in power down by.." newline bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "Normal CAN operation,Restricted Operation Mode active" newline bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "The Host CPU has no write access to the..,The Host CPU has write access to the protected.." newline bitfld.long 0x0C 0. "INIT,Initialization" "Normal Operation,Initialization is started" line.long 0x10 "MCAN_NBTP,Nominal Bit Timing & Prescaler Register Configuration of arbitration phase bit timing" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width Valid values are 0 to 127 (0x00-0x7F)" newline hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta" newline hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point Valid values are 1 to 255 (0x01-0xFF)" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point Valid values are 0 to 127 (0x00-0x7F)" line.long 0x14 "MCAN_TSCC,Timestamp Counter Configuration Timestamp counter prescaler setting. selection of internal/external timestamp vector" bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0x0-0xF)]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "Timestamp counter value always 0x0000,Timestamp counter value incremented according to,External timestamp counter value used,Same as 00" line.long 0x18 "MCAN_TSCV,Timestamp Counter Value Read/reset timestamp counter" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)" line.long 0x1C "MCAN_TOCC,Timeout Counter Configuration Configuration of timeout period. selection of timeout counter operation mode" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)" newline bitfld.long 0x1C 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to" "Continuous operation,Timeout controlled by Tx Event FIFO,Timeout controlled by Rx FIFO 0,Timeout controlled by Rx FIFO 1" newline bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "Timeout Counter disabled,Timeout Counter enabled" line.long 0x20 "MCAN_TOCV,Timeout Counter Value Read/reset timeout counter" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of" rgroup.long 0x1A40++0x0B line.long 0x00 "MCAN_ECR,Error Counter Register State of Rx/Tx Error Counter. CAN Error Logging" hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented" newline bitfld.long 0x00 15. "RP,Receive Error Passive" "The Receive Error Counter is below the error..,The Receive Error Counter has reached the error.." newline hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127" newline hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255" line.long 0x04 "MCAN_PSR,Protocol Status Register CAN protocol controller status. transmitter delay compensation value" hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value Position of the secondary sample point defined by the sum of the measured delay from the MCAN_TX to MCAN_RX pins and" newline bitfld.long 0x04 14. "PXE,Protocol Exception Event" "No protocol exception event occurred since last..,Protocol exception event occurred" newline bitfld.long 0x04 13. "RFDF,Received a CAN FD Message This bit is set independent of acceptance filtering" "Since this bit was reset by the Host CPU no CAN..,Message in CAN FD format with FDF flag set has.." newline bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its BRS flag set" newline bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message This bit is set together with" "Last received CAN FD message did not have its..,Last received CAN FD message had its ESI flag set" newline bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "BO,Bus_Off Status" "The MCAN module is not Bus_Off,The MCAN module is in Bus_Off state" newline bitfld.long 0x04 6. "EW,Warning Status" "Both error counters are below the Error_Warning..,At least one of error counter has reached the.." newline bitfld.long 0x04 5. "EP,Error Passive" "The MCAN module is in the Error_Active state,The MCAN module is in the Error_Passive state" newline bitfld.long 0x04 3.--4. "ACT,Activity Monitors the module's CAN communication state" "Synchronizing - node is synchronizing on CAN..,Idle - node is neither receiver nor transmitter,Receiver - node is operating as receiver,Transmitter - node is operating as transmitter" newline bitfld.long 0x04 0.--2. "LEC,Last Error Code" "No Error,Stuff Error,Form Error,AckError,Bit1Error,Bit0Error,CRCError,NoChange" line.long 0x08 "MCAN_TDCR,Transmitter Delay Comensation Register Configuration of transmitter delay compensation offset and filter window length" hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset Offset value defining the distance between the measured delay from the MCAN_RX and MCAN_TX pins and the secondary sample point" newline hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position dominant edges on the MCAN_RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment" group.long 0x1A50++0x0F line.long 0x00 "MCAN_IR,Interrupt RegisterThe flags are set when one of the listed conditions is detected (edge-sensitive)" bitfld.long 0x00 29. "ARA,Access to Reserved Address" "No access to reserved address occurred,Access to reserved address occurred" newline bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "No protocol error in data phase,Protocol error in data phase detected (" newline bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "No protocol error in arbitration phase,Protocol error in arbitration phase detected (" newline bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "No Message RAM Watchdog event occurred,Message RAM Watchdog event due to missing READY" newline bitfld.long 0x00 25. "BO,Bus_Off Status" "Bus_Off status unchanged,Bus_Off status changed" newline bitfld.long 0x00 24. "EW,Warning Status" "Error_Warning status unchanged,Error_Warning status changed" newline bitfld.long 0x00 23. "EP,Error Passive" "Error_Passive status unchanged,Error_Passive status changed" newline bitfld.long 0x00 22. "ELO,Error Logging Overflow" "CAN Error Logging Counter did not overflow,Overflow of CAN Error Logging Counter occurred" newline bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "No bit error detected when reading from Message..,Bit error detected uncorrected (example: parity.." newline bitfld.long 0x00 20. "BEC,Bit Error Corrected Message RAM bit error detected and corrected" "No bit error detected when reading from Message..,Bit error detected and corrected (example: ECC)" newline bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "No Rx Buffer updated,At least one received message stored into an Rx.." newline bitfld.long 0x00 18. "TOO,Timeout Occurred" "No timeout,Timeout reached" newline bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler: - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "No Message RAM access failure occurred,Message RAM access failure occurred" newline bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "No timestamp counter wrap-around,Timestamp counter wrapped around" newline bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "Tx Event FIFO fill level below watermark,Tx Event FIFO fill level reached watermark" newline bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "Tx Event FIFO unchanged,Tx Handler wrote Tx Event FIFO element" newline bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "Tx FIFO non-empty,Tx FIFO empty" newline bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "No transmission cancellation finished,Transmission cancellation finished" newline bitfld.long 0x00 9. "TC,Transmission Completed" "No transmission completed,Transmission completed" newline bitfld.long 0x00 8. "HPM,High Priority Message" "No high priority message received,High priority message received" newline bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "Rx FIFO 1 fill level below watermark,Rx FIFO 1 fill level reached watermark" newline bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "No new message written to Rx FIFO 1,New message written to Rx FIFO 1" newline bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "Rx FIFO 0 fill level below watermark,Rx FIFO 0 fill level reached watermark" newline bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "No new message written to Rx FIFO 0,New message written to Rx FIFO 0" line.long 0x04 "MCAN_IE,Interrupt EnableThe settings in the Interrupt Enable register determine which status changes in the Interrupt Register are signalled on an interrupt line" bitfld.long 0x04 29. "ARAE,Access to Reserved Address Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" newline bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 8. "HPME,High Priority Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "Interrupt disabled,Interrupt enabled" newline bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "Interrupt disabled,Interrupt enabled" line.long 0x08 "MCAN_ILS,Interrupt Line SelectThe Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines" bitfld.long 0x08 29. "ARAL,Access to Reserved Address Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 8. "HPML,High Priority Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" newline bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "Interrupt assigned to interrupt line INT0,Interrupt assigned to interrupt line INT1" line.long 0x0C "MCAN_ILE,Interrupt Line Enable Enable/disable interrupt lines INT0/INT1" bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "Interrupt line INT1 disabled,Interrupt line INT1 enabled" newline bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "Interrupt line INT0 disabled,Interrupt line INT0 enabled" group.long 0x1A80++0x0B line.long 0x00 "MCAN_GFC,Global Filter Configuration Handling of non-matching frames and remote frames" bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "Accept in Rx..,Accept in Rx..,Reject,Reject" newline bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "Filter remote frames with 11-bit standard IDs,Reject all remote frames with 11-bit standard IDs" newline bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "Filter remote frames with 29-bit extended IDs,Reject all remote frames with 29-bit extended IDs" line.long 0x04 "MCAN_SIDFC,Standard ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard" newline hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see" line.long 0x08 "MCAN_XIDFC,Extended ID Filter Configuration Number of filter elements. pointer to start of filter list" hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended" newline hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see" group.long 0x1A90++0x57 line.long 0x00 "MCAN_XIDAM,Extended ID AND Mask 29-bit logical AND mask for J1939" hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame" line.long 0x04 "MCAN_HPMS,High Priority Message Status Status monitoring of incoming high priority messages" bitfld.long 0x04 15. "FLST,Filter List Indicates the filter list of the matching filter element" "Standard Filter List,Extended Filter List" newline hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index Index of matching filter element" newline bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "No FIFO selected,FIFO message lost,Message stored in FIFO 0,Message stored in FIFO 1" newline bitfld.long 0x04 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_NDAT1,New Data 1 NewDat flags of dedicated Rx buffers 0-31" bitfld.long 0x08 31. "ND31,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 30. "ND30,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 29. "ND29,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 28. "ND28,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 27. "ND27,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 26. "ND26,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 25. "ND25,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 24. "ND24,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 23. "ND23,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 22. "ND22,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 21. "ND21,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 20. "ND20,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 19. "ND19,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 18. "ND18,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 17. "ND17,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 16. "ND16,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 15. "ND15,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 14. "ND14,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 13. "ND13,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 12. "ND12,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 11. "ND11,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 10. "ND10,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 9. "ND9,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 8. "ND8,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 7. "ND7,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 6. "ND6,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 5. "ND5,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 4. "ND4,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 3. "ND3,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 2. "ND2,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 1. "ND1,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x08 0. "ND0,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x0C "MCAN_NDAT2,New Data 2 NewDat flags of dedicated Rx buffers 32-63" bitfld.long 0x0C 31. "ND63,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 30. "ND62,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 29. "ND61,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 28. "ND60,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 27. "ND59,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 26. "ND58,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 25. "ND57,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 24. "ND56,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 23. "ND55,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 22. "ND54,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 21. "ND53,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 20. "ND52,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 19. "ND51,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 18. "ND50,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 17. "ND49,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 16. "ND48,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 15. "ND47,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 14. "ND46,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 13. "ND45,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 12. "ND44,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 11. "ND43,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 10. "ND42,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 9. "ND41,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 8. "ND40,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 7. "ND39,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 6. "ND38,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 5. "ND37,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 4. "ND36,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 3. "ND35,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 2. "ND34,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 1. "ND33,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" newline bitfld.long 0x0C 0. "ND32,New Data" "Rx Buffer not updated,Rx Buffer updated from new message" line.long 0x10 "MCAN_RXF0C,Rx FIFO 0 Configuration FIFO 0 operation mode. watermark. size and start address" bitfld.long 0x10 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see 0x0: FIFO 0 blocking mode 0x1: FIFO 0 overwrite mode" "FIFO 0 blocking mode,FIFO 0 overwrite mode" newline hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x10 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see" line.long 0x14 "MCAN_RXF0S,Rx FIFO 0 Status FIFO 0 message lost/full indication. put index. get index and fill level" bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 0 message lost,Rx FIFO 0 message lost also set after write.." newline bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "Rx FIFO 0 not full,Rx FIFO 0 full" newline bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64" line.long 0x18 "MCAN_RXF0A,Rx FIFO 0 Acknowledge FIFO 0 acknowledge last index of read buffers. updates get index and fill level" bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "MCAN_RXBC,Rx Buffer Configuration Start address of Rx buffer section" hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM Also used to reference debug messages A B C" line.long 0x20 "MCAN_RXF1C,Rx FIFO 1 Configuration FIFO 1 operation mode. watermark. size and start address" bitfld.long 0x20 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see 0x0: FIFO 1 blocking mode 0x1: FIFO 1 overwrite mode" "FIFO 1 blocking mode,FIFO 1 overwrite mode" newline hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x20 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see" line.long 0x24 "MCAN_RXF1S,Rx FIFO 1 Status FIFO 1 message lost/full indication. put index. get index and fill level" bitfld.long 0x24 30.--31. "DMS,Debug Message Status" "Idle state wait for reception of debug messages..,Debug message A received,Debug messages A B received,Debug messages A B C received" newline bitfld.long 0x24 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag" "No Rx FIFO 1 message lost,Rx FIFO 1 message lost also set after write.." newline bitfld.long 0x24 24. "F1F,Rx FIFO 1 Full" "Rx FIFO 1 not full,Rx FIFO 1 full" newline bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64" line.long 0x28 "MCAN_RXF1A,Rx FIFO 1 Acknowledge FIFO 1 acknowledge last index of read buffers. updates get index and fill level" bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x2C "MCAN_RXESC,Rx Buffer/FIFO Element Size Configuration Configure data field size for storage of accepted frames" bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" newline bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x30 "MCAN_TXBC,Tx Buffer Configuration Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address" bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "Tx FIFO operation,Tx Queue operation" newline bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see" line.long 0x34 "MCAN_TXFQS,Tx FIFO/Queue Status Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level" bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "Tx FIFO/Queue not full,Tx FIFO/Queue full" newline bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "MCAN_TXESC,Tx Buffer Element Size Configuration Configure data field size for frame transmission" bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "8 byte data field,12 byte data field,16 byte data field,20 byte data field,24 byte data field,32 byte data field,48 byte data field,64 byte data field" line.long 0x3C "MCAN_TXBRP,Tx Buffer Request Pending Tx buffers with pending transmission request" bitfld.long 0x3C 31. "TRP31,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 30. "TRP30,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 29. "TRP29,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 28. "TRP28,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 27. "TRP27,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 26. "TRP26,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 25. "TRP25,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 24. "TRP24,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 23. "TRP23,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 22. "TRP22,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 21. "TRP21,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 20. "TRP20,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 19. "TRP19,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 18. "TRP18,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 17. "TRP17,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 16. "TRP16,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 15. "TRP15,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 14. "TRP14,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 13. "TRP13,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 12. "TRP12,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 11. "TRP11,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 10. "TRP10,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 9. "TRP9,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 8. "TRP8,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 7. "TRP7,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 6. "TRP6,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 5. "TRP5,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 4. "TRP4,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 3. "TRP3,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 2. "TRP2,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 1. "TRP1,Transmission Request Pending" "No transmission request pending,Transmission request pending" newline bitfld.long 0x3C 0. "TRP0,Transmission Request Pending" "No transmission request pending,Transmission request pending" line.long 0x40 "MCAN_TXBAR,Tx Buffer Add Request Add transmission requests" bitfld.long 0x40 31. "AR31,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 30. "AR30,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 29. "AR29,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 28. "AR28,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 27. "AR27,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 26. "AR26,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 25. "AR25,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 24. "AR24,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 23. "AR23,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 22. "AR22,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 21. "AR21,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 20. "AR20,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 19. "AR19,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 18. "AR18,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 17. "AR17,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 16. "AR16,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 15. "AR15,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 14. "AR14,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 13. "AR13,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 12. "AR12,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 11. "AR11,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 10. "AR10,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 9. "AR9,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 8. "AR8,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 7. "AR7,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 6. "AR6,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 5. "AR5,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 4. "AR4,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 3. "AR3,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 2. "AR2,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 1. "AR1,Add Request" "No transmission request added,Transmission requested added" newline bitfld.long 0x40 0. "AR0,Add Request" "No transmission request added,Transmission requested added" line.long 0x44 "MCAN_TXBCR,Tx Buffer Cancellation Request Request cancellation of pending transmissions" bitfld.long 0x44 31. "CR31,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 30. "CR30,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 29. "CR29,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 28. "CR28,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 27. "CR27,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 26. "CR26,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 25. "CR25,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 24. "CR24,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 23. "CR23,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 22. "CR22,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 21. "CR21,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 20. "CR20,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 19. "CR19,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 18. "CR18,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 17. "CR17,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 16. "CR16,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 15. "CR15,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 14. "CR14,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 13. "CR13,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 12. "CR12,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 11. "CR11,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 10. "CR10,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 9. "CR9,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 8. "CR8,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 7. "CR7,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 6. "CR6,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 5. "CR5,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 4. "CR4,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 3. "CR3,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 2. "CR2,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 1. "CR1,Cancellation Request" "No cancellation pending,Cancellation pending" newline bitfld.long 0x44 0. "CR0,Cancellation Request" "No cancellation pending,Cancellation pending" line.long 0x48 "MCAN_TXBTO,Tx Buffer Transmission Occurred Signals successful transmissions. set when corresponding flag is cleared" bitfld.long 0x48 31. "TO31,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 30. "TO30,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 29. "TO29,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 28. "TO28,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 27. "TO27,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 26. "TO26,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 25. "TO25,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 24. "TO24,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 23. "TO23,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 22. "TO22,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 21. "TO21,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 20. "TO20,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 19. "TO19,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 18. "TO18,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 17. "TO17,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 16. "TO16,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 15. "TO15,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 14. "TO14,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 13. "TO13,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 12. "TO12,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 11. "TO11,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 10. "TO10,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 9. "TO9,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 8. "TO8,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 7. "TO7,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 6. "TO6,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 5. "TO5,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 4. "TO4,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 3. "TO3,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 2. "TO2,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 1. "TO1,Transmission Occurred" "No transmission occurred,Transmission occurred" newline bitfld.long 0x48 0. "TO0,Transmission Occurred" "No transmission occurred,Transmission occurred" line.long 0x4C "MCAN_TXBCF,Tx Buffer Cancellation Finished Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request" bitfld.long 0x4C 31. "CF31,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 30. "CF30,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 29. "CF29,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 28. "CF28,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 27. "CF27,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 26. "CF26,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 25. "CF25,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 24. "CF24,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 23. "CF23,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 22. "CF22,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 21. "CF21,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 20. "CF20,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 19. "CF19,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 18. "CF18,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 17. "CF17,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 16. "CF16,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 15. "CF15,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 14. "CF14,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 13. "CF13,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 12. "CF12,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 11. "CF11,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 10. "CF10,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 9. "CF9,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 8. "CF8,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 7. "CF7,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 6. "CF6,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 5. "CF5,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 4. "CF4,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 3. "CF3,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 2. "CF2,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 1. "CF1,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" newline bitfld.long 0x4C 0. "CF0,Cancellation Finished" "No transmit buffer cancellation,Transmit buffer cancellation finished" line.long 0x50 "MCAN_TXBTIE,Tx Buffer Transmission Interrupt Enable Enable transmit interrupts for selected Tx buffers" bitfld.long 0x50 31. "TIE31,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 30. "TIE30,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 29. "TIE29,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 28. "TIE28,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 27. "TIE27,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 26. "TIE26,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 25. "TIE25,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 24. "TIE24,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 23. "TIE23,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 22. "TIE22,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 21. "TIE21,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 20. "TIE20,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 19. "TIE19,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 18. "TIE18,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 17. "TIE17,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 16. "TIE16,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 15. "TIE15,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 14. "TIE14,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 13. "TIE13,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 12. "TIE12,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 11. "TIE11,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 10. "TIE10,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 9. "TIE9,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 8. "TIE8,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 7. "TIE7,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 6. "TIE6,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 5. "TIE5,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 4. "TIE4,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 3. "TIE3,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 2. "TIE2,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 1. "TIE1,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" newline bitfld.long 0x50 0. "TIE0,Transmission Interrupt Enable" "Transmission interrupt disabled,Transmission interrupt enable" line.long 0x54 "MCAN_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable Enable cancellation finished interrupts for selected Tx buffers" bitfld.long 0x54 31. "CFIE31,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 30. "CFIE30,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 29. "CFIE29,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 28. "CFIE28,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 27. "CFIE27,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 26. "CFIE26,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 25. "CFIE25,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 24. "CFIE24,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 23. "CFIE23,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 22. "CFIE22,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 21. "CFIE21,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 20. "CFIE20,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 19. "CFIE19,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 18. "CFIE18,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 17. "CFIE17,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 16. "CFIE16,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 15. "CFIE15,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 14. "CFIE14,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 13. "CFIE13,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 12. "CFIE12,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 11. "CFIE11,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 10. "CFIE10,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 9. "CFIE9,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 8. "CFIE8,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 7. "CFIE7,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 6. "CFIE6,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 5. "CFIE5,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 4. "CFIE4,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 3. "CFIE3,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 2. "CFIE2,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 1. "CFIE1,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" newline bitfld.long 0x54 0. "CFIE0,Cancellation Finished Interrupt Enable" "Cancellation finished interrupt disabled,Cancellation finished interrupt enabled" group.long 0x1AF0++0x0B line.long 0x00 "MCAN_TXEFC,Tx Event FIFO Configuration Tx event FIFO watermark. size and start address" bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see" line.long 0x04 "MCAN_TXEFS,Tx Event FIFO Status Tx event FIFO element lost/full indication. put index. get index. and fill level" bitfld.long 0x04 25. "TEFL,This bit is a copy of interrupt flag" "No Tx Event FIFO element lost,Tx Event FIFO element lost also set after write.." newline bitfld.long 0x04 24. "EFF,Event FIFO Full" "Tx Event FIFO not full,Tx Event FIFO full" newline bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "MCAN_TXEFA,Tx Event FIFO Acknowledge Tx event FIFO acknowledge last index of read elements. updates get index and fill level" bitfld.long 0x08 0.--4. "EFAI,After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1C00++0x03 line.long 0x00 "MCANSS_ECC_AGGR_REVISION,Aggregator Revision Register Revision parameters" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C08++0x1F line.long 0x00 "MCANSS_ECC_VECTOR,ECC Vector Register ECC Vector Register" rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read is complete" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a" "0,1" newline hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" line.long 0x04 "MCANSS_ECC_MISC_STATUS,Misc Status Misc Status" hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" line.long 0x08 "MCANSS_ECC_WRAP_REVISION,ECC Wrapper Revision Register Revision parameters" bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3" newline bitfld.long 0x08 28.--29. "BU,Business Unit" "0,1,2,3" newline hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID" newline bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "MCANSS_ECC_CONTROL,ECC Control ECC Control Register" bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1" newline bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1" newline bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.long 0x0C 2. "ENABLE_RMW,Enable RMW" "0,1" newline bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1" line.long 0x10 "MCANSS_ECC_ERR_CTRL1,ECC Error Control1 Register ECC Error Control1 Register" hexmask.long.word 0x10 16.--31. 1. "ECC_BIT1,Data bit that needs to be flipped when FORCE_SEC is set" newline hexmask.long.word 0x10 0.--15. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied" line.long 0x14 "MCANSS_ECC_ERR_CTRL2,ECC Error Control2 Register ECC Error Control2 Register" hexmask.long.word 0x14 0.--15. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" line.long 0x18 "MCANSS_ECC_ERR_STAT1,ECC Error Status1 Register ECC Error Status1 Register" hexmask.long.word 0x18 16.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" newline bitfld.long 0x18 9. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1" newline bitfld.long 0x18 8. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1" newline bitfld.long 0x18 1. "ECC_DED,Level Double Bit Error Status" "0,1" newline bitfld.long 0x18 0. "ECC_SEC,Level Single Bit Error Status" "0,1" line.long 0x1C "MCANSS_ECC_ERR_STAT2,ECC Error Status2 Register ECC Error Status2 Register" hexmask.long.word 0x1C 16.--31. 1. "ECC_BIT2,Data bit that corresponds to the double-bit error" newline hexmask.long.word 0x1C 0.--15. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" group.long 0x1C3C++0x07 line.long 0x00 "MCANSS_ECC_SEC_EOI_REG,EOI Register EOI Register" bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_SEC_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1C80++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1CC0++0x03 line.long 0x00 "MCANSS_ECC_SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" group.long 0x1D3C++0x07 line.long 0x00 "MCANSS_ECC_DED_EOI_REG,EOI Register EOI Register" bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1" line.long 0x04 "MCANSS_ECC_DED_STATUS_REG0,Interrupt Status Register 0 Interrupt Status Register 0" bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for MSGMEM_PEND" "0,1" group.long 0x1D80++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0 Interrupt Enable Set Register 0" bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for MSGMEM_PEND" "0,1" group.long 0x1DC0++0x03 line.long 0x00 "MCANSS_ECC_DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0 Interrupt Enable Clear Register 0" bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for MSGMEM_PEND" "0,1" width 0x0B tree.end tree.end tree "MMU" repeat 2. (list 1. 2. )(list ad:0x4881C000 ad:0x4881E000 ) tree "System_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end repeat 2. (list 0. 1. )(list ad:0x40D01000 ad:0x40D02000 ) tree "DSP1_MMU$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the fourth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of fourth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "region not valid,64K bytes,128K bytes,256K bytes,512K bytes,1M bytes,2M bytes,4M bytes,8M bytes,16M bytes,32M bytes,64M bytes,128M bytes,256M bytes,512M bytes,1G bytes" width 0x0B tree.end repeat.end tree "IPU1_MMU" base ad:0x58882000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" width 0x0B tree.end tree "IPU2_MMU" base ad:0x55082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" width 0x0B tree.end tree.end tree "Multichannel_Audio_Serial_Port" tree "MCASP1_AFIFO" base ad:0x48461000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP2_AFIFO" base ad:0x48465000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP3_AFIFO" base ad:0x48469000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP4_AFIFO" base ad:0x4846D000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP5_AFIFO" base ad:0x48471000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP6_AFIFO" base ad:0x48475000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP7_AFIFO" base ad:0x48479000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP8_AFIFO" base ad:0x4847D000 group.long 0x00++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" abitfld.long 0x00 8.--15. "WNUMEVT,Write word count (32-bit) to generate TX event to host" "0x40=3 to 64 words currently in write..,0xFF=Reserved" abitfld.long 0x00 0.--7. "WNUMDMA,Write word count (32-bit words)" "0x10=3 to 16 words,0xFF=Reserved" line.long 0x04 "WFIFOSTS,The Write FIFO status register" abitfld.long 0x04 0.--7. "WLVL,Write level (read-only)" "0x40=3 to 64 words currently in write..,0xFF=Reserved" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" abitfld.long 0x08 8.--15. "RNUMEVT,Read word count (32-bit) to generate RX event to host" "0x40=3 to 64 words currently in read..,0xFF=Reserved" abitfld.long 0x08 0.--7. "RNUMDMA,Read word count (32-bit words)" "0x10=3-16 words,0xFF=Reserved" line.long 0x0C "RFIFOSTS,The Read FIFO status register" abitfld.long 0x0C 0.--7. "RLVL,Read level (read-only)" "0x40=3 to 64 words currently in read FIFO,0xFF=Reserved" width 0x0B tree.end tree "MCASP1_CFG" base ad:0x48460000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_10" group.long 0x2A8++0x03 line.long 0x00 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x228++0x03 line.long 0x00 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A8++0x03 line.long 0x00 "MCASP_XRSRCTLn_10,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_11" group.long 0x2AC++0x03 line.long 0x00 "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x22C++0x03 line.long 0x00 "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1AC++0x03 line.long 0x00 "MCASP_XRSRCTLn_11,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_12" group.long 0x2B0++0x03 line.long 0x00 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x230++0x03 line.long 0x00 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B0++0x03 line.long 0x00 "MCASP_XRSRCTLn_12,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_13" group.long 0x2B4++0x03 line.long 0x00 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x234++0x03 line.long 0x00 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B4++0x03 line.long 0x00 "MCASP_XRSRCTLn_13,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_14" group.long 0x2B8++0x03 line.long 0x00 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x238++0x03 line.long 0x00 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B8++0x03 line.long 0x00 "MCASP_XRSRCTLn_14,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_15" group.long 0x2BC++0x03 line.long 0x00 "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x23C++0x03 line.long 0x00 "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1BC++0x03 line.long 0x00 "MCASP_XRSRCTLn_15,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x290++0x03 line.long 0x00 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x210++0x03 line.long 0x00 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x190++0x03 line.long 0x00 "MCASP_XRSRCTLn_4,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x294++0x03 line.long 0x00 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x214++0x03 line.long 0x00 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x194++0x03 line.long 0x00 "MCASP_XRSRCTLn_5,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_6" group.long 0x298++0x03 line.long 0x00 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x218++0x03 line.long 0x00 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x198++0x03 line.long 0x00 "MCASP_XRSRCTLn_6,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_7" group.long 0x29C++0x03 line.long 0x00 "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x21C++0x03 line.long 0x00 "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x19C++0x03 line.long 0x00 "MCASP_XRSRCTLn_7,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_8" group.long 0x2A0++0x03 line.long 0x00 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x220++0x03 line.long 0x00 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A0++0x03 line.long 0x00 "MCASP_XRSRCTLn_8,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_9" group.long 0x2A4++0x03 line.long 0x00 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x224++0x03 line.long 0x00 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A4++0x03 line.long 0x00 "MCASP_XRSRCTLn_9,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP2_CFG" base ad:0x48464000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_10" group.long 0x2A8++0x03 line.long 0x00 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x228++0x03 line.long 0x00 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A8++0x03 line.long 0x00 "MCASP_XRSRCTLn_10,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_11" group.long 0x2AC++0x03 line.long 0x00 "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x22C++0x03 line.long 0x00 "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1AC++0x03 line.long 0x00 "MCASP_XRSRCTLn_11,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_12" group.long 0x2B0++0x03 line.long 0x00 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x230++0x03 line.long 0x00 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B0++0x03 line.long 0x00 "MCASP_XRSRCTLn_12,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_13" group.long 0x2B4++0x03 line.long 0x00 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x234++0x03 line.long 0x00 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B4++0x03 line.long 0x00 "MCASP_XRSRCTLn_13,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_14" group.long 0x2B8++0x03 line.long 0x00 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x238++0x03 line.long 0x00 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1B8++0x03 line.long 0x00 "MCASP_XRSRCTLn_14,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_15" group.long 0x2BC++0x03 line.long 0x00 "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x23C++0x03 line.long 0x00 "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1BC++0x03 line.long 0x00 "MCASP_XRSRCTLn_15,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x290++0x03 line.long 0x00 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x210++0x03 line.long 0x00 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x190++0x03 line.long 0x00 "MCASP_XRSRCTLn_4,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x294++0x03 line.long 0x00 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x214++0x03 line.long 0x00 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x194++0x03 line.long 0x00 "MCASP_XRSRCTLn_5,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_6" group.long 0x298++0x03 line.long 0x00 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x218++0x03 line.long 0x00 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x198++0x03 line.long 0x00 "MCASP_XRSRCTLn_6,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_7" group.long 0x29C++0x03 line.long 0x00 "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x21C++0x03 line.long 0x00 "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x19C++0x03 line.long 0x00 "MCASP_XRSRCTLn_7,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_8" group.long 0x2A0++0x03 line.long 0x00 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x220++0x03 line.long 0x00 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A0++0x03 line.long 0x00 "MCASP_XRSRCTLn_8,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_9" group.long 0x2A4++0x03 line.long 0x00 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x224++0x03 line.long 0x00 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x1A4++0x03 line.long 0x00 "MCASP_XRSRCTLn_9,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP1_DAT" base ad:0x45800000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP2_DAT" base ad:0x45C00000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP3_DAT" base ad:0x46000000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP4_DAT" base ad:0x48436000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP5_DAT" base ad:0x4843A000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP6_DAT" base ad:0x4844C000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP7_DAT" base ad:0x48450000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP8_DAT" base ad:0x48454000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the MCASP automatically cycles through the appropriate serializers" width 0x0B tree.end tree "MCASP3_CFG" base ad:0x48468000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP4_CFG" base ad:0x4846C000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP5_CFG" base ad:0x48470000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP6_CFG" base ad:0x48474000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP7_CFG" base ad:0x48478000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree "MCASP8_CFG" base ad:0x4847C000 tree "Channel_0" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_1" group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x284++0x03 line.long 0x00 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x204++0x03 line.long 0x00 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x184++0x03 line.long 0x00 "MCASP_XRSRCTLn_1,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_2" group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x288++0x03 line.long 0x00 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x208++0x03 line.long 0x00 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x188++0x03 line.long 0x00 "MCASP_XRSRCTLn_2,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_3" group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x28C++0x03 line.long 0x00 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x20C++0x03 line.long 0x00 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x18C++0x03 line.long 0x00 "MCASP_XRSRCTLn_3,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end tree "Channel_4" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end tree "Channel_5" group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end group.long 0x70++0x03 line.long 0x00 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" bitfld.long 0x00 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" newline bitfld.long 0x00 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xB0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" bitfld.long 0x00 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" newline bitfld.long 0x00 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x00 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "Divide-by-1,Divide-by-2 0x2 to,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide-by-3 to divide-by-32" group.long 0x74++0x03 line.long 0x00 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" bitfld.long 0x00 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" newline hexmask.long.word 0x00 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0xB4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x00 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x00 19. "DIVBUSY,Status: divide ratio change in progress? Not supported" "DIVBUSY_0,DIVBUSY_1" newline bitfld.long 0x00 18. "ADJBUSY,Status: one-shot adjustment in progress? Not supported" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x00 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "(m+0) input clocks per output clock i.e,(m-1) input clocks per output clock,(m+1) input clocks per output clock,(m+0) input clocks per output clock i.e" newline bitfld.long 0x00 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" bitfld.long 0x00 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" newline abitfld.long 0x00 0.--11. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" "0x000=Divide-by-1,0x001=Divide-by-2 0x2 to,0xFFF=Divide-by-3 to divide-by-4096" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" group.long 0xD0++0x03 line.long 0x00 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x00 0. "ENABLE,One-shot clock adjust enable" "ENABLE_0,ENABLE_1" group.long 0x7C++0x03 line.long 0x00 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT)" bitfld.long 0x00 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" group.long 0xBC++0x03 line.long 0x00 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x00 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x00 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" group.long 0x60++0x03 line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" newline bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0xA0++0x03 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" newline bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" newline bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" newline rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" newline rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" group.long 0x4C++0x03 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects betweeninternal-level (MCASP module-level) and chip I/O-level loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" newline bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" group.long 0x20++0x03 line.long 0x00 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" rgroup.long 0x1C++0x03 line.long 0x00 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins" bitfld.long 0x00 31. "AFSR,Logic level on AFSR pin (device level: mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Logic level on AFSX pin (device level: mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x14++0x0B line.long 0x00 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x04 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x04 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" newline bitfld.long 0x04 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" newline bitfld.long 0x04 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" newline bitfld.long 0x04 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x04 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x04 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" newline bitfld.long 0x04 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" newline bitfld.long 0x04 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" newline bitfld.long 0x04 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x04 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x04 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x08 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x08 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" newline bitfld.long 0x08 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" newline bitfld.long 0x08 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" newline bitfld.long 0x08 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x08 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x08 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" newline bitfld.long 0x08 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" newline bitfld.long 0x08 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" newline bitfld.long 0x08 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x08 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x08 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x10++0x03 line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" newline bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO" "AXR15_0,AXR15_1" newline bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO" "AXR13_0,AXR13_1" newline bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO" "AXR9_0,AXR9_1" newline bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO" "AXR7_0,AXR7_1" newline bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO" "AXR6_0,AXR6_1" bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO" "AXR5_0,AXR5_1" newline bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO" "AXR3_0,AXR3_1" newline bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO" "AXR0_0,AXR0_1" rgroup.long 0x00++0x03 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" newline hexmask.long.word 0x00 16.--27. 1. "FUNCTION,MCASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" newline bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x00 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0x88++0x03 line.long 0x00 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "RCNT," hexmask.long.byte 0x00 16.--23. 1. "RMAX," newline hexmask.long.byte 0x00 8.--15. 1. "RMIN," bitfld.long 0x00 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" group.long 0x6C++0x03 line.long 0x00 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" abitfld.long 0x00 7.--15. "RMOD,Receive frame sync mode select bits" "0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x1FF=Reserved" bitfld.long 0x00 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" newline bitfld.long 0x00 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x00 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" group.long 0x68++0x03 line.long 0x00 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x00 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x00 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" newline bitfld.long 0x00 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x00 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" bitfld.long 0x00 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" newline bitfld.long 0x00 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" group.long 0x64++0x03 line.long 0x00 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" group.long 0x80++0x03 line.long 0x00 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x00 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x00 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" newline bitfld.long 0x00 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x00 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" newline bitfld.long 0x00 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" bitfld.long 0x00 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" newline bitfld.long 0x00 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x00 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" newline bitfld.long 0x00 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" group.long 0x78++0x03 line.long 0x00 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" rgroup.long 0x84++0x03 line.long 0x00 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x00 0.--8. 1. "RSLOTCNT," group.long 0xC8++0x03 line.long 0x00 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x00 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. "XMAX,0x0 to" newline hexmask.long.byte 0x00 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x00 0.--3. "XPS,Transmit clock check prescaler value" "MCASP interface clock divided by 1,MCASP interface clock divided by 2,MCASP interface clock divided by 4,MCASP interface clock divided by 8,MCASP interface clock divided by 16,MCASP interface clock divided by 32,MCASP interface clock divided by 64,MCASP interface clock divided by 128,MCASP interface clock divided by 256 0x9 to,?,?,?,?,?,?,Reserved" group.long 0x50++0x03 line.long 0x00 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the MCASP" bitfld.long 0x00 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x00 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" newline bitfld.long 0x00 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0xAC++0x03 line.long 0x00 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" abitfld.long 0x00 7.--15. "XMOD,Transmit frame-sync mode select bits" "0x000=Burst mode,0x001=Reserved,0x002=2-slot TDM mode (I2S transmit mode),0x020=3-slot TDM to 32-slot TDM mode,0x17F=Reserved,0x180=384-slot DIT mode All other: Reserved" bitfld.long 0x00 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" newline bitfld.long 0x00 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x00 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" group.long 0xA8++0x03 line.long 0x00 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x00 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x00 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" newline bitfld.long 0x00 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x00 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" newline bitfld.long 0x00 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" bitfld.long 0x00 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" newline bitfld.long 0x00 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" group.long 0xA4++0x03 line.long 0x00 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" group.long 0xC0++0x03 line.long 0x00 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the MCASP logic has priority and the flag remains set" bitfld.long 0x00 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x00 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" newline bitfld.long 0x00 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x00 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" newline bitfld.long 0x00 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" rbitfld.long 0x00 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" newline bitfld.long 0x00 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x00 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" newline bitfld.long 0x00 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" group.long 0xB8++0x03 line.long 0x00 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" rgroup.long 0xC4++0x03 line.long 0x00 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x00 0.--8. 1. "XSLOTCNT,Current transmit time slot count" group.long 0xCC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x00 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x00 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x00 0.--1. "IDLE_MODE," "?,No-idle mode,Smart-idle mode - default..,Reserved" width 0x0B tree.end tree.end tree "Multichannel_Serial_Peripheral_Interface" repeat 4. (list 1. 2. 3. 4. )(list ad:0x48098000 ad:0x4809A000 ad:0x480B8000 ad:0x480BA000 ) tree "McSPI$1" base $2 tree "Channel_0" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see Transfer Format)" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see Transfer Format)" "PHA_0,PHA_1" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x" bitfld.long 0x00 6. "RXFFF,Channel x FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel x FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel x FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel x FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel x end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel x transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel x receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" tree.end tree "Channel_1" group.long 0x140++0x03 line.long 0x00 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see Transfer Format)" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see Transfer Format)" "PHA_0,PHA_1" group.long 0x148++0x03 line.long 0x00 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x" bitfld.long 0x00 6. "RXFFF,Channel x FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel x FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel x FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel x FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel x end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel x transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel x receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" tree.end tree "Channel_2" group.long 0x154++0x03 line.long 0x00 "MCSPI_CHxCONF_2,This register is dedicated to the configuration of the channel x" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see Transfer Format)" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see Transfer Format)" "PHA_0,PHA_1" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CHxCTRL_2,This register is dedicated to enable channel x" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CHxSTAT_2,This register provides status information about transmitter and receiver registers of channel x" bitfld.long 0x00 6. "RXFFF,Channel x FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel x FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel x FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel x FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel x end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel x transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel x receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RXx_2,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x160++0x03 line.long 0x00 "MCSPI_TXx_2,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" tree.end tree "Channel_3" group.long 0x168++0x03 line.long 0x00 "MCSPI_CHxCONF_3,This register is dedicated to the configuration of the channel x" bitfld.long 0x00 29. "CLKG,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see Transfer Format)" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see Transfer Format)" "PHA_0,PHA_1" group.long 0x170++0x03 line.long 0x00 "MCSPI_CHxCTRL_3,This register is dedicated to enable channel x" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CHxSTAT_3,This register provides status information about transmitter and receiver registers of channel x" bitfld.long 0x00 6. "RXFFF,Channel x FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel x FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel x FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel x FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel x end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel x transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel x receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RXx_3,This register contains a single SPI word for channel x received through the serial link. whatever SPI word length is" group.long 0x174++0x03 line.long 0x00 "MCSPI_TXx_3,This register contains a single SPI word for channel x to transmit on the serial link. whatever SPI word length is" tree.end rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit" group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the module's hardware configuration" bitfld.long 0x00 6. "RETMODE,Retention Mode" "Retention mode disabled,Retention mode enabled" bitfld.long 0x00 1.--5. "FFNBYTE,FIFO number of bytes parameter - FF16bytes" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0. "USEFIFO,Use of a FIFO enable" "USEFIFO_0_r,USEFIFO_1_r" rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,McSPI module revision identifier Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x00 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x00 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in theMCSPI_CHxCONF[22:21] SPIENSLV bits - IrqDisabled" "WKE_0,WKE_1" bitfld.long 0x00 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" newline bitfld.long 0x00 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" bitfld.long 0x00 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x00 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x00 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x00 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x00 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" newline bitfld.long 0x00 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x00 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" bitfld.long 0x00 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" newline bitfld.long 0x00 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x00 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" bitfld.long 0x00 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[31:16] WCNT" "EOW_0_r,EOW_1_w" bitfld.long 0x00 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the fieldMCSPI_CHxCONF[22:21] SPIENSLV - NoEvnt_r" "WKS_0_w,WKS_1_r" bitfld.long 0x00 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" newline bitfld.long 0x00 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" bitfld.long 0x00 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x00 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x00 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x00 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x00 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" newline bitfld.long 0x00 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x00 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" bitfld.long 0x00 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" newline bitfld.long 0x00 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x00 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" bitfld.long 0x00 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface" bitfld.long 0x00 8. "FDAA,FIFO DMA address 256-bit aligned This bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x00 7. "MOA,Multiple word interface access: this bit can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" bitfld.long 0x00 4.--6. "INITDLY,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" newline bitfld.long 0x00 3. "SYSTEM_TEST,Enables the system test mode - Off" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x00 2. "MS,Master/slave - Master" "MS_0,MS_1" bitfld.long 0x00 1. "PIN34,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin)" "PIN34_0,PIN34_1" newline bitfld.long 0x00 0. "SINGLE,Single channel/Multi Channel (master mode only) - Multi" "SINGLE_0,SINGLE_1" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the McSPI revision number" hexmask.long.byte 0x00 0.--7. 1. "REVISION,McSPI core revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" group.long 0x110++0x07 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period - None" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control - NoWakeUp" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - InProgress" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" bitfld.long 0x00 11. "SSB,Set status bit - Off" "SSB_0,SSB_1" bitfld.long 0x00 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" bitfld.long 0x00 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" newline bitfld.long 0x00 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x00 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" bitfld.long 0x00 6. "SPICLK,SPICLK line (signal data value) If [10] SPIENDIR = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "SPICLK_0,SPICLK_1" newline bitfld.long 0x00 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If [9] SPIDATDIR1 = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this bit" "SPIDAT_1_0,SPIDAT_1_1" bitfld.long 0x00 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If [8] SPIDATDIR0 = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this bit" "SPIDAT_0_0,SPIDAT_0_1" bitfld.long 0x00 3. "SPIEN_3,SPIEN[3] line (signal data value) If [10] SPIENDIR = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this bit" "SPIEN_3_0,SPIEN_3_1" newline bitfld.long 0x00 2. "SPIEN_2,SPIEN[2] line (signal data value) If [10] SPIENDIR = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this bit" "SPIEN_2_0,SPIEN_2_1" bitfld.long 0x00 1. "SPIEN_1,SPIEN[1] line (signal data value) If [10] SPIENDIR = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this bit" "SPIEN_1_0,SPIEN_1_1" bitfld.long 0x00 0. "SPIEN_0,SPIEN[0] line (signal data value) If [10] SPIENDIR = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this bit" "SPIEN_0_0,SPIEN_0_1" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in theMCSPI_CHxCONF[22:21] SPIENSLV bits - NoWakeUp" "WKEN_0,WKEN_1" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full This field holds the programmable almost-full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" width 0x0B tree.end repeat.end tree.end tree "Multimaster_High_Speed_I2C_Controller" repeat 5. (list 3. 1. 2. 4. 5. )(list ad:0x48060000 ad:0x48070000 ad:0x48072000 ad:0x4807A000 ad:0x4807C000 ) tree "I2C$1" base $2 rgroup.word 0x00++0x01 line.word 0x00 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features. bugs. and compatibility" rgroup.word 0x04++0x01 line.word 0x00 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features. bugs. and compatibility" group.word 0x10++0x01 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits - boothoff" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3" bitfld.word 0x00 3.--4. "IDLEMODE,Idle Mode selection bits - smartidle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.word 0x00 2. "ENAWAKEUP,Enable Wakeup control bit - disable" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.word 0x00 1. "SRST,SoftReset bit - nmode" "SRST_0,SRST_1" bitfld.word 0x00 0. "AUTOIDLE,Autoidle bit - disable" "AUTOIDLE_0,AUTOIDLE_1" group.word 0x20++0x01 line.word 0x00 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1" group.word 0x24++0x01 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1" rbitfld.word 0x00 12. "BB,Bus busy status" "BB_0_r,BB_1_r" newline bitfld.word 0x00 11. "ROVR,Receive overrun status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow status" "XUDF_0_r,XUDF_1_r" bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1" newline bitfld.word 0x00 8. "BF,Bus Free IRQ status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1" bitfld.word 0x00 6. "STC,Start Condition IRQ status" "STC_0,STC_1" newline bitfld.word 0x00 5. "GC,General call IRQ status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ status" "XRDY_0,XRDY_1" bitfld.word 0x00 3. "RRDY,Receive data ready IRQ status" "RRDY_0,RRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ status" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ status" "AL_0,AL_1" group.word 0x28++0x01 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x00 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1" rbitfld.word 0x00 12. "BB,Bus busy enabled status" "BB_0_r,BB_1_r" newline bitfld.word 0x00 11. "ROVR,Receive overrun enabled status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow enabled status" "XUDF_0_r,XUDF_1_r" bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1" newline bitfld.word 0x00 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1" bitfld.word 0x00 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1" newline bitfld.word 0x00 5. "GC,General call IRQ enabled status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ enabled status" "XRDY_0,XRDY_1" bitfld.word 0x00 3. "RRDY,Receive data ready IRQ enabled status" "RRDY_0,RRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ enabled status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ enabled status" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ enabled status" "AL_0,AL_1" group.word 0x2C++0x01 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable set" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable set" "RDR_IE_0,RDR_IE_1" bitfld.word 0x00 11. "ROVR,Receive overrun enable set.Read" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow enable set.Read" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable set" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable set" "BF_IE_0,BF_IE_1" newline bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable set" "AERR_IE_0,AERR_IE_1" bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable set" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable set" "GC_IE_0,GC_IE_1" newline bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable set" "XRDY_IE_0,XRDY_IE_1" bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable set" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable set" "ARDY_IE_0,ARDY_IE_1" newline bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable set" "NACK_IE_0,NACK_IE_1" bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable set" "AL_IE_0,AL_IE_1" group.word 0x30++0x01 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable clear" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable clear" "RDR_IE_0,RDR_IE_1" bitfld.word 0x00 11. "ROVR,Receive overrun enable clear.Read" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow enable clear.Read" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS_IE,Addressed as Slave interrupt enable clear" "AAS_IE_0,AAS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable clear" "BF_IE_0,BF_IE_1" newline bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable clear" "AERR_IE_0,AERR_IE_1" bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable clear" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable clear" "GC_IE_0,GC_IE_1" newline bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable clear" "XRDY_IE_0,XRDY_IE_1" bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable clear" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable clear" "ARDY_IE_0,ARDY_IE_1" newline bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable clear" "NACK_IE_0,NACK_IE_1" bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable clear" "AL_IE_0,AL_IE_1" group.word 0x34++0x01 line.word 0x00 "I2C_WE,I2C wakeup enable vector" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x38++0x01 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set" bitfld.word 0x00 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "DMARX_ENABLE_SET_0,DMARX_ENABLE_SET_1" group.word 0x3C++0x01 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set" bitfld.word 0x00 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "DMATX_ENABLE_SET_0,DMATX_ENABLE_SET_1" group.word 0x40++0x01 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear" bitfld.word 0x00 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "DMARX_ENABLE_CLEAR_0,DMARX_ENABLE_CLEAR_1" group.word 0x44++0x01 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear" bitfld.word 0x00 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "DMATX_ENABLE_CLEAR_0,DMATX_ENABLE_CLEAR_1" group.word 0x48++0x01 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x4C++0x01 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x90++0x01 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. "RDONE,Reset done bit - rstcomp" "RDONE_0_r,RDONE_1_r" group.word 0x94++0x01 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. "RDMA_EN,Receive DMA channel enable - disable" "RDMA_EN_0,RDMA_EN_1" bitfld.word 0x00 14. "RXFIFO_CLR,Receive FIFO clear - nmode" "RXFIFO_CLR_0,RXFIFO_CLR_1" bitfld.word 0x00 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.word 0x00 7. "XDMA_EN,Transmit DMA channel enable - disable" "XDMA_EN_0,XDMA_EN_1" bitfld.word 0x00 6. "TXFIFO_CLR,Transmit FIFO clear - nmode" "TXFIFO_CLR_0,TXFIFO_CLR_1" bitfld.word 0x00 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x01 line.word 0x00 "I2C_CNT,Data counter register" group.word 0x9C++0x01 line.word 0x00 "I2C_DATA,Data access register" hexmask.word.byte 0x00 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.word 0xA4++0x01 line.word 0x00 "I2C_CON,I2C configuration register" bitfld.word 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1" bitfld.word 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3" bitfld.word 0x00 11. "STB,Start byte mode (master mode only)" "STB_0,STB_1" newline bitfld.word 0x00 10. "MST,Master/slave mode" "MST_0,MST_1" bitfld.word 0x00 9. "TRX,Transmitter/Receiver mode (master mode only)" "TRX_0,TRX_1" bitfld.word 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1" newline bitfld.word 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1" bitfld.word 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1" bitfld.word 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1" newline bitfld.word 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1" bitfld.word 0x00 1. "STP,Stop condition (master mode only)" "STP_0,STP_1" bitfld.word 0x00 0. "STT,Start condition (master mode only)" "STT_0,STT_1" group.word 0xA8++0x01 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. "MCODE,Master Code" "MCODE_0,MCODE_1,MCODE_2,MCODE_3,MCODE_4,MCODE_5,MCODE_6,MCODE_7" hexmask.word 0x00 0.--9. 1. "OA,Own address" group.word 0xAC++0x01 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. "SA,Slave address" group.word 0xB0++0x01 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" abitfld.word 0x00 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256" group.word 0xB4++0x01 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.word.byte 0x00 8.--15. 1. "HSSCLL,High speed mode SCL low time - The value of the bit field is automatically increased by 7" hexmask.word.byte 0x00 0.--7. 1. "SCLL,Fast/standard mode SCL low time - The value of the bit field is automatically increased by 7" group.word 0xB8++0x01 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register" hexmask.word.byte 0x00 8.--15. 1. "HSSCLH,High speed mode SCL high time - The value of the bit field is automatically increased by 5" hexmask.word.byte 0x00 0.--7. 1. "SCLH,Fast/standard mode SCL high time - The value of the bit field is automatically increased by 5" group.word 0xBC++0x01 line.word 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.word 0x00 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1" bitfld.word 0x00 14. "FREE,Free running mode (on breakpoint) - stop" "FREE_0,FREE_1" bitfld.word 0x00 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3" newline bitfld.word 0x00 11. "SSB,Set all status bits inI2C_IRQSTATUS_RAW [14:0]" "SSB_0,SSB_1" rbitfld.word 0x00 8. "SCL_I_FUNC,SCL line input value (functional mode)" "SCL_I_FUNC_0_r,SCL_I_FUNC_1_r" rbitfld.word 0x00 7. "SCL_O_FUNC,SCL line output value (functional mode)" "SCL_O_FUNC_0_r,SCL_O_FUNC_1_r" newline rbitfld.word 0x00 6. "SDA_I_FUNC,SDA line input value (functional mode)" "SDA_I_FUNC_0_r,SDA_I_FUNC_1_r" rbitfld.word 0x00 5. "SDA_O_FUNC,SDA line output value (functional mode)" "SDA_O_FUNC_0_r,SDA_O_FUNC_1_r" rbitfld.word 0x00 3. "SCL_I,SCL line sense input value - sclih" "SCL_I_0_r,SCL_I_1_r" newline bitfld.word 0x00 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1" rbitfld.word 0x00 1. "SDA_I,SDA line sense input value" "SDA_I_0_r,SDA_I_1_r" bitfld.word 0x00 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1" rgroup.word 0xC0++0x01 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.word 0x00 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "FIFODEPTH_0_r,FIFODEPTH_1_r,FIFODEPTH_2_r,FIFODEPTH_3_r" bitfld.word 0x00 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x01 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. "OA1,Own address 1" group.word 0xC8++0x01 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. "OA2,Own address 2" group.word 0xCC++0x01 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. "OA3,Own address 3" rgroup.word 0xD0++0x01 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register" bitfld.word 0x00 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0_r,OA3_ACT_1_r" bitfld.word 0x00 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0_r,OA2_ACT_1_r" bitfld.word 0x00 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0_r,OA1_ACT_1_r" newline bitfld.word 0x00 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0_r,OA0_ACT_1_r" group.word 0xD4++0x01 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" bitfld.word 0x00 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1" bitfld.word 0x00 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1" bitfld.word 0x00 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1" newline bitfld.word 0x00 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1" width 0x0B tree.end repeat.end tree.end tree "On_Chip_Memory_OCM_Subsystem" repeat 3. (list 1. 2. 3. )(list ad:0x48804000 ad:0x4880A000 ad:0x48810000 ) tree "OCMC_RAM$1" base $2 group.long 0x200++0x03 line.long 0x00 "CFG_OCMC_CBUF_EN,CBUF mode enable register" bitfld.long 0x00 27. "CBUF_EN_11,CBUF 11 enable" "Disable,Enable" newline bitfld.long 0x00 26. "CBUF_EN_10,CBUF 10 enable" "Disable,Enable" newline bitfld.long 0x00 25. "CBUF_EN_9,CBUF 9 enable" "Disable,Enable" newline bitfld.long 0x00 24. "CBUF_EN_8,CBUF 8 enable" "Disable,Enable" newline bitfld.long 0x00 23. "CBUF_EN_7,CBUF 7 enable" "Disable,Enable" newline bitfld.long 0x00 22. "CBUF_EN_6,CBUF 6 enable" "Disable,Enable" newline bitfld.long 0x00 21. "CBUF_EN_5,CBUF 5 enable" "Disable,Enable" newline bitfld.long 0x00 20. "CBUF_EN_4,CBUF 4 enable" "Disable,Enable" newline bitfld.long 0x00 19. "CBUF_EN_3,CBUF 3 enable" "Disable,Enable" newline bitfld.long 0x00 18. "CBUF_EN_2,CBUF 2 enable" "Disable,Enable" newline bitfld.long 0x00 17. "CBUF_EN_1,CBUF 1 enable" "Disable,Enable" newline bitfld.long 0x00 16. "CBUF_EN_0,CBUF 0 enable" "Disable,Enable" newline bitfld.long 0x00 2. "NEW_FRAME_SEL,CBUF New Frame Event Definition Select" "New frame event flag is set when a VBUF access..,New frame event flag is set when a VBUF access.." newline bitfld.long 0x00 1. "CBUF_DEBUG_EN,CBUF Debug Enable Mode" "Default Normal mode,Debug mode" newline bitfld.long 0x00 0. "CBUF_MODE_EN,CBUF Mode Enable" "Disable all CBUF address translation,Enable CBUF address translation" group.long 0x208++0x03 line.long 0x00 "CFG_OCMC_CBUF_ERR_HANDLER," bitfld.long 0x00 8. "UNDERFLOW_LAST_CBUF_SLICE_DISABLE," "0,1" newline bitfld.long 0x00 6.--7. "OVERFLOW_CHECK_REENABLE_SEL,Overflow check re-enable selection" "Overflow check is disabled until next wtire to..,Overflow check is disabled until next write to..,Overflow check is disabled until next read from..,Overflow check is re-enabled immediately" newline bitfld.long 0x00 4.--5. "OVERFLOW_WRITE_HANDLER_SEL,Overflow write handler selection" "Writes disabled only on CBUF_overflow_wrap cases..,Writes disabled on all overflow cases until next..,Writes serviced with CBUF pointer updated even..,Reserved" newline bitfld.long 0x00 3. "UNDERFLOW_ERR_CHECK_EN,Underflow chek enable" "UNDERFLOW_ERR_CHECK_EN_0,UNDERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x00 2. "OVERFLOW_ERR_CHECK_EN,Overflow chek enable" "OVERFLOW_ERR_CHECK_EN_0,OVERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x00 1. "SHORT_FRAME_PREV_EOF_SEL," "0,1" newline bitfld.long 0x00 0. "SHORT_FRAME_DETECT_CHECK_EN,Short frame detection enable" "SHORT_FRAME_DETECT_CHECK_EN_0,SHORT_FRAME_DETECT_CHECK_EN_1" group.long 0x204++0x03 line.long 0x00 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic" bitfld.long 0x00 11. "CBUF_RESET_11,cbuf_reset_11" "0,1" newline bitfld.long 0x00 10. "CBUF_RESET_10,cbuf_reset_10" "0,1" newline bitfld.long 0x00 9. "CBUF_RESET_9,cbuf_reset_9" "0,1" newline bitfld.long 0x00 8. "CBUF_RESET_8,cbuf_reset_8" "0,1" newline bitfld.long 0x00 7. "CBUF_RESET_7,cbuf_reset_7" "0,1" newline bitfld.long 0x00 6. "CBUF_RESET_6,cbuf_reset_6" "0,1" newline bitfld.long 0x00 5. "CBUF_RESET_5,cbuf_reset_5" "0,1" newline bitfld.long 0x00 4. "CBUF_RESET_4,cbuf_reset_4" "0,1" newline bitfld.long 0x00 3. "CBUF_RESET_3,cbuf_reset_3" "0,1" newline bitfld.long 0x00 2. "CBUF_RESET_2,cbuf_reset_2" "0,1" newline bitfld.long 0x00 1. "CBUF_RESET_1,cbuf_reset_1" "0,1" newline bitfld.long 0x00 0. "CBUF_RESET_0,cbuf_reset_0" "0,1" group.long 0x80++0x03 line.long 0x00 "CFG_OCMC_ECC," bitfld.long 0x00 5. "CFG_ECC_OPT_NON_ECC_READ,Optimize read latency for non-ECC" "Disable,Enable" newline bitfld.long 0x00 4. "CFG_ECC_ERR_SRESP_EN,ECC non-correctable error SRESP enable" "Disable,Enable" newline bitfld.long 0x00 3. "CFG_ECC_SEC_AUTO_CORRECT,SEC error auto correction mode" "Disable,Enable (If the OCM.." newline bitfld.long 0x00 0.--2. "CFG_OCMC_MODE,OCM Controller memory access modes" "Non-ECC mode (data access),Non-ECC mode (code access),Full ECC enabled mode,Block ECC enabled mode 0x4-0x7,?..." group.long 0x8C++0x03 line.long 0x00 "CFG_OCMC_ECC_CLEAR_HIST," bitfld.long 0x00 3. "CLEAR_SEC_BIT_DISTR,Clear stored single error correction (SEC) bit distribution history" "Reserved (not used),Cleares the following registers" newline bitfld.long 0x00 2. "CLEAR_ADDR_ERR_CNT,Clear stored address error history" "Reserved (not used),Clears" newline bitfld.long 0x00 1. "CLEAR_DED_ERR_CNT,Clear stored double error detection (DED) history" "Reserved (not used),Clears" newline bitfld.long 0x00 0. "CLEAR_SEC_ERR_CNT,Clear stored single error correction history" "Reserved (not used),Clears" group.long 0x88++0x03 line.long 0x00 "CFG_OCMC_ECC_ERROR," bitfld.long 0x00 24. "CFG_DISCARD_DUP_ADDR,Do not save duplicate error address" "Save the duplicated addresses,Save only the unique addresses" newline bitfld.long 0x00 20.--23. "CFG_ADDR_ERR_CNT_MAX,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "CFG_DED_CNT_MAX,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. "CFG_SEC_CNT_MAX,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" group.long 0x84++0x03 line.long 0x00 "CFG_OCMC_ECC_MEM_BLK," hexmask.long.tbyte 0x00 0.--19. 1. "CFG_ECC_ENABLED_128K_BLK,ECC memory block enable bits" tree "Channel_0" group.long 0x24C++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_0," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x248++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_0," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x244++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_0," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x240++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_0," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x304++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_0," rgroup.long 0x300++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_0," tree.end tree "Channel_1" group.long 0x262++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_1," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x25E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_1," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x25A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_1," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x256++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_1," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x30C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_1," rgroup.long 0x308++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_1," tree.end tree "Channel_10" group.long 0x328++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_10," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x324++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_10," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x320++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_10," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x31C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_10," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x354++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_10," rgroup.long 0x350++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_10," tree.end tree "Channel_11" group.long 0x33E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_11," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x33A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_11," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x336++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_11," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x332++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_11," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x35C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_11," rgroup.long 0x358++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_11," tree.end tree "Channel_2" group.long 0x278++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_2," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x274++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_2," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x270++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_2," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x26C++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_2," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x314++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_2," rgroup.long 0x310++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_2," tree.end tree "Channel_3" group.long 0x28E++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_3," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x28A++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_3," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x286++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_3," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x282++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_3," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x31C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_3," rgroup.long 0x318++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_3," tree.end tree "Channel_4" group.long 0x2A4++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_4," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x2A0++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_4," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x29C++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_4," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x298++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_4," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x324++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_4," rgroup.long 0x320++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_4," tree.end tree "Channel_5" group.long 0x2BA++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_5," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x2B6++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_5," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x2B2++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_5," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x2AE++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_5," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x32C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_5," rgroup.long 0x328++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_5," tree.end tree "Channel_6" group.long 0x2D0++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_6," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x2CC++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_6," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x2C8++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_6," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x2C4++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_6," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x334++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_6," rgroup.long 0x330++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_6," tree.end tree "Channel_7" group.long 0x2E6++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_7," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x2E2++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_7," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x2DE++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_7," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x2DA++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_7," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x33C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_7," rgroup.long 0x338++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_7," tree.end tree "Channel_8" group.long 0x2FC++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_8," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x2F8++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_8," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x2F4++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_8," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x2F0++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_8," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x344++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_8," rgroup.long 0x340++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_8," tree.end tree "Channel_9" group.long 0x312++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_9," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x30E++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_9," hexmask.long.tbyte 0x00 4.--21. 1. "ADDR,SRAM start address for this CBUF - bits [21:4]" group.long 0x30A++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_9," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame end address for this CBUF - bits [23:4]" group.long 0x306++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_9," hexmask.long.tbyte 0x00 4.--23. 1. "ADDR,Virtual frame start address for this CBUF - bits [23:4]" rgroup.long 0x34C++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_9," rgroup.long 0x348++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_9," tree.end group.long 0x4C++0x03 line.long 0x00 "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x48++0x03 line.long 0x00 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x44++0x03 line.long 0x00 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x40++0x03 line.long 0x00 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x6C++0x03 line.long 0x00 "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x68++0x03 line.long 0x00 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x64++0x03 line.long 0x00 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" group.long 0x60++0x03 line.long 0x00 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" rgroup.long 0x360++0x03 line.long 0x00 "LAST_ILLEGAL_OCMC_ADDR," rgroup.long 0x00++0x03 line.long 0x00 "OCMC_ECC_PID," group.long 0x50++0x03 line.long 0x00 "OCMC_INTR0_EOI,This register contains the EOI vector" bitfld.long 0x00 0. "EOI_VECTOR," "0,1" group.long 0x70++0x03 line.long 0x00 "OCMC_INTR1_EOI,This register contains the EOI vector" bitfld.long 0x00 0. "EOI_VECTOR," "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration" bitfld.long 0x00 12.--16. "VBUF_ADDR_MSB,This bit field returns the MSB bit of the valid VBUF address range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 9. "MEM_CBUF_ENABLE,Indicates whether CBUF is supported or not" "MEM_CBUF_ENABLE_0,MEM_CBUF_ENABLE_1" newline bitfld.long 0x00 8. "MEM_ECC_ENABLE,Indicates whether ECC is supported or not" "MEM_ECC_ENABLE_0,MEM_ECC_ENABLE_1" newline bitfld.long 0x00 0.--4. "MEM_SIZE_128K_CNT,This bit field indicates how many 128KiB memory blocks are present in the SRAM" "?,One 128KiB memory block,Two 128KiB memory blocks,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,20 memory blocks of 128KiB,?..." group.long 0x04++0x07 line.long 0x00 "OCMC_SYSCONFIG_PM," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x04 "OCMC_SYSCONFIG_RST," bitfld.long 0x04 0. "SW_RST,Software reset of the OCM controller configuration and history logic (does not reset L4 interface) - NORMAL_OP" "SW_RST_0,SW_RST_1" rgroup.long 0x9C++0x03 line.long 0x00 "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" bitfld.long 0x00 18. "VALID,ADDRERR FIFO valid addres indication" "The ADDRERR FIFO is empty,There is a valid address in the ADDRERR FIFO" newline hexmask.long.tbyte 0x00 0.--17. 1. "ADDRESS_128BIT,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" group.long 0x224++0x07 line.long 0x00 "STATUS_CBUF_OVERFLOW_MID," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected in the middle of a frame" line.long 0x04 "STATUS_CBUF_OVERFLOW_WRAP," hexmask.long.word 0x04 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected during buffer switching" group.long 0x220++0x03 line.long 0x00 "STATUS_CBUF_RD_ADDR_SEQ_ERROR," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF read address is not incrementing in raster scan order" group.long 0x218++0x03 line.long 0x00 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,Indicates that the CBUF read address is out of the CBUF range" group.long 0x230++0x03 line.long 0x00 "STATUS_CBUF_SHORT_FRAME_DETECT," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF short frame detected" group.long 0x22C++0x03 line.long 0x00 "STATUS_CBUF_UNDERFLOW," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF underflow condition detected" group.long 0x21C++0x03 line.long 0x00 "STATUS_CBUF_VBUF_RD_START_ERROR," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF read is not from the base address at VBUF access start" group.long 0x214++0x03 line.long 0x00 "STATUS_CBUF_WR_ADDR_SEQ_ERROR," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,CBUF address is not incrementing in raster scan order" group.long 0x20C++0x07 line.long 0x00 "STATUS_CBUF_WR_OUT_OF_RANGE_ERR," hexmask.long.word 0x00 0.--11. 1. "CBUF_ERR,Indicates that the CBUF write address is out of the CBUF range" line.long 0x04 "STATUS_CBUF_WR_VBUF_START_ERR," hexmask.long.word 0x04 0.--11. 1. "CBUF_ERR,CBUF write is not to the base address at vbuf access start" rgroup.long 0x98++0x03 line.long 0x00 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" bitfld.long 0x00 18. "VALID,DED FIFO valid addres indication" "The DED FIFO is empty,There is a valid address in the DED FIFO" newline hexmask.long.tbyte 0x00 0.--17. 1. "ADDRESS_128BIT,DED error 128-bit memory address (Read from the DED error address trace fifo)" rgroup.long 0x90++0x03 line.long 0x00 "STATUS_ERROR_CNT,OCM Controller error status" bitfld.long 0x00 20.--23. "ADDR_ERROR_CNT,Counter for the address errors found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "DED_ERROR_CNT,Counter for the double error detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. "SEC_ERROR_CNT,Counter for the single errors occured" rgroup.long 0xA0++0x13 line.long 0x00 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" line.long 0x04 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" line.long 0x08 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" line.long 0x0C "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" line.long 0x10 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" abitfld.long 0x10 0.--7. "SEC_ECC_CODE_ERROR_FOUND,ECC Code (excluding the parity bit) error distribution [7:0]" "0x00=SEC error not found,0x01=SEC error found In the corresponding bit.." rgroup.long 0x94++0x03 line.long 0x00 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" bitfld.long 0x00 18. "VALID,SEC FIFO valid addres indication" "VALID_0,VALID_1" newline hexmask.long.tbyte 0x00 0.--17. 1. "ADDRESS_128BIT,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" width 0x0B tree.end repeat.end tree.end tree "PCIe_Controller" tree "PCIe_SS1_EP_CFG_DBICS" base ad:0x51000000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PM_STATE,Power Management Control and Status Register" "PM_STATE_0,PM_STATE_1,PM_STATE_2,PM_STATE_3" group.long 0x50++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_MSI_CAP,Message Signaled Interrupt Capability structure header" rbitfld.long 0x00 24. "PVM_EN,MSI Per Vector Masking (PVM) supported" "0,1" rbitfld.long 0x00 23. "MSI_64_EN,64-bit Address Capable (CS)" "0,1" newline bitfld.long 0x00 20.--22. "MME,Multiple Message Enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. "MMC,Multiple Message Capable (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "MSI_EN,MSI Enable" "0,1" hexmask.long.byte 0x00 8.--15. 1. "MSI_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,MSI Capability ID Read 0x05 MSI" line.long 0x04 "PCIECTRL_EP_DBICS_MSI_ADD_L32,PCIe memory space address of MSI write TLP request. lower 32 bits" hexmask.long 0x04 2.--31. 1. "ADDR,Lower 32-bit address (DWORD aligned)" line.long 0x08 "PCIECTRL_EP_DBICS_MSI_ADD_U32,PCIe memory space address of MSI write TLP request. upper 32 bits (used if MSI_64_EN = 1)" line.long 0x0C "PCIECTRL_EP_DBICS_MSI_DATA,Data of MSI write TLP request (modified for multiple vectors)" hexmask.long.word 0x0C 0.--15. 1. "DATA,MSI data" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline rbitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS2_EP_CFG_DBICS" base ad:0x51800000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PM_STATE,Power Management Control and Status Register" "PM_STATE_0,PM_STATE_1,PM_STATE_2,PM_STATE_3" group.long 0x50++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_MSI_CAP,Message Signaled Interrupt Capability structure header" rbitfld.long 0x00 24. "PVM_EN,MSI Per Vector Masking (PVM) supported" "0,1" rbitfld.long 0x00 23. "MSI_64_EN,64-bit Address Capable (CS)" "0,1" newline bitfld.long 0x00 20.--22. "MME,Multiple Message Enable" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--19. "MMC,Multiple Message Capable (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "MSI_EN,MSI Enable" "0,1" hexmask.long.byte 0x00 8.--15. 1. "MSI_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,MSI Capability ID Read 0x05 MSI" line.long 0x04 "PCIECTRL_EP_DBICS_MSI_ADD_L32,PCIe memory space address of MSI write TLP request. lower 32 bits" hexmask.long 0x04 2.--31. 1. "ADDR,Lower 32-bit address (DWORD aligned)" line.long 0x08 "PCIECTRL_EP_DBICS_MSI_ADD_U32,PCIe memory space address of MSI write TLP request. upper 32 bits (used if MSI_64_EN = 1)" line.long 0x0C "PCIECTRL_EP_DBICS_MSI_DATA,Data of MSI write TLP request (modified for multiple vectors)" hexmask.long.word 0x0C 0.--15. 1. "DATA,MSI data" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline rbitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS1_EP_CFG_DBICS2" base ad:0x51001000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x18 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x18 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode. contains the upper bits of BAR2 mask" hexmask.long 0x1C 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x1C 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x20 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x20 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode. contains the upper bits of BAR4 mask" hexmask.long 0x24 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x24 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS2_EP_CFG_DBICS2" base ad:0x51801000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x18 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x18 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode. contains the upper bits of BAR2 mask" hexmask.long 0x1C 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x1C 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x20 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x20 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode. contains the upper bits of BAR4 mask" hexmask.long 0x24 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x24 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS1_EP_CFG_PCIe" base ad:0x20000000 rgroup.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS)" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x14 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x18 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x1C "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x20 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x24 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x28 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (that is programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" rbitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" rgroup.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." bitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline bitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline bitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),?,8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" rbitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS2_EP_CFG_PCIe" base ad:0x30000000 rgroup.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline abitfld.long 0x0C 16.--22. "HEAD_TYP,Header Type" "0x00=EP header,0x01=RC header" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS)" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x14 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x18 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x1C "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x20 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline rbitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x24 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline rbitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 Bit,?,64 Bit,?..." newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "BAR type is Memory,BAR type is I/O" line.long 0x28 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (that is programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "from D0 Bit,from D1 Bit,from D2 Bit,from D3hot Bit,from D3cold (if Vaux present),?..." bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" rbitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" rgroup.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "PCIe endpoint,Legacy PCIe endpoint,?..." bitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline bitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline bitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),?,8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" rbitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "64 Byte,128 Byte" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PCIe_SS1_PL_CONF" base ad:0x51000700 tree "Channel_0" group.long 0x128++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_1" group.long 0x134++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_1,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_1,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_1,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_2" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_2,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_2,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_2,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_3" group.long 0x14C++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_3,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_3,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_3,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_4" group.long 0x158++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_4,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_4,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_4,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_5" group.long 0x164++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_5,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_5,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_5,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_6" group.long 0x170++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_6,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_6,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_6,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_7" group.long 0x17C++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_7,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_7,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_7,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end group.long 0x0C++0x03 line.long 0x00 "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" bitfld.long 0x00 30. "L1_ENTR_WO_L0S,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" bitfld.long 0x00 27.--29. "L1_ENTR_LAT,L1 Entrance Latency" "1 uS,2 uS,4 uS,8 uS,16 uS,32 uS,64 uS,64 uS.." newline bitfld.long 0x00 24.--26. "L0S_ENTR_LAT,L0s Entrance Latency; Values correspond to" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. "COMMOM_CLK_N_FTS,Alternative N_FTS value for common clock mode" newline hexmask.long.byte 0x00 8.--15. 1. "N_FTS,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported and may cause LTSSM to go into Recovery upon L0s exit" hexmask.long.byte 0x00 0.--7. 1. "ACK_FREQ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" group.long 0x1D0++0x07 line.long 0x00 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x00 3. "RESET_TIMEOUT_ERR_MAP,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" bitfld.long 0x00 2. "NO_VID_ERR_MAP,Vendor ID Non-existent Slave Error Response Mapping" "0,1" newline bitfld.long 0x00 1. "DBI_ERR_MAP,DIF Slave Error Response Mapping" "0,1" bitfld.long 0x00 0. "SLAVE_ERR_MAP,Global Slave Error Response Mapping" "0,1" line.long 0x04 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" bitfld.long 0x04 8. "FLUSH_EN,Enable flush" "0,1" hexmask.long.byte 0x04 0.--7. 1. "TIMEOUT_VALUE,Timeout Value (ms)" group.long 0x1BC++0x03 line.long 0x00 "PCIECTRL_PL_DBI_RO_WR_EN,DIF Read-Only register Write Enable (Sticky)" bitfld.long 0x00 0. "CX_DBI_RO_WR_EN,Control the writability over DIF of certain configuration fields that are RO over the PCIe wire - WRDIS" "CX_DBI_RO_WR_EN_0,CX_DBI_RO_WR_EN_1" group.long 0x20++0x03 line.long 0x00 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" group.long 0x200++0x0B line.long 0x00 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible" bitfld.long 0x00 31. "REGION_DIRECTION,- OUTBOUND" "REGION_DIRECTION_0,REGION_DIRECTION_1" bitfld.long 0x00 0.--3. "REGION_INDEX,Outbound region from 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x04 20.--24. "FUNCTION_NUMBER,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--17. "AT,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" newline bitfld.long 0x04 9.--10. "ATTR,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" bitfld.long 0x04 8. "TD,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" newline bitfld.long 0x04 5.--7. "TC,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "TYPE,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" bitfld.long 0x08 31. "REGION_ENABLE,Enable AT for this region" "0,1" bitfld.long 0x08 30. "MATCH_MODE,Sets inbound TLP match mode depending on TYPE - _0" "MATCH_MODE_0,MATCH_MODE_1" newline bitfld.long 0x08 29. "INVERT_MODE,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x08 28. "CFG_SHIFT_MODE,Enable the shifting of CFG CID (BDF) incoming and outgoing TLP; CFG get mapped to a contiguous" "0,1" newline bitfld.long 0x08 27. "FUZZY_TYPE_MATCH_MODE,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x08 24.--25. "RESPONSE_CODE,Override HW-generated completion status when responding inbound TLP" "No override use HW-generated CS,Unsupported Request,Completer Abort,?..." newline bitfld.long 0x08 21. "MESSAGE_CODE_MATCH_ENABLE,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x08 20. "VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE,VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" "0,1" newline bitfld.long 0x08 19. "FUNCTION_NUMBER_MATCH_ENABLE,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x08 18. "AT_MATCH_ENABLE,Enable AT match criteria on inbound TLP ATS not SUPPORTED: DO not USE" "0,1" newline bitfld.long 0x08 16. "ATTR_MATCH_ENABLE,Enable ATTR match criteria on inbound TLP" "0,1" bitfld.long 0x08 15. "TD_MATCH_ENABLE,Enable TD match criteria on inbound TLP" "0,1" newline bitfld.long 0x08 14. "TC_MATCH_ENABLE,Enable TC match criteria on inbound TLP" "0,1" bitfld.long 0x08 8.--10. "BAR_NUMBER,BAR number for mayching with incoming MEM I/O TLP (if Match_Mode = 1)" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x08 0.--7. 1. "MESSAGECODE,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" rgroup.long 0x220++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" group.long 0x214++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LIMIT," hexmask.long.word 0x00 0.--11. 1. "ONES," group.long 0x20C++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LOWER_BASE," hexmask.long.word 0x00 0.--11. 1. "ZERO," group.long 0x218++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LOWER_TARGET," hexmask.long.word 0x00 0.--11. 1. "ZERO," group.long 0x210++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" group.long 0x21C++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" group.long 0x00++0x03 line.long 0x00 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. "REPLAY_TIME_LIMIT,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core.." hexmask.long.word 0x00 0.--15. 1. "ACK_LATENCY_TIME_LIMIT,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core base frequency of the device PCIe core corresponding to 250 MHz for.." group.long 0x14++0x03 line.long 0x00 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" bitfld.long 0x00 31. "DIS_L2L_SKEW,Disable Lane-to-Lane Deskew" "0,1" bitfld.long 0x00 25. "ACKNAK_DIS,Ack/Nak Disable" "0,1" newline bitfld.long 0x00 24. "FC_DIS,Flow Control Disable" "0,1" hexmask.long.tbyte 0x00 0.--23. 1. "LANE_SKEW,Insert Lane Skew for Transmit" group.long 0x120++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" group.long 0x188++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" group.long 0x124++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" group.long 0x24++0x03 line.long 0x00 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x00 0. "EN_OBNP_SUBREQ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests" "0,1" group.long 0x114++0x03 line.long 0x00 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" rgroup.long 0x110++0x03 line.long 0x00 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" group.long 0x1B8++0x03 line.long 0x00 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" bitfld.long 0x00 31. "LOOPBACK_EN,PIPE Loopback Enable" "0,1" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" rbitfld.long 0x00 23. "CROSSLINK_ACT,Crosslink Active" "0,1" bitfld.long 0x00 22. "CROSSLINK_EN,Crosslink Enable" "0,1" newline bitfld.long 0x00 16.--21. "LINK_MODE,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode" "?,_1x,?,_2x,?,?,?,_4x,?..." bitfld.long 0x00 7. "FAST_LINK,Fast Link Mode" "0,1" newline bitfld.long 0x00 5. "DL_EN,DLL Link Enable" "0,1" bitfld.long 0x00 3. "RESET_ASSERT,Reset Assert" "0,1" newline bitfld.long 0x00 2. "LB_EN,Loopback Enable" "0,1" bitfld.long 0x00 1. "SCRAMBLE_DIS,Scramble Disable" "0,1" newline bitfld.long 0x00 0. "VEN_DLLP_REQ,Vendor Specific DLLP transmit Request" "0,1" group.long 0x08++0x03 line.long 0x00 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x00 24.--31. 1. "LOW_POWER_ENTR_CNT,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for.." bitfld.long 0x00 16.--21. "FORCED_LINK_COMMAND,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. "FORCE_LINK,Forces the LTSSM state and the Link command specified in this register; Self-clearing - FORCE" "?,FORCE_LINK_1" bitfld.long 0x00 8.--11. "FORCED_LTSSM_STATE,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "LINK_NUM,Link Number; Not used for Endpoint" group.long 0x3C++0x03 line.long 0x00 "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x00 31. "FC_LATENCY_OVR_EN,FC Latency Timer Override Enable" "0,1" hexmask.long.word 0x00 16.--28. 1. "FC_LATENCY_OVR,FC Latency Timer Override Value" newline rbitfld.long 0x00 2. "RCVQ_not_EMPTY,Received Queue Not Empty" "0,1" rbitfld.long 0x00 1. "RTYB_not_EMPTY,Transmit Retry Buffer Not Empty" "0,1" newline rbitfld.long 0x00 0. "CRDT_not_RTRN,Received TLP FC Credits Not Returned" "0,1" group.long 0x18++0x07 line.long 0x00 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" bitfld.long 0x00 19.--23. "ACK_LATENCY_INC,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--18. "REPLAY_ADJ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_FUNC,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)" line.long 0x04 "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x04 16.--31. 1. "FLT_MSK_1,Mask RADM Filtering and Error Handling Rules: Mask 1" bitfld.long 0x04 15. "DIS_FC_TIM,Disable FC Watchdog Timer" "0,1" newline hexmask.long.word 0x04 0.--10. 1. "SKP_INT,SKP Interval Value minus one PIPE clock cycles" rgroup.long 0x38++0x03 line.long 0x00 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "CPLH_CRDT,Transmit Completion Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "CPLD_CRDT,Transmit Completion Data FC Credits" rgroup.long 0x34++0x03 line.long 0x00 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "NPH_CRDT,Transmit Non-Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "NPD_CRDT,Transmit Non-Posted Data FC Credits" rgroup.long 0x30++0x03 line.long 0x00 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "PH_CRDT,Transmit Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "PD_CRDT,Transmit Posted Data FC Credits" group.long 0x50++0x03 line.long 0x00 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" bitfld.long 0x00 21.--23. "CPL_QMODE,VC0 Completion TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS,?..." hexmask.long.byte 0x00 12.--19. 1. "CPL_HCRD,VC0 Completion Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "CPL_DCRD,VC0 Completion Data Credits" group.long 0x4C++0x03 line.long 0x00 "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" bitfld.long 0x00 21.--23. "NP_QMODE,VC0 Non-Poster TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS Others: Reserved,?..." hexmask.long.byte 0x00 12.--19. 1. "NP_HCRD,VC0 Non-Posted Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "NP_DCRD,VC0 Non-Posted Data Credits" group.long 0x48++0x03 line.long 0x00 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" bitfld.long 0x00 31. "STRICT_VC_PRIORITY,VC Ordering for Receive Queues - ROUND_ROBIN" "STRICT_VC_PRIORITY_0,STRICT_VC_PRIORITY_1" bitfld.long 0x00 30. "ORDERING_RULES,VC0 TLP Type Ordering Rules - STRICT" "ORDERING_RULES_0,ORDERING_RULES_1" newline bitfld.long 0x00 21.--23. "P_QMODE,VC0 Poster TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS Others: Reserved,?..." hexmask.long.byte 0x00 12.--19. 1. "P_HCRD,VC0 Posted Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "P_DCRD,VC0 Posted Data Credits" rgroup.long 0x40++0x07 line.long 0x00 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x00 24.--31. 1. "WRR_VC3,WRR Weight for VC3" hexmask.long.byte 0x00 16.--23. 1. "WRR_VC2,WRR Weight for VC2" newline hexmask.long.byte 0x00 8.--15. 1. "WRR_VC1,WRR Weight for VC1" hexmask.long.byte 0x00 0.--7. 1. "WRR_VC0,WRR Weight for VC0" line.long 0x04 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x04 24.--31. 1. "WRR_VC7,WRR Weight for VC7" hexmask.long.byte 0x04 16.--23. 1. "WRR_VC6,WRR Weight for VC6" newline hexmask.long.byte 0x04 8.--15. 1. "WRR_VC5,WRR Weight for VC5" hexmask.long.byte 0x04 0.--7. 1. "WRR_VC4,WRR Weight for VC4" group.long 0x04++0x03 line.long 0x00 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" group.long 0x10C++0x03 line.long 0x00 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" bitfld.long 0x00 20. "CFG_UP_SEL_DEEMPH,Used to set the de-emphasis level for Upstream Ports" "0,1" bitfld.long 0x00 19. "CFG_TX_COMPLIANCE_RCV,Config Tx Compliance Receive Bit" "0,1" newline bitfld.long 0x00 18. "CFG_PHY_TXSWING,Config PHY Tx Swing" "0,1" bitfld.long 0x00 17. "CFG_DIRECTED_SPEED_CHANGE,Directed Speed Change" "0,1" newline hexmask.long.word 0x00 8.--16. 1. "CFG_LANE_EN,Predetermined Number of Lanes" hexmask.long.byte 0x00 0.--7. 1. "CFG_Gen2_N_FTS,Number of Fast Training Sequences" width 0x0B tree.end tree "PCIe_SS2_PL_CONF" base ad:0x51800700 tree "Channel_0" group.long 0x128++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_1" group.long 0x134++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_1,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_1,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_1,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_2" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_2,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_2,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_2,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_3" group.long 0x14C++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_3,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_3,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_3,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_4" group.long 0x158++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_4,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_4,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_4,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_5" group.long 0x164++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_5,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_5,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_5,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_6" group.long 0x170++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_6,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_6,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_6,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end tree "Channel_7" group.long 0x17C++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_7,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_7,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_7,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end group.long 0x0C++0x03 line.long 0x00 "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" bitfld.long 0x00 30. "L1_ENTR_WO_L0S,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" bitfld.long 0x00 27.--29. "L1_ENTR_LAT,L1 Entrance Latency" "1 uS,2 uS,4 uS,8 uS,16 uS,32 uS,64 uS,64 uS.." newline bitfld.long 0x00 24.--26. "L0S_ENTR_LAT,L0s Entrance Latency; Values correspond to" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. "COMMOM_CLK_N_FTS,Alternative N_FTS value for common clock mode" newline hexmask.long.byte 0x00 8.--15. 1. "N_FTS,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported and may cause LTSSM to go into Recovery upon L0s exit" hexmask.long.byte 0x00 0.--7. 1. "ACK_FREQ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" group.long 0x1D0++0x07 line.long 0x00 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x00 3. "RESET_TIMEOUT_ERR_MAP,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" bitfld.long 0x00 2. "NO_VID_ERR_MAP,Vendor ID Non-existent Slave Error Response Mapping" "0,1" newline bitfld.long 0x00 1. "DBI_ERR_MAP,DIF Slave Error Response Mapping" "0,1" bitfld.long 0x00 0. "SLAVE_ERR_MAP,Global Slave Error Response Mapping" "0,1" line.long 0x04 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" bitfld.long 0x04 8. "FLUSH_EN,Enable flush" "0,1" hexmask.long.byte 0x04 0.--7. 1. "TIMEOUT_VALUE,Timeout Value (ms)" group.long 0x1BC++0x03 line.long 0x00 "PCIECTRL_PL_DBI_RO_WR_EN,DIF Read-Only register Write Enable (Sticky)" bitfld.long 0x00 0. "CX_DBI_RO_WR_EN,Control the writability over DIF of certain configuration fields that are RO over the PCIe wire - WRDIS" "CX_DBI_RO_WR_EN_0,CX_DBI_RO_WR_EN_1" group.long 0x20++0x03 line.long 0x00 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" group.long 0x200++0x0B line.long 0x00 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible" bitfld.long 0x00 31. "REGION_DIRECTION,- OUTBOUND" "REGION_DIRECTION_0,REGION_DIRECTION_1" bitfld.long 0x00 0.--3. "REGION_INDEX,Outbound region from 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x04 20.--24. "FUNCTION_NUMBER,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--17. "AT,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" newline bitfld.long 0x04 9.--10. "ATTR,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" bitfld.long 0x04 8. "TD,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" newline bitfld.long 0x04 5.--7. "TC,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "TYPE,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" bitfld.long 0x08 31. "REGION_ENABLE,Enable AT for this region" "0,1" bitfld.long 0x08 30. "MATCH_MODE,Sets inbound TLP match mode depending on TYPE - _0" "MATCH_MODE_0,MATCH_MODE_1" newline bitfld.long 0x08 29. "INVERT_MODE,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x08 28. "CFG_SHIFT_MODE,Enable the shifting of CFG CID (BDF) incoming and outgoing TLP; CFG get mapped to a contiguous" "0,1" newline bitfld.long 0x08 27. "FUZZY_TYPE_MATCH_MODE,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x08 24.--25. "RESPONSE_CODE,Override HW-generated completion status when responding inbound TLP" "No override use HW-generated CS,Unsupported Request,Completer Abort,?..." newline bitfld.long 0x08 21. "MESSAGE_CODE_MATCH_ENABLE,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x08 20. "VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE,VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" "0,1" newline bitfld.long 0x08 19. "FUNCTION_NUMBER_MATCH_ENABLE,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x08 18. "AT_MATCH_ENABLE,Enable AT match criteria on inbound TLP ATS not SUPPORTED: DO not USE" "0,1" newline bitfld.long 0x08 16. "ATTR_MATCH_ENABLE,Enable ATTR match criteria on inbound TLP" "0,1" bitfld.long 0x08 15. "TD_MATCH_ENABLE,Enable TD match criteria on inbound TLP" "0,1" newline bitfld.long 0x08 14. "TC_MATCH_ENABLE,Enable TC match criteria on inbound TLP" "0,1" bitfld.long 0x08 8.--10. "BAR_NUMBER,BAR number for mayching with incoming MEM I/O TLP (if Match_Mode = 1)" "BAR0,BAR1,BAR2,BAR3,BAR4,BAR5,ROM,?..." newline hexmask.long.byte 0x08 0.--7. 1. "MESSAGECODE,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" rgroup.long 0x220++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" group.long 0x214++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LIMIT," hexmask.long.word 0x00 0.--11. 1. "ONES," group.long 0x20C++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LOWER_BASE," hexmask.long.word 0x00 0.--11. 1. "ZERO," group.long 0x218++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x00 12.--31. 1. "IATU_REG_LOWER_TARGET," hexmask.long.word 0x00 0.--11. 1. "ZERO," group.long 0x210++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" group.long 0x21C++0x03 line.long 0x00 "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" group.long 0x00++0x03 line.long 0x00 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. "REPLAY_TIME_LIMIT,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core.." hexmask.long.word 0x00 0.--15. 1. "ACK_LATENCY_TIME_LIMIT,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core base frequency of the device PCIe core corresponding to 250 MHz for.." group.long 0x14++0x03 line.long 0x00 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" bitfld.long 0x00 31. "DIS_L2L_SKEW,Disable Lane-to-Lane Deskew" "0,1" bitfld.long 0x00 25. "ACKNAK_DIS,Ack/Nak Disable" "0,1" newline bitfld.long 0x00 24. "FC_DIS,Flow Control Disable" "0,1" hexmask.long.tbyte 0x00 0.--23. 1. "LANE_SKEW,Insert Lane Skew for Transmit" group.long 0x120++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" group.long 0x188++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" group.long 0x124++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" group.long 0x24++0x03 line.long 0x00 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x00 0. "EN_OBNP_SUBREQ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests" "0,1" group.long 0x114++0x03 line.long 0x00 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" rgroup.long 0x110++0x03 line.long 0x00 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" group.long 0x1B8++0x03 line.long 0x00 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" bitfld.long 0x00 31. "LOOPBACK_EN,PIPE Loopback Enable" "0,1" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" rbitfld.long 0x00 23. "CROSSLINK_ACT,Crosslink Active" "0,1" bitfld.long 0x00 22. "CROSSLINK_EN,Crosslink Enable" "0,1" newline bitfld.long 0x00 16.--21. "LINK_MODE,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode" "?,_1x,?,_2x,?,?,?,_4x,?..." bitfld.long 0x00 7. "FAST_LINK,Fast Link Mode" "0,1" newline bitfld.long 0x00 5. "DL_EN,DLL Link Enable" "0,1" bitfld.long 0x00 3. "RESET_ASSERT,Reset Assert" "0,1" newline bitfld.long 0x00 2. "LB_EN,Loopback Enable" "0,1" bitfld.long 0x00 1. "SCRAMBLE_DIS,Scramble Disable" "0,1" newline bitfld.long 0x00 0. "VEN_DLLP_REQ,Vendor Specific DLLP transmit Request" "0,1" group.long 0x08++0x03 line.long 0x00 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x00 24.--31. 1. "LOW_POWER_ENTR_CNT,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for.." bitfld.long 0x00 16.--21. "FORCED_LINK_COMMAND,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15. "FORCE_LINK,Forces the LTSSM state and the Link command specified in this register; Self-clearing - FORCE" "?,FORCE_LINK_1" bitfld.long 0x00 8.--11. "FORCED_LTSSM_STATE,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "LINK_NUM,Link Number; Not used for Endpoint" group.long 0x3C++0x03 line.long 0x00 "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x00 31. "FC_LATENCY_OVR_EN,FC Latency Timer Override Enable" "0,1" hexmask.long.word 0x00 16.--28. 1. "FC_LATENCY_OVR,FC Latency Timer Override Value" newline rbitfld.long 0x00 2. "RCVQ_not_EMPTY,Received Queue Not Empty" "0,1" rbitfld.long 0x00 1. "RTYB_not_EMPTY,Transmit Retry Buffer Not Empty" "0,1" newline rbitfld.long 0x00 0. "CRDT_not_RTRN,Received TLP FC Credits Not Returned" "0,1" group.long 0x18++0x07 line.long 0x00 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" bitfld.long 0x00 19.--23. "ACK_LATENCY_INC,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--18. "REPLAY_ADJ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_FUNC,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)" line.long 0x04 "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x04 16.--31. 1. "FLT_MSK_1,Mask RADM Filtering and Error Handling Rules: Mask 1" bitfld.long 0x04 15. "DIS_FC_TIM,Disable FC Watchdog Timer" "0,1" newline hexmask.long.word 0x04 0.--10. 1. "SKP_INT,SKP Interval Value minus one PIPE clock cycles" rgroup.long 0x38++0x03 line.long 0x00 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "CPLH_CRDT,Transmit Completion Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "CPLD_CRDT,Transmit Completion Data FC Credits" rgroup.long 0x34++0x03 line.long 0x00 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "NPH_CRDT,Transmit Non-Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "NPD_CRDT,Transmit Non-Posted Data FC Credits" rgroup.long 0x30++0x03 line.long 0x00 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "PH_CRDT,Transmit Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "PD_CRDT,Transmit Posted Data FC Credits" group.long 0x50++0x03 line.long 0x00 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" bitfld.long 0x00 21.--23. "CPL_QMODE,VC0 Completion TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS,?..." hexmask.long.byte 0x00 12.--19. 1. "CPL_HCRD,VC0 Completion Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "CPL_DCRD,VC0 Completion Data Credits" group.long 0x4C++0x03 line.long 0x00 "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" bitfld.long 0x00 21.--23. "NP_QMODE,VC0 Non-Poster TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS Others: Reserved,?..." hexmask.long.byte 0x00 12.--19. 1. "NP_HCRD,VC0 Non-Posted Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "NP_DCRD,VC0 Non-Posted Data Credits" group.long 0x48++0x03 line.long 0x00 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" bitfld.long 0x00 31. "STRICT_VC_PRIORITY,VC Ordering for Receive Queues - ROUND_ROBIN" "STRICT_VC_PRIORITY_0,STRICT_VC_PRIORITY_1" bitfld.long 0x00 30. "ORDERING_RULES,VC0 TLP Type Ordering Rules - STRICT" "ORDERING_RULES_0,ORDERING_RULES_1" newline bitfld.long 0x00 21.--23. "P_QMODE,VC0 Poster TLP Queue Mode" "?,STORE_AND_FORWARD,CUT_THROUGH,?,BYPASS Others: Reserved,?..." hexmask.long.byte 0x00 12.--19. 1. "P_HCRD,VC0 Posted Header Credits" newline hexmask.long.word 0x00 0.--11. 1. "P_DCRD,VC0 Posted Data Credits" rgroup.long 0x40++0x07 line.long 0x00 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x00 24.--31. 1. "WRR_VC3,WRR Weight for VC3" hexmask.long.byte 0x00 16.--23. 1. "WRR_VC2,WRR Weight for VC2" newline hexmask.long.byte 0x00 8.--15. 1. "WRR_VC1,WRR Weight for VC1" hexmask.long.byte 0x00 0.--7. 1. "WRR_VC0,WRR Weight for VC0" line.long 0x04 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x04 24.--31. 1. "WRR_VC7,WRR Weight for VC7" hexmask.long.byte 0x04 16.--23. 1. "WRR_VC6,WRR Weight for VC6" newline hexmask.long.byte 0x04 8.--15. 1. "WRR_VC5,WRR Weight for VC5" hexmask.long.byte 0x04 0.--7. 1. "WRR_VC4,WRR Weight for VC4" group.long 0x04++0x03 line.long 0x00 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" group.long 0x10C++0x03 line.long 0x00 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" bitfld.long 0x00 20. "CFG_UP_SEL_DEEMPH,Used to set the de-emphasis level for Upstream Ports" "0,1" bitfld.long 0x00 19. "CFG_TX_COMPLIANCE_RCV,Config Tx Compliance Receive Bit" "0,1" newline bitfld.long 0x00 18. "CFG_PHY_TXSWING,Config PHY Tx Swing" "0,1" bitfld.long 0x00 17. "CFG_DIRECTED_SPEED_CHANGE,Directed Speed Change" "0,1" newline hexmask.long.word 0x00 8.--16. 1. "CFG_LANE_EN,Predetermined Number of Lanes" hexmask.long.byte 0x00 0.--7. 1. "CFG_Gen2_N_FTS,Number of Fast Training Sequences" width 0x0B tree.end tree "PCIe_SS1_RC_CFG_DBICS" base ad:0x51000000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LS Bit of I/O address" "32 bit,?,64 bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x14 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 bit,?,64 bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x18 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" line.long 0x14 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." width 0x0B tree.end tree "PCIe_SS2_RC_CFG_DBICS" base ad:0x51800000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above)" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LS Bit of I/O address" "32 bit,?,64 bit,?..." newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x14 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below)" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "32 bit,?,64 bit,?..." newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x18 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" line.long 0x14 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." width 0x0B tree.end tree "PCIe_SS1_RC_CFG_DBICS2" base ad:0x51001000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask Reads like in CS mode" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "COMM_L1_EXIT_LAT,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "COMM_L0S_EXIT_LAT,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" line.long 0x14 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed: Read" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." width 0x0B tree.end tree "PCIe_SS2_RC_CFG_DBICS2" base ad:0x51801000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask Reads like in CS mode" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support not SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_not_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "COMM_L1_EXIT_LAT,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "COMM_L0S_EXIT_LAT,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." line.long 0x10 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "DISABLED,L0S_ENABLED,L1_ENABLED,L0S_AND_L1_ENABLED" line.long 0x14 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed: Read" "?,2.5 GT/s (Gen1),5 GT/s (Gen2),8 GT/s (Gen3),?..." width 0x0B tree.end tree "PCIe_SS1_TI_CONF" base ad:0x51002000 rgroup.long 0x00++0x03 line.long 0x00 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces" bitfld.long 0x00 16. "MCOHERENT_EN,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag" "MCOHERENT_EN_0,MCOHERENT_EN_1" newline bitfld.long 0x00 4.--5. "STANDBYMODE,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state" "Force-standby mode = Initiator is..,No-standby mode = initiator is unconditionally..,Smart-standby mode = initiator's standby state..,Smart-Standby wakeup-capable mode = initiator's.." newline bitfld.long 0x00 2.--3. "IDLEMODE,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state" "Force-idle mode = local target's idle state..,No-idle mode = local target never enters idle..,Smart-idle mode = local target's idle state..,Smart-idle wakeup-capable mode" group.long 0x18++0x03 line.long 0x00 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0.--3. "LINE_NUMBER,Write the IRQ line number to apply software EOI to it" "Read always returns zeros,software EOI on message-signalled (MSI)..,?..." group.long 0x20++0x1F line.long 0x00 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled" bitfld.long 0x00 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 12. "LINK_UP_EVT,Link-up state change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 11. "LINK_REQ_RST,Link Request Reset IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 10. "PM_PME,PM Power Management Event message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 5. "ERR_ECRC,ECRC Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 3. "ERR_COR,Correctable Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 1. "ERR_FATAL,Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 0. "ERR_SYS,System Error IRQ status" "No event pending,IRQ event pending" line.long 0x04 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled" bitfld.long 0x04 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 12. "LINK_UP_EVT,Link-up state change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 11. "LINK_REQ_RST,Link Request Reset IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 10. "PM_PME,PM Power Management Event message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 5. "ERR_ECRC,ECRC Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 3. "ERR_COR,Correctable Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 1. "ERR_FATAL,Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 0. "ERR_SYS,System Error IRQ status" "No event pending,IRQ event pending" line.long 0x08 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x08 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 0. "ERR_SYS_EN,System Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x0C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x0C 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 0. "ERR_SYS_EN,System Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x10 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled" bitfld.long 0x10 4. "MSI,Message Signaled Interrupt IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x10 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "No event pending,IRQ event pending" line.long 0x14 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled" bitfld.long 0x14 4. "MSI,Message Signaled Interrupt IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x14 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "No event pending,IRQ event pending" line.long 0x18 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x18 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 3. "INTD_EN,INTD IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 2. "INTC_EN,INTC IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 1. "INTB_EN,INTB IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 0. "INTA_EN,INTA IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x1C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x1C 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 3. "INTD_EN,INTD IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 2. "INTC_EN,INTC IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 1. "INTB_EN,INTB IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 0. "INTA_EN,INTA IRQ enable" "IRQ event is disabled,IRQ event is enabled" group.long 0x100++0x0F line.long 0x00 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x00 0.--3. "TYPE,PCIe device type including the contents of the PCI config space (Type-0 for EP Type-1 for RC); Apply fundamental reset after change; Do not change during core operation;" "PCIe endpoint (EP),Legacy PCIe endpoint (LEG_EP),?,?,Root Complex (RC) Other values: Reserved,?..." line.long 0x04 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions. including fundamental reset" hexmask.long.byte 0x04 21.--28. 1. "BUS_NUM,PCIe bus number" newline rbitfld.long 0x04 16.--20. "DEV_NUM,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 2.--7. "LTSSM_STATE,LTSSM state /substate implementation-specific for debug" "DETECT_QUIET,DETECT_ACT,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." newline bitfld.long 0x04 1. "APP_REQ_RETRY_EN,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "APP_REQ_RETRY_EN_0,APP_REQ_RETRY_EN_1" newline bitfld.long 0x04 0. "LTSSM_EN,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "LTSSM_EN_0,LTSSM_EN_1" line.long 0x08 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x08 11. "AUX_PWR_DET,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off" "AUX_PWR_DET_0,AUX_PWR_DET_1" newline bitfld.long 0x08 10. "REQ_EXIT_L1,Request to exit L1 state (to L0) - INACTIVE" "REQ_EXIT_L1_0,REQ_EXIT_L1_1" newline bitfld.long 0x08 9. "REQ_ENTR_L1,Request to transition to L1 state - INACTIVE" "REQ_ENTR_L1_0,REQ_ENTR_L1_1" newline bitfld.long 0x08 8. "L23_READY,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF/PME_TO_Ack handshake" "L23_READY_0,L23_READY_1" newline bitfld.long 0x08 1. "PM_PME,Transmits PM_PME wakeup message (EP mode only) - NOACTION" "PM_PME_0,PM_PME_1" newline bitfld.long 0x08 0. "PME_TURN_OFF,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready - NOACTION" "PME_TURN_OFF_0,PME_TURN_OFF_1" line.long 0x0C "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" rbitfld.long 0x0C 16. "LINK_UP,Link status from LTSSM - DOWN" "LINK_UP_0,LINK_UP_1" newline bitfld.long 0x0C 0. "REVERSE_LANES,Manual lane reversal control allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged - STRAIGHT" "REVERSE_LANES_0,REVERSE_LANES_1" group.long 0x124++0x0B line.long 0x00 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x00 0. "ASSERT_F0,INTx ASSERT for function 0" "INTx is inactive (has been deasserted),INTx is active (has been asserted)" line.long 0x04 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x04 0. "DEASSERT_F0,INTx DEASSERT for function 0" "INTx is inactive (has been deasserted),INTx is active (has been asserted)" line.long 0x08 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI. together with MSI capability descriptor already configured by remote RC" bitfld.long 0x08 7.--11. "MSI_VECTOR,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 4.--6. "MSI_TC,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 1.--3. "MSI_FUNC_NUM,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "MSI_REQ_GRANT,MSI transmit request (and grant status)" "MSI transmission request pending,Request MSI transmission" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x00 0.--5. "SEL,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector. depending on DEBUG_CFG.sel value" line.long 0x08 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x08 1. "INV_ECRC,Corrupt LSB of ECRC in the next packet then self-clears" "No CRC corruption pending,Request CRC corruption" newline bitfld.long 0x08 0. "INV_LCRC,Corrupts LSB of LCRC in the next packet then self-clears" "No CRC corruption pending,Request CRC corruption" width 0x0B tree.end tree "PCIe_SS2_TI_CONF" base ad:0x51802000 rgroup.long 0x00++0x03 line.long 0x00 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces" bitfld.long 0x00 16. "MCOHERENT_EN,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag" "MCOHERENT_EN_0,MCOHERENT_EN_1" newline bitfld.long 0x00 4.--5. "STANDBYMODE,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state" "Force-standby mode = Initiator is..,No-standby mode = initiator is unconditionally..,Smart-standby mode = initiator's standby state..,Smart-Standby wakeup-capable mode = initiator's.." newline bitfld.long 0x00 2.--3. "IDLEMODE,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state" "Force-idle mode = local target's idle state..,No-idle mode = local target never enters idle..,Smart-idle mode = local target's idle state..,Smart-idle wakeup-capable mode" group.long 0x18++0x03 line.long 0x00 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0.--3. "LINE_NUMBER,Write the IRQ line number to apply software EOI to it" "Read always returns zeros,software EOI on message-signalled (MSI)..,?..." group.long 0x20++0x1F line.long 0x00 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled" bitfld.long 0x00 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 12. "LINK_UP_EVT,Link-up state change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 11. "LINK_REQ_RST,Link Request Reset IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 10. "PM_PME,PM Power Management Event message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 5. "ERR_ECRC,ECRC Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 3. "ERR_COR,Correctable Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 1. "ERR_FATAL,Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x00 0. "ERR_SYS,System Error IRQ status" "No event pending,IRQ event pending" line.long 0x04 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled" bitfld.long 0x04 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 12. "LINK_UP_EVT,Link-up state change IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 11. "LINK_REQ_RST,Link Request Reset IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 10. "PM_PME,PM Power Management Event message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 5. "ERR_ECRC,ECRC Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 3. "ERR_COR,Correctable Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 1. "ERR_FATAL,Fatal Error message received IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x04 0. "ERR_SYS,System Error IRQ status" "No event pending,IRQ event pending" line.long 0x08 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x08 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x08 0. "ERR_SYS_EN,System Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x0C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x0C 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x0C 0. "ERR_SYS_EN,System Error IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x10 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled" bitfld.long 0x10 4. "MSI,Message Signaled Interrupt IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x10 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x10 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "No event pending,IRQ event pending" line.long 0x14 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled" bitfld.long 0x14 4. "MSI,Message Signaled Interrupt IRQ status" "No event pending,IRQ event pending" newline bitfld.long 0x14 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "No event pending,IRQ event pending" newline bitfld.long 0x14 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "No event pending,IRQ event pending" line.long 0x18 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x18 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 3. "INTD_EN,INTD IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 2. "INTC_EN,INTC IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 1. "INTB_EN,INTB IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x18 0. "INTA_EN,INTA IRQ enable" "IRQ event is disabled,IRQ event is enabled" line.long 0x1C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x1C 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 3. "INTD_EN,INTD IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 2. "INTC_EN,INTC IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 1. "INTB_EN,INTB IRQ enable" "IRQ event is disabled,IRQ event is enabled" newline bitfld.long 0x1C 0. "INTA_EN,INTA IRQ enable" "IRQ event is disabled,IRQ event is enabled" group.long 0x100++0x0F line.long 0x00 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x00 0.--3. "TYPE,PCIe device type including the contents of the PCI config space (Type-0 for EP Type-1 for RC); Apply fundamental reset after change; Do not change during core operation;" "PCIe endpoint (EP),Legacy PCIe endpoint (LEG_EP),?,?,Root Complex (RC) Other values: Reserved,?..." line.long 0x04 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions. including fundamental reset" hexmask.long.byte 0x04 21.--28. 1. "BUS_NUM,PCIe bus number" newline rbitfld.long 0x04 16.--20. "DEV_NUM,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 2.--7. "LTSSM_STATE,LTSSM state /substate implementation-specific for debug" "DETECT_QUIET,DETECT_ACT,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." newline bitfld.long 0x04 1. "APP_REQ_RETRY_EN,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "APP_REQ_RETRY_EN_0,APP_REQ_RETRY_EN_1" newline bitfld.long 0x04 0. "LTSSM_EN,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "LTSSM_EN_0,LTSSM_EN_1" line.long 0x08 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x08 11. "AUX_PWR_DET,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off" "AUX_PWR_DET_0,AUX_PWR_DET_1" newline bitfld.long 0x08 10. "REQ_EXIT_L1,Request to exit L1 state (to L0) - INACTIVE" "REQ_EXIT_L1_0,REQ_EXIT_L1_1" newline bitfld.long 0x08 9. "REQ_ENTR_L1,Request to transition to L1 state - INACTIVE" "REQ_ENTR_L1_0,REQ_ENTR_L1_1" newline bitfld.long 0x08 8. "L23_READY,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF/PME_TO_Ack handshake" "L23_READY_0,L23_READY_1" newline bitfld.long 0x08 1. "PM_PME,Transmits PM_PME wakeup message (EP mode only) - NOACTION" "PM_PME_0,PM_PME_1" newline bitfld.long 0x08 0. "PME_TURN_OFF,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready - NOACTION" "PME_TURN_OFF_0,PME_TURN_OFF_1" line.long 0x0C "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" rbitfld.long 0x0C 16. "LINK_UP,Link status from LTSSM - DOWN" "LINK_UP_0,LINK_UP_1" newline bitfld.long 0x0C 0. "REVERSE_LANES,Manual lane reversal control allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged - STRAIGHT" "REVERSE_LANES_0,REVERSE_LANES_1" group.long 0x124++0x0B line.long 0x00 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x00 0. "ASSERT_F0,INTx ASSERT for function 0" "INTx is inactive (has been deasserted),INTx is active (has been asserted)" line.long 0x04 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x04 0. "DEASSERT_F0,INTx DEASSERT for function 0" "INTx is inactive (has been deasserted),INTx is active (has been asserted)" line.long 0x08 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI. together with MSI capability descriptor already configured by remote RC" bitfld.long 0x08 7.--11. "MSI_VECTOR,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 4.--6. "MSI_TC,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 1.--3. "MSI_FUNC_NUM,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "MSI_REQ_GRANT,MSI transmit request (and grant status)" "MSI transmission request pending,Request MSI transmission" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x00 0.--5. "SEL,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector. depending on DEBUG_CFG.sel value" line.long 0x08 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x08 1. "INV_ECRC,Corrupt LSB of ECRC in the next packet then self-clears" "No CRC corruption pending,Request CRC corruption" newline bitfld.long 0x08 0. "INV_LCRC,Corrupts LSB of LCRC in the next packet then self-clears" "No CRC corruption pending,Request CRC corruption" width 0x0B tree.end tree.end tree "PCIe_PHY_Subsystem" repeat 2. (list 1. 3. )(list ad:0x4A080000 ad:0x4A090000 ) tree "OCP2SCP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,Revision register" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - ForceIdle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP interface clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,Reset done - Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Timing register" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end repeat.end tree "PCIe1_PHY_RX" base ad:0x4A094000 group.long 0x0C++0x03 line.long 0x00 "PCIEPHYRX_ANA_PROGRAMMABILITY_REG1,Programmability for different analog circuits in the PHY" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANATESTMODE,Programmability for Analog circuits in the PHY" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "PCIEPHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "PCIEPHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "PCIEPHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" newline bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate" "Full Rate,Half Rate,Quarter Rate,RESERVED" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" newline bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" newline bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "PCIEPHYRX_EQUALIZER_REG1,The module has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--10. "MEM_EQCTL," "?,Fully adaptive; FTC normal,Fully adaptive; FTC inverted,Hold equalizer state 01xx - Init equalizer to..,?,?,?,?,Partially adaptive; zero=1084 MHz,Partially adaptive; zero= 805 MHz,Partially adaptive; zero= 573 MHz,Partially adaptive; zero= 402 MHZ,Partially adaptive; zero= 304 MHz,Partially adaptive; zero= 216 MHz,Partially adaptive; zero= 156 MHz,Partially adaptive; zero= 135 MHz" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the MEM_EQLEV[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the MEM_EQFTC[4:0]" "0,1" width 0x0B tree.end tree "PCIe1_PHY_TX" base ad:0x4A094400 group.long 0x0C++0x07 line.long 0x00 "PCIEPHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" line.long 0x04 "PCIEPHYTX_DRIVER_DATA_CONFIG1,Configures the Driver data pattern" hexmask.long.byte 0x04 25.--31. 1. "MEM_EVEN_OUT_CONFIG0,Overriding the even TX data driver - to AFE" hexmask.long.byte 0x04 18.--24. 1. "MEM_ODD_OUT_CONFIG0,Overriding the odd TX data driver - to AFE" newline hexmask.long.byte 0x04 11.--17. 1. "MEM_EVEN_OUT_CONFIG1,Overriding the even TX data driver - to AFE" hexmask.long.byte 0x04 4.--10. 1. "MEM_ODD_OUT_CONFIG1,Overriding the odd TX data driver - to AFE" newline bitfld.long 0x04 2.--3. "MEM_HS_RATE_ANA_OVERRIDE,Override for the HS rate signal going to the AFE" "0,1,2,3" bitfld.long 0x04 1. "MEM_OVRD_HS_RATE_ANA_OVERRIDE,Pin override for the hs_rate_ana_override" "0,1" group.long 0x2C++0x07 line.long 0x00 "PCIEPHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" newline bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "?,generate 1010 pattern,?,?,Fixed 31 bit value from pattgen_preload_val,?..." line.long 0x04 "PCIEPHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" width 0x0B tree.end tree.end tree "PRCM" tree "CAM_PRM" base ad:0x4AE07000 group.long 0x00++0x07 line.long 0x00 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "VIP_BANK_ONSTATE,VIP_BANK memory state when domain is ON" "?,?,?,VIP_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "VIP_BANK_STATEST,VIP_BANK memory state status - MEM_OFF" "VIP_BANK_STATEST_0,VIP_BANK_STATEST_1,VIP_BANK_STATEST_2,VIP_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x17 line.long 0x00 "PM_CAM_VIP1_WKDEP,This register controls wakeup dependency based on VIP1 service requests" bitfld.long 0x00 9. "WKUPDEP_VIP1_EVE4,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_VIP1_EVE4_0,WKUPDEP_VIP1_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_VIP1_EVE3,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_VIP1_EVE3_0,WKUPDEP_VIP1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_VIP1_EVE2,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_EVE2_0,WKUPDEP_VIP1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_VIP1_EVE1,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_EVE1_0,WKUPDEP_VIP1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VIP1_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_DSP2_0,WKUPDEP_VIP1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_VIP1_IPU1,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_IPU1_0,WKUPDEP_VIP1_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_VIP1_DSP1,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_DSP1_0,WKUPDEP_VIP1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VIP1_IPU2,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP1_IPU2_0,WKUPDEP_VIP1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_VIP1_MPU,Wakeup dependency from VIP1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_MPU_0,WKUPDEP_VIP1_MPU_1" line.long 0x04 "RM_CAM_VIP1_CONTEXT,This register contains dedicated VIP1 context statuses" bitfld.long 0x04 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_CAM_VIP2_WKDEP,This register controls wakeup dependency based on VIP2 service requests" bitfld.long 0x08 9. "WKUPDEP_VIP2_EVE4,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_VIP2_EVE4_0,WKUPDEP_VIP2_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_VIP2_EVE3,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_VIP2_EVE3_0,WKUPDEP_VIP2_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_VIP2_EVE2,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_EVE2_0,WKUPDEP_VIP2_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_VIP2_EVE1,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_EVE1_0,WKUPDEP_VIP2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_VIP2_DSP2,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_DSP2_0,WKUPDEP_VIP2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_VIP2_IPU1,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_IPU1_0,WKUPDEP_VIP2_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_VIP2_DSP1,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_DSP1_0,WKUPDEP_VIP2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_VIP2_IPU2,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP2_IPU2_0,WKUPDEP_VIP2_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_VIP2_MPU,Wakeup dependency from VIP2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_MPU_0,WKUPDEP_VIP2_MPU_1" line.long 0x0C "RM_CAM_VIP2_CONTEXT,This register contains dedicated VIP2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_CAM_VIP3_WKDEP,This register controls wakeup dependency based on VIP3 service requests.VIP3 is not supported in this family of devices" bitfld.long 0x10 9. "WKUPDEP_VIP3_EVE4,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE4_0,WKUPDEP_VIP3_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_VIP3_EVE3,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE3_0,WKUPDEP_VIP3_EVE3_1" bitfld.long 0x10 7. "WKUPDEP_VIP3_EVE2,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE2_0,WKUPDEP_VIP3_EVE2_1" newline bitfld.long 0x10 6. "WKUPDEP_VIP3_EVE1,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE1_0,WKUPDEP_VIP3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_VIP3_DSP2,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_DSP2_0,WKUPDEP_VIP3_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_VIP3_IPU1,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_IPU1_0,WKUPDEP_VIP3_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_VIP3_DSP1,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_DSP1_0,WKUPDEP_VIP3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_VIP3_IPU2,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VIP3_IPU2_0,WKUPDEP_VIP3_IPU2_1" bitfld.long 0x10 0. "WKUPDEP_VIP3_MPU,Wakeup dependency from VIP3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_MPU_0,WKUPDEP_VIP3_MPU_1" line.long 0x14 "RM_CAM_VIP3_CONTEXT,This register contains dedicated VIP3 context statuses" bitfld.long 0x14 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "CKGEN_PRM" base ad:0x4AE06100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_SYSCLK1,Select the SYS CLK for SYSCLK1_32K_CLK" bitfld.long 0x00 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_6" "CLKSEL_0,CLKSEL_1" group.long 0x08++0x27 line.long 0x00 "CM_CLKSEL_WKUPAON,Control the functional clock source of WKUPAON. PRM and Smart Reflex functional clock" bitfld.long 0x00 0. "CLKSEL,Select the clock source for WKUPAON_ICLK clock - SEL_SYS_CLK" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_ABE_PLL_REF,Control the source of the reference clock for DPLL_ABE" bitfld.long 0x04 0. "CLKSEL,Select the source for the DPLL_ABE reference clock" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_SYS,ROM code sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK" bitfld.long 0x08 0.--2. "SYS_CLKSEL,System clock input selection" "SYS_CLKSEL_0,SYS_CLKSEL_1,SYS_CLKSEL_2,SYS_CLKSEL_3,SYS_CLKSEL_4,SYS_CLKSEL_5,SYS_CLKSEL_6,SYS_CLKSEL_7" line.long 0x0C "CM_CLKSEL_ABE_PLL_BYPAS,Control the source of the bypass clock for DPLL_ABE" bitfld.long 0x0C 0. "CLKSEL,Control the source of the bypass clock for DPLL_ABE - SEL_SYS_CLK" "CLKSEL_0,CLKSEL_1" line.long 0x10 "CM_CLKSEL_ABE_PLL_SYS,Control the source of the SYS clock for DPLL_ABE" bitfld.long 0x10 0. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1" line.long 0x14 "CM_CLKSEL_ABE_24M,Select the ABE_24M_FCLK for TIMERS subsystems" bitfld.long 0x14 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_8" "CLKSEL_0,CLKSEL_1" line.long 0x18 "CM_CLKSEL_ABE_SYS,Select the SYS CLK for IPU subsystems" bitfld.long 0x18 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x1C "CM_CLKSEL_HDMI_MCASP_AUX,Select the HDMI_CLK for McASP subsystems" bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_HDMI_TIMER,Select the HDMI_CLK for TIMER subsystems" bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_MCASP_SYS,Select the SYS CLK for ABE_24M_FCLK" bitfld.long 0x24 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_8" "CLKSEL_0,CLKSEL_1" group.long 0x38++0x03 line.long 0x00 "CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,Select the PER_ABE_X1_GFCLK_CLK for McASP subsystems" bitfld.long 0x00 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0x44++0x37 line.long 0x00 "CM_CLKSEL_TIMER_SYS,Select the SYS CLK for TIMERS subsystems" bitfld.long 0x00 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_VIDEO1_MCASP_AUX,Select the VIDEO1_CLK for McASP subsystems" bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_VIDEO1_TIMER,Select the VIDEO1_CLK for TIMER subsystems" bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_VIDEO2_MCASP_AUX,Select the VIDEO2_CLK for McASP subsystems" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_VIDEO2_TIMER,Select the VIDEO2_CLK for TIMER subsystems" bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_CLKOUTMUX0,Control the source of the CLKOUTMUX0_CLK" bitfld.long 0x14 0.--4. "CLKSEL,Select the source clock for CLKOUTMUX0_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_CLKSEL_CLKOUTMUX1,Control the source of the CLKOUTMUX1_CLK" bitfld.long 0x18 0.--4. "CLKSEL,Select the source clock for CLKOUTMUX1_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x1C "CM_CLKSEL_CLKOUTMUX2,Control the source of the CLKOUTMUX2_CLK" bitfld.long 0x1C 0.--4. "CLKSEL,Select the source clock for CLKOUTMUX2_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_CLKSEL_HDMI_PLL_SYS,Control the source of the SYS clock for DPLL_HDMI" bitfld.long 0x20 0. "CLKSEL,Select the SYS clock for the DPLL_HDMI - SEL_SYS_CLK1" "CLKSEL_0,CLKSEL_1" line.long 0x24 "CM_CLKSEL_VIDEO1_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x24 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO1" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_VIDEO2_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x28 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO2" "CLKSEL_0,CLKSEL_1" line.long 0x2C "CM_CLKSEL_ABE_CLK_DIV,Select the ABE_CLK" bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_ABE_GICLK_DIV,Select the ABE_GICLK" bitfld.long 0x30 0. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x34 "CM_CLKSEL_AESS_FCLK_DIV,Select the AESS_FCLK" bitfld.long 0x34 0. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1" group.long 0x80++0x5B line.long 0x00 "CM_CLKSEL_EVE_CLK,Control the source of the EVE_CLK for EVE1. EVE2. ISS" bitfld.long 0x00 0. "CLKSEL,Select the EVE_CLK for EVE1 EVE2 ISS - SEL_EVE_GFCLK" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX,Select the USB_OTG_CLK" bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,Select the CORE_DPLL_OUT_CLK" bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_DSP_GFCLK_CLKOUTMUX,Select the DSP_GFCLK" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,Select the EMIF_PHY_GCLK" bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_EMU_CLK_CLKOUTMUX,Select the EMU_CLK" bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX,Select the FUNC_96M_AON_CLK" bitfld.long 0x18 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x1C "CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,Select the GMAC_250M_CLK" bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_GPU_GCLK_CLKOUTMUX,Select the GPU_GCLK" bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_HDMI_CLK_CLKOUTMUX,Select the HDMI_CLK" bitfld.long 0x24 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x28 "CM_CLKSEL_IVA_GCLK_CLKOUTMUX,Select the IVA_GCLK" bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,Select the L3INIT_480M_GFCLK" bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_MPU_GCLK_CLKOUTMUX,Select the MPU_GCLK" bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_PCIE1_CLK_CLKOUTMUX,Select the PCIE1_DCLK. where APLL_PCIE_M2_CLK is the source clock of PCIE1_DCLK" bitfld.long 0x34 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x38 "CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,Select the PCIE2_DCLK. where PCIE_M2_CLK is the source clock of PCIE2_DCLK" bitfld.long 0x38 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x3C "CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,Select the PER_ABE_X1_CLK" bitfld.long 0x3C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x40 "CM_CLKSEL_SATA_CLK_CLKOUTMUX,Select the SATA_CLK" bitfld.long 0x40 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x44 "CM_CLKSEL_OSC_32K_CLK_CLKOUTMUX,Select the OSC_32K_CLK [warm reset insensitive]Note: The OSC_32K_CLK clock. provided by the On-die 32K RC Osc is not accurate 32KHz clock" bitfld.long 0x44 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x48 "CM_CLKSEL_SYS_CLK1_CLKOUTMUX,Select the SYS_CLK1" bitfld.long 0x48 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x4C "CM_CLKSEL_SYS_CLK2_CLKOUTMUX,Select the SYS_CLK2" bitfld.long 0x4C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x50 "CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,Select the VIDEO1_CLK" bitfld.long 0x50 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x54 "CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX,Select the VIDEO2_CLK" bitfld.long 0x54 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x58 "CM_CLKSEL_ABE_LP_CLK,Select the ABE_LP_CLK" bitfld.long 0x58 0. "CLKSEL,Selects the divider value - CLK_DIV_16" "CLKSEL_0,CLKSEL_1" group.long 0xE0++0x03 line.long 0x00 "CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,Select the EVE_GFCLK" bitfld.long 0x00 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" width 0x0B tree.end tree "CM_CORE__CAM" base ad:0x4A009000 group.long 0x00++0x07 line.long 0x00 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 12. "CLKACTIVITY_LVDSRX_96M_GFCLK,This field indicates the state of the LVDSRX_96M_GFCLK clock input of the domain" "CLKACTIVITY_LVDSRX_96M_GFCLK_0,CLKACTIVITY_LVDSRX_96M_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_VIP3_GCLK,This field indicates the state of the VIP3_GCLK clock input of the domain" "CLKACTIVITY_VIP3_GCLK_0,CLKACTIVITY_VIP3_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_VIP2_GCLK,This field indicates the state of the VIP2_GCLK clock input of the domain" "CLKACTIVITY_VIP2_GCLK_0,CLKACTIVITY_VIP2_GCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_VIP1_GCLK,This field indicates the state of the VIP1_GCLK clock input of the domain" "CLKACTIVITY_VIP1_GCLK_0,CLKACTIVITY_VIP1_GCLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CAM clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain" "VPE_STATDEP_0,VPE_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_CAM_VIP1_CLKCTRL,This register manages the VIP1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_CAM_VIP2_CLKCTRL,This register manages the VIP2 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_CAM_VIP3_CLKCTRL,This register manages the CAL clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for CAL between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x40++0x03 line.long 0x00 "CM_CAM_CSI1_CLKCTRL,This register manages the CSI1 clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_CAM_CSI2_CLKCTRL,This register manages the CSI2 clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CM_CORE__CKGEN" base ad:0x4A008100 group.long 0x04++0x03 line.long 0x00 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p" bitfld.long 0x00 0. "CLKSEL,Select the configuration of the divider - SEL_DIV_1" "CLKSEL_0,CLKSEL_1" group.long 0x40++0x13 line.long 0x00 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" newline bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 11. "CLKX2ST,DPLL CLKOUTX2 status - CLK_GATED" "CLKX2ST_0,CLKX2ST_1" newline rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_PER" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x58++0x0F line.long 0x00 "CM_DIV_H11_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x00 0.--5. "DIVHS,This field programs the H11 post-divider factor (1 to 63) of DPLL_PER" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x04 "CM_DIV_H12_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x04 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x04 0.--5. "DIVHS,This field programs the H12 post-divider factor (1 to 63) of DPLL_PER" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x08 "CM_DIV_H13_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x08 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x08 0.--5. "DIVHS,This field programs the H13 post-divider factor (1 to 63) of DPLL_PER" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x0C "CM_DIV_H14_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" rbitfld.long 0x0C 9. "CLKST,HSDIVIDER1 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x0C 0.--5. "DIVHS,This field programs the H14 post-divider factor (1 to 63) of DPLL_PER" "DIVHS_0,?,DIVHS_2,?,DIVHS_4,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x80++0x13 line.long 0x00 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" newline bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" newline bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" newline bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline hexmask.long.byte 0x10 0.--6. 1. "DIVHS,This field programs the M2 post-divider factor (1 to 127) of DPLL_USB" rgroup.long 0xB4++0x03 line.long 0x00 "CM_CLKDCOLDO_DPLL_USB,This register provides status over CLKDCOLDO output of the DPLL" bitfld.long 0x00 9. "ST_DPLL_CLKDCOLDO,DPLL CLKDCOLDO status - CLK_GATED" "ST_DPLL_CLKDCOLDO_0,ST_DPLL_CLKDCOLDO_1" group.long 0x100++0x13 line.long 0x00 "CM_CLKMODE_DPLL_PCIE_REF,This register allows controlling the DPLL modes" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PCIE_REF,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" newline bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PCIE_REF,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PCIE_REF,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" newline bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for CLKOUT,CLKINPULOW is selected as the BYPASS clock for.." newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" newline hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PCIE_REF,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 10. "CLKLDOST,DPLL CLKOUTLDO status - CLK_GATED" "CLKLDOST_0,CLKLDOST_1" newline rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline hexmask.long.byte 0x10 0.--6. 1. "DIVHS,This field programs the M2 post-divider factor (1 to 127) of DPLL_PCIE_REF" group.long 0x11C++0x0F line.long 0x00 "CM_CLKMODE_APLL_PCIE,This register allows controlling the APLL modes" bitfld.long 0x00 8. "CLKDIV_BYPASS,- PCIEDIVBY2_BYPASS_0" "CLKDIV_BYPASS_0,CLKDIV_BYPASS_1" newline bitfld.long 0x00 7. "REFSEL,Select source of reference input clock - CLKREF_ADPLL" "REFSEL_0,REFSEL_1" newline rbitfld.long 0x00 3.--5. "INPSEL,Reference clock is 100MHz" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 2. "MODE,APLLPCIE Mode Status - PCIE" "MODE_0,?" newline bitfld.long 0x00 0.--1. "MODE_SELECT,Control APLL mode.Note:Please note that setting [1:0] MODE_SELECT bitfield to 0x0 does not disable the APLL_PCIE" "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3" line.long 0x04 "CM_IDLEST_APLL_PCIE,This register allows monitoring APLL activity" bitfld.long 0x04 0. "ST_APLL_CLK,APLL lock status - APLL_UNLOCKED" "ST_APLL_CLK_0,ST_APLL_CLK_1" line.long 0x08 "CM_DIV_M2_APLL_PCIE,This register provides controls over the M2 divider of the DPLL" bitfld.long 0x08 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline hexmask.long.byte 0x08 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x0C "CM_CLKVCOLDO_APLL_PCIE,This register provides status over CLKVCOLDO and CLKVCOLDO_DIV outputs of the APLL" bitfld.long 0x0C 10. "CLK_DIVST,APLL CLKVCOLDO_DIV status - CLK_GATED" "CLK_DIVST_0,CLK_DIVST_1" newline bitfld.long 0x0C 9. "CLKST,APLL CLKVCOLDO status - CLK_GATED" "CLKST_0,CLKST_1" width 0x0B tree.end tree "CM_CORE__CORE" base ad:0x4A008700 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_L3MAIN1_L4_GICLK,This field indicates the state of the L3MAIN1_L4_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L4_GICLK_0,CLKACTIVITY_L3MAIN1_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3MAIN1_L3_GICLK,This field indicates the state of the L3MAIN1_L3_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L3_GICLK_0,CLKACTIVITY_L3MAIN1_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3MAIN1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3MAIN1 domain towards 'target' domains" rbitfld.long 0x00 31. "EVE4_DYNDEP,Dynamic dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "?,EVE4_DYNDEP_1" newline rbitfld.long 0x00 30. "EVE3_DYNDEP,Dynamic dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "?,EVE3_DYNDEP_1" newline rbitfld.long 0x00 29. "EVE2_DYNDEP,Dynamic dependency towards EVE2 clock domain - ENABLED" "?,EVE2_DYNDEP_1" newline rbitfld.long 0x00 28. "EVE1_DYNDEP,Dynamic dependency towards EVE1 clock domain - ENABLED" "?,EVE1_DYNDEP_1" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 23. "L4PER3_DYNDEP,Dynamic dependency towards L4PER3 clock domain - ENABLED" "?,L4PER3_DYNDEP_1" newline rbitfld.long 0x00 22. "L4PER2_DYNDEP,Dynamic dependency towards L4PER2 clock domain - ENABLED" "?,L4PER2_DYNDEP_1" newline rbitfld.long 0x00 21. "PCIE_DYNDEP,Dynamic dependency towards PCIE clock domain - ENABLED" "?,PCIE_DYNDEP_1" newline rbitfld.long 0x00 20. "DSP2_DYNDEP,Dynamic dependency towards DSP2 clock domain - ENABLED" "?,DSP2_DYNDEP_1" newline rbitfld.long 0x00 18. "IPU1_DYNDEP,Dynamic dependency towards IPU1 clock domain - ENABLED" "?,IPU1_DYNDEP_1" newline rbitfld.long 0x00 15. "WKUPAON_DYNDEP,Dynamic dependency towards WKUPAON clock domain - ENABLED" "?,WKUPAON_DYNDEP_1" newline rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain - ENABLED" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 13. "L4PER_DYNDEP,Dynamic dependency towards L4PER1 clock domain - ENABLED" "?,L4PER_DYNDEP_1" newline rbitfld.long 0x00 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x00 10. "GPU_DYNDEP,Dynamic dependency towards GPU clock domain - ENABLED" "?,GPU_DYNDEP_1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain - ENABLED" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" newline rbitfld.long 0x00 2. "IVA_DYNDEP,Dynamic dependency towards IVA clock domain - ENABLED" "?,IVA_DYNDEP_1" newline rbitfld.long 0x00 1. "DSP1_DYNDEP,Dynamic dependency towards DSP1 clock domain - ENABLED" "?,DSP1_DYNDEP_1" newline rbitfld.long 0x00 0. "IPU2_DYNDEP,Dynamic dependency towards IPU2 clock domain" "?,IPU2_DYNDEP_1" rgroup.long 0x20++0x03 line.long 0x00 "CM_L3MAIN1_L3_MAIN_1_CLKCTRL,This register manages the L3_MAIN_1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x28++0x03 line.long 0x00 "CM_L3MAIN1_GPMC_CLKCTRL,This register manages the GPMC clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_MMU_EDMA_CLKCTRL,This register manages the MMU_L4_EDMA clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_MMU_PCIESS_CLKCTRL,This register manages the MMU_L4_PCIESS clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM1_CLKCTRL,This register manages the OCMC_RAM1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x58++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM2_CLKCTRL,This register manages the OCMC_RAM2 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM3_CLKCTRL,This register manages the OCMC_RAM3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x70++0x03 line.long 0x00 "CM_L3MAIN1_TPCC_CLKCTRL,This register manages the TPCC clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_L3MAIN1_TPTC1_CLKCTRL,This register manages the TPTC1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L3MAIN1_TPTC2_CLKCTRL,This register manages the TPTC2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x200++0x0B line.long 0x00 "CM_IPU2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IPU2_GFCLK,This field indicates the state of the IPU2_GFCLK clock in the domain" "CLKACTIVITY_IPU2_GFCLK_0,CLKACTIVITY_IPU2_GFCLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU2 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU2_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain - DISABLED" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" line.long 0x08 "CM_IPU2_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain - DISABLED" "CAM_DYNDEP_0,?" newline rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x220++0x03 line.long 0x00 "CM_IPU2_IPU2_CLKCTRL,This register manages the IPU2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x300++0x0B line.long 0x00 "CM_DMA_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DMA_L3_GICLK,This field indicates the state of the DMA_L3_GICLK clock in the domain" "CLKACTIVITY_DMA_L3_GICLK_0,CLKACTIVITY_DMA_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DMA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DMA_STATICDEP,This register controls the static domain depedencies from DMA domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" rgroup.long 0x320++0x03 line.long 0x00 "CM_DMA_DMA_SYSTEM_CLKCTRL,This register manages the DMA_SYSTEM clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x400++0x03 line.long 0x00 "CM_EMIF_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_EMIF_PHY_GCLK,This field indicates the state of the EMIF_PHY_GCLK clock in the domain" "CLKACTIVITY_EMIF_PHY_GCLK_0,CLKACTIVITY_EMIF_PHY_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_EMIF_DLL_GCLK,This field indicates the state of the DLL_GCLK clock in the domain" "CLKACTIVITY_EMIF_DLL_GCLK_0,CLKACTIVITY_EMIF_DLL_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_EMIF_L3_GICLK,This field indicates the state of the EMIF_L3_GICLK clock in the domain" "CLKACTIVITY_EMIF_L3_GICLK_0,CLKACTIVITY_EMIF_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMIF clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x420++0x03 line.long 0x00 "CM_EMIF_DMM_CLKCTRL,This register manages the DMM clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x428++0x03 line.long 0x00 "CM_EMIF_EMIF_OCP_FW_CLKCTRL,This register manages the EMIF_OCP_FW clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x430++0x03 line.long 0x00 "CM_EMIF_EMIF1_CLKCTRL,This register manages the EMIF1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x438++0x03 line.long 0x00 "CM_EMIF_EMIF2_CLKCTRL,This register manages the EMIF2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x440++0x03 line.long 0x00 "CM_EMIF_EMIF_DLL_CLKCTRL,This register manages the DLL clock" bitfld.long 0x00 8. "OPTFCLKEN_DLL_CLK,Optional functional clock control" "OPTFCLKEN_DLL_CLK_0,OPTFCLKEN_DLL_CLK_1" group.long 0x600++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_L4CFG_L3_GICLK,This field indicates the state of the L4CFG_L3_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L3_GICLK_0,CLKACTIVITY_L4CFG_L3_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4CFG_L4_GICLK,This field indicates the state of the L4CFG_L4_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L4_GICLK_0,CLKACTIVITY_L4CFG_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4CFG clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x608++0x03 line.long 0x00 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4CFG domain towards 'target' domains" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" newline rbitfld.long 0x00 19. "MPU_DYNDEP,Dynamic dependency towards MPU clock domain - ENABLED" "?,MPU_DYNDEP_1" newline rbitfld.long 0x00 17. "CUSTEFUSE_DYNDEP,Dynamic dependency towards CUSTEFUSE clock domain - ENABLED" "?,CUSTEFUSE_DYNDEP_1" newline rbitfld.long 0x00 16. "COREAON_DYNDEP,Dynamic dependency towards COREAON clock domain - ENABLED" "?,COREAON_DYNDEP_1" newline rbitfld.long 0x00 11. "SDMA_DYNDEP,Dynamic dependency towards DMA clock domain" "?,SDMA_DYNDEP_1" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" rgroup.long 0x620++0x03 line.long 0x00 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x628++0x03 line.long 0x00 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x630++0x03 line.long 0x00 "CM_L4CFG_MAILBOX1_CLKCTRL,This register manages the MAILBOX1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x638++0x03 line.long 0x00 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks.NOTE: This register is NOT supported on this device" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x640++0x03 line.long 0x00 "CM_L4CFG_OCP2SCP2_CLKCTRL,This register manages the OCP2SCP2 clocks and the optional clock of USB PHY" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x648++0x03 line.long 0x00 "CM_L4CFG_MAILBOX2_CLKCTRL,This register manages the MAILBOX2 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x650++0x03 line.long 0x00 "CM_L4CFG_MAILBOX3_CLKCTRL,This register manages the MAILBOX3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x658++0x03 line.long 0x00 "CM_L4CFG_MAILBOX4_CLKCTRL,This register manages the MAILBOX4 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x660++0x03 line.long 0x00 "CM_L4CFG_MAILBOX5_CLKCTRL,This register manages the MAILBOX5 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x668++0x03 line.long 0x00 "CM_L4CFG_MAILBOX6_CLKCTRL,This register manages the MAILBOX6 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x670++0x03 line.long 0x00 "CM_L4CFG_MAILBOX7_CLKCTRL,This register manages the MAILBOX7 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x678++0x03 line.long 0x00 "CM_L4CFG_MAILBOX8_CLKCTRL,This register manages the MAILBOX8 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x680++0x03 line.long 0x00 "CM_L4CFG_MAILBOX9_CLKCTRL,This register manages the MAILBOX9 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x688++0x03 line.long 0x00 "CM_L4CFG_MAILBOX10_CLKCTRL,This register manages the MAILBOX10 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x690++0x03 line.long 0x00 "CM_L4CFG_MAILBOX11_CLKCTRL,This register manages the MAILBOX11 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x698++0x03 line.long 0x00 "CM_L4CFG_MAILBOX12_CLKCTRL,This register manages the MAILBOX12 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A0++0x03 line.long 0x00 "CM_L4CFG_MAILBOX13_CLKCTRL,This register manages the MAILBOX13 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x700++0x03 line.long 0x00 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition" bitfld.long 0x00 10. "CLKACTIVITY_L3INSTR_TS_GCLK,This field indicates the state of the L3INSTR_TS_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_TS_GCLK_0,CLKACTIVITY_L3INSTR_TS_GCLK_1" newline bitfld.long 0x00 9. "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK,This field indicates the state of the L3INSTR_DLL_AGING_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_0,CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_1" newline bitfld.long 0x00 8. "CLKACTIVITY_L3INSTR_L3_GICLK,This field indicates the state of the L3INSTR_L3_GICLK clock in the domain" "CLKACTIVITY_L3INSTR_L3_GICLK_0,CLKACTIVITY_L3INSTR_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INSTR clock domain" "?,?,?,CLKTRCTRL_3" group.long 0x720++0x03 line.long 0x00 "CM_L3INSTR_L3_MAIN_2_CLKCTRL,This register manages the L3_MAIN_2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x728++0x03 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x740++0x03 line.long 0x00 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL,This register manages the OCP_WP_NOC clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x748++0x03 line.long 0x00 "CM_L3INSTR_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x750++0x03 line.long 0x00 "CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,This register manages the CTRL_MODULE_BANDGAP clock" bitfld.long 0x00 24.--25. "CLKSEL,Selects the divider value for generating the Thermal Sensor clock from WKUPAON_ICLK source" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CM_CORE__COREAON" base ad:0x4A008600 group.long 0x00++0x03 line.long 0x00 "CM_COREAON_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 16. "CLKACTIVITY_ABE_GICLK,This field indicates the state of the ABE_GICLK clock input of the domain" "CLKACTIVITY_ABE_GICLK_0,CLKACTIVITY_ABE_GICLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_COREAON_32K_GFCLK,This field indicates the state of the COREAON_32K_GFCLK clock in the domain" "CLKACTIVITY_COREAON_32K_GFCLK_0,CLKACTIVITY_COREAON_32K_GFCLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the COREAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x40++0x03 line.long 0x00 "CM_COREAON_USB_PHY1_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" group.long 0x88++0x03 line.long 0x00 "CM_COREAON_USB_PHY2_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" group.long 0x98++0x03 line.long 0x00 "CM_COREAON_USB_PHY3_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" group.long 0xA0++0x03 line.long 0x00 "CM_COREAON_CLKOUTMUX1_CLKCTRL,Used for controlling the CLKOUTMUX 1 gate" bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX1_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX1_CLK_0,OPTFCLKEN_CLKOUTMUX1_CLK_1" group.long 0xB0++0x03 line.long 0x00 "CM_COREAON_CLKOUTMUX2_CLKCTRL,Used for controlling the CLKOUTMUX 2 gate" bitfld.long 0x00 8. "OPTFCLKEN_CLKOUTMUX2_CLK,Optional functional clock control" "OPTFCLKEN_CLKOUTMUX2_CLK_0,OPTFCLKEN_CLKOUTMUX2_CLK_1" group.long 0xC0++0x03 line.long 0x00 "CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL,Used for controlling the L3INIT_60M_GFCLK gate" bitfld.long 0x00 8. "OPTFCLKEN_L3INIT_60M_GFCLK,Optional functional clock control; used to control the clock of USB2PHY2" "OPTFCLKEN_L3INIT_60M_GFCLK_0,OPTFCLKEN_L3INIT_60M_GFCLK_1" group.long 0xD0++0x03 line.long 0x00 "CM_COREAON_ABE_GICLK_CLKCTRL,Used for controlling ABE_GICLK gate" bitfld.long 0x00 8. "OPTFCLKEN_ABE_GICLK,Optional functional clock control" "OPTFCLKEN_ABE_GICLK_0,OPTFCLKEN_ABE_GICLK_1" width 0x0B tree.end tree "CM_CORE__CUSTEFUSE" base ad:0x4A009600 group.long 0x00++0x03 line.long 0x00 "CM_CUSTEFUSE_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK,This field indicates the state of the Cust_Efuse_SYS_CLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_0,CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CUSTEFUSE_L4_GICLK,This field indicates the state of the L4_CUSTEFUSE_GICLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_L4_GICLK_0,CLKACTIVITY_CUSTEFUSE_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CUSTEFUSE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x20++0x03 line.long 0x00 "CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL,This register manages the CUSTEFUSE clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE__DSS" base ad:0x4A009100 group.long 0x00++0x0B line.long 0x00 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition" rbitfld.long 0x00 18. "CLKACTIVITY_HDMI_PHY_GFCLK,This field indicates the state of the HDMI_PHY_GFCLK clock in the domain" "CLKACTIVITY_HDMI_PHY_GFCLK_0,CLKACTIVITY_HDMI_PHY_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_HDMI_CEC_GFCLK,This field indicates the state of the HDMI_CEC_GFCLK clock in the domain" "CLKACTIVITY_HDMI_CEC_GFCLK_0,CLKACTIVITY_HDMI_CEC_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_DSS_L4_GICLK,This field indicates the state of the DSS_L4_GICLK clock in the domain" "CLKACTIVITY_DSS_L4_GICLK_0,CLKACTIVITY_DSS_L4_GICLK_1" rbitfld.long 0x00 13. "CLKACTIVITY_BB2D_GFCLK,This field indicates the state of the BB2D_GFCLK clock in the domain" "CLKACTIVITY_BB2D_GFCLK_0,CLKACTIVITY_BB2D_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_VIDEO2_DPLL_CLK,This field indicates the state of the VIDEO2_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO2_DPLL_CLK_0,CLKACTIVITY_VIDEO2_DPLL_CLK_1" rbitfld.long 0x00 11. "CLKACTIVITY_HDMI_DPLL_CLK,This field indicates the state of the HDMI_DPLL_CLK clock in the domain" "CLKACTIVITY_HDMI_DPLL_CLK_0,CLKACTIVITY_HDMI_DPLL_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_VIDEO1_DPLL_CLK,This field indicates the state of the VIDEO1_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO1_DPLL_CLK_0,CLKACTIVITY_VIDEO1_DPLL_CLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_DSS_GFCLK,This field indicates the state of the DSS_GFCLK clock in the domain" "CLKACTIVITY_DSS_GFCLK_0,CLKACTIVITY_DSS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_DSS_L3_GICLK,This field indicates the state of the DSS_L3_GICLK clock in the domain" "CLKACTIVITY_DSS_L3_GICLK_0,CLKACTIVITY_DSS_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSS clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 13. "OPTFCLKEN_VIDEO2_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO2_CLK_0,OPTFCLKEN_VIDEO2_CLK_1" bitfld.long 0x00 12. "OPTFCLKEN_VIDEO1_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO1_CLK_0,OPTFCLKEN_VIDEO1_CLK_1" newline bitfld.long 0x00 11. "OPTFCLKEN_32KHZ_CLK,Optional functional clock control" "OPTFCLKEN_32KHZ_CLK_0,OPTFCLKEN_32KHZ_CLK_1" bitfld.long 0x00 10. "OPTFCLKEN_HDMI_CLK,Optional functional clock control" "OPTFCLKEN_HDMI_CLK_0,OPTFCLKEN_HDMI_CLK_1" newline bitfld.long 0x00 9. "OPTFCLKEN_48MHZ_CLK,Optional functional clock control" "OPTFCLKEN_48MHZ_CLK_0,OPTFCLKEN_48MHZ_CLK_1" bitfld.long 0x00 8. "OPTFCLKEN_DSSCLK,Optional functional clock control" "OPTFCLKEN_DSSCLK_0,OPTFCLKEN_DSSCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_DSS_BB2D_CLKCTRL,This register manages the BB2D clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE__GPU" base ad:0x4A009200 group.long 0x00++0x0B line.long 0x00 "CM_GPU_CLKSTCTRL,This register enables the GPU domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_GPU_HYD_GCLK,This field indicates the state of the GPU_HYD_GCLK clock in the domain" "CLKACTIVITY_GPU_HYD_GCLK_0,CLKACTIVITY_GPU_HYD_GCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_GPU_CORE_GCLK,This field indicates the state of the GPU_CORE_GCLK clock in the domain" "CLKACTIVITY_GPU_CORE_GCLK_0,CLKACTIVITY_GPU_CORE_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GPU_L3_GICLK,This field indicates the state of the GPU_L3_GICLK clock in the domain" "CLKACTIVITY_GPU_L3_GICLK_0,CLKACTIVITY_GPU_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the GPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GPU_STATICDEP,This register controls the static domain depedencies from GPU domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_GPU_DYNAMICDEP,This register controls the dynamic domain depedencies from GPU domain towards 'target' domains" bitfld.long 0x08 6. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_GPU_GPU_CLKCTRL,This register manages the GPU clocks" bitfld.long 0x00 26.--27. "CLKSEL_HYD_CLK,Select the source of the functional clock - SEL_CORE_GPU_CLK" "CLKSEL_HYD_CLK_0,CLKSEL_HYD_CLK_1,CLKSEL_HYD_CLK_2,CLKSEL_HYD_CLK_3" bitfld.long 0x00 24.--25. "CLKSEL_CORE_CLK,Select the source of the functional clock - SEL_CORE_GPU_CLK" "CLKSEL_CORE_CLK_0,CLKSEL_CORE_CLK_1,CLKSEL_CORE_CLK_2,CLKSEL_CORE_CLK_3" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE__IVA" base ad:0x4A008F00 group.long 0x00++0x0B line.long 0x00 "CM_IVA_CLKSTCTRL,This register enables the IVA domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IVA_GCLK,This field indicates the state of the IVA_ROOT_CLK clock input of the domain" "CLKACTIVITY_IVA_GCLK_0,CLKACTIVITY_IVA_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IVA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IVA_STATICDEP,This register controls the static domain depedencies from IVA domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_IVA_DYNAMICDEP,This register controls the dynamic domain depedencies from IVA domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_IVA_IVA_CLKCTRL,This register manages the IVA clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_IVA_SL2_CLKCTRL,This register manages the SL2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE__L3INIT" base ad:0x4A009300 group.long 0x00++0x0B line.long 0x00 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 24. "CLKACTIVITY_SATA_REF_GFCLK,This field indicates the state of the SATA_REF_GFCLK clock in the domain" "CLKACTIVITY_SATA_REF_GFCLK_0,CLKACTIVITY_SATA_REF_GFCLK_1" newline rbitfld.long 0x00 23. "CLKACTIVITY_L3INIT_32K_GFCLK,This field indicates the state of the L3INIT_32K_FCLK clock in the domain" "CLKACTIVITY_L3INIT_32K_GFCLK_0,CLKACTIVITY_L3INIT_32K_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_L3INIT_960M_GFCLK,This field indicates the state of the L3INIT_960M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_960M_GFCLK_0,CLKACTIVITY_L3INIT_960M_GFCLK_1" newline rbitfld.long 0x00 21. "CLKACTIVITY_L3INIT_480M_GFCLK,This field indicates the state of the L3INIT_480M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_480M_GFCLK_0,CLKACTIVITY_L3INIT_480M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_USB_OTG_SS_REF_CLK,This field indicates the state of the USB_OTG_SS_REF_CLK clock in the domain" "CLKACTIVITY_USB_OTG_SS_REF_CLK_0,CLKACTIVITY_USB_OTG_SS_REF_CLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MMC2_GFCLK,This field indicates the state of the MMC2 clock in the domain" "CLKACTIVITY_MMC2_GFCLK_0,CLKACTIVITY_MMC2_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_MMC1_GFCLK,This field indicates the state of the MMC1_GFCLK clock in the domain" "CLKACTIVITY_MMC1_GFCLK_0,CLKACTIVITY_MMC1_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_USB_DPLL_HS_CLK,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_HS_CLK_0,CLKACTIVITY_USB_DPLL_HS_CLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_USB_DPLL_CLK,This field indicates the state of the USB_DPLL_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_CLK_0,CLKACTIVITY_USB_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_L3INIT_48M_GFCLK,This field indicates the state of the INIT_48M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_48M_GFCLK_0,CLKACTIVITY_L3INIT_48M_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK,This field indicates the state of the L3INIT_USB_LFPS_TX_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_0,CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_L3INIT_L4_GICLK,This field indicates the state of the L3INIT_L4_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L4_GICLK_0,CLKACTIVITY_L3INIT_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3INIT_L3_GICLK,This field indicates the state of the L3INIT_L3_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L3_GICLK_0,CLKACTIVITY_L3INIT_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L3INIT_STATICDEP,This register controls the static domain depedencies from L3INIT domain towards 'target' domains" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x28++0x03 line.long 0x00 "CM_L3INIT_MMC1_CLKCTRL,This register manages the MMC1 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC1 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L3INIT_MMC2_CLKCTRL,This register manages the MMC2 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC2 clock divide ratio - DIV1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS2_CLKCTRL,This register manages the USB_OTG_SS2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock) - FCLK_DIS" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS3_CLKCTRL,This register manages the USB_OTG_SS3 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS4_CLKCTRL,This register manages the USB_OTG_SS4 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x78++0x03 line.long 0x00 "CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,This register manages the IEE1500_2_OCP clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x88++0x03 line.long 0x00 "CM_L3INIT_SATA_CLKCTRL,This register manages the SATA clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REF_CLK,SATA optional clock control: REF_CLK (from SYS_CLK clock) - FCLK_DIS" "OPTFCLKEN_REF_CLK_0,OPTFCLKEN_REF_CLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x07 line.long 0x00 "CM_PCIE_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 13. "CLKACTIVITY_PCIE_32K_GFCLK,This field indicates the state of the PCIE_32K_GFCLK clock in the domain" "CLKACTIVITY_PCIE_32K_GFCLK_0,CLKACTIVITY_PCIE_32K_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_PCIE_SYS_GFCLK,This field indicates the state of the PCIE_SYS_GFCLK clock in the domain" "CLKACTIVITY_PCIE_SYS_GFCLK_0,CLKACTIVITY_PCIE_SYS_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_PCIE_REF_GFCLK,This field indicates the state of the PCIE_REF_GFCLK clock in the domain" "CLKACTIVITY_PCIE_REF_GFCLK_0,CLKACTIVITY_PCIE_REF_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_PCIE_PHY_DIV_GCLK,This field indicates the state of the PCIE_PHY_DIV_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_DIV_GCLK_0,CLKACTIVITY_PCIE_PHY_DIV_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_PCIE_PHY_GCLK,This field indicates the state of the PCIE_PHY_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_GCLK_0,CLKACTIVITY_PCIE_PHY_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_PCIE_L3_GICLK,This field indicates the state of the PCIE_L3_GICLK clock in the domain" "CLKACTIVITY_PCIE_L3_GICLK_0,CLKACTIVITY_PCIE_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_PCIE_STATICDEP,This register controls the static domain depedencies from PCIE domain towards 'target' domains" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" group.long 0xB0++0x03 line.long 0x00 "CM_PCIE_PCIESS1_CLKCTRL,This register manages the PCESS1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed.Note: In order to disable the APLL_PCIE the user needs to disable PCIe_SSx (where x = 1 or 2) using the CM_PCIE_PCIESSx_CLKCTRL[1:0] MODULEMODE registers" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_PCIE_PCIESS2_CLKCTRL,This register manages the PCESS2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed.Note: In order to disable the APLL_PCIE the user needs to disable PCIe_SSx (where x = 1 or 2) using the CM_PCIE_PCIESSx_CLKCTRL[1:0] MODULEMODE registers" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xC0++0x0B line.long 0x00 "CM_GMAC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 12. "CLKACTIVITY_GMAC_MAIN_CLK,This field indicates the state of the GMAC_MAIN_CLK clock in the domain" "CLKACTIVITY_GMAC_MAIN_CLK_0,CLKACTIVITY_GMAC_MAIN_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_GMAC_RFT_CLK,This field indicates the state of the GMAC_RFT_CLK clock in the domain" "CLKACTIVITY_GMAC_RFT_CLK_0,CLKACTIVITY_GMAC_RFT_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_RMII_50MHZ_CLK,This field indicates the state of the RMII_50MHZ_CLK clock in the domain" "CLKACTIVITY_RMII_50MHZ_CLK_0,CLKACTIVITY_RMII_50MHZ_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_RGMII_5MHZ_CLK,This field indicates the state of the RGMII_5MHZ_CLK clock in the domain" "CLKACTIVITY_RGMII_5MHZ_CLK_0,CLKACTIVITY_RGMII_5MHZ_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GMII_250MHZ_CLK,This field indicates the state of the GMII_250MHZ_CLK clock in the domain" "CLKACTIVITY_GMII_250MHZ_CLK_0,CLKACTIVITY_GMII_250MHZ_CLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,WARNING: This bit field must not be programmed for SW_SLEEP or HW_AUTO for EEE mode" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GMAC_STATICDEP,This register controls the static domain depedencies from GMAC domain towards 'target' domains" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_GMAC_DYNAMICDEP,This register controls the dynamic domain depedencies from GMAC domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0xD0++0x03 line.long 0x00 "CM_GMAC_GMAC_CLKCTRL,This register manages the GMAC clocks" bitfld.long 0x00 25.--27. "CLKSEL_RFT,Selects the source of the GMAC_RFT_CLK" "CLKSEL_RFT_0,CLKSEL_RFT_1,CLKSEL_RFT_2,CLKSEL_RFT_3,CLKSEL_RFT_4,CLKSEL_RFT_5,CLKSEL_RFT_6,CLKSEL_RFT_7" newline bitfld.long 0x00 24. "CLKSEL_REF,Selects the source of the RMII_50MHZ_CLK functional clock" "CLKSEL_REF_0,CLKSEL_REF_1" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE0++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP1_CLKCTRL,This register manages the OCP2SCP1 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE8++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP3_CLKCTRL,This register manages the OCP2SCP3 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock) - FCLK_DIS" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE__L4PER" base ad:0x4A009700 group.long 0x00++0x03 line.long 0x00 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 27. "CLKACTIVITY_L4PER_32K_GFCLK,This field indicates the state of the L4PER_32K_FCLK clock in the domain" "CLKACTIVITY_L4PER_32K_GFCLK_0,CLKACTIVITY_L4PER_32K_GFCLK_1" rbitfld.long 0x00 26. "CLKACTIVITY_UART5_GFCLK,This field indicates the state of the UART5_GFCLK clock in the domain" "CLKACTIVITY_UART5_GFCLK_0,CLKACTIVITY_UART5_GFCLK_1" newline rbitfld.long 0x00 24. "CLKACTIVITY_GPIO_GFCLK,This field indicates the state of the GPIO_GFCLK clock in the domain" "CLKACTIVITY_GPIO_GFCLK_0,CLKACTIVITY_GPIO_GFCLK_1" rbitfld.long 0x00 23. "CLKACTIVITY_MMC4_GFCLK,This field indicates the state of the MMC4_GFCLK clock in the domain" "CLKACTIVITY_MMC4_GFCLK_0,CLKACTIVITY_MMC4_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_MMC3_GFCLK,This field indicates the state of the MMC3_GFCLK clock in the domain" "CLKACTIVITY_MMC3_GFCLK_0,CLKACTIVITY_MMC3_GFCLK_1" rbitfld.long 0x00 21. "CLKACTIVITY_PER_96M_GFCLK,This field indicates the state of the PER_96M_GFCLK clock in the domain" "CLKACTIVITY_PER_96M_GFCLK_0,CLKACTIVITY_PER_96M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_PER_48M_GFCLK,This field indicates the state of the PER_48M_GFCLK clock in the domain" "CLKACTIVITY_PER_48M_GFCLK_0,CLKACTIVITY_PER_48M_GFCLK_1" rbitfld.long 0x00 18. "CLKACTIVITY_UART4_GFCLK,This field indicates the state of the UART4_GFCLK clock in the domain" "CLKACTIVITY_UART4_GFCLK_0,CLKACTIVITY_UART4_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_UART3_GFCLK,This field indicates the state of the UART3_GFCLK clock in the domain" "CLKACTIVITY_UART3_GFCLK_0,CLKACTIVITY_UART3_GFCLK_1" rbitfld.long 0x00 16. "CLKACTIVITY_UART2_GFCLK,This field indicates the state of the UART2_GFCLK clock in the domain" "CLKACTIVITY_UART2_GFCLK_0,CLKACTIVITY_UART2_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_UART1_GFCLK,This field indicates the state of the UART1_GFCLK clock in the domain" "CLKACTIVITY_UART1_GFCLK_0,CLKACTIVITY_UART1_GFCLK_1" rbitfld.long 0x00 14. "CLKACTIVITY_TIMER9_GFCLK,This field indicates the state of the DMT9_GFCLK clock in the domain" "CLKACTIVITY_TIMER9_GFCLK_0,CLKACTIVITY_TIMER9_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_TIMER4_GFCLK,This field indicates the state of the DMT4_GFCLK clock in the domain" "CLKACTIVITY_TIMER4_GFCLK_0,CLKACTIVITY_TIMER4_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_TIMER3_GFCLK,This field indicates the state of the DMT3_GFCLK clock in the domain" "CLKACTIVITY_TIMER3_GFCLK_0,CLKACTIVITY_TIMER3_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_TIMER2_GFCLK,This field indicates the state of the DMT2_GFCLK clock in the domain" "CLKACTIVITY_TIMER2_GFCLK_0,CLKACTIVITY_TIMER2_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_TIMER11_GFCLK,This field indicates the state of the DMT11_GFCLK clock in the domain" "CLKACTIVITY_TIMER11_GFCLK_0,CLKACTIVITY_TIMER11_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_TIMER10_GFCLK,This field indicates the state of the DMT10_GFCLK clock in the domain" "CLKACTIVITY_TIMER10_GFCLK_0,CLKACTIVITY_TIMER10_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_L4PER_L3_GICLK,This field indicates the state of the L4PER_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER_L3_GICLK_0,CLKACTIVITY_L4PER_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x07 line.long 0x00 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER domain towards 'target' domains" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain - ENABLED" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain - ENABLED" "?,DSS_DYNDEP_1" rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" line.long 0x04 "CM_L4PER2_L4_PER2_CLKCTRL,This register manages the L4_PER2 clocks" bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x14++0x07 line.long 0x00 "CM_L4PER3_L4_PER3_CLKCTRL,This register manages the L4_PER3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PRUSS1_CLKCTRL,This register manages the PRU-ICSS clocks.Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS) is not supported in this family of devices" rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_L4PER_TIMER10_CLKCTRL,This register manages the TIMER10 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L4PER_TIMER11_CLKCTRL,This register manages the TIMER11 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_L4PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L4PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L4PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L4PER_TIMER9_CLKCTRL,This register manages the TIMER9 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x58++0x03 line.long 0x00 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x60++0x03 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_L4PER2_PWMSS2_CLKCTRL,This register manages the PWMSS2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x98++0x03 line.long 0x00 "CM_L4PER2_PWMSS3_CLKCTRL,This register manages the PWMSS3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x03 line.long 0x00 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA8++0x03 line.long 0x00 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB0++0x03 line.long 0x00 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xC0++0x0B line.long 0x00 "CM_L4PER_L4_PER1_CLKCTRL,This register manages the L4_PER1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PWMSS1_CLKCTRL,This register manages the PWMSS1 clocks" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_L4PER3_TIMER13_CLKCTRL,This register manages the TIMER13 clocks" bitfld.long 0x08 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x08 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x08 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD0++0x03 line.long 0x00 "CM_L4PER3_TIMER14_CLKCTRL,This register manages the TIMER14 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD8++0x03 line.long 0x00 "CM_L4PER3_TIMER15_CLKCTRL,This register manages the TIMER15 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the MCSPI1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF8++0x03 line.long 0x00 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the MCSPI2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x100++0x03 line.long 0x00 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the MCSPI3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x108++0x03 line.long 0x00 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the MCSPI4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x110++0x03 line.long 0x00 "CM_L4PER_GPIO7_CLKCTRL,This register manages the GPIO7 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x118++0x03 line.long 0x00 "CM_L4PER_GPIO8_CLKCTRL,This register manages the GPIO8 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x120++0x03 line.long 0x00 "CM_L4PER_MMC3_CLKCTRL,This register manages the MMC3 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value - MMCCLK_DIV_1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x128++0x03 line.long 0x00 "CM_L4PER_MMC4_CLKCTRL,This register manages the MMC4 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value - MMCCLK_DIV_1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x130++0x03 line.long 0x00 "CM_L4PER3_TIMER16_CLKCTRL,This register manages the TIMER16 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x138++0x03 line.long 0x00 "CM_L4PER2_QSPI_CLKCTRL,This register manages the QSPI clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,QSPI clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x140++0x03 line.long 0x00 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x148++0x03 line.long 0x00 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x150++0x03 line.long 0x00 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x158++0x03 line.long 0x00 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x160++0x03 line.long 0x00 "CM_L4PER2_MCASP2_CLKCTRL,This register manages the MCASP2 clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x168++0x03 line.long 0x00 "CM_L4PER2_MCASP3_CLKCTRL,This register manages the MCASP3 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x170++0x03 line.long 0x00 "CM_L4PER_UART5_CLKCTRL,This register manages the UART5 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x178++0x03 line.long 0x00 "CM_L4PER2_MCASP5_CLKCTRL,This register manages the MCASP5 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x180++0x0B line.long 0x00 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_L4SEC_L3_GICLK,This field indicates the state of the L3_SECURE_GICLK clock in the domain" "CLKACTIVITY_L4SEC_L3_GICLK_0,CLKACTIVITY_L4SEC_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L4SEC_STATICDEP,This register controls the static domain depedencies from L4SEC domain towards 'target' domains" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain depedencies from L4SEC domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x190++0x03 line.long 0x00 "CM_L4PER2_MCASP8_CLKCTRL,This register manages the MCASP8 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x198++0x03 line.long 0x00 "CM_L4PER2_MCASP4_CLKCTRL,This register manages the MCASP4 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A0++0x03 line.long 0x00 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A8++0x03 line.long 0x00 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B0++0x03 line.long 0x00 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B8++0x03 line.long 0x00 "CM_L4SEC_FPKA_CLKCTRL,This register manages the FPKA clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C0++0x03 line.long 0x00 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C8++0x03 line.long 0x00 "CM_L4SEC_SHA2MD51_CLKCTRL,This register manages the SHA2MD51 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1D0++0x03 line.long 0x00 "CM_L4PER2_UART7_CLKCTRL,This register manages the UART7 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x1D8++0x03 line.long 0x00 "CM_L4SEC_DMA_CRYPTO_CLKCTRL,This register manages the DMA_CRYPTO clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x1E0++0x03 line.long 0x00 "CM_L4PER2_UART8_CLKCTRL,This register manages the UART8 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1E8++0x03 line.long 0x00 "CM_L4PER2_UART9_CLKCTRL,This register manages the UART9 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F0++0x03 line.long 0x00 "CM_L4PER2_DCAN2_CLKCTRL,This register manages the DCAN2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F8++0x1F line.long 0x00 "CM_L4SEC_SHA2MD52_CLKCTRL,This register manages the SHA2MD52 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "CM_L4PER2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x04 31. "CLKACTIVITY_MCASP8_AUX_GFCLK,This field indicates the state of the MCASP8_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP8_AUX_GFCLK_0,CLKACTIVITY_MCASP8_AUX_GFCLK_1" rbitfld.long 0x04 30. "CLKACTIVITY_MCASP8_AHCLKX,This field indicates the state of the MCASP8_AHCLKX clock in the domain" "CLKACTIVITY_MCASP8_AHCLKX_0,CLKACTIVITY_MCASP8_AHCLKX_1" newline rbitfld.long 0x04 29. "CLKACTIVITY_MCASP7_AUX_GFCLK,This field indicates the state of the MCASP7_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP7_AUX_GFCLK_0,CLKACTIVITY_MCASP7_AUX_GFCLK_1" rbitfld.long 0x04 28. "CLKACTIVITY_MCASP7_AHCLKX,This field indicates the state of the MCASP7_AHCLKX clock in the domain" "CLKACTIVITY_MCASP7_AHCLKX_0,CLKACTIVITY_MCASP7_AHCLKX_1" newline rbitfld.long 0x04 27. "CLKACTIVITY_MCASP6_AUX_GFCLK,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AUX_GFCLK_0,CLKACTIVITY_MCASP6_AUX_GFCLK_1" rbitfld.long 0x04 26. "CLKACTIVITY_MCASP6_AHCLKX,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AHCLKX_0,CLKACTIVITY_MCASP6_AHCLKX_1" newline rbitfld.long 0x04 25. "CLKACTIVITY_MCASP5_AHCLKX,This field indicates the state of the MCASP5_AHCLKX clock in the domain" "CLKACTIVITY_MCASP5_AHCLKX_0,CLKACTIVITY_MCASP5_AHCLKX_1" rbitfld.long 0x04 24. "CLKACTIVITY_MCASP5_AUX_GFCLK,This field indicates the state of the MCASP5_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP5_AUX_GFCLK_0,CLKACTIVITY_MCASP5_AUX_GFCLK_1" newline rbitfld.long 0x04 23. "CLKACTIVITY_MCASP4_AUX_GFCLK,This field indicates the state of the MCASP4_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP4_AUX_GFCLK_0,CLKACTIVITY_MCASP4_AUX_GFCLK_1" rbitfld.long 0x04 22. "CLKACTIVITY_MCASP4_AHCLKX,This field indicates the state of the MCASP4_AHCLKX clock in the domain" "CLKACTIVITY_MCASP4_AHCLKX_0,CLKACTIVITY_MCASP4_AHCLKX_1" newline rbitfld.long 0x04 21. "CLKACTIVITY_MCASP3_AUX_GFCLK,This field indicates the state of the MCASP3_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP3_AUX_GFCLK_0,CLKACTIVITY_MCASP3_AUX_GFCLK_1" rbitfld.long 0x04 20. "CLKACTIVITY_MCASP3_AHCLKX,This field indicates the state of the MCASP3_AHCLKX clock in the domain" "CLKACTIVITY_MCASP3_AHCLKX_0,CLKACTIVITY_MCASP3_AHCLKX_1" newline rbitfld.long 0x04 19. "CLKACTIVITY_MCASP2_AUX_GFCLK,This field indicates the state of the MCASP2_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP2_AUX_GFCLK_0,CLKACTIVITY_MCASP2_AUX_GFCLK_1" rbitfld.long 0x04 18. "CLKACTIVITY_MCASP2_AHCLKR,This field indicates the state of the MCASP2_AHCLKR clock in the domain" "CLKACTIVITY_MCASP2_AHCLKR_0,CLKACTIVITY_MCASP2_AHCLKR_1" newline rbitfld.long 0x04 17. "CLKACTIVITY_MCASP2_AHCLKX,This field indicates the state of the MCASP2_AHCLKX clock in the domain" "CLKACTIVITY_MCASP2_AHCLKX_0,CLKACTIVITY_MCASP2_AHCLKX_1" rbitfld.long 0x04 16. "CLKACTIVITY_L4PER2_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER2_L3_GICLK_0,CLKACTIVITY_L4PER2_L3_GICLK_1" newline rbitfld.long 0x04 15. "CLKACTIVITY_DCAN2_SYS_CLK,This field indicates the state of the DCAN2_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN2_SYS_CLK_0,CLKACTIVITY_DCAN2_SYS_CLK_1" rbitfld.long 0x04 14. "CLKACTIVITY_ICSS_IEP_CLK,This field indicates the state of the ICSS_IEP_CLK clock in the domain" "CLKACTIVITY_ICSS_IEP_CLK_0,CLKACTIVITY_ICSS_IEP_CLK_1" newline rbitfld.long 0x04 13. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" rbitfld.long 0x04 12. "CLKACTIVITY_QSPI_GFCLK,This field indicates the state of the QSPI_GFCLK clock in the domain" "CLKACTIVITY_QSPI_GFCLK_0,CLKACTIVITY_QSPI_GFCLK_1" newline rbitfld.long 0x04 11. "CLKACTIVITY_UART9_GFCLK,This field indicates the state of the UART9_GFCLK clock in the domain" "CLKACTIVITY_UART9_GFCLK_0,CLKACTIVITY_UART9_GFCLK_1" rbitfld.long 0x04 10. "CLKACTIVITY_UART8_GFCLK,This field indicates the state of the UART8_GFCLK clock in the domain" "CLKACTIVITY_UART8_GFCLK_0,CLKACTIVITY_UART8_GFCLK_1" newline rbitfld.long 0x04 9. "CLKACTIVITY_UART7_GFCLK,This field indicates the state of the UART7_GFCLK clock in the domain" "CLKACTIVITY_UART7_GFCLK_0,CLKACTIVITY_UART7_GFCLK_1" rbitfld.long 0x04 8. "CLKACTIVITY_ICSS_CLK,This field indicates the state of the ICSS_CLK clock in the domain" "CLKACTIVITY_ICSS_CLK_0,CLKACTIVITY_ICSS_CLK_1" newline bitfld.long 0x04 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x08 "CM_L4PER2_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER2 domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 22. "GMAC_DYNDEP,Dynamic dependency towards GMAC clock domain - ENABLED" "?,GMAC_DYNDEP_1" newline rbitfld.long 0x08 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" rbitfld.long 0x08 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x08 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" line.long 0x0C "CM_L4PER2_MCASP6_CLKCTRL,This register manages the MCASP6 clocks" bitfld.long 0x0C 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x0C 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x10 "CM_L4PER2_MCASP7_CLKCTRL,This register manages the MCASP7 clocks" bitfld.long 0x10 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x10 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x10 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x10 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x14 "CM_L4PER2_STATICDEP,This register controls the static domain depedencies from L4PER2 domain towards 'target' domains" bitfld.long 0x14 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x14 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x14 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x14 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x14 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x18 "CM_L4PER3_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x18 12. "CLKACTIVITY_TIMER16_GFCLK,This field indicates the state of the DMT16_GFCLK clock in the domain" "CLKACTIVITY_TIMER16_GFCLK_0,CLKACTIVITY_TIMER16_GFCLK_1" rbitfld.long 0x18 11. "CLKACTIVITY_TIMER15_GFCLK,This field indicates the state of the DMT15_GFCLK clock in the domain" "CLKACTIVITY_TIMER15_GFCLK_0,CLKACTIVITY_TIMER15_GFCLK_1" newline rbitfld.long 0x18 10. "CLKACTIVITY_TIMER14_GFCLK,This field indicates the state of the DMT14_GFCLK clock in the domain" "CLKACTIVITY_TIMER14_GFCLK_0,CLKACTIVITY_TIMER14_GFCLK_1" rbitfld.long 0x18 9. "CLKACTIVITY_TIMER13_GFCLK,This field indicates the state of the DMT13_GFCLK clock in the domain" "CLKACTIVITY_TIMER13_GFCLK_0,CLKACTIVITY_TIMER13_GFCLK_1" newline rbitfld.long 0x18 8. "CLKACTIVITY_L4PER3_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER3_L3_GICLK_0,CLKACTIVITY_L4PER3_L3_GICLK_1" bitfld.long 0x18 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x1C "CM_L4PER3_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER3 domain towards 'target' domains" rbitfld.long 0x1C 31. "VPE_DYNDEP,Dynamic dependency towards VPE clock domain" "?,VPE_DYNDEP_1" bitfld.long 0x1C 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 23. "RTC_DYNDEP,Dynamic dependency towards RTC clock domain" "?,RTC_DYNDEP_1" rbitfld.long 0x1C 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x1C 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain - ENABLED" "?,CAM_DYNDEP_1" rbitfld.long 0x1C 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x1C 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" rbitfld.long 0x1C 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" width 0x0B tree.end tree "CM_CORE__OCP_SOCKET" base ad:0x4A008000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE,This register contains the IP revision code for the CM_CORE part of the PRCM" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_PROFILING_CLKCTRL,This register manages the CM_CORE_PROFILING clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_CORE_DEBUG_CFG,This register is used to configure the CM_CORE's 32-bit debug output" hexmask.long.byte 0x00 24.--31. 1. "SEL3,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--23. 1. "SEL2,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--15. 1. "SEL1,Internal signal block select for debug word byte-1" hexmask.long.byte 0x00 0.--7. 1. "SEL0,Internal signal block select for debug word byte-0" width 0x0B tree.end tree "CM_CORE__RESTORE" base ad:0x4A009E00 group.long 0x18++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x20++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x28++0x17 line.long 0x00 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x04 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x08 "CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE,Second address map for register" line.long 0x0C "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register" line.long 0x10 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE,Second address map for register" line.long 0x14 "CM_CM_CORE_PROFILING_CLKCTRL_RESTORE,Second address map for register" group.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP_RESTORE,Second address map for register" group.long 0x58++0x07 line.long 0x00 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x04 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register" width 0x0B tree.end tree "CM_CORE_AON__CKGEN" base ad:0x4A005100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_CORE,CORE module clock selection" rbitfld.long 0x00 8. "CLKSEL_L4,Selects L4 interconnect clock (L4_clk) - L3_CLK_DIV_1" "CLKSEL_L4_0,CLKSEL_L4_1" bitfld.long 0x00 4. "CLKSEL_L3,Selects L3 interconnect clock (L3_clk) - CORE_CLK_DIV_1" "CLKSEL_L3_0,CLKSEL_L3_1" group.long 0x08++0x03 line.long 0x00 "CM_CLKSEL_ABE,ABE module clock selection" bitfld.long 0x00 0.--1. "CLKSEL_OPP,Selects the OPP divider ABE domain - DIV_1" "CLKSEL_OPP_0,CLKSEL_OPP_1,CLKSEL_OPP_2,CLKSEL_OPP_3" group.long 0x10++0x03 line.long 0x00 "CM_DLL_CTRL,Special register for DLL control" bitfld.long 0x00 0. "DLL_OVERRIDE,Control if DLL lock and code outputs are overriden or not - NO_OVR" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" group.long 0x20++0x13 line.long 0x00 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x0C 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x3C++0x0B line.long 0x00 "CM_DIV_H12_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,This field programs the H12 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x04 "CM_DIV_H13_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x04 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x04 0.--5. "DIVHS,This field programs the H13 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x08 "CM_DIV_H14_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" rbitfld.long 0x08 9. "CLKST,HSDIVIDER1 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x08 0.--5. "DIVHS,This field programs the H14 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" group.long 0x54++0x1F line.long 0x00 "CM_DIV_H22_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the 2nd HSDIVIDER" rbitfld.long 0x00 9. "CLKST,HSDIVIDER2 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,This field programs the H22 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x04 "CM_DIV_H23_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the 2nd HSDIVIDER" rbitfld.long 0x04 9. "CLKST,HSDIVIDER2 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x04 0.--5. "DIVHS,This field programs the H23 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x08 "CM_DIV_H24_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the 2nd HSDIVIDER" rbitfld.long 0x08 9. "CLKST,HSDIVIDER2 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x08 0.--5. "DIVHS,This field programs the H24 post-divider factor (1 to 63) of DPLL_CORE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x0C "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes" rbitfld.long 0x0C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x0C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x0C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x0C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x10 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity" bitfld.long 0x10 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x10 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x10 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x14 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity" bitfld.long 0x14 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x18 "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" rbitfld.long 0x18 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" bitfld.long 0x18 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline hexmask.long.word 0x18 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x18 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x1C "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x1C 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_MPU" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x9C++0x17 line.long 0x00 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL MPU bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity" bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity" bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL" bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_IVA,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x14 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_IVA" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0xDC++0x1B line.long 0x00 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes" bitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,DPLL_REGM4XEN_1" bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity" bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity" bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL" rbitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_ABE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x14 11. "CLKX2ST,DPLL CLKOUTX2 status - CLK_GATED" "CLKX2ST_0,CLKX2ST_1" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x14 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_ABE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" line.long 0x18 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x18 0.--4. "DIVHS,This field programs the M3 post-divider factor (1 to 31) of DPLL_ABE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x110++0x13 line.long 0x00 "CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_DDR,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_DDR,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." bitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_DDR" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x128++0x03 line.long 0x00 "CM_DIV_H11_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,This field programs the H11 post-divider factor (1 to 63) of DPLL_DDR" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" group.long 0x134++0x17 line.long 0x00 "CM_CLKMODE_DPLL_DSP,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_DSP,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_DSP,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_DSP,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_DSP,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_DSP" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" line.long 0x14 "CM_DIV_M3_DPLL_DSP,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x14 0.--4. "DIVHS,This field programs the M3 post-divider factor (1 to 31) of DPLL_DSP" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x154++0x03 line.long 0x00 "CM_BYPCLK_DPLL_DSP,Control IVA PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" group.long 0x160++0x07 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS" bitfld.long 0x00 16.--18. "DPLL_DDR_DPLL_EN,Shadow register forCM_CLKMODE_DPLL_DDR.DPLL_EN" "DPLL_DDR_DPLL_EN_0,DPLL_DDR_DPLL_EN_1,DPLL_DDR_DPLL_EN_2,DPLL_DDR_DPLL_EN_3,DPLL_DDR_DPLL_EN_4,DPLL_DDR_DPLL_EN_5,DPLL_DDR_DPLL_EN_6,DPLL_DDR_DPLL_EN_7" bitfld.long 0x00 11.--15. "DPLL_DDR_M2_DIV,Shadow register forCM_DIV_M2_DPLL_DDR.DIVHS" "DPLL_DDR_M2_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 3. "DLL_RESET,Specify if DLL should be reset or not during the frequency change hardware sequence" "DLL_RESET_0,DLL_RESET_1" bitfld.long 0x00 2. "DLL_OVERRIDE,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" newline bitfld.long 0x00 0. "FREQ_UPDATE,Writing '1' indicates that a new configuration is available" "FREQ_UPDATE_0,FREQ_UPDATE_1" line.long 0x04 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS" bitfld.long 0x04 2.--7. "DPLL_CORE_H12_DIV,Shadow register forCM_DIV_H12_DPLL_CORE.DIVHS" "DPLL_CORE_H12_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x04 1. "CLKSEL_L3,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3" "CLKSEL_L3_0,CLKSEL_L3_1" newline bitfld.long 0x04 0. "GPMC_FREQ_UPDATE,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation" "GPMC_FREQ_UPDATE_0,GPMC_FREQ_UPDATE_1" group.long 0x170++0x03 line.long 0x00 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)" bitfld.long 0x00 0.--5. "PRESCAL,Time unit is equal to (PRESCAL + 1) L4 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x184++0x13 line.long 0x00 "CM_CLKMODE_DPLL_EVE,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_EVE,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_EVE,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_EVE,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_EVE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_EVE" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" group.long 0x1A4++0x27 line.long 0x00 "CM_BYPCLK_DPLL_EVE,Control IVA PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_GMAC,This register allows controlling the DPLL modes" rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_GMAC,This register allows monitoring DPLL activity" bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_GMAC,This register provides automatic control over the DPLL activity" bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_CTL_DISABLE" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_GMAC,This register provides controls over the DPLL" bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." bitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline bitfld.long 0x10 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_GMAC,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x14 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_GMAC" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" line.long 0x18 "CM_DIV_M3_DPLL_GMAC,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x18 0.--4. "DIVHS,This field programs the M3 post-divider factor (1 to 31) of DPLL_GMAC" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" line.long 0x1C "CM_DIV_H11_DPLL_GMAC,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x1C 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x1C 0.--5. "DIVHS,This field programs the H11 post-divider factor (1 to 63) of DPLL_GMAC" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x20 "CM_DIV_H12_DPLL_GMAC,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x20 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x20 0.--5. "DIVHS,This field programs the H12 post-divider factor (1 to 63) of DPLL_GMAC" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" line.long 0x24 "CM_DIV_H13_DPLL_GMAC,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x24 0.--5. "DIVHS,This field programs the H13 post-divider factor (1 to 63) of DPLL_GMAC" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_63" group.long 0x1D8++0x13 line.long 0x00 "CM_CLKMODE_DPLL_GPU,This register allows controlling the DPLL modes" rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_GPU,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_GPU,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_GPU,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "CLKINP is selected as the BYPASS clock for..,CLKINPULOW is selected as the BYPASS clock for.." rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x0C 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_GPU,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,This field programs the M2 post-divider factor (1 to 31) of DPLL_GPU" "DIVHS_0,DIVHS_1,DIVHS_2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,DIVHS_31" width 0x0B tree.end tree "CM_CORE_AON__DSP1" base ad:0x4A005400 group.long 0x00++0x0B line.long 0x00 "CM_DSP1_CLKSTCTRL,This register enables the DSP domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DSP1_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP1_GFCLK_0,CLKACTIVITY_DSP1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP1_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE Clock Domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE Clock Domain" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU Clock Domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 Clock Domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock DomainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock DomainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 Clock Domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 Clock Domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 Clock Domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE Clock Domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON Clock Domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON Clock Domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1Clock Domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG Clock Domain - DISABLED" "L4CFG_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM Clock Domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS Clock Domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT Clock Domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 Clock Domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF Clock Domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA Clock Domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 Clock Domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP1_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_DSP1_DSP1_CLKCTRL,This register manages the DSP clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE_AON__DSP2" base ad:0x4A005600 group.long 0x00++0x0B line.long 0x00 "CM_DSP2_CLKSTCTRL,This register enables the DSP domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DSP2_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP2_GFCLK_0,CLKACTIVITY_DSP2_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP2_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE Clock Domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE Clock Domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU Clock Domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 Clock Domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 Clock DomainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 Clock DomainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 Clock Domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 Clock Domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE Clock Domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON Clock Domain - DISABLED" "COREAON_STATDEP_0,?" bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON Clock Domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 Clock Domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG Clock Domain - DISABLED" "L4CFG_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM Clock Domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS Clock Domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT Clock Domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 Clock Domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF Clock Domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 Clock Domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP2_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_DSP2_DSP2_CLKCTRL,This register manages the DSP clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end repeat 4. (list 1. 2. 3. 4. )(list ad:0x4A005640 ad:0x4A005680 ad:0x4A0056C0 ad:0x4A005700 ) tree "CM_CORE_AON__EVE$1" base $2 group.long 0x00++0x07 line.long 0x00 "CM_EVE1_CLKSTCTRL,This register enables the EVE domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_EVE1_GFCLK,This field indicates the state of the EVE1_GFCLK clock in the domain" "CLKACTIVITY_EVE1_GFCLK_0,CLKACTIVITY_EVE1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE1_STATICDEP,This register controls the static domain depedencies from EVE1 domain towards 'target' domains" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_EVE1_EVE1_CLKCTRL,This register manages the EVE clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end repeat.end tree "CM_CORE_AON__INSTR" base ad:0x4A005F00 rgroup.long 0x00++0x03 line.long 0x00 "CMI_IDENTICATION,CM profiling identification register" group.long 0x10++0x07 line.long 0x00 "CMI_SYS_CONFIG,CM profiling system configuartion register" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local tartget state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "CMI_STATUS,CM profiling status register" bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "FIFOEMPTY_0,FIFOEMPTY_1" group.long 0x24++0x0F line.long 0x00 "CMI_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "CLAIM_3_0,CLAIM_3_1,CLAIM_3_2,CLAIM_3_3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "CLAIM_2_0,CLAIM_2_1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "CLAIM_1_0,CLAIM_1_1" newline bitfld.long 0x00 15. "MOD_ACT_EN,When HIGH the CM Module Activity collection is enabled" "MOD_ACT_EN_0,MOD_ACT_EN_1" bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the CM events capture is enabled" "EVT_CAPT_EN_0,EVT_CAPT_EN_1" line.long 0x04 "CMI_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x04 31. "SNAP_CAPT_EN_1F,Snapshot capture enable - Class-ID = 0x1F" "SNAP_CAPT_EN_1F_0,SNAP_CAPT_EN_1F_1" bitfld.long 0x04 30. "SNAP_CAPT_EN_1E," "SNAP_CAPT_EN_1E_0,SNAP_CAPT_EN_1E_1" bitfld.long 0x04 29. "SNAP_CAPT_EN_1D," "SNAP_CAPT_EN_1D_0,SNAP_CAPT_EN_1D_1" newline bitfld.long 0x04 28. "SNAP_CAPT_EN_1C," "SNAP_CAPT_EN_1C_0,SNAP_CAPT_EN_1C_1" bitfld.long 0x04 27. "SNAP_CAPT_EN_1B," "SNAP_CAPT_EN_1B_0,SNAP_CAPT_EN_1B_1" bitfld.long 0x04 26. "SNAP_CAPT_EN_1A," "SNAP_CAPT_EN_1A_0,SNAP_CAPT_EN_1A_1" newline bitfld.long 0x04 25. "SNAP_CAPT_EN_19," "SNAP_CAPT_EN_19_0,SNAP_CAPT_EN_19_1" bitfld.long 0x04 24. "SNAP_CAPT_EN_18," "SNAP_CAPT_EN_18_0,SNAP_CAPT_EN_18_1" bitfld.long 0x04 23. "SNAP_CAPT_EN_17," "SNAP_CAPT_EN_17_0,SNAP_CAPT_EN_17_1" newline bitfld.long 0x04 22. "SNAP_CAPT_EN_16," "SNAP_CAPT_EN_16_0,SNAP_CAPT_EN_16_1" bitfld.long 0x04 21. "SNAP_CAPT_EN_15," "SNAP_CAPT_EN_15_0,SNAP_CAPT_EN_15_1" bitfld.long 0x04 20. "SNAP_CAPT_EN_14," "SNAP_CAPT_EN_14_0,SNAP_CAPT_EN_14_1" newline bitfld.long 0x04 19. "SNAP_CAPT_EN_13," "SNAP_CAPT_EN_13_0,SNAP_CAPT_EN_13_1" bitfld.long 0x04 18. "SNAP_CAPT_EN_12," "SNAP_CAPT_EN_12_0,SNAP_CAPT_EN_12_1" bitfld.long 0x04 17. "SNAP_CAPT_EN_11," "SNAP_CAPT_EN_11_0,SNAP_CAPT_EN_11_1" newline bitfld.long 0x04 16. "SNAP_CAPT_EN_10,Snapshot capture enable - Class-ID = 0x10" "SNAP_CAPT_EN_10_0,SNAP_CAPT_EN_10_1" bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03 [0x23]" "SNAP_CAPT_EN_03_0,SNAP_CAPT_EN_03_1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02 [0x22]" "SNAP_CAPT_EN_02_0,SNAP_CAPT_EN_02_1" newline bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01 [0x21]" "SNAP_CAPT_EN_01_0,SNAP_CAPT_EN_01_1" bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00 [0x20]" "SNAP_CAPT_EN_00_0,SNAP_CAPT_EN_00_1" line.long 0x08 "CMI_TRIGGERING,CM profiling triggering control register" bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing CM events from external trigger detection" "TRIG_STOP_EN_0,TRIG_STOP_EN_1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing CM events from external trigger detection" "TRIG_START_EN_0,TRIG_START_EN_1" line.long 0x0C "CMI_SAMPLING,CM profiling sampling window register" bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "FCLK_DIV_FACOR_0,FCLK_DIV_FACOR_1,FCLK_DIV_FACOR_2,FCLK_DIV_FACOR_3,FCLK_DIV_FACOR_4,FCLK_DIV_FACOR_5,FCLK_DIV_FACOR_6,FCLK_DIV_FACOR_7,FCLK_DIV_FACOR_8,FCLK_DIV_FACOR_9,FCLK_DIV_FACOR_10,FCLK_DIV_FACOR_11,FCLK_DIV_FACOR_12,FCLK_DIV_FACOR_13,FCLK_DIV_FACOR_14,FCLK_DIV_FACOR_15" hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,CM events sampling window size" width 0x0B tree.end tree "CM_CORE_AON__IPU" base ad:0x4A005500 group.long 0x00++0x0B line.long 0x00 "CM_IPU1_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IPU1_GFCLK,This field indicates the state of the IPU1_GFCLK clock in the domain" "CLKACTIVITY_IPU1_GFCLK_0,CLKACTIVITY_IPU1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IPU1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU1_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_IPU1_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_IPU1_IPU1_CLKCTRL,This register manages the IPU1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects the timer functional clock - SEL_DPLL_ABE_X2_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_IPU_CLKSTCTRL,This register enables the ABE domain power state transition" rbitfld.long 0x00 18. "CLKACTIVITY_MCASP1_AHCLKR,This field indicates the state of the MCASP1_AHCLKR clock in the domain" "CLKACTIVITY_MCASP1_AHCLKR_0,CLKACTIVITY_MCASP1_AHCLKR_1" rbitfld.long 0x00 17. "CLKACTIVITY_MCASP1_AHCLKX,This field indicates the state of the MCASP1_AHCLKX clock in the domain" "CLKACTIVITY_MCASP1_AHCLKX_0,CLKACTIVITY_MCASP1_AHCLKX_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MCASP1_AUX_GFCLK,This field indicates the state of the MCASP1_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP1_AUX_GFCLK_0,CLKACTIVITY_MCASP1_AUX_GFCLK_1" rbitfld.long 0x00 14. "CLKACTIVITY_UART6_GFCLK,This field indicates the state of the UART6_GFCLK clock in the domain" "CLKACTIVITY_UART6_GFCLK_0,CLKACTIVITY_UART6_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_IPU_96M_GFCLK,This field indicates the state of the IPU_96M_GFCLK clock in the domain" "CLKACTIVITY_IPU_96M_GFCLK_0,CLKACTIVITY_IPU_96M_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_TIMER8_GFCLK,This field indicates the state of the TIMER8_GFCLK clock in the domain" "CLKACTIVITY_TIMER8_GFCLK_0,CLKACTIVITY_TIMER8_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_TIMER7_GFCLK,This field indicates the state of the TIMER7_GFCLK clock in the domain" "CLKACTIVITY_TIMER7_GFCLK_0,CLKACTIVITY_TIMER7_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_TIMER6_GFCLK,This field indicates the state of the TIMER6_GFCLK clock in the domain" "CLKACTIVITY_TIMER6_GFCLK_0,CLKACTIVITY_TIMER6_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_TIMER5_GFCLK,This field indicates the state of the TIMER5_GFCLK functional clock in the domain" "CLKACTIVITY_TIMER5_GFCLK_0,CLKACTIVITY_TIMER5_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_IPU_L3_GICLK,This field indicates the state of the IPU_L3_GICLK interface clock in the domain" "CLKACTIVITY_IPU_L3_GICLK_0,CLKACTIVITY_IPU_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the ABE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x50++0x03 line.long 0x00 "CM_IPU_MCASP1_CLKCTRL,This register manages the McASP clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_ABE_24M_GFCLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_IPU_TIMER5_CLKCTRL,This register manages the TIMER5 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x60++0x03 line.long 0x00 "CM_IPU_TIMER6_CLKCTRL,This register manages the TIMER6 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_IPU_TIMER7_CLKCTRL,This register manages the TIMER7 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_IPU_TIMER8_CLKCTRL,This register manages the TIMER8 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_IPU_I2C5_CLKCTRL,This register manages the I2C5 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_IPU_UART6_CLKCTRL,This register manages the UART6 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE_AON__MPU" base ad:0x4A005300 group.long 0x00++0x0B line.long 0x00 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_MPU_GCLK,This field indicates the state of the MPU_DPLL_CLK clock in the domain" "CLKACTIVITY_MPU_GCLK_0,CLKACTIVITY_MPU_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the MPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_MPU_STATICDEP,This register controls the static domain depedencies from MPU domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 22. "EVE4_STATDEP,Static dependency towards EVE4 clock domainEVE4 is not supported in this family of devices" "EVE4_STATDEP_0,EVE4_STATDEP_1" newline bitfld.long 0x04 21. "EVE3_STATDEP,Static dependency towards EVE3 clock domainEVE3 is not supported in this family of devices" "EVE3_STATDEP_0,EVE3_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain" "SDMA_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks" bitfld.long 0x00 26. "CLKSEL_ABE_DIV_MODE,Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock - DIV8" "CLKSEL_ABE_DIV_MODE_0,CLKSEL_ABE_DIV_MODE_1" bitfld.long 0x00 24.--25. "CLKSEL_EMIF_DIV_MODE,Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock - DIV4A" "CLKSEL_EMIF_DIV_MODE_0,CLKSEL_EMIF_DIV_MODE_1,CLKSEL_EMIF_DIV_MODE_2,CLKSEL_EMIF_DIV_MODE_3" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_MPU_MPU_MPU_DBG_CLKCTRL,This register manages the MPU_MPU_DBG clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "CM_CORE_AON__OCP_SOCKET" base ad:0x4A005000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE_AON,This register contains the IP revision code for the CM_CORE_AON part of the PRCM" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_AON_PROFILING_CLKCTRL,This register manages the CM_CORE_AON_PROFILING clock" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xEC++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_OUT,This register is used to monitor the CM_COREAON's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xF0)++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_CFG$1,This register is used to configure the CM_CORE_AON's 32-bit debug output" hexmask.long.word 0x00 0.--9. 1. "SEL0,Internal signal block select for debug word byte-0" repeat.end width 0x0B tree.end tree "CM_CORE_AON__RESTORE" base ad:0x4A005E00 group.long 0x00++0x07 line.long 0x00 "CM_CLKSEL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register" group.long 0x10++0x0B line.long 0x00 "CM_DIV_H12_DPLL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_H13_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_H14_DPLL_CORE_RESTORE,Second address map for register" group.long 0x20++0x0F line.long 0x00 "CM_DIV_H22_DPLL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_H23_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_H24_DPLL_CORE_RESTORE,Second address map for register" line.long 0x0C "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register" group.long 0x38++0x1B line.long 0x00 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register" line.long 0x08 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register" line.long 0x0C "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x10 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x14 "CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE,Second address map for register" line.long 0x18 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register" width 0x0B tree.end tree "CM_CORE_AON__RTC" base ad:0x4A005740 group.long 0x00++0x07 line.long 0x00 "CM_RTC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_RTC_AUX_CLK,This field indicates the state of the RTC_AUX_CLK in the domain" "CLKACTIVITY_RTC_AUX_CLK_0,CLKACTIVITY_RTC_AUX_CLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_RTC_L4_GICLK,This field indicates the state of the RTC_L4_GICLK clock in the domain" "CLKACTIVITY_RTC_L4_GICLK_0,CLKACTIVITY_RTC_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_RTC_RTCSS_CLKCTRL,This register manages the RTC clocks" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "CM_CORE_AON__VPE" base ad:0x4A005760 group.long 0x00++0x0B line.long 0x00 "CM_VPE_CLKSTCTRL,This register enables the VPE domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_VPE_GCLK,This field indicates the state of the VPE_GCLK clock in the domain" "CLKACTIVITY_VPE_GCLK_0,CLKACTIVITY_VPE_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_VPE_VPE_CLKCTRL,This register manages the VPE clocks" rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_VPE_STATICDEP,This register controls the static domain depedencies from VPE domain towards 'target' domains" bitfld.long 0x08 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" rbitfld.long 0x08 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x08 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" width 0x0B tree.end tree "CORE_PRM" base ad:0x4AE06700 group.long 0x00++0x07 line.long 0x00 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" rbitfld.long 0x00 24.--25. "OCP_NRET_BANK_ONSTATE,OCP_WP bank and DMM bank2 state when domain is ON" "?,?,?,OCP_NRET_BANK_ONSTATE_3" rbitfld.long 0x00 22.--23. "IPU_UNICACHE_ONSTATE,IPU UNICACHE bank state when domain is ON" "?,?,?,IPU_UNICACHE_ONSTATE_3" newline rbitfld.long 0x00 20.--21. "IPU_L2RAM_ONSTATE,IPU L2 bank state when domain is ON" "?,?,?,IPU_L2RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "CORE_OCMRAM_ONSTATE,OCMRAM bank state when domain is ON" "?,?,?,CORE_OCMRAM_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "CORE_OTHER_BANK_ONSTATE,DMA/ICR bank and DMM bank1 state when domain is ON" "?,?,?,CORE_OTHER_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 12.--13. "OCP_NRET_BANK_STATEST,OCP_WP bank and DMM bank2 state status - MEM_OFF" "OCP_NRET_BANK_STATEST_0,OCP_NRET_BANK_STATEST_1,OCP_NRET_BANK_STATEST_2,OCP_NRET_BANK_STATEST_3" rbitfld.long 0x04 10.--11. "IPU_UNICACHE_STATEST,IPU UNICACHE bank state status - MEM_OFF" "IPU_UNICACHE_STATEST_0,IPU_UNICACHE_STATEST_1,IPU_UNICACHE_STATEST_2,IPU_UNICACHE_STATEST_3" newline rbitfld.long 0x04 8.--9. "IPU_L2RAM_STATEST,IPU L2 bank state status - MEM_OFF" "IPU_L2RAM_STATEST_0,IPU_L2RAM_STATEST_1,IPU_L2RAM_STATEST_2,IPU_L2RAM_STATEST_3" rbitfld.long 0x04 6.--7. "CORE_OCMRAM_STATEST,OCMRAM bank state status - MEM_OFF" "CORE_OCMRAM_STATEST_0,CORE_OCMRAM_STATEST_1,CORE_OCMRAM_STATEST_2,CORE_OCMRAM_STATEST_3" newline rbitfld.long 0x04 4.--5. "CORE_OTHER_BANK_STATEST,DMA/ICR bank and DMM bank1 state status - MEM_OFF" "CORE_OTHER_BANK_STATEST_0,CORE_OTHER_BANK_STATEST_1,CORE_OTHER_BANK_STATEST_2,CORE_OTHER_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - RESERVED" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_L3MAIN1_L3_MAIN_1_CONTEXT,This register contains dedicated L3_MAIN_1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_L3MAIN1_GPMC_CONTEXT,This register contains dedicated GPMC context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x34++0x03 line.long 0x00 "RM_L3MAIN1_MMU_EDMA_CONTEXT,This register contains dedicated MMU context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x4C++0x1B line.long 0x00 "RM_L3MAIN1_MMU_PCIESS_CONTEXT,This register contains dedicated MMU context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L3MAIN1_OCMC_RAM1_WKDEP,This register controls wakeup dependency based on OCMC_RAM1 service requests" bitfld.long 0x04 9. "WKUPDEP_OCMC_RAM1_EVE4,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_OCMC_RAM1_EVE4_0,WKUPDEP_OCMC_RAM1_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_OCMC_RAM1_EVE3,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_OCMC_RAM1_EVE3_0,WKUPDEP_OCMC_RAM1_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_OCMC_RAM1_EVE2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_EVE2_0,WKUPDEP_OCMC_RAM1_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_OCMC_RAM1_EVE1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_EVE1_0,WKUPDEP_OCMC_RAM1_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_OCMC_RAM1_DSP2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_DSP2_0,WKUPDEP_OCMC_RAM1_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_OCMC_RAM1_IPU1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_IPU1_0,WKUPDEP_OCMC_RAM1_IPU1_1" newline bitfld.long 0x04 2. "WKUPDEP_OCMC_RAM1_DSP1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_DSP1_0,WKUPDEP_OCMC_RAM1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_OCMC_RAM1_IPU2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM1_IPU2_0,WKUPDEP_OCMC_RAM1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_OCMC_RAM1_MPU,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_MPU_0,WKUPDEP_OCMC_RAM1_MPU_1" line.long 0x08 "RM_L3MAIN1_OCMC_RAM1_CONTEXT,This register contains dedicated OCMC_RAM context statuses" bitfld.long 0x08 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L3MAIN1_OCMC_RAM2_WKDEP,This register controls wakeup dependency based on OCMC_RAM2 service requests" bitfld.long 0x0C 9. "WKUPDEP_OCMC_RAM2_EVE4,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_OCMC_RAM2_EVE4_0,WKUPDEP_OCMC_RAM2_EVE4_1" bitfld.long 0x0C 8. "WKUPDEP_OCMC_RAM2_EVE3,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_OCMC_RAM2_EVE3_0,WKUPDEP_OCMC_RAM2_EVE3_1" newline bitfld.long 0x0C 7. "WKUPDEP_OCMC_RAM2_EVE2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_EVE2_0,WKUPDEP_OCMC_RAM2_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_OCMC_RAM2_EVE1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_EVE1_0,WKUPDEP_OCMC_RAM2_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_OCMC_RAM2_DSP2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_DSP2_0,WKUPDEP_OCMC_RAM2_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_OCMC_RAM2_IPU1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_IPU1_0,WKUPDEP_OCMC_RAM2_IPU1_1" newline bitfld.long 0x0C 2. "WKUPDEP_OCMC_RAM2_DSP1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_DSP1_0,WKUPDEP_OCMC_RAM2_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_OCMC_RAM2_IPU2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM2_IPU2_0,WKUPDEP_OCMC_RAM2_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_OCMC_RAM2_MPU,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_MPU_0,WKUPDEP_OCMC_RAM2_MPU_1" line.long 0x10 "RM_L3MAIN1_OCMC_RAM2_CONTEXT,This register contains dedicated OCMC_RAM2 context statuses" bitfld.long 0x10 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L3MAIN1_OCMC_RAM3_WKDEP,This register controls wakeup dependency based on OCMC_RAM3 service requests" bitfld.long 0x14 9. "WKUPDEP_OCMC_RAM3_EVE4,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_OCMC_RAM3_EVE4_0,WKUPDEP_OCMC_RAM3_EVE4_1" bitfld.long 0x14 8. "WKUPDEP_OCMC_RAM3_EVE3,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_OCMC_RAM3_EVE3_0,WKUPDEP_OCMC_RAM3_EVE3_1" newline bitfld.long 0x14 7. "WKUPDEP_OCMC_RAM3_EVE2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_EVE2_0,WKUPDEP_OCMC_RAM3_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_OCMC_RAM3_EVE1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_EVE1_0,WKUPDEP_OCMC_RAM3_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_OCMC_RAM3_DSP2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_DSP2_0,WKUPDEP_OCMC_RAM3_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_OCMC_RAM3_IPU1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_IPU1_0,WKUPDEP_OCMC_RAM3_IPU1_1" newline bitfld.long 0x14 2. "WKUPDEP_OCMC_RAM3_DSP1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_DSP1_0,WKUPDEP_OCMC_RAM3_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_OCMC_RAM3_IPU2,Wakeup dependency from OCMC_RAM3 module RW 0x0 (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_OCMC_RAM3_IPU2_0,WKUPDEP_OCMC_RAM3_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_OCMC_RAM3_MPU,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_MPU_0,WKUPDEP_OCMC_RAM3_MPU_1" line.long 0x18 "RM_L3MAIN1_OCMC_RAM3_CONTEXT,This register contains dedicated OCMC_RAM3 context statuses" bitfld.long 0x18 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x70++0x17 line.long 0x00 "PM_L3MAIN1_TPCC_WKDEP,This register controls wakeup dependency based on TPCC service requests" bitfld.long 0x00 9. "WKUPDEP_TPCC_EVE4,Wakeup dependency from TPCC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TPCC_EVE4_0,WKUPDEP_TPCC_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_TPCC_EVE3,Wakeup dependency from TPCC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TPCC_EVE3_0,WKUPDEP_TPCC_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_TPCC_EVE2,Wakeup dependency from TPCC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_EVE2_0,WKUPDEP_TPCC_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_TPCC_EVE1,Wakeup dependency from TPCC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_EVE1_0,WKUPDEP_TPCC_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_TPCC_DSP2,Wakeup dependency from TPCC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_DSP2_0,WKUPDEP_TPCC_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_TPCC_IPU1,Wakeup dependency from TPCC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_IPU1_0,WKUPDEP_TPCC_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_TPCC_DSP1,Wakeup dependency from TPCC module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_DSP1_0,WKUPDEP_TPCC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_TPCC_IPU2,Wakeup dependency from TPCC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPCC_IPU2_0,WKUPDEP_TPCC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_TPCC_MPU,Wakeup dependency from TPCC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_MPU_0,WKUPDEP_TPCC_MPU_1" line.long 0x04 "RM_L3MAIN1_TPCC_CONTEXT,This register contains dedicated TPCC context statuses" bitfld.long 0x04 8. "LOSTMEM_TPCC_BANK,Specify if memory-based context in TPCC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPCC_BANK_0,LOSTMEM_TPCC_BANK_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3MAIN1_TPTC1_WKDEP,This register controls wakeup dependency based on TPTC service requests" bitfld.long 0x08 9. "WKUPDEP_TPTC1_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TPTC1_EVE4_0,WKUPDEP_TPTC1_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_TPTC1_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TPTC1_EVE3_0,WKUPDEP_TPTC1_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_TPTC1_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_EVE2_0,WKUPDEP_TPTC1_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TPTC1_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_EVE1_0,WKUPDEP_TPTC1_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TPTC1_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_DSP2_0,WKUPDEP_TPTC1_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TPTC1_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_IPU1_0,WKUPDEP_TPTC1_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TPTC1_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_DSP1_0,WKUPDEP_TPTC1_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TPTC1_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC1_IPU2_0,WKUPDEP_TPTC1_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TPTC1_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_MPU_0,WKUPDEP_TPTC1_MPU_1" line.long 0x0C "RM_L3MAIN1_TPTC1_CONTEXT,This register contains dedicated TPTC1 context statuses" bitfld.long 0x0C 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x10 "PM_L3MAIN1_TPTC2_WKDEP,This register controls wakeup dependency based on TPTC service requests" bitfld.long 0x10 9. "WKUPDEP_TPTC2_EVE4,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TPTC2_EVE4_0,WKUPDEP_TPTC2_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_TPTC2_EVE3,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TPTC2_EVE3_0,WKUPDEP_TPTC2_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_TPTC2_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_EVE2_0,WKUPDEP_TPTC2_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TPTC2_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_EVE1_0,WKUPDEP_TPTC2_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TPTC2_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_DSP2_0,WKUPDEP_TPTC2_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TPTC2_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_IPU1_0,WKUPDEP_TPTC2_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TPTC2_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_DSP1_0,WKUPDEP_TPTC2_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TPTC2_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TPTC2_IPU2_0,WKUPDEP_TPTC2_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TPTC2_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_MPU_0,WKUPDEP_TPTC2_MPU_1" line.long 0x14 "RM_L3MAIN1_TPTC2_CONTEXT,This register contains dedicated TPTC2 context statuses" bitfld.long 0x14 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x210++0x07 line.long 0x00 "RM_IPU2_RSTCTRL,This register controls the release of the IPU2 sub-system resets" bitfld.long 0x00 2. "RST_IPU,IPU system reset control" "RST_IPU_0,RST_IPU_1" bitfld.long 0x00 1. "RST_CPU1,IPU Cortex M4 CPU1 reset control - CLEAR" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x00 0. "RST_CPU0,IPU Cortex M4 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU2_RSTST,This register logs the different reset sources of the IPU2 SS" bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M4 CPU1 has been reset due to IPU ICECRUSHER1 reset source - RESET_NO" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M4 CPU0 has been reset due to IPU ICECRUSHER0 reset source - RESET_NO" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" newline bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M4 CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M4 CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" newline bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status - RESET_NO" "RST_IPU_0,RST_IPU_1" bitfld.long 0x04 1. "RST_CPU1,IPU Cortex-M4 CPU1 SW reset status - RESET_NO" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x04 0. "RST_CPU0,IPU Cortex-M4 CPU0 SW reset status - RESET_NO" "RST_CPU0_0,RST_CPU0_1" group.long 0x224++0x03 line.long 0x00 "RM_IPU2_IPU2_CONTEXT,This register contains dedicated IPU2 context statuses" bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x324++0x03 line.long 0x00 "RM_DMA_DMA_SYSTEM_CONTEXT,This register contains dedicated SDMA context statuses" bitfld.long 0x00 8. "LOSTMEM_CORE_OTHER_BANK,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_OTHER_BANK_0,LOSTMEM_CORE_OTHER_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x424++0x03 line.long 0x00 "RM_EMIF_DMM_CONTEXT,This register contains dedicated DMM context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x42C++0x03 line.long 0x00 "RM_EMIF_EMIF_OCP_FW_CONTEXT,This register contains dedicated EMIF_OCP_FW context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x434++0x03 line.long 0x00 "RM_EMIF_EMIF1_CONTEXT,This register contains dedicated EMIF_1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x43C++0x03 line.long 0x00 "RM_EMIF_EMIF2_CONTEXT,This register contains dedicated EMIF_2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x444++0x03 line.long 0x00 "RM_EMIF_EMIF_DLL_CONTEXT,This register contains dedicated DLL context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x624++0x03 line.long 0x00 "RM_L4CFG_L4_CFG_CONTEXT,This register contains dedicated L4_CFG context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x62C++0x03 line.long 0x00 "RM_L4CFG_SPINLOCK_CONTEXT,This register contains dedicated HW_SEM context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x634++0x03 line.long 0x00 "RM_L4CFG_MAILBOX1_CONTEXT,This register contains dedicated MAILBOX1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x63C++0x03 line.long 0x00 "RM_L4CFG_SAR_ROM_CONTEXT,This register contains dedicated SAR_ROM context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x644++0x03 line.long 0x00 "RM_L4CFG_OCP2SCP2_CONTEXT,This register contains dedicated OCP2SCP2 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x64C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX2_CONTEXT,This register contains dedicated MAILBOX2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x654++0x03 line.long 0x00 "RM_L4CFG_MAILBOX3_CONTEXT,This register contains dedicated MAILBOX3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x65C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX4_CONTEXT,This register contains dedicated MAILBOX4 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x664++0x03 line.long 0x00 "RM_L4CFG_MAILBOX5_CONTEXT,This register contains dedicated MAILBOX5 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x66C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX6_CONTEXT,This register contains dedicated MAILBOX6 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x674++0x03 line.long 0x00 "RM_L4CFG_MAILBOX7_CONTEXT,This register contains dedicated MAILBOX7 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x67C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX8_CONTEXT,This register contains dedicated MAILBOX8 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x684++0x03 line.long 0x00 "RM_L4CFG_MAILBOX9_CONTEXT,This register contains dedicated MAILBOX9 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x68C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX10_CONTEXT,This register contains dedicated MAILBOX10 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x694++0x03 line.long 0x00 "RM_L4CFG_MAILBOX11_CONTEXT,This register contains dedicated MAILBOX11 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x69C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX12_CONTEXT,This register contains dedicated MAILBOX12 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x6A4++0x03 line.long 0x00 "RM_L4CFG_MAILBOX13_CONTEXT,This register contains dedicated MAILBOX13 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x724++0x03 line.long 0x00 "RM_L3INSTR_L3_MAIN_2_CONTEXT,This register contains dedicated L3_3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x72C++0x03 line.long 0x00 "RM_L3INSTR_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x744++0x03 line.long 0x00 "RM_L3INSTR_OCP_WP_NOC_CONTEXT,This register contains dedicated OCP_WP1 context statuses" bitfld.long 0x00 8. "LOSTMEM_CORE_NRET_BANK,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_NRET_BANK_0,LOSTMEM_CORE_NRET_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "CUSTEFUSE_PRM" base ad:0x4AE07600 group.long 0x00++0x07 line.long 0x00 "PM_CUSTEFUSE_PWRSTCTRL,This register controls the CUSTEFUSE power state to reach upon a domain sleep transition" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CUSTEFUSE_PWRSTST,This register provides a status on the current CUSTEFUSE power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,This register contains dedicated CUSTEFUSE module context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DEVICE_PRM" base ad:0x4AE07D00 group.long 0x00++0x0B line.long 0x00 "PRM_RSTCTRL,Global software cold and warm reset control" bitfld.long 0x00 1. "RST_GLOBAL_COLD_SW,Global COLD software reset control" "RST_GLOBAL_COLD_SW_0,RST_GLOBAL_COLD_SW_1" bitfld.long 0x00 0. "RST_GLOBAL_WARM_SW,Global WARM software reset control" "RST_GLOBAL_WARM_SW_0,RST_GLOBAL_WARM_SW_1" line.long 0x04 "PRM_RSTST,This register logs the global reset sources" bitfld.long 0x04 16. "TSHUT_IVA_RST,TSHUT_IVA warm reset event" "TSHUT_IVA_RST_0,TSHUT_IVA_RST_1" bitfld.long 0x04 15. "TSHUT_DSPEVE_RST,TSHUT_DSPEVE warm reset event" "TSHUT_DSPEVE_RST_0,TSHUT_DSPEVE_RST_1" newline bitfld.long 0x04 13. "TSHUT_CORE_RST,TSHUT_CORE warm reset event" "TSHUT_CORE_RST_0,TSHUT_CORE_RST_1" bitfld.long 0x04 12. "TSHUT_MM_RST,TSHUT_GPU warm reset event" "TSHUT_MM_RST_0,TSHUT_MM_RST_1" newline bitfld.long 0x04 11. "TSHUT_MPU_RST,TSHUT_MPU warm reset event" "TSHUT_MPU_RST_0,TSHUT_MPU_RST_1" bitfld.long 0x04 9. "ICEPICK_RST,IcePick reset event" "ICEPICK_RST_0,ICEPICK_RST_1" newline bitfld.long 0x04 5. "EXTERNAL_WARM_RST,External warm reset event - _0X0" "EXTERNAL_WARM_RST_0,EXTERNAL_WARM_RST_1" bitfld.long 0x04 3. "MPU_WDT_RST,WD_TIMER2 and MPU subsystem watchdog reset event" "MPU_WDT_RST_0,MPU_WDT_RST_1" newline bitfld.long 0x04 1. "GLOBAL_WARM_SW_RST,Global warm software reset event - _0X0" "GLOBAL_WARM_SW_RST_0,GLOBAL_WARM_SW_RST_1" bitfld.long 0x04 0. "GLOBAL_COLD_RST,Power-on (cold) reset event - _0X0" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x08 "PRM_RSTTIME,Reset duration control" bitfld.long 0x08 10.--14. "RSTTIME2,Power domain reset duration 2 in number of RM.SYSCLK clock cycles" "RSTTIME2_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.word 0x08 0.--9. 1. "RSTTIME1,Global reset duration 1 in number of Func_32k_clk clock cycles" group.long 0x18++0x0B line.long 0x00 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller" hexmask.long.byte 0x00 16.--23. 1. "HG_PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" hexmask.long.byte 0x00 8.--15. 1. "PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" newline hexmask.long.byte 0x00 0.--7. 1. "PCHARGE_TIME,Number of system clock cycles for the SRAM pre-charge duration" line.long 0x04 "PRM_IO_COUNT,This register allows controlling DDR IO isolation removal setup" hexmask.long.byte 0x04 0.--7. 1. "ISO_2_ON_TIME,Determines the setup time of the DDR IOs going out of isolation" line.long 0x08 "PRM_IO_PMCTRL,This register allows controlling power management features of the IOs" bitfld.long 0x08 16. "GLOBAL_WUEN,Global IO wakeup enable" "GLOBAL_WUEN_0,GLOBAL_WUEN_1" rbitfld.long 0x08 9. "WUCLK_STATUS,Gives value of WUCLKOUT signal coming back from IO pad ring" "WUCLK_STATUS_0,WUCLK_STATUS_1" newline bitfld.long 0x08 8. "WUCLK_CTRL,Direct control on WUCLKIN signal to IO pad ring" "WUCLK_CTRL_0,WUCLK_CTRL_1" rbitfld.long 0x08 5. "IO_ON_STATUS,Gives the functional status of the IO ring" "IO_ON_STATUS_0,IO_ON_STATUS_1" newline bitfld.long 0x08 4. "ISOOVR_EXTEND,Control non-EMIF IO isolation extension upon a device wakeup from OFF mode" "ISOOVR_EXTEND_0,ISOOVR_EXTEND_1" rbitfld.long 0x08 1. "ISOCLK_STATUS,Gives value of ISOCLKOUT signal coming back from IO pad ring" "ISOCLK_STATUS_0,ISOCLK_STATUS_1" newline bitfld.long 0x08 0. "ISOCLK_OVERRIDE,Override control on ISOCLKIN signal to IO pad ring" "ISOCLK_OVERRIDE_0,ISOCLK_OVERRIDE_1" group.long 0xBC++0x03 line.long 0x00 "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters" hexmask.long.byte 0x00 24.--31. 1. "STARTUP_COUNT,Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0x00 16.--23. 1. "SLPCNT_VALUE,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" newline hexmask.long.byte 0x00 8.--15. 1. "VSETUPCNT_VALUE,SRAM LDO rampup time from retention to active mode" bitfld.long 0x00 0.--5. "PCHARGECNT_VALUE,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC4++0x3B line.long 0x00 "PRM_SLDO_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain" bitfld.long 0x00 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x00 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x00 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x00 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x00 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x00 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x00 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x00 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x00 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x04 "PRM_SLDO_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" bitfld.long 0x04 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" bitfld.long 0x04 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x04 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,?" line.long 0x08 "PRM_SLDO_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain" bitfld.long 0x08 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x08 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x08 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x08 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x08 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x08 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x08 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x08 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x08 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x0C "PRM_SLDO_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain" rbitfld.long 0x0C 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x0C 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x0C 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x10 "PRM_SLDO_GPU_SETUP,Setup of the SRAM LDO for GPU voltage domain" bitfld.long 0x10 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x10 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x10 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x10 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x10 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x10 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x10 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x10 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x10 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x14 "PRM_SLDO_GPU_CTRL,Control and status of the SRAM LDO for GPU voltage domain" rbitfld.long 0x14 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x14 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x14 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x18 "PRM_ABBLDO_MPU_SETUP,Selects the MPU_ABB LDO mode" hexmask.long.byte 0x18 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x18 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline bitfld.long 0x18 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x1C "PRM_ABBLDO_MPU_CTRL,Control and Status of ABB on MPU voltage domain" rbitfld.long 0x1C 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x1C 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x1C 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x1C 0.--1. "OPP_SEL,To control the ABB LDO (FBB/RBB) at a given OPP set to 0x1" "OPP_SEL_0,OPP_SEL_1,?,?" line.long 0x20 "PRM_ABBLDO_GPU_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x20 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x20 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline bitfld.long 0x20 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x24 "PRM_ABBLDO_GPU_CTRL,Control and Status of ABB on GPU voltage domain" rbitfld.long 0x24 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x24 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x24 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x24 0.--1. "OPP_SEL,To control the ABB LDO (FBB/RBB) at a given OPP set to 0x1" "OPP_SEL_0,OPP_SEL_1,?,?" line.long 0x28 "PRM_BANDGAP_SETUP,Setup of the bandgap" hexmask.long.byte 0x28 0.--7. 1. "STARTUP_COUNT,Determines the start-up duration of BANDGAP" line.long 0x2C "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition" bitfld.long 0x2C 9. "EMIF2_OFFWKUP_DISABLE,Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode" "EMIF2_OFFWKUP_DISABLE_0,EMIF2_OFFWKUP_DISABLE_1" bitfld.long 0x2C 8. "EMIF1_OFFWKUP_DISABLE,Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode" "EMIF1_OFFWKUP_DISABLE_0,EMIF1_OFFWKUP_DISABLE_1" newline bitfld.long 0x2C 0. "DEVICE_OFF_ENABLE,Controls transition to device OFF mode" "DEVICE_OFF_ENABLE_0,DEVICE_OFF_ENABLE_1" line.long 0x30 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1" line.long 0x34 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A" line.long 0x38 "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B" group.long 0x118++0x1F line.long 0x00 "PRM_SLDO_DSPEVE_SETUP,Setup of the SRAM LDO for DSPEVE voltage domain" bitfld.long 0x00 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x00 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x00 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x00 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x00 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x00 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x00 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x00 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x00 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x04 "PRM_SLDO_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain" bitfld.long 0x04 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x04 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x04 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x04 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x04 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x04 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x04 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x04 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x04 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x08 "PRM_ABBLDO_DSPEVE_CTRL,Control and Status of ABB on DSPEVE voltage domain" rbitfld.long 0x08 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x08 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x08 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x08 0.--1. "OPP_SEL,To control the ABB LDO (FBB/RBB) at a given OPP set to 0x1" "OPP_SEL_0,OPP_SEL_1,?,?" line.long 0x0C "PRM_ABBLDO_IVA_CTRL,Control and Status of ABB on IVA voltage domain" rbitfld.long 0x0C 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x0C 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x0C 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x0C 0.--1. "OPP_SEL,To control the ABB LDO (FBB/RBB) at a given OPP set to 0x1" "OPP_SEL_0,OPP_SEL_1,?,?" line.long 0x10 "PRM_SLDO_DSPEVE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" rbitfld.long 0x10 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x10 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x10 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x14 "PRM_SLDO_IVA_CTRL,Control and status of the SRAM LDO for CORE voltage domain" rbitfld.long 0x14 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x14 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x14 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x18 "PRM_ABBLDO_DSPEVE_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x18 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x18 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline bitfld.long 0x18 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x1C "PRM_ABBLDO_IVA_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x1C 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x1C 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" newline bitfld.long 0x1C 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" width 0x0B tree.end tree "DSP1_PRM" base ad:0x4AE06400 group.long 0x00++0x07 line.long 0x00 "PM_DSP1_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "DSP1_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP1_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP1_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP1_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP1_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP1_L1_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP1_PWRSTST,This register provides a status on the DSP domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "DSP1_EDMA_STATEST,DSP_EDMA memory state status - MEM_OFF" "DSP1_EDMA_STATEST_0,DSP1_EDMA_STATEST_1,DSP1_EDMA_STATEST_2,DSP1_EDMA_STATEST_3" rbitfld.long 0x04 6.--7. "DSP1_L2_STATEST,DSP_L2 memory state status - MEM_OFF" "DSP1_L2_STATEST_0,DSP1_L2_STATEST_1,DSP1_L2_STATEST_2,DSP1_L2_STATEST_3" newline rbitfld.long 0x04 4.--5. "DSP1_L1_STATEST,DSP_L1 memory state status - MEM_OFF" "DSP1_L1_STATEST_0,DSP1_L1_STATEST_1,DSP1_L1_STATEST_2,DSP1_L1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP1_RSTCTRL,This register controls the release of the DSP sub-system resets" bitfld.long 0x00 1. "RST_DSP1,DSP reset control - CLEAR" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x00 0. "RST_DSP1_LRST,DSP Local reset control - CLEAR" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" line.long 0x04 "RM_DSP1_RSTST,This register logs the different reset sources of the DSP domain" bitfld.long 0x04 3. "RST_DSP1_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS - RESET_NO" "RST_DSP1_EMU_REQ_0,RST_DSP1_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP1_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP1_EMU_0,RST_DSP1_EMU_1" newline bitfld.long 0x04 1. "RST_DSP1,DSP SW reset status - RESET_NO" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x04 0. "RST_DSP1_LRST,DSP Local SW reset - RESET_NO" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP1_DSP1_CONTEXT,This register contains dedicated DSP context statuses" bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSP2_PRM" base ad:0x4AE07B00 group.long 0x00++0x07 line.long 0x00 "PM_DSP2_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "DSP2_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP2_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP2_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP2_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP2_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP2_L1_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP2_PWRSTST,This register provides a status on the DSP domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "DSP2_EDMA_STATEST,DSP_EDMA memory state status - MEM_OFF" "DSP2_EDMA_STATEST_0,DSP2_EDMA_STATEST_1,DSP2_EDMA_STATEST_2,DSP2_EDMA_STATEST_3" rbitfld.long 0x04 6.--7. "DSP2_L2_STATEST,DSP_L2 memory state status - MEM_OFF" "DSP2_L2_STATEST_0,DSP2_L2_STATEST_1,DSP2_L2_STATEST_2,DSP2_L2_STATEST_3" newline rbitfld.long 0x04 4.--5. "DSP2_L1_STATEST,DSP_L1 memory state status - MEM_OFF" "DSP2_L1_STATEST_0,DSP2_L1_STATEST_1,DSP2_L1_STATEST_2,DSP2_L1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP2_RSTCTRL,This register controls the release of the DSP sub-system resets" bitfld.long 0x00 1. "RST_DSP2,DSP SW reset control - CLEAR" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x00 0. "RST_DSP2_LRST,DSP Local reset control - CLEAR" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" line.long 0x04 "RM_DSP2_RSTST,This register logs the different reset sources of the DSP domain" bitfld.long 0x04 3. "RST_DSP2_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS - RESET_NO" "RST_DSP2_EMU_REQ_0,RST_DSP2_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP2_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP2_EMU_0,RST_DSP2_EMU_1" newline bitfld.long 0x04 1. "RST_DSP2,DSP SW reset status - RESET_NO" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x04 0. "RST_DSP2_LRST,DSP Local SW reset - RESET_NO" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP2_DSP2_CONTEXT,This register contains dedicated DSP context statuses" bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "DSS_PRM" base ad:0x4AE07100 group.long 0x00++0x07 line.long 0x00 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "DSS_MEM_ONSTATE,DSS_MEM state when domain is ON" "?,?,?,DSS_MEM_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "DSS_MEM_STATEST,DSS_MEM state status - MEM_OFF" "DSS_MEM_STATEST_0,DSS_MEM_STATEST_1,DSS_MEM_STATEST_2,DSS_MEM_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x0B line.long 0x00 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests" bitfld.long 0x00 29. "WKUPDEP_DSI1_B_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DSI1_B_EVE4_0,WKUPDEP_DSI1_B_EVE4_1" bitfld.long 0x00 28. "WKUPDEP_DSI1_B_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DSI1_B_EVE3_0,WKUPDEP_DSI1_B_EVE3_1" newline bitfld.long 0x00 27. "WKUPDEP_DSI1_B_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_EVE2_0,WKUPDEP_DSI1_B_EVE2_1" bitfld.long 0x00 26. "WKUPDEP_DSI1_B_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_EVE1_0,WKUPDEP_DSI1_B_EVE1_1" newline bitfld.long 0x00 25. "WKUPDEP_DSI1_B_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_DSP2_0,WKUPDEP_DSI1_B_DSP2_1" bitfld.long 0x00 24. "WKUPDEP_DSI1_B_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_IPU1_0,WKUPDEP_DSI1_B_IPU1_1" newline bitfld.long 0x00 23. "WKUPDEP_DSI1_B_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_SDMA_0,WKUPDEP_DSI1_B_SDMA_1" bitfld.long 0x00 22. "WKUPDEP_DSI1_B_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_DSP1_0,WKUPDEP_DSI1_B_DSP1_1" newline bitfld.long 0x00 21. "WKUPDEP_DSI1_B_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_B_IPU2_0,WKUPDEP_DSI1_B_IPU2_1" bitfld.long 0x00 20. "WKUPDEP_DSI1_B_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_MPU_0,WKUPDEP_DSI1_B_MPU_1" newline bitfld.long 0x00 19. "WKUPDEP_DSI1_A_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DSI1_A_EVE4_0,WKUPDEP_DSI1_A_EVE4_1" bitfld.long 0x00 18. "WKUPDEP_DSI1_A_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DSI1_A_EVE3_0,WKUPDEP_DSI1_A_EVE3_1" newline bitfld.long 0x00 17. "WKUPDEP_DSI1_A_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_EVE2_0,WKUPDEP_DSI1_A_EVE2_1" bitfld.long 0x00 16. "WKUPDEP_DSI1_A_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_EVE1_0,WKUPDEP_DSI1_A_EVE1_1" newline bitfld.long 0x00 15. "WKUPDEP_DSI1_A_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_DSP2_0,WKUPDEP_DSI1_A_DSP2_1" bitfld.long 0x00 14. "WKUPDEP_DSI1_A_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_IPU1_0,WKUPDEP_DSI1_A_IPU1_1" newline bitfld.long 0x00 13. "WKUPDEP_DSI1_A_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_SDMA_0,WKUPDEP_DSI1_A_SDMA_1" bitfld.long 0x00 12. "WKUPDEP_DSI1_A_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_DSP1_0,WKUPDEP_DSI1_A_DSP1_1" newline bitfld.long 0x00 11. "WKUPDEP_DSI1_A_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_A_IPU2_0,WKUPDEP_DSI1_A_IPU2_1" bitfld.long 0x00 10. "WKUPDEP_DSI1_A_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_MPU_0,WKUPDEP_DSI1_A_MPU_1" newline bitfld.long 0x00 9. "WKUPDEP_DISPC_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DISPC_EVE4_0,WKUPDEP_DISPC_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_DISPC_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DISPC_EVE3_0,WKUPDEP_DISPC_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_DISPC_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_EVE2_0,WKUPDEP_DISPC_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_DISPC_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_EVE1_0,WKUPDEP_DISPC_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_DISPC_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_DSP2_0,WKUPDEP_DISPC_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_DISPC_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_IPU1_0,WKUPDEP_DISPC_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_DISPC_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_SDMA_0,WKUPDEP_DISPC_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_DISPC_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_DSP1_0,WKUPDEP_DISPC_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_DISPC_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DISPC_IPU2_0,WKUPDEP_DISPC_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_DISPC_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_MPU_0,WKUPDEP_DISPC_MPU_1" line.long 0x04 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses" bitfld.long 0x04 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_DSS_DSS2_WKDEP,This register controls wakeup dependency based on DSS service requests" bitfld.long 0x08 25. "WKUPDEP_HDMIDMA_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIDMA_DSP2_0,WKUPDEP_HDMIDMA_DSP2_1" bitfld.long 0x08 23. "WKUPDEP_HDMIDMA_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIDMA_SDMA_0,WKUPDEP_HDMIDMA_SDMA_1" newline bitfld.long 0x08 22. "WKUPDEP_HDMIDMA_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIDMA_DSP1_0,WKUPDEP_HDMIDMA_DSP1_1" bitfld.long 0x08 19. "WKUPDEP_DSI1_C_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DSI1_C_EVE4_0,WKUPDEP_DSI1_C_EVE4_1" newline bitfld.long 0x08 18. "WKUPDEP_DSI1_C_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DSI1_C_EVE3_0,WKUPDEP_DSI1_C_EVE3_1" bitfld.long 0x08 17. "WKUPDEP_DSI1_C_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_EVE2_0,WKUPDEP_DSI1_C_EVE2_1" newline bitfld.long 0x08 16. "WKUPDEP_DSI1_C_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_EVE1_0,WKUPDEP_DSI1_C_EVE1_1" bitfld.long 0x08 15. "WKUPDEP_DSI1_C_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_DSP2_0,WKUPDEP_DSI1_C_DSP2_1" newline bitfld.long 0x08 14. "WKUPDEP_DSI1_C_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_IPU1_0,WKUPDEP_DSI1_C_IPU1_1" bitfld.long 0x08 13. "WKUPDEP_DSI1_C_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_SDMA_0,WKUPDEP_DSI1_C_SDMA_1" newline bitfld.long 0x08 12. "WKUPDEP_DSI1_C_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_DSP1_0,WKUPDEP_DSI1_C_DSP1_1" bitfld.long 0x08 11. "WKUPDEP_DSI1_C_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DSI1_C_IPU2_0,WKUPDEP_DSI1_C_IPU2_1" newline bitfld.long 0x08 10. "WKUPDEP_DSI1_C_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_MPU_0,WKUPDEP_DSI1_C_MPU_1" bitfld.long 0x08 9. "WKUPDEP_HDMIIRQ_EVE4,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_HDMIIRQ_EVE4_0,WKUPDEP_HDMIIRQ_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_HDMIIRQ_EVE3,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_HDMIIRQ_EVE3_0,WKUPDEP_HDMIIRQ_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_HDMIIRQ_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_EVE2_0,WKUPDEP_HDMIIRQ_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_HDMIIRQ_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_EVE1_0,WKUPDEP_HDMIIRQ_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_HDMIIRQ_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_DSP2_0,WKUPDEP_HDMIIRQ_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_HDMIIRQ_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_IPU1_0,WKUPDEP_HDMIIRQ_IPU1_1" bitfld.long 0x08 2. "WKUPDEP_HDMIIRQ_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_DSP1_0,WKUPDEP_HDMIIRQ_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_HDMIIRQ_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_HDMIIRQ_IPU2_0,WKUPDEP_HDMIIRQ_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_HDMIIRQ_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_MPU_0,WKUPDEP_HDMIIRQ_MPU_1" group.long 0x34++0x03 line.long 0x00 "RM_DSS_BB2D_CONTEXT,This register contains dedicated BB2B context statuses" bitfld.long 0x00 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EMU_CM" base ad:0x4AE07A00 group.long 0x00++0x0F line.long 0x00 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_EMU_SYS_CLK,This field indicates the state of the EMU_SYS_CLK clock in the domain" "CLKACTIVITY_EMU_SYS_CLK_0,CLKACTIVITY_EMU_SYS_CLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks" bitfld.long 0x04 18. "STBYST,Module standby status - FUNC" "STBYST_0,STBYST_1" bitfld.long 0x04 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x08 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" line.long 0x0C "CM_EMU_MPU_EMU_DBG_CLKCTRL,This register manages the MPU_EMU_DBG clocks" bitfld.long 0x0C 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" width 0x0B tree.end tree "EMU_PRM" base ad:0x4AE07900 rgroup.long 0x00++0x07 line.long 0x00 "PM_EMU_PWRSTCTRL,This register controls the EMU power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. "EMU_BANK_ONSTATE,EMU memory state when domain is ON" "?,?,?,EMU_BANK_ONSTATE_3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,?,?,?" line.long 0x04 "PM_EMU_PWRSTST,This register provides a status on the EMU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "EMU_BANK_STATEST,EMU memory bank state status - MEM_OFF" "EMU_BANK_STATEST_0,EMU_BANK_STATEST_1,EMU_BANK_STATEST_2,EMU_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,?,?,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_EMU_DEBUGSS_CONTEXT,This register contains dedicated DEBUGSS context statuses" bitfld.long 0x00 8. "LOSTMEM_EMU_BANK,Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EMU_BANK_0,LOSTMEM_EMU_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE1_PRM" base ad:0x4AE07B40 group.long 0x00++0x07 line.long 0x00 "PM_EVE1_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "EVE1_BANK_ONSTATE,EVE1 state when domain is ON" "?,?,?,EVE1_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE1_PWRSTST,This register provides a status on the EVE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE1_BANK_STATEST,EVE0 memory state status - MEM_OFF" "EVE1_BANK_STATEST_0,EVE1_BANK_STATEST_1,EVE1_BANK_STATEST_2,EVE1_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE1_RSTCTRL,This register controls the release of the EVE sub-system resets" bitfld.long 0x00 1. "RST_EVE1,EVE reset control - CLEAR" "RST_EVE1_0,RST_EVE1_1" bitfld.long 0x00 0. "RST_EVE1_LRST,EVE Local reset control - CLEAR" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" line.long 0x04 "RM_EVE1_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE1_EMU_REQ,EVE1 processor has been reset due to EVE emulation reset request driven from EVE1-SS - RESET_NO" "RST_EVE1_EMU_REQ_0,RST_EVE1_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE1_EMU,EVE1 domain has been reset due to emulation reset source e.g" "RST_EVE1_EMU_0,RST_EVE1_EMU_1" newline bitfld.long 0x04 1. "RST_EVE1,EVE0 SW reset status - RESET_NO" "RST_EVE1_0,RST_EVE1_1" bitfld.long 0x04 0. "RST_EVE1_LRST,EVE0 Local SW reset - RESET_NO" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE1_EVE1_WKDEP,This register controls wakeup dependency based on EVE1 service requests" bitfld.long 0x00 9. "WKUPDEP_EVE1_EVE4,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_EVE1_EVE4_0,WKUPDEP_EVE1_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_EVE1_EVE3,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_EVE1_EVE3_0,WKUPDEP_EVE1_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_EVE1_EVE2,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_EVE2_0,WKUPDEP_EVE1_EVE2_1" bitfld.long 0x00 5. "WKUPDEP_EVE1_DSP2,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_DSP2_0,WKUPDEP_EVE1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE1_IPU1,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_IPU1_0,WKUPDEP_EVE1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE1_SDMA,Wakeup dependency from EVE1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_SDMA_0,WKUPDEP_EVE1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE1_DSP1,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_DSP1_0,WKUPDEP_EVE1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE1_IPU2,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE1_IPU2_0,WKUPDEP_EVE1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE1_MPU,Wakeup dependency from EVE1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_MPU_0,WKUPDEP_EVE1_MPU_1" line.long 0x04 "RM_EVE1_EVE1_CONTEXT,This register contains dedicated EVE context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE2_PRM" base ad:0x4AE07B80 group.long 0x00++0x07 line.long 0x00 "PM_EVE2_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "EVE2_BANK_ONSTATE,EVE2 state when domain is ON" "?,?,?,EVE2_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE2_PWRSTST,This register provides a status on the EVE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE2_BANK_STATEST,EVE2 memory state status - MEM_OFF" "EVE2_BANK_STATEST_0,EVE2_BANK_STATEST_1,EVE2_BANK_STATEST_2,EVE2_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE2_RSTCTRL,This register controls the release of the EVE sub-system resets" bitfld.long 0x00 1. "RST_EVE2,EVE SW reset control - CLEAR" "RST_EVE2_0,RST_EVE2_1" bitfld.long 0x00 0. "RST_EVE2_LRST,EVE Local reset control - CLEAR" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" line.long 0x04 "RM_EVE2_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE2_EMU_REQ,EVE2 processor has been reset due to EVE emulation reset request driven from EVE2-SS - RESET_NO" "RST_EVE2_EMU_REQ_0,RST_EVE2_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE2_EMU,EVE2 domain has been reset due to emulation reset source e.g" "RST_EVE2_EMU_0,RST_EVE2_EMU_1" newline bitfld.long 0x04 1. "RST_EVE2,EVE SW reset status - RESET_NO" "RST_EVE2_0,RST_EVE2_1" bitfld.long 0x04 0. "RST_EVE2_LRST,EVE Local SW reset - RESET_NO" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE2_EVE2_WKDEP,This register controls wakeup dependency based on EVE2 service requests" bitfld.long 0x00 9. "WKUPDEP_EVE2_EVE4,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_EVE2_EVE4_0,WKUPDEP_EVE2_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_EVE2_EVE3,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_EVE2_EVE3_0,WKUPDEP_EVE2_EVE3_1" newline bitfld.long 0x00 6. "WKUPDEP_EVE2_EVE1,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_EVE1_0,WKUPDEP_EVE2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE2_DSP2,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_DSP2_0,WKUPDEP_EVE2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE2_IPU1,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_IPU1_0,WKUPDEP_EVE2_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE2_SDMA,Wakeup dependency from EVE2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_SDMA_0,WKUPDEP_EVE2_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE2_DSP1,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_DSP1_0,WKUPDEP_EVE2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE2_IPU2,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE2_IPU2_0,WKUPDEP_EVE2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE2_MPU,Wakeup dependency from EVE2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_MPU_0,WKUPDEP_EVE2_MPU_1" line.long 0x04 "RM_EVE2_EVE2_CONTEXT,This register contains dedicated EVE context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE3_PRM" base ad:0x4AE07BC0 group.long 0x00++0x07 line.long 0x00 "PM_EVE3_PWRSTCTRL,This register controls the ISS power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "EVE3_BANK_ONSTATE,ISS state when domain is ON" "?,?,?,EVE3_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE3_PWRSTST,This register is used to provide a power state status on the EVE3 domain. where the ISS module is implemented" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE3_BANK_STATEST,ISS memory state status - MEM_OFF" "EVE3_BANK_STATEST_0,EVE3_BANK_STATEST_1,EVE3_BANK_STATEST_2,EVE3_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE3_RSTCTRL,This register controls the release of the ISS sub-system resets" bitfld.long 0x00 1. "RST_EVE3,ISS SW reset control - CLEAR" "RST_EVE3_0,RST_EVE3_1" bitfld.long 0x00 0. "RST_EVE3_LRST,ISS Local reset control - CLEAR" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" line.long 0x04 "RM_EVE3_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE3_EMU_REQ,ISS processor has been reset due to ISS emulation reset request driven from ISS - RESET_NO" "RST_EVE3_EMU_REQ_0,RST_EVE3_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE3_EMU,EVE3 domain has been reset due to emulation reset source e.g" "RST_EVE3_EMU_0,RST_EVE3_EMU_1" newline bitfld.long 0x04 1. "RST_EVE3,ISS SW reset status - RESET_NO" "RST_EVE3_0,RST_EVE3_1" bitfld.long 0x04 0. "RST_EVE3_LRST,ISS Local SW reset - RESET_NO" "RST_EVE3_LRST_0,RST_EVE3_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE3_EVE3_WKDEP,This register controls wakeup dependency based on ISS service requests" bitfld.long 0x00 9. "WKUPDEP_EVE3_EVE4,Wakeup dependency from ISS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_EVE3_EVE4_0,WKUPDEP_EVE3_EVE4_1" bitfld.long 0x00 7. "WKUPDEP_EVE3_EVE2,Wakeup dependency from ISS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_EVE2_0,WKUPDEP_EVE3_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_EVE3_EVE1,Wakeup dependency from ISS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_EVE1_0,WKUPDEP_EVE3_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE3_DSP2,Wakeup dependency from ISS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_DSP2_0,WKUPDEP_EVE3_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE3_IPU1,Wakeup dependency from ISS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_IPU1_0,WKUPDEP_EVE3_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE3_SDMA,Wakeup dependency from ISS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_SDMA_0,WKUPDEP_EVE3_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE3_DSP1,Wakeup dependency from ISS module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_DSP1_0,WKUPDEP_EVE3_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE3_IPU2,Wakeup dependency from ISS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE3_IPU2_0,WKUPDEP_EVE3_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE3_MPU,Wakeup dependency from ISS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE3_MPU_0,WKUPDEP_EVE3_MPU_1" line.long 0x04 "RM_EVE3_EVE3_CONTEXT,This register contains dedicated ISS context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in ISS memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "EVE4_PRM" base ad:0x4AE07C00 group.long 0x00++0x07 line.long 0x00 "PM_EVE4_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transitionEVE4 is not supported in this family of devices" rbitfld.long 0x00 16.--17. "EVE4_BANK_ONSTATE,EVE4 state when domain is ON" "?,?,?,EVE4_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE4_PWRSTST,This register provides a status on the EVE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE4_BANK_STATEST,EVE4 memory state status - MEM_OFF" "EVE4_BANK_STATEST_0,EVE4_BANK_STATEST_1,EVE4_BANK_STATEST_2,EVE4_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE4_RSTCTRL,This register controls the release of the EVE sub-system resets.EVE4 is not supported in this family of devices" bitfld.long 0x00 1. "RST_EVE4,EVE SW reset control - CLEAR" "RST_EVE4_0,RST_EVE4_1" bitfld.long 0x00 0. "RST_EVE4_LRST,EVE4 Local reset control - CLEAR" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" line.long 0x04 "RM_EVE4_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE4_EMU_REQ,EVE4 processor has been reset due to EVE emulation reset request driven from EVE4-SS - RESET_NO" "RST_EVE4_EMU_REQ_0,RST_EVE4_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE4_EMU,EVE4 domain has been reset due to emulation reset source e.g" "RST_EVE4_EMU_0,RST_EVE4_EMU_1" newline bitfld.long 0x04 1. "RST_EVE4,EVE4 SW reset status - RESET_NO" "RST_EVE4_0,RST_EVE4_1" bitfld.long 0x04 0. "RST_EVE4_LRST,EVE4 Local SW reset - RESET_NO" "RST_EVE4_LRST_0,RST_EVE4_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE4_EVE4_WKDEP,This register controls wakeup dependency based on EVE4 service requests.EVE4 is not supported in this family of devices" bitfld.long 0x00 8. "WKUPDEP_EVE4_EVE3,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_EVE3_0,WKUPDEP_EVE4_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_EVE4_EVE2,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_EVE2_0,WKUPDEP_EVE4_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_EVE4_EVE1,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_EVE1_0,WKUPDEP_EVE4_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE4_DSP2,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_DSP2_0,WKUPDEP_EVE4_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE4_IPU1,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_IPU1_0,WKUPDEP_EVE4_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE4_SDMA,Wakeup dependency from EVE4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_SDMA_0,WKUPDEP_EVE4_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE4_DSP1,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_DSP1_0,WKUPDEP_EVE4_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE4_IPU2,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_EVE4_IPU2_0,WKUPDEP_EVE4_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE4_MPU,Wakeup dependency from EVE4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE4_MPU_0,WKUPDEP_EVE4_MPU_1" line.long 0x04 "RM_EVE4_EVE4_CONTEXT,This register contains dedicated EVE context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE4 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "GPU_PRM" base ad:0x4AE07200 group.long 0x00++0x07 line.long 0x00 "PM_GPU_PWRSTCTRL,This register controls the GPU power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "GPU_MEM_ONSTATE,GPU_MEM memory bank state when domain is ON" "?,?,?,GPU_MEM_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_GPU_PWRSTST,This register provides a status on the current GPU power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "GPU_MEM_STATEST,GPU_MEM memory bank state status - MEM_OFF" "GPU_MEM_STATEST_0,GPU_MEM_STATEST_1,GPU_MEM_STATEST_2,GPU_MEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_GPU_GPU_CONTEXT,This register contains dedicated GPU context statuses" bitfld.long 0x00 8. "LOSTMEM_GPU_MEM,Specify if memory-based context in GPU_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GPU_MEM_0,LOSTMEM_GPU_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "INSTR_PRM" base ad:0x4AE07F00 rgroup.long 0x00++0x03 line.long 0x00 "PMI_IDENTICATION,PM profiling identification register" group.long 0x10++0x07 line.long 0x00 "PMI_SYS_CONFIG,PM profiling system configuartion register" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local tartget state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "PMI_STATUS,PM profiling status register" bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "FIFOEMPTY_0,FIFOEMPTY_1" group.long 0x24++0x0F line.long 0x00 "PMI_CONFIGURATION,PM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "CLAIM_3_0,CLAIM_3_1,CLAIM_3_2,CLAIM_3_3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "CLAIM_2_0,CLAIM_2_1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "CLAIM_1_0,CLAIM_1_1" newline bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the PM events capture is enabled" "EVT_CAPT_EN_0,EVT_CAPT_EN_1" line.long 0x04 "PMI_CLASS_FILTERING,PM profiling class filtering register" bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03" "SNAP_CAPT_EN_03_0,SNAP_CAPT_EN_03_1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02" "SNAP_CAPT_EN_02_0,SNAP_CAPT_EN_02_1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01" "SNAP_CAPT_EN_01_0,SNAP_CAPT_EN_01_1" newline bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00" "SNAP_CAPT_EN_00_0,SNAP_CAPT_EN_00_1" line.long 0x08 "PMI_TRIGGERING,PM profiling triggering control register" bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing PM events from external trigger detection" "TRIG_STOP_EN_0,TRIG_STOP_EN_1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing PM events from external trigger detection" "TRIG_START_EN_0,TRIG_START_EN_1" line.long 0x0C "PMI_SAMPLING,PM profiling sampling window register" bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "FCLK_DIV_FACOR_0,FCLK_DIV_FACOR_1,FCLK_DIV_FACOR_2,FCLK_DIV_FACOR_3,FCLK_DIV_FACOR_4,FCLK_DIV_FACOR_5,FCLK_DIV_FACOR_6,FCLK_DIV_FACOR_7,FCLK_DIV_FACOR_8,FCLK_DIV_FACOR_9,FCLK_DIV_FACOR_10,FCLK_DIV_FACOR_11,FCLK_DIV_FACOR_12,FCLK_DIV_FACOR_13,FCLK_DIV_FACOR_14,FCLK_DIV_FACOR_15" hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,PM events sampling window size" width 0x0B tree.end tree "IPU_PRM" base ad:0x4AE06500 group.long 0x00++0x07 line.long 0x00 "PM_IPU_PWRSTCTRL,This register controls the IPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "PERIPHMEM_ONSTATE,PERIPHMEM memory state when domain is ON" "?,?,?,PERIPHMEM_ONSTATE_3" rbitfld.long 0x00 16.--17. "AESSMEM_ONSTATE,AESSMEM memory state when domain is ON" "?,?,?,AESSMEM_ONSTATE_3" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IPU_PWRSTST,This register provides a status on the IPU domain current power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "PERIPHMEM_STATEST,PERIPHMEM memory state status - MEM_OFF" "PERIPHMEM_STATEST_0,PERIPHMEM_STATEST_1,PERIPHMEM_STATEST_2,PERIPHMEM_STATEST_3" rbitfld.long 0x04 4.--5. "AESSMEM_STATEST,AESSMEM memory state status - MEM_OFF" "AESSMEM_STATEST_0,AESSMEM_STATEST_1,AESSMEM_STATEST_2,AESSMEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IPU1_RSTCTRL,This register controls the release of the IPU1 sub-system resets" bitfld.long 0x00 2. "RST_IPU,IPU system reset control" "RST_IPU_0,RST_IPU_1" bitfld.long 0x00 1. "RST_CPU1,IPU Cortex M4 CPU1 reset control - CLEAR" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x00 0. "RST_CPU0,IPU Cortex M4 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU1_RSTST,This register logs the different reset sources of the IPU1 SS" bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M4 CPU1 has been reset due to IPU ICECRUSHER1 reset source - RESET_NO" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M4 CPU0 has been reset due to IPU ICECRUSHER0 reset source - RESET_NO" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" newline bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M4 CPU1 has been reset due to emulation reset source for example assert reset command initiated by the icepick module - RESET_NO" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M4 CPU0 has been reset due to emulation reset source for example assert reset command initiated by the icepick module - RESET_NO" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" newline bitfld.long 0x04 2. "RST_IPU,IPU system software reset status - RESET_NO" "RST_IPU_0,RST_IPU_1" bitfld.long 0x04 1. "RST_CPU1,IPU Cortex-M4 CPU1 software reset status - RESET_NO" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x04 0. "RST_CPU0,IPU Cortex-M4 CPU0 software reset status - RESET_NO" "RST_CPU0_0,RST_CPU0_1" group.long 0x24++0x03 line.long 0x00 "RM_IPU1_IPU1_CONTEXT,This register contains dedicated IPU1 context statuses" bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x37 line.long 0x00 "PM_IPU_MCASP1_WKDEP,This register controls wakeup dependency based on MCASP1 service requests" bitfld.long 0x00 15. "WKUPDEP_MCASP1_DMA_DSP2,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_DMA_DSP2_0,WKUPDEP_MCASP1_DMA_DSP2_1" bitfld.long 0x00 13. "WKUPDEP_MCASP1_DMA_SDMA,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_DMA_SDMA_0,WKUPDEP_MCASP1_DMA_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_MCASP1_DMA_DSP1,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_DMA_DSP1_0,WKUPDEP_MCASP1_DMA_DSP1_1" bitfld.long 0x00 9. "WKUPDEP_MCASP1_IRQ_EVE4,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP1_IRQ_EVE4_0,WKUPDEP_MCASP1_IRQ_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_MCASP1_IRQ_EVE3,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP1_IRQ_EVE3_0,WKUPDEP_MCASP1_IRQ_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_MCASP1_IRQ_EVE2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_EVE2_0,WKUPDEP_MCASP1_IRQ_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MCASP1_IRQ_EVE1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_EVE1_0,WKUPDEP_MCASP1_IRQ_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MCASP1_IRQ_DSP2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_DSP2_0,WKUPDEP_MCASP1_IRQ_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MCASP1_IRQ_IPU1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_IPU1_0,WKUPDEP_MCASP1_IRQ_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_MCASP1_IRQ_DSP1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_DSP1_0,WKUPDEP_MCASP1_IRQ_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCASP1_IRQ_IPU2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCASP1_IRQ_IPU2_0,WKUPDEP_MCASP1_IRQ_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCASP1_IRQ_MPU,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_MPU_0,WKUPDEP_MCASP1_IRQ_MPU_1" line.long 0x04 "RM_IPU_MCASP1_CONTEXT,This register contains dedicated McASP context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_IPU_TIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests" bitfld.long 0x08 9. "WKUPDEP_TIMER5_EVE4,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER5_EVE4_0,WKUPDEP_TIMER5_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_TIMER5_EVE3,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER5_EVE3_0,WKUPDEP_TIMER5_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_TIMER5_EVE2,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_EVE2_0,WKUPDEP_TIMER5_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TIMER5_EVE1,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_EVE1_0,WKUPDEP_TIMER5_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TIMER5_DSP2,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_DSP2_0,WKUPDEP_TIMER5_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TIMER5_IPU1,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_IPU1_0,WKUPDEP_TIMER5_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER5_DSP1,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_DSP1_0,WKUPDEP_TIMER5_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER5_IPU2,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER5_IPU2_0,WKUPDEP_TIMER5_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER5_MPU,Wakeup dependency from TIMER5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_MPU_0,WKUPDEP_TIMER5_MPU_1" line.long 0x0C "RM_IPU_TIMER5_CONTEXT,This register contains dedicated TIMER5 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_IPU_TIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests" bitfld.long 0x10 9. "WKUPDEP_TIMER6_EVE4,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER6_EVE4_0,WKUPDEP_TIMER6_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_TIMER6_EVE3,Wakeup dependency from TIMER6 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER6_EVE3_0,WKUPDEP_TIMER6_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_TIMER6_EVE2,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_EVE2_0,WKUPDEP_TIMER6_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER6_EVE1,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_EVE1_0,WKUPDEP_TIMER6_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER6_DSP2,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_DSP2_0,WKUPDEP_TIMER6_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER6_IPU1,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_IPU1_0,WKUPDEP_TIMER6_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER6_DSP1,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_DSP1_0,WKUPDEP_TIMER6_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER6_IPU2,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER6_IPU2_0,WKUPDEP_TIMER6_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER6_MPU,Wakeup dependency from TIMER6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_MPU_0,WKUPDEP_TIMER6_MPU_1" line.long 0x14 "RM_IPU_TIMER6_CONTEXT,This register contains dedicated TIMER6 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_IPU_TIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests" bitfld.long 0x18 9. "WKUPDEP_TIMER7_EVE4,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER7_EVE4_0,WKUPDEP_TIMER7_EVE4_1" bitfld.long 0x18 8. "WKUPDEP_TIMER7_EVE3,Wakeup dependency from TIMER7 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER7_EVE3_0,WKUPDEP_TIMER7_EVE3_1" newline bitfld.long 0x18 7. "WKUPDEP_TIMER7_EVE2,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_EVE2_0,WKUPDEP_TIMER7_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER7_EVE1,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_EVE1_0,WKUPDEP_TIMER7_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER7_DSP2,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_DSP2_0,WKUPDEP_TIMER7_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER7_IPU1,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_IPU1_0,WKUPDEP_TIMER7_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER7_DSP1,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_DSP1_0,WKUPDEP_TIMER7_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER7_IPU2,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER7_IPU2_0,WKUPDEP_TIMER7_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER7_MPU,Wakeup dependency from TIMER7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_MPU_0,WKUPDEP_TIMER7_MPU_1" line.long 0x1C "RM_IPU_TIMER7_CONTEXT,This register contains dedicated TIMER7 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_IPU_TIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests" bitfld.long 0x20 9. "WKUPDEP_TIMER8_EVE4,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER8_EVE4_0,WKUPDEP_TIMER8_EVE4_1" bitfld.long 0x20 8. "WKUPDEP_TIMER8_EVE3,Wakeup dependency from TIMER8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER8_EVE3_0,WKUPDEP_TIMER8_EVE3_1" newline bitfld.long 0x20 7. "WKUPDEP_TIMER8_EVE2,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_EVE2_0,WKUPDEP_TIMER8_EVE2_1" bitfld.long 0x20 6. "WKUPDEP_TIMER8_EVE1,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_EVE1_0,WKUPDEP_TIMER8_EVE1_1" newline bitfld.long 0x20 5. "WKUPDEP_TIMER8_DSP2,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_DSP2_0,WKUPDEP_TIMER8_DSP2_1" bitfld.long 0x20 4. "WKUPDEP_TIMER8_IPU1,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_IPU1_0,WKUPDEP_TIMER8_IPU1_1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER8_DSP1,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_DSP1_0,WKUPDEP_TIMER8_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER8_IPU2,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER8_IPU2_0,WKUPDEP_TIMER8_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER8_MPU,Wakeup dependency from TIMER8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_MPU_0,WKUPDEP_TIMER8_MPU_1" line.long 0x24 "RM_IPU_TIMER8_CONTEXT,This register contains dedicated TIMER8 context statuses" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_IPU_I2C5_WKDEP,This register controls wakeup dependency based on I2C5 service requests" bitfld.long 0x28 15. "WKUPDEP_I2C5_DMA_DSP2,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_DMA_DSP2_0,WKUPDEP_I2C5_DMA_DSP2_1" bitfld.long 0x28 13. "WKUPDEP_I2C5_DMA_SDMA,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_DMA_SDMA_0,WKUPDEP_I2C5_DMA_SDMA_1" newline bitfld.long 0x28 12. "WKUPDEP_I2C5_DMA_DSP1,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_DMA_DSP1_0,WKUPDEP_I2C5_DMA_DSP1_1" bitfld.long 0x28 9. "WKUPDEP_I2C5_IRQ_EVE4,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_I2C5_IRQ_EVE4_0,WKUPDEP_I2C5_IRQ_EVE4_1" newline bitfld.long 0x28 8. "WKUPDEP_I2C5_IRQ_EVE3,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_I2C5_IRQ_EVE3_0,WKUPDEP_I2C5_IRQ_EVE3_1" bitfld.long 0x28 7. "WKUPDEP_I2C5_IRQ_EVE2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_EVE2_0,WKUPDEP_I2C5_IRQ_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_I2C5_IRQ_EVE1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_EVE1_0,WKUPDEP_I2C5_IRQ_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_I2C5_IRQ_DSP2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_DSP2_0,WKUPDEP_I2C5_IRQ_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_I2C5_IRQ_IPU1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_IPU1_0,WKUPDEP_I2C5_IRQ_IPU1_1" bitfld.long 0x28 2. "WKUPDEP_I2C5_IRQ_DSP1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_DSP1_0,WKUPDEP_I2C5_IRQ_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_I2C5_IRQ_IPU2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C5_IRQ_IPU2_0,WKUPDEP_I2C5_IRQ_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_I2C5_IRQ_MPU,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_MPU_0,WKUPDEP_I2C5_IRQ_MPU_1" line.long 0x2C "RM_IPU_I2C5_CONTEXT,This register contains dedicated I2C5 context statuses" bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x30 "PM_IPU_UART6_WKDEP,This register controls wakeup dependency based on UART6 service requests" bitfld.long 0x30 9. "WKUPDEP_UART6_EVE4,Wakeup dependency from UART6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART6_EVE4_0,WKUPDEP_UART6_EVE4_1" bitfld.long 0x30 8. "WKUPDEP_UART6_EVE3,Wakeup dependency from UART6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART6_EVE3_0,WKUPDEP_UART6_EVE3_1" newline bitfld.long 0x30 7. "WKUPDEP_UART6_EVE2,Wakeup dependency from UART6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_EVE2_0,WKUPDEP_UART6_EVE2_1" bitfld.long 0x30 6. "WKUPDEP_UART6_EVE1,Wakeup dependency from UART6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_EVE1_0,WKUPDEP_UART6_EVE1_1" newline bitfld.long 0x30 5. "WKUPDEP_UART6_DSP2,Wakeup dependency from UART6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_DSP2_0,WKUPDEP_UART6_DSP2_1" bitfld.long 0x30 4. "WKUPDEP_UART6_IPU1,Wakeup dependency from UART6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_IPU1_0,WKUPDEP_UART6_IPU1_1" newline bitfld.long 0x30 3. "WKUPDEP_UART6_SDMA,Wakeup dependency from UART6 module (SWakeup signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_SDMA_0,WKUPDEP_UART6_SDMA_1" bitfld.long 0x30 2. "WKUPDEP_UART6_DSP1,Wakeup dependency from UART6 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_DSP1_0,WKUPDEP_UART6_DSP1_1" newline bitfld.long 0x30 1. "WKUPDEP_UART6_IPU2,Wakeup dependency from UART6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART6_IPU2_0,WKUPDEP_UART6_IPU2_1" bitfld.long 0x30 0. "WKUPDEP_UART6_MPU,Wakeup dependency from UART6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_MPU_0,WKUPDEP_UART6_MPU_1" line.long 0x34 "RM_IPU_UART6_CONTEXT,This register contains dedicated UART6 context statuses" bitfld.long 0x34 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x34 1. "LOSTCONTEXT_RFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" width 0x0B tree.end tree "IVA_PRM" base ad:0x4AE06F00 group.long 0x00++0x07 line.long 0x00 "PM_IVA_PWRSTCTRL,This register controls the IVA power state to reach upon a domain sleep transition" rbitfld.long 0x00 22.--23. "TCM2_MEM_ONSTATE,TCM_CORE memory state when domain is ON" "?,?,?,TCM2_MEM_ONSTATE_3" rbitfld.long 0x00 20.--21. "TCM1_MEM_ONSTATE,TCM1 memory state when domain is ON" "?,?,?,TCM1_MEM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "SL2_MEM_ONSTATE,SL2 memory state when domain is ON" "?,?,?,SL2_MEM_ONSTATE_3" rbitfld.long 0x00 16.--17. "HWA_MEM_ONSTATE,HWA memory state when domain is ON" "?,?,?,HWA_MEM_ONSTATE_3" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IVA_PWRSTST,This register provides a status on the current IVA power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 10.--11. "TCM2_MEM_STATEST,TCM2 memory state status - MEM_OFF" "TCM2_MEM_STATEST_0,TCM2_MEM_STATEST_1,TCM2_MEM_STATEST_2,TCM2_MEM_STATEST_3" rbitfld.long 0x04 8.--9. "TCM1_MEM_STATEST,TCM1 memory state status - MEM_OFF" "TCM1_MEM_STATEST_0,TCM1_MEM_STATEST_1,TCM1_MEM_STATEST_2,TCM1_MEM_STATEST_3" newline rbitfld.long 0x04 6.--7. "SL2_MEM_STATEST,SL2 memory state status - MEM_OFF" "SL2_MEM_STATEST_0,SL2_MEM_STATEST_1,SL2_MEM_STATEST_2,SL2_MEM_STATEST_3" rbitfld.long 0x04 4.--5. "HWA_MEM_STATEST,HWA memory state status - MEM_OFF" "HWA_MEM_STATEST_0,HWA_MEM_STATEST_1,HWA_MEM_STATEST_2,HWA_MEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IVA_RSTCTRL,This register controls the release of the IVA sub-system resets" bitfld.long 0x00 2. "RST_LOGIC,IVA logic and SL2 reset control - CLEAR" "RST_LOGIC_0,RST_LOGIC_1" bitfld.long 0x00 1. "RST_SEQ2,IVA Sequencer2 reset control - CLEAR" "RST_SEQ2_0,RST_SEQ2_1" newline bitfld.long 0x00 0. "RST_SEQ1,IVA sequencer1 reset control - CLEAR" "RST_SEQ1_0,RST_SEQ1_1" line.long 0x04 "RM_IVA_RSTST,This register logs the different reset sources of the IVA domain" bitfld.long 0x04 6. "RST_ICECRUSHER_SEQ2,Sequencer2 CPU has been reset due to IVA ICECRUSHER2 reset event - RESET_NO" "RST_ICECRUSHER_SEQ2_0,RST_ICECRUSHER_SEQ2_1" bitfld.long 0x04 5. "RST_ICECRUSHER_SEQ1,Sequencer1 CPU has been reset due to IVA ICECRUSHER1 reset event - RESET_NO" "RST_ICECRUSHER_SEQ1_0,RST_ICECRUSHER_SEQ1_1" newline bitfld.long 0x04 4. "RST_EMULATION_SEQ2,Sequencer2 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ2_0,RST_EMULATION_SEQ2_1" bitfld.long 0x04 3. "RST_EMULATION_SEQ1,Sequencer1 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ1_0,RST_EMULATION_SEQ1_1" newline bitfld.long 0x04 2. "RST_LOGIC,IVA logic and SL2 SW reset - RESET_NO" "RST_LOGIC_0,RST_LOGIC_1" bitfld.long 0x04 1. "RST_SEQ2,IVA Sequencer2 CPU SW reset - RESET_NO" "RST_SEQ2_0,RST_SEQ2_1" newline bitfld.long 0x04 0. "RST_SEQ1,IVA Sequencer1 CPU SW reset - RESET_NO" "RST_SEQ1_0,RST_SEQ1_1" group.long 0x24++0x03 line.long 0x00 "RM_IVA_IVA_CONTEXT,This register contains dedicated IVA context statuses" bitfld.long 0x00 10. "LOSTMEM_HWA_MEM,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_HWA_MEM_0,LOSTMEM_HWA_MEM_1" bitfld.long 0x00 9. "LOSTMEM_TCM2_MEM,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM2_MEM_0,LOSTMEM_TCM2_MEM_1" newline bitfld.long 0x00 8. "LOSTMEM_TCM1_MEM,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM1_MEM_0,LOSTMEM_TCM1_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_IVA_SL2_CONTEXT,This register contains dedicated SL2 context statuses" bitfld.long 0x00 8. "LOSTMEM_SL2_MEM,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_SL2_MEM_0,LOSTMEM_SL2_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "L3INIT_PRM" base ad:0x4AE07300 group.long 0x00++0x07 line.long 0x00 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition Note: In the L3INIT power domain OFF state is only allowed in systems where Ethernet RGMII is NOT used in the system - this is very application.." rbitfld.long 0x00 18.--19. "GMAC_BANK_ONSTATE,GMAC BANK state when domain is ON" "?,?,?,GMAC_BANK_ONSTATE_3" rbitfld.long 0x00 16.--17. "L3INIT_BANK2_ONSTATE,L3INIT BANK2 state when domain is ON" "?,?,?,L3INIT_BANK2_ONSTATE_3" newline rbitfld.long 0x00 14.--15. "L3INIT_BANK1_ONSTATE,L3INIT BANK1 state when domain is ON" "?,?,?,L3INIT_BANK1_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "L3INIT_GMAC_STATEST,L3INIT GMAC state status - MEM_OFF" "L3INIT_GMAC_STATEST_0,L3INIT_GMAC_STATEST_1,L3INIT_GMAC_STATEST_2,L3INIT_GMAC_STATEST_3" rbitfld.long 0x04 6.--7. "L3INIT_BANK2_STATEST,L3INIT BANK2 state status - MEM_OFF" "L3INIT_BANK2_STATEST_0,L3INIT_BANK2_STATEST_1,L3INIT_BANK2_STATEST_2,L3INIT_BANK2_STATEST_3" newline rbitfld.long 0x04 4.--5. "L3INIT_BANK1_STATEST,L3INIT BANK1 state status - MEM_OFF" "L3INIT_BANK1_STATEST_0,L3INIT_BANK1_STATEST_1,L3INIT_BANK1_STATEST_2,L3INIT_BANK1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_PCIESS_RSTCTRL,This register controls the release of the PCIESS local reset" bitfld.long 0x00 0. "RST_LOCAL_PCIE1,PCIESS1 local reset control - CLEAR" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" line.long 0x04 "RM_PCIESS_RSTST,This register logs the different reset sources of the PCIESS domain" bitfld.long 0x04 0. "RST_LOCAL_PCIE1,PCIESS1 local SW reset - RESET_NO" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" group.long 0x28++0x0F line.long 0x00 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests" bitfld.long 0x00 9. "WKUPDEP_MMC1_EVE4,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MMC1_EVE4_0,WKUPDEP_MMC1_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_MMC1_EVE3,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MMC1_EVE3_0,WKUPDEP_MMC1_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_MMC1_EVE2,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_EVE2_0,WKUPDEP_MMC1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MMC1_EVE1,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_EVE1_0,WKUPDEP_MMC1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MMC1_DSP2,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_DSP2_0,WKUPDEP_MMC1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MMC1_IPU1,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_IPU1_0,WKUPDEP_MMC1_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_MMC1_SDMA,Wakeup dependency from MMC1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_SDMA_0,WKUPDEP_MMC1_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_MMC1_DSP1,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_DSP1_0,WKUPDEP_MMC1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MMC1_IPU2,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_IPU2_0,WKUPDEP_MMC1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MMC1_MPU,Wakeup dependency from MMC1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_MPU_0,WKUPDEP_MMC1_MPU_1" line.long 0x04 "RM_L3INIT_MMC1_CONTEXT,This register contains dedicated MMC1 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests" bitfld.long 0x08 9. "WKUPDEP_MMC2_EVE4,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MMC2_EVE4_0,WKUPDEP_MMC2_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_MMC2_EVE3,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MMC2_EVE3_0,WKUPDEP_MMC2_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_MMC2_EVE2,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_EVE2_0,WKUPDEP_MMC2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_MMC2_EVE1,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_EVE1_0,WKUPDEP_MMC2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_MMC2_DSP2,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_DSP2_0,WKUPDEP_MMC2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_MMC2_IPU1,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_IPU1_0,WKUPDEP_MMC2_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_MMC2_SDMA,Wakeup dependency from MMC2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_SDMA_0,WKUPDEP_MMC2_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_MMC2_DSP1,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_DSP1_0,WKUPDEP_MMC2_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_MMC2_IPU2,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_IPU2_0,WKUPDEP_MMC2_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_MMC2_MPU,Wakeup dependency from MMC2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_MPU_0,WKUPDEP_MMC2_MPU_1" line.long 0x0C "RM_L3INIT_MMC2_CONTEXT,This register contains dedicated MMC2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x40++0x17 line.long 0x00 "PM_L3INIT_USB_OTG_SS2_WKDEP,This register controls wakeup dependency based on USB_OTG_SS2 service requests" bitfld.long 0x00 9. "WKUPDEP_USB_OTG_SS2_EVE4,Wakeup dependency from USB2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS2_EVE4_0,WKUPDEP_USB_OTG_SS2_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_USB_OTG_SS2_EVE3,Wakeup dependency from USB2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS2_EVE3_0,WKUPDEP_USB_OTG_SS2_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_USB_OTG_SS2_EVE2,Wakeup dependency from USB2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_EVE2_0,WKUPDEP_USB_OTG_SS2_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_USB_OTG_SS2_EVE1,Wakeup dependency from USB2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_EVE1_0,WKUPDEP_USB_OTG_SS2_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_USB_OTG_SS2_DSP2,Wakeup dependency from USB2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_DSP2_0,WKUPDEP_USB_OTG_SS2_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_USB_OTG_SS2_IPU1,Wakeup dependency from USB2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_IPU1_0,WKUPDEP_USB_OTG_SS2_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_USB_OTG_SS2_DSP1,Wakeup dependency from USB2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_DSP1_0,WKUPDEP_USB_OTG_SS2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_USB_OTG_SS2_IPU2,Wakeup dependency from USB2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_IPU2_0,WKUPDEP_USB_OTG_SS2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_USB_OTG_SS2_MPU,Wakeup dependency from USB2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_MPU_0,WKUPDEP_USB_OTG_SS2_MPU_1" line.long 0x04 "RM_L3INIT_USB_OTG_SS2_CONTEXT,This register contains dedicated USB_OTG_SS2 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3INIT_USB_OTG_SS3_WKDEP,This register controls wakeup dependency based on USB_OTG_SS3 service requests" bitfld.long 0x08 9. "WKUPDEP_USB_OTG_SS3_EVE4,Wakeup dependency from USB3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS3_EVE4_0,WKUPDEP_USB_OTG_SS3_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_USB_OTG_SS3_EVE3,Wakeup dependency from USB3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS3_EVE3_0,WKUPDEP_USB_OTG_SS3_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_USB_OTG_SS3_EVE2,Wakeup dependency from USB3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_EVE2_0,WKUPDEP_USB_OTG_SS3_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_USB_OTG_SS3_EVE1,Wakeup dependency from USB3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_EVE1_0,WKUPDEP_USB_OTG_SS3_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_USB_OTG_SS3_DSP2,Wakeup dependency from USB3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_DSP2_0,WKUPDEP_USB_OTG_SS3_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_USB_OTG_SS3_IPU1,Wakeup dependency from USB3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_IPU1_0,WKUPDEP_USB_OTG_SS3_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_USB_OTG_SS3_DSP1,Wakeup dependency from USB3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_DSP1_0,WKUPDEP_USB_OTG_SS3_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_USB_OTG_SS3_IPU2,Wakeup dependency from USB3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_IPU2_0,WKUPDEP_USB_OTG_SS3_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_USB_OTG_SS3_MPU,Wakeup dependency from USB3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_MPU_0,WKUPDEP_USB_OTG_SS3_MPU_1" line.long 0x0C "RM_L3INIT_USB_OTG_SS3_CONTEXT,This register contains dedicated USB_OTG_SS3 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x10 "PM_L3INIT_USB_OTG_SS4_WKDEP,This register controls wakeup dependency based on USB_OTG_SS4 service requests" bitfld.long 0x10 9. "WKUPDEP_USB_OTG_SS4_EVE4,Wakeup dependency from USB4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS4_EVE4_0,WKUPDEP_USB_OTG_SS4_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_USB_OTG_SS4_EVE3,Wakeup dependency from USB4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS4_EVE3_0,WKUPDEP_USB_OTG_SS4_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_USB_OTG_SS4_EVE2,Wakeup dependency from USB4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_EVE2_0,WKUPDEP_USB_OTG_SS4_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_USB_OTG_SS4_EVE1,Wakeup dependency from USB4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_EVE1_0,WKUPDEP_USB_OTG_SS4_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_USB_OTG_SS4_DSP2,Wakeup dependency from USB4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_DSP2_0,WKUPDEP_USB_OTG_SS4_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_USB_OTG_SS4_IPU1,Wakeup dependency from USB4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_IPU1_0,WKUPDEP_USB_OTG_SS4_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_USB_OTG_SS4_DSP1,Wakeup dependency from USB4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_DSP1_0,WKUPDEP_USB_OTG_SS4_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_USB_OTG_SS4_IPU2,Wakeup dependency from USB4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_IPU2_0,WKUPDEP_USB_OTG_SS4_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_USB_OTG_SS4_MPU,Wakeup dependency from USB4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_MPU_0,WKUPDEP_USB_OTG_SS4_MPU_1" line.long 0x14 "RM_L3INIT_USB_OTG_SS4_CONTEXT,This register contains dedicated USB_OTG_SS4 context statuses" bitfld.long 0x14 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x7C++0x03 line.long 0x00 "RM_L3INIT_IEEE1500_2_OCP_CONTEXT,This register contains dedicated IEEE1500_2_OCP context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x88++0x07 line.long 0x00 "PM_L3INIT_SATA_WKDEP,This register controls wakeup dependency based on SATA service requests" bitfld.long 0x00 9. "WKUPDEP_SATA_EVE4,Wakeup dependency from SATA module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_SATA_EVE4_0,WKUPDEP_SATA_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_SATA_EVE3,Wakeup dependency from SATA module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_SATA_EVE3_0,WKUPDEP_SATA_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_SATA_EVE2,Wakeup dependency from SATA module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_EVE2_0,WKUPDEP_SATA_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_SATA_EVE1,Wakeup dependency from SATA module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_EVE1_0,WKUPDEP_SATA_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SATA_DSP2,Wakeup dependency from SATA module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_DSP2_0,WKUPDEP_SATA_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_SATA_IPU1,Wakeup dependency from SATA module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_IPU1_0,WKUPDEP_SATA_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SATA_DSP1,Wakeup dependency from SATA module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_DSP1_0,WKUPDEP_SATA_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_SATA_IPU2,Wakeup dependency from SATA module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_IPU2_0,WKUPDEP_SATA_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SATA_MPU,Wakeup dependency from SATA module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains - DISABLED" "WKUPDEP_SATA_MPU_0,WKUPDEP_SATA_MPU_1" line.long 0x04 "RM_L3INIT_SATA_CONTEXT,This register contains dedicated SATA context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x0F line.long 0x00 "PM_PCIE_PCIESS1_WKDEP,This register controls wakeup dependency based on PCIESS1 service requests" bitfld.long 0x00 9. "WKUPDEP_PCIESS1_EVE4,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_PCIESS1_EVE4_0,WKUPDEP_PCIESS1_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_PCIESS1_EVE3,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_PCIESS1_EVE3_0,WKUPDEP_PCIESS1_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_PCIESS1_EVE2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_EVE2_0,WKUPDEP_PCIESS1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_PCIESS1_EVE1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_EVE1_0,WKUPDEP_PCIESS1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_PCIESS1_DSP2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_DSP2_0,WKUPDEP_PCIESS1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_PCIESS1_IPU1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_IPU1_0,WKUPDEP_PCIESS1_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_PCIESS1_DSP1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_DSP1_0,WKUPDEP_PCIESS1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_PCIESS1_IPU2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_PCIESS1_IPU2_0,WKUPDEP_PCIESS1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_PCIESS1_MPU,Wakeup dependency from PCIESS1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_MPU_0,WKUPDEP_PCIESS1_MPU_1" line.long 0x04 "RM_PCIE_PCIESS1_CONTEXT,This register contains dedicated PCIESS1 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_PCIE_PCIESS2_WKDEP,This register controls wakeup dependency based on PCIESS2 service requests" bitfld.long 0x08 9. "WKUPDEP_PCIESS2_EVE4,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_PCIESS2_EVE4_0,WKUPDEP_PCIESS2_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_PCIESS2_EVE3,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_PCIESS2_EVE3_0,WKUPDEP_PCIESS2_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_PCIESS2_EVE2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_EVE2_0,WKUPDEP_PCIESS2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_PCIESS2_EVE1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_EVE1_0,WKUPDEP_PCIESS2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_PCIESS2_DSP2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_DSP2_0,WKUPDEP_PCIESS2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_PCIESS2_IPU1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_IPU1_0,WKUPDEP_PCIESS2_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_PCIESS2_DSP1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_DSP1_0,WKUPDEP_PCIESS2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_PCIESS2_IPU2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_IPU2_0,WKUPDEP_PCIESS2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_PCIESS2_MPU,Wakeup dependency from PCIESS2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_MPU_0,WKUPDEP_PCIESS2_MPU_1" line.long 0x0C "RM_PCIE_PCIESS2_CONTEXT,This register contains dedicated PCIESS2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_GMAC_GMAC_CONTEXT,This register contains dedicated GMAC context statuses" bitfld.long 0x00 8. "LOSTMEM_GMAC_BANK,Specify if memory-based context in GMAC_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GMAC_BANK_0,LOSTMEM_GMAC_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xE4++0x03 line.long 0x00 "RM_L3INIT_OCP2SCP1_CONTEXT,This register contains dedicated OCP2SCP1 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xEC++0x0B line.long 0x00 "RM_L3INIT_OCP2SCP3_CONTEXT,This register contains dedicated OCP2SCP3 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3INIT_USB_OTG_SS1_WKDEP,This register controls wakeup dependency based on USB_OTG_SS1 service requests" bitfld.long 0x04 9. "WKUPDEP_USB_OTG_SS1_EVE4,Wakeup dependency from USB1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS1_EVE4_0,WKUPDEP_USB_OTG_SS1_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_USB_OTG_SS1_EVE3,Wakeup dependency from USB1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_USB_OTG_SS1_EVE3_0,WKUPDEP_USB_OTG_SS1_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_USB_OTG_SS1_EVE2,Wakeup dependency from USB1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_EVE2_0,WKUPDEP_USB_OTG_SS1_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_USB_OTG_SS1_EVE1,Wakeup dependency from USB1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_EVE1_0,WKUPDEP_USB_OTG_SS1_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_USB_OTG_SS1_DSP2,Wakeup dependency from USB1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_DSP2_0,WKUPDEP_USB_OTG_SS1_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_USB_OTG_SS1_IPU1,Wakeup dependency from USB1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_IPU1_0,WKUPDEP_USB_OTG_SS1_IPU1_1" newline bitfld.long 0x04 2. "WKUPDEP_USB_OTG_SS1_DSP1,Wakeup dependency from USB1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_DSP1_0,WKUPDEP_USB_OTG_SS1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_USB_OTG_SS1_IPU2,Wakeup dependency from USB1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_IPU2_0,WKUPDEP_USB_OTG_SS1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_USB_OTG_SS1_MPU,Wakeup dependency from USB1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_MPU_0,WKUPDEP_USB_OTG_SS1_MPU_1" line.long 0x08 "RM_L3INIT_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG_SS1 context statuses" bitfld.long 0x08 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" width 0x0B tree.end tree "L4PER_PRM" base ad:0x4AE07400 group.long 0x00++0x07 line.long 0x00 "PM_L4PER_PWRSTCTRL,This register controls the L4PER power state to reach upon a domain sleep transition" rbitfld.long 0x00 18.--19. "NONRETAINED_BANK_ONSTATE,NONRETAINED_BANK state when domain is ON" "?,?,?,NONRETAINED_BANK_ONSTATE_3" rbitfld.long 0x00 16.--17. "RETAINED_BANK_ONSTATE,RETAINED_BANK state when domain is ON" "?,?,?,RETAINED_BANK_ONSTATE_3" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L4PER_PWRSTST,This register provides a status on the current L4PER power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 6.--7. "NONRETAINED_BANK_STATEST,NONRETAINED_BANK state status - MEM_OFF" "NONRETAINED_BANK_STATEST_0,NONRETAINED_BANK_STATEST_1,NONRETAINED_BANK_STATEST_2,NONRETAINED_BANK_STATEST_3" rbitfld.long 0x04 4.--5. "RETAINED_BANK_STATEST,RETAINED_BANK state status - MEM_OFF" "RETAINED_BANK_STATEST_0,RETAINED_BANK_STATEST_1,RETAINED_BANK_STATEST_2,RETAINED_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - RESERVED" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x0C++0x03 line.long 0x00 "RM_L4PER2_L4PER2_CONTEXT,This register contains dedicated L4_PER2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x14++0x03 line.long 0x00 "RM_L4PER3_L4PER3_CONTEXT,This register contains dedicated L4_PER3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C++0x03 line.long 0x00 "RM_L4PER2_PRUSS1_CONTEXT,This register contains dedicated PRU-ICSS1 context statuses" bitfld.long 0x00 8. "LOSTMEM_PRUSS1_BANK,Specify if memory-based context in PRU-ICSS memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_PRUSS1_BANK_0,LOSTMEM_PRUSS1_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x28++0x2F line.long 0x00 "PM_L4PER_TIMER10_WKDEP,This register controls wakeup dependency based on TIMER10 service requests" bitfld.long 0x00 9. "WKUPDEP_TIMER10_EVE4,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER10_EVE4_0,WKUPDEP_TIMER10_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_TIMER10_EVE3,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER10_EVE3_0,WKUPDEP_TIMER10_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_TIMER10_EVE2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_EVE2_0,WKUPDEP_TIMER10_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_TIMER10_EVE1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_EVE1_0,WKUPDEP_TIMER10_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_TIMER10_DSP2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_DSP2_0,WKUPDEP_TIMER10_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_TIMER10_IPU1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_IPU1_0,WKUPDEP_TIMER10_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_TIMER10_DSP1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_DSP1_0,WKUPDEP_TIMER10_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_TIMER10_IPU2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER10_IPU2_0,WKUPDEP_TIMER10_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_TIMER10_MPU,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_MPU_0,WKUPDEP_TIMER10_MPU_1" line.long 0x04 "RM_L4PER_TIMER10_CONTEXT,This register contains dedicated TIMER10 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_TIMER11_WKDEP,This register controls wakeup dependency based on TIMER11 service requests" bitfld.long 0x08 9. "WKUPDEP_TIMER11_EVE4,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER11_EVE4_0,WKUPDEP_TIMER11_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_TIMER11_EVE3,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER11_EVE3_0,WKUPDEP_TIMER11_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_TIMER11_EVE2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_EVE2_0,WKUPDEP_TIMER11_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TIMER11_EVE1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_EVE1_0,WKUPDEP_TIMER11_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TIMER11_DSP2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_DSP2_0,WKUPDEP_TIMER11_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TIMER11_IPU1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_IPU1_0,WKUPDEP_TIMER11_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER11_DSP1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_DSP1_0,WKUPDEP_TIMER11_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER11_IPU2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER11_IPU2_0,WKUPDEP_TIMER11_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER11_MPU,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_MPU_0,WKUPDEP_TIMER11_MPU_1" line.long 0x0C "RM_L4PER_TIMER11_CONTEXT,This register contains dedicated TIMER11 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_TIMER2_WKDEP,This register controls wakeup dependency based on TIMER2 service requests" bitfld.long 0x10 9. "WKUPDEP_TIMER2_EVE4,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER2_EVE4_0,WKUPDEP_TIMER2_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_TIMER2_EVE3,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER2_EVE3_0,WKUPDEP_TIMER2_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_TIMER2_EVE2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_EVE2_0,WKUPDEP_TIMER2_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER2_EVE1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_EVE1_0,WKUPDEP_TIMER2_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER2_DSP2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_DSP2_0,WKUPDEP_TIMER2_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER2_IPU1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_IPU1_0,WKUPDEP_TIMER2_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER2_DSP1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_DSP1_0,WKUPDEP_TIMER2_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER2_IPU2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER2_IPU2_0,WKUPDEP_TIMER2_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER2_MPU,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_MPU_0,WKUPDEP_TIMER2_MPU_1" line.long 0x14 "RM_L4PER_TIMER2_CONTEXT,This register contains dedicated TIMER2 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_TIMER3_WKDEP,This register controls wakeup dependency based on TIMER3 service requests" bitfld.long 0x18 9. "WKUPDEP_TIMER3_EVE4,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER3_EVE4_0,WKUPDEP_TIMER3_EVE4_1" bitfld.long 0x18 8. "WKUPDEP_TIMER3_EVE3,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER3_EVE3_0,WKUPDEP_TIMER3_EVE3_1" newline bitfld.long 0x18 7. "WKUPDEP_TIMER3_EVE2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_EVE2_0,WKUPDEP_TIMER3_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER3_EVE1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_EVE1_0,WKUPDEP_TIMER3_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER3_DSP2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_DSP2_0,WKUPDEP_TIMER3_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER3_IPU1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_IPU1_0,WKUPDEP_TIMER3_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER3_DSP1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_DSP1_0,WKUPDEP_TIMER3_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER3_IPU2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER3_IPU2_0,WKUPDEP_TIMER3_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER3_MPU,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_MPU_0,WKUPDEP_TIMER3_MPU_1" line.long 0x1C "RM_L4PER_TIMER3_CONTEXT,This register contains dedicated TIMER3 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_TIMER4_WKDEP,This register controls wakeup dependency based on TIMER4 service requests" bitfld.long 0x20 9. "WKUPDEP_TIMER4_EVE4,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER4_EVE4_0,WKUPDEP_TIMER4_EVE4_1" bitfld.long 0x20 8. "WKUPDEP_TIMER4_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER4_EVE3_0,WKUPDEP_TIMER4_EVE3_1" newline bitfld.long 0x20 7. "WKUPDEP_TIMER4_EVE2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_EVE2_0,WKUPDEP_TIMER4_EVE2_1" bitfld.long 0x20 6. "WKUPDEP_TIMER4_EVE1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_EVE1_0,WKUPDEP_TIMER4_EVE1_1" newline bitfld.long 0x20 5. "WKUPDEP_TIMER4_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_DSP2_0,WKUPDEP_TIMER4_DSP2_1" bitfld.long 0x20 4. "WKUPDEP_TIMER4_IPU1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_IPU1_0,WKUPDEP_TIMER4_IPU1_1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER4_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_DSP1_0,WKUPDEP_TIMER4_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER4_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER4_IPU2_0,WKUPDEP_TIMER4_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER4_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_MPU_0,WKUPDEP_TIMER4_MPU_1" line.long 0x24 "RM_L4PER_TIMER4_CONTEXT,This register contains dedicated TIMER4 context statuses" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_L4PER_TIMER9_WKDEP,This register controls wakeup dependency based on TIMER9 service requests" bitfld.long 0x28 9. "WKUPDEP_TIMER9_EVE4,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER9_EVE4_0,WKUPDEP_TIMER9_EVE4_1" bitfld.long 0x28 8. "WKUPDEP_TIMER9_EVE3,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER9_EVE3_0,WKUPDEP_TIMER9_EVE3_1" newline bitfld.long 0x28 7. "WKUPDEP_TIMER9_EVE2,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_EVE2_0,WKUPDEP_TIMER9_EVE2_1" bitfld.long 0x28 6. "WKUPDEP_TIMER9_EVE1,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_EVE1_0,WKUPDEP_TIMER9_EVE1_1" newline bitfld.long 0x28 5. "WKUPDEP_TIMER9_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_DSP2_0,WKUPDEP_TIMER9_DSP2_1" bitfld.long 0x28 4. "WKUPDEP_TIMER9_IPU1,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_IPU1_0,WKUPDEP_TIMER9_IPU1_1" newline bitfld.long 0x28 2. "WKUPDEP_TIMER9_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_DSP1_0,WKUPDEP_TIMER9_DSP1_1" bitfld.long 0x28 1. "WKUPDEP_TIMER9_IPU2,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER9_IPU2_0,WKUPDEP_TIMER9_IPU2_1" newline bitfld.long 0x28 0. "WKUPDEP_TIMER9_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_MPU_0,WKUPDEP_TIMER9_MPU_1" line.long 0x2C "RM_L4PER_TIMER9_CONTEXT,This register contains dedicated TIMER9 context statuses" bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x5C++0x2B line.long 0x00 "RM_L4PER_ELM_CONTEXT,This register contains dedicated ELM context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests" bitfld.long 0x04 19. "WKUPDEP_GPIO2_IRQ2_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO2_IRQ2_EVE4_0,WKUPDEP_GPIO2_IRQ2_EVE4_1" bitfld.long 0x04 18. "WKUPDEP_GPIO2_IRQ2_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO2_IRQ2_EVE3_0,WKUPDEP_GPIO2_IRQ2_EVE3_1" newline bitfld.long 0x04 17. "WKUPDEP_GPIO2_IRQ2_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_EVE2_0,WKUPDEP_GPIO2_IRQ2_EVE2_1" bitfld.long 0x04 16. "WKUPDEP_GPIO2_IRQ2_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_EVE1_0,WKUPDEP_GPIO2_IRQ2_EVE1_1" newline bitfld.long 0x04 15. "WKUPDEP_GPIO2_IRQ2_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_DSP2_0,WKUPDEP_GPIO2_IRQ2_DSP2_1" bitfld.long 0x04 14. "WKUPDEP_GPIO2_IRQ2_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_IPU1_0,WKUPDEP_GPIO2_IRQ2_IPU1_1" newline bitfld.long 0x04 12. "WKUPDEP_GPIO2_IRQ2_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP1 + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_DSP1_0,WKUPDEP_GPIO2_IRQ2_DSP1_1" bitfld.long 0x04 11. "WKUPDEP_GPIO2_IRQ2_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ2_IPU2_0,WKUPDEP_GPIO2_IRQ2_IPU2_1" newline bitfld.long 0x04 10. "WKUPDEP_GPIO2_IRQ2_MPU,Wakeup dependency from GPIO2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_MPU_0,WKUPDEP_GPIO2_IRQ2_MPU_1" bitfld.long 0x04 9. "WKUPDEP_GPIO2_IRQ1_EVE4,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO2_IRQ1_EVE4_0,WKUPDEP_GPIO2_IRQ1_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_GPIO2_IRQ1_EVE3,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO2_IRQ1_EVE3_0,WKUPDEP_GPIO2_IRQ1_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_GPIO2_IRQ1_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_EVE2_0,WKUPDEP_GPIO2_IRQ1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_GPIO2_IRQ1_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_EVE1_0,WKUPDEP_GPIO2_IRQ1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_GPIO2_IRQ1_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_DSP2_0,WKUPDEP_GPIO2_IRQ1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_GPIO2_IRQ1_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_IPU1_0,WKUPDEP_GPIO2_IRQ1_IPU1_1" bitfld.long 0x04 2. "WKUPDEP_GPIO2_IRQ1_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_DSP1_0,WKUPDEP_GPIO2_IRQ1_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_GPIO2_IRQ1_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO2_IRQ1_IPU2_0,WKUPDEP_GPIO2_IRQ1_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_GPIO2_IRQ1_MPU,Wakeup dependency from GPIO2 module (SWakeup signal for POROCPSINTERRUPT1) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_MPU_0,WKUPDEP_GPIO2_IRQ1_MPU_1" line.long 0x08 "RM_L4PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 context statuses" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests" bitfld.long 0x0C 19. "WKUPDEP_GPIO3_IRQ2_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO3_IRQ2_EVE4_0,WKUPDEP_GPIO3_IRQ2_EVE4_1" bitfld.long 0x0C 18. "WKUPDEP_GPIO3_IRQ2_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO3_IRQ2_EVE3_0,WKUPDEP_GPIO3_IRQ2_EVE3_1" newline bitfld.long 0x0C 17. "WKUPDEP_GPIO3_IRQ2_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_EVE2_0,WKUPDEP_GPIO3_IRQ2_EVE2_1" bitfld.long 0x0C 16. "WKUPDEP_GPIO3_IRQ2_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_EVE1_0,WKUPDEP_GPIO3_IRQ2_EVE1_1" newline bitfld.long 0x0C 15. "WKUPDEP_GPIO3_IRQ2_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_DSP2_0,WKUPDEP_GPIO3_IRQ2_DSP2_1" bitfld.long 0x0C 14. "WKUPDEP_GPIO3_IRQ2_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_IPU1_0,WKUPDEP_GPIO3_IRQ2_IPU1_1" newline bitfld.long 0x0C 12. "WKUPDEP_GPIO3_IRQ2_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_DSP1_0,WKUPDEP_GPIO3_IRQ2_DSP1_1" bitfld.long 0x0C 11. "WKUPDEP_GPIO3_IRQ2_IPU2,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ2_IPU2_0,WKUPDEP_GPIO3_IRQ2_IPU2_1" newline bitfld.long 0x0C 10. "WKUPDEP_GPIO3_IRQ2_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_MPU_0,WKUPDEP_GPIO3_IRQ2_MPU_1" bitfld.long 0x0C 9. "WKUPDEP_GPIO3_IRQ1_EVE4,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO3_IRQ1_EVE4_0,WKUPDEP_GPIO3_IRQ1_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_GPIO3_IRQ1_EVE3,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO3_IRQ1_EVE3_0,WKUPDEP_GPIO3_IRQ1_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_GPIO3_IRQ1_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_EVE2_0,WKUPDEP_GPIO3_IRQ1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_GPIO3_IRQ1_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_EVE1_0,WKUPDEP_GPIO3_IRQ1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_GPIO3_IRQ1_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_DSP2_0,WKUPDEP_GPIO3_IRQ1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_GPIO3_IRQ1_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_IPU1_0,WKUPDEP_GPIO3_IRQ1_IPU1_1" bitfld.long 0x0C 2. "WKUPDEP_GPIO3_IRQ1_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_DSP1_0,WKUPDEP_GPIO3_IRQ1_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_GPIO3_IRQ1_IPU2,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO3_IRQ1_IPU2_0,WKUPDEP_GPIO3_IRQ1_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_GPIO3_IRQ1_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_MPU_0,WKUPDEP_GPIO3_IRQ1_MPU_1" line.long 0x10 "RM_L4PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 context statuses" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x14 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests" bitfld.long 0x14 19. "WKUPDEP_GPIO4_IRQ2_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO4_IRQ2_EVE4_0,WKUPDEP_GPIO4_IRQ2_EVE4_1" bitfld.long 0x14 18. "WKUPDEP_GPIO4_IRQ2_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO4_IRQ2_EVE3_0,WKUPDEP_GPIO4_IRQ2_EVE3_1" newline bitfld.long 0x14 17. "WKUPDEP_GPIO4_IRQ2_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_EVE2_0,WKUPDEP_GPIO4_IRQ2_EVE2_1" bitfld.long 0x14 16. "WKUPDEP_GPIO4_IRQ2_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_EVE1_0,WKUPDEP_GPIO4_IRQ2_EVE1_1" newline bitfld.long 0x14 15. "WKUPDEP_GPIO4_IRQ2_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_DSP2_0,WKUPDEP_GPIO4_IRQ2_DSP2_1" bitfld.long 0x14 14. "WKUPDEP_GPIO4_IRQ2_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_IPU1_0,WKUPDEP_GPIO4_IRQ2_IPU1_1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO4_IRQ2_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_DSP1_0,WKUPDEP_GPIO4_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO4_IRQ2_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ2_IPU2_0,WKUPDEP_GPIO4_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO4_IRQ2_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_MPU_0,WKUPDEP_GPIO4_IRQ2_MPU_1" bitfld.long 0x14 9. "WKUPDEP_GPIO4_IRQ1_EVE4,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO4_IRQ1_EVE4_0,WKUPDEP_GPIO4_IRQ1_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_GPIO4_IRQ1_EVE3,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO4_IRQ1_EVE3_0,WKUPDEP_GPIO4_IRQ1_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_GPIO4_IRQ1_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_EVE2_0,WKUPDEP_GPIO4_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO4_IRQ1_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_EVE1_0,WKUPDEP_GPIO4_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO4_IRQ1_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_DSP2_0,WKUPDEP_GPIO4_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO4_IRQ1_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_IPU1_0,WKUPDEP_GPIO4_IRQ1_IPU1_1" bitfld.long 0x14 2. "WKUPDEP_GPIO4_IRQ1_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_DSP1_0,WKUPDEP_GPIO4_IRQ1_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_GPIO4_IRQ1_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO4_IRQ1_IPU2_0,WKUPDEP_GPIO4_IRQ1_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_GPIO4_IRQ1_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_MPU_0,WKUPDEP_GPIO4_IRQ1_MPU_1" line.long 0x18 "RM_L4PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 context statuses" bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x1C "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests" bitfld.long 0x1C 19. "WKUPDEP_GPIO5_IRQ2_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO5_IRQ2_EVE4_0,WKUPDEP_GPIO5_IRQ2_EVE4_1" bitfld.long 0x1C 18. "WKUPDEP_GPIO5_IRQ2_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO5_IRQ2_EVE3_0,WKUPDEP_GPIO5_IRQ2_EVE3_1" newline bitfld.long 0x1C 17. "WKUPDEP_GPIO5_IRQ2_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_EVE2_0,WKUPDEP_GPIO5_IRQ2_EVE2_1" bitfld.long 0x1C 16. "WKUPDEP_GPIO5_IRQ2_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_EVE1_0,WKUPDEP_GPIO5_IRQ2_EVE1_1" newline bitfld.long 0x1C 15. "WKUPDEP_GPIO5_IRQ2_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_DSP2_0,WKUPDEP_GPIO5_IRQ2_DSP2_1" bitfld.long 0x1C 14. "WKUPDEP_GPIO5_IRQ2_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_IPU1_0,WKUPDEP_GPIO5_IRQ2_IPU1_1" newline bitfld.long 0x1C 12. "WKUPDEP_GPIO5_IRQ2_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_DSP1_0,WKUPDEP_GPIO5_IRQ2_DSP1_1" bitfld.long 0x1C 11. "WKUPDEP_GPIO5_IRQ2_IPU2,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ2_IPU2_0,WKUPDEP_GPIO5_IRQ2_IPU2_1" newline bitfld.long 0x1C 10. "WKUPDEP_GPIO5_IRQ2_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_MPU_0,WKUPDEP_GPIO5_IRQ2_MPU_1" bitfld.long 0x1C 9. "WKUPDEP_GPIO5_IRQ1_EVE4,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO5_IRQ1_EVE4_0,WKUPDEP_GPIO5_IRQ1_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_GPIO5_IRQ1_EVE3,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO5_IRQ1_EVE3_0,WKUPDEP_GPIO5_IRQ1_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_GPIO5_IRQ1_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_EVE2_0,WKUPDEP_GPIO5_IRQ1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_GPIO5_IRQ1_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_EVE1_0,WKUPDEP_GPIO5_IRQ1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_GPIO5_IRQ1_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_DSP2_0,WKUPDEP_GPIO5_IRQ1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_GPIO5_IRQ1_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_IPU1_0,WKUPDEP_GPIO5_IRQ1_IPU1_1" bitfld.long 0x1C 2. "WKUPDEP_GPIO5_IRQ1_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_DSP1_0,WKUPDEP_GPIO5_IRQ1_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_GPIO5_IRQ1_IPU2,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO5_IRQ1_IPU2_0,WKUPDEP_GPIO5_IRQ1_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_GPIO5_IRQ1_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_MPU_0,WKUPDEP_GPIO5_IRQ1_MPU_1" line.long 0x20 "RM_L4PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 context statuses" bitfld.long 0x20 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x24 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests" bitfld.long 0x24 19. "WKUPDEP_GPIO6_IRQ2_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO6_IRQ2_EVE4_0,WKUPDEP_GPIO6_IRQ2_EVE4_1" bitfld.long 0x24 18. "WKUPDEP_GPIO6_IRQ2_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO6_IRQ2_EVE3_0,WKUPDEP_GPIO6_IRQ2_EVE3_1" newline bitfld.long 0x24 17. "WKUPDEP_GPIO6_IRQ2_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_EVE2_0,WKUPDEP_GPIO6_IRQ2_EVE2_1" bitfld.long 0x24 16. "WKUPDEP_GPIO6_IRQ2_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_EVE1_0,WKUPDEP_GPIO6_IRQ2_EVE1_1" newline bitfld.long 0x24 15. "WKUPDEP_GPIO6_IRQ2_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_DSP2_0,WKUPDEP_GPIO6_IRQ2_DSP2_1" bitfld.long 0x24 14. "WKUPDEP_GPIO6_IRQ2_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_IPU1_0,WKUPDEP_GPIO6_IRQ2_IPU1_1" newline bitfld.long 0x24 12. "WKUPDEP_GPIO6_IRQ2_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_DSP1_0,WKUPDEP_GPIO6_IRQ2_DSP1_1" bitfld.long 0x24 11. "WKUPDEP_GPIO6_IRQ2_IPU2,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ2_IPU2_0,WKUPDEP_GPIO6_IRQ2_IPU2_1" newline bitfld.long 0x24 10. "WKUPDEP_GPIO6_IRQ2_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_MPU_0,WKUPDEP_GPIO6_IRQ2_MPU_1" bitfld.long 0x24 9. "WKUPDEP_GPIO6_IRQ1_EVE4,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO6_IRQ1_EVE4_0,WKUPDEP_GPIO6_IRQ1_EVE4_1" newline bitfld.long 0x24 8. "WKUPDEP_GPIO6_IRQ1_EVE3,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO6_IRQ1_EVE3_0,WKUPDEP_GPIO6_IRQ1_EVE3_1" bitfld.long 0x24 7. "WKUPDEP_GPIO6_IRQ1_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_EVE2_0,WKUPDEP_GPIO6_IRQ1_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_GPIO6_IRQ1_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_EVE1_0,WKUPDEP_GPIO6_IRQ1_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_GPIO6_IRQ1_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_DSP2_0,WKUPDEP_GPIO6_IRQ1_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_GPIO6_IRQ1_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_IPU1_0,WKUPDEP_GPIO6_IRQ1_IPU1_1" bitfld.long 0x24 2. "WKUPDEP_GPIO6_IRQ1_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_DSP1_0,WKUPDEP_GPIO6_IRQ1_DSP1_1" newline bitfld.long 0x24 1. "WKUPDEP_GPIO6_IRQ1_IPU2,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO6_IRQ1_IPU2_0,WKUPDEP_GPIO6_IRQ1_IPU2_1" bitfld.long 0x24 0. "WKUPDEP_GPIO6_IRQ1_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_MPU_0,WKUPDEP_GPIO6_IRQ1_MPU_1" line.long 0x28 "RM_L4PER_GPIO6_CONTEXT,This register contains dedicated GPIO6 context statuses" bitfld.long 0x28 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L4PER2_PWMSS2_CONTEXT,This register contains dedicated PWMSS2 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x43 line.long 0x00 "RM_L4PER2_PWMSS3_CONTEXT,This register contains dedicated PWMSS3 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests" bitfld.long 0x04 15. "WKUPDEP_I2C1_DMA_DSP2,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_DMA_DSP2_0,WKUPDEP_I2C1_DMA_DSP2_1" bitfld.long 0x04 13. "WKUPDEP_I2C1_DMA_SDMA,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_DMA_SDMA_0,WKUPDEP_I2C1_DMA_SDMA_1" newline bitfld.long 0x04 12. "WKUPDEP_I2C1_DMA_DSP1,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_DMA_DSP1_0,WKUPDEP_I2C1_DMA_DSP1_1" bitfld.long 0x04 9. "WKUPDEP_I2C1_IRQ_EVE4,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_I2C1_IRQ_EVE4_0,WKUPDEP_I2C1_IRQ_EVE4_1" newline bitfld.long 0x04 8. "WKUPDEP_I2C1_IRQ_EVE3,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_I2C1_IRQ_EVE3_0,WKUPDEP_I2C1_IRQ_EVE3_1" bitfld.long 0x04 7. "WKUPDEP_I2C1_IRQ_EVE2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_EVE2_0,WKUPDEP_I2C1_IRQ_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_I2C1_IRQ_EVE1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_EVE1_0,WKUPDEP_I2C1_IRQ_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_I2C1_IRQ_DSP2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_DSP2_0,WKUPDEP_I2C1_IRQ_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_I2C1_IRQ_IPU1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_IPU1_0,WKUPDEP_I2C1_IRQ_IPU1_1" bitfld.long 0x04 2. "WKUPDEP_I2C1_IRQ_DSP1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_DSP1_0,WKUPDEP_I2C1_IRQ_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_I2C1_IRQ_IPU2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C1_IRQ_IPU2_0,WKUPDEP_I2C1_IRQ_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_I2C1_IRQ_MPU,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_MPU_0,WKUPDEP_I2C1_IRQ_MPU_1" line.long 0x08 "RM_L4PER_I2C1_CONTEXT,This register contains dedicated I2C1 context statuses" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests" bitfld.long 0x0C 15. "WKUPDEP_I2C2_DMA_DSP2,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_DMA_DSP2_0,WKUPDEP_I2C2_DMA_DSP2_1" bitfld.long 0x0C 13. "WKUPDEP_I2C2_DMA_SDMA,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_DMA_SDMA_0,WKUPDEP_I2C2_DMA_SDMA_1" newline bitfld.long 0x0C 12. "WKUPDEP_I2C2_DMA_DSP1,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_DMA_DSP1_0,WKUPDEP_I2C2_DMA_DSP1_1" bitfld.long 0x0C 9. "WKUPDEP_I2C2_IRQ_EVE4,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_I2C2_IRQ_EVE4_0,WKUPDEP_I2C2_IRQ_EVE4_1" newline bitfld.long 0x0C 8. "WKUPDEP_I2C2_IRQ_EVE3,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_I2C2_IRQ_EVE3_0,WKUPDEP_I2C2_IRQ_EVE3_1" bitfld.long 0x0C 7. "WKUPDEP_I2C2_IRQ_EVE2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_EVE2_0,WKUPDEP_I2C2_IRQ_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_I2C2_IRQ_EVE1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_EVE1_0,WKUPDEP_I2C2_IRQ_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_I2C2_IRQ_DSP2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_DSP2_0,WKUPDEP_I2C2_IRQ_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_I2C2_IRQ_IPU1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_IPU1_0,WKUPDEP_I2C2_IRQ_IPU1_1" bitfld.long 0x0C 2. "WKUPDEP_I2C2_IRQ_DSP1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_DSP1_0,WKUPDEP_I2C2_IRQ_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_I2C2_IRQ_IPU2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C2_IRQ_IPU2_0,WKUPDEP_I2C2_IRQ_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_I2C2_IRQ_MPU,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_MPU_0,WKUPDEP_I2C2_IRQ_MPU_1" line.long 0x10 "RM_L4PER_I2C2_CONTEXT,This register contains dedicated I2C2 context statuses" bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests" bitfld.long 0x14 15. "WKUPDEP_I2C3_DMA_DSP2,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_DMA_DSP2_0,WKUPDEP_I2C3_DMA_DSP2_1" bitfld.long 0x14 13. "WKUPDEP_I2C3_DMA_SDMA,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_DMA_SDMA_0,WKUPDEP_I2C3_DMA_SDMA_1" newline bitfld.long 0x14 12. "WKUPDEP_I2C3_DMA_DSP1,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_DMA_DSP1_0,WKUPDEP_I2C3_DMA_DSP1_1" bitfld.long 0x14 9. "WKUPDEP_I2C3_IRQ_EVE4,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_I2C3_IRQ_EVE4_0,WKUPDEP_I2C3_IRQ_EVE4_1" newline bitfld.long 0x14 8. "WKUPDEP_I2C3_IRQ_EVE3,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_I2C3_IRQ_EVE3_0,WKUPDEP_I2C3_IRQ_EVE3_1" bitfld.long 0x14 7. "WKUPDEP_I2C3_IRQ_EVE2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_EVE2_0,WKUPDEP_I2C3_IRQ_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_I2C3_IRQ_EVE1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_EVE1_0,WKUPDEP_I2C3_IRQ_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_I2C3_IRQ_DSP2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_DSP2_0,WKUPDEP_I2C3_IRQ_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_I2C3_IRQ_IPU1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_IPU1_0,WKUPDEP_I2C3_IRQ_IPU1_1" bitfld.long 0x14 2. "WKUPDEP_I2C3_IRQ_DSP1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_DSP1_0,WKUPDEP_I2C3_IRQ_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_I2C3_IRQ_IPU2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C3_IRQ_IPU2_0,WKUPDEP_I2C3_IRQ_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_I2C3_IRQ_MPU,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_MPU_0,WKUPDEP_I2C3_IRQ_MPU_1" line.long 0x18 "RM_L4PER_I2C3_CONTEXT,This register contains dedicated I2C3 context statuses" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests" bitfld.long 0x1C 15. "WKUPDEP_I2C4_DMA_DSP2,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_DMA_DSP2_0,WKUPDEP_I2C4_DMA_DSP2_1" bitfld.long 0x1C 13. "WKUPDEP_I2C4_DMA_SDMA,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_DMA_SDMA_0,WKUPDEP_I2C4_DMA_SDMA_1" newline bitfld.long 0x1C 12. "WKUPDEP_I2C4_DMA_DSP1,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_DMA_DSP1_0,WKUPDEP_I2C4_DMA_DSP1_1" bitfld.long 0x1C 9. "WKUPDEP_I2C4_IRQ_EVE4,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_I2C4_IRQ_EVE4_0,WKUPDEP_I2C4_IRQ_EVE4_1" newline bitfld.long 0x1C 8. "WKUPDEP_I2C4_IRQ_EVE3,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_I2C4_IRQ_EVE3_0,WKUPDEP_I2C4_IRQ_EVE3_1" bitfld.long 0x1C 7. "WKUPDEP_I2C4_IRQ_EVE2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_EVE2_0,WKUPDEP_I2C4_IRQ_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_I2C4_IRQ_EVE1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_EVE1_0,WKUPDEP_I2C4_IRQ_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_I2C4_IRQ_DSP2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_DSP2_0,WKUPDEP_I2C4_IRQ_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_I2C4_IRQ_IPU1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_IPU1_0,WKUPDEP_I2C4_IRQ_IPU1_1" bitfld.long 0x1C 2. "WKUPDEP_I2C4_IRQ_DSP1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_DSP1_0,WKUPDEP_I2C4_IRQ_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_I2C4_IRQ_IPU2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_I2C4_IRQ_IPU2_0,WKUPDEP_I2C4_IRQ_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_I2C4_IRQ_MPU,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_MPU_0,WKUPDEP_I2C4_IRQ_MPU_1" line.long 0x20 "RM_L4PER_I2C4_CONTEXT,This register contains dedicated I2C4 context statuses" bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "RM_L4PER_L4PER1_CONTEXT,This register contains dedicated L4_PER1 context statuses" bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "RM_L4PER2_PWMSS1_CONTEXT,This register contains dedicated PWMSS1 context statuses" bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_TIMER13_WKDEP,This register controls wakeup dependency based on TIMER13 service requests" bitfld.long 0x2C 9. "WKUPDEP_TIMER13_EVE4,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER13_EVE4_0,WKUPDEP_TIMER13_EVE4_1" bitfld.long 0x2C 8. "WKUPDEP_TIMER13_EVE3,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER13_EVE3_0,WKUPDEP_TIMER13_EVE3_1" newline bitfld.long 0x2C 7. "WKUPDEP_TIMER13_EVE2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_EVE2_0,WKUPDEP_TIMER13_EVE2_1" bitfld.long 0x2C 6. "WKUPDEP_TIMER13_EVE1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_EVE1_0,WKUPDEP_TIMER13_EVE1_1" newline bitfld.long 0x2C 5. "WKUPDEP_TIMER13_DSP2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_DSP2_0,WKUPDEP_TIMER13_DSP2_1" bitfld.long 0x2C 4. "WKUPDEP_TIMER13_IPU1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_IPU1_0,WKUPDEP_TIMER13_IPU1_1" newline bitfld.long 0x2C 2. "WKUPDEP_TIMER13_DSP1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_DSP1_0,WKUPDEP_TIMER13_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_TIMER13_IPU2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER13_IPU2_0,WKUPDEP_TIMER13_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_TIMER13_MPU,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_MPU_0,WKUPDEP_TIMER13_MPU_1" line.long 0x30 "RM_L4PER3_TIMER13_CONTEXT,This register contains dedicated TIMER13 context statuses" bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x34 "PM_L4PER_TIMER14_WKDEP,This register controls wakeup dependency based on TIMER14 service requests" bitfld.long 0x34 9. "WKUPDEP_TIMER14_EVE4,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER14_EVE4_0,WKUPDEP_TIMER14_EVE4_1" bitfld.long 0x34 8. "WKUPDEP_TIMER14_EVE3,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER14_EVE3_0,WKUPDEP_TIMER14_EVE3_1" newline bitfld.long 0x34 7. "WKUPDEP_TIMER14_EVE2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_EVE2_0,WKUPDEP_TIMER14_EVE2_1" bitfld.long 0x34 6. "WKUPDEP_TIMER14_EVE1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_EVE1_0,WKUPDEP_TIMER14_EVE1_1" newline bitfld.long 0x34 5. "WKUPDEP_TIMER14_DSP2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_DSP2_0,WKUPDEP_TIMER14_DSP2_1" bitfld.long 0x34 4. "WKUPDEP_TIMER14_IPU1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_IPU1_0,WKUPDEP_TIMER14_IPU1_1" newline bitfld.long 0x34 2. "WKUPDEP_TIMER14_DSP1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_DSP1_0,WKUPDEP_TIMER14_DSP1_1" bitfld.long 0x34 1. "WKUPDEP_TIMER14_IPU2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER14_IPU2_0,WKUPDEP_TIMER14_IPU2_1" newline bitfld.long 0x34 0. "WKUPDEP_TIMER14_MPU,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_MPU_0,WKUPDEP_TIMER14_MPU_1" line.long 0x38 "RM_L4PER3_TIMER14_CONTEXT,This register contains dedicated TIMER14 context statuses" bitfld.long 0x38 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x3C "PM_L4PER_TIMER15_WKDEP,This register controls wakeup dependency based on TIMER15 service requests" bitfld.long 0x3C 9. "WKUPDEP_TIMER15_EVE4,5Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER15_EVE4_0,WKUPDEP_TIMER15_EVE4_1" bitfld.long 0x3C 8. "WKUPDEP_TIMER15_EVE3,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER15_EVE3_0,WKUPDEP_TIMER15_EVE3_1" newline bitfld.long 0x3C 7. "WKUPDEP_TIMER15_EVE2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_EVE2_0,WKUPDEP_TIMER15_EVE2_1" bitfld.long 0x3C 6. "WKUPDEP_TIMER15_EVE1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_EVE1_0,WKUPDEP_TIMER15_EVE1_1" newline bitfld.long 0x3C 5. "WKUPDEP_TIMER15_DSP2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_DSP2_0,WKUPDEP_TIMER15_DSP2_1" bitfld.long 0x3C 4. "WKUPDEP_TIMER15_IPU1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_IPU1_0,WKUPDEP_TIMER15_IPU1_1" newline bitfld.long 0x3C 2. "WKUPDEP_TIMER15_DSP1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_DSP1_0,WKUPDEP_TIMER15_DSP1_1" bitfld.long 0x3C 1. "WKUPDEP_TIMER15_IPU2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER15_IPU2_0,WKUPDEP_TIMER15_IPU2_1" newline bitfld.long 0x3C 0. "WKUPDEP_TIMER15_MPU,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_MPU_0,WKUPDEP_TIMER15_MPU_1" line.long 0x40 "RM_L4PER3_TIMER15_CONTEXT,This register contains dedicated TIMER15 context statuses" bitfld.long 0x40 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF0++0xAF line.long 0x00 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests" bitfld.long 0x00 9. "WKUPDEP_MCSPI1_EVE4,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCSPI1_EVE4_0,WKUPDEP_MCSPI1_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_MCSPI1_EVE3,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCSPI1_EVE3_0,WKUPDEP_MCSPI1_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_MCSPI1_EVE2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_EVE2_0,WKUPDEP_MCSPI1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MCSPI1_EVE1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_EVE1_0,WKUPDEP_MCSPI1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MCSPI1_DSP2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_DSP2_0,WKUPDEP_MCSPI1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MCSPI1_IPU1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_IPU1_0,WKUPDEP_MCSPI1_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_MCSPI1_SDMA,Wakeup dependency from MCSPI1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_SDMA_0,WKUPDEP_MCSPI1_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_MCSPI1_DSP1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_DSP1_0,WKUPDEP_MCSPI1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCSPI1_IPU2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI1_IPU2_0,WKUPDEP_MCSPI1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCSPI1_MPU,Wakeup dependency from MCSPI1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_MPU_0,WKUPDEP_MCSPI1_MPU_1" line.long 0x04 "RM_L4PER_MCSPI1_CONTEXT,This register contains dedicated MCSPI1 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests" bitfld.long 0x08 9. "WKUPDEP_MCSPI2_EVE4,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCSPI2_EVE4_0,WKUPDEP_MCSPI2_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_MCSPI2_EVE3,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCSPI2_EVE3_0,WKUPDEP_MCSPI2_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_MCSPI2_EVE2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_EVE2_0,WKUPDEP_MCSPI2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_MCSPI2_EVE1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_EVE1_0,WKUPDEP_MCSPI2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_MCSPI2_DSP2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_DSP2_0,WKUPDEP_MCSPI2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_MCSPI2_IPU1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_IPU1_0,WKUPDEP_MCSPI2_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_MCSPI2_SDMA,Wakeup dependency from MCSPI2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_SDMA_0,WKUPDEP_MCSPI2_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_MCSPI2_DSP1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_DSP1_0,WKUPDEP_MCSPI2_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_MCSPI2_IPU2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI2_IPU2_0,WKUPDEP_MCSPI2_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_MCSPI2_MPU,Wakeup dependency from MCSPI2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_MPU_0,WKUPDEP_MCSPI2_MPU_1" line.long 0x0C "RM_L4PER_MCSPI2_CONTEXT,This register contains dedicated MCSPI2 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests" bitfld.long 0x10 9. "WKUPDEP_MCSPI3_EVE4,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCSPI3_EVE4_0,WKUPDEP_MCSPI3_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_MCSPI3_EVE3,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCSPI3_EVE3_0,WKUPDEP_MCSPI3_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_MCSPI3_EVE2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_EVE2_0,WKUPDEP_MCSPI3_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_MCSPI3_EVE1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_EVE1_0,WKUPDEP_MCSPI3_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_MCSPI3_DSP2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_DSP2_0,WKUPDEP_MCSPI3_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_MCSPI3_IPU1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_IPU1_0,WKUPDEP_MCSPI3_IPU1_1" newline bitfld.long 0x10 3. "WKUPDEP_MCSPI3_SDMA,Wakeup dependency from MCSPI3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_SDMA_0,WKUPDEP_MCSPI3_SDMA_1" bitfld.long 0x10 2. "WKUPDEP_MCSPI3_DSP1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_DSP1_0,WKUPDEP_MCSPI3_DSP1_1" newline bitfld.long 0x10 1. "WKUPDEP_MCSPI3_IPU2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI3_IPU2_0,WKUPDEP_MCSPI3_IPU2_1" bitfld.long 0x10 0. "WKUPDEP_MCSPI3_MPU,Wakeup dependency from MCSPI3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_MPU_0,WKUPDEP_MCSPI3_MPU_1" line.long 0x14 "RM_L4PER_MCSPI3_CONTEXT,This register contains dedicated MCSPI3 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests" bitfld.long 0x18 9. "WKUPDEP_MCSPI4_EVE4,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCSPI4_EVE4_0,WKUPDEP_MCSPI4_EVE4_1" bitfld.long 0x18 8. "WKUPDEP_MCSPI4_EVE3,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCSPI4_EVE3_0,WKUPDEP_MCSPI4_EVE3_1" newline bitfld.long 0x18 7. "WKUPDEP_MCSPI4_EVE2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_EVE2_0,WKUPDEP_MCSPI4_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_MCSPI4_EVE1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_EVE1_0,WKUPDEP_MCSPI4_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_MCSPI4_DSP2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_DSP2_0,WKUPDEP_MCSPI4_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_MCSPI4_IPU1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_IPU1_0,WKUPDEP_MCSPI4_IPU1_1" newline bitfld.long 0x18 3. "WKUPDEP_MCSPI4_SDMA,Wakeup dependency from MCSPI4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_SDMA_0,WKUPDEP_MCSPI4_SDMA_1" bitfld.long 0x18 2. "WKUPDEP_MCSPI4_DSP1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_DSP1_0,WKUPDEP_MCSPI4_DSP1_1" newline bitfld.long 0x18 1. "WKUPDEP_MCSPI4_IPU2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_MCSPI4_IPU2_0,WKUPDEP_MCSPI4_IPU2_1" bitfld.long 0x18 0. "WKUPDEP_MCSPI4_MPU,Wakeup dependency from MCSPI4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_MPU_0,WKUPDEP_MCSPI4_MPU_1" line.long 0x1C "RM_L4PER_MCSPI4_CONTEXT,This register contains dedicated MCSPI4 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_GPIO7_WKDEP,This register controls wakeup dependency based on GPIO7 service requests" bitfld.long 0x20 19. "WKUPDEP_GPIO7_IRQ2_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO7_IRQ2_EVE4_0,WKUPDEP_GPIO7_IRQ2_EVE4_1" bitfld.long 0x20 18. "WKUPDEP_GPIO7_IRQ2_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO7_IRQ2_EVE3_0,WKUPDEP_GPIO7_IRQ2_EVE3_1" newline bitfld.long 0x20 17. "WKUPDEP_GPIO7_IRQ2_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_EVE2_0,WKUPDEP_GPIO7_IRQ2_EVE2_1" bitfld.long 0x20 16. "WKUPDEP_GPIO7_IRQ2_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_EVE1_0,WKUPDEP_GPIO7_IRQ2_EVE1_1" newline bitfld.long 0x20 15. "WKUPDEP_GPIO7_IRQ2_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_DSP2_0,WKUPDEP_GPIO7_IRQ2_DSP2_1" bitfld.long 0x20 14. "WKUPDEP_GPIO7_IRQ2_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_IPU1_0,WKUPDEP_GPIO7_IRQ2_IPU1_1" newline bitfld.long 0x20 12. "WKUPDEP_GPIO7_IRQ2_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_DSP1_0,WKUPDEP_GPIO7_IRQ2_DSP1_1" bitfld.long 0x20 11. "WKUPDEP_GPIO7_IRQ2_IPU2,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ2_IPU2_0,WKUPDEP_GPIO7_IRQ2_IPU2_1" newline bitfld.long 0x20 10. "WKUPDEP_GPIO7_IRQ2_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_MPU_0,WKUPDEP_GPIO7_IRQ2_MPU_1" bitfld.long 0x20 9. "WKUPDEP_GPIO7_IRQ1_EVE4,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO7_IRQ1_EVE4_0,WKUPDEP_GPIO7_IRQ1_EVE4_1" newline bitfld.long 0x20 8. "WKUPDEP_GPIO7_IRQ1_EVE3,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO7_IRQ1_EVE3_0,WKUPDEP_GPIO7_IRQ1_EVE3_1" bitfld.long 0x20 7. "WKUPDEP_GPIO7_IRQ1_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_EVE2_0,WKUPDEP_GPIO7_IRQ1_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_GPIO7_IRQ1_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_EVE1_0,WKUPDEP_GPIO7_IRQ1_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_GPIO7_IRQ1_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_DSP2_0,WKUPDEP_GPIO7_IRQ1_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_GPIO7_IRQ1_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_IPU1_0,WKUPDEP_GPIO7_IRQ1_IPU1_1" bitfld.long 0x20 2. "WKUPDEP_GPIO7_IRQ1_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_DSP1_0,WKUPDEP_GPIO7_IRQ1_DSP1_1" newline bitfld.long 0x20 1. "WKUPDEP_GPIO7_IRQ1_IPU2,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO7_IRQ1_IPU2_0,WKUPDEP_GPIO7_IRQ1_IPU2_1" bitfld.long 0x20 0. "WKUPDEP_GPIO7_IRQ1_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_MPU_0,WKUPDEP_GPIO7_IRQ1_MPU_1" line.long 0x24 "RM_L4PER_GPIO7_CONTEXT,This register contains dedicated GPIO7 context statuses" bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x28 "PM_L4PER_GPIO8_WKDEP,This register controls wakeup dependency based on GPIO8 service requests" bitfld.long 0x28 19. "WKUPDEP_GPIO8_IRQ2_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO8_IRQ2_EVE4_0,WKUPDEP_GPIO8_IRQ2_EVE4_1" bitfld.long 0x28 18. "WKUPDEP_GPIO8_IRQ2_EVE3,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO8_IRQ2_EVE3_0,WKUPDEP_GPIO8_IRQ2_EVE3_1" newline bitfld.long 0x28 17. "WKUPDEP_GPIO8_IRQ2_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_EVE2_0,WKUPDEP_GPIO8_IRQ2_EVE2_1" bitfld.long 0x28 16. "WKUPDEP_GPIO8_IRQ2_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_EVE1_0,WKUPDEP_GPIO8_IRQ2_EVE1_1" newline bitfld.long 0x28 15. "WKUPDEP_GPIO8_IRQ2_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_DSP2_0,WKUPDEP_GPIO8_IRQ2_DSP2_1" bitfld.long 0x28 14. "WKUPDEP_GPIO8_IRQ2_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_IPU1_0,WKUPDEP_GPIO8_IRQ2_IPU1_1" newline bitfld.long 0x28 12. "WKUPDEP_GPIO8_IRQ2_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_DSP1_0,WKUPDEP_GPIO8_IRQ2_DSP1_1" bitfld.long 0x28 11. "WKUPDEP_GPIO8_IRQ2_IPU2,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ2_IPU2_0,WKUPDEP_GPIO8_IRQ2_IPU2_1" newline bitfld.long 0x28 10. "WKUPDEP_GPIO8_IRQ2_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_MPU_0,WKUPDEP_GPIO8_IRQ2_MPU_1" bitfld.long 0x28 9. "WKUPDEP_GPIO8_IRQ1_EVE4,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO8_IRQ1_EVE4_0,WKUPDEP_GPIO8_IRQ1_EVE4_1" newline bitfld.long 0x28 8. "WKUPDEP_GPIO8_IRQ1_EVE3,Wakeup dependency from GPIO8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO8_IRQ1_EVE3_0,WKUPDEP_GPIO8_IRQ1_EVE3_1" bitfld.long 0x28 7. "WKUPDEP_GPIO8_IRQ1_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_EVE2_0,WKUPDEP_GPIO8_IRQ1_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_GPIO8_IRQ1_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_EVE1_0,WKUPDEP_GPIO8_IRQ1_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_GPIO8_IRQ1_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_DSP2_0,WKUPDEP_GPIO8_IRQ1_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_GPIO8_IRQ1_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_IPU1_0,WKUPDEP_GPIO8_IRQ1_IPU1_1" bitfld.long 0x28 2. "WKUPDEP_GPIO8_IRQ1_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_DSP1_0,WKUPDEP_GPIO8_IRQ1_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_GPIO8_IRQ1_IPU2,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO8_IRQ1_IPU2_0,WKUPDEP_GPIO8_IRQ1_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_GPIO8_IRQ1_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_MPU_0,WKUPDEP_GPIO8_IRQ1_MPU_1" line.long 0x2C "RM_L4PER_GPIO8_CONTEXT,This register contains dedicated GPIO8 context statuses" bitfld.long 0x2C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x30 "PM_L4PER_MMC3_WKDEP,This register controls wakeup dependency based on MMC3 service requests" bitfld.long 0x30 9. "WKUPDEP_MMC3_EVE4,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MMC3_EVE4_0,WKUPDEP_MMC3_EVE4_1" bitfld.long 0x30 8. "WKUPDEP_MMC3_EVE3,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MMC3_EVE3_0,WKUPDEP_MMC3_EVE3_1" newline bitfld.long 0x30 7. "WKUPDEP_MMC3_EVE2,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_EVE2_0,WKUPDEP_MMC3_EVE2_1" bitfld.long 0x30 6. "WKUPDEP_MMC3_EVE1,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_EVE1_0,WKUPDEP_MMC3_EVE1_1" newline bitfld.long 0x30 5. "WKUPDEP_MMC3_DSP2,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_DSP2_0,WKUPDEP_MMC3_DSP2_1" bitfld.long 0x30 4. "WKUPDEP_MMC3_IPU1,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_IPU1_0,WKUPDEP_MMC3_IPU1_1" newline bitfld.long 0x30 3. "WKUPDEP_MMC3_SDMA,Wakeup dependency from MMC3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_SDMA_0,WKUPDEP_MMC3_SDMA_1" bitfld.long 0x30 2. "WKUPDEP_MMC3_DSP1,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_DSP1_0,WKUPDEP_MMC3_DSP1_1" newline bitfld.long 0x30 1. "WKUPDEP_MMC3_IPU2,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_IPU2_0,WKUPDEP_MMC3_IPU2_1" bitfld.long 0x30 0. "WKUPDEP_MMC3_MPU,Wakeup dependency from MMC3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_MPU_0,WKUPDEP_MMC3_MPU_1" line.long 0x34 "RM_L4PER_MMC3_CONTEXT,This register contains dedicated MMC3 context statuses" bitfld.long 0x34 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x34 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x38 "PM_L4PER_MMC4_WKDEP,This register controls wakeup dependency based on MMC4 service requests" bitfld.long 0x38 9. "WKUPDEP_MMC4_EVE4,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MMC4_EVE4_0,WKUPDEP_MMC4_EVE4_1" bitfld.long 0x38 8. "WKUPDEP_MMC4_EVE3,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MMC4_EVE3_0,WKUPDEP_MMC4_EVE3_1" newline bitfld.long 0x38 7. "WKUPDEP_MMC4_EVE2,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_EVE2_0,WKUPDEP_MMC4_EVE2_1" bitfld.long 0x38 6. "WKUPDEP_MMC4_EVE1,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_EVE1_0,WKUPDEP_MMC4_EVE1_1" newline bitfld.long 0x38 5. "WKUPDEP_MMC4_DSP2,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_DSP2_0,WKUPDEP_MMC4_DSP2_1" bitfld.long 0x38 4. "WKUPDEP_MMC4_IPU1,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_IPU1_0,WKUPDEP_MMC4_IPU1_1" newline bitfld.long 0x38 3. "WKUPDEP_MMC4_SDMA,Wakeup dependency from MMC4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_SDMA_0,WKUPDEP_MMC4_SDMA_1" bitfld.long 0x38 2. "WKUPDEP_MMC4_DSP1,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_DSP1_0,WKUPDEP_MMC4_DSP1_1" newline bitfld.long 0x38 1. "WKUPDEP_MMC4_IPU2,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_IPU2_0,WKUPDEP_MMC4_IPU2_1" bitfld.long 0x38 0. "WKUPDEP_MMC4_MPU,Wakeup dependency from MMC4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_MPU_0,WKUPDEP_MMC4_MPU_1" line.long 0x3C "RM_L4PER_MMC4_CONTEXT,This register contains dedicated MMC4 context statuses" bitfld.long 0x3C 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x3C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x40 "PM_L4PER_TIMER16_WKDEP,This register controls wakeup dependency based on TIMER16 service requests" bitfld.long 0x40 9. "WKUPDEP_TIMER16_EVE4,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER16_EVE4_0,WKUPDEP_TIMER16_EVE4_1" bitfld.long 0x40 8. "WKUPDEP_TIMER16_EVE3,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER16_EVE3_0,WKUPDEP_TIMER16_EVE3_1" newline bitfld.long 0x40 7. "WKUPDEP_TIMER16_EVE2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_EVE2_0,WKUPDEP_TIMER16_EVE2_1" bitfld.long 0x40 6. "WKUPDEP_TIMER16_EVE1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_EVE1_0,WKUPDEP_TIMER16_EVE1_1" newline bitfld.long 0x40 5. "WKUPDEP_TIMER16_DSP2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_DSP2_0,WKUPDEP_TIMER16_DSP2_1" bitfld.long 0x40 4. "WKUPDEP_TIMER16_IPU1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_IPU1_0,WKUPDEP_TIMER16_IPU1_1" newline bitfld.long 0x40 2. "WKUPDEP_TIMER16_DSP1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_DSP1_0,WKUPDEP_TIMER16_DSP1_1" bitfld.long 0x40 1. "WKUPDEP_TIMER16_IPU2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER16_IPU2_0,WKUPDEP_TIMER16_IPU2_1" newline bitfld.long 0x40 0. "WKUPDEP_TIMER16_MPU,6Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_MPU_0,WKUPDEP_TIMER16_MPU_1" line.long 0x44 "RM_L4PER3_TIMER16_CONTEXT,This register contains dedicated TIMER16 context statuses" bitfld.long 0x44 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x48 "PM_L4PER2_QSPI_WKDEP,This register controls wakeup dependency based on QSPI service requests" bitfld.long 0x48 9. "WKUPDEP_QSPI_EVE4,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_QSPI_EVE4_0,WKUPDEP_QSPI_EVE4_1" bitfld.long 0x48 8. "WKUPDEP_QSPI_EVE3,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_QSPI_EVE3_0,WKUPDEP_QSPI_EVE3_1" newline bitfld.long 0x48 7. "WKUPDEP_QSPI_EVE2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_EVE2_0,WKUPDEP_QSPI_EVE2_1" bitfld.long 0x48 6. "WKUPDEP_QSPI_EVE1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_EVE1_0,WKUPDEP_QSPI_EVE1_1" newline bitfld.long 0x48 5. "WKUPDEP_QSPI_DSP2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_DSP2_0,WKUPDEP_QSPI_DSP2_1" bitfld.long 0x48 4. "WKUPDEP_QSPI_IPU1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_IPU1_0,WKUPDEP_QSPI_IPU1_1" newline bitfld.long 0x48 2. "WKUPDEP_QSPI_DSP1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_DSP1_0,WKUPDEP_QSPI_DSP1_1" bitfld.long 0x48 1. "WKUPDEP_QSPI_IPU2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_QSPI_IPU2_0,WKUPDEP_QSPI_IPU2_1" newline bitfld.long 0x48 0. "WKUPDEP_QSPI_MPU,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_MPU_0,WKUPDEP_QSPI_MPU_1" line.long 0x4C "RM_L4PER2_QSPI_CONTEXT,This register contains dedicated QSPI context statuses" bitfld.long 0x4C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x50 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests" bitfld.long 0x50 9. "WKUPDEP_UART1_EVE4,Wakeup dependency from UART1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART1_EVE4_0,WKUPDEP_UART1_EVE4_1" bitfld.long 0x50 8. "WKUPDEP_UART1_EVE3,Wakeup dependency from UART1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART1_EVE3_0,WKUPDEP_UART1_EVE3_1" newline bitfld.long 0x50 7. "WKUPDEP_UART1_EVE2,Wakeup dependency from UART1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_EVE2_0,WKUPDEP_UART1_EVE2_1" bitfld.long 0x50 6. "WKUPDEP_UART1_EVE1,Wakeup dependency from UART1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_EVE1_0,WKUPDEP_UART1_EVE1_1" newline bitfld.long 0x50 5. "WKUPDEP_UART1_DSP2,Wakeup dependency from UART1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_DSP2_0,WKUPDEP_UART1_DSP2_1" bitfld.long 0x50 4. "WKUPDEP_UART1_IPU1,Wakeup dependency from UART1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_IPU1_0,WKUPDEP_UART1_IPU1_1" newline bitfld.long 0x50 3. "WKUPDEP_UART1_SDMA,Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_SDMA_0,WKUPDEP_UART1_SDMA_1" bitfld.long 0x50 2. "WKUPDEP_UART1_DSP1,Wakeup dependency from UART1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_DSP1_0,WKUPDEP_UART1_DSP1_1" newline bitfld.long 0x50 1. "WKUPDEP_UART1_IPU2,Wakeup dependency from UART1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART1_IPU2_0,WKUPDEP_UART1_IPU2_1" bitfld.long 0x50 0. "WKUPDEP_UART1_MPU,Wakeup dependency from UART1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_MPU_0,WKUPDEP_UART1_MPU_1" line.long 0x54 "RM_L4PER_UART1_CONTEXT,This register contains dedicated UART1 context statuses" bitfld.long 0x54 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x54 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x58 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests" bitfld.long 0x58 9. "WKUPDEP_UART2_EVE4,Wakeup dependency from UART2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART2_EVE4_0,WKUPDEP_UART2_EVE4_1" bitfld.long 0x58 8. "WKUPDEP_UART2_EVE3,Wakeup dependency from UART2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART2_EVE3_0,WKUPDEP_UART2_EVE3_1" newline bitfld.long 0x58 7. "WKUPDEP_UART2_EVE2,Wakeup dependency from UART2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_EVE2_0,WKUPDEP_UART2_EVE2_1" bitfld.long 0x58 6. "WKUPDEP_UART2_EVE1,Wakeup dependency from UART2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_EVE1_0,WKUPDEP_UART2_EVE1_1" newline bitfld.long 0x58 5. "WKUPDEP_UART2_DSP2,Wakeup dependency from UART2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_DSP2_0,WKUPDEP_UART2_DSP2_1" bitfld.long 0x58 4. "WKUPDEP_UART2_IPU1,Wakeup dependency from UART2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_IPU1_0,WKUPDEP_UART2_IPU1_1" newline bitfld.long 0x58 3. "WKUPDEP_UART2_SDMA,Wakeup dependency from UART2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_SDMA_0,WKUPDEP_UART2_SDMA_1" bitfld.long 0x58 2. "WKUPDEP_UART2_DSP1,Wakeup dependency from UART2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_DSP1_0,WKUPDEP_UART2_DSP1_1" newline bitfld.long 0x58 1. "WKUPDEP_UART2_IPU2,Wakeup dependency from UART2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART2_IPU2_0,WKUPDEP_UART2_IPU2_1" bitfld.long 0x58 0. "WKUPDEP_UART2_MPU,Wakeup dependency from UART2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_MPU_0,WKUPDEP_UART2_MPU_1" line.long 0x5C "RM_L4PER_UART2_CONTEXT,This register contains dedicated UART2 context statuses" bitfld.long 0x5C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x5C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x60 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests" bitfld.long 0x60 9. "WKUPDEP_UART3_EVE4,Wakeup dependency from UART3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART3_EVE4_0,WKUPDEP_UART3_EVE4_1" bitfld.long 0x60 8. "WKUPDEP_UART3_EVE3,Wakeup dependency from UART3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART3_EVE3_0,WKUPDEP_UART3_EVE3_1" newline bitfld.long 0x60 7. "WKUPDEP_UART3_EVE2,Wakeup dependency from UART3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_EVE2_0,WKUPDEP_UART3_EVE2_1" bitfld.long 0x60 6. "WKUPDEP_UART3_EVE1,Wakeup dependency from UART3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_EVE1_0,WKUPDEP_UART3_EVE1_1" newline bitfld.long 0x60 5. "WKUPDEP_UART3_DSP2,Wakeup dependency from UART3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_DSP2_0,WKUPDEP_UART3_DSP2_1" bitfld.long 0x60 4. "WKUPDEP_UART3_IPU1,Wakeup dependency from UART3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_IPU1_0,WKUPDEP_UART3_IPU1_1" newline bitfld.long 0x60 3. "WKUPDEP_UART3_SDMA,Wakeup dependency from UART3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_SDMA_0,WKUPDEP_UART3_SDMA_1" bitfld.long 0x60 2. "WKUPDEP_UART3_DSP1,Wakeup dependency from UART3 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_DSP1_0,WKUPDEP_UART3_DSP1_1" newline bitfld.long 0x60 1. "WKUPDEP_UART3_IPU2,Wakeup dependency from UART3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART3_IPU2_0,WKUPDEP_UART3_IPU2_1" bitfld.long 0x60 0. "WKUPDEP_UART3_MPU,Wakeup dependency from UART3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_MPU_0,WKUPDEP_UART3_MPU_1" line.long 0x64 "RM_L4PER_UART3_CONTEXT,This register contains dedicated UART3 context statuses" bitfld.long 0x64 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x64 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x68 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests" bitfld.long 0x68 9. "WKUPDEP_UART4_EVE4,Wakeup dependency from UART4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART4_EVE4_0,WKUPDEP_UART4_EVE4_1" bitfld.long 0x68 8. "WKUPDEP_UART4_EVE3,Wakeup dependency from UART4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART4_EVE3_0,WKUPDEP_UART4_EVE3_1" newline bitfld.long 0x68 7. "WKUPDEP_UART4_EVE2,Wakeup dependency from UART4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_EVE2_0,WKUPDEP_UART4_EVE2_1" bitfld.long 0x68 6. "WKUPDEP_UART4_EVE1,Wakeup dependency from UART4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_EVE1_0,WKUPDEP_UART4_EVE1_1" newline bitfld.long 0x68 5. "WKUPDEP_UART4_DSP2,Wakeup dependency from UART4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_DSP2_0,WKUPDEP_UART4_DSP2_1" bitfld.long 0x68 4. "WKUPDEP_UART4_IPU1,Wakeup dependency from UART4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_IPU1_0,WKUPDEP_UART4_IPU1_1" newline bitfld.long 0x68 3. "WKUPDEP_UART4_SDMA,Wakeup dependency from UART4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_SDMA_0,WKUPDEP_UART4_SDMA_1" bitfld.long 0x68 2. "WKUPDEP_UART4_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_DSP1_0,WKUPDEP_UART4_DSP1_1" newline bitfld.long 0x68 1. "WKUPDEP_UART4_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART4_IPU2_0,WKUPDEP_UART4_IPU2_1" bitfld.long 0x68 0. "WKUPDEP_UART4_MPU,Wakeup dependency from UART4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_MPU_0,WKUPDEP_UART4_MPU_1" line.long 0x6C "RM_L4PER_UART4_CONTEXT,This register contains dedicated UART4 context statuses" bitfld.long 0x6C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x6C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x70 "PM_L4PER2_MCASP2_WKDEP,This register controls wakeup dependency based on MCASP2 service requests" bitfld.long 0x70 15. "WKUPDEP_MCASP2_DMA_DSP2,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_DSP2_0,WKUPDEP_MCASP2_DMA_DSP2_1" bitfld.long 0x70 13. "WKUPDEP_MCASP2_DMA_SDMA,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_SDMA_0,WKUPDEP_MCASP2_DMA_SDMA_1" newline bitfld.long 0x70 12. "WKUPDEP_MCASP2_DMA_DSP1,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_DSP1_0,WKUPDEP_MCASP2_DMA_DSP1_1" bitfld.long 0x70 9. "WKUPDEP_MCASP2_IRQ_EVE4,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP2_IRQ_EVE4_0,WKUPDEP_MCASP2_IRQ_EVE4_1" newline bitfld.long 0x70 8. "WKUPDEP_MCASP2_IRQ_EVE3,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP2_IRQ_EVE3_0,WKUPDEP_MCASP2_IRQ_EVE3_1" bitfld.long 0x70 7. "WKUPDEP_MCASP2_IRQ_EVE2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_EVE2_0,WKUPDEP_MCASP2_IRQ_EVE2_1" newline bitfld.long 0x70 6. "WKUPDEP_MCASP2_IRQ_EVE1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_EVE1_0,WKUPDEP_MCASP2_IRQ_EVE1_1" bitfld.long 0x70 5. "WKUPDEP_MCASP2_IRQ_DSP2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_DSP2_0,WKUPDEP_MCASP2_IRQ_DSP2_1" newline bitfld.long 0x70 4. "WKUPDEP_MCASP2_IRQ_IPU1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_IPU1_0,WKUPDEP_MCASP2_IRQ_IPU1_1" bitfld.long 0x70 2. "WKUPDEP_MCASP2_IRQ_DSP1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_DSP1_0,WKUPDEP_MCASP2_IRQ_DSP1_1" newline bitfld.long 0x70 1. "WKUPDEP_MCASP2_IRQ_IPU2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_IPU2_0,WKUPDEP_MCASP2_IRQ_IPU2_1" bitfld.long 0x70 0. "WKUPDEP_MCASP2_IRQ_MPU,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_MPU_0,WKUPDEP_MCASP2_IRQ_MPU_1" line.long 0x74 "RM_L4PER2_MCASP2_CONTEXT,This register contains dedicated MCASP2 context statuses" bitfld.long 0x74 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x78 "PM_L4PER2_MCASP3_WKDEP,This register controls wakeup dependency based on MCASP3 service requests" bitfld.long 0x78 15. "WKUPDEP_MCASP3_DMA_DSP2,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_DSP2_0,WKUPDEP_MCASP3_DMA_DSP2_1" bitfld.long 0x78 13. "WKUPDEP_MCASP3_DMA_SDMA,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_SDMA_0,WKUPDEP_MCASP3_DMA_SDMA_1" newline bitfld.long 0x78 12. "WKUPDEP_MCASP3_DMA_DSP1,3Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_DSP1_0,WKUPDEP_MCASP3_DMA_DSP1_1" bitfld.long 0x78 9. "WKUPDEP_MCASP3_IRQ_EVE4,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP3_IRQ_EVE4_0,WKUPDEP_MCASP3_IRQ_EVE4_1" newline bitfld.long 0x78 8. "WKUPDEP_MCASP3_IRQ_EVE3,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP3_IRQ_EVE3_0,WKUPDEP_MCASP3_IRQ_EVE3_1" bitfld.long 0x78 7. "WKUPDEP_MCASP3_IRQ_EVE2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_EVE2_0,WKUPDEP_MCASP3_IRQ_EVE2_1" newline bitfld.long 0x78 6. "WKUPDEP_MCASP3_IRQ_EVE1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_EVE1_0,WKUPDEP_MCASP3_IRQ_EVE1_1" bitfld.long 0x78 5. "WKUPDEP_MCASP3_IRQ_DSP2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_DSP2_0,WKUPDEP_MCASP3_IRQ_DSP2_1" newline bitfld.long 0x78 4. "WKUPDEP_MCASP3_IRQ_IPU1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_IPU1_0,WKUPDEP_MCASP3_IRQ_IPU1_1" bitfld.long 0x78 2. "WKUPDEP_MCASP3_IRQ_DSP1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_DSP1_0,WKUPDEP_MCASP3_IRQ_DSP1_1" newline bitfld.long 0x78 1. "WKUPDEP_MCASP3_IRQ_IPU2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_IPU2_0,WKUPDEP_MCASP3_IRQ_IPU2_1" bitfld.long 0x78 0. "WKUPDEP_MCASP3_IRQ_MPU,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_MPU_0,WKUPDEP_MCASP3_IRQ_MPU_1" line.long 0x7C "RM_L4PER2_MCASP3_CONTEXT,This register contains dedicated MCASP3 context statuses" bitfld.long 0x7C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x80 "PM_L4PER_UART5_WKDEP,This register controls wakeup dependency based on UART5 service requests" bitfld.long 0x80 9. "WKUPDEP_UART5_EVE4,Wakeup dependency from UART5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART5_EVE4_0,WKUPDEP_UART5_EVE4_1" bitfld.long 0x80 8. "WKUPDEP_UART5_EVE3,Wakeup dependency from UART5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART5_EVE3_0,WKUPDEP_UART5_EVE3_1" newline bitfld.long 0x80 7. "WKUPDEP_UART5_EVE2,Wakeup dependency from UART5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_EVE2_0,WKUPDEP_UART5_EVE2_1" bitfld.long 0x80 6. "WKUPDEP_UART5_EVE1,Wakeup dependency from UART5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_EVE1_0,WKUPDEP_UART5_EVE1_1" newline bitfld.long 0x80 5. "WKUPDEP_UART5_DSP2,Wakeup dependency from UART5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_DSP2_0,WKUPDEP_UART5_DSP2_1" bitfld.long 0x80 4. "WKUPDEP_UART5_IPU1,Wakeup dependency from UART5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_IPU1_0,WKUPDEP_UART5_IPU1_1" newline bitfld.long 0x80 3. "WKUPDEP_UART5_SDMA,Wakeup dependency from UART5 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_SDMA_0,WKUPDEP_UART5_SDMA_1" bitfld.long 0x80 2. "WKUPDEP_UART5_DSP1,Wakeup dependency from UART5 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_DSP1_0,WKUPDEP_UART5_DSP1_1" newline bitfld.long 0x80 1. "WKUPDEP_UART5_IPU2,Wakeup dependency from UART5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART5_IPU2_0,WKUPDEP_UART5_IPU2_1" bitfld.long 0x80 0. "WKUPDEP_UART5_MPU,Wakeup dependency from UART5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_MPU_0,WKUPDEP_UART5_MPU_1" line.long 0x84 "RM_L4PER_UART5_CONTEXT,This register contains dedicated UART5 context statuses" bitfld.long 0x84 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x84 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x88 "PM_L4PER2_MCASP5_WKDEP,This register controls wakeup dependency based on MCASP5 service requests" bitfld.long 0x88 15. "WKUPDEP_MCASP5_DMA_DSP2,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_DSP2_0,WKUPDEP_MCASP5_DMA_DSP2_1" bitfld.long 0x88 13. "WKUPDEP_MCASP5_DMA_SDMA,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_SDMA_0,WKUPDEP_MCASP5_DMA_SDMA_1" newline bitfld.long 0x88 12. "WKUPDEP_MCASP5_DMA_DSP1,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_DSP1_0,WKUPDEP_MCASP5_DMA_DSP1_1" bitfld.long 0x88 9. "WKUPDEP_MCASP5_IRQ_EVE4,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP5_IRQ_EVE4_0,WKUPDEP_MCASP5_IRQ_EVE4_1" newline bitfld.long 0x88 8. "WKUPDEP_MCASP5_IRQ_EVE3,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP5_IRQ_EVE3_0,WKUPDEP_MCASP5_IRQ_EVE3_1" bitfld.long 0x88 7. "WKUPDEP_MCASP5_IRQ_EVE2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_EVE2_0,WKUPDEP_MCASP5_IRQ_EVE2_1" newline bitfld.long 0x88 6. "WKUPDEP_MCASP5_IRQ_EVE1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_EVE1_0,WKUPDEP_MCASP5_IRQ_EVE1_1" bitfld.long 0x88 5. "WKUPDEP_MCASP5_IRQ_DSP2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_DSP2_0,WKUPDEP_MCASP5_IRQ_DSP2_1" newline bitfld.long 0x88 4. "WKUPDEP_MCASP5_IRQ_IPU1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_IPU1_0,WKUPDEP_MCASP5_IRQ_IPU1_1" bitfld.long 0x88 2. "WKUPDEP_MCASP5_IRQ_DSP1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_DSP1_0,WKUPDEP_MCASP5_IRQ_DSP1_1" newline bitfld.long 0x88 1. "WKUPDEP_MCASP5_IRQ_IPU2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_IPU2_0,WKUPDEP_MCASP5_IRQ_IPU2_1" bitfld.long 0x88 0. "WKUPDEP_MCASP5_IRQ_MPU,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_MPU_0,WKUPDEP_MCASP5_IRQ_MPU_1" line.long 0x8C "RM_L4PER2_MCASP5_CONTEXT,This register contains dedicated MCASP5 context statuses" bitfld.long 0x8C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x90 "PM_L4PER2_MCASP6_WKDEP,This register controls wakeup dependency based on MCASP6 service requests" bitfld.long 0x90 15. "WKUPDEP_MCASP6_DMA_DSP2,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_DSP2_0,WKUPDEP_MCASP6_DMA_DSP2_1" bitfld.long 0x90 13. "WKUPDEP_MCASP6_DMA_SDMA,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_SDMA_0,WKUPDEP_MCASP6_DMA_SDMA_1" newline bitfld.long 0x90 12. "WKUPDEP_MCASP6_DMA_DSP1,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_DSP1_0,WKUPDEP_MCASP6_DMA_DSP1_1" bitfld.long 0x90 9. "WKUPDEP_MCASP6_IRQ_EVE4,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP6_IRQ_EVE4_0,WKUPDEP_MCASP6_IRQ_EVE4_1" newline bitfld.long 0x90 8. "WKUPDEP_MCASP6_IRQ_EVE3,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP6_IRQ_EVE3_0,WKUPDEP_MCASP6_IRQ_EVE3_1" bitfld.long 0x90 7. "WKUPDEP_MCASP6_IRQ_EVE2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_EVE2_0,WKUPDEP_MCASP6_IRQ_EVE2_1" newline bitfld.long 0x90 6. "WKUPDEP_MCASP6_IRQ_EVE1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_EVE1_0,WKUPDEP_MCASP6_IRQ_EVE1_1" bitfld.long 0x90 5. "WKUPDEP_MCASP6_IRQ_DSP2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_DSP2_0,WKUPDEP_MCASP6_IRQ_DSP2_1" newline bitfld.long 0x90 4. "WKUPDEP_MCASP6_IRQ_IPU1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_IPU1_0,WKUPDEP_MCASP6_IRQ_IPU1_1" bitfld.long 0x90 2. "WKUPDEP_MCASP6_IRQ_DSP1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_DSP1_0,WKUPDEP_MCASP6_IRQ_DSP1_1" newline bitfld.long 0x90 1. "WKUPDEP_MCASP6_IRQ_IPU2,Wakeup dependency from MCASP6 (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_IPU2_0,WKUPDEP_MCASP6_IRQ_IPU2_1" bitfld.long 0x90 0. "WKUPDEP_MCASP6_IRQ_MPU,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_MPU_0,WKUPDEP_MCASP6_IRQ_MPU_1" line.long 0x94 "RM_L4PER2_MCASP6_CONTEXT,This register contains dedicated MCASP6 context statuses" bitfld.long 0x94 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x98 "PM_L4PER2_MCASP7_WKDEP,This register controls wakeup dependency based on MCASP7 service requests" bitfld.long 0x98 15. "WKUPDEP_MCASP7_DMA_DSP2,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_DSP2_0,WKUPDEP_MCASP7_DMA_DSP2_1" bitfld.long 0x98 13. "WKUPDEP_MCASP7_DMA_SDMA,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_SDMA_0,WKUPDEP_MCASP7_DMA_SDMA_1" newline bitfld.long 0x98 12. "WKUPDEP_MCASP7_DMA_DSP1,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_DSP1_0,WKUPDEP_MCASP7_DMA_DSP1_1" bitfld.long 0x98 9. "WKUPDEP_MCASP7_IRQ_EVE4,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP7_IRQ_EVE4_0,WKUPDEP_MCASP7_IRQ_EVE4_1" newline bitfld.long 0x98 8. "WKUPDEP_MCASP7_IRQ_EVE3,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP7_IRQ_EVE3_0,WKUPDEP_MCASP7_IRQ_EVE3_1" bitfld.long 0x98 7. "WKUPDEP_MCASP7_IRQ_EVE2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_EVE2_0,WKUPDEP_MCASP7_IRQ_EVE2_1" newline bitfld.long 0x98 6. "WKUPDEP_MCASP7_IRQ_EVE1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_EVE1_0,WKUPDEP_MCASP7_IRQ_EVE1_1" bitfld.long 0x98 5. "WKUPDEP_MCASP7_IRQ_DSP2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_DSP2_0,WKUPDEP_MCASP7_IRQ_DSP2_1" newline bitfld.long 0x98 4. "WKUPDEP_MCASP7_IRQ_IPU1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_IPU1_0,WKUPDEP_MCASP7_IRQ_IPU1_1" bitfld.long 0x98 2. "WKUPDEP_MCASP7_IRQ_DSP1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_DSP1_0,WKUPDEP_MCASP7_IRQ_DSP1_1" newline bitfld.long 0x98 1. "WKUPDEP_MCASP7_IRQ_IPU2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_IPU2_0,WKUPDEP_MCASP7_IRQ_IPU2_1" bitfld.long 0x98 0. "WKUPDEP_MCASP7_IRQ_MPU,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_MPU_0,WKUPDEP_MCASP7_IRQ_MPU_1" line.long 0x9C "RM_L4PER2_MCASP7_CONTEXT,This register contains dedicated MCASP7 context statuses" bitfld.long 0x9C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA0 "PM_L4PER2_MCASP8_WKDEP,This register controls wakeup dependency based on MCASP8 service requests" bitfld.long 0xA0 15. "WKUPDEP_MCASP8_DMA_DSP2,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_DSP2_0,WKUPDEP_MCASP8_DMA_DSP2_1" bitfld.long 0xA0 13. "WKUPDEP_MCASP8_DMA_SDMA,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_SDMA_0,WKUPDEP_MCASP8_DMA_SDMA_1" newline bitfld.long 0xA0 12. "WKUPDEP_MCASP8_DMA_DSP1,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_DSP1_0,WKUPDEP_MCASP8_DMA_DSP1_1" bitfld.long 0xA0 9. "WKUPDEP_MCASP8_IRQ_EVE4,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP8_IRQ_EVE4_0,WKUPDEP_MCASP8_IRQ_EVE4_1" newline bitfld.long 0xA0 8. "WKUPDEP_MCASP8_IRQ_EVE3,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP8_IRQ_EVE3_0,WKUPDEP_MCASP8_IRQ_EVE3_1" bitfld.long 0xA0 7. "WKUPDEP_MCASP8_IRQ_EVE2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_EVE2_0,WKUPDEP_MCASP8_IRQ_EVE2_1" newline bitfld.long 0xA0 6. "WKUPDEP_MCASP8_IRQ_EVE1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_EVE1_0,WKUPDEP_MCASP8_IRQ_EVE1_1" bitfld.long 0xA0 5. "WKUPDEP_MCASP8_IRQ_DSP2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_DSP2_0,WKUPDEP_MCASP8_IRQ_DSP2_1" newline bitfld.long 0xA0 4. "WKUPDEP_MCASP8_IRQ_IPU1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_IPU1_0,WKUPDEP_MCASP8_IRQ_IPU1_1" bitfld.long 0xA0 2. "WKUPDEP_MCASP8_IRQ_DSP1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_DSP1_0,WKUPDEP_MCASP8_IRQ_DSP1_1" newline bitfld.long 0xA0 1. "WKUPDEP_MCASP8_IRQ_IPU2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_IPU2_0,WKUPDEP_MCASP8_IRQ_IPU2_1" bitfld.long 0xA0 0. "WKUPDEP_MCASP8_IRQ_MPU,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_MPU_0,WKUPDEP_MCASP8_IRQ_MPU_1" line.long 0xA4 "RM_L4PER2_MCASP8_CONTEXT,This register contains dedicated MCASP8 context statuses" bitfld.long 0xA4 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA8 "PM_L4PER2_MCASP4_WKDEP,This register controls wakeup dependency based on MCASP4 service requests" bitfld.long 0xA8 15. "WKUPDEP_MCASP4_DMA_DSP2,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_DSP2_0,WKUPDEP_MCASP4_DMA_DSP2_1" bitfld.long 0xA8 13. "WKUPDEP_MCASP4_DMA_SDMA,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_SDMA_0,WKUPDEP_MCASP4_DMA_SDMA_1" newline bitfld.long 0xA8 12. "WKUPDEP_MCASP4_DMA_DSP1,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_DSP1_0,WKUPDEP_MCASP4_DMA_DSP1_1" bitfld.long 0xA8 9. "WKUPDEP_MCASP4_IRQ_EVE4,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_MCASP4_IRQ_EVE4_0,WKUPDEP_MCASP4_IRQ_EVE4_1" newline bitfld.long 0xA8 8. "WKUPDEP_MCASP4_IRQ_EVE3,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_MCASP4_IRQ_EVE3_0,WKUPDEP_MCASP4_IRQ_EVE3_1" bitfld.long 0xA8 7. "WKUPDEP_MCASP4_IRQ_EVE2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_EVE2_0,WKUPDEP_MCASP4_IRQ_EVE2_1" newline bitfld.long 0xA8 6. "WKUPDEP_MCASP4_IRQ_EVE1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_EVE1_0,WKUPDEP_MCASP4_IRQ_EVE1_1" bitfld.long 0xA8 5. "WKUPDEP_MCASP4_IRQ_DSP2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_DSP2_0,WKUPDEP_MCASP4_IRQ_DSP2_1" newline bitfld.long 0xA8 4. "WKUPDEP_MCASP4_IRQ_IPU1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_IPU1_0,WKUPDEP_MCASP4_IRQ_IPU1_1" bitfld.long 0xA8 2. "WKUPDEP_MCASP4_IRQ_DSP1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_DSP1_0,WKUPDEP_MCASP4_IRQ_DSP1_1" newline bitfld.long 0xA8 1. "WKUPDEP_MCASP4_IRQ_IPU2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_IPU2_0,WKUPDEP_MCASP4_IRQ_IPU2_1" bitfld.long 0xA8 0. "WKUPDEP_MCASP4_IRQ_MPU,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_MPU_0,WKUPDEP_MCASP4_IRQ_MPU_1" line.long 0xAC "RM_L4PER2_MCASP4_CONTEXT,This register contains dedicated MCASP4 context statuses" bitfld.long 0xAC 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1A4++0x03 line.long 0x00 "RM_L4SEC_AES1_CONTEXT,This register contains dedicated AES1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1AC++0x03 line.long 0x00 "RM_L4SEC_AES2_CONTEXT,This register contains dedicated AES2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1B4++0x03 line.long 0x00 "RM_L4SEC_DES3DES_CONTEXT,This register contains dedicated DES3DES context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1BC++0x03 line.long 0x00 "RM_L4SEC_FPKA_CONTEXT,This register contains dedicated FPKA context statuses" bitfld.long 0x00 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C4++0x03 line.long 0x00 "RM_L4SEC_RNG_CONTEXT,This register contains dedicated RNG context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1CC++0x0B line.long 0x00 "RM_L4SEC_SHA2MD51_CONTEXT,This register contains dedicated SHA2MD51 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L4PER2_UART7_WKDEP,This register controls wakeup dependency based on UART7 service requests" bitfld.long 0x04 9. "WKUPDEP_UART7_EVE4,Wakeup dependency from UART7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART7_EVE4_0,WKUPDEP_UART7_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_UART7_EVE3,Wakeup dependency from UART7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART7_EVE3_0,WKUPDEP_UART7_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_UART7_EVE2,Wakeup dependency from UART7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_EVE2_0,WKUPDEP_UART7_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_UART7_EVE1,Wakeup dependency from UART7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_EVE1_0,WKUPDEP_UART7_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_UART7_DSP2,Wakeup dependency from UART7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_DSP2_0,WKUPDEP_UART7_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_UART7_IPU1,Wakeup dependency from UART7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_IPU1_0,WKUPDEP_UART7_IPU1_1" newline bitfld.long 0x04 3. "WKUPDEP_UART7_SDMA,Wakeup dependency from UART7 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_SDMA_0,WKUPDEP_UART7_SDMA_1" bitfld.long 0x04 2. "WKUPDEP_UART7_DSP1,Wakeup dependency from UART7 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_DSP1_0,WKUPDEP_UART7_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_UART7_IPU2,Wakeup dependency from UART7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART7_IPU2_0,WKUPDEP_UART7_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_UART7_MPU,Wakeup dependency from UART7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_MPU_0,WKUPDEP_UART7_MPU_1" line.long 0x08 "RM_L4PER2_UART7_CONTEXT,This register contains dedicated UART7 context statuses" bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1DC++0x1B line.long 0x00 "RM_L4SEC_DMA_CRYPTO_CONTEXT,This register contains dedicated DMA_CRYPTO context statuses" bitfld.long 0x00 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L4PER2_UART8_WKDEP,This register controls wakeup dependency based on UART8 service requests" bitfld.long 0x04 9. "WKUPDEP_UART8_EVE4,Wakeup dependency from UART8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART8_EVE4_0,WKUPDEP_UART8_EVE4_1" bitfld.long 0x04 8. "WKUPDEP_UART8_EVE3,Wakeup dependency from UART8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART8_EVE3_0,WKUPDEP_UART8_EVE3_1" newline bitfld.long 0x04 7. "WKUPDEP_UART8_EVE2,Wakeup dependency from UART8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_EVE2_0,WKUPDEP_UART8_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_UART8_EVE1,Wakeup dependency from UART8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_EVE1_0,WKUPDEP_UART8_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_UART8_DSP2,Wakeup dependency from UART8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_DSP2_0,WKUPDEP_UART8_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_UART8_IPU1,Wakeup dependency from UART8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_IPU1_0,WKUPDEP_UART8_IPU1_1" newline bitfld.long 0x04 3. "WKUPDEP_UART8_SDMA,Wakeup dependency from UART8 module (SWakeup signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_SDMA_0,WKUPDEP_UART8_SDMA_1" bitfld.long 0x04 2. "WKUPDEP_UART8_DSP1,Wakeup dependency from UART8 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_DSP1_0,WKUPDEP_UART8_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_UART8_IPU2,Wakeup dependency from UART8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART8_IPU2_0,WKUPDEP_UART8_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_UART8_MPU,Wakeup dependency from UART8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_MPU_0,WKUPDEP_UART8_MPU_1" line.long 0x08 "RM_L4PER2_UART8_CONTEXT,This register contains dedicated UART8 context statuses" bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER2_UART9_WKDEP,This register controls wakeup dependency based on UART9 service requests" bitfld.long 0x0C 9. "WKUPDEP_UART9_EVE4,Wakeup dependency from UART9 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART9_EVE4_0,WKUPDEP_UART9_EVE4_1" bitfld.long 0x0C 8. "WKUPDEP_UART9_EVE3,Wakeup dependency from UART9 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART9_EVE3_0,WKUPDEP_UART9_EVE3_1" newline bitfld.long 0x0C 7. "WKUPDEP_UART9_EVE2,Wakeup dependency from UART9 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_EVE2_0,WKUPDEP_UART9_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_UART9_EVE1,Wakeup dependency from UART9 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_EVE1_0,WKUPDEP_UART9_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_UART9_DSP2,Wakeup dependency from UART9 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_DSP2_0,WKUPDEP_UART9_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_UART9_IPU1,Wakeup dependency from UART9 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_IPU1_0,WKUPDEP_UART9_IPU1_1" newline bitfld.long 0x0C 3. "WKUPDEP_UART9_SDMA,Wakeup dependency from UART9 module (SWakeup signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_SDMA_0,WKUPDEP_UART9_SDMA_1" bitfld.long 0x0C 2. "WKUPDEP_UART9_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_DSP1_0,WKUPDEP_UART9_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_UART9_IPU2,Wakeup dependency from UART9 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART9_IPU2_0,WKUPDEP_UART9_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_UART9_MPU,Wakeup dependency from UART9 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_MPU_0,WKUPDEP_UART9_MPU_1" line.long 0x10 "RM_L4PER2_UART9_CONTEXT,This register contains dedicated UART9 context statuses" bitfld.long 0x10 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x14 "PM_L4PER2_DCAN2_WKDEP,This register controls wakeup dependency based on DCAN2 service requests" bitfld.long 0x14 9. "WKUPDEP_DCAN2_EVE4,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DCAN2_EVE4_0,WKUPDEP_DCAN2_EVE4_1" bitfld.long 0x14 8. "WKUPDEP_DCAN2_EVE3,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DCAN2_EVE3_0,WKUPDEP_DCAN2_EVE3_1" newline bitfld.long 0x14 7. "WKUPDEP_DCAN2_EVE2,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_EVE2_0,WKUPDEP_DCAN2_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_DCAN2_EVE1,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_EVE1_0,WKUPDEP_DCAN2_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_DCAN2_DSP2,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_DSP2_0,WKUPDEP_DCAN2_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_DCAN2_IPU1,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_IPU1_0,WKUPDEP_DCAN2_IPU1_1" newline bitfld.long 0x14 3. "WKUPDEP_DCAN2_SDMA,Wakeup dependency from DCAN2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_SDMA_0,WKUPDEP_DCAN2_SDMA_1" bitfld.long 0x14 2. "WKUPDEP_DCAN2_DSP1,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_DSP1_0,WKUPDEP_DCAN2_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_DCAN2_IPU2,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN2_IPU2_0,WKUPDEP_DCAN2_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_DCAN2_MPU,Wakeup dependency from DCAN2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_MPU_0,WKUPDEP_DCAN2_MPU_1" line.long 0x18 "RM_L4PER2_DCAN2_CONTEXT,This register contains dedicated DCAN2 context statuses" bitfld.long 0x18 8. "LOSTMEM_DCAN_BANK,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_BANK_0,LOSTMEM_DCAN_BANK_1" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1FC++0x03 line.long 0x00 "RM_L4SEC_SHA2MD52_CONTEXT,This register contains dedicated SHA2MD52 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" width 0x0B tree.end tree "MPU_PRM" base ad:0x4AE06300 group.long 0x00++0x07 line.long 0x00 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "MPU_RAM_ONSTATE,MPU_RAM memory state when domain is ON" "?,?,?,MPU_RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "MPU_L2_ONSTATE,MPU_L2 memory state when domain is ON" "?,?,?,MPU_L2_ONSTATE_3" rbitfld.long 0x00 10. "MPU_RAM_RETSTATE,MPU_RAM memory state when domain is RETENTION" "?,MPU_RAM_RETSTATE_1" newline bitfld.long 0x00 9. "MPU_L2_RETSTATE,MPU_L2 memory state when domain is RETENTION" "MPU_L2_RETSTATE_0,MPU_L2_RETSTATE_1" rbitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,?" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 8.--9. "MPU_RAM_STATEST,MPU_RAM memory state status - MEM_OFF" "MPU_RAM_STATEST_0,MPU_RAM_STATEST_1,MPU_RAM_STATEST_2,MPU_RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "MPU_L2_STATEST,MPU_L2 memory state status - MEM_OFF" "MPU_L2_STATEST_0,MPU_L2_STATEST_1,MPU_L2_STATEST_2,MPU_L2_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses" bitfld.long 0x00 10. "LOSTMEM_MPU_RAM,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_MPU_RAM_0,LOSTMEM_MPU_RAM_1" bitfld.long 0x00 9. "LOSTMEM_MPU_L2,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MPU_L2_0,LOSTMEM_MPU_L2_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "OCP_SOCKET_PRM" base ad:0x4AE06000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" group.long 0x10++0x13 line.long 0x00 "PRM_IRQSTATUS_MPU,This register provides status on MPU interrupt events" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" newline bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x00 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x04 "PRM_IRQSTATUS_MPU_2,This register provides status on MPU interrupt events" bitfld.long 0x04 7. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" line.long 0x08 "PRM_IRQENABLE_MPU,This register is used to enable or disable MPU interrupt activation" bitfld.long 0x08 31. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 30. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" bitfld.long 0x08 29. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" newline bitfld.long 0x08 11. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 10. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" newline bitfld.long 0x08 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_MPU_2,This register is used to enable or disable MPU interrupt activation" bitfld.long 0x0C 7. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" line.long 0x10 "PRM_IRQSTATUS_IPU2,This register provides status on IPU2 interrupt events" bitfld.long 0x10 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x10 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x10 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x10 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x10 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x10 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x10 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" newline bitfld.long 0x10 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x10 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" newline bitfld.long 0x10 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x10 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" newline bitfld.long 0x10 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x28++0x03 line.long 0x00 "PRM_IRQENABLE_IPU2,This register is used to enable or disable IPU2 interrupt activationt" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x00 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" newline bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x30++0x03 line.long 0x00 "PRM_IRQSTATUS_DSP1,This register provides status on DSP1 interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x38++0x03 line.long 0x00 "PRM_IRQENABLE_DSP1,This register is used to enable or disable DSP1 interrupt activation" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x40++0x33 line.long 0x00 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "PRM_IRQENABLE_DSP2,This register is used to enable or disable DSP2 interrupt activation" bitfld.long 0x04 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x04 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x04 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x04 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x04 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x04 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x04 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x04 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x04 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x04 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x04 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x04 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x04 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x04 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x04 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x04 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x08 "PRM_IRQENABLE_EVE1,This register is used to enable or disable EVE1 interrupt activation" bitfld.long 0x08 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x08 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x08 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x08 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x08 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_EVE2,This register is used to enable or disable EVE2 interrupt activation" bitfld.long 0x0C 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x0C 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x0C 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x0C 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x0C 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x0C 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x0C 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x0C 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x0C 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x0C 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x0C 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x0C 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x0C 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x0C 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x0C 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x0C 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x10 "PRM_IRQENABLE_EVE3,This register is used to enable or disable EVE3 interrupt activation" bitfld.long 0x10 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x10 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x10 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x10 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x10 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x10 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x10 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x10 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x10 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x10 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x10 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x10 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x10 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x10 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x14 "PRM_IRQENABLE_EVE4,This register is used to enable or disable EVE4 interrupt activation.EVE4 is not supported in this family of devices" bitfld.long 0x14 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x14 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x14 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x14 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x14 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x14 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x14 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x14 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x14 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x14 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x14 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x14 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x14 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x14 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x14 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x14 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x18 "PRM_IRQENABLE_IPU1,This register is used to enable or disable IPU1 interrupt activation" bitfld.long 0x18 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x18 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x18 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x18 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x18 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x18 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x18 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x18 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x18 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" newline bitfld.long 0x18 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x18 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x18 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" newline bitfld.long 0x18 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x18 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x18 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" newline bitfld.long 0x18 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x18 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x1C "PRM_IRQSTATUS_DSP2,This register provides status on DSP interrupt events" bitfld.long 0x1C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x1C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x1C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x1C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x1C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x1C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x1C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x1C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x1C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x1C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x1C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x1C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x1C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x1C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x1C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x1C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x20 "PRM_IRQSTATUS_EVE1,This register provides status on EVE interrupt events" bitfld.long 0x20 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x20 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x20 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x20 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x20 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x20 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x20 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x20 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x20 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x20 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x20 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x20 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x20 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x20 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x20 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x20 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x24 "PRM_IRQSTATUS_EVE2,This register provides status on EVE interrupt events" bitfld.long 0x24 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x24 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x24 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x24 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x24 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x24 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x24 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x24 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x24 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x24 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x24 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x24 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x24 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x24 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x24 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x24 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x28 "PRM_IRQSTATUS_EVE3,This register provides status on EVE interrupt events" bitfld.long 0x28 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x28 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x28 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x28 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x28 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x28 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x28 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x28 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x28 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x28 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x28 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x28 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x28 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x28 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x28 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x28 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x2C "PRM_IRQSTATUS_EVE4,This register provides status on EVE interrupt events" bitfld.long 0x2C 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x2C 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x2C 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x2C 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x2C 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x2C 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x2C 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x2C 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x2C 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x2C 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x2C 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x2C 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x2C 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x2C 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x2C 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x2C 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x30 "PRM_IRQSTATUS_IPU1,This register provides status on IPU1 interrupt events" bitfld.long 0x30 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x30 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x30 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x30 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x30 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x30 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x30 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x30 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x30 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" newline bitfld.long 0x30 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x30 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x30 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" newline bitfld.long 0x30 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x30 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x30 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" newline bitfld.long 0x30 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x30 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" rgroup.long 0xF4++0x03 line.long 0x00 "PRM_DEBUG_OUT,This register is used to monitor the PRM's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xE4)++0x03 line.long 0x00 "PRM_DEBUG_CFG$1,This register is used to configure the PRM's 32-bit debug output" hexmask.long.word 0x00 0.--8. 1. "SEL1,Internal signal block select for debug word byte-1" repeat.end width 0x0B tree.end tree "RTC_PRM" base ad:0x4AE07C40 group.long 0x20++0x07 line.long 0x00 "PM_RTC_RTCSS_WKDEP,This register controls wakeup dependency based on RTCSS service requests" bitfld.long 0x00 19. "WKUPDEP_RTC_IRQ2_EVE4,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_RTC_IRQ2_EVE4_0,WKUPDEP_RTC_IRQ2_EVE4_1" bitfld.long 0x00 18. "WKUPDEP_RTC_IRQ2_EVE3,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_RTC_IRQ2_EVE3_0,WKUPDEP_RTC_IRQ2_EVE3_1" newline bitfld.long 0x00 17. "WKUPDEP_RTC_IRQ2_EVE2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_EVE2_0,WKUPDEP_RTC_IRQ2_EVE2_1" bitfld.long 0x00 16. "WKUPDEP_RTC_IRQ2_EVE1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_EVE1_0,WKUPDEP_RTC_IRQ2_EVE1_1" newline bitfld.long 0x00 15. "WKUPDEP_RTC_IRQ2_DSP2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_DSP2_0,WKUPDEP_RTC_IRQ2_DSP2_1" bitfld.long 0x00 14. "WKUPDEP_RTC_IRQ2_IPU1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_IPU1_0,WKUPDEP_RTC_IRQ2_IPU1_1" newline bitfld.long 0x00 12. "WKUPDEP_RTC_IRQ2_DSP1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_DSP1_0,WKUPDEP_RTC_IRQ2_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_RTC_IRQ2_IPU2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_IPU2_0,WKUPDEP_RTC_IRQ2_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_RTC_IRQ2_MPU,Wakeup dependency from RTCSS module (timer_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_MPU_0,WKUPDEP_RTC_IRQ2_MPU_1" bitfld.long 0x00 9. "WKUPDEP_RTC_IRQ1_EVE4,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_RTC_IRQ1_EVE4_0,WKUPDEP_RTC_IRQ1_EVE4_1" newline bitfld.long 0x00 8. "WKUPDEP_RTC_IRQ1_EVE3,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_RTC_IRQ1_EVE3_0,WKUPDEP_RTC_IRQ1_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_RTC_IRQ1_EVE2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_EVE2_0,WKUPDEP_RTC_IRQ1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_RTC_IRQ1_EVE1,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_EVE1_0,WKUPDEP_RTC_IRQ1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_RTC_IRQ1_DSP2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_DSP2_0,WKUPDEP_RTC_IRQ1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_RTC_IRQ1_IPU1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_IPU1_0,WKUPDEP_RTC_IRQ1_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_RTC_IRQ1_DSP1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_DSP1_0,WKUPDEP_RTC_IRQ1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_RTC_IRQ1_IPU2,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_IPU2_0,WKUPDEP_RTC_IRQ1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_RTC_IRQ1_MPU,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_MPU_0,WKUPDEP_RTC_IRQ1_MPU_1" line.long 0x04 "RM_RTC_RTCSS_CONTEXT,This register contains dedicated RTCSS context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "VPE_PRM" base ad:0x4AE07C80 group.long 0x00++0x07 line.long 0x00 "PM_VPE_PWRSTCTRL,This register controls the VPE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "VPE_BANK_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,VPE_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_VPE_PWRSTST,This register provides a status on the VPE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "VPE_BANK_STATEST,VPE_BANK memory state status - MEM_OFF" "VPE_BANK_STATEST_0,VPE_BANK_STATEST_1,VPE_BANK_STATEST_2,VPE_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x07 line.long 0x00 "PM_VPE_VPE_WKDEP,This register controls wakeup dependency based on VPE service requests" bitfld.long 0x00 9. "WKUPDEP_VPE_EVE4,Wakeup dependency from VPE module (Swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_VPE_EVE4_0,WKUPDEP_VPE_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_VPE_EVE3,Wakeup dependency from VPE module (Swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_VPE_EVE3_0,WKUPDEP_VPE_EVE3_1" bitfld.long 0x00 7. "WKUPDEP_VPE_EVE2,Wakeup dependency from VPE module (Swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_EVE2_0,WKUPDEP_VPE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_VPE_EVE1,Wakeup dependency from VPE module ( Swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_EVE1_0,WKUPDEP_VPE_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VPE_DSP2,Wakeup dependency from VPE module (Swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_DSP2_0,WKUPDEP_VPE_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_VPE_IPU1,Wakeup dependency from VPE module (Swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_IPU1_0,WKUPDEP_VPE_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_VPE_DSP1,Wakeup dependency from VPE module (Swakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_DSP1_0,WKUPDEP_VPE_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VPE_IPU2,Wakeup dependency from VPE module ( Swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_VPE_IPU2_0,WKUPDEP_VPE_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_VPE_MPU,Wakeup dependency from VPE module (Swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_MPU_0,WKUPDEP_VPE_MPU_1" line.long 0x04 "RM_VPE_VPE_CONTEXT,This register contains dedicated VPE context statuses" bitfld.long 0x04 8. "LOSTMEM_VPE_BANK,Specify if memory-based context in VPE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VPE_BANK_0,LOSTMEM_VPE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" width 0x0B tree.end tree "WKUPAON_CM" base ad:0x4AE07800 group.long 0x00++0x03 line.long 0x00 "CM_WKUPAON_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 19. "CLKACTIVITY_ADC_L3_GICLK,This field indicates the state of the ADC_L3_GICLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive] - INACT. - ACT" "CLKACTIVITY_ADC_L3_GICLK_0,CLKACTIVITY_ADC_L3_GICLK_1" rbitfld.long 0x00 18. "CLKACTIVITY_UART10_GFCLK,This field indicates the state of the UART10_GFCLK clock in the domain" "CLKACTIVITY_UART10_GFCLK_0,CLKACTIVITY_UART10_GFCLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_TIMER1_GFCLK,This field indicates the state of the TIMER1_GFCLK clock in the domain" "CLKACTIVITY_TIMER1_GFCLK_0,CLKACTIVITY_TIMER1_GFCLK_1" rbitfld.long 0x00 16. "CLKACTIVITY_DCAN1_SYS_CLK,This field indicates the state of the DCAN1_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN1_SYS_CLK_0,CLKACTIVITY_DCAN1_SYS_CLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_SYS_CLK_FUNC,This field indicates the state of the functional SYS_CLK clocks in the domain (this exclude activity of EMU_GCLK clock)" "CLKACTIVITY_SYS_CLK_FUNC_0,CLKACTIVITY_SYS_CLK_FUNC_1" rbitfld.long 0x00 12. "CLKACTIVITY_WKUPAON_GICLK,This field indicates the state of the WKUPAON_GICLK clock in the domain" "CLKACTIVITY_WKUPAON_GICLK_0,CLKACTIVITY_WKUPAON_GICLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_WKUPAON_SYS_GFCLK,This field indicates the state of the WKUPAON_SYS_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_SYS_GFCLK_0,CLKACTIVITY_WKUPAON_SYS_GFCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_ABE_LP_CLK,This field indicates the state of the ABE_LP_CLK clock in the domain" "CLKACTIVITY_ABE_LP_CLK_0,CLKACTIVITY_ABE_LP_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_SYS_CLK,This field indicates the state of the SYS_CLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive] - INACT. - ACT" "CLKACTIVITY_SYS_CLK_0,CLKACTIVITY_SYS_CLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_WKUPAON_L4_WKUP_CLKCTRL,This register manages the WKUPAON clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x30++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER2_CLKCTRL,This register manages the WD_TIMER2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_WKUPAON_GPIO1_CLKCTRL,This register manages the GPIO1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_WKUPAON_TIMER1_CLKCTRL,This register manages the TIMER1 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - SEL_TIMER_SYS_CLK" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,?,?,?,?,?" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x48++0x03 line.long 0x00 "CM_WKUPAON_TIMER12_CLKCTRL,This register manages the TIMER12 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_WKUPAON_COUNTER_32K_CLKCTRL,This register manages the COUNTER_32K clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x80++0x03 line.long 0x00 "CM_WKUPAON_UART10_CLKCTRL,This register manages the UART10 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_WKUPAON_DCAN1_CLKCTRL,This register manages the DCAN1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects SYS clock for DCAN1 between SYS_CLK1 and SYS_CLK2 - SEL_SYS_CLK1" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x03 line.long 0x00 "CM_WKUPAON_ADC_CLKCTRL,This register manages the MCAN clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" width 0x0B tree.end tree "WKUPAON_PRM" base ad:0x4AE07700 group.long 0x24++0x03 line.long 0x00 "RM_WKUPAON_L4_WKUP_CONTEXT,This register contains dedicated L4_WKUP context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x1F line.long 0x00 "PM_WKUPAON_WD_TIMER2_WKDEP,This register controls wakeup dependency based on WD_TIMER2 service requests" bitfld.long 0x00 9. "WKUPDEP_WD_TIMER2_EVE4,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_WD_TIMER2_EVE4_0,WKUPDEP_WD_TIMER2_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_WD_TIMER2_EVE3,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_WD_TIMER2_EVE3_0,WKUPDEP_WD_TIMER2_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_WD_TIMER2_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_EVE2_0,WKUPDEP_WD_TIMER2_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_WD_TIMER2_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_EVE1_0,WKUPDEP_WD_TIMER2_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_WD_TIMER2_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_DSP2_0,WKUPDEP_WD_TIMER2_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_WD_TIMER2_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_IPU1_0,WKUPDEP_WD_TIMER2_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_WD_TIMER2_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_DSP1_0,WKUPDEP_WD_TIMER2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_WD_TIMER2_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_WD_TIMER2_IPU2_0,WKUPDEP_WD_TIMER2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_WD_TIMER2_MPU,Wakeup dependency from WDT2 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains - DISABLED" "WKUPDEP_WD_TIMER2_MPU_0,WKUPDEP_WD_TIMER2_MPU_1" line.long 0x04 "RM_WKUPAON_WD_TIMER2_CONTEXT,This register contains dedicated WD_TIMER2 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests" bitfld.long 0x08 19. "WKUPDEP_GPIO1_IRQ2_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO1_IRQ2_EVE4_0,WKUPDEP_GPIO1_IRQ2_EVE4_1" bitfld.long 0x08 18. "WKUPDEP_GPIO1_IRQ2_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO1_IRQ2_EVE3_0,WKUPDEP_GPIO1_IRQ2_EVE3_1" newline bitfld.long 0x08 17. "WKUPDEP_GPIO1_IRQ2_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_EVE2_0,WKUPDEP_GPIO1_IRQ2_EVE2_1" bitfld.long 0x08 16. "WKUPDEP_GPIO1_IRQ2_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_EVE1_0,WKUPDEP_GPIO1_IRQ2_EVE1_1" newline bitfld.long 0x08 15. "WKUPDEP_GPIO1_IRQ2_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_DSP2_0,WKUPDEP_GPIO1_IRQ2_DSP2_1" bitfld.long 0x08 14. "WKUPDEP_GPIO1_IRQ2_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_IPU1_0,WKUPDEP_GPIO1_IRQ2_IPU1_1" newline bitfld.long 0x08 12. "WKUPDEP_GPIO1_IRQ2_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_DSP1_0,WKUPDEP_GPIO1_IRQ2_DSP1_1" bitfld.long 0x08 11. "WKUPDEP_GPIO1_IRQ2_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ2_IPU2_0,WKUPDEP_GPIO1_IRQ2_IPU2_1" newline bitfld.long 0x08 10. "WKUPDEP_GPIO1_IRQ2_MPU,Wakeup dependency from GPIO1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_MPU_0,WKUPDEP_GPIO1_IRQ2_MPU_1" bitfld.long 0x08 9. "WKUPDEP_GPIO1_IRQ1_EVE4,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_GPIO1_IRQ1_EVE4_0,WKUPDEP_GPIO1_IRQ1_EVE4_1" newline bitfld.long 0x08 8. "WKUPDEP_GPIO1_IRQ1_EVE3,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_GPIO1_IRQ1_EVE3_0,WKUPDEP_GPIO1_IRQ1_EVE3_1" bitfld.long 0x08 7. "WKUPDEP_GPIO1_IRQ1_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_EVE2_0,WKUPDEP_GPIO1_IRQ1_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_GPIO1_IRQ1_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_EVE1_0,WKUPDEP_GPIO1_IRQ1_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_GPIO1_IRQ1_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_DSP2_0,WKUPDEP_GPIO1_IRQ1_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_GPIO1_IRQ1_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_IPU1_0,WKUPDEP_GPIO1_IRQ1_IPU1_1" bitfld.long 0x08 2. "WKUPDEP_GPIO1_IRQ1_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_DSP1_0,WKUPDEP_GPIO1_IRQ1_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_GPIO1_IRQ1_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_GPIO1_IRQ1_IPU2_0,WKUPDEP_GPIO1_IRQ1_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_GPIO1_IRQ1_MPU,Wakeup dependency from GPIO1 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_MPU_0,WKUPDEP_GPIO1_IRQ1_MPU_1" line.long 0x0C "RM_WKUPAON_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_WKUPAON_TIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests" bitfld.long 0x10 9. "WKUPDEP_TIMER1_EVE4,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER1_EVE4_0,WKUPDEP_TIMER1_EVE4_1" bitfld.long 0x10 8. "WKUPDEP_TIMER1_EVE3,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER1_EVE3_0,WKUPDEP_TIMER1_EVE3_1" newline bitfld.long 0x10 7. "WKUPDEP_TIMER1_EVE2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_EVE2_0,WKUPDEP_TIMER1_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER1_EVE1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_EVE1_0,WKUPDEP_TIMER1_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER1_DSP2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_DSP2_0,WKUPDEP_TIMER1_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER1_IPU1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_IPU1_0,WKUPDEP_TIMER1_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER1_DSP1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_DSP1_0,WKUPDEP_TIMER1_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER1_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER1_IPU2_0,WKUPDEP_TIMER1_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER1_MPU,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_MPU_0,WKUPDEP_TIMER1_MPU_1" line.long 0x14 "RM_WKUPAON_TIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_WKUPAON_TIMER12_WKDEP,This register controls wakeup dependency based on TIMER12 service requests" bitfld.long 0x18 9. "WKUPDEP_TIMER12_EVE4,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_TIMER12_EVE4_0,WKUPDEP_TIMER12_EVE4_1" bitfld.long 0x18 8. "WKUPDEP_TIMER12_EVE3,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_TIMER12_EVE3_0,WKUPDEP_TIMER12_EVE3_1" newline bitfld.long 0x18 7. "WKUPDEP_TIMER12_EVE2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_EVE2_0,WKUPDEP_TIMER12_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER12_EVE1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_EVE1_0,WKUPDEP_TIMER12_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER12_DSP2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_DSP2_0,WKUPDEP_TIMER12_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER12_IPU1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_IPU1_0,WKUPDEP_TIMER12_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER12_DSP1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_DSP1_0,WKUPDEP_TIMER12_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER12_IPU2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_TIMER12_IPU2_0,WKUPDEP_TIMER12_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER12_MPU,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_MPU_0,WKUPDEP_TIMER12_MPU_1" line.long 0x1C "RM_WKUPAON_TIMER12_CONTEXT,This register contains dedicated TIMER12 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x54++0x03 line.long 0x00 "RM_WKUPAON_COUNTER_32K_CONTEXT,This register contains dedicated COUNTER_32K context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x80++0x0F line.long 0x00 "PM_WKUPAON_UART10_WKDEP,This register controls wakeup dependency based on UART10 service requests" bitfld.long 0x00 9. "WKUPDEP_UART10_EVE4,Wakeup dependency from UART10 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_UART10_EVE4_0,WKUPDEP_UART10_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_UART10_EVE3,Wakeup dependency from UART10 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_UART10_EVE3_0,WKUPDEP_UART10_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_UART10_EVE2,Wakeup dependency from UART10 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_EVE2_0,WKUPDEP_UART10_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_UART10_EVE1,Wakeup dependency from UART10 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_EVE1_0,WKUPDEP_UART10_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_UART10_DSP2,Wakeup dependency from UART10 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_DSP2_0,WKUPDEP_UART10_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_UART10_IPU1,Wakeup dependency from UART10 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_IPU1_0,WKUPDEP_UART10_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_UART10_SDMA,Wakeup dependency from UART10 module (SWakeup signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_SDMA_0,WKUPDEP_UART10_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_UART10_DSP1,Wakeup dependency from UART10 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_DSP1_0,WKUPDEP_UART10_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_UART10_IPU2,Wakeup dependency from UART10 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_UART10_IPU2_0,WKUPDEP_UART10_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_UART10_MPU,Wakeup dependency from UART10 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_MPU_0,WKUPDEP_UART10_MPU_1" line.long 0x04 "RM_WKUPAON_UART10_CONTEXT,This register contains dedicated UART10 context statuses" bitfld.long 0x04 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in UART memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_DCAN1_WKDEP,This register controls wakeup dependency based on DCAN1 service requests" bitfld.long 0x08 9. "WKUPDEP_DCAN1_EVE4,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_DCAN1_EVE4_0,WKUPDEP_DCAN1_EVE4_1" bitfld.long 0x08 8. "WKUPDEP_DCAN1_EVE3,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_DCAN1_EVE3_0,WKUPDEP_DCAN1_EVE3_1" newline bitfld.long 0x08 7. "WKUPDEP_DCAN1_EVE2,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_EVE2_0,WKUPDEP_DCAN1_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_DCAN1_EVE1,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_EVE1_0,WKUPDEP_DCAN1_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_DCAN1_DSP2,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_DSP2_0,WKUPDEP_DCAN1_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_DCAN1_IPU1,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_IPU1_0,WKUPDEP_DCAN1_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_DCAN1_SDMA,Wakeup dependency from DCAN1 module (SWakeup signal) towards SDMA + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_SDMA_0,WKUPDEP_DCAN1_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_DCAN1_DSP1,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_DSP1_0,WKUPDEP_DCAN1_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_DCAN1_IPU2,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "WKUPDEP_DCAN1_IPU2_0,WKUPDEP_DCAN1_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_DCAN1_MPU,Wakeup dependency from DCAN1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_MPU_0,WKUPDEP_DCAN1_MPU_1" line.long 0x0C "RM_WKUPAON_DCAN1_CONTEXT,This register contains dedicated DCAN1 context statuses" bitfld.long 0x0C 8. "LOSTMEM_DCAN_MEM,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_MEM_0,LOSTMEM_DCAN_MEM_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xA0++0x03 line.long 0x00 "PM_WKUPAON_ADC_WKDEP,This register controls wakeup dependency based on MCAN service requests" bitfld.long 0x00 9. "WKUPDEP_ADC_EVE4,Wakeup dependency from MCAN module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE4 is not supported in this family of devices" "WKUPDEP_ADC_EVE4_0,WKUPDEP_ADC_EVE4_1" bitfld.long 0x00 8. "WKUPDEP_ADC_EVE3,Wakeup dependency from MCAN module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domainsEVE3 is not supported in this family of devices" "WKUPDEP_ADC_EVE3_0,WKUPDEP_ADC_EVE3_1" newline bitfld.long 0x00 7. "WKUPDEP_ADC_EVE2,Wakeup dependency from MCAN module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_EVE2_0,WKUPDEP_ADC_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_ADC_EVE1,Wakeup dependency from MCAN module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_EVE1_0,WKUPDEP_ADC_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_ADC_DSP2,Wakeup dependency from MCAN module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_DSP2_0,WKUPDEP_ADC_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_ADC_IPU1,Wakeup dependency from MCAN module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_IPU1_0,WKUPDEP_ADC_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_ADC_DSP1,Wakeup dependency from MCAN module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_DSP1_0,WKUPDEP_ADC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_ADC_IPU2,Wakeup dependency from MCAN module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_IPU2_0,WKUPDEP_ADC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_ADC_MPU,Wakeup dependency from MCAN module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_ADC_MPU_0,WKUPDEP_ADC_MPU_1" width 0x0B tree.end tree.end tree "PWM_Subsystem_Resources" tree "PWMSS1_CFG" base ad:0x4843E000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "Software reset is completed,Software reset assertion" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM/eHRPWM module" "No effect,A request to stop.." bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module" "No effect,Enables the interface.." newline bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "No effect,A request to stop.." bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "No effect,Enables the interface.." newline bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "No effect,A request to stop.." bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "No effect,Enables the interface.." line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM/eHRPWM module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." width 0x0B tree.end tree "PWMSS2_CFG" base ad:0x48440000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "Software reset is completed,Software reset assertion" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM/eHRPWM module" "No effect,A request to stop.." bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module" "No effect,Enables the interface.." newline bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "No effect,A request to stop.." bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "No effect,Enables the interface.." newline bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "No effect,A request to stop.." bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "No effect,Enables the interface.." line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM/eHRPWM module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." width 0x0B tree.end tree "PWMSS3_CFG" base ad:0x48442000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "Software reset is completed,Software reset assertion" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM/eHRPWM module" "No effect,A request to stop.." bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module" "No effect,Enables the interface.." newline bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "No effect,A request to stop.." bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "No effect,Enables the interface.." newline bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "No effect,A request to stop.." bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "No effect,Enables the interface.." line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM. eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM/eHRPWM module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." newline bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "No interface clock stop acknowledged,Interface clock stop request is acknowledged for.." bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "No clock enable request acknowledged,Interface clock enable request is acknowledged.." width 0x0B tree.end tree "PWMSS1_ECAP" base ad:0x4843E100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "TSCNT counter stops immediately on emulation..,TSCNT counter runs until = 0,TSCNT counter is unaffected by emulation suspend..,TSCNT counter is unaffected by emulation suspend.." bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "Divide by 1 (i.e . no prescale..,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 60,Divide by 62" newline bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register..,Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register.." bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "Do not reset counter on Capture Event 4..,Reset counter after Capture Event 4 time-stamp.." newline bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "Capture Event 4 triggered on a rising edge (RE),Capture Event 4 triggered on a falling edge (FE)" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "Do not reset counter on Capture Event 3..,Reset counter after Event 3 time-stamp has been.." newline bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "Capture Event 3 triggered on a rising edge (RE),Capture Event 3 triggered on a falling edge (FE)" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "Do not reset counter on Capture Event 2..,Reset counter after Event 2 time-stamp has been.." newline bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "Capture Event 2 triggered on a rising edge (RE),Capture Event 2 triggered on a falling edge (FE)" bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "Do not reset counter on Capture Event 1..,Reset counter after Event 1 time-stamp has been.." newline bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "Capture Event 1 triggered on a rising edge (RE),Capture Event 1 triggered on a falling edge (FE)" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.." bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" newline bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "Writing a zero has no effect,Writing a one forces a TSCNT shadow load of.." bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "Select sync-in event to be the sync-out signal..,Select TSCNT = PRD event to be the sync-out signal,Disable sync out signal,Disable sync out signal" newline bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "Disable sync-in option,Enable counter (TSCNT) to be loaded from" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running" newline bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode" newline bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "Disable Compare Equal as an Interrupt source,Enable Compare Equal as an Interrupt source" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "Disable Period Equal as an Interrupt source,Enable Period Equal as an Interrupt source" newline bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source" newline bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source" newline bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.." bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.." newline bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.." bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAPn pin" newline bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAPn pin" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAPn pin" newline bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAPn pin" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition" newline bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" newline bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition" newline bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.." line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit" newline bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit" newline bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit" newline bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "No effect,Writing a 1 sets the.." rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" width 0x0B tree.end tree "PWMSS2_ECAP" base ad:0x48440100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "TSCNT counter stops immediately on emulation..,TSCNT counter runs until = 0,TSCNT counter is unaffected by emulation suspend..,TSCNT counter is unaffected by emulation suspend.." bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "Divide by 1 (i.e . no prescale..,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 60,Divide by 62" newline bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register..,Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register.." bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "Do not reset counter on Capture Event 4..,Reset counter after Capture Event 4 time-stamp.." newline bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "Capture Event 4 triggered on a rising edge (RE),Capture Event 4 triggered on a falling edge (FE)" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "Do not reset counter on Capture Event 3..,Reset counter after Event 3 time-stamp has been.." newline bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "Capture Event 3 triggered on a rising edge (RE),Capture Event 3 triggered on a falling edge (FE)" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "Do not reset counter on Capture Event 2..,Reset counter after Event 2 time-stamp has been.." newline bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "Capture Event 2 triggered on a rising edge (RE),Capture Event 2 triggered on a falling edge (FE)" bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "Do not reset counter on Capture Event 1..,Reset counter after Event 1 time-stamp has been.." newline bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "Capture Event 1 triggered on a rising edge (RE),Capture Event 1 triggered on a falling edge (FE)" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.." bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" newline bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "Writing a zero has no effect,Writing a one forces a TSCNT shadow load of.." bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "Select sync-in event to be the sync-out signal..,Select TSCNT = PRD event to be the sync-out signal,Disable sync out signal,Disable sync out signal" newline bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "Disable sync-in option,Enable counter (TSCNT) to be loaded from" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running" newline bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode" newline bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "Disable Compare Equal as an Interrupt source,Enable Compare Equal as an Interrupt source" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "Disable Period Equal as an Interrupt source,Enable Period Equal as an Interrupt source" newline bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source" newline bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source" newline bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.." bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.." newline bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.." bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAPn pin" newline bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAPn pin" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAPn pin" newline bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAPn pin" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition" newline bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" newline bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition" newline bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.." line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit" newline bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit" newline bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit" newline bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "No effect,Writing a 1 sets the.." rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" width 0x0B tree.end tree "PWMSS3_ECAP" base ad:0x48442100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "TSCNT counter stops immediately on emulation..,TSCNT counter runs until = 0,TSCNT counter is unaffected by emulation suspend..,TSCNT counter is unaffected by emulation suspend.." bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "Divide by 1 (i.e . no prescale..,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 60,Divide by 62" newline bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register..,Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register.." bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "Do not reset counter on Capture Event 4..,Reset counter after Capture Event 4 time-stamp.." newline bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "Capture Event 4 triggered on a rising edge (RE),Capture Event 4 triggered on a falling edge (FE)" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "Do not reset counter on Capture Event 3..,Reset counter after Event 3 time-stamp has been.." newline bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "Capture Event 3 triggered on a rising edge (RE),Capture Event 3 triggered on a falling edge (FE)" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "Do not reset counter on Capture Event 2..,Reset counter after Event 2 time-stamp has been.." newline bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "Capture Event 2 triggered on a rising edge (RE),Capture Event 2 triggered on a falling edge (FE)" bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "Do not reset counter on Capture Event 1..,Reset counter after Event 1 time-stamp has been.." newline bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "Capture Event 1 triggered on a rising edge (RE),Capture Event 1 triggered on a falling edge (FE)" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "Output is active high (Compare value defines..,Output is active low (Compare value defines low.." bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" newline bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "Writing a zero has no effect,Writing a one forces a TSCNT shadow load of.." bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "Select sync-in event to be the sync-out signal..,Select TSCNT = PRD event to be the sync-out signal,Disable sync out signal,Disable sync out signal" newline bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "Disable sync-in option,Enable counter (TSCNT) to be loaded from" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "TSCNT stopped,TSCNT free-running" newline bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "Has no effect (reading always returns a 0),Arms the one-shot sequence as follows" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "Stop after Capture Event 1 in one-shot mode,Stop after Capture Event 2 in one-shot mode,Stop after Capture Event 3 in one-shot mode,Stop after Capture Event 4 in one-shot mode" newline bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "Operate in continuous mode,Operate in one-shot mode" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "Disable Compare Equal as an Interrupt source,Enable Compare Equal as an Interrupt source" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "Disable Period Equal as an Interrupt source,Enable Period Equal as an Interrupt source" newline bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "Disable counter Overflow as an Interrupt source,Enable counter Overflow as an Interrupt source" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "Disable Capture Event 4 as an Interrupt source,Enable Capture Event 4 as an Interrupt source" newline bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "Disable Capture Event 3 as an Interrupt source,Enable Capture Event 3 as an Interrupt source" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "Disable Capture Event 2 as an Interrupt source,Enable Capture Event 2 as an Interrupt source" newline bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "Disable Capture Event 1 as an Interrupt source,Enable Capture Event 1 as an Interrupt source" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the.." bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) reached the period.." newline bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "Indicates no event occurred,Indicates the counter (TSCNT) has made the.." bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "Indicates no event occurred,Indicates the fourth event occurred at ECAPn pin" newline bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "Indicates no event occurred,Indicates the third event occurred at ECAPn pin" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "Indicates no event occurred,Indicates the second event occurred at ECAPn pin" newline bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "Indicates no event occurred,Indicates the first event occurred at ECAPn pin" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "Indicates no interrupt generated,Indicates that an interrupt was generated" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=CMP flag condition" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "Writing a 0 has no effect,Writing a 1 clears the TSCNT=PRD flag condition" newline bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CNTOVF flag condition" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" newline bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT3 flag condition" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT2 flag condition" newline bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "Writing a 0 has no effect,Writing a 1 clears the CEVT1 flag condition" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "Writing a 0 has no effect,Writing a 1 clears the INT flag and enable.." line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "No effect,Writing a 1 sets the TSCNT=CMP flag bit" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "No effect,Writing a 1 sets the TSCNT=PRD flag bit" newline bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "No effect,Writing a 1 to this bit sets the CNTOVF flag bit" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "No effect,Writing a 1 sets the CEVT4 flag bit" newline bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "No effect,Writing a 1 sets the CEVT3 flag bit" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "No effect,Writing a 1 sets the CEVT2 flag bit" newline bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "No effect,Writing a 1 sets the.." rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" width 0x0B tree.end tree "PWMSS1_EPWM" base ad:0x4843E200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "Stop after the next time-base counter increment..,Stop when counter completes a whole cycle,Free run,Free run" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "Count down after the synchronization event,Count up after the synchronization event" newline bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "/1..,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "/1,/2..,/4,/6,/8,/10,/12,/14" newline bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "Writing a 0 has no effect and reads always..,Writing a 1 forces a one-time synchronization.." bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "Time-base counter equal to zero (,TBCNT =,TBCNT = CMPB,Disable EPWMxSYNCO signal" newline bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "The period register (,Load" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "Do not load the time-base counter (,Load the time-base counter with the phase.." newline bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "Up-count mode,Down-count mode,Up-down-count mode,Stop-freeze counter operation (default on.." line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "Reading a 0 indicates the time-base counter..,Reading a 1 on this bit indicates that the.." bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "Writing a 0 will have no effect,Reading a 1 on this bit indicates that an.." newline bitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "Time-Base Counter is currently counting down,Time-Base Counter is currently counting up" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," bitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "CMPB shadow FIFO not full yet,Indicates the CMPB shadow FIFO is full" bitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "CMPA shadow FIFO not full yet,Indicates the CMPA shadow FIFO is full a CPU.." newline bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "Shadow mode,Immediate mode" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "Shadow mode,Immediate mode" newline bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "?,Load on event counter equals period,Load on event counter equals zero or counter..,Load immediately (the active register is.." bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "Writing a 0 (zero) has no effect,Initiates a single s/w forced event" newline bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "Writing a 0 (zero) has no effect,Initiates a single software forced event" newline bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "Forcing disabled that is has no effect,Forces a continuous low on output B,Forces a continuous high on output B,Software forcing is disabled and has no effect" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "Forcing disabled that is has no effect,Forces a continuous low on output A,Forces a continuous high on output A,Software forcing is disabled and has no effect" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the..,EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the.." bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "Active high (AH) mode,Active low complementary (ALC) mode,Active high complementary (AHC),Active low (AL) mode" newline bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "Dead-band generation is bypassed for both output..,Disable rising-edge delay,Disable falling-edge delay,Dead-band is fully enabled for both rising-edge.." line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," abitfld.word 0x16 8.--15. "OSHTN,Trip-zone n (TZn) select" "0x00=Disable TZn as a one-shot trip source for..,0x01=Enable TZn as a one-shot trip source for.." bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "Disable TZ0 as a CBC trip source for this ePWM..,Enable TZ0 as a CBC trip source for this ePWM.." group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "High impedance (EPWMxB = High-impedance state),Force EPWMxB to a high state,Force EPWMxB to a low state,Do nothing no action is taken on EPWMxB" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "High impedance (EPWMxA = High-impedance state),Force EPWMxA to a high state,Force EPWMxA to a low state,Do nothing no action is taken on EPWMxA" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation; a one-shot trip.." bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation; a cycle-by-cycle.." line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "No one-shot trip event has occurred,Indicates a trip event has occurred on a pin.." bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "No cycle-by-cycle trip event has occurred,Indicates a trip event has occurred on a pin.." newline bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "Indicates no interrupt has been generated,Indicates an EPWMxTZINT interrupt was generated.." line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "Has no effect,Clears this Trip (set) condition" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "Has no effect,Clears this Trip (set) condition" newline bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "Has no effect,Clears the trip-interrupt flag for this ePWM.." line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "Writing of 0 is ignored,Forces a one-shot trip event and sets" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "Writing of 0 is ignored,Forces a cycle-by-cycle trip event and sets" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disable EPWMx_INT generation,Enable EPWMx_INT generation" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,Enable event time-base counter equal to zero,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event,Enable event" line.word 0x0C "EPWM_ETPS," bitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "No events have occurred,1 event has occurred,2 events have occurred,3 events have occurred" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "Disable the interrupt event counter,Generate an interrupt on the first event INTCNT..,Generate interrupt on,Generate interrupt on" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Indicates no event occurred,Indicates that an ePWMx interrupt (EWPMx_INT).." line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "Writing a 0 has no effect,Writing 1 clears" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "Writing 0 to this bit will be ignored,Writing 1 generates an interrupt on EPWMxINT and.." line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "Duty = 1/8 (12.5%),Duty = 2/8 (25.0%),Duty = 3/8 (37.5%),Duty = 4/8 (50.0%),Duty = 5/8 (62.5%),Duty = 6/8 (75.0%),Duty = 7/8 (87.5%),Reserved" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "Divide by 1 (no prescale),Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8" newline bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "?,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,?..." bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "Disable (bypass) PWM chopping function,Enable chopping function" group.word 0xC0++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "Select CNT_zero pulse,Select PRD_eq pulse" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "Select CMPAHR(8) bus from compare module of EPWM..,Select TBPHSHR(8) bus from time base module" newline bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "No delay inserted (default on reset),Delay inserted rising edge,Delay inserted falling edge,Delay inserted on both edges" width 0x0B tree.end tree "PWMSS2_EPWM" base ad:0x48440200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "Stop after the next time-base counter increment..,Stop when counter completes a whole cycle,Free run,Free run" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "Count down after the synchronization event,Count up after the synchronization event" newline bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "/1..,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "/1,/2..,/4,/6,/8,/10,/12,/14" newline bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "Writing a 0 has no effect and reads always..,Writing a 1 forces a one-time synchronization.." bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "Time-base counter equal to zero (,TBCNT =,TBCNT = CMPB,Disable EPWMxSYNCO signal" newline bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "The period register (,Load" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "Do not load the time-base counter (,Load the time-base counter with the phase.." newline bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "Up-count mode,Down-count mode,Up-down-count mode,Stop-freeze counter operation (default on.." line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "Reading a 0 indicates the time-base counter..,Reading a 1 on this bit indicates that the.." bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "Writing a 0 will have no effect,Reading a 1 on this bit indicates that an.." newline bitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "Time-Base Counter is currently counting down,Time-Base Counter is currently counting up" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," bitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "CMPB shadow FIFO not full yet,Indicates the CMPB shadow FIFO is full" bitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "CMPA shadow FIFO not full yet,Indicates the CMPA shadow FIFO is full a CPU.." newline bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "Shadow mode,Immediate mode" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "Shadow mode,Immediate mode" newline bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "?,Load on event counter equals period,Load on event counter equals zero or counter..,Load immediately (the active register is.." bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "Writing a 0 (zero) has no effect,Initiates a single s/w forced event" newline bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "Writing a 0 (zero) has no effect,Initiates a single software forced event" newline bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "Forcing disabled that is has no effect,Forces a continuous low on output B,Forces a continuous high on output B,Software forcing is disabled and has no effect" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "Forcing disabled that is has no effect,Forces a continuous low on output A,Forces a continuous high on output A,Software forcing is disabled and has no effect" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the..,EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the.." bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "Active high (AH) mode,Active low complementary (ALC) mode,Active high complementary (AHC),Active low (AL) mode" newline bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "Dead-band generation is bypassed for both output..,Disable rising-edge delay,Disable falling-edge delay,Dead-band is fully enabled for both rising-edge.." line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," abitfld.word 0x16 8.--15. "OSHTN,Trip-zone n (TZn) select" "0x00=Disable TZn as a one-shot trip source for..,0x01=Enable TZn as a one-shot trip source for.." bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "Disable TZ0 as a CBC trip source for this ePWM..,Enable TZ0 as a CBC trip source for this ePWM.." group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "High impedance (EPWMxB = High-impedance state),Force EPWMxB to a high state,Force EPWMxB to a low state,Do nothing no action is taken on EPWMxB" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "High impedance (EPWMxA = High-impedance state),Force EPWMxA to a high state,Force EPWMxA to a low state,Do nothing no action is taken on EPWMxA" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation; a one-shot trip.." bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation; a cycle-by-cycle.." line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "No one-shot trip event has occurred,Indicates a trip event has occurred on a pin.." bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "No cycle-by-cycle trip event has occurred,Indicates a trip event has occurred on a pin.." newline bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "Indicates no interrupt has been generated,Indicates an EPWMxTZINT interrupt was generated.." line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "Has no effect,Clears this Trip (set) condition" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "Has no effect,Clears this Trip (set) condition" newline bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "Has no effect,Clears the trip-interrupt flag for this ePWM.." line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "Writing of 0 is ignored,Forces a one-shot trip event and sets" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "Writing of 0 is ignored,Forces a cycle-by-cycle trip event and sets" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disable EPWMx_INT generation,Enable EPWMx_INT generation" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,Enable event time-base counter equal to zero,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event,Enable event" line.word 0x0C "EPWM_ETPS," bitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "No events have occurred,1 event has occurred,2 events have occurred,3 events have occurred" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "Disable the interrupt event counter,Generate an interrupt on the first event INTCNT..,Generate interrupt on,Generate interrupt on" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Indicates no event occurred,Indicates that an ePWMx interrupt (EWPMx_INT).." line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "Writing a 0 has no effect,Writing 1 clears" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "Writing 0 to this bit will be ignored,Writing 1 generates an interrupt on EPWMxINT and.." line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "Duty = 1/8 (12.5%),Duty = 2/8 (25.0%),Duty = 3/8 (37.5%),Duty = 4/8 (50.0%),Duty = 5/8 (62.5%),Duty = 6/8 (75.0%),Duty = 7/8 (87.5%),Reserved" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "Divide by 1 (no prescale),Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8" newline bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "?,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,?..." bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "Disable (bypass) PWM chopping function,Enable chopping function" group.word 0xC0++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "Select CNT_zero pulse,Select PRD_eq pulse" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "Select CMPAHR(8) bus from compare module of EPWM..,Select TBPHSHR(8) bus from time base module" newline bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "No delay inserted (default on reset),Delay inserted rising edge,Delay inserted falling edge,Delay inserted on both edges" width 0x0B tree.end tree "PWMSS3_EPWM" base ad:0x48442200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "Stop after the next time-base counter increment..,Stop when counter completes a whole cycle,Free run,Free run" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "Count down after the synchronization event,Count up after the synchronization event" newline bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "/1..,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "/1,/2..,/4,/6,/8,/10,/12,/14" newline bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "Writing a 0 has no effect and reads always..,Writing a 1 forces a one-time synchronization.." bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "Time-base counter equal to zero (,TBCNT =,TBCNT = CMPB,Disable EPWMxSYNCO signal" newline bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "The period register (,Load" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "Do not load the time-base counter (,Load the time-base counter with the phase.." newline bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "Up-count mode,Down-count mode,Up-down-count mode,Stop-freeze counter operation (default on.." line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "Reading a 0 indicates the time-base counter..,Reading a 1 on this bit indicates that the.." bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "Writing a 0 will have no effect,Reading a 1 on this bit indicates that an.." newline bitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "Time-Base Counter is currently counting down,Time-Base Counter is currently counting up" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," bitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "CMPB shadow FIFO not full yet,Indicates the CMPB shadow FIFO is full" bitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "CMPA shadow FIFO not full yet,Indicates the CMPA shadow FIFO is full a CPU.." newline bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "Shadow mode,Immediate mode" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "Shadow mode,Immediate mode" newline bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "Time-base counter equal to zero (,Load on TBCNT = PRD,Load on either TBCNT = 0 or TBCNT = PRD,Freeze (no loads possible)" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" newline bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxA output" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" newline bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "Do nothing (action disabled),Clear,Set,Toggle EPWMxB output" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "?,Load on event counter equals period,Load on event counter equals zero or counter..,Load immediately (the active register is.." bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "Writing a 0 (zero) has no effect,Initiates a single s/w forced event" newline bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "Writing a 0 (zero) has no effect,Initiates a single software forced event" newline bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "Does nothing (action disabled),Clear (low),Set (high),Toggle (Low -> High High -> Low)" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "Forcing disabled that is has no effect,Forces a continuous low on output B,Forces a continuous high on output B,Software forcing is disabled and has no effect" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "Forcing disabled that is has no effect,Forces a continuous low on output A,Forces a continuous high on output A,Software forcing is disabled and has no effect" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the..,EPWMxA In (from the action-qualifier) is the..,EPWMxB In (from the action-qualifier) is the.." bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "Active high (AH) mode,Active low complementary (ALC) mode,Active high complementary (AHC),Active low (AL) mode" newline bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "Dead-band generation is bypassed for both output..,Disable rising-edge delay,Disable falling-edge delay,Dead-band is fully enabled for both rising-edge.." line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," abitfld.word 0x16 8.--15. "OSHTN,Trip-zone n (TZn) select" "0x00=Disable TZn as a one-shot trip source for..,0x01=Enable TZn as a one-shot trip source for.." bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "Disable TZ0 as a CBC trip source for this ePWM..,Enable TZ0 as a CBC trip source for this ePWM.." group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "High impedance (EPWMxB = High-impedance state),Force EPWMxB to a high state,Force EPWMxB to a low state,Do nothing no action is taken on EPWMxB" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "High impedance (EPWMxA = High-impedance state),Force EPWMxA to a high state,Force EPWMxA to a low state,Do nothing no action is taken on EPWMxA" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "Disable one-shot interrupt generation,Enable Interrupt generation; a one-shot trip.." bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disable cycle-by-cycle interrupt generation,Enable interrupt generation; a cycle-by-cycle.." line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "No one-shot trip event has occurred,Indicates a trip event has occurred on a pin.." bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "No cycle-by-cycle trip event has occurred,Indicates a trip event has occurred on a pin.." newline bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "Indicates no interrupt has been generated,Indicates an EPWMxTZINT interrupt was generated.." line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "Has no effect,Clears this Trip (set) condition" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "Has no effect,Clears this Trip (set) condition" newline bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "Has no effect,Clears the trip-interrupt flag for this ePWM.." line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "Writing of 0 is ignored,Forces a one-shot trip event and sets" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "Writing of 0 is ignored,Forces a cycle-by-cycle trip event and sets" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disable EPWMx_INT generation,Enable EPWMx_INT generation" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,Enable event time-base counter equal to zero,Enable event time-base counter equal to period..,Reserved,Enable event time-base counter equal to CMPA..,Enable event time-base counter equal to CMPA..,Enable event,Enable event" line.word 0x0C "EPWM_ETPS," bitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "No events have occurred,1 event has occurred,2 events have occurred,3 events have occurred" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "Disable the interrupt event counter,Generate an interrupt on the first event INTCNT..,Generate interrupt on,Generate interrupt on" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Indicates no event occurred,Indicates that an ePWMx interrupt (EWPMx_INT).." line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "Writing a 0 has no effect,Writing 1 clears" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "Writing 0 to this bit will be ignored,Writing 1 generates an interrupt on EPWMxINT and.." line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "Duty = 1/8 (12.5%),Duty = 2/8 (25.0%),Duty = 3/8 (37.5%),Duty = 4/8 (50.0%),Duty = 5/8 (62.5%),Duty = 6/8 (75.0%),Duty = 7/8 (87.5%),Reserved" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "Divide by 1 (no prescale),Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7,Divide by 8" newline bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "?,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,SYSCLKOUT/8 wide,?..." bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "Disable (bypass) PWM chopping function,Enable chopping function" group.word 0xC0++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "Select CNT_zero pulse,Select PRD_eq pulse" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "Select CMPAHR(8) bus from compare module of EPWM..,Select TBPHSHR(8) bus from time base module" newline bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "No delay inserted (default on reset),Delay inserted rising edge,Delay inserted falling edge,Delay inserted on both edges" width 0x0B tree.end tree "PWMSS1_EQEP" base ad:0x4843E180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.." bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output" newline bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output" bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution" newline bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" newline bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input" bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input" newline bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input" bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "x stops immediately,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event" newline bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.." newline bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.." bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "The position counter is latched on the rising..,Clockwise Direction" newline bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled" newline bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "Latch on position counter read by CPU,Latch on unit time out" bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer" newline bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128" newline bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP" newline bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit" newline abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.." line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.." newline bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match" newline bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.." bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow" newline bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout" newline bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction" bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB" newline bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.." line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt" bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt" line.word 0x14 "EQEP_QEPSTS," bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected" bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.." newline bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)" bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.." newline bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.." newline bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse" bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," width 0x0B tree.end tree "PWMSS2_EQEP" base ad:0x48440180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.." bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output" newline bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output" bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution" newline bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" newline bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input" bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input" newline bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input" bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "x stops immediately,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event" newline bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.." newline bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.." bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "The position counter is latched on the rising..,Clockwise Direction" newline bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled" newline bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "Latch on position counter read by CPU,Latch on unit time out" bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer" newline bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128" newline bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP" newline bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit" newline abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.." line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.." newline bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match" newline bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.." bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow" newline bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout" newline bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction" bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB" newline bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.." line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt" bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt" line.word 0x14 "EQEP_QEPSTS," bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected" bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.." newline bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)" bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.." newline bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.." newline bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse" bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," width 0x0B tree.end tree "PWMSS3_EQEP" base ad:0x48442180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "Quadrature count mode (QCLK = iCLK QDIR = iDIR),Direction-count mode (QCLK = xCLK QDIR = xDIR),UP count mode for frequency measurement (QCLK =..,DOWN count mode for frequency measurement (QCLK.." bitfld.word 0x04 13. "SOEN,Sync output-enable" "Disable position-compare sync output,Enable position-compare sync output" newline bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "Index pin is used for sync output,Strobe pin is used for sync output" bitfld.word 0x04 11. "XCR,External clock rate" "2x resolution,1x resolution" newline bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "Quadrature-clock inputs are not swapped,Quadrature-clock inputs are swapped" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" newline bitfld.word 0x04 8. "QAP,QEPA input polarity" "No effect,Negates QEPA input" bitfld.word 0x04 7. "QBP,QEPB input polarity" "No effect,Negates QEPB input" newline bitfld.word 0x04 6. "QIP,QEPI input polarity" "No effect,Negates QEPI input" bitfld.word 0x04 5. "QSP,QEPS input polarity" "No effect,Negates QEPS input" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "x stops immediately,x continues to count until the rollover,x is unaffected by emulation suspend,x is unaffected by emulation suspend" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "Position counter reset on an index event,Position counter reset on the maximum position,Position counter reset on the first index event,Position counter reset on a unit time event" newline bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "Does nothing (action disabled),Does nothing (action disabled),Initializes the position counter on rising edge..,Clockwise Direction" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "Do nothing (action disabled),Do nothing (action disabled),Initializes the position counter on the rising..,Initializes the position counter on the falling.." newline bitfld.word 0x06 7. "SWI,Software initialization of position counter" "Do nothing (action disabled),Initialize position counter this bit is cleared.." bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "The position counter is latched on the rising..,Clockwise Direction" newline bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "Reserved,Latches position counter on rising edge of the..,Latches position counter on falling edge of the..,Software index marker" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "Reset the eQEP peripheral internal operating..,eQEP position counter is enabled" newline bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "Latch on position counter read by CPU,Latch on unit time out" bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "Disable eQEP unit timer,Enable unit timer" newline bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "Disable the eQEP watchdog timer,Enable the eQEP watchdog timer" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "eQEP capture unit is disabled,eQEP capture unit is enabled" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "CAPCLK = SYSCLKOUT/1,CAPCLK = SYSCLKOUT/2,CAPCLK = SYSCLKOUT/4,CAPCLK = SYSCLKOUT/8,CAPCLK = SYSCLKOUT/16,CAPCLK = SYSCLKOUT/32,CAPCLK = SYSCLKOUT/64,CAPCLK = SYSCLKOUT/128" newline bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "UPEVNT = QCLK/1,UPEVNT = QCLK/2,UPEVNT = QCLK/4,UPEVNT = QCLK/8,UPEVNT = QCLK/16,UPEVNT = QCLK/32,UPEVNT = QCLK/64,UPEVNT = QCLK/128,UPEVNT = QCLK/256,UPEVNT = QCLK/512,UPEVNT = QCLK/1024,UPEVNT = QCLK/2048,Reserved,Reserved,Reserved,Reserved" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "Shadow disabled load Immediate,Shadow enabled" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "Load on QPOSCNT = 0,Load when QPOSCNT = QPOSCMP" newline bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "Active HIGH pulse output,Active LOW pulse output" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "Disable position compare unit,Enable position compare unit" newline abitfld.word 0x0A 0.--11. "PCSPW,Select-position-compare sync output pulse width" "0x000=1 x 4 x SYSCLKOUT cycles,0x001=2 x 4 x SYSCLKOUT cycles,0x002=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x..,0xFFF=3 x 4 x SYSCLKOUT cycles to 4096 x 4 x.." line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "Interrupt is disabled,Interrupt is enabled" bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "Interrupt is disabled,Interrupt is enabled" newline bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "Interrupt is disabled,Interrupt is enabled" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "No interrupt generated,Set by eQEP unit timer period match" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to.." newline bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "No interrupt generated,This bit is set after latching the QPOSCNT to" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "No interrupt generated,This bit is set on position-compare match" newline bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "No interrupt generated,This bit is set after transferring the shadow.." bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "No interrupt generated,This bit is set on position counter overflow" newline bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "No interrupt generated,This bit is set on position counter underflow" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "No interrupt generated,Set by watch dog timeout" newline bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "No interrupt generated,This bit is set during change of direction" bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "No interrupt generated,Set on simultaneous transition of QEPA and QEPB" newline bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "No interrupt generated,Position counter error" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "No interrupt generated,Interrupt was generated" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "No effect,Clears the interrupt flag" newline bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "No effect,Clears the interrupt flag" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "No effect,Clears the interrupt flag.." line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "No effect,Force the interrupt" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "No effect,Force the interrupt" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "No effect,Force the interrupt" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "No effect,Force the interrupt" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "No effect,Force the interrupt" bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "No effect,Force the interrupt" newline bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "No effect,Force the interrupt" line.word 0x14 "EQEP_QEPSTS," bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "No unit position event detected,Unit position event detected" bitfld.word 0x14 6. "FDF,Direction on the first index marker" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on the.." newline bitfld.word 0x14 5. "QDF,Quadrature direction flag" "Counter-clockwise rotation (or reverse movement),Clockwise rotation (or forward movement)" bitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "Counter-clockwise rotation (or reverse movement)..,Clockwise rotation (or forward movement) on.." newline bitfld.word 0x14 3. "COEF,Capture overflow error flag" "Sticky bit cleared by writing 1,Overflow occurred in eQEP Capture timer (QEPCTMR)" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "Sticky bit cleared by writing 1,Direction change occurred between the capture.." newline bitfld.word 0x14 1. "FIMF,First index marker flag" "Sticky bit cleared by writing 1,Set by first occurrence of index pulse" bitfld.word 0x14 0. "PCEF,Position counter error flag" "No error occurred during the last index transition,Position counter error" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," width 0x0B tree.end tree.end tree "Quad_Serial_Peripheral_Interface" base ad:0x4B300000 rgroup.long 0x00++0x03 line.long 0x00 "QSPI_PID,Revision register" group.long 0x10++0x03 line.long 0x00 "QSPI_SYSCONFIG," bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Reserved" group.long 0x20++0x13 line.long 0x00 "QSPI_INTR_STATUS_RAW_SET,This register contains raw interrupt status flags" bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status" "WIRQ_RAW_0,WIRQ_RAW_1" bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status" "FIRQ_RAW_0,FIRQ_RAW_1" line.long 0x04 "QSPI_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status" "WIRQ_ENA_0,WIRQ_ENA_1" bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status" "FIRQ_ENA_0,FIRQ_ENA_1" line.long 0x08 "QSPI_INTR_ENABLE_SET_REG,This register enables the interrupts" bitfld.long 0x08 1. "WIRQ_ENA_SET,Word interrupt enable.Read" "WIRQ_ENA_SET_0,WIRQ_ENA_SET_1" bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame interrupt enable.Read" "FIRQ_ENA_SET_0,FIRQ_ENA_SET_1" line.long 0x0C "QSPI_INTR_ENABLE_CLEAR_REG,This register disables the interrupts" bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word interrupt disable.Read" "WIRQ_ENA_CLR_0,WIRQ_ENA_CLR_1" bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame interrupt disable.Read" "FIRQ_ENA_CLR_0,FIRQ_ENA_CLR_1" line.long 0x10 "QSPI_INTC_EOI_REG,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if a new interrupt event is pending. when using the pulsed output" group.long 0x40++0x33 line.long 0x00 "QSPI_SPI_CLOCK_CNTRL_REG,This register controls the external SPI clock generation" bitfld.long 0x00 31. "CLKEN,External SPI clock (qspi1_sclk) enable" "CLKEN_0,CLKEN_1" hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Divide ratio for the external SPI clock (qspi1_sclk)" line.long 0x04 "QSPI_SPI_DC_REG,This register controls the different modes for each output chip select" bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3" "CSP3_0,CSP3_1" bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3" "CKP3_0,CKP3_1" newline bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2" "CSP2_0,CSP2_1" bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2" "CKP2_0,CKP2_1" newline bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1" "CSP1_0,CSP1_1" bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1" "CKP1_0,CKP1_1" newline bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0" "Data is output on the same cycle as the..,Data is output 1 qspi1_sclk cycle after the..,Data is output 2 qspi1_sclk cycles after the..,Data is output 3 qspi1_sclk cycles after the.." bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "Data shifted out on rising edge; input on,Data shifted out on falling edge; input on" newline bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0" "CSP0_0,CSP0_1" bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0" "CKP0_0,CKP0_1" line.long 0x08 "QSPI_SPI_CMD_REG,This register sets up the SPI command" bitfld.long 0x08 28.--29. "CSNUM,Device select" "Chip Select 0 active,Chip Select 1 active,Chip Select 2 active,Chip Select 3 active" abitfld.long 0x08 19.--25. "WLEN,Word length" "0x00=1 bit,0x01=2 bits,0x7F=128 bits" newline bitfld.long 0x08 16.--18. "CMD,Transfer command" "Reserved,4-pin Read Single,4-pin Write Single,4-pin Read Dual,Reserved,3-pin Read Single,3-pin Write Single,6-pin Read Quad" bitfld.long 0x08 15. "FIRQ,Frame complete interrupt enable" "FIRQ_0,FIRQ_1" newline bitfld.long 0x08 14. "WIRQ,Word complete interrupt enable - WORD_COUNT_IRQ_DISABLE" "WIRQ_0,WIRQ_1" abitfld.long 0x08 0.--11. "FLEN,Frame Length" "0x000=1 word,0x001=2 words,0xFFF=4096 words" line.long 0x0C "QSPI_SPI_STATUS_REG,This register contains indicators to allow the user to monitor the progression of a frame transfer" hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count" bitfld.long 0x0C 2. "FC,Frame complete" "FC_0,FC_1" newline bitfld.long 0x0C 1. "WC,Word complete" "WC_0,WC_1" bitfld.long 0x0C 0. "BUSY,Busy bit" "BUSY_0,BUSY_1" line.long 0x10 "QSPI_SPI_DATA_REG,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x14 "QSPI_SPI_SETUP0_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 0 output)" bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write command" newline bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command" line.long 0x18 "QSPI_SPI_SETUP1_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 1 output)" bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write command" newline bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command" line.long 0x1C "QSPI_SPI_SETUP2_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 2 output)" bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write command" newline bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command" line.long 0x20 "QSPI_SPI_SETUP3_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 3 output)" bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write command" newline bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "Normal read (all data input on qspi1_d[1]),Dual read (odd bytes input on qspi1_d[1]; even..,Normal read (all data input on qspi1_d[1]),Quad read (uses also qspi1_d[2] and qspi1_d[3])" bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "No dummy bytes required,Use 8 bits,Use 16 bits,Use 24 bits" newline bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command" line.long 0x24 "QSPI_SPI_SWITCH_REG,This register allows initiators to switch control of the SPI core port between the configuration port and the SFI translator" bitfld.long 0x24 1. "MM_INT_EN,Memory mapped mode interrupt enable" "MM_INT_EN_0,MM_INT_EN_1" bitfld.long 0x24 0. "MMPT_S,MPT select" "MMPT_S_0,MMPT_S_1" line.long 0x28 "QSPI_SPI_DATA_REG_1,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x2C "QSPI_SPI_DATA_REG_2,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x30 "QSPI_SPI_DATA_REG_3,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" width 0x0B tree.end tree "RTC" base ad:0x48838000 group.long 0x00++0x1B line.long 0x00 "RTC_SECONDS_REG,Used to program the required seconds value of the current time" bitfld.long 0x00 4.--6. "SEC1,Second digit of seconds" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "SEC0,First digit of seconds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTC_MINUTES_REG,Used to program the required minutes value of the current time" bitfld.long 0x04 4.--6. "MIN1,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--3. "MIN0,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RTC_HOURS_REG,Used to program the hours value of the current time" bitfld.long 0x08 7. "PM_NAM,Only used in PM_AM mode (otherwise 0)" "AM,PM" newline bitfld.long 0x08 4.--5. "HOUR1,Second digit of hours Range is 0 to 2" "0,1,2,3" newline bitfld.long 0x08 0.--3. "HOUR0,First digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RTC_DAYS_REG,Used to program the day of the month value of the current date" bitfld.long 0x0C 4.--5. "DAY1,Second digit of days Range from 0 to 3" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "DAY0,First digit of days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "RTC_MONTHS_REG,MONTHS_REG is used to set the month in the year value of the current date" bitfld.long 0x10 4. "MONTH1,Second digit of months Range from 0 to 1" "0,1" newline bitfld.long 0x10 0.--3. "MONTH0,First digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "RTC_YEARS_REG,YEARS_REG is used to program the year value of the current date" bitfld.long 0x14 4.--7. "YEAR1,Second digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "YEAR0,First digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "RTC_WEEKS_REG,WEEKS_REG is used to program the day of the week value of the current date" bitfld.long 0x18 0.--2. "WEEK,First digit of Days in a week Range from 0 (Sunday) to 6 (Saturday)" "0,1,2,3,4,5,6,7" group.long 0x20++0x17 line.long 0x00 "RTC_ALARM_SECONDS_REG,ALARM_SECONDS_REG is used to program the seconds value for the alarm interrupt" bitfld.long 0x00 4.--6. "ALARM_SEC1,Second digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "ALARM_SEC0,First digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTC_ALARM_MINUTES_REG,ALARM_MINUTES_REG is used to program the minute value for the alarm interrupt" bitfld.long 0x04 4.--6. "ALARM_MIN1,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--3. "ALARM_MIN0,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RTC_ALARM_HOURS_REG,ALARM_HOURS_REG is used to program the hour value for the alarm interrupt" bitfld.long 0x08 7. "ALARM_PM_NAM,Only used in PM_AM mode (otherwise 0)" "AM,PM" newline bitfld.long 0x08 4.--5. "ALARM_HOUR1,Second digit of hours" "0,1,2,3" newline bitfld.long 0x08 0.--3. "ALARM_HOUR0,First digit of hours" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RTC_ALARM_DAYS_REG,ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt" bitfld.long 0x0C 4.--5. "ALARM_DAY1,Second digit for days" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "ALARM_DAY0,First digit for days" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "RTC_ALARM_MONTHS_REG,ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt" bitfld.long 0x10 4. "ALARM_MONTH1,Second digit of months" "0,1" newline bitfld.long 0x10 0.--3. "ALARM_MONTH0,First digit of months" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "RTC_ALARM_YEARS_REG,ALARM_YEARS_REG is used to program the year for the alarm interrupt" bitfld.long 0x14 4.--7. "ALARM_YEAR1,Second digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "ALARM_YEAR0,First digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x17 line.long 0x00 "RTC_CTRL_REG,CTRL_REG contains the controls to enable/disable RTC" bitfld.long 0x00 6. "RTC_DISABLE," "0,1" newline bitfld.long 0x00 5. "SET_32_COUNTER," "0,1" newline bitfld.long 0x00 4. "TEST_MODE," "0,1" newline bitfld.long 0x00 3. "MODE_12_24," "0,1" newline bitfld.long 0x00 2. "AUTO_COMP," "0,1" newline bitfld.long 0x00 1. "ROUND_30S," "0,1" newline bitfld.long 0x00 0. "STOP_RTC," "0,1" line.long 0x04 "RTC_STATUS_REG,RTC STATUS_REG contains bits that signal the status of interrupts. events to the processor" bitfld.long 0x04 7. "ALARM2,Indicates that an alarm2 interrupt has been generated" "0,1" newline bitfld.long 0x04 6. "ALARM,Indicates that an alarm interrupt has been generated" "0,1" newline rbitfld.long 0x04 5. "EVENT_1D,One day has occurred" "0,1" newline rbitfld.long 0x04 4. "EVENT_1H,One hour has occurred" "0,1" newline rbitfld.long 0x04 3. "EVENT_1M,One minute has occurred" "0,1" newline rbitfld.long 0x04 2. "EVENT_1S,One second has occurred" "0,1" newline rbitfld.long 0x04 1. "RUN," "0,1" newline rbitfld.long 0x04 0. "BUSY," "0,1" line.long 0x08 "RTC_INTERRUPTS_REG,INTERRUPTS_REG is used to enable or disable RTC from generating interrupts" bitfld.long 0x08 4. "IT_ALARM2,Enable one interrupt when the alarm value is reached (TC ALARM2 registers) by the TC registers" "0,1" newline bitfld.long 0x08 3. "IT_ALARM,Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers" "0,1" newline bitfld.long 0x08 2. "IT_TIMER,Enable periodic interrupt" "interrupt disabled,interrupt enabled" newline bitfld.long 0x08 0.--1. "EVERY,Interrupt period" "every second,every minute,every hour,every day" line.long 0x0C "RTC_COMP_LSB_REG,COMP_LSB_REG is used to program the LSB value of the 32-kHz periods to be added to the 32-kHz counter every hour" hexmask.long.byte 0x0C 0.--7. 1. "RTC_COMP_LSB,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" line.long 0x10 "RTC_COMP_MSB_REG,COMP_MSB_REG is used to program the MSB value of the 32-kHz periods to be added to the 32-kHz counter every hour" hexmask.long.byte 0x10 0.--7. 1. "RTC_COMP_MSB,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" line.long 0x14 "RTC_OSC_REG,OSC_REG is used to program the oscillator resistance value. and to select and enable the clock source" bitfld.long 0x14 6. "K32CLK_EN,32-kHz clock enable post clock mux of RTC_32K_AUX_CLK and RTC_32K_CLK" "0,1" newline bitfld.long 0x14 4. "OSC32K_GZ,Disable the oscillator and applies high impedance to the output" "Enable,Disabled and.." newline bitfld.long 0x14 3. "K32CLK_SEL,32-kHz clock source select" "Selects internal clock source namely..,Selects external clock source namely RTC_32K_CLK.." newline bitfld.long 0x14 2. "RES_SELECT,External feedback resistor selection" "Internal,External" newline bitfld.long 0x14 1. "SW2,Inverter size adjustment" "0,1" newline bitfld.long 0x14 0. "SW1,Inverter size adjustment" "0,1" group.long 0x60++0x3F line.long 0x00 "RTC_SCRATCH0_REG,Used to hold some required values for the RTC register" line.long 0x04 "RTC_SCRATCH1_REG,Used to hold some required values for the RTC register" line.long 0x08 "RTC_SCRATCH2_REG,Used to hold some required values for the RTC register" line.long 0x0C "RTC_KICK0_REG,The KICK0 register allows writing to unlock the kick0 data" line.long 0x10 "RTC_KICK1_REG,Kick1 data" line.long 0x14 "RTC_REVISION_REG," line.long 0x18 "RTC_SYSCONFIG_REG," bitfld.long 0x18 0.--1. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x1C "RTC_IRQWAKEEN," bitfld.long 0x1C 1. "ALARM_WAKEEN,Wakeup generation for event Alarm" "Wakeup disabled,Wakeup enable" newline bitfld.long 0x1C 0. "TIMMER_WAKEEN,Wakeup generation for event Timer" "Wakeup disabled,Wakeup enable Timer wakeup should not get.." line.long 0x20 "RTC_ALARM2_SECONDS_REG,ALARM2_SECONDS_REG is used to program the seconds value of the ALARM2 time" bitfld.long 0x20 4.--6. "ALARM2_SEC1,Second digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--3. "ALARM2_SEC0,First digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x24 "RTC_ALARM2_MINUTES_REG," bitfld.long 0x24 4.--6. "ALARM2_MIN1,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--3. "ALARM2_MIN0,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "RTC_ALARM2_HOURS_REG," bitfld.long 0x28 7. "ALARM2_PM_NAM,Only used in PM_AM mode (otherwise 0)" "AM,PM" newline bitfld.long 0x28 4.--5. "ALARM2_HOUR1,Second digit of hours Range is 0 to 2" "0,1,2,3" newline bitfld.long 0x28 0.--3. "ALARM2_HOUR0,First digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "RTC_ALARM2_DAYS_REG," bitfld.long 0x2C 4.--5. "ALARM_DAY1,Second digit for days Range from 0 to 3" "0,1,2,3" newline bitfld.long 0x2C 0.--3. "ALARM_DAY0,First digit for days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "RTC_ALARM2_MONTHS_REG," bitfld.long 0x30 4. "ALARM2_MONTH1,Second digit of months Range from 0 to 1" "0,1" newline bitfld.long 0x30 0.--3. "ALARM2_MONTH0,First digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x34 "RTC_ALARM2_YEARS_REG," bitfld.long 0x34 4.--7. "ALARM2_YEAR1,Second digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34 0.--3. "ALARM2_YEAR0,First digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x38 "RTC_PMIC_REG," bitfld.long 0x38 19.--22. "EXT_WAKEUP_POL_HL,External wakeup inputs polarity enable for Active High and Active Low" "Disabled,Enabled Active High..,?..." newline bitfld.long 0x38 17.--18. "PWR_ENABLE_SM,Power State Machine state" "Idle/Default,Shutdown (ALARM2 and pwr_enable enable is set..,Time based wakeup (ALARM status is set),External event based wakeup (one or more bit set.." newline bitfld.long 0x38 16. "PWR_ENABLE_EN,pwr_enable enable" "Disable When Disabled PMIC_PWR_ENABLE will..,Enable When enabled" newline bitfld.long 0x38 12.--15. "EXT_WAKEUP_STATUS,External wakeup status" "External wakeup event has not occurred,External wakeup event has occurred Wrt 1 to..,?..." newline bitfld.long 0x38 8.--11. "EXT_WAKEUP_DB_EN,External wakeup debounce enabled" "Disable,Enable..,?..." newline bitfld.long 0x38 4.--7. "EXT_WAKEUP_POL,External wakeup inputs polarity" "Active High,Active Low EXT_WAKEUP_POL[0]..,?..." newline bitfld.long 0x38 0.--3. "EXT_WAKEUP_EN,Enable External wakeup inputs" "Ext Wakeup disabled,Ext Wakeup enable EXT_WAKEUP_EN[0] controls..,?..." line.long 0x3C "RTC_RTL_DEBOUNCE_REG," hexmask.long.byte 0x3C 0.--7. 1. "DEBOUNCE_REG,Debounce time see for details" width 0x0B tree.end tree "SATA_Controller" tree "DWC_ahsata" base ad:0x4A140000 group.long 0x00++0x1B line.long 0x00 "SATA_CAP,Capabilities register: Basic capabilities of the SATA AHCI core" rbitfld.long 0x00 31. "S64A,Supports 64-bit addressing - 64bit" "S64A_0_r,S64A_1_r" rbitfld.long 0x00 30. "SNCQ,Supports NCQ (Native Command Queuing) Controller supports SATA NCQ by handling DMA setup FIS natively" "SNCQ_0_r,SNCQ_1_r" rbitfld.long 0x00 29. "SSNTF,Supports SNotification register Controller supports SATA_PxSNTF (SNotification) register and its associated functionality" "SSNTF_0_r,SSNTF_1_r" newline bitfld.long 0x00 28. "SMPS,Supports mechanical presence switch Support of a mechanical presence switch for hot plug operation depending on integration Writable once after power up read-only afterward - NO" "SMPS_0,SMPS_1" bitfld.long 0x00 27. "SSS,Supports staggered spin-up Controller can support this feature through SATA_PxCMD.SUD Writable once after power up read-only afterward - NO" "SSS_0,SSS_1" rbitfld.long 0x00 26. "SALP,Supports aggressive link power management - YES" "SALP_0_r,SALP_1_r" newline rbitfld.long 0x00 25. "SAL,Supports Activity LED - YES" "SAL_0_r,SAL_1_r" rbitfld.long 0x00 24. "SCLO,Supports command list override Supports the SATA_PxCMD.CLO bit functionality for enumeration of PM devices - YES" "SCLO_0_r,SCLO_1_r" rbitfld.long 0x00 20.--23. "ISS,Interface speed support Maximum speed the HBA can support - 6G" "?,ISS_1_r,ISS_2_r,ISS_3_r,?,?,?,?,?,?,?,?,?,?,?,?" newline rbitfld.long 0x00 19. "SNZO,Supports Non-zero DMA offsets - YES" "SNZO_0_r,SNZO_1_r" rbitfld.long 0x00 18. "SAM,Supports AHCI mode only SATA controller supports AHCI mode only and does not support legacy task file-based register interface" "SAM_0_r,SAM_1_r" rbitfld.long 0x00 17. "SPM,Supports PM (Port Multiplier) SATA controller supports command-based switching PM on any port" "SPM_0_r,SPM_1_r" newline rbitfld.long 0x00 16. "FBSS,FIS-based switching supported Support of PM FIS-based switching" "FBSS_0_r,FBSS_1_r" rbitfld.long 0x00 15. "PMD,PIO Multiple DRQ Support of multiple DRQ block data transfers for the PIO command protocol - YES" "PMD_0_r,PMD_1_r" rbitfld.long 0x00 14. "SSC,SLUMBER state capable Support of transitions to the interface SLUMBER power management state - YES" "SSC_0_r,SSC_1_r" newline rbitfld.long 0x00 13. "PSC,PARTIAL state capable Support of transitions to the interface PARTIAL power management state - YES" "PSC_0_r,PSC_1_r" rbitfld.long 0x00 8.--12. "NCS,Number of command slots: slots supported by the SATA controller minus" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NCS_31_r" rbitfld.long 0x00 7. "CCCS,Command completion coalescing supported - YES" "CCCS_0_r,CCCS_1_r" newline rbitfld.long 0x00 6. "EMS,Enclosure management supported - YES" "EMS_0_r,EMS_1_r" rbitfld.long 0x00 5. "SXS,Supports external SATA - YES" "SXS_0_r,SXS_1_r" rbitfld.long 0x00 0.--4. "NP,Number of ports: ports supported by the SATA controller minus" "NP_0_r,NP_1_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "SATA_GHC,Global HBA control" rbitfld.long 0x04 31. "AE,AHCI enable Always set because SATA controller supports AHCI mode only as indicated by the SATA_CAP.SAM = 1" "0,1" bitfld.long 0x04 1. "IE,Interrupt enable Global enable of SATA controller interrupts" "IE_0,IE_1" bitfld.long 0x04 0. "HR,HBA reset Global reset control - noaction" "HR_0_r,HR_1_r" line.long 0x08 "SATA_IS,Interrupt status Indicates which port has a pending interrupt" bitfld.long 0x08 0. "IPS,Interrupt pending status" "0,1" line.long 0x0C "SATA_PI,Ports implemented Indicates which ports are exposed by the SATA controller and available for use" bitfld.long 0x0C 0. "PI,Ports implemented" "0,1" line.long 0x10 "SATA_VS,AHCI version supported: 1.3 WARNING: Controller complies fully with AHCI version 1.10 and also complies with AHCI version 1.3 except for FIS-based switching. which is not currently supported" hexmask.long.word 0x10 16.--31. 1. "MJR,Major Version Number: 1" hexmask.long.word 0x10 0.--15. 1. "MNR,Minor Version Number: 3.00" line.long 0x14 "SATA_CCC_CTL,CCC (Command Completion Coalescing) control Used to configure the CCC feature for the SATA controller Reset on global reset" abitfld.long 0x14 16.--31. "TV,Time-out value" "0x0001=no,0xFFFF=timeout slectable between.." abitfld.long 0x14 8.--15. "CC,Command completions Number of command completions necessary to cause a CCC interrupt Loaded prior to enabling CCC becomes read-only when SATA_CCC_CTL.EN =" "0x01=nocount,0xFF=specifies the number of commands upon.." rbitfld.long 0x14 3.--7. "INT,Interrupt Number of the interrupt used by the CCC feature using the number of ports configured for the core When a CCC interrupt occurs the SATA_IS.IPS[INT] bit is set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0. "EN,Enable CCC enable - dis" "EN_0,EN_1" line.long 0x18 "SATA_CCC_PORTS,CCC ports Specifies the ports that are coalesced as part of the CCC feature when .EN = 1 Reset on global reset" bitfld.long 0x18 0. "PRT,Ports Bit-significant field Set a bit to 1 to make the corresponding port part of the CCC feature" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SATA_CAP2,Extended capabilities" bitfld.long 0x00 2. "APST,Automatic PARTIAL to SLUMBER transitions - YES" "APST_0_r,APST_1_r" bitfld.long 0x00 1. "NVMP,NVMHCI present - YES" "NVMP_0_r,NVMP_1_r" bitfld.long 0x00 0. "BOH,BIOS/OS Handoff - YES" "BOH_0_r,BOH_1_r" rgroup.long 0xA0++0x13 line.long 0x00 "SATA_BISTAFR,Built-In. Self-Test (BIST) Activate FIS Register Reset on global reset or port reset" hexmask.long.byte 0x00 8.--15. 1. "NCP,Noncompliant pattern Least significant byte of the received BIST Activate FIS second DWORD (bits [7:0])" hexmask.long.byte 0x00 0.--7. 1. "PD,Pattern definition Pattern definition field of the received BIST Activate FIS - bits [23:16] of the first DWORD" line.long 0x04 "SATA_BISTCR,BIST control register Reset on global reset or port reset" bitfld.long 0x04 20. "FERLB,Far-end retimed loopback - noaction" "FERLB_0_r,FERLB_1_w" bitfld.long 0x04 18. "TXO,Transmit only - noaction" "TXO_0,TXO_1" bitfld.long 0x04 17. "CNTCLR,Counter clear Clears BIST error count registers - noaction" "CNTCLR_0_r,CNTCLR_1_w" newline bitfld.long 0x04 16. "NEALB,Near-end analog loopback This mode should be initiated in the PARTIAL or SLUMBER power state or with the device disconnected from the port PHY (link NOCOMM state)" "NEALB_0_w,NEALB_1_w" bitfld.long 0x04 15. "LLB,Lab Loopback Mode Masks out phy_sig_det from the OOB detector in BIST Loopback Mode" "0,1" bitfld.long 0x04 13. "ERRLOSSEN,Always keep this bit at default value" "0,1" newline bitfld.long 0x04 12. "SDFE,Signal detect feature enable Not affected by global reset or port reset - dis" "SDFE_0,SDFE_1" bitfld.long 0x04 10. "LLC_RPD,Link layer control repeat primitive drop In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_RPD_0,LLC_RPD_1" bitfld.long 0x04 9. "LLC_DESCRAM,Link layer control descrambler In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_DESCRAM_0,LLC_DESCRAM_1" newline bitfld.long 0x04 8. "LLC_SCRAM,Link layer control scrambler In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_SCRAM_0,LLC_SCRAM_1" bitfld.long 0x04 6. "ERREN,Error enable Allow or filter (disable) PHY internal errors outside the FIS boundary to set corresponding SATA_PxSERR bits - filter" "ERREN_0,ERREN_1" bitfld.long 0x04 5. "FLIP,Flip disparity Change disparity of the current test pattern to the opposite each time its state is changed by software" "0,1" newline bitfld.long 0x04 4. "PV,Pattern version Selects either short or long version of the SSOP HTDP LTDP LFSCP COMP pattern - short" "PV_0,PV_1" bitfld.long 0x04 0.--3. "PATTERN,Pattern Defines one of the listed SATA-compliant patterns for far-end retimed/ far-end analog/ near-end analog initiator modes or noncompliant patterns for transmit-only responder mode when initiated by software writing to the SATA_BISTCR.TXO.." "PATTERN_0,PATTERN_1,PATTERN_2,PATTERN_3,PATTERN_4,PATTERN_5,PATTERN_6,PATTERN_7,PATTERN_8,?,?,?,?,?,?,?" line.long 0x08 "SATA_BISTFCTR,BIST frame-information-structure CounT register Received BIST FIS count in the loopback initiator far-end retimed. far-end analog. and near-end analog modes" line.long 0x0C "SATA_BISTSR,BIST status register Errors detected in the received BIST FIS in the loopback initiator far-end retimed. far-end analog. and near-end analog modes Updated each time a new BIST FIS is received Reset on global reset. port reset (COMRESET). or.." hexmask.long.byte 0x0C 16.--23. 1. "BRSTERR,Burst error count" hexmask.long.word 0x0C 0.--15. 1. "FRAMERR,Frame error count" line.long 0x10 "SATA_BISTDECR,BIST double-word error count register Number of DWORD errors detected in the received BIST frame in the loopback initiator far-end retimed. far-end analog. and near-end analog modes Updated each time a new BIST frame is received. when the.." group.long 0xBC++0x03 line.long 0x00 "SATA_OOBR,OOB (Out Of Band Register) register Controls the link layer OOB detection counters" bitfld.long 0x00 31. "WE,WRITE_ENABLE - no" "WE_0,WE_1" hexmask.long.byte 0x00 24.--30. 1. "CWMIN,COMWAKE_MIN in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" hexmask.long.byte 0x00 16.--23. 1. "CWMAX,COMWAKE_MAX in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" newline hexmask.long.byte 0x00 8.--15. 1. "CIMIN,COMINIT_MIN in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" hexmask.long.byte 0x00 0.--7. 1. "CIMAX,COMINIT_MAX in OOB rx clock cycles Read-only when SATA_OOBR.WE=0" group.long 0xE0++0x03 line.long 0x00 "SATA_TIMER1MS,Timer 1 ms Configuration to generate the 1-ms tick for the CCC logic Must be initialized before using the CCC feature Reset on power up. not affected by global reset" hexmask.long.tbyte 0x00 0.--19. 1. "TIMV,OCP bus clock frequency in kHz (for example reset value is 100 000 = 100 MHz)" rgroup.long 0xE8++0x33 line.long 0x00 "SATA_GPARAM1R,Global parameters register 1 Hardware configuration of the DWC AHCI SATA core" bitfld.long 0x00 31. "ALIGN_M,RX data alignment - yes" "ALIGN_M_0_r,ALIGN_M_1_r" bitfld.long 0x00 30. "RX_BUFFER,RX data buffer implemented - yes" "RX_BUFFER_0_r,RX_BUFFER_1_r" bitfld.long 0x00 28.--29. "PHY_DATA,PHY data width (in 8- or 10-bit" "PHY_DATA_0_r,PHY_DATA_1_r,PHY_DATA_2_r,?" newline bitfld.long 0x00 27. "PHY_RST,PHY reset mode - hi" "PHY_RST_0_r,PHY_RST_1_r" bitfld.long 0x00 21.--26. "PHY_CTRL,PHY control width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--20. "PHY_STAT,PHY status width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 14. "LATCH_M,Test mode lock-up latches - yes" "LATCH_M_0_r,LATCH_M_1_r" bitfld.long 0x00 13. "BIST_M,BIST loopback checking" "BIST_M_0_r,BIST_M_1_r" bitfld.long 0x00 11.--12. "PHY_TYPE,PHY interface type - snps" "PHY_TYPE_0_r,PHY_TYPE_1_r,?,?" newline bitfld.long 0x00 10. "RETURN_ERR,Error response on illegal access - yes" "RETURN_ERR_0_r,RETURN_ERR_1_r" bitfld.long 0x00 8.--9. "AHB_ENDIAN,Endianness of master and slave - conf" "AHB_ENDIAN_0_r,AHB_ENDIAN_1_r,AHB_ENDIAN_2_r,?" bitfld.long 0x00 7. "S_HADDR,Slave address bus width - 64bit" "S_HADDR_0_r,S_HADDR_1_r" newline bitfld.long 0x00 6. "M_HADDR,Master address bus width - 64bit" "M_HADDR_0_r,M_HADDR_1_r" bitfld.long 0x00 3.--5. "S_HDATA,Slave Data Bus Width" "S_HDATA_0_r,S_HDATA_1_r,S_HDATA_2_r,S_HDATA_3_r,?,?,?,?" bitfld.long 0x00 0.--2. "M_HDATA,Master Data Bus Width" "M_HDATA_0_r,M_HDATA_1_r,M_HDATA_2_r,M_HDATA_3_r,?,?,?,?" line.long 0x04 "SATA_GPARAM2R,Global parameters register 2 Hardware configuration of the DWC AHCI SATA core. continued" bitfld.long 0x04 14. "DEV_CP,Cold presence detection implemented in core - yes" "DEV_CP_0_r,DEV_CP_1_r" bitfld.long 0x04 13. "DEV_MP,Mechanical presence switch implemented in core - yes" "DEV_MP_0_r,DEV_MP_1_r" bitfld.long 0x04 12. "ENCODE_M,8b/10b Encoding/decoding implemented in core - yes" "ENCODE_M_0_r,ENCODE_M_1_r" newline bitfld.long 0x04 11. "RXOOB_CLK_M,RX OOB clocking mode: - sep" "RXOOB_CLK_M_0_r,RXOOB_CLK_M_1_r" bitfld.long 0x04 10. "RX_OOB_M,RX OOB mode: sequence generation implemented - yes" "RX_OOB_M_0_r,RX_OOB_M_1_r" bitfld.long 0x04 9. "TX_OOB_M,TX OOB mode: sequence generation implemented - yes" "TX_OOB_M_0_r,TX_OOB_M_1_r" newline hexmask.long.word 0x04 0.--8. 1. "RXOOB_CLK,RX OOB clock frequency in MHz" line.long 0x08 "SATA_PPARAMR,Port parameter register Hardware configuration of the DWC AHCI SATA core port selected by .PSEL" bitfld.long 0x08 11. "TX_MEM_M,TX FIFO memory mode: - sync" "TX_MEM_M_0_r,TX_MEM_M_1_r" bitfld.long 0x08 10. "TX_MEM_S,TX FIFO memory selection: - int" "TX_MEM_S_0_r,TX_MEM_S_1_r" bitfld.long 0x08 9. "RX_MEM_M,RX FIFO memory mode: - sync" "RX_MEM_M_0_r,RX_MEM_M_1_r" newline bitfld.long 0x08 8. "RX_MEM_S,RX FIFO memory selection: - int" "RX_MEM_S_0_r,RX_MEM_S_1_r" bitfld.long 0x08 4.--7. "TXFIFO_DEPTH,Tx FIFO Depth in dwords (log2) - 3" "?,?,?,TXFIFO_DEPTH_3_r,TXFIFO_DEPTH_4_r,TXFIFO_DEPTH_5_r,TXFIFO_DEPTH_6_r,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 0.--3. "RXFIFO_DEPTH,Rx FIFO Depth in dwords (log2) - 3" "?,?,?,?,RXFIFO_DEPTH_4_r,RXFIFO_DEPTH_5_r,RXFIFO_DEPTH_6_r,RXFIFO_DEPTH_7_r,?,?,?,?,?,?,?,?" line.long 0x0C "SATA_TESTR,Test register Puts the SATA controller slave interface in a test mode and selects a port for BIST operation" bitfld.long 0x0C 16.--18. "PSEL,Port select: Selects the port for BIST operation - 0" "PSEL_0,?,?,?,?,?,?,?" bitfld.long 0x0C 0. "TEST_IF,Test interface - default" "TEST_IF_0,TEST_IF_1" line.long 0x10 "SATA_VERSIONR,Version register" line.long 0x14 "SATA_IDR,ID register. containing the 32-bit Highlander (HL) revision" line.long 0x18 "SATA_PxCLB,Port command List base address 32-bit base physical address for the command list for this port" hexmask.long.tbyte 0x18 10.--31. 1. "CLB,Command list base address (bits 31:10)" hexmask.long.word 0x18 0.--9. 1. "ZERO,Always 0 as address is 1 KiB-aligned" line.long 0x1C "SATA_PxCLBU,Port Command List Base Upper address Upper half of the 64-bit base physical address for the command list for this Port" line.long 0x20 "SATA_PxFB,Port Frame-information-structure Base address 32-bit base physical address for received FISes for this port" hexmask.long.tbyte 0x20 8.--31. 1. "FB,FIS base address (bits 31:8)" hexmask.long.byte 0x20 0.--7. 1. "ZERO,Always 0 as address is 256-bytes aligned" line.long 0x24 "SATA_PxFBU,FIS Base Upper Address Upper half of the 64-bit base physical address for received FISes for this port" line.long 0x28 "SATA_PxIS,Port interrupt status Bits are set by internal conditions and cleared (when possible) by writing 1 to them" bitfld.long 0x28 31. "CPDS,Cold port detect status Set when the pX_cp_det input changes its state due to the insertion or removal of a device Valid only if the port supports cold presence detection as indicated by the SATA_PxCMD.CPD bit set to 1" "CPDS_0_r,CPDS_1_r" bitfld.long 0x28 30. "TFES,Task file error status Set whenever the SATA_PxTFD.STS register is updated by the device and the error bit (bit 0) is set" "TFES_0_r,TFES_1_r" bitfld.long 0x28 29. "HBFS,Host bus fatal error status Set when master (DMA) detects an ERROR response from the slave - noaction" "HBFS_0_r,HBFS_1_r" newline bitfld.long 0x28 28. "HBDS,Host bus data error status This bit is always cleared to 0" "HBDS_0_r,HBDS_1_r" bitfld.long 0x28 27. "IFS,Interface fatal error status This bit is set when any of the following conditions is detected: 1) SYNC escape is received from the device during H2D register or data FIS transmission. 2) One or more of the following errors are detected during data.." "IFS_0_r,IFS_1_r" bitfld.long 0x28 26. "INFS,Interface nonfatal error status Set when any of the following conditions is detected: 1) One or more of the following errors are detected during nondata FIS transfer: - 10b to 8b decode error (SATA_PxSERR.DIAG_B) - Protocol (SATA_PxSERR.ERR_P) -.." "INFS_0_r,INFS_1_r" newline bitfld.long 0x28 24. "OFS,Overflow status Set when command list overflow is detected during read or write operation when the software builds command table that has fever total bytes than the transaction given to the device" "OFS_0_r,OFS_1_r" bitfld.long 0x28 23. "IPMS,Incorrect PM status FIS received from a device in which the PM field did not match what was expected May be set during enumeration of devices on a PM due to the normal PM enumeration process Must be used only after enumeration is complete on the PM.." "IPMS_0_r,IPMS_1_r" rbitfld.long 0x28 22. "PRCS,PhyRdy change status Reflects the state of SATA_PxSERR.DIAG_N To clear this bit clear the SATA_PxSERR.DIAG_N bit to 0" "PRCS_0_r,PRCS_1_r" newline bitfld.long 0x28 7. "DMPS,Device mechanical presence status Set when the pX_mp_switch input changes its state as a result of a mechanical switch attached to this port opening or closing Valid only when SATA_CAP.SMPS and SATA_PxCMD.MPSP are set - noaction" "DMPS_0_r,DMPS_1_r" rbitfld.long 0x28 6. "PCS,Port connect change status This bit reflects the state of the SATA_PxSERR.DIAG_X bit" "PCS_0_r,PCS_1_r" bitfld.long 0x28 5. "DPS,Descriptor processed A PRD with the I bit set has transferred all of its data" "DPS_0_r,DPS_1_r" newline rbitfld.long 0x28 4. "UFS,Unknown FIS interrupt An unknown FIS was received and has been copied into system memory" "UFS_0_r,UFS_1_r" bitfld.long 0x28 3. "SDBS,Set device bits interrupt A Set Device Bits FIS is received with the I bit set and copied into system memory" "SDBS_0_r,SDBS_1_r" bitfld.long 0x28 2. "DSS,DMA setup FIS interrupt A DMA Setup FIS is received with the I bit set and copied into system memory" "DSS_0_r,DSS_1_r" newline bitfld.long 0x28 1. "PSS,PIO setup FIS interrupt A PIO Setup FIS is received with the I bit set copied into system memory and the data related to the FIS is transferred" "PSS_0_r,PSS_1_r" bitfld.long 0x28 0. "DHRS,Device to host register FIS interrupt A D2H register FIS is received with the I bit set and copied into system memory" "DHRS_0_r,DHRS_1_r" line.long 0x2C "SATA_PxIE,Port interrupt enable Enables and disables the reporting of the corresponding interrupt to system software When a bit is set (1). .IE = 1. and the corresponding interrupt condition in is active. then the SATA controller interrupt output is.." bitfld.long 0x2C 31. "CPDE,Cold port detect enable - dis" "CPDE_0,CPDE_1" bitfld.long 0x2C 30. "TFEE,Task file error enable - dis" "TFEE_0,TFEE_1" bitfld.long 0x2C 29. "HBFE,Host bus fatal error enable - dis" "HBFE_0,HBFE_1" newline bitfld.long 0x2C 28. "HBDE,Host bus data error enable - dis" "HBDE_0,HBDE_1" bitfld.long 0x2C 27. "IFE,Interface fatal error enable - dis" "IFE_0,IFE_1" bitfld.long 0x2C 26. "INFE,Interface non fatal error enable - dis" "INFE_0,INFE_1" newline bitfld.long 0x2C 24. "OFE,Overflow enable - dis" "OFE_0,OFE_1" bitfld.long 0x2C 23. "IPME,Incorrect PM enable - dis" "IPME_0,IPME_1" bitfld.long 0x2C 22. "PRCE,PhyRdy change enable - dis" "PRCE_0,PRCE_1" newline bitfld.long 0x2C 7. "DMPE,Device mechanical presence enable - dis" "DMPE_0,DMPE_1" bitfld.long 0x2C 6. "PCE,Port connect change enable - dis" "PCE_0,PCE_1" bitfld.long 0x2C 5. "DPE,Descriptor processed interrupt enable - dis" "DPE_0,DPE_1" newline bitfld.long 0x2C 4. "UFE,Unknown FIS interrupt enable - dis" "UFE_0,UFE_1" bitfld.long 0x2C 3. "SDBE,Set device bits interrupt enable - dis" "SDBE_0,SDBE_1" bitfld.long 0x2C 2. "DSE,DMA setup FIS interrupt enable - dis" "DSE_0,DSE_1" newline bitfld.long 0x2C 1. "PSE,PIO setup FIS interrupt enable - dis" "PSE_0,PSE_1" bitfld.long 0x2C 0. "DHRE,Device to host register FIS interrupt enable - dis" "DHRE_0,DHRE_1" line.long 0x30 "SATA_PxCMD,Port command" bitfld.long 0x30 28.--31. "ICC,Interface communication control Control of power management states of the interface If the link layer is in the L_IDLE state writes cause the port to request a transition to a given interface state" "ICC_0_r,ICC_1,ICC_2,?,?,?,ICC_6,?,?,?,?,?,?,?,?,?" bitfld.long 0x30 27. "ASP,Aggressive SLUMBER/PARTIAL - PARTIAL" "ASP_0,ASP_1" bitfld.long 0x30 26. "ALPE,Aggressive link power management enable - dis" "ALPE_0,ALPE_1" newline bitfld.long 0x30 25. "DLAE,Drive LED on ATAPI enable - dis" "DLAE_0,DLAE_1" bitfld.long 0x30 24. "ATAPI,Device is ATAPI Used by the port to determine whether or not to assert pX_act_led output when commands are active" "ATAPI_0,ATAPI_1" bitfld.long 0x30 23. "APSTE,Auto PARTIAL to SLUMBER transition enable - dis" "APSTE_0,APSTE_1" newline bitfld.long 0x30 22. "FBSCP,FIS-based Switching Capable Port May only be set to ?1? if CAP.SPM = CAP.FBSS = 1 (not the case)" "FBSCP_0,FBSCP_1" bitfld.long 0x30 21. "ESP,External SATA port Writable once after power up read-only afterward - int" "ESP_0,ESP_1" bitfld.long 0x30 20. "CPD,Cold presence detect Writable once after power up read-only afterward - no" "CPD_0,CPD_1" newline bitfld.long 0x30 19. "MPSP,Mechanical presence switch attached to port Writable once after power up read-only afterward - no" "MPSP_0,MPSP_1" bitfld.long 0x30 18. "HPCP,Hot plug capable port Writable once after power up read-only afterward - no" "HPCP_0,HPCP_1" bitfld.long 0x30 17. "PMA,PM attached Software is responsible for detecting the presence of a PM" "PMA_0,PMA_1" newline rbitfld.long 0x30 16. "CPS,Cold presence state Reports whether a device is currently detected on this port as indicated by the pX_cp_det input state (assuming SATA_PxCMD.CPD = 1)" "CPS_0_r,CPS_1_r" rbitfld.long 0x30 15. "CR,Command list running For details see the AHCI state-machine in Section 5.3.2 of the AHCI specification" "CR_0_r,CR_1_r" rbitfld.long 0x30 14. "FR,FIS receive running For details see Section 10.3.2 of the AHCI specification" "FR_0_r,FR_1_r" newline rbitfld.long 0x30 13. "MPSS,Mechanical presence switch state Reports the state of a mechanical presence switch attached to this port as indicated by the pX_mp_switch input state (assuming SATA_CAP.SMPS = 1 and SATA_PxCMD.MPSP = 1) Cleared to 0 when SATA_CAP.SMPS =" "MPSS_0_r,MPSS_1_r" rbitfld.long 0x30 8.--12. "CCS,Current command slot This field is valid when SATA_PxCMD.ST is set to 1 and is set to the command slot value of the command currently issued by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 4. "FRE,FIS receive enable Must not be set until SATA_PxFB / SATA_PxFBU is programmed with a valid pointer to the FIS receive area Base can be moved after clearing FRE and waiting for FR to clear to 0" "FRE_0,FRE_1" newline bitfld.long 0x30 3. "CLO,Command list override - noaction" "CLO_0_r,CLO_1_r" bitfld.long 0x30 2. "POD,Power-on device Writable if SATA_PxCMD.CPD = 1 (cold presence detection enabled) otherwise read-only -1" "POD_0,POD_1" bitfld.long 0x30 1. "SUD,Spin-up device Writable if SATA_CAP.SSS = 1 (staggered spin-up supported) else read-only 1" "SUD_0,SUD_1" newline bitfld.long 0x30 0. "ST,Start - newEnum1" "ST_0,ST_1" rgroup.long 0x120++0x1F line.long 0x00 "SATA_PxTFD,Port Task File Data: copies specific fields of the task file when FISes are received" hexmask.long.byte 0x00 8.--15. 1. "ERR,Err: Latest copy of the task file error register" bitfld.long 0x00 7. "STS_BSY,Status busy Latest copy of the 8-bit task file status register bit 7 STS_BSY = Interface is busy" "0,1" bitfld.long 0x00 4.--6. "STS_CS2,Status command-specific Latest copy of the 8-bit task file status register bits 6:4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "STS_DRQ,Status data request Latest copy of the 8-bit task file status register bit 3 STS_DRQ = Data transfer is requested" "0,1" bitfld.long 0x00 1.--2. "STS_CS,Status command-specific Latest copy of the 8-bit task file status register bits 2:1" "0,1,2,3" bitfld.long 0x00 0. "STS_ERR,Status error Latest copy of the 8-bit task file status register bit 0 STS_ERR = Error during the transfer" "0,1" line.long 0x04 "SATA_PxSIG,Port signature: Signature received from a device on the first D2H register FIS" hexmask.long.byte 0x04 24.--31. 1. "SIG_LBAH,Signature LBA high (cylinder high) register" hexmask.long.byte 0x04 16.--23. 1. "SIG_LBAM,Signature LBA mid (cylinder low) register" hexmask.long.byte 0x04 8.--15. 1. "SIG_LBAL,Signature LBA low (sector number) register" newline hexmask.long.byte 0x04 0.--7. 1. "SIG_SCR,Signature sector count register" line.long 0x08 "SATA_PxSSTS,Port SATA status Current state of the interface and host. updated continuously and asynchronously" bitfld.long 0x08 8.--11. "IPM,Interface power management: Current interface state - 2" "IPM_0_r,IPM_1_r,IPM_2_r,?,?,?,IPM_6_r,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "SPD,Current interface speed: Negotiated interface communication speed - 3" "SPD_0_r,SPD_1_r,SPD_2_r,SPD_3_r,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 0.--3. "DET,Device detection: Interface device detection and PHY state - 3" "DET_0_r,DET_1_r,?,DET_3_r,DET_4_r,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "SATA_PxSCTL,Port SATA control Control of SATA interface capabilities" rbitfld.long 0x0C 16.--19. "PMP,PM port: This field is not used by the AHCI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 12.--15. "SPM,Select power management: This field is not used by the AHCI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. "IPM,Interface power management transitions allowed: Indicates which power states the HBA is allowed to transition to" "IPM_0,IPM_1,IPM_2,IPM_3,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 4.--7. "SPD,Speed allowed: Highest allowable speed of the interface The two MSBs are always 2'b00 (not writable) as for all unreserved field values" "SPD_0,SPD_1,SPD_2,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x0C 0.--3. "DET,Device detection initialization: Controls the HBA device detection and interface initialization" "DET_0,DET_1,?,?,DET_4,?,?,?,?,?,?,?,?,?,?,?" line.long 0x10 "SATA_PxSERR,Port SATA error Detected interface errors accumulated since the last time it cleared" bitfld.long 0x10 26. "DIAG_X," "0,1" bitfld.long 0x10 25. "DIAG_F,Unknown FIS type: One or more FISes were received by the transport layer with good CRC but had a type field that was not recognized/known and the length was = 64 bytes" "0,1" bitfld.long 0x10 24. "DIAG_T,Transport state transition error: Transport Layer protocol violation detected" "0,1" newline bitfld.long 0x10 23. "DIAG_S,Link sequence error: One or more Link state machine error conditions encountered including device doing SYNC escape during FIS transmission" "0,1" bitfld.long 0x10 22. "DIAG_H,Handshake error: One or more R-ERRp received in response to frame transmission" "0,1" bitfld.long 0x10 21. "DIAG_C,CRC error: One ore more CRC errors detected by the link layer during FIS reception" "0,1" newline rbitfld.long 0x10 20. "DIAG_D,Disparity error: Not used by AHCI always 0" "0,1" bitfld.long 0x10 19. "DIAG_B,10bit-to-8bit decode error: Errors detected by the 10b8b decoder" "0,1" bitfld.long 0x10 18. "DIAG_W,Comm wake: Comm wake signal detected by the PHY" "0,1" newline bitfld.long 0x10 17. "DIAG_I,PHY internal error: Internal error detected by the PHY" "0,1" bitfld.long 0x10 16. "DIAG_N,PhyRdy" "0,1" bitfld.long 0x10 11. "ERR_E,Internal error: One or more errors detected on the master (DMA) or the slave (MMR access) interfaces" "0,1" newline bitfld.long 0x10 10. "ERR_P,Protocol error: Any of the following conditions: - Transport state transition error (DIAG_T) - Link sequence error (DIAG_S) - RxFIFO overflow - Link bad end error (WTRM instead of EOF received)" "0,1" bitfld.long 0x10 9. "ERR_C,Nonrecovered persistent communication error: PHY Ready signal is negated due to loss of communication with the device or problems with the interface but not after transition from ACTIVE to PARTIAL or SLUMBER power management state" "0,1" bitfld.long 0x10 8. "ERR_T,Nonrecovered transient data integrity error: Any of the following conditions are set during data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" newline bitfld.long 0x10 1. "ERR_M,Recovered communication error: PHY Ready condition is detected after interface initialization but not after transition from PARTIAL or SLUMBER power management state to ACTIVE state" "0,1" bitfld.long 0x10 0. "ERR_I,Recovered data integrity error: Any of the following conditions are set during non-data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" line.long 0x14 "SATA_PxSACT,Port SATA active (SActive): Indicates which command slots contain commands" line.long 0x18 "SATA_PxCI,Port command issue: Indicates that a command is constructed and may be carried out" line.long 0x1C "SATA_PxSNTF,Port SATA notification: Used to determine if asynchronous notification events have occurred for directly connected devices and devices connected to a PM" hexmask.long.word 0x1C 0.--15. 1. "PMN,PM notify: Indicates whether a particular device with the corresponding PM port number issued a set device bits FIS to the SATA controller Port with the notification bit set: - PM Port 0h sets bit 0" group.long 0x170++0x03 line.long 0x00 "SATA_PxDMACR,Port DMA control register" bitfld.long 0x00 4.--7. "RXTS,Receive transaction size: DMA transaction size for receive operations (system bus write device read)" "RXTS_0,RXTS_1,RXTS_2,RXTS_3,RXTS_4,RXTS_5,RXTS_6,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "TXTS,Transmit transaction size: DMA transaction size for transmit operations (system bus read device write)" "TXTS_0,TXTS_1,TXTS_2,TXTS_3,TXTS_4,TXTS_5,?,?,?,?,?,?,?,?,?,?" width 0x0B tree.end tree "SATAMAC_wrapper" base ad:0x4A141100 group.long 0x00++0x07 line.long 0x00 "SATA_SYSCONFIG,This register controls the idle and standby modes of Highlander 08 modules" bitfld.long 0x00 16. "OVERRIDE0,Override for clock stopping" "OVERRIDE0_0,OVERRIDE0_1" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator-state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x04 "SATA_CDRLOCK,Programmable delay for CDR lock indication" hexmask.long.word 0x04 0.--11. 1. "CDR_LOCK_DELAY,CDR lock delay in parallel (10-bit) serdes interface clock cycles" width 0x0B tree.end tree.end tree "Spinlock" base ad:0x4A0F6000 tree "REG_Bundle_0" group.long 0x800++0x3FF line.long 0x00 "SPINLOCK_LOCK_REG_i_0,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x04 "SPINLOCK_LOCK_REG_i_1,This register contains the state of one lock" bitfld.long 0x04 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x08 "SPINLOCK_LOCK_REG_i_2,This register contains the state of one lock" bitfld.long 0x08 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x0C "SPINLOCK_LOCK_REG_i_3,This register contains the state of one lock" bitfld.long 0x0C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x10 "SPINLOCK_LOCK_REG_i_4,This register contains the state of one lock" bitfld.long 0x10 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x14 "SPINLOCK_LOCK_REG_i_5,This register contains the state of one lock" bitfld.long 0x14 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x18 "SPINLOCK_LOCK_REG_i_6,This register contains the state of one lock" bitfld.long 0x18 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C "SPINLOCK_LOCK_REG_i_7,This register contains the state of one lock" bitfld.long 0x1C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x20 "SPINLOCK_LOCK_REG_i_8,This register contains the state of one lock" bitfld.long 0x20 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x24 "SPINLOCK_LOCK_REG_i_9,This register contains the state of one lock" bitfld.long 0x24 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x28 "SPINLOCK_LOCK_REG_i_10,This register contains the state of one lock" bitfld.long 0x28 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C "SPINLOCK_LOCK_REG_i_11,This register contains the state of one lock" bitfld.long 0x2C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x30 "SPINLOCK_LOCK_REG_i_12,This register contains the state of one lock" bitfld.long 0x30 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x34 "SPINLOCK_LOCK_REG_i_13,This register contains the state of one lock" bitfld.long 0x34 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x38 "SPINLOCK_LOCK_REG_i_14,This register contains the state of one lock" bitfld.long 0x38 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C "SPINLOCK_LOCK_REG_i_15,This register contains the state of one lock" bitfld.long 0x3C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x40 "SPINLOCK_LOCK_REG_i_16,This register contains the state of one lock" bitfld.long 0x40 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x44 "SPINLOCK_LOCK_REG_i_17,This register contains the state of one lock" bitfld.long 0x44 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x48 "SPINLOCK_LOCK_REG_i_18,This register contains the state of one lock" bitfld.long 0x48 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x4C "SPINLOCK_LOCK_REG_i_19,This register contains the state of one lock" bitfld.long 0x4C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x50 "SPINLOCK_LOCK_REG_i_20,This register contains the state of one lock" bitfld.long 0x50 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x54 "SPINLOCK_LOCK_REG_i_21,This register contains the state of one lock" bitfld.long 0x54 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x58 "SPINLOCK_LOCK_REG_i_22,This register contains the state of one lock" bitfld.long 0x58 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x5C "SPINLOCK_LOCK_REG_i_23,This register contains the state of one lock" bitfld.long 0x5C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x60 "SPINLOCK_LOCK_REG_i_24,This register contains the state of one lock" bitfld.long 0x60 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x64 "SPINLOCK_LOCK_REG_i_25,This register contains the state of one lock" bitfld.long 0x64 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x68 "SPINLOCK_LOCK_REG_i_26,This register contains the state of one lock" bitfld.long 0x68 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x6C "SPINLOCK_LOCK_REG_i_27,This register contains the state of one lock" bitfld.long 0x6C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x70 "SPINLOCK_LOCK_REG_i_28,This register contains the state of one lock" bitfld.long 0x70 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x74 "SPINLOCK_LOCK_REG_i_29,This register contains the state of one lock" bitfld.long 0x74 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x78 "SPINLOCK_LOCK_REG_i_30,This register contains the state of one lock" bitfld.long 0x78 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x7C "SPINLOCK_LOCK_REG_i_31,This register contains the state of one lock" bitfld.long 0x7C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x80 "SPINLOCK_LOCK_REG_i_32,This register contains the state of one lock" bitfld.long 0x80 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x84 "SPINLOCK_LOCK_REG_i_33,This register contains the state of one lock" bitfld.long 0x84 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x88 "SPINLOCK_LOCK_REG_i_34,This register contains the state of one lock" bitfld.long 0x88 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x8C "SPINLOCK_LOCK_REG_i_35,This register contains the state of one lock" bitfld.long 0x8C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x90 "SPINLOCK_LOCK_REG_i_36,This register contains the state of one lock" bitfld.long 0x90 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x94 "SPINLOCK_LOCK_REG_i_37,This register contains the state of one lock" bitfld.long 0x94 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x98 "SPINLOCK_LOCK_REG_i_38,This register contains the state of one lock" bitfld.long 0x98 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x9C "SPINLOCK_LOCK_REG_i_39,This register contains the state of one lock" bitfld.long 0x9C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xA0 "SPINLOCK_LOCK_REG_i_40,This register contains the state of one lock" bitfld.long 0xA0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xA4 "SPINLOCK_LOCK_REG_i_41,This register contains the state of one lock" bitfld.long 0xA4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xA8 "SPINLOCK_LOCK_REG_i_42,This register contains the state of one lock" bitfld.long 0xA8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xAC "SPINLOCK_LOCK_REG_i_43,This register contains the state of one lock" bitfld.long 0xAC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xB0 "SPINLOCK_LOCK_REG_i_44,This register contains the state of one lock" bitfld.long 0xB0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xB4 "SPINLOCK_LOCK_REG_i_45,This register contains the state of one lock" bitfld.long 0xB4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xB8 "SPINLOCK_LOCK_REG_i_46,This register contains the state of one lock" bitfld.long 0xB8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xBC "SPINLOCK_LOCK_REG_i_47,This register contains the state of one lock" bitfld.long 0xBC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xC0 "SPINLOCK_LOCK_REG_i_48,This register contains the state of one lock" bitfld.long 0xC0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xC4 "SPINLOCK_LOCK_REG_i_49,This register contains the state of one lock" bitfld.long 0xC4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xC8 "SPINLOCK_LOCK_REG_i_50,This register contains the state of one lock" bitfld.long 0xC8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xCC "SPINLOCK_LOCK_REG_i_51,This register contains the state of one lock" bitfld.long 0xCC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xD0 "SPINLOCK_LOCK_REG_i_52,This register contains the state of one lock" bitfld.long 0xD0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xD4 "SPINLOCK_LOCK_REG_i_53,This register contains the state of one lock" bitfld.long 0xD4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xD8 "SPINLOCK_LOCK_REG_i_54,This register contains the state of one lock" bitfld.long 0xD8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xDC "SPINLOCK_LOCK_REG_i_55,This register contains the state of one lock" bitfld.long 0xDC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xE0 "SPINLOCK_LOCK_REG_i_56,This register contains the state of one lock" bitfld.long 0xE0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xE4 "SPINLOCK_LOCK_REG_i_57,This register contains the state of one lock" bitfld.long 0xE4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xE8 "SPINLOCK_LOCK_REG_i_58,This register contains the state of one lock" bitfld.long 0xE8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xEC "SPINLOCK_LOCK_REG_i_59,This register contains the state of one lock" bitfld.long 0xEC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xF0 "SPINLOCK_LOCK_REG_i_60,This register contains the state of one lock" bitfld.long 0xF0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xF4 "SPINLOCK_LOCK_REG_i_61,This register contains the state of one lock" bitfld.long 0xF4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xF8 "SPINLOCK_LOCK_REG_i_62,This register contains the state of one lock" bitfld.long 0xF8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0xFC "SPINLOCK_LOCK_REG_i_63,This register contains the state of one lock" bitfld.long 0xFC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x100 "SPINLOCK_LOCK_REG_i_64,This register contains the state of one lock" bitfld.long 0x100 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x104 "SPINLOCK_LOCK_REG_i_65,This register contains the state of one lock" bitfld.long 0x104 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x108 "SPINLOCK_LOCK_REG_i_66,This register contains the state of one lock" bitfld.long 0x108 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x10C "SPINLOCK_LOCK_REG_i_67,This register contains the state of one lock" bitfld.long 0x10C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x110 "SPINLOCK_LOCK_REG_i_68,This register contains the state of one lock" bitfld.long 0x110 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x114 "SPINLOCK_LOCK_REG_i_69,This register contains the state of one lock" bitfld.long 0x114 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x118 "SPINLOCK_LOCK_REG_i_70,This register contains the state of one lock" bitfld.long 0x118 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x11C "SPINLOCK_LOCK_REG_i_71,This register contains the state of one lock" bitfld.long 0x11C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x120 "SPINLOCK_LOCK_REG_i_72,This register contains the state of one lock" bitfld.long 0x120 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x124 "SPINLOCK_LOCK_REG_i_73,This register contains the state of one lock" bitfld.long 0x124 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x128 "SPINLOCK_LOCK_REG_i_74,This register contains the state of one lock" bitfld.long 0x128 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x12C "SPINLOCK_LOCK_REG_i_75,This register contains the state of one lock" bitfld.long 0x12C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x130 "SPINLOCK_LOCK_REG_i_76,This register contains the state of one lock" bitfld.long 0x130 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x134 "SPINLOCK_LOCK_REG_i_77,This register contains the state of one lock" bitfld.long 0x134 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x138 "SPINLOCK_LOCK_REG_i_78,This register contains the state of one lock" bitfld.long 0x138 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x13C "SPINLOCK_LOCK_REG_i_79,This register contains the state of one lock" bitfld.long 0x13C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x140 "SPINLOCK_LOCK_REG_i_80,This register contains the state of one lock" bitfld.long 0x140 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x144 "SPINLOCK_LOCK_REG_i_81,This register contains the state of one lock" bitfld.long 0x144 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x148 "SPINLOCK_LOCK_REG_i_82,This register contains the state of one lock" bitfld.long 0x148 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x14C "SPINLOCK_LOCK_REG_i_83,This register contains the state of one lock" bitfld.long 0x14C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x150 "SPINLOCK_LOCK_REG_i_84,This register contains the state of one lock" bitfld.long 0x150 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x154 "SPINLOCK_LOCK_REG_i_85,This register contains the state of one lock" bitfld.long 0x154 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x158 "SPINLOCK_LOCK_REG_i_86,This register contains the state of one lock" bitfld.long 0x158 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x15C "SPINLOCK_LOCK_REG_i_87,This register contains the state of one lock" bitfld.long 0x15C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x160 "SPINLOCK_LOCK_REG_i_88,This register contains the state of one lock" bitfld.long 0x160 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x164 "SPINLOCK_LOCK_REG_i_89,This register contains the state of one lock" bitfld.long 0x164 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x168 "SPINLOCK_LOCK_REG_i_90,This register contains the state of one lock" bitfld.long 0x168 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x16C "SPINLOCK_LOCK_REG_i_91,This register contains the state of one lock" bitfld.long 0x16C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x170 "SPINLOCK_LOCK_REG_i_92,This register contains the state of one lock" bitfld.long 0x170 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x174 "SPINLOCK_LOCK_REG_i_93,This register contains the state of one lock" bitfld.long 0x174 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x178 "SPINLOCK_LOCK_REG_i_94,This register contains the state of one lock" bitfld.long 0x178 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x17C "SPINLOCK_LOCK_REG_i_95,This register contains the state of one lock" bitfld.long 0x17C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x180 "SPINLOCK_LOCK_REG_i_96,This register contains the state of one lock" bitfld.long 0x180 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x184 "SPINLOCK_LOCK_REG_i_97,This register contains the state of one lock" bitfld.long 0x184 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x188 "SPINLOCK_LOCK_REG_i_98,This register contains the state of one lock" bitfld.long 0x188 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x18C "SPINLOCK_LOCK_REG_i_99,This register contains the state of one lock" bitfld.long 0x18C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x190 "SPINLOCK_LOCK_REG_i_100,This register contains the state of one lock" bitfld.long 0x190 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x194 "SPINLOCK_LOCK_REG_i_101,This register contains the state of one lock" bitfld.long 0x194 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x198 "SPINLOCK_LOCK_REG_i_102,This register contains the state of one lock" bitfld.long 0x198 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x19C "SPINLOCK_LOCK_REG_i_103,This register contains the state of one lock" bitfld.long 0x19C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A0 "SPINLOCK_LOCK_REG_i_104,This register contains the state of one lock" bitfld.long 0x1A0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A4 "SPINLOCK_LOCK_REG_i_105,This register contains the state of one lock" bitfld.long 0x1A4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1A8 "SPINLOCK_LOCK_REG_i_106,This register contains the state of one lock" bitfld.long 0x1A8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1AC "SPINLOCK_LOCK_REG_i_107,This register contains the state of one lock" bitfld.long 0x1AC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B0 "SPINLOCK_LOCK_REG_i_108,This register contains the state of one lock" bitfld.long 0x1B0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B4 "SPINLOCK_LOCK_REG_i_109,This register contains the state of one lock" bitfld.long 0x1B4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1B8 "SPINLOCK_LOCK_REG_i_110,This register contains the state of one lock" bitfld.long 0x1B8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1BC "SPINLOCK_LOCK_REG_i_111,This register contains the state of one lock" bitfld.long 0x1BC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C0 "SPINLOCK_LOCK_REG_i_112,This register contains the state of one lock" bitfld.long 0x1C0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C4 "SPINLOCK_LOCK_REG_i_113,This register contains the state of one lock" bitfld.long 0x1C4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1C8 "SPINLOCK_LOCK_REG_i_114,This register contains the state of one lock" bitfld.long 0x1C8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1CC "SPINLOCK_LOCK_REG_i_115,This register contains the state of one lock" bitfld.long 0x1CC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D0 "SPINLOCK_LOCK_REG_i_116,This register contains the state of one lock" bitfld.long 0x1D0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D4 "SPINLOCK_LOCK_REG_i_117,This register contains the state of one lock" bitfld.long 0x1D4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1D8 "SPINLOCK_LOCK_REG_i_118,This register contains the state of one lock" bitfld.long 0x1D8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1DC "SPINLOCK_LOCK_REG_i_119,This register contains the state of one lock" bitfld.long 0x1DC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E0 "SPINLOCK_LOCK_REG_i_120,This register contains the state of one lock" bitfld.long 0x1E0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E4 "SPINLOCK_LOCK_REG_i_121,This register contains the state of one lock" bitfld.long 0x1E4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1E8 "SPINLOCK_LOCK_REG_i_122,This register contains the state of one lock" bitfld.long 0x1E8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1EC "SPINLOCK_LOCK_REG_i_123,This register contains the state of one lock" bitfld.long 0x1EC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F0 "SPINLOCK_LOCK_REG_i_124,This register contains the state of one lock" bitfld.long 0x1F0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F4 "SPINLOCK_LOCK_REG_i_125,This register contains the state of one lock" bitfld.long 0x1F4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1F8 "SPINLOCK_LOCK_REG_i_126,This register contains the state of one lock" bitfld.long 0x1F8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x1FC "SPINLOCK_LOCK_REG_i_127,This register contains the state of one lock" bitfld.long 0x1FC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x200 "SPINLOCK_LOCK_REG_i_128,This register contains the state of one lock" bitfld.long 0x200 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x204 "SPINLOCK_LOCK_REG_i_129,This register contains the state of one lock" bitfld.long 0x204 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x208 "SPINLOCK_LOCK_REG_i_130,This register contains the state of one lock" bitfld.long 0x208 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x20C "SPINLOCK_LOCK_REG_i_131,This register contains the state of one lock" bitfld.long 0x20C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x210 "SPINLOCK_LOCK_REG_i_132,This register contains the state of one lock" bitfld.long 0x210 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x214 "SPINLOCK_LOCK_REG_i_133,This register contains the state of one lock" bitfld.long 0x214 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x218 "SPINLOCK_LOCK_REG_i_134,This register contains the state of one lock" bitfld.long 0x218 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x21C "SPINLOCK_LOCK_REG_i_135,This register contains the state of one lock" bitfld.long 0x21C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x220 "SPINLOCK_LOCK_REG_i_136,This register contains the state of one lock" bitfld.long 0x220 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x224 "SPINLOCK_LOCK_REG_i_137,This register contains the state of one lock" bitfld.long 0x224 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x228 "SPINLOCK_LOCK_REG_i_138,This register contains the state of one lock" bitfld.long 0x228 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x22C "SPINLOCK_LOCK_REG_i_139,This register contains the state of one lock" bitfld.long 0x22C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x230 "SPINLOCK_LOCK_REG_i_140,This register contains the state of one lock" bitfld.long 0x230 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x234 "SPINLOCK_LOCK_REG_i_141,This register contains the state of one lock" bitfld.long 0x234 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x238 "SPINLOCK_LOCK_REG_i_142,This register contains the state of one lock" bitfld.long 0x238 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x23C "SPINLOCK_LOCK_REG_i_143,This register contains the state of one lock" bitfld.long 0x23C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x240 "SPINLOCK_LOCK_REG_i_144,This register contains the state of one lock" bitfld.long 0x240 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x244 "SPINLOCK_LOCK_REG_i_145,This register contains the state of one lock" bitfld.long 0x244 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x248 "SPINLOCK_LOCK_REG_i_146,This register contains the state of one lock" bitfld.long 0x248 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x24C "SPINLOCK_LOCK_REG_i_147,This register contains the state of one lock" bitfld.long 0x24C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x250 "SPINLOCK_LOCK_REG_i_148,This register contains the state of one lock" bitfld.long 0x250 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x254 "SPINLOCK_LOCK_REG_i_149,This register contains the state of one lock" bitfld.long 0x254 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x258 "SPINLOCK_LOCK_REG_i_150,This register contains the state of one lock" bitfld.long 0x258 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x25C "SPINLOCK_LOCK_REG_i_151,This register contains the state of one lock" bitfld.long 0x25C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x260 "SPINLOCK_LOCK_REG_i_152,This register contains the state of one lock" bitfld.long 0x260 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x264 "SPINLOCK_LOCK_REG_i_153,This register contains the state of one lock" bitfld.long 0x264 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x268 "SPINLOCK_LOCK_REG_i_154,This register contains the state of one lock" bitfld.long 0x268 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x26C "SPINLOCK_LOCK_REG_i_155,This register contains the state of one lock" bitfld.long 0x26C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x270 "SPINLOCK_LOCK_REG_i_156,This register contains the state of one lock" bitfld.long 0x270 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x274 "SPINLOCK_LOCK_REG_i_157,This register contains the state of one lock" bitfld.long 0x274 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x278 "SPINLOCK_LOCK_REG_i_158,This register contains the state of one lock" bitfld.long 0x278 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x27C "SPINLOCK_LOCK_REG_i_159,This register contains the state of one lock" bitfld.long 0x27C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x280 "SPINLOCK_LOCK_REG_i_160,This register contains the state of one lock" bitfld.long 0x280 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x284 "SPINLOCK_LOCK_REG_i_161,This register contains the state of one lock" bitfld.long 0x284 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x288 "SPINLOCK_LOCK_REG_i_162,This register contains the state of one lock" bitfld.long 0x288 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x28C "SPINLOCK_LOCK_REG_i_163,This register contains the state of one lock" bitfld.long 0x28C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x290 "SPINLOCK_LOCK_REG_i_164,This register contains the state of one lock" bitfld.long 0x290 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x294 "SPINLOCK_LOCK_REG_i_165,This register contains the state of one lock" bitfld.long 0x294 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x298 "SPINLOCK_LOCK_REG_i_166,This register contains the state of one lock" bitfld.long 0x298 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x29C "SPINLOCK_LOCK_REG_i_167,This register contains the state of one lock" bitfld.long 0x29C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A0 "SPINLOCK_LOCK_REG_i_168,This register contains the state of one lock" bitfld.long 0x2A0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A4 "SPINLOCK_LOCK_REG_i_169,This register contains the state of one lock" bitfld.long 0x2A4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2A8 "SPINLOCK_LOCK_REG_i_170,This register contains the state of one lock" bitfld.long 0x2A8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2AC "SPINLOCK_LOCK_REG_i_171,This register contains the state of one lock" bitfld.long 0x2AC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B0 "SPINLOCK_LOCK_REG_i_172,This register contains the state of one lock" bitfld.long 0x2B0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B4 "SPINLOCK_LOCK_REG_i_173,This register contains the state of one lock" bitfld.long 0x2B4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2B8 "SPINLOCK_LOCK_REG_i_174,This register contains the state of one lock" bitfld.long 0x2B8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2BC "SPINLOCK_LOCK_REG_i_175,This register contains the state of one lock" bitfld.long 0x2BC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C0 "SPINLOCK_LOCK_REG_i_176,This register contains the state of one lock" bitfld.long 0x2C0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C4 "SPINLOCK_LOCK_REG_i_177,This register contains the state of one lock" bitfld.long 0x2C4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2C8 "SPINLOCK_LOCK_REG_i_178,This register contains the state of one lock" bitfld.long 0x2C8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2CC "SPINLOCK_LOCK_REG_i_179,This register contains the state of one lock" bitfld.long 0x2CC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D0 "SPINLOCK_LOCK_REG_i_180,This register contains the state of one lock" bitfld.long 0x2D0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D4 "SPINLOCK_LOCK_REG_i_181,This register contains the state of one lock" bitfld.long 0x2D4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2D8 "SPINLOCK_LOCK_REG_i_182,This register contains the state of one lock" bitfld.long 0x2D8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2DC "SPINLOCK_LOCK_REG_i_183,This register contains the state of one lock" bitfld.long 0x2DC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E0 "SPINLOCK_LOCK_REG_i_184,This register contains the state of one lock" bitfld.long 0x2E0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E4 "SPINLOCK_LOCK_REG_i_185,This register contains the state of one lock" bitfld.long 0x2E4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2E8 "SPINLOCK_LOCK_REG_i_186,This register contains the state of one lock" bitfld.long 0x2E8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2EC "SPINLOCK_LOCK_REG_i_187,This register contains the state of one lock" bitfld.long 0x2EC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F0 "SPINLOCK_LOCK_REG_i_188,This register contains the state of one lock" bitfld.long 0x2F0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F4 "SPINLOCK_LOCK_REG_i_189,This register contains the state of one lock" bitfld.long 0x2F4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2F8 "SPINLOCK_LOCK_REG_i_190,This register contains the state of one lock" bitfld.long 0x2F8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x2FC "SPINLOCK_LOCK_REG_i_191,This register contains the state of one lock" bitfld.long 0x2FC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x300 "SPINLOCK_LOCK_REG_i_192,This register contains the state of one lock" bitfld.long 0x300 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x304 "SPINLOCK_LOCK_REG_i_193,This register contains the state of one lock" bitfld.long 0x304 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x308 "SPINLOCK_LOCK_REG_i_194,This register contains the state of one lock" bitfld.long 0x308 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x30C "SPINLOCK_LOCK_REG_i_195,This register contains the state of one lock" bitfld.long 0x30C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x310 "SPINLOCK_LOCK_REG_i_196,This register contains the state of one lock" bitfld.long 0x310 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x314 "SPINLOCK_LOCK_REG_i_197,This register contains the state of one lock" bitfld.long 0x314 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x318 "SPINLOCK_LOCK_REG_i_198,This register contains the state of one lock" bitfld.long 0x318 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x31C "SPINLOCK_LOCK_REG_i_199,This register contains the state of one lock" bitfld.long 0x31C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x320 "SPINLOCK_LOCK_REG_i_200,This register contains the state of one lock" bitfld.long 0x320 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x324 "SPINLOCK_LOCK_REG_i_201,This register contains the state of one lock" bitfld.long 0x324 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x328 "SPINLOCK_LOCK_REG_i_202,This register contains the state of one lock" bitfld.long 0x328 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x32C "SPINLOCK_LOCK_REG_i_203,This register contains the state of one lock" bitfld.long 0x32C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x330 "SPINLOCK_LOCK_REG_i_204,This register contains the state of one lock" bitfld.long 0x330 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x334 "SPINLOCK_LOCK_REG_i_205,This register contains the state of one lock" bitfld.long 0x334 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x338 "SPINLOCK_LOCK_REG_i_206,This register contains the state of one lock" bitfld.long 0x338 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x33C "SPINLOCK_LOCK_REG_i_207,This register contains the state of one lock" bitfld.long 0x33C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x340 "SPINLOCK_LOCK_REG_i_208,This register contains the state of one lock" bitfld.long 0x340 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x344 "SPINLOCK_LOCK_REG_i_209,This register contains the state of one lock" bitfld.long 0x344 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x348 "SPINLOCK_LOCK_REG_i_210,This register contains the state of one lock" bitfld.long 0x348 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x34C "SPINLOCK_LOCK_REG_i_211,This register contains the state of one lock" bitfld.long 0x34C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x350 "SPINLOCK_LOCK_REG_i_212,This register contains the state of one lock" bitfld.long 0x350 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x354 "SPINLOCK_LOCK_REG_i_213,This register contains the state of one lock" bitfld.long 0x354 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x358 "SPINLOCK_LOCK_REG_i_214,This register contains the state of one lock" bitfld.long 0x358 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x35C "SPINLOCK_LOCK_REG_i_215,This register contains the state of one lock" bitfld.long 0x35C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x360 "SPINLOCK_LOCK_REG_i_216,This register contains the state of one lock" bitfld.long 0x360 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x364 "SPINLOCK_LOCK_REG_i_217,This register contains the state of one lock" bitfld.long 0x364 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x368 "SPINLOCK_LOCK_REG_i_218,This register contains the state of one lock" bitfld.long 0x368 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x36C "SPINLOCK_LOCK_REG_i_219,This register contains the state of one lock" bitfld.long 0x36C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x370 "SPINLOCK_LOCK_REG_i_220,This register contains the state of one lock" bitfld.long 0x370 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x374 "SPINLOCK_LOCK_REG_i_221,This register contains the state of one lock" bitfld.long 0x374 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x378 "SPINLOCK_LOCK_REG_i_222,This register contains the state of one lock" bitfld.long 0x378 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x37C "SPINLOCK_LOCK_REG_i_223,This register contains the state of one lock" bitfld.long 0x37C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x380 "SPINLOCK_LOCK_REG_i_224,This register contains the state of one lock" bitfld.long 0x380 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x384 "SPINLOCK_LOCK_REG_i_225,This register contains the state of one lock" bitfld.long 0x384 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x388 "SPINLOCK_LOCK_REG_i_226,This register contains the state of one lock" bitfld.long 0x388 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x38C "SPINLOCK_LOCK_REG_i_227,This register contains the state of one lock" bitfld.long 0x38C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x390 "SPINLOCK_LOCK_REG_i_228,This register contains the state of one lock" bitfld.long 0x390 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x394 "SPINLOCK_LOCK_REG_i_229,This register contains the state of one lock" bitfld.long 0x394 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x398 "SPINLOCK_LOCK_REG_i_230,This register contains the state of one lock" bitfld.long 0x398 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x39C "SPINLOCK_LOCK_REG_i_231,This register contains the state of one lock" bitfld.long 0x39C 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A0 "SPINLOCK_LOCK_REG_i_232,This register contains the state of one lock" bitfld.long 0x3A0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A4 "SPINLOCK_LOCK_REG_i_233,This register contains the state of one lock" bitfld.long 0x3A4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3A8 "SPINLOCK_LOCK_REG_i_234,This register contains the state of one lock" bitfld.long 0x3A8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3AC "SPINLOCK_LOCK_REG_i_235,This register contains the state of one lock" bitfld.long 0x3AC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B0 "SPINLOCK_LOCK_REG_i_236,This register contains the state of one lock" bitfld.long 0x3B0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B4 "SPINLOCK_LOCK_REG_i_237,This register contains the state of one lock" bitfld.long 0x3B4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3B8 "SPINLOCK_LOCK_REG_i_238,This register contains the state of one lock" bitfld.long 0x3B8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3BC "SPINLOCK_LOCK_REG_i_239,This register contains the state of one lock" bitfld.long 0x3BC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C0 "SPINLOCK_LOCK_REG_i_240,This register contains the state of one lock" bitfld.long 0x3C0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C4 "SPINLOCK_LOCK_REG_i_241,This register contains the state of one lock" bitfld.long 0x3C4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3C8 "SPINLOCK_LOCK_REG_i_242,This register contains the state of one lock" bitfld.long 0x3C8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3CC "SPINLOCK_LOCK_REG_i_243,This register contains the state of one lock" bitfld.long 0x3CC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D0 "SPINLOCK_LOCK_REG_i_244,This register contains the state of one lock" bitfld.long 0x3D0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D4 "SPINLOCK_LOCK_REG_i_245,This register contains the state of one lock" bitfld.long 0x3D4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3D8 "SPINLOCK_LOCK_REG_i_246,This register contains the state of one lock" bitfld.long 0x3D8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3DC "SPINLOCK_LOCK_REG_i_247,This register contains the state of one lock" bitfld.long 0x3DC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E0 "SPINLOCK_LOCK_REG_i_248,This register contains the state of one lock" bitfld.long 0x3E0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E4 "SPINLOCK_LOCK_REG_i_249,This register contains the state of one lock" bitfld.long 0x3E4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3E8 "SPINLOCK_LOCK_REG_i_250,This register contains the state of one lock" bitfld.long 0x3E8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3EC "SPINLOCK_LOCK_REG_i_251,This register contains the state of one lock" bitfld.long 0x3EC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F0 "SPINLOCK_LOCK_REG_i_252,This register contains the state of one lock" bitfld.long 0x3F0 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F4 "SPINLOCK_LOCK_REG_i_253,This register contains the state of one lock" bitfld.long 0x3F4 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3F8 "SPINLOCK_LOCK_REG_i_254,This register contains the state of one lock" bitfld.long 0x3F8 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" line.long 0x3FC "SPINLOCK_LOCK_REG_i_255,This register contains the state of one lock" bitfld.long 0x3FC 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" tree.end rgroup.long 0x00++0x03 line.long 0x00 "SPINLOCK_REVISION,This register contains the IP revision code" group.long 0x10++0x07 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE request/acknowledgement control)" "SIDLEMODE_0_r,SIDLEMODE_1_r,SIDLEMODE_2_r,SIDLEMODE_3_r" rbitfld.long 0x00 2. "ENWAKEUP,Asynchronous wakeup gereration" "ENWAKEUP_0_r,ENWAKEUP_1_r" bitfld.long 0x00 1. "SOFTRESET,Module software reset" "SOFTRESET_0_w,SOFTRESET_1_w" rbitfld.long 0x00 0. "AUTOGATING,Internal interface clock gating strategy" "AUTOGATING_0_r,AUTOGATING_1_r" line.long 0x04 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module" hexmask.long.byte 0x04 24.--31. 1. "NUMLOCKS,Number of lock registers implemeted" bitfld.long 0x04 15. "IU7,In-Use flag 0 covering lock registers" "IU7_0_r,IU7_1_r" bitfld.long 0x04 14. "IU6,In-Use flag 0 covering lock registers" "IU6_0_r,IU6_1_r" bitfld.long 0x04 13. "IU5,In-Use flag 0 covering lock registers" "IU5_0_r,IU5_1_r" bitfld.long 0x04 12. "IU4,In-Use flag 0 covering lock registers" "IU4_0_r,IU4_1_r" newline bitfld.long 0x04 11. "IU3,In-Use flag 0 covering lock registers" "IU3_0_r,IU3_1_r" bitfld.long 0x04 10. "IU2,In-Use flag 0 covering lock registers" "IU2_0_r,IU2_1_r" bitfld.long 0x04 9. "IU1,In-Use flag 0 covering lock registers" "IU1_0_r,IU1_1_r" bitfld.long 0x04 8. "IU0,In-Use flag 0 covering lock registers" "IU0_0_r,IU0_1_r" bitfld.long 0x04 0. "RESETDONE,Reset done status" "RESETDONE_0_r,RESETDONE_1_r" width 0x0B tree.end tree "System_DMA" base ad:0x4A056000 rgroup.long 0x64++0x03 line.long 0x00 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW" bitfld.long 0x00 21. "LINK_LIST_CPBLTY_TYPE4,Link List capability for type4 descriptor capability" "LINK_LIST_CPBLTY_TYPE4_0,LINK_LIST_CPBLTY_TYPE4_1" newline bitfld.long 0x00 20. "LINK_LIST_CPBLTY_TYPE123,Link List capability for type123 descriptor capability" "LINK_LIST_CPBLTY_TYPE123_0,LINK_LIST_CPBLTY_TYPE123_1" newline bitfld.long 0x00 19. "CONST_FILL_CPBLTY,Constant_Fill_Capability - NoLCH" "CONST_FILL_CPBLTY_0_r,CONST_FILL_CPBLTY_1_r" newline bitfld.long 0x00 18. "TRANSPARENT_BLT_CPBLTY,Transparent_BLT_Capability - NoLCH" "TRANSPARENT_BLT_CPBLTY_0_r,TRANSPARENT_BLT_CPBLTY_1_r" rgroup.long 0x6C++0x0F line.long 0x00 "DMA4_CAPS_2,DMA Capabilities Register 2" bitfld.long 0x00 8. "SEPARATE_SRC_AND_DST_INDEX_CPBLTY,Separate_source/destination_index_capability - NotSupported" "SEPARATE_SRC_AND_DST_INDEX_CPBLTY_0_r,SEPARATE_SRC_AND_DST_INDEX_CPBLTY_1_r" newline bitfld.long 0x00 7. "DST_DOUBLE_INDEX_ADRS_CPBLTY,Destination_double_index_address_capability - NotSupported" "DST_DOUBLE_INDEX_ADRS_CPBLTY_0_r,DST_DOUBLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 6. "DST_SINGLE_INDEX_ADRS_CPBLTY,Destination_single_index_address_capability - NotSupported" "DST_SINGLE_INDEX_ADRS_CPBLTY_0_r,DST_SINGLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 5. "DST_POST_INCRMNT_ADRS_CPBLTY,Destination_post_increment_address_capability - NotSupported" "DST_POST_INCRMNT_ADRS_CPBLTY_0_r,DST_POST_INCRMNT_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 4. "DST_CONST_ADRS_CPBLTY,Destination_constant_address_capability - NotSupported" "DST_CONST_ADRS_CPBLTY_0_r,DST_CONST_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 3. "SRC_DOUBLE_INDEX_ADRS_CPBLTY,Source_double_index_address_capability - NotSupported" "SRC_DOUBLE_INDEX_ADRS_CPBLTY_0_r,SRC_DOUBLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 2. "SRC_SINGLE_INDEX_ADRS_CPBLTY,Source_single_index_address_capability - NotSupported" "SRC_SINGLE_INDEX_ADRS_CPBLTY_0_r,SRC_SINGLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 1. "SRC_POST_INCREMENT_ADRS_CPBLTY,Source_post_increment_address_capability - NotSupported" "SRC_POST_INCREMENT_ADRS_CPBLTY_0_r,SRC_POST_INCREMENT_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 0. "SRC_CONST_ADRS_CPBLTY,Source_constant_address_capability - NotSupported" "SRC_CONST_ADRS_CPBLTY_0_r,SRC_CONST_ADRS_CPBLTY_1_r" line.long 0x04 "DMA4_CAPS_3,DMA Capabilities Register 3" bitfld.long 0x04 7. "BLOCK_SYNCHR_CPBLTY," "BLOCK_SYNCHR_CPBLTY_0_r,BLOCK_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 6. "PKT_SYNCHR_CPBLTY,Packet_synchronization_capability - NotSupported" "PKT_SYNCHR_CPBLTY_0_r,PKT_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 5. "CHANNEL_CHANINIG_CPBLTY," "CHANNEL_CHANINIG_CPBLTY_0_r,CHANNEL_CHANINIG_CPBLTY_1_r" newline bitfld.long 0x04 4. "CHANNEL_INTERLEAVE_CPBLTY," "CHANNEL_INTERLEAVE_CPBLTY_0_r,CHANNEL_INTERLEAVE_CPBLTY_1_r" newline bitfld.long 0x04 1. "FRAME_SYNCHR_CPBLTY," "FRAME_SYNCHR_CPBLTY_0_r,FRAME_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 0. "ELMNT_SYNCHR_CPBLTY," "ELMNT_SYNCHR_CPBLTY_0_r,ELMNT_SYNCHR_CPBLTY_1_r" line.long 0x08 "DMA4_CAPS_4,DMA Capabilities Register 4" bitfld.long 0x08 14. "EOSB_INTERRUPT_CPBLTY,End of Super Block detection capability" "EOSB_INTERRUPT_CPBLTY_0,EOSB_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 12. "DRAIN_END_INTERRUPT_CPBLTY,Drain End detection capability" "DRAIN_END_INTERRUPT_CPBLTY_0,DRAIN_END_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 11. "MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY,Misaligned error detection capability" "MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY_0,MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 10. "SUPERVISOR_ERR_INTERRUPT_CPBLTY,Supervisor error detection capability" "SUPERVISOR_ERR_INTERRUPT_CPBLTY_0,SUPERVISOR_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 8. "TRANS_ERR_INTERRUPT_CPBLTY,Transaction error detection capability" "TRANS_ERR_INTERRUPT_CPBLTY_0,TRANS_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 7. "PKT_INTERRUPT_CPBLTY,End of Packet detection capability" "PKT_INTERRUPT_CPBLTY_0_r,PKT_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 6. "SYNC_STATUS_CPBLTY,Sync_status_capability - NotSupported" "SYNC_STATUS_CPBLTY_0_r,SYNC_STATUS_CPBLTY_1_r" newline bitfld.long 0x08 5. "BLOCK_INTERRUPT_CPBLTY,End of block detection capability" "BLOCK_INTERRUPT_CPBLTY_0_r,BLOCK_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 4. "LAST_FRAME_INTERRUPT_CPBLTY,Start of last frame detection capability" "LAST_FRAME_INTERRUPT_CPBLTY_0_r,LAST_FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 3. "FRAME_INTERRUPT_CPBLTY,End of frame detection capability" "FRAME_INTERRUPT_CPBLTY_0_r,FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 2. "HALF_FRAME_INTERRUPT_CPBLTY,Detection capability of the half of frame end" "HALF_FRAME_INTERRUPT_CPBLTY_0_r,HALF_FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 1. "EVENT_DROP_INTERRUPT_CPBLTY,Request collision detection capability" "EVENT_DROP_INTERRUPT_CPBLTY_0_r,EVENT_DROP_INTERRUPT_CPBLTY_1_r" line.long 0x0C "DMA4_GCR,FIFO sharing between high and low priority channel" bitfld.long 0x0C 24. "CHANNEL_ID_GATE,Gates the Channel ID bus monitoring on both Read and Write ports" "Gates the Channel ID qualifiers on both Read and..,Does not gate the Channel ID qualifiers on both.." newline hexmask.long.byte 0x0C 16.--23. 1. "ARBITRATION_RATE,Arbitration switching rate between prioritized and regular channel queues" newline bitfld.long 0x0C 14.--15. "HI_LO_FIFO_BUDGET,Allow to have a separate Global FIFO budget for high and low priority channels" "HI_LO_FIFO_BUDGET_0,HI_LO_FIFO_BUDGET_1,HI_LO_FIFO_BUDGET_2,HI_LO_FIFO_BUDGET_3" newline bitfld.long 0x0C 12.--13. "HI_THREAD_RESERVED,Allow thread reservation for high priority channel on both read and write ports" "HI_THREAD_RESERVED_0,HI_THREAD_RESERVED_1,HI_THREAD_RESERVED_2,HI_THREAD_RESERVED_3" newline hexmask.long.byte 0x0C 0.--7. 1. "MAX_CHANNEL_FIFO_DEPTH,Maximum FIFO depth allocated to one logical channel" group.long 0x2C++0x03 line.long 0x00 "DMA4_OCP_SYSCONFIG,DMA system configuration register" bitfld.long 0x00 12.--13. "MIDLEMODE,Read write power management standby/wait control - Force" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activities during wake-up Bit" "0,1,2,3" newline bitfld.long 0x00 5. "EMUFREE,Enable sensitivity to MSuspend - Frozen" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Configuration port power management Idle req/ack control - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock gating strategy - FreeRunning" "AUTOIDLE_0,AUTOIDLE_1" rgroup.long 0x00++0x03 line.long 0x00 "DMA4_REVISION,This register contains the DMA revision code" rgroup.long 0x28++0x03 line.long 0x00 "DMA4_SYSSTATUS,The register provides status information about the module excluding the interrupt status information (see interrupt status register)" bitfld.long 0x00 0. "RESETDONE,Internal reset monitoring - OnGoing" "RESETDONE_0_r,RESETDONE_1_r" tree "DMA_Channel_0" group.long 0xD8++0x03 line.long 0x00 "DMA4_CCDNi_0," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xBC++0x07 line.long 0x00 "DMA4_CCENi_0,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_0,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x80++0x03 line.long 0x00 "DMA4_CCRi_0,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB8++0x03 line.long 0x00 "DMA4_CDACi_0,Channel Destination Address Value" group.long 0xAC++0x07 line.long 0x00 "DMA4_CDEIi_0,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_0,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xD0++0x03 line.long 0x00 "DMA4_CDPi_0,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xA0++0x03 line.long 0x00 "DMA4_CDSAi_0,Channel Destination Start Address" group.long 0x94++0x07 line.long 0x00 "DMA4_CENi_0,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_0,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x88++0x03 line.long 0x00 "DMA4_CICRi_0,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x84++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_0,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x03 line.long 0x00 "DMA4_CNDPi_0,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC4++0x03 line.long 0x00 "DMA4_COLORi_0,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xB4++0x03 line.long 0x00 "DMA4_CSACi_0,Channel Source Address Value" group.long 0x90++0x03 line.long 0x00 "DMA4_CSDPi_0,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xA4++0x07 line.long 0x00 "DMA4_CSEIi_0,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_0,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x8C++0x03 line.long 0x00 "DMA4_CSRi_0,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x9C++0x03 line.long 0x00 "DMA4_CSSAi_0,Channel Source Start Address" group.long 0x18++0x03 line.long 0x00 "DMA4_IRQENABLE_Lj_0,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on line Lj" group.long 0x08++0x03 line.long 0x00 "DMA4_IRQSTATUS_Lj_0,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj" tree.end tree "DMA_Channel_1" group.long 0x138++0x03 line.long 0x00 "DMA4_CCDNi_1," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x11C++0x07 line.long 0x00 "DMA4_CCENi_1,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_1,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xE0++0x03 line.long 0x00 "DMA4_CCRi_1,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x118++0x03 line.long 0x00 "DMA4_CDACi_1,Channel Destination Address Value" group.long 0x10C++0x07 line.long 0x00 "DMA4_CDEIi_1,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_1,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x130++0x03 line.long 0x00 "DMA4_CDPi_1,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x100++0x03 line.long 0x00 "DMA4_CDSAi_1,Channel Destination Start Address" group.long 0xF4++0x07 line.long 0x00 "DMA4_CENi_1,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_1,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xE8++0x03 line.long 0x00 "DMA4_CICRi_1,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xE4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_1,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "DMA4_CNDPi_1,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x124++0x03 line.long 0x00 "DMA4_COLORi_1,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x114++0x03 line.long 0x00 "DMA4_CSACi_1,Channel Source Address Value" group.long 0xF0++0x03 line.long 0x00 "DMA4_CSDPi_1,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x104++0x07 line.long 0x00 "DMA4_CSEIi_1,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_1,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xEC++0x03 line.long 0x00 "DMA4_CSRi_1,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xFC++0x03 line.long 0x00 "DMA4_CSSAi_1,Channel Source Start Address" group.long 0x1C++0x03 line.long 0x00 "DMA4_IRQENABLE_Lj_1,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on line Lj" group.long 0x0C++0x03 line.long 0x00 "DMA4_IRQSTATUS_Lj_1,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj" tree.end tree "DMA_Channel_10" group.long 0x498++0x03 line.long 0x00 "DMA4_CCDNi_10," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x47C++0x07 line.long 0x00 "DMA4_CCENi_10,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_10,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x440++0x03 line.long 0x00 "DMA4_CCRi_10,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x478++0x03 line.long 0x00 "DMA4_CDACi_10,Channel Destination Address Value" group.long 0x46C++0x07 line.long 0x00 "DMA4_CDEIi_10,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_10,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x490++0x03 line.long 0x00 "DMA4_CDPi_10,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x460++0x03 line.long 0x00 "DMA4_CDSAi_10,Channel Destination Start Address" group.long 0x454++0x07 line.long 0x00 "DMA4_CENi_10,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_10,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x448++0x03 line.long 0x00 "DMA4_CICRi_10,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x444++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_10,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x494++0x03 line.long 0x00 "DMA4_CNDPi_10,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x484++0x03 line.long 0x00 "DMA4_COLORi_10,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x474++0x03 line.long 0x00 "DMA4_CSACi_10,Channel Source Address Value" group.long 0x450++0x03 line.long 0x00 "DMA4_CSDPi_10,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x464++0x07 line.long 0x00 "DMA4_CSEIi_10,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_10,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x44C++0x03 line.long 0x00 "DMA4_CSRi_10,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x45C++0x03 line.long 0x00 "DMA4_CSSAi_10,Channel Source Start Address" tree.end tree "DMA_Channel_11" group.long 0x4F8++0x03 line.long 0x00 "DMA4_CCDNi_11," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x4DC++0x07 line.long 0x00 "DMA4_CCENi_11,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_11,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x4A0++0x03 line.long 0x00 "DMA4_CCRi_11,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4D8++0x03 line.long 0x00 "DMA4_CDACi_11,Channel Destination Address Value" group.long 0x4CC++0x07 line.long 0x00 "DMA4_CDEIi_11,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_11,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x4F0++0x03 line.long 0x00 "DMA4_CDPi_11,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x4C0++0x03 line.long 0x00 "DMA4_CDSAi_11,Channel Destination Start Address" group.long 0x4B4++0x07 line.long 0x00 "DMA4_CENi_11,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_11,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x4A8++0x03 line.long 0x00 "DMA4_CICRi_11,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x4A4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_11,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F4++0x03 line.long 0x00 "DMA4_CNDPi_11,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x4E4++0x03 line.long 0x00 "DMA4_COLORi_11,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x4D4++0x03 line.long 0x00 "DMA4_CSACi_11,Channel Source Address Value" group.long 0x4B0++0x03 line.long 0x00 "DMA4_CSDPi_11,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x4C4++0x07 line.long 0x00 "DMA4_CSEIi_11,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_11,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x4AC++0x03 line.long 0x00 "DMA4_CSRi_11,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x4BC++0x03 line.long 0x00 "DMA4_CSSAi_11,Channel Source Start Address" tree.end tree "DMA_Channel_12" group.long 0x558++0x03 line.long 0x00 "DMA4_CCDNi_12," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x53C++0x07 line.long 0x00 "DMA4_CCENi_12,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_12,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x500++0x03 line.long 0x00 "DMA4_CCRi_12,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x538++0x03 line.long 0x00 "DMA4_CDACi_12,Channel Destination Address Value" group.long 0x52C++0x07 line.long 0x00 "DMA4_CDEIi_12,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_12,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x550++0x03 line.long 0x00 "DMA4_CDPi_12,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x520++0x03 line.long 0x00 "DMA4_CDSAi_12,Channel Destination Start Address" group.long 0x514++0x07 line.long 0x00 "DMA4_CENi_12,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_12,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x508++0x03 line.long 0x00 "DMA4_CICRi_12,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x504++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_12,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x554++0x03 line.long 0x00 "DMA4_CNDPi_12,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x544++0x03 line.long 0x00 "DMA4_COLORi_12,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x534++0x03 line.long 0x00 "DMA4_CSACi_12,Channel Source Address Value" group.long 0x510++0x03 line.long 0x00 "DMA4_CSDPi_12,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x524++0x07 line.long 0x00 "DMA4_CSEIi_12,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_12,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x50C++0x03 line.long 0x00 "DMA4_CSRi_12,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x51C++0x03 line.long 0x00 "DMA4_CSSAi_12,Channel Source Start Address" tree.end tree "DMA_Channel_13" group.long 0x5B8++0x03 line.long 0x00 "DMA4_CCDNi_13," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x59C++0x07 line.long 0x00 "DMA4_CCENi_13,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_13,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x560++0x03 line.long 0x00 "DMA4_CCRi_13,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x598++0x03 line.long 0x00 "DMA4_CDACi_13,Channel Destination Address Value" group.long 0x58C++0x07 line.long 0x00 "DMA4_CDEIi_13,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_13,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x5B0++0x03 line.long 0x00 "DMA4_CDPi_13,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x580++0x03 line.long 0x00 "DMA4_CDSAi_13,Channel Destination Start Address" group.long 0x574++0x07 line.long 0x00 "DMA4_CENi_13,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_13,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x568++0x03 line.long 0x00 "DMA4_CICRi_13,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x564++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_13,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B4++0x03 line.long 0x00 "DMA4_CNDPi_13,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x5A4++0x03 line.long 0x00 "DMA4_COLORi_13,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x594++0x03 line.long 0x00 "DMA4_CSACi_13,Channel Source Address Value" group.long 0x570++0x03 line.long 0x00 "DMA4_CSDPi_13,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x584++0x07 line.long 0x00 "DMA4_CSEIi_13,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_13,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x56C++0x03 line.long 0x00 "DMA4_CSRi_13,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x57C++0x03 line.long 0x00 "DMA4_CSSAi_13,Channel Source Start Address" tree.end tree "DMA_Channel_14" group.long 0x618++0x03 line.long 0x00 "DMA4_CCDNi_14," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x5FC++0x07 line.long 0x00 "DMA4_CCENi_14,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_14,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x5C0++0x03 line.long 0x00 "DMA4_CCRi_14,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5F8++0x03 line.long 0x00 "DMA4_CDACi_14,Channel Destination Address Value" group.long 0x5EC++0x07 line.long 0x00 "DMA4_CDEIi_14,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_14,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x610++0x03 line.long 0x00 "DMA4_CDPi_14,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x5E0++0x03 line.long 0x00 "DMA4_CDSAi_14,Channel Destination Start Address" group.long 0x5D4++0x07 line.long 0x00 "DMA4_CENi_14,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_14,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x5C8++0x03 line.long 0x00 "DMA4_CICRi_14,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x5C4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_14,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x614++0x03 line.long 0x00 "DMA4_CNDPi_14,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x604++0x03 line.long 0x00 "DMA4_COLORi_14,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x5F4++0x03 line.long 0x00 "DMA4_CSACi_14,Channel Source Address Value" group.long 0x5D0++0x03 line.long 0x00 "DMA4_CSDPi_14,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x5E4++0x07 line.long 0x00 "DMA4_CSEIi_14,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_14,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x5CC++0x03 line.long 0x00 "DMA4_CSRi_14,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x5DC++0x03 line.long 0x00 "DMA4_CSSAi_14,Channel Source Start Address" tree.end tree "DMA_Channel_15" group.long 0x678++0x03 line.long 0x00 "DMA4_CCDNi_15," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x65C++0x07 line.long 0x00 "DMA4_CCENi_15,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_15,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x620++0x03 line.long 0x00 "DMA4_CCRi_15,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x658++0x03 line.long 0x00 "DMA4_CDACi_15,Channel Destination Address Value" group.long 0x64C++0x07 line.long 0x00 "DMA4_CDEIi_15,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_15,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x670++0x03 line.long 0x00 "DMA4_CDPi_15,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x640++0x03 line.long 0x00 "DMA4_CDSAi_15,Channel Destination Start Address" group.long 0x634++0x07 line.long 0x00 "DMA4_CENi_15,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_15,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x628++0x03 line.long 0x00 "DMA4_CICRi_15,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x624++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_15,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x674++0x03 line.long 0x00 "DMA4_CNDPi_15,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x664++0x03 line.long 0x00 "DMA4_COLORi_15,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x654++0x03 line.long 0x00 "DMA4_CSACi_15,Channel Source Address Value" group.long 0x630++0x03 line.long 0x00 "DMA4_CSDPi_15,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x644++0x07 line.long 0x00 "DMA4_CSEIi_15,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_15,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x62C++0x03 line.long 0x00 "DMA4_CSRi_15,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x63C++0x03 line.long 0x00 "DMA4_CSSAi_15,Channel Source Start Address" tree.end tree "DMA_Channel_16" group.long 0x6D8++0x03 line.long 0x00 "DMA4_CCDNi_16," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x6BC++0x07 line.long 0x00 "DMA4_CCENi_16,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_16,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x680++0x03 line.long 0x00 "DMA4_CCRi_16,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6B8++0x03 line.long 0x00 "DMA4_CDACi_16,Channel Destination Address Value" group.long 0x6AC++0x07 line.long 0x00 "DMA4_CDEIi_16,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_16,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x6D0++0x03 line.long 0x00 "DMA4_CDPi_16,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x6A0++0x03 line.long 0x00 "DMA4_CDSAi_16,Channel Destination Start Address" group.long 0x694++0x07 line.long 0x00 "DMA4_CENi_16,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_16,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x688++0x03 line.long 0x00 "DMA4_CICRi_16,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x684++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_16,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x6D4++0x03 line.long 0x00 "DMA4_CNDPi_16,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x6C4++0x03 line.long 0x00 "DMA4_COLORi_16,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x6B4++0x03 line.long 0x00 "DMA4_CSACi_16,Channel Source Address Value" group.long 0x690++0x03 line.long 0x00 "DMA4_CSDPi_16,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x6A4++0x07 line.long 0x00 "DMA4_CSEIi_16,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_16,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x68C++0x03 line.long 0x00 "DMA4_CSRi_16,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x69C++0x03 line.long 0x00 "DMA4_CSSAi_16,Channel Source Start Address" tree.end tree "DMA_Channel_17" group.long 0x738++0x03 line.long 0x00 "DMA4_CCDNi_17," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x71C++0x07 line.long 0x00 "DMA4_CCENi_17,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_17,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x6E0++0x03 line.long 0x00 "DMA4_CCRi_17,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x718++0x03 line.long 0x00 "DMA4_CDACi_17,Channel Destination Address Value" group.long 0x70C++0x07 line.long 0x00 "DMA4_CDEIi_17,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_17,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x730++0x03 line.long 0x00 "DMA4_CDPi_17,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x700++0x03 line.long 0x00 "DMA4_CDSAi_17,Channel Destination Start Address" group.long 0x6F4++0x07 line.long 0x00 "DMA4_CENi_17,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_17,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x6E8++0x03 line.long 0x00 "DMA4_CICRi_17,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x6E4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_17,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x734++0x03 line.long 0x00 "DMA4_CNDPi_17,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x724++0x03 line.long 0x00 "DMA4_COLORi_17,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x714++0x03 line.long 0x00 "DMA4_CSACi_17,Channel Source Address Value" group.long 0x6F0++0x03 line.long 0x00 "DMA4_CSDPi_17,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x704++0x07 line.long 0x00 "DMA4_CSEIi_17,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_17,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x6EC++0x03 line.long 0x00 "DMA4_CSRi_17,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x6FC++0x03 line.long 0x00 "DMA4_CSSAi_17,Channel Source Start Address" tree.end tree "DMA_Channel_18" group.long 0x798++0x03 line.long 0x00 "DMA4_CCDNi_18," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x77C++0x07 line.long 0x00 "DMA4_CCENi_18,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_18,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x740++0x03 line.long 0x00 "DMA4_CCRi_18,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x778++0x03 line.long 0x00 "DMA4_CDACi_18,Channel Destination Address Value" group.long 0x76C++0x07 line.long 0x00 "DMA4_CDEIi_18,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_18,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x790++0x03 line.long 0x00 "DMA4_CDPi_18,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x760++0x03 line.long 0x00 "DMA4_CDSAi_18,Channel Destination Start Address" group.long 0x754++0x07 line.long 0x00 "DMA4_CENi_18,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_18,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x748++0x03 line.long 0x00 "DMA4_CICRi_18,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x744++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_18,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x794++0x03 line.long 0x00 "DMA4_CNDPi_18,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x784++0x03 line.long 0x00 "DMA4_COLORi_18,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x774++0x03 line.long 0x00 "DMA4_CSACi_18,Channel Source Address Value" group.long 0x750++0x03 line.long 0x00 "DMA4_CSDPi_18,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x764++0x07 line.long 0x00 "DMA4_CSEIi_18,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_18,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x74C++0x03 line.long 0x00 "DMA4_CSRi_18,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x75C++0x03 line.long 0x00 "DMA4_CSSAi_18,Channel Source Start Address" tree.end tree "DMA_Channel_19" group.long 0x7F8++0x03 line.long 0x00 "DMA4_CCDNi_19," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x7DC++0x07 line.long 0x00 "DMA4_CCENi_19,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_19,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x7A0++0x03 line.long 0x00 "DMA4_CCRi_19,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7D8++0x03 line.long 0x00 "DMA4_CDACi_19,Channel Destination Address Value" group.long 0x7CC++0x07 line.long 0x00 "DMA4_CDEIi_19,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_19,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x7F0++0x03 line.long 0x00 "DMA4_CDPi_19,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x7C0++0x03 line.long 0x00 "DMA4_CDSAi_19,Channel Destination Start Address" group.long 0x7B4++0x07 line.long 0x00 "DMA4_CENi_19,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_19,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x7A8++0x03 line.long 0x00 "DMA4_CICRi_19,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x7A4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_19,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x7F4++0x03 line.long 0x00 "DMA4_CNDPi_19,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x7E4++0x03 line.long 0x00 "DMA4_COLORi_19,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x7D4++0x03 line.long 0x00 "DMA4_CSACi_19,Channel Source Address Value" group.long 0x7B0++0x03 line.long 0x00 "DMA4_CSDPi_19,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x7C4++0x07 line.long 0x00 "DMA4_CSEIi_19,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_19,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x7AC++0x03 line.long 0x00 "DMA4_CSRi_19,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x7BC++0x03 line.long 0x00 "DMA4_CSSAi_19,Channel Source Start Address" tree.end tree "DMA_Channel_2" group.long 0x198++0x03 line.long 0x00 "DMA4_CCDNi_2," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x17C++0x07 line.long 0x00 "DMA4_CCENi_2,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_2,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x140++0x03 line.long 0x00 "DMA4_CCRi_2,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x178++0x03 line.long 0x00 "DMA4_CDACi_2,Channel Destination Address Value" group.long 0x16C++0x07 line.long 0x00 "DMA4_CDEIi_2,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_2,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x190++0x03 line.long 0x00 "DMA4_CDPi_2,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x160++0x03 line.long 0x00 "DMA4_CDSAi_2,Channel Destination Start Address" group.long 0x154++0x07 line.long 0x00 "DMA4_CENi_2,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_2,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x148++0x03 line.long 0x00 "DMA4_CICRi_2,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x144++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_2,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x194++0x03 line.long 0x00 "DMA4_CNDPi_2,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x184++0x03 line.long 0x00 "DMA4_COLORi_2,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x174++0x03 line.long 0x00 "DMA4_CSACi_2,Channel Source Address Value" group.long 0x150++0x03 line.long 0x00 "DMA4_CSDPi_2,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x164++0x07 line.long 0x00 "DMA4_CSEIi_2,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_2,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x14C++0x03 line.long 0x00 "DMA4_CSRi_2,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x15C++0x03 line.long 0x00 "DMA4_CSSAi_2,Channel Source Start Address" group.long 0x20++0x03 line.long 0x00 "DMA4_IRQENABLE_Lj_2,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on line Lj" group.long 0x10++0x03 line.long 0x00 "DMA4_IRQSTATUS_Lj_2,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj" tree.end tree "DMA_Channel_20" group.long 0x858++0x03 line.long 0x00 "DMA4_CCDNi_20," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x83C++0x07 line.long 0x00 "DMA4_CCENi_20,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_20,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x800++0x03 line.long 0x00 "DMA4_CCRi_20,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x838++0x03 line.long 0x00 "DMA4_CDACi_20,Channel Destination Address Value" group.long 0x82C++0x07 line.long 0x00 "DMA4_CDEIi_20,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_20,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x850++0x03 line.long 0x00 "DMA4_CDPi_20,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x820++0x03 line.long 0x00 "DMA4_CDSAi_20,Channel Destination Start Address" group.long 0x814++0x07 line.long 0x00 "DMA4_CENi_20,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_20,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x808++0x03 line.long 0x00 "DMA4_CICRi_20,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x804++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_20,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x854++0x03 line.long 0x00 "DMA4_CNDPi_20,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x844++0x03 line.long 0x00 "DMA4_COLORi_20,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x834++0x03 line.long 0x00 "DMA4_CSACi_20,Channel Source Address Value" group.long 0x810++0x03 line.long 0x00 "DMA4_CSDPi_20,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x824++0x07 line.long 0x00 "DMA4_CSEIi_20,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_20,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x80C++0x03 line.long 0x00 "DMA4_CSRi_20,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x81C++0x03 line.long 0x00 "DMA4_CSSAi_20,Channel Source Start Address" tree.end tree "DMA_Channel_21" group.long 0x8B8++0x03 line.long 0x00 "DMA4_CCDNi_21," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x89C++0x07 line.long 0x00 "DMA4_CCENi_21,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_21,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x860++0x03 line.long 0x00 "DMA4_CCRi_21,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x898++0x03 line.long 0x00 "DMA4_CDACi_21,Channel Destination Address Value" group.long 0x88C++0x07 line.long 0x00 "DMA4_CDEIi_21,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_21,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x8B0++0x03 line.long 0x00 "DMA4_CDPi_21,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x880++0x03 line.long 0x00 "DMA4_CDSAi_21,Channel Destination Start Address" group.long 0x874++0x07 line.long 0x00 "DMA4_CENi_21,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_21,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x868++0x03 line.long 0x00 "DMA4_CICRi_21,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x864++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_21,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8B4++0x03 line.long 0x00 "DMA4_CNDPi_21,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x8A4++0x03 line.long 0x00 "DMA4_COLORi_21,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x894++0x03 line.long 0x00 "DMA4_CSACi_21,Channel Source Address Value" group.long 0x870++0x03 line.long 0x00 "DMA4_CSDPi_21,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x884++0x07 line.long 0x00 "DMA4_CSEIi_21,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_21,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x86C++0x03 line.long 0x00 "DMA4_CSRi_21,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x87C++0x03 line.long 0x00 "DMA4_CSSAi_21,Channel Source Start Address" tree.end tree "DMA_Channel_22" group.long 0x918++0x03 line.long 0x00 "DMA4_CCDNi_22," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x8FC++0x07 line.long 0x00 "DMA4_CCENi_22,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_22,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x8C0++0x03 line.long 0x00 "DMA4_CCRi_22,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x8F8++0x03 line.long 0x00 "DMA4_CDACi_22,Channel Destination Address Value" group.long 0x8EC++0x07 line.long 0x00 "DMA4_CDEIi_22,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_22,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x910++0x03 line.long 0x00 "DMA4_CDPi_22,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x8E0++0x03 line.long 0x00 "DMA4_CDSAi_22,Channel Destination Start Address" group.long 0x8D4++0x07 line.long 0x00 "DMA4_CENi_22,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_22,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x8C8++0x03 line.long 0x00 "DMA4_CICRi_22,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x8C4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_22,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x914++0x03 line.long 0x00 "DMA4_CNDPi_22,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x904++0x03 line.long 0x00 "DMA4_COLORi_22,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x8F4++0x03 line.long 0x00 "DMA4_CSACi_22,Channel Source Address Value" group.long 0x8D0++0x03 line.long 0x00 "DMA4_CSDPi_22,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x8E4++0x07 line.long 0x00 "DMA4_CSEIi_22,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_22,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x8CC++0x03 line.long 0x00 "DMA4_CSRi_22,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x8DC++0x03 line.long 0x00 "DMA4_CSSAi_22,Channel Source Start Address" tree.end tree "DMA_Channel_23" group.long 0x978++0x03 line.long 0x00 "DMA4_CCDNi_23," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x95C++0x07 line.long 0x00 "DMA4_CCENi_23,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_23,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x920++0x03 line.long 0x00 "DMA4_CCRi_23,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x958++0x03 line.long 0x00 "DMA4_CDACi_23,Channel Destination Address Value" group.long 0x94C++0x07 line.long 0x00 "DMA4_CDEIi_23,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_23,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x970++0x03 line.long 0x00 "DMA4_CDPi_23,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x940++0x03 line.long 0x00 "DMA4_CDSAi_23,Channel Destination Start Address" group.long 0x934++0x07 line.long 0x00 "DMA4_CENi_23,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_23,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x928++0x03 line.long 0x00 "DMA4_CICRi_23,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x924++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_23,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x974++0x03 line.long 0x00 "DMA4_CNDPi_23,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x964++0x03 line.long 0x00 "DMA4_COLORi_23,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x954++0x03 line.long 0x00 "DMA4_CSACi_23,Channel Source Address Value" group.long 0x930++0x03 line.long 0x00 "DMA4_CSDPi_23,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x944++0x07 line.long 0x00 "DMA4_CSEIi_23,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_23,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x92C++0x03 line.long 0x00 "DMA4_CSRi_23,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x93C++0x03 line.long 0x00 "DMA4_CSSAi_23,Channel Source Start Address" tree.end tree "DMA_Channel_24" group.long 0x9D8++0x03 line.long 0x00 "DMA4_CCDNi_24," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x9BC++0x07 line.long 0x00 "DMA4_CCENi_24,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_24,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x980++0x03 line.long 0x00 "DMA4_CCRi_24,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x9B8++0x03 line.long 0x00 "DMA4_CDACi_24,Channel Destination Address Value" group.long 0x9AC++0x07 line.long 0x00 "DMA4_CDEIi_24,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_24,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x9D0++0x03 line.long 0x00 "DMA4_CDPi_24,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x9A0++0x03 line.long 0x00 "DMA4_CDSAi_24,Channel Destination Start Address" group.long 0x994++0x07 line.long 0x00 "DMA4_CENi_24,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_24,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x988++0x03 line.long 0x00 "DMA4_CICRi_24,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x984++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_24,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x9D4++0x03 line.long 0x00 "DMA4_CNDPi_24,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x9C4++0x03 line.long 0x00 "DMA4_COLORi_24,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x9B4++0x03 line.long 0x00 "DMA4_CSACi_24,Channel Source Address Value" group.long 0x990++0x03 line.long 0x00 "DMA4_CSDPi_24,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x9A4++0x07 line.long 0x00 "DMA4_CSEIi_24,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_24,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x98C++0x03 line.long 0x00 "DMA4_CSRi_24,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x99C++0x03 line.long 0x00 "DMA4_CSSAi_24,Channel Source Start Address" tree.end tree "DMA_Channel_25" group.long 0xA38++0x03 line.long 0x00 "DMA4_CCDNi_25," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xA1C++0x07 line.long 0x00 "DMA4_CCENi_25,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_25,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x9E0++0x03 line.long 0x00 "DMA4_CCRi_25,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA18++0x03 line.long 0x00 "DMA4_CDACi_25,Channel Destination Address Value" group.long 0xA0C++0x07 line.long 0x00 "DMA4_CDEIi_25,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_25,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xA30++0x03 line.long 0x00 "DMA4_CDPi_25,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xA00++0x03 line.long 0x00 "DMA4_CDSAi_25,Channel Destination Start Address" group.long 0x9F4++0x07 line.long 0x00 "DMA4_CENi_25,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_25,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x9E8++0x03 line.long 0x00 "DMA4_CICRi_25,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x9E4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_25,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA34++0x03 line.long 0x00 "DMA4_CNDPi_25,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xA24++0x03 line.long 0x00 "DMA4_COLORi_25,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xA14++0x03 line.long 0x00 "DMA4_CSACi_25,Channel Source Address Value" group.long 0x9F0++0x03 line.long 0x00 "DMA4_CSDPi_25,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xA04++0x07 line.long 0x00 "DMA4_CSEIi_25,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_25,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x9EC++0x03 line.long 0x00 "DMA4_CSRi_25,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x9FC++0x03 line.long 0x00 "DMA4_CSSAi_25,Channel Source Start Address" tree.end tree "DMA_Channel_26" group.long 0xA98++0x03 line.long 0x00 "DMA4_CCDNi_26," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xA7C++0x07 line.long 0x00 "DMA4_CCENi_26,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_26,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xA40++0x03 line.long 0x00 "DMA4_CCRi_26,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA78++0x03 line.long 0x00 "DMA4_CDACi_26,Channel Destination Address Value" group.long 0xA6C++0x07 line.long 0x00 "DMA4_CDEIi_26,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_26,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xA90++0x03 line.long 0x00 "DMA4_CDPi_26,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xA60++0x03 line.long 0x00 "DMA4_CDSAi_26,Channel Destination Start Address" group.long 0xA54++0x07 line.long 0x00 "DMA4_CENi_26,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_26,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xA48++0x03 line.long 0x00 "DMA4_CICRi_26,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xA44++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_26,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA94++0x03 line.long 0x00 "DMA4_CNDPi_26,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xA84++0x03 line.long 0x00 "DMA4_COLORi_26,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xA74++0x03 line.long 0x00 "DMA4_CSACi_26,Channel Source Address Value" group.long 0xA50++0x03 line.long 0x00 "DMA4_CSDPi_26,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xA64++0x07 line.long 0x00 "DMA4_CSEIi_26,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_26,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xA4C++0x03 line.long 0x00 "DMA4_CSRi_26,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xA5C++0x03 line.long 0x00 "DMA4_CSSAi_26,Channel Source Start Address" tree.end tree "DMA_Channel_27" group.long 0xAF8++0x03 line.long 0x00 "DMA4_CCDNi_27," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xADC++0x07 line.long 0x00 "DMA4_CCENi_27,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_27,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xAA0++0x03 line.long 0x00 "DMA4_CCRi_27,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAD8++0x03 line.long 0x00 "DMA4_CDACi_27,Channel Destination Address Value" group.long 0xACC++0x07 line.long 0x00 "DMA4_CDEIi_27,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_27,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xAF0++0x03 line.long 0x00 "DMA4_CDPi_27,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xAC0++0x03 line.long 0x00 "DMA4_CDSAi_27,Channel Destination Start Address" group.long 0xAB4++0x07 line.long 0x00 "DMA4_CENi_27,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_27,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xAA8++0x03 line.long 0x00 "DMA4_CICRi_27,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xAA4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_27,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAF4++0x03 line.long 0x00 "DMA4_CNDPi_27,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xAE4++0x03 line.long 0x00 "DMA4_COLORi_27,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xAD4++0x03 line.long 0x00 "DMA4_CSACi_27,Channel Source Address Value" group.long 0xAB0++0x03 line.long 0x00 "DMA4_CSDPi_27,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xAC4++0x07 line.long 0x00 "DMA4_CSEIi_27,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_27,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xAAC++0x03 line.long 0x00 "DMA4_CSRi_27,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xABC++0x03 line.long 0x00 "DMA4_CSSAi_27,Channel Source Start Address" tree.end tree "DMA_Channel_28" group.long 0xB58++0x03 line.long 0x00 "DMA4_CCDNi_28," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xB3C++0x07 line.long 0x00 "DMA4_CCENi_28,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_28,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xB00++0x03 line.long 0x00 "DMA4_CCRi_28,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB38++0x03 line.long 0x00 "DMA4_CDACi_28,Channel Destination Address Value" group.long 0xB2C++0x07 line.long 0x00 "DMA4_CDEIi_28,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_28,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xB50++0x03 line.long 0x00 "DMA4_CDPi_28,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xB20++0x03 line.long 0x00 "DMA4_CDSAi_28,Channel Destination Start Address" group.long 0xB14++0x07 line.long 0x00 "DMA4_CENi_28,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_28,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xB08++0x03 line.long 0x00 "DMA4_CICRi_28,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xB04++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_28,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB54++0x03 line.long 0x00 "DMA4_CNDPi_28,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xB44++0x03 line.long 0x00 "DMA4_COLORi_28,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xB34++0x03 line.long 0x00 "DMA4_CSACi_28,Channel Source Address Value" group.long 0xB10++0x03 line.long 0x00 "DMA4_CSDPi_28,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xB24++0x07 line.long 0x00 "DMA4_CSEIi_28,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_28,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xB0C++0x03 line.long 0x00 "DMA4_CSRi_28,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xB1C++0x03 line.long 0x00 "DMA4_CSSAi_28,Channel Source Start Address" tree.end tree "DMA_Channel_29" group.long 0xBB8++0x03 line.long 0x00 "DMA4_CCDNi_29," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xB9C++0x07 line.long 0x00 "DMA4_CCENi_29,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_29,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xB60++0x03 line.long 0x00 "DMA4_CCRi_29,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB98++0x03 line.long 0x00 "DMA4_CDACi_29,Channel Destination Address Value" group.long 0xB8C++0x07 line.long 0x00 "DMA4_CDEIi_29,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_29,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xBB0++0x03 line.long 0x00 "DMA4_CDPi_29,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xB80++0x03 line.long 0x00 "DMA4_CDSAi_29,Channel Destination Start Address" group.long 0xB74++0x07 line.long 0x00 "DMA4_CENi_29,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_29,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xB68++0x03 line.long 0x00 "DMA4_CICRi_29,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xB64++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_29,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xBB4++0x03 line.long 0x00 "DMA4_CNDPi_29,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xBA4++0x03 line.long 0x00 "DMA4_COLORi_29,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xB94++0x03 line.long 0x00 "DMA4_CSACi_29,Channel Source Address Value" group.long 0xB70++0x03 line.long 0x00 "DMA4_CSDPi_29,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xB84++0x07 line.long 0x00 "DMA4_CSEIi_29,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_29,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xB6C++0x03 line.long 0x00 "DMA4_CSRi_29,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xB7C++0x03 line.long 0x00 "DMA4_CSSAi_29,Channel Source Start Address" tree.end tree "DMA_Channel_3" group.long 0x1F8++0x03 line.long 0x00 "DMA4_CCDNi_3," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x1DC++0x07 line.long 0x00 "DMA4_CCENi_3,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_3,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x1A0++0x03 line.long 0x00 "DMA4_CCRi_3,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1D8++0x03 line.long 0x00 "DMA4_CDACi_3,Channel Destination Address Value" group.long 0x1CC++0x07 line.long 0x00 "DMA4_CDEIi_3,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_3,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x1F0++0x03 line.long 0x00 "DMA4_CDPi_3,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x1C0++0x03 line.long 0x00 "DMA4_CDSAi_3,Channel Destination Start Address" group.long 0x1B4++0x07 line.long 0x00 "DMA4_CENi_3,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_3,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x1A8++0x03 line.long 0x00 "DMA4_CICRi_3,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x1A4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_3,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1F4++0x03 line.long 0x00 "DMA4_CNDPi_3,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x1E4++0x03 line.long 0x00 "DMA4_COLORi_3,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x1D4++0x03 line.long 0x00 "DMA4_CSACi_3,Channel Source Address Value" group.long 0x1B0++0x03 line.long 0x00 "DMA4_CSDPi_3,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x1C4++0x07 line.long 0x00 "DMA4_CSEIi_3,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_3,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x1AC++0x03 line.long 0x00 "DMA4_CSRi_3,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x1BC++0x03 line.long 0x00 "DMA4_CSSAi_3,Channel Source Start Address" group.long 0x24++0x03 line.long 0x00 "DMA4_IRQENABLE_Lj_3,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on line Lj" group.long 0x14++0x03 line.long 0x00 "DMA4_IRQSTATUS_Lj_3,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj" tree.end tree "DMA_Channel_30" group.long 0xC18++0x03 line.long 0x00 "DMA4_CCDNi_30," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xBFC++0x07 line.long 0x00 "DMA4_CCENi_30,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_30,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xBC0++0x03 line.long 0x00 "DMA4_CCRi_30,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xBF8++0x03 line.long 0x00 "DMA4_CDACi_30,Channel Destination Address Value" group.long 0xBEC++0x07 line.long 0x00 "DMA4_CDEIi_30,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_30,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xC10++0x03 line.long 0x00 "DMA4_CDPi_30,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xBE0++0x03 line.long 0x00 "DMA4_CDSAi_30,Channel Destination Start Address" group.long 0xBD4++0x07 line.long 0x00 "DMA4_CENi_30,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_30,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xBC8++0x03 line.long 0x00 "DMA4_CICRi_30,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xBC4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_30,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC14++0x03 line.long 0x00 "DMA4_CNDPi_30,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC04++0x03 line.long 0x00 "DMA4_COLORi_30,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xBF4++0x03 line.long 0x00 "DMA4_CSACi_30,Channel Source Address Value" group.long 0xBD0++0x03 line.long 0x00 "DMA4_CSDPi_30,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xBE4++0x07 line.long 0x00 "DMA4_CSEIi_30,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_30,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xBCC++0x03 line.long 0x00 "DMA4_CSRi_30,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xBDC++0x03 line.long 0x00 "DMA4_CSSAi_30,Channel Source Start Address" tree.end tree "DMA_Channel_31" group.long 0xC78++0x03 line.long 0x00 "DMA4_CCDNi_31," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xC5C++0x07 line.long 0x00 "DMA4_CCENi_31,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_31,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0xC20++0x03 line.long 0x00 "DMA4_CCRi_31,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC58++0x03 line.long 0x00 "DMA4_CDACi_31,Channel Destination Address Value" group.long 0xC4C++0x07 line.long 0x00 "DMA4_CDEIi_31,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_31,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xC70++0x03 line.long 0x00 "DMA4_CDPi_31,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xC40++0x03 line.long 0x00 "DMA4_CDSAi_31,Channel Destination Start Address" group.long 0xC34++0x07 line.long 0x00 "DMA4_CENi_31,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_31,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0xC28++0x03 line.long 0x00 "DMA4_CICRi_31,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0xC24++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_31,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC74++0x03 line.long 0x00 "DMA4_CNDPi_31,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC64++0x03 line.long 0x00 "DMA4_COLORi_31,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xC54++0x03 line.long 0x00 "DMA4_CSACi_31,Channel Source Address Value" group.long 0xC30++0x03 line.long 0x00 "DMA4_CSDPi_31,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xC44++0x07 line.long 0x00 "DMA4_CSEIi_31,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_31,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0xC2C++0x03 line.long 0x00 "DMA4_CSRi_31,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0xC3C++0x03 line.long 0x00 "DMA4_CSSAi_31,Channel Source Start Address" tree.end tree "DMA_Channel_4" group.long 0x258++0x03 line.long 0x00 "DMA4_CCDNi_4," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x23C++0x07 line.long 0x00 "DMA4_CCENi_4,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_4,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x200++0x03 line.long 0x00 "DMA4_CCRi_4,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x238++0x03 line.long 0x00 "DMA4_CDACi_4,Channel Destination Address Value" group.long 0x22C++0x07 line.long 0x00 "DMA4_CDEIi_4,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_4,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x250++0x03 line.long 0x00 "DMA4_CDPi_4,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x220++0x03 line.long 0x00 "DMA4_CDSAi_4,Channel Destination Start Address" group.long 0x214++0x07 line.long 0x00 "DMA4_CENi_4,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_4,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x208++0x03 line.long 0x00 "DMA4_CICRi_4,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x204++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_4,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x254++0x03 line.long 0x00 "DMA4_CNDPi_4,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x244++0x03 line.long 0x00 "DMA4_COLORi_4,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x234++0x03 line.long 0x00 "DMA4_CSACi_4,Channel Source Address Value" group.long 0x210++0x03 line.long 0x00 "DMA4_CSDPi_4,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x224++0x07 line.long 0x00 "DMA4_CSEIi_4,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_4,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x20C++0x03 line.long 0x00 "DMA4_CSRi_4,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x21C++0x03 line.long 0x00 "DMA4_CSSAi_4,Channel Source Start Address" tree.end tree "DMA_Channel_5" group.long 0x2B8++0x03 line.long 0x00 "DMA4_CCDNi_5," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x29C++0x07 line.long 0x00 "DMA4_CCENi_5,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_5,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x260++0x03 line.long 0x00 "DMA4_CCRi_5,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x298++0x03 line.long 0x00 "DMA4_CDACi_5,Channel Destination Address Value" group.long 0x28C++0x07 line.long 0x00 "DMA4_CDEIi_5,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_5,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x2B0++0x03 line.long 0x00 "DMA4_CDPi_5,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x280++0x03 line.long 0x00 "DMA4_CDSAi_5,Channel Destination Start Address" group.long 0x274++0x07 line.long 0x00 "DMA4_CENi_5,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_5,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x268++0x03 line.long 0x00 "DMA4_CICRi_5,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x264++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_5,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2B4++0x03 line.long 0x00 "DMA4_CNDPi_5,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x2A4++0x03 line.long 0x00 "DMA4_COLORi_5,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x294++0x03 line.long 0x00 "DMA4_CSACi_5,Channel Source Address Value" group.long 0x270++0x03 line.long 0x00 "DMA4_CSDPi_5,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x284++0x07 line.long 0x00 "DMA4_CSEIi_5,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_5,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x26C++0x03 line.long 0x00 "DMA4_CSRi_5,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x27C++0x03 line.long 0x00 "DMA4_CSSAi_5,Channel Source Start Address" tree.end tree "DMA_Channel_6" group.long 0x318++0x03 line.long 0x00 "DMA4_CCDNi_6," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x2FC++0x07 line.long 0x00 "DMA4_CCENi_6,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_6,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x2C0++0x03 line.long 0x00 "DMA4_CCRi_6,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2F8++0x03 line.long 0x00 "DMA4_CDACi_6,Channel Destination Address Value" group.long 0x2EC++0x07 line.long 0x00 "DMA4_CDEIi_6,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_6,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x310++0x03 line.long 0x00 "DMA4_CDPi_6,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x2E0++0x03 line.long 0x00 "DMA4_CDSAi_6,Channel Destination Start Address" group.long 0x2D4++0x07 line.long 0x00 "DMA4_CENi_6,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_6,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x2C8++0x03 line.long 0x00 "DMA4_CICRi_6,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x2C4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_6,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x314++0x03 line.long 0x00 "DMA4_CNDPi_6,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x304++0x03 line.long 0x00 "DMA4_COLORi_6,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x2F4++0x03 line.long 0x00 "DMA4_CSACi_6,Channel Source Address Value" group.long 0x2D0++0x03 line.long 0x00 "DMA4_CSDPi_6,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x2E4++0x07 line.long 0x00 "DMA4_CSEIi_6,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_6,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x2CC++0x03 line.long 0x00 "DMA4_CSRi_6,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x2DC++0x03 line.long 0x00 "DMA4_CSSAi_6,Channel Source Start Address" tree.end tree "DMA_Channel_7" group.long 0x378++0x03 line.long 0x00 "DMA4_CCDNi_7," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x35C++0x07 line.long 0x00 "DMA4_CCENi_7,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_7,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x320++0x03 line.long 0x00 "DMA4_CCRi_7,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x358++0x03 line.long 0x00 "DMA4_CDACi_7,Channel Destination Address Value" group.long 0x34C++0x07 line.long 0x00 "DMA4_CDEIi_7,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_7,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x370++0x03 line.long 0x00 "DMA4_CDPi_7,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x340++0x03 line.long 0x00 "DMA4_CDSAi_7,Channel Destination Start Address" group.long 0x334++0x07 line.long 0x00 "DMA4_CENi_7,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_7,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x328++0x03 line.long 0x00 "DMA4_CICRi_7,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x324++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_7,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x374++0x03 line.long 0x00 "DMA4_CNDPi_7,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x364++0x03 line.long 0x00 "DMA4_COLORi_7,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x354++0x03 line.long 0x00 "DMA4_CSACi_7,Channel Source Address Value" group.long 0x330++0x03 line.long 0x00 "DMA4_CSDPi_7,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x344++0x07 line.long 0x00 "DMA4_CSEIi_7,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_7,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x32C++0x03 line.long 0x00 "DMA4_CSRi_7,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x33C++0x03 line.long 0x00 "DMA4_CSSAi_7,Channel Source Start Address" tree.end tree "DMA_Channel_8" group.long 0x3D8++0x03 line.long 0x00 "DMA4_CCDNi_8," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x3BC++0x07 line.long 0x00 "DMA4_CCENi_8,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_8,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x380++0x03 line.long 0x00 "DMA4_CCRi_8,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3B8++0x03 line.long 0x00 "DMA4_CDACi_8,Channel Destination Address Value" group.long 0x3AC++0x07 line.long 0x00 "DMA4_CDEIi_8,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_8,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x3D0++0x03 line.long 0x00 "DMA4_CDPi_8,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x3A0++0x03 line.long 0x00 "DMA4_CDSAi_8,Channel Destination Start Address" group.long 0x394++0x07 line.long 0x00 "DMA4_CENi_8,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_8,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x388++0x03 line.long 0x00 "DMA4_CICRi_8,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x384++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_8,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3D4++0x03 line.long 0x00 "DMA4_CNDPi_8,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x3C4++0x03 line.long 0x00 "DMA4_COLORi_8,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x3B4++0x03 line.long 0x00 "DMA4_CSACi_8,Channel Source Address Value" group.long 0x390++0x03 line.long 0x00 "DMA4_CSDPi_8,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x3A4++0x07 line.long 0x00 "DMA4_CSEIi_8,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_8,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x38C++0x03 line.long 0x00 "DMA4_CSRi_8,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x39C++0x03 line.long 0x00 "DMA4_CSSAi_8,Channel Source Start Address" tree.end tree "DMA_Channel_9" group.long 0x438++0x03 line.long 0x00 "DMA4_CCDNi_9," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x41C++0x07 line.long 0x00 "DMA4_CCENi_9,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_9,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x3E0++0x03 line.long 0x00 "DMA4_CCRi_9,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" newline bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" newline bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" newline bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" newline bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" newline bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" newline rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" newline bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" newline bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "An entire frame is transferred once a DMA..,A packet is transferred once a DMA request is made" newline bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x418++0x03 line.long 0x00 "DMA4_CDACi_9,Channel Destination Address Value" group.long 0x40C++0x07 line.long 0x00 "DMA4_CDEIi_9,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_9,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x430++0x03 line.long 0x00 "DMA4_CDPi_9,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" newline bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" newline bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" newline bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x400++0x03 line.long 0x00 "DMA4_CDSAi_9,Channel Destination Start Address" group.long 0x3F4++0x07 line.long 0x00 "DMA4_CENi_9,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_9,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x3E8++0x03 line.long 0x00 "DMA4_CICRi_9,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" newline bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" newline bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" newline bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" newline bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" newline bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x3E4++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_9,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" newline bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x434++0x03 line.long 0x00 "DMA4_CNDPi_9,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x424++0x03 line.long 0x00 "DMA4_COLORi_9,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x414++0x03 line.long 0x00 "DMA4_CSACi_9,Channel Source Address Value" group.long 0x3F0++0x03 line.long 0x00 "DMA4_CSDPi_9,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" newline bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" newline bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" newline bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" newline bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" newline bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x404++0x07 line.long 0x00 "DMA4_CSEIi_9,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_9,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x3EC++0x03 line.long 0x00 "DMA4_CSRi_9,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "Status bit unchanged,Status bit is reset" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" newline bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" newline bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" newline bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" newline bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" newline bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x3FC++0x03 line.long 0x00 "DMA4_CSSAi_9,Channel Source Start Address" tree.end width 0x0B tree.end tree "UART_IrDA_CIR" repeat 3. (list 3. 1. 2. )(list ad:0x48020000 ad:0x4806A000 ad:0x4806C000 ) tree "UART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UART_DLL,This register. with. stores the 14-bit divisor for generation of the baud clock in the baud rate generator" hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x00++0x03 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register" hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register" group.long 0x00++0x07 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register" hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register" line.long 0x04 "UART_DLH,This register. with. stores the 14-bit divisor for generating the baud clock in the baud rate generator" bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. "CTS_IT," "CTS_IT_0,CTS_IT_1" newline bitfld.long 0x00 6. "RTS_IT," "RTS_IT_0,RTS_IT_1" newline bitfld.long 0x00 5. "XOFF_IT," "XOFF_IT_0,XOFF_IT_1" newline bitfld.long 0x00 4. "SLEEP_MODE," "SLEEP_MODE_0,SLEEP_MODE_1" newline bitfld.long 0x00 3. "MODEM_STS_IT," "MODEM_STS_IT_0,MODEM_STS_IT_1" newline bitfld.long 0x00 2. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" group.long 0x04++0x03 line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually" bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0,TX_STATUS_IT_1" newline bitfld.long 0x00 3. "RX_OVERRUN_IT," "RX_OVERRUN_IT_0,RX_OVERRUN_IT_1" newline bitfld.long 0x00 2. "RX_STOP_IT," "RX_STOP_IT_0,RX_STOP_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" group.long 0x04++0x07 line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually" bitfld.long 0x00 7. "EOF_IT," "EOF_IT_0,EOF_IT_1" newline bitfld.long 0x00 6. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0,TX_STATUS_IT_1" newline bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "STS_FIFO_TRIG_IT_0,STS_FIFO_TRIG_IT_1" newline bitfld.long 0x00 3. "RX_OVERRUN_IT," "RX_OVERRUN_IT_0,RX_OVERRUN_IT_1" newline bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "LAST_RX_BYTE_IT_0,LAST_RX_BYTE_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" line.long 0x04 "UART_EFR,Enhanced feature register" bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1" newline bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1" newline bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1" newline bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1" newline bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "SW_FLOW_CONTROL_0,SW_FLOW_CONTROL_1,SW_FLOW_CONTROL_2,SW_FLOW_CONTROL_3,SW_FLOW_CONTROL_4,SW_FLOW_CONTROL_5,SW_FLOW_CONTROL_6,SW_FLOW_CONTROL_7,SW_FLOW_CONTROL_8,SW_FLOW_CONTROL_9,SW_FLOW_CONTROL_10,SW_FLOW_CONTROL_11,SW_FLOW_CONTROL_12,SW_FLOW_CONTROL_13,SW_FLOW_CONTROL_14,SW_FLOW_CONTROL_15" group.long 0x08++0x03 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If UART_SCR[7] = 0 and.." newline bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If UART_SCR[6].." newline bitfld.long 0x00 3. "DMA_MODE,This register is considered ifUART_SCR[0] = 0" "DMA_MODE_0_w,DMA_MODE_1_w" newline bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0_w,TX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0_w,RX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0_w,FIFO_EN_1_w" rgroup.long 0x08++0x03 line.long 0x00 "UART_IIR,Interrupt identification register" bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents ofUART_FCR[0] on both bits" "FCR_MIRROR_0,FCR_MIRROR_1,FCR_MIRROR_2,FCR_MIRROR_3" newline bitfld.long 0x00 1.--5. "IT_TYPE," "Modem interrupt,?,?,?,,?..." newline bitfld.long 0x00 0. "IT_PENDING," "?,IT_PENDING_1_r" rgroup.long 0x08++0x03 line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active" bitfld.long 0x00 5. "TX_STATUS_IT," "?,TX_STATUS_IT_1_r" newline bitfld.long 0x00 3. "RX_OE_IT," "?,RX_OE_IT_1_r" newline bitfld.long 0x00 2. "RX_STOP_IT," "?,RX_STOP_IT_1_r" newline bitfld.long 0x00 1. "THR_IT," "?,THR_IT_1_r" newline bitfld.long 0x00 0. "RHR_IT," "?,RHR_IT_1_r" rgroup.long 0x08++0x0B line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active" bitfld.long 0x00 7. "EOF_IT," "EOF_IT_0_r,EOF_IT_1_r" newline bitfld.long 0x00 6. "LINE_STS_IT," "LINE_STS_IT_0_r,LINE_STS_IT_1_r" newline bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0_r,TX_STATUS_IT_1_r" newline bitfld.long 0x00 4. "STS_FIFO_IT," "STS_FIFO_IT_0_r,STS_FIFO_IT_1_r" newline bitfld.long 0x00 3. "RX_OE_IT," "RX_OE_IT_0_r,RX_OE_IT_1_r" newline bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "RX_FIFO_LAST_BYTE_IT_0_r,RX_FIFO_LAST_BYTE_IT_1_r" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0_r,THR_IT_1_r" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0_r,RHR_IT_1_r" line.long 0x04 "UART_LCR,Line control register" bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1" newline bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1" newline bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (ifUART_LCR[3] = 1)" "PARITY_TYPE2_0,PARITY_TYPE2_1" newline bitfld.long 0x04 4. "PARITY_TYPE1," "PARITY_TYPE1_0,PARITY_TYPE1_1" newline bitfld.long 0x04 3. "PARITY_EN," "?,PARITY_EN_1" newline bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1" newline bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3" line.long 0x08 "UART_MCR,Modem control register" bitfld.long 0x08 6. "TCR_TLR," "?,TCR_TLR_1" newline bitfld.long 0x08 5. "XON_EN," "?,XON_EN_1" newline bitfld.long 0x08 4. "LOOPBACK_EN," "?,LOOPBACK_EN_1" newline bitfld.long 0x08 3. "CD_STS_CH," "?,CD_STS_CH_1" newline bitfld.long 0x08 2. "RI_STS_CH," "?,RI_STS_CH_1" newline bitfld.long 0x08 1. "RTS,In loopback controls theUART_MSR[4] bit" "RTS_0,RTS_1" newline bitfld.long 0x08 0. "DTR," "?,DTR_1" group.long 0x10++0x07 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" line.long 0x04 "UART_LSR,Line status register" bitfld.long 0x04 7. "RX_FIFO_STS," "?,RX_FIFO_STS_1_r" newline bitfld.long 0x04 6. "TX_SR_E," "?,TX_SR_E_1_r" newline bitfld.long 0x04 5. "TX_FIFO_E," "?,TX_FIFO_E_1_r" newline bitfld.long 0x04 4. "RX_BI," "?,RX_BI_1_r" newline bitfld.long 0x04 3. "RX_FE," "?,RX_FE_1_r" newline bitfld.long 0x04 2. "RX_PE," "?,RX_PE_1_r" newline bitfld.long 0x04 1. "RX_OE," "?,RX_OE_1_r" newline bitfld.long 0x04 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" rgroup.long 0x14++0x03 line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode" bitfld.long 0x00 7. "THR_EMPTY," "?,THR_EMPTY_1_r" newline bitfld.long 0x00 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR)" "RX_STOP_0_r,RX_STOP_1_r" newline bitfld.long 0x00 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" rgroup.long 0x14++0x03 line.long 0x00 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)" bitfld.long 0x00 7. "THR_EMPTY," "?,THR_EMPTY_1_r" newline bitfld.long 0x00 6. "STS_FIFO_FULL," "?,STS_FIFO_FULL_1_r" newline bitfld.long 0x00 5. "RX_LAST_BYTE," "?,RX_LAST_BYTE_1_r" newline bitfld.long 0x00 4. "FRAME_TOO_LONG," "?,FRAME_TOO_LONG_1_r" newline bitfld.long 0x00 3. "ABORT," "?,ABORT_1_r" newline bitfld.long 0x00 2. "CRC," "?,CRC_1_r" newline bitfld.long 0x00 1. "STS_FIFO_E," "?,STS_FIFO_E_1_r" newline bitfld.long 0x00 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" group.long 0x14++0x07 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" line.long 0x04 "UART_MSR,Modem status register" bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1" newline bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1" newline bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1" newline bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1" newline bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (orUART_MCR[3] in loopback) changed" "0,1" newline bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high" "0,1" newline bitfld.long 0x04 1. "DSR_STS," "?,DSR_STS_1_r" newline bitfld.long 0x04 0. "CTS_STS," "?,CTS_STS_1_r" group.long 0x18++0x03 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "RX_FIFO_TRIG_START_0,RX_FIFO_TRIG_START_1,RX_FIFO_TRIG_START_2,RX_FIFO_TRIG_START_3,RX_FIFO_TRIG_START_4,RX_FIFO_TRIG_START_5,RX_FIFO_TRIG_START_6,RX_FIFO_TRIG_START_7,RX_FIFO_TRIG_START_8,RX_FIFO_TRIG_START_9,RX_FIFO_TRIG_START_10,RX_FIFO_TRIG_START_11,RX_FIFO_TRIG_START_12,RX_FIFO_TRIG_START_13,RX_FIFO_TRIG_START_14,RX_FIFO_TRIG_START_15" newline bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "RX_FIFO_TRIG_HALT_0,RX_FIFO_TRIG_HALT_1,RX_FIFO_TRIG_HALT_2,RX_FIFO_TRIG_HALT_3,RX_FIFO_TRIG_HALT_4,RX_FIFO_TRIG_HALT_5,RX_FIFO_TRIG_HALT_6,RX_FIFO_TRIG_HALT_7,RX_FIFO_TRIG_HALT_8,RX_FIFO_TRIG_HALT_9,RX_FIFO_TRIG_HALT_10,RX_FIFO_TRIG_HALT_11,RX_FIFO_TRIG_HALT_12,RX_FIFO_TRIG_HALT_13,RX_FIFO_TRIG_HALT_14,RX_FIFO_TRIG_HALT_15" group.long 0x18++0x07 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x04 "UART_SPR,Scratchpad register" hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x03 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "RX_FIFO_TRIG_DMA_0,RX_FIFO_TRIG_DMA_1,RX_FIFO_TRIG_DMA_2,RX_FIFO_TRIG_DMA_3,RX_FIFO_TRIG_DMA_4,RX_FIFO_TRIG_DMA_5,RX_FIFO_TRIG_DMA_6,RX_FIFO_TRIG_DMA_7,RX_FIFO_TRIG_DMA_8,RX_FIFO_TRIG_DMA_9,RX_FIFO_TRIG_DMA_10,RX_FIFO_TRIG_DMA_11,RX_FIFO_TRIG_DMA_12,RX_FIFO_TRIG_DMA_13,RX_FIFO_TRIG_DMA_14,RX_FIFO_TRIG_DMA_15" newline bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "TX_FIFO_TRIG_DMA_0,TX_FIFO_TRIG_DMA_1,TX_FIFO_TRIG_DMA_2,TX_FIFO_TRIG_DMA_3,TX_FIFO_TRIG_DMA_4,TX_FIFO_TRIG_DMA_5,TX_FIFO_TRIG_DMA_6,TX_FIFO_TRIG_DMA_7,TX_FIFO_TRIG_DMA_8,TX_FIFO_TRIG_DMA_9,TX_FIFO_TRIG_DMA_10,TX_FIFO_TRIG_DMA_11,TX_FIFO_TRIG_DMA_12,TX_FIFO_TRIG_DMA_13,TX_FIFO_TRIG_DMA_14,TX_FIFO_TRIG_DMA_15" group.long 0x1C++0x0F line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes" line.long 0x04 "UART_MDR1,Mode definition register 1" bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "FRAME_END_MODE_0,FRAME_END_MODE_1" newline bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "SIP_MODE_0,SIP_MODE_1" newline bitfld.long 0x04 5. "SCT,Store and control the transmission" "SCT_0,SCT_1" newline bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "SET_TXIR_0,SET_TXIR_1" newline bitfld.long 0x04 3. "IR_SLEEP," "?,IR_SLEEP_1" newline bitfld.long 0x04 0.--2. "MODE_SELECT," "?,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7" line.long 0x08 "UART_MDR2,Mode definition register 2" rbitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate function forUART_MDR1[4] (SET_TXIR)" "SET_TXIR_ALT_0,SET_TXIR_ALT_1" newline bitfld.long 0x08 6. "IRRXINVERT,IR mode only (IrDA and CIR)" "IRRXINVERT_0,IRRXINVERT_1" newline bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition" "CIR_PULSE_MODE_0,CIR_PULSE_MODE_1,CIR_PULSE_MODE_2,CIR_PULSE_MODE_3" newline bitfld.long 0x08 3. "UART_PULSE,UART mode only" "UART_PULSE_0,UART_PULSE_1" newline bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only" "STS_FIFO_TRIG_0,STS_FIFO_TRIG_1,STS_FIFO_TRIG_2,STS_FIFO_TRIG_3" newline rbitfld.long 0x08 0. "IRTX_UNDERRUN,IrDA transmission status interrupt" "IRTX_UNDERRUN_0_r,IRTX_UNDERRUN_1_r" line.long 0x0C "UART_SFLSR,Status FIFO line status register" bitfld.long 0x0C 4. "OE_ERROR," "OE_ERROR_0,OE_ERROR_1" newline bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "FRAME_TOO_LONG_ERROR_0,FRAME_TOO_LONG_ERROR_1" newline bitfld.long 0x0C 2. "ABORT_DETECT," "ABORT_DETECT_0,ABORT_DETECT_1" newline bitfld.long 0x0C 1. "CRC_ERROR," "CRC_ERROR_0,CRC_ERROR_1" group.long 0x28++0x07 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length" line.long 0x04 "UART_RESUME,IR-IrDA and IR-CIR modes only" hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x07 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "TXFLH_0,TXFLH_1,TXFLH_2,TXFLH_3,TXFLH_4,TXFLH_5,TXFLH_6,TXFLH_7,TXFLH_8,TXFLH_9,TXFLH_10,TXFLH_11,TXFLH_12,TXFLH_13,TXFLH_14,TXFLH_15,TXFLH_16,TXFLH_17,TXFLH_18,TXFLH_19,TXFLH_20,TXFLH_21,TXFLH_22,TXFLH_23,TXFLH_24,TXFLH_25,TXFLH_26,TXFLH_27,TXFLH_28,TXFLH_29,TXFLH_30,TXFLH_31" line.long 0x04 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x07 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length" line.long 0x04 "UART_RXFLH,Received frame length register high" bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "RXFLH_0,RXFLH_1,RXFLH_2,RXFLH_3,RXFLH_4,RXFLH_5,RXFLH_6,RXFLH_7,RXFLH_8,RXFLH_9,RXFLH_10,RXFLH_11,RXFLH_12,RXFLH_13,RXFLH_14,RXFLH_15" rgroup.long 0x34++0x07 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "SFREGH_0,SFREGH_1,SFREGH_2,SFREGH_3,SFREGH_4,SFREGH_5,SFREGH_6,SFREGH_7,SFREGH_8,SFREGH_9,SFREGH_10,SFREGH_11,SFREGH_12,SFREGH_13,SFREGH_14,SFREGH_15" line.long 0x04 "UART_BLR,BOF control register" bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "STS_FIFO_RESET_0,STS_FIFO_RESET_1" newline bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "XBOF_TYPE_0,XBOF_TYPE_1" rgroup.long 0x38++0x13 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,PARITY_TYPE_1_r,PARITY_TYPE_2_r,PARITY_TYPE_3_r" newline bitfld.long 0x00 5. "BIT_BY_CHAR," "?,BIT_BY_CHAR_1_r" newline bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0_r,SPEED_1_r,SPEED_2_r,SPEED_3_r,SPEED_4_r,SPEED_5_r,SPEED_6_r,SPEED_7_r,SPEED_8_r,SPEED_9_r,SPEED_10_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "UART_ACREG,Auxiliary control register" bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "PULSE_TYPE_0,PULSE_TYPE_1" newline bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "SD_MOD_0,SD_MOD_1" newline bitfld.long 0x04 5. "DIS_IR_RX," "?,DIS_IR_RX_1" newline bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "DIS_TX_UNDERRUN_0,DIS_TX_UNDERRUN_1" newline bitfld.long 0x04 3. "SEND_SIP,MIR/FIR modes only" "SEND_SIP_0,SEND_SIP_1" newline bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "SCTX_EN_0,SCTX_EN_1" newline bitfld.long 0x04 1. "ABORT_EN,Frame abort" "ABORT_EN_0,ABORT_EN_1" newline bitfld.long 0x04 0. "EOT_EN,EOT (end of transmission) bit" "EOT_EN_0,EOT_EN_1" line.long 0x08 "UART_SCR,Supplementary control register" bitfld.long 0x08 7. "RX_TRIG_GRANU1," "?,RX_TRIG_GRANU1_1" newline bitfld.long 0x08 6. "TX_TRIG_GRANU1," "?,TX_TRIG_GRANU1_1" newline bitfld.long 0x08 5. "DSR_IT," "?,DSR_IT_1" newline bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "?,RX_CTS_DSR_WAKE_UP_ENABLE_1" newline bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "?,TX_EMPTY_CTL_IT_1" newline bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if theUART_SCR[0] bit =" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3" newline bitfld.long 0x08 0. "DMA_MODE_CTL," "?,DMA_MODE_CTL_1" line.long 0x0C "UART_SSR,Supplementary status register" bitfld.long 0x0C 2. "DMA_COUNTER_RST," "?,DMA_COUNTER_RST_1" newline rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "?,RX_CTS_DSR_WAKE_UP_STS_1_r" newline rbitfld.long 0x0C 0. "TX_FIFO_FULL," "?,TX_FIFO_FULL_1_r" line.long 0x10 "UART_EBLR,BOF length register" hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification" rgroup.long 0x50++0x27 line.long 0x00 "UART_MVR,Module version register" line.long 0x04 "UART_SYSC,System configuration register" bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "UART_SYSS,System status register" bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x0C "UART_WER,Wake-up enable register" bitfld.long 0x0C 7. "TX_WAKEUP_EN," "?,TX_WAKEUP_EN_1" newline bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "?,EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_1" newline bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "?,EVENT_5_RHR_INTERRUPT_1" newline bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "?,EVENT_4_RX_ACTIVITY_1" newline bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "?,EVENT_3_DCD_CD_ACTIVITY_1" newline bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "?,EVENT_2_RI_ACTIVITY_1" newline bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "?,EVENT_1_DSR_ACTIVITY_1" newline bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "?,EVENT_0_CTS_ACTIVITY_1" line.long 0x10 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple)" line.long 0x14 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x18 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" line.long 0x1C "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1" newline bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1" line.long 0x20 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1" newline bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1" line.long 0x24 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set" group.long 0x80++0x07 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register" "0,1" newline bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "NONDEFAULT_FREQ_0,NONDEFAULT_FREQ_1" newline bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "DISABLE_CIR_RX_DEMOD_0,DISABLE_CIR_RX_DEMOD_1" line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end repeat.end tree.end tree "USB3_PHY_and_SATA_PHY" tree "DPLLCTRL_SATA" base ad:0x4A096800 rgroup.long 0x04++0x1F line.long 0x00 "PLL_STATUS,This register contains the status information" bitfld.long 0x00 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x00 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x00 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x00 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" bitfld.long 0x00 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x00 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x00 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x00 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x04 "PLL_GO,This register contains the GO bit" bitfld.long 0x04 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x08 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x08 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x08 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x0C "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0C 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,?,?" bitfld.long 0x0C 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_USB_OTG_SS / DPLLCTRL_SATA 0x2 Set if DCO frequency is between 750MHz and 1500MHz 0x4 Set if DCO frequency is between 1250MHz and 2500MHz Other values: Reserved" "PLL_SELFREQDCO_0,PLL_SELFREQDCO_1,PLL_SELFREQDCO_2,PLL_SELFREQDCO_3,PLL_SELFREQDCO_4,PLL_SELFREQDCO_5,PLL_SELFREQDCO_6,PLL_SELFREQDCO_7" bitfld.long 0x0C 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x10 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x10 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration" line.long 0x14 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x14 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x14 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_Off" "EN_SSC_0,EN_SSC_1" line.long 0x18 "PLL_SSC_CONFIGURATION2," bitfld.long 0x18 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x18 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider control for SSC" hexmask.long.tbyte 0x18 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x1C "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.tbyte 0x1C 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "DPLLCTRL_USB_OTG_SS" base ad:0x4A084C00 rgroup.long 0x04++0x1F line.long 0x00 "PLL_STATUS,This register contains the status information" bitfld.long 0x00 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x00 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x00 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x00 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" bitfld.long 0x00 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x00 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x00 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x00 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x04 "PLL_GO,This register contains the GO bit" bitfld.long 0x04 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x08 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x08 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x08 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x0C "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0C 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,?,?" bitfld.long 0x0C 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_USB_OTG_SS / DPLLCTRL_SATA 0x2 Set if DCO frequency is between 750MHz and 1500MHz 0x4 Set if DCO frequency is between 1250MHz and 2500MHz Other values: Reserved" "PLL_SELFREQDCO_0,PLL_SELFREQDCO_1,PLL_SELFREQDCO_2,PLL_SELFREQDCO_3,PLL_SELFREQDCO_4,PLL_SELFREQDCO_5,PLL_SELFREQDCO_6,PLL_SELFREQDCO_7" bitfld.long 0x0C 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x10 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x10 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration" line.long 0x14 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x14 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x14 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_Off" "EN_SSC_0,EN_SSC_1" line.long 0x18 "PLL_SSC_CONFIGURATION2," bitfld.long 0x18 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x18 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider control for SSC" hexmask.long.tbyte 0x18 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x1C "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.tbyte 0x1C 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" width 0x0B tree.end tree "USB3_PHY_RX" base ad:0x4A084400 group.long 0x0C++0x03 line.long 0x00 "USB3PHYRX_ANA_PROGRAMMABILITY_REG1,Some programmability for different analog circuits in the PHY" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANAMODE,Programmability for Analog circuits in the IP" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "USB3PHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "USB3PHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "USB3PHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section of the PHY" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" newline bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of PLL_CLK (after the bypassing by MEM_EN_PLLBYP and the division by MEM_PLLDIV) frequency and the output data rate" "Full Rate,Half Rate,Quarter Rate,RESERVED" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" newline bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" newline bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "USB3PHYRX_EQUALIZER_REG1,The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--10. "MEM_EQCTL," "?,Fully adaptive; FTC normal,Fully adaptive; FTC inverted,Hold eq state 01xx - Init eq to fully adaptive..,?,?,?,?,Partially adaptive; zero=1084 MHz,Partially adaptive; zero= 805 MHz,Partially adaptive; zero= 573 MHz,Partially adaptive; zero= 402 MHZ,Partially adaptive; zero= 304 MHz,Partially adaptive; zero= 216 MHz,Partially adaptive; zero= 156 MHz,Partially adaptive; zero= 135 MHz" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the eqlev[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the eqftc[4:0]" "0,1" width 0x0B tree.end tree "USB3_PHY_TX" base ad:0x4A084800 group.long 0x0C++0x03 line.long 0x00 "USB3PHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" group.long 0x2C++0x07 line.long 0x00 "USB3PHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" newline bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "31-bit LFSR mode,generate 1010 pattern,7-bit LFSR mode,23-bit LFSR mode,Fixed 31-bit value from PATTGEN_PRELOAD_VAL,?..." line.long 0x04 "USB3PHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" width 0x0B tree.end tree.end tree "VCOP_CPU_and_Instruction_Set" tree "EVE1_VCOP" base ad:0x42084000 tree "Channel_0" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_1" rgroup.long 0x44++0x03 line.long 0x00 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x64++0x03 line.long 0x00 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_2" rgroup.long 0x48++0x03 line.long 0x00 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x68++0x03 line.long 0x00 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_3" rgroup.long 0x4C++0x03 line.long 0x00 "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x6C++0x03 line.long 0x00 "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_4" rgroup.long 0x50++0x03 line.long 0x00 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x70++0x03 line.long 0x00 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_5" rgroup.long 0x54++0x03 line.long 0x00 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x74++0x03 line.long 0x00 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_6" rgroup.long 0x58++0x03 line.long 0x00 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x78++0x03 line.long 0x00 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_7" rgroup.long 0x5C++0x03 line.long 0x00 "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x7C++0x03 line.long 0x00 "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end group.long 0x04++0x03 line.long 0x00 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x00 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x00 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" group.long 0x10++0x03 line.long 0x00 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x00 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x00 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x00 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x00 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x00 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x00 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x00 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x00 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x00 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x00 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x00 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x00 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x00 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x00 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x00 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x00 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" group.long 0x0C++0x03 line.long 0x00 "VCOP_MAX_ITERS," hexmask.long.word 0x00 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "MAX_ITERS,Maximum iteration count" rgroup.long 0x24++0x03 line.long 0x00 "VCOP_PARAM_PTR," rgroup.long 0x00++0x03 line.long 0x00 "VCOP_PID," rgroup.long 0x08++0x03 line.long 0x00 "VCOP_STATUS,VCOP status register" bitfld.long 0x00 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x00 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x00 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" rgroup.long 0x20++0x03 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" width 0x0B tree.end tree "EVE2_VCOP" base ad:0x42184000 tree "Channel_0" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_1" rgroup.long 0x44++0x03 line.long 0x00 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x64++0x03 line.long 0x00 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_2" rgroup.long 0x48++0x03 line.long 0x00 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x68++0x03 line.long 0x00 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_3" rgroup.long 0x4C++0x03 line.long 0x00 "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x6C++0x03 line.long 0x00 "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_4" rgroup.long 0x50++0x03 line.long 0x00 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x70++0x03 line.long 0x00 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_5" rgroup.long 0x54++0x03 line.long 0x00 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x74++0x03 line.long 0x00 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_6" rgroup.long 0x58++0x03 line.long 0x00 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x78++0x03 line.long 0x00 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_7" rgroup.long 0x5C++0x03 line.long 0x00 "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x7C++0x03 line.long 0x00 "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end group.long 0x04++0x03 line.long 0x00 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x00 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x00 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" group.long 0x10++0x03 line.long 0x00 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x00 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x00 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x00 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x00 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x00 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x00 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x00 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x00 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x00 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x00 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x00 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x00 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x00 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x00 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x00 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x00 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" group.long 0x0C++0x03 line.long 0x00 "VCOP_MAX_ITERS," hexmask.long.word 0x00 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "MAX_ITERS,Maximum iteration count" rgroup.long 0x24++0x03 line.long 0x00 "VCOP_PARAM_PTR," rgroup.long 0x00++0x03 line.long 0x00 "VCOP_PID," rgroup.long 0x08++0x03 line.long 0x00 "VCOP_STATUS,VCOP status register" bitfld.long 0x00 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x00 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x00 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" rgroup.long 0x20++0x03 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" width 0x0B tree.end tree "EVE3_VCOP" base ad:0x42284000 tree "Channel_0" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_1" rgroup.long 0x44++0x03 line.long 0x00 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x64++0x03 line.long 0x00 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_2" rgroup.long 0x48++0x03 line.long 0x00 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x68++0x03 line.long 0x00 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_3" rgroup.long 0x4C++0x03 line.long 0x00 "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x6C++0x03 line.long 0x00 "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_4" rgroup.long 0x50++0x03 line.long 0x00 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x70++0x03 line.long 0x00 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_5" rgroup.long 0x54++0x03 line.long 0x00 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x74++0x03 line.long 0x00 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_6" rgroup.long 0x58++0x03 line.long 0x00 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x78++0x03 line.long 0x00 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_7" rgroup.long 0x5C++0x03 line.long 0x00 "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x7C++0x03 line.long 0x00 "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end group.long 0x04++0x03 line.long 0x00 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x00 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x00 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" group.long 0x10++0x03 line.long 0x00 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x00 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x00 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x00 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x00 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x00 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x00 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x00 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x00 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x00 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x00 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x00 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x00 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x00 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x00 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x00 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x00 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" group.long 0x0C++0x03 line.long 0x00 "VCOP_MAX_ITERS," hexmask.long.word 0x00 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "MAX_ITERS,Maximum iteration count" rgroup.long 0x24++0x03 line.long 0x00 "VCOP_PARAM_PTR," rgroup.long 0x00++0x03 line.long 0x00 "VCOP_PID," rgroup.long 0x08++0x03 line.long 0x00 "VCOP_STATUS,VCOP status register" bitfld.long 0x00 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x00 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x00 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" rgroup.long 0x20++0x03 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" width 0x0B tree.end tree "EVE4_VCOP" base ad:0x42384000 tree "Channel_0" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_1" rgroup.long 0x44++0x03 line.long 0x00 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x64++0x03 line.long 0x00 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_2" rgroup.long 0x48++0x03 line.long 0x00 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x68++0x03 line.long 0x00 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_3" rgroup.long 0x4C++0x03 line.long 0x00 "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x6C++0x03 line.long 0x00 "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_4" rgroup.long 0x50++0x03 line.long 0x00 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x70++0x03 line.long 0x00 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_5" rgroup.long 0x54++0x03 line.long 0x00 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x74++0x03 line.long 0x00 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_6" rgroup.long 0x58++0x03 line.long 0x00 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x78++0x03 line.long 0x00 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_7" rgroup.long 0x5C++0x03 line.long 0x00 "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x7C++0x03 line.long 0x00 "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end group.long 0x04++0x03 line.long 0x00 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x00 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x00 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" group.long 0x10++0x03 line.long 0x00 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x00 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x00 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x00 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x00 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x00 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x00 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x00 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x00 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x00 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x00 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x00 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x00 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x00 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x00 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x00 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x00 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" group.long 0x0C++0x03 line.long 0x00 "VCOP_MAX_ITERS," hexmask.long.word 0x00 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "MAX_ITERS,Maximum iteration count" rgroup.long 0x24++0x03 line.long 0x00 "VCOP_PARAM_PTR," rgroup.long 0x00++0x03 line.long 0x00 "VCOP_PID," rgroup.long 0x08++0x03 line.long 0x00 "VCOP_STATUS,VCOP status register" bitfld.long 0x00 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x00 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x00 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" rgroup.long 0x20++0x03 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" width 0x0B tree.end tree "EVE_VCOP" base ad:0x42084000 tree "Channel_0" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_1" rgroup.long 0x44++0x03 line.long 0x00 "VCOP_LD_PTR_i_1,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x64++0x03 line.long 0x00 "VCOP_ST_PTR_j_1,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_2" rgroup.long 0x48++0x03 line.long 0x00 "VCOP_LD_PTR_i_2,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x68++0x03 line.long 0x00 "VCOP_ST_PTR_j_2,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_3" rgroup.long 0x4C++0x03 line.long 0x00 "VCOP_LD_PTR_i_3,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x6C++0x03 line.long 0x00 "VCOP_ST_PTR_j_3,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_4" rgroup.long 0x50++0x03 line.long 0x00 "VCOP_LD_PTR_i_4,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x70++0x03 line.long 0x00 "VCOP_ST_PTR_j_4,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_5" rgroup.long 0x54++0x03 line.long 0x00 "VCOP_LD_PTR_i_5,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x74++0x03 line.long 0x00 "VCOP_ST_PTR_j_5,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_6" rgroup.long 0x58++0x03 line.long 0x00 "VCOP_LD_PTR_i_6,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x78++0x03 line.long 0x00 "VCOP_ST_PTR_j_6,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end tree "Channel_7" rgroup.long 0x5C++0x03 line.long 0x00 "VCOP_LD_PTR_i_7,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x7C++0x03 line.long 0x00 "VCOP_ST_PTR_j_7,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end group.long 0x04++0x03 line.long 0x00 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x00 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x00 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" group.long 0x10++0x03 line.long 0x00 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x00 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x00 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x00 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x00 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x00 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x00 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x00 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x00 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x00 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x00 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x00 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x00 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x00 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x00 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x00 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x00 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" group.long 0x0C++0x03 line.long 0x00 "VCOP_MAX_ITERS," hexmask.long.word 0x00 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x00 0.--15. 1. "MAX_ITERS,Maximum iteration count" rgroup.long 0x24++0x03 line.long 0x00 "VCOP_PARAM_PTR," rgroup.long 0x00++0x03 line.long 0x00 "VCOP_PID," rgroup.long 0x08++0x03 line.long 0x00 "VCOP_STATUS,VCOP status register" bitfld.long 0x00 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x00 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x00 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" rgroup.long 0x20++0x03 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" width 0x0B tree.end tree.end tree "VIP" tree "VIP1_Slice0_csc" base ad:0x48975700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP1_Slice1_csc" base ad:0x48975C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP2_Slice0_csc" base ad:0x48995700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP2_Slice1_csc" base ad:0x48995C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VIP1_Slice0_parser" base ad:0x48975500 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP1_Slice1_parser" base ad:0x48975A00 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP2_Slice0_parser" base ad:0x48995500 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP2_Slice1_parser" base ad:0x48995A00 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "Do not clip active pixels,Clip Active Pixels as follows" newline bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "Do not clip Blanking Data,Clip Blanking Data as follows" newline bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "?,16b data interface,Dual independent 8b data interfaces,Undefined" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" newline bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" newline bitfld.long 0x04 8. "ENABLE," "0,1" newline bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "Use data[7:0] to extract control codes,Use data[15:8] to extract control codes,Use data[23:16] to extract control codes,Undefined In 16b and 24b modes" newline bitfld.long 0x04 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed 4:2:2 YUV stream,embedded sync 4x multiplexed 4:2:2 YUV stream,embedded sync line multiplexed 4:2:2 YUV stream,discrete sync single 4:2:2 YUV stream,embedded sync single RGB stream or single 444..,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "?,Cross Swap,Left Center Swap,Center Right Swap,Right Rotate,Left Rotate,RAW16 to RGB565 Mapping,RAW12 Swap" newline hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "Ignore the protection bits in the XV (fvh)..,Use the protection bits in an attempt to do.." newline bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "For 2x/4x mux mode srcnum is in the least..,For 2x/4x mux mode srcnum is in the least.." newline bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" newline bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "Normal Discrete Mode,Basic Discrete Mode" newline bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "Use HSYNC style line capture,Use ACTVID style line capture" newline bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "Take FID from pin,FID is determined by VSYNC skew" newline bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "ACTVID is active low,ACTVID is active high" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "VSYNC is active low,VSYNC is active high" newline bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "HSYNC is active low,HSYNC is active high" newline bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" newline bitfld.long 0x0C 8. "ENABLE," "0,1" newline bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" newline bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "SYNC_TYPE," "?,embedded sync 2x multiplexed YUV stream,embedded sync 4x multiplexed YUV stream,embedded sync line multiplexed YUV stream,discrete sync single YUV stream,embedded sync single RGB stream,reserved,reserved,reserved,reserved,discrete sync single 24b RGB stream,?..." line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" newline bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "Extract 8b Mode Vertical Ancillary Data from..,Extract 8b Mode Vertical Ancillary Data from..,?,Extract every single sample of vertical.." newline hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" newline bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" newline bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" newline bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" newline bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" newline bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" newline bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" newline bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" newline bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" newline bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" newline bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" newline bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" newline bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" newline bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" newline bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" newline bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" newline bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" newline bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" newline bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" newline bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" newline bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" newline bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" newline bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" newline bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" newline bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" newline bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" newline bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" newline bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" newline bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" newline bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" newline bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" newline bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" newline bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" newline bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" newline bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" newline hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" newline hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" newline hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" newline hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" newline hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" newline hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" newline hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" newline hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" newline hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" newline hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" newline hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" newline hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" newline hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" newline hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" newline hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" newline hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" newline hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" newline hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" newline hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" newline hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" newline hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" newline hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" newline hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" newline hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" newline hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" newline hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" newline hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" newline hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" newline hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" newline hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" newline hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" newline hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" newline hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" newline bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" newline hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" newline hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" width 0x0B tree.end tree "VIP1_Slice0_sc" base ad:0x48975800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP1_Slice1_sc" base ad:0x48975D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP2_Slice0_sc" base ad:0x48995800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP2_Slice1_sc" base ad:0x48995D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" newline bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "disable trimming,enable trimming" newline bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "disable luma peaking,enable luma peaking" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "the input video format is progressive,the input video format is interlace" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "The polyphase scaler is always used regardless..,The polyphase scaler is bypassed only when.." newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "the 4X decimation filter is disabled,the 4X decimation filter is enabled" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "the 2X decimation filter is disabled,the 2X decimation filter is enabled" newline bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "the cfg_dcm_2x and cfg_dcm_4x bits will enable..,HW will decide whether up-scaling or.." newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "The output of edge-detection block will be force..,The calculation results of edge-detection block.." newline bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "Poly-phase filter will be used for the vertical..,Running average filter will be used for the.." newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "Progressive input,Interlaced input Must be set to 1 when.." newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "Scaling module will engaged,Scaling module will be bypassed" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "Anamorphic scaling,Linear scaling" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "The output format of SC is progressive,The output format of SC is interlace" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" newline hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" newline hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" newline hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" newline bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" newline hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" newline hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" newline hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VIP1_top_level" base ad:0x48970000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "Force-standby mode,No-standby mode,Same behavior as bit-field value of 0x1,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 16. "VPDMA_INT1_DESCRIPTOR_RAW,VPDMA INT1 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 15. "VPDMA_INT1_LIST7_NOTIFY_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 14. "VPDMA_INT1_LIST7_COMPLETE_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 13. "VPDMA_INT1_LIST6_NOTIFY_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 12. "VPDMA_INT1_LIST6_COMPLETE_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 11. "VPDMA_INT1_LIST5_NOTIFY_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 10. "VPDMA_INT1_LIST5_COMPLETE_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 9. "VPDMA_INT1_LIST4_NOTIFY_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 8. "VPDMA_INT1_LIST4_COMPLETE_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 7. "VPDMA_INT1_LIST3_NOTIFY_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 6. "VPDMA_INT1_LIST3_COMPLETE_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 5. "VPDMA_INT1_LIST2_NOTIFY_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 4. "VPDMA_INT1_LIST2_COMPLETE_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 3. "VPDMA_INT1_LIST1_NOTIFY_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 2. "VPDMA_INT1_LIST1_COMPLETE_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 1. "VPDMA_INT1_LIST0_NOTIFY_RAW,VPDMA INT1 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 0. "VPDMA_INT1_LIST0_COMPLETE_RAW,VPDMA INT1 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 7. "VPDMA_INT1_CLIENT_RAW,VPDMA INT1 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 5. "VPDMA_INT1_CHANNEL_GROUP5_RAW,VPDMA INT1 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 4. "VPDMA_INT1_CHANNEL_GROUP4_RAW,VPDMA INT1 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 3. "VPDMA_INT1_CHANNEL_GROUP3_RAW,VPDMA INT1 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 2. "VPDMA_INT1_CHANNEL_GROUP2_RAW,VPDMA INT1 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 1. "VPDMA_INT1_CHANNEL_GROUP1_RAW,VPDMA INT1 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 0. "VPDMA_INT1_CHANNEL_GROUP0_RAW,VPDMA INT1 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 16. "VPDMA_INT1_DESCRIPTOR_ENA,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 15. "VPDMA_INT1_LIST7_NOTIFY_ENA,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 14. "VPDMA_INT1_LIST7_COMPLETE_ENA,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 13. "VPDMA_INT1_LIST6_NOTIFY_ENA,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 12. "VPDMA_INT1_LIST6_COMPLETE_ENA,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 11. "VPDMA_INT1_LIST5_NOTIFY_ENA,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 10. "VPDMA_INT1_LIST5_COMPLETE_ENA,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 9. "VPDMA_INT1_LIST4_NOTIFY_ENA,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 8. "VPDMA_INT1_LIST4_COMPLETE_ENA,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 7. "VPDMA_INT1_LIST3_NOTIFY_ENA,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 6. "VPDMA_INT1_LIST3_COMPLETE_ENA,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 5. "VPDMA_INT1_LIST2_NOTIFY_ENA,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 4. "VPDMA_INT1_LIST2_COMPLETE_ENA,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 3. "VPDMA_INT1_LIST1_NOTIFY_ENA,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 2. "VPDMA_INT1_LIST1_COMPLETE_ENA,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 1. "VPDMA_INT1_LIST0_NOTIFY_ENA,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 0. "VPDMA_INT1_LIST0_COMPLETE_ENA,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 7. "VPDMA_INT1_CLIENT_ENA,VPDMA INT1 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 16. "VPDMA_INT1_DESCRIPTOR_ENA_SET,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_SET,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_SET,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_SET,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_SET,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_SET,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_SET,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_SET,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_SET,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_SET,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_SET,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_SET,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_SET,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_SET,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_SET,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_SET,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_SET,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 7. "VPDMA_INT1_CLIENT_ENA_SET,VPDMA INT1 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_SET,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_SET,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_SET,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_SET,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_SET,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_SET,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_SET,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 16. "VPDMA_INT1_DESCRIPTOR_ENA_CLR,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_CLR,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_CLR,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_CLR,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_CLR,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_CLR,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_CLR,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_CLR,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_CLR,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_CLR,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_CLR,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_CLR,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_CLR,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_CLR,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_CLR,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_CLR,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_CLR,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 7. "VPDMA_INT1_CLIENT_ENA_CLR,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" bitfld.long 0x00 17. "VIP2_DP_EN,VIP Slice1 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 16. "VIP1_DP_EN,VIP Slice0 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "Clock Disabled,Clock Enabled" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in VIP Main Data Path" "0,1" newline bitfld.long 0x04 28. "S1_CHR_DS_1_RST,VIP Slice1 CHRDS1 reset" "0,1" newline bitfld.long 0x04 27. "S0_CHR_DS_1_RST,VIP Slice0 CHRDS1 reset" "0,1" newline bitfld.long 0x04 26. "S1_CHR_DS_0_RST,VIP Slice1 CHRDS0 reset" "0,1" newline bitfld.long 0x04 25. "S0_CHR_DS_0_RST,VIP Slice0 CHRDS0 reset" "0,1" newline bitfld.long 0x04 23. "S1_SC_RST,VIP Slice1 SC reset" "0,1" newline bitfld.long 0x04 22. "S0_SC_RST,VIP Slice0 SC reset" "0,1" newline bitfld.long 0x04 21. "S1_CSC_RST,VIP Slice1 CSC reset" "0,1" newline bitfld.long 0x04 20. "S0_CSC_RST,VIP Slice0 CSC reset" "0,1" newline bitfld.long 0x04 19. "S1_PARSER_RST,VIP Slice1 parser reset" "0,1" newline bitfld.long 0x04 18. "S0_PARSER_RST,VIP Slice0 parser reset" "0,1" newline bitfld.long 0x04 17. "VIP2_DP_RST,VIP Slice1 Data Path Reset" "0,1" newline bitfld.long 0x04 16. "VIP1_DP_RST,VIP Slice0 Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" newline bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" newline bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "All fields written,Only vip1_csc_src_select written,Only vip1_sc_src_select written,Only vip1_rgb_src_select written,Only vip1_rgb_out_lo_select written,Only vip1_rgb_out_hi_select written,Only vip1_chr_ds_1_src_select written,Only vip1_chr_ds_2_src_select written,Only vip1_multi_channel_select written,Only vip1_chr_ds_1_bypass written,Only vip1_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "All fields written,Only vip2_csc_src_select written,Only vip2_sc_src_select written,Only vip2_rgb_src_select written,Only vip2_rgb_out_lo_select written,Only vip2_rgb_out_hi_select written,Only vip2_chr_ds_1_src_select written,Only vip2_chr_ds_2_src_select written,Only vip2_multi_channel_select written,Only vip2_chr_ds_1_bypass written,Only vip2_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" width 0x0B tree.end tree "VIP2_top_level" base ad:0x48990000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" newline bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "Force-standby mode,No-standby mode,Same behavior as bit-field value of 0x1,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 16. "VPDMA_INT1_DESCRIPTOR_RAW,VPDMA INT1 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 15. "VPDMA_INT1_LIST7_NOTIFY_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 14. "VPDMA_INT1_LIST7_COMPLETE_RAW,VPDMA INT1 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 13. "VPDMA_INT1_LIST6_NOTIFY_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 12. "VPDMA_INT1_LIST6_COMPLETE_RAW,VPDMA INT1 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 11. "VPDMA_INT1_LIST5_NOTIFY_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 10. "VPDMA_INT1_LIST5_COMPLETE_RAW,VPDMA INT1 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 9. "VPDMA_INT1_LIST4_NOTIFY_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 8. "VPDMA_INT1_LIST4_COMPLETE_RAW,VPDMA INT1 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 7. "VPDMA_INT1_LIST3_NOTIFY_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 6. "VPDMA_INT1_LIST3_COMPLETE_RAW,VPDMA INT1 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 5. "VPDMA_INT1_LIST2_NOTIFY_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 4. "VPDMA_INT1_LIST2_COMPLETE_RAW,VPDMA INT1 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 3. "VPDMA_INT1_LIST1_NOTIFY_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 2. "VPDMA_INT1_LIST1_COMPLETE_RAW,VPDMA INT1 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 1. "VPDMA_INT1_LIST0_NOTIFY_RAW,VPDMA INT1 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x20 0. "VPDMA_INT1_LIST0_COMPLETE_RAW,VPDMA INT1 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 7. "VPDMA_INT1_CLIENT_RAW,VPDMA INT1 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 5. "VPDMA_INT1_CHANNEL_GROUP5_RAW,VPDMA INT1 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 4. "VPDMA_INT1_CHANNEL_GROUP4_RAW,VPDMA INT1 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 3. "VPDMA_INT1_CHANNEL_GROUP3_RAW,VPDMA INT1 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 2. "VPDMA_INT1_CHANNEL_GROUP2_RAW,VPDMA INT1 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 1. "VPDMA_INT1_CHANNEL_GROUP1_RAW,VPDMA INT1 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x24 0. "VPDMA_INT1_CHANNEL_GROUP0_RAW,VPDMA INT1 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x28 16. "VPDMA_INT1_DESCRIPTOR_ENA,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 15. "VPDMA_INT1_LIST7_NOTIFY_ENA,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 14. "VPDMA_INT1_LIST7_COMPLETE_ENA,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 13. "VPDMA_INT1_LIST6_NOTIFY_ENA,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 12. "VPDMA_INT1_LIST6_COMPLETE_ENA,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 11. "VPDMA_INT1_LIST5_NOTIFY_ENA,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 10. "VPDMA_INT1_LIST5_COMPLETE_ENA,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 9. "VPDMA_INT1_LIST4_NOTIFY_ENA,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 8. "VPDMA_INT1_LIST4_COMPLETE_ENA,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 7. "VPDMA_INT1_LIST3_NOTIFY_ENA,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 6. "VPDMA_INT1_LIST3_COMPLETE_ENA,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 5. "VPDMA_INT1_LIST2_NOTIFY_ENA,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 4. "VPDMA_INT1_LIST2_COMPLETE_ENA,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 3. "VPDMA_INT1_LIST1_NOTIFY_ENA,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 2. "VPDMA_INT1_LIST1_COMPLETE_ENA,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 1. "VPDMA_INT1_LIST0_NOTIFY_ENA,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x28 0. "VPDMA_INT1_LIST0_COMPLETE_ENA,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 7. "VPDMA_INT1_CLIENT_ENA,VPDMA INT1 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x2C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 16. "VPDMA_INT1_DESCRIPTOR_ENA_SET,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_SET,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_SET,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_SET,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_SET,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_SET,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_SET,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_SET,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_SET,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_SET,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_SET,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_SET,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_SET,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_SET,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_SET,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_SET,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x30 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_SET,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 7. "VPDMA_INT1_CLIENT_ENA_SET,VPDMA INT1 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_SET,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_SET,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_SET,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_SET,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_SET,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_SET,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x34 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_SET,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 16. "VPDMA_INT1_DESCRIPTOR_ENA_CLR,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 15. "VPDMA_INT1_LIST7_NOTIFY_ENA_CLR,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 14. "VPDMA_INT1_LIST7_COMPLETE_ENA_CLR,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 13. "VPDMA_INT1_LIST6_NOTIFY_ENA_CLR,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 12. "VPDMA_INT1_LIST6_COMPLETE_ENA_CLR,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 11. "VPDMA_INT1_LIST5_NOTIFY_ENA_CLR,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 10. "VPDMA_INT1_LIST5_COMPLETE_ENA_CLR,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 9. "VPDMA_INT1_LIST4_NOTIFY_ENA_CLR,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 8. "VPDMA_INT1_LIST4_COMPLETE_ENA_CLR,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 7. "VPDMA_INT1_LIST3_NOTIFY_ENA_CLR,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 6. "VPDMA_INT1_LIST3_COMPLETE_ENA_CLR,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 5. "VPDMA_INT1_LIST2_NOTIFY_ENA_CLR,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 4. "VPDMA_INT1_LIST2_COMPLETE_ENA_CLR,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 3. "VPDMA_INT1_LIST1_NOTIFY_ENA_CLR,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 2. "VPDMA_INT1_LIST1_COMPLETE_ENA_CLR,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 1. "VPDMA_INT1_LIST0_NOTIFY_ENA_CLR,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x38 0. "VPDMA_INT1_LIST0_COMPLETE_ENA_CLR,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 7. "VPDMA_INT1_CLIENT_ENA_CLR,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 6. "VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 5. "VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 4. "VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 3. "VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 2. "VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 1. "VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x3C 0. "VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" bitfld.long 0x00 17. "VIP2_DP_EN,VIP Slice1 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 16. "VIP1_DP_EN,VIP Slice0 Data Path Clock Enable " "Clock Disabled,Clock Enabled" newline bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "Clock Disabled,Clock Enabled" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in VIP Main Data Path" "0,1" newline bitfld.long 0x04 28. "S1_CHR_DS_1_RST,VIP Slice1 CHRDS1 reset" "0,1" newline bitfld.long 0x04 27. "S0_CHR_DS_1_RST,VIP Slice0 CHRDS1 reset" "0,1" newline bitfld.long 0x04 26. "S1_CHR_DS_0_RST,VIP Slice1 CHRDS0 reset" "0,1" newline bitfld.long 0x04 25. "S0_CHR_DS_0_RST,VIP Slice0 CHRDS0 reset" "0,1" newline bitfld.long 0x04 23. "S1_SC_RST,VIP Slice1 SC reset" "0,1" newline bitfld.long 0x04 22. "S0_SC_RST,VIP Slice0 SC reset" "0,1" newline bitfld.long 0x04 21. "S1_CSC_RST,VIP Slice1 CSC reset" "0,1" newline bitfld.long 0x04 20. "S0_CSC_RST,VIP Slice0 CSC reset" "0,1" newline bitfld.long 0x04 19. "S1_PARSER_RST,VIP Slice1 parser reset" "0,1" newline bitfld.long 0x04 18. "S0_PARSER_RST,VIP Slice0 parser reset" "0,1" newline bitfld.long 0x04 17. "VIP2_DP_RST,VIP Slice1 Data Path Reset" "0,1" newline bitfld.long 0x04 16. "VIP1_DP_RST,VIP Slice0 Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" newline bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" newline bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "All fields written,Only vip1_csc_src_select written,Only vip1_sc_src_select written,Only vip1_rgb_src_select written,Only vip1_rgb_out_lo_select written,Only vip1_rgb_out_hi_select written,Only vip1_chr_ds_1_src_select written,Only vip1_chr_ds_2_src_select written,Only vip1_multi_channel_select written,Only vip1_chr_ds_1_bypass written,Only vip1_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "All fields written,Only vip2_csc_src_select written,Only vip2_sc_src_select written,Only vip2_rgb_src_select written,Only vip2_rgb_out_lo_select written,Only vip2_rgb_out_hi_select written,Only vip2_chr_ds_1_src_select written,Only vip2_chr_ds_2_src_select written,Only vip2_multi_channel_select written,Only vip2_chr_ds_1_bypass written,Only vip2_chr_ds_2_bypass written,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" newline bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "VIP Chroma Downsampler 1 selected,VIP Chroma Downsampler 1 Bypassed Chroma.." newline bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "VIP_PARSER A and B channels operate in single..,VIP_PARSER A and B channels directly drive VPDMA.." newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "Path Disabled (no input to CHR_DS),Source from Scaler (SC_M),Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved" newline bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "Output Type is 420/422,Output Type is RGB" newline bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "Source from Compositor RGB input,Source from CSC" newline bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "Path Disabled,Source from Color Space Converter (CSC),Source from VIP_PARSER A port,Source from VIP_PARSER B port,Source from Transcode (422),Reserved,Reserved,Reserved" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "Path Disabled,Source from VIP_PARSER A (422) port,Source from VIP_PARSER B port,Source from Transcode (422),Source from VIP_PARSER A (RGB) port,Source from Compositor (RGB),Reserved,Reserved" width 0x0B tree.end tree "VIP1_VPDMA" base ad:0x4897D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x3F line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_GRPX3,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 30. "INT_STAT_GRPX2,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 29. "INT_STAT_GRPX1,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x10 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_chroma" "0,1" bitfld.long 0x10 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x10 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" bitfld.long 0x18 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" bitfld.long 0x18 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" bitfld.long 0x18 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" bitfld.long 0x18 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" bitfld.long 0x18 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" bitfld.long 0x18 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" bitfld.long 0x18 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" bitfld.long 0x18 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" line.long 0x1C "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x20 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x20 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x24 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x28 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x28 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x28 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x28 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x28 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x28 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x28 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x28 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x28 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x28 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x2C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x30 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x30 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x30 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x30 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x30 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x30 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x34 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x38 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x38 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" bitfld.long 0x38 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x38 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x38 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x38 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x38 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" bitfld.long 0x38 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" newline bitfld.long 0x38 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x38 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x38 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x3C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x3C 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x78++0x47 line.long 0x00 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x00 31. "INT_STAT_GRPX1_DATA,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 30. "INT_STAT_COMP_WRBK,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 29. "INT_STAT_SC_OUT,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 20. "INT_STAT_SC_IN_LUMA,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 19. "INT_STAT_SC_IN_CHROMA,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 18. "INT_STAT_PIP_WRBK,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 17. "INT_STAT_DEI_SC_OUT,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x08 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x10 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x18 31. "INT_STAT_GRPX3,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 30. "INT_STAT_GRPX2,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 29. "INT_STAT_GRPX1,The last write DMA transaction has completed for channel scaler_out" "0,1" newline bitfld.long 0x18 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x18 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x18 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" bitfld.long 0x18 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" bitfld.long 0x18 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x18 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" bitfld.long 0x18 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x18 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x18 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x18 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" bitfld.long 0x18 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x1C "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x1C 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x20 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" line.long 0x24 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x28 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x28 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x28 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x28 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x28 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x28 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x28 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x28 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x28 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x28 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x28 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x28 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x2C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x2C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x30 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x30 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x30 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x30 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x30 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x30 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x30 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x34 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x38 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x38 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x38 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x38 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x38 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x38 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x38 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x38 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x3C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x40 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" bitfld.long 0x40 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_chroma" "0,1" newline bitfld.long 0x40 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x40 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x40 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x40 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x40 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x40 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" bitfld.long 0x40 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" newline bitfld.long 0x40 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x40 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x40 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x40 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x40 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x40 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x40 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x40 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x40 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x40 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x40 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x40 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x40 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x40 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x40 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x40 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x44 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0xC8++0x17 line.long 0x00 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x00 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 18. "INT_MASK_NF_READ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x08 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x10 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 14. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ) group.long ($2+0x2C0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x280)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end width 0x0B tree.end tree "VIP2_VPDMA" base ad:0x4899D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x3F line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_GRPX3,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 30. "INT_STAT_GRPX2,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x10 29. "INT_STAT_GRPX1,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x10 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_chroma" "0,1" bitfld.long 0x10 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x10 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" bitfld.long 0x18 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" bitfld.long 0x18 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" bitfld.long 0x18 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" bitfld.long 0x18 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" bitfld.long 0x18 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" bitfld.long 0x18 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" bitfld.long 0x18 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" bitfld.long 0x18 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" line.long 0x1C "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x20 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x20 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x24 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x28 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x28 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x28 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x28 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x28 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x28 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x28 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x28 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x28 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x28 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x2C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x30 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x30 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x30 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x30 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x30 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x30 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x34 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x38 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x38 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" bitfld.long 0x38 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x38 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x38 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x38 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x38 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x38 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" bitfld.long 0x38 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" newline bitfld.long 0x38 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x38 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x38 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x38 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x3C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x3C 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x78++0x47 line.long 0x00 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x00 31. "INT_STAT_GRPX1_DATA,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 30. "INT_STAT_COMP_WRBK,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 29. "INT_STAT_SC_OUT,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 20. "INT_STAT_SC_IN_LUMA,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 19. "INT_STAT_SC_IN_CHROMA,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 18. "INT_STAT_PIP_WRBK,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 17. "INT_STAT_DEI_SC_OUT,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x08 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x10 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x18 31. "INT_STAT_GRPX3,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 30. "INT_STAT_GRPX2,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 29. "INT_STAT_GRPX1,The last write DMA transaction has completed for channel scaler_out" "0,1" newline bitfld.long 0x18 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" bitfld.long 0x18 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" bitfld.long 0x18 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x18 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" bitfld.long 0x18 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" bitfld.long 0x18 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x18 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" bitfld.long 0x18 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" bitfld.long 0x18 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x18 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" bitfld.long 0x18 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" bitfld.long 0x18 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x1C "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x1C 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x1C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x1C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x20 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" line.long 0x24 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x28 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x28 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x28 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x28 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x28 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x28 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x28 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x28 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x28 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x28 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x28 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x28 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x28 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x28 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x28 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x28 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x28 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x28 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x28 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x2C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x2C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x30 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x30 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x30 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x30 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x30 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x30 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x30 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x30 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x30 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x30 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x30 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x34 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x34 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x38 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x38 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x38 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x38 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x38 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x38 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x38 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x38 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x3C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" bitfld.long 0x40 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" bitfld.long 0x40 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_chroma" "0,1" newline bitfld.long 0x40 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" bitfld.long 0x40 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x40 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" bitfld.long 0x40 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" bitfld.long 0x40 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x40 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" bitfld.long 0x40 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" bitfld.long 0x40 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" newline bitfld.long 0x40 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x40 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x40 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x40 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x40 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x40 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x40 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x40 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x40 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x40 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x40 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x40 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x40 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x40 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x40 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x40 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x44 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0xC8++0x17 line.long 0x00 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x00 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 18. "INT_MASK_NF_READ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x00 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x08 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x10 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 14. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ) group.long ($2+0x2C0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x280)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "command request,command accept,data request,data rcvd,data empty,data full,frame start,frame end" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end width 0x0B tree.end tree.end tree "VPE" tree "VPE_CHR_US_INST_0" base ad:0x489D0300 rgroup.long 0x00++0x23 line.long 0x00 "VPE_PID," line.long 0x04 "VPE_REG0," hexmask.long.word 0x04 18.--31. 1. "ANCHOR_FID0_C0,C0 coefficient for Anchor Pixel" bitfld.long 0x04 16.--17. "CFG_MODE," "?,CFG_MODE_1,?,?" hexmask.long.word 0x04 2.--15. 1. "ANCHOR_FID0_C1,C1 coefficient for Anchor Pixel" line.long 0x08 "VPE_REG1," hexmask.long.word 0x08 18.--31. 1. "ANCHOR_FID0_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x08 2.--15. 1. "ANCHOR_FID0_C3,C3 coefficient for Anchor Pixel" line.long 0x0C "VPE_REG2," hexmask.long.word 0x0C 18.--31. 1. "INTERP_FID0_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x0C 2.--15. 1. "INTERP_FID0_C1,C1 coefficient for Interpolated Pixel" line.long 0x10 "VPE_REG3," hexmask.long.word 0x10 18.--31. 1. "INTERP_FID0_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x10 2.--15. 1. "INTERP_FID0_C3,C3 coefficient for Interpolated Pixel" line.long 0x14 "VPE_REG4," hexmask.long.word 0x14 18.--31. 1. "ANCHOR_FID1_C0,C0 coefficient for Anchor Pixel" hexmask.long.word 0x14 2.--15. 1. "ANCHOR_FID1_C1,C1 coefficient for Anchor Pixel" line.long 0x18 "VPE_REG5," hexmask.long.word 0x18 18.--31. 1. "ANCHOR_FID1_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x18 2.--15. 1. "ANCHOR_FID1_C3,C3 coefficient for Anchor Pixel" line.long 0x1C "VPE_REG6," hexmask.long.word 0x1C 18.--31. 1. "INTERP_FID1_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x1C 2.--15. 1. "INTERP_FID1_C1,C1 coefficient for Interpolated Pixel" line.long 0x20 "VPE_REG7," hexmask.long.word 0x20 18.--31. 1. "INTERP_FID1_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x20 2.--15. 1. "INTERP_FID1_C3,C3 coefficient for Interpolated Pixel" width 0x0B tree.end tree "VPE_CHR_US_INST_1" base ad:0x489D0400 rgroup.long 0x00++0x23 line.long 0x00 "VPE_PID," line.long 0x04 "VPE_REG0," hexmask.long.word 0x04 18.--31. 1. "ANCHOR_FID0_C0,C0 coefficient for Anchor Pixel" bitfld.long 0x04 16.--17. "CFG_MODE," "?,CFG_MODE_1,?,?" hexmask.long.word 0x04 2.--15. 1. "ANCHOR_FID0_C1,C1 coefficient for Anchor Pixel" line.long 0x08 "VPE_REG1," hexmask.long.word 0x08 18.--31. 1. "ANCHOR_FID0_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x08 2.--15. 1. "ANCHOR_FID0_C3,C3 coefficient for Anchor Pixel" line.long 0x0C "VPE_REG2," hexmask.long.word 0x0C 18.--31. 1. "INTERP_FID0_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x0C 2.--15. 1. "INTERP_FID0_C1,C1 coefficient for Interpolated Pixel" line.long 0x10 "VPE_REG3," hexmask.long.word 0x10 18.--31. 1. "INTERP_FID0_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x10 2.--15. 1. "INTERP_FID0_C3,C3 coefficient for Interpolated Pixel" line.long 0x14 "VPE_REG4," hexmask.long.word 0x14 18.--31. 1. "ANCHOR_FID1_C0,C0 coefficient for Anchor Pixel" hexmask.long.word 0x14 2.--15. 1. "ANCHOR_FID1_C1,C1 coefficient for Anchor Pixel" line.long 0x18 "VPE_REG5," hexmask.long.word 0x18 18.--31. 1. "ANCHOR_FID1_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x18 2.--15. 1. "ANCHOR_FID1_C3,C3 coefficient for Anchor Pixel" line.long 0x1C "VPE_REG6," hexmask.long.word 0x1C 18.--31. 1. "INTERP_FID1_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x1C 2.--15. 1. "INTERP_FID1_C1,C1 coefficient for Interpolated Pixel" line.long 0x20 "VPE_REG7," hexmask.long.word 0x20 18.--31. 1. "INTERP_FID1_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x20 2.--15. 1. "INTERP_FID1_C3,C3 coefficient for Interpolated Pixel" width 0x0B tree.end tree "VPE_CHR_US_INST_2" base ad:0x489D0500 rgroup.long 0x00++0x23 line.long 0x00 "VPE_PID," line.long 0x04 "VPE_REG0," hexmask.long.word 0x04 18.--31. 1. "ANCHOR_FID0_C0,C0 coefficient for Anchor Pixel" bitfld.long 0x04 16.--17. "CFG_MODE," "?,CFG_MODE_1,?,?" hexmask.long.word 0x04 2.--15. 1. "ANCHOR_FID0_C1,C1 coefficient for Anchor Pixel" line.long 0x08 "VPE_REG1," hexmask.long.word 0x08 18.--31. 1. "ANCHOR_FID0_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x08 2.--15. 1. "ANCHOR_FID0_C3,C3 coefficient for Anchor Pixel" line.long 0x0C "VPE_REG2," hexmask.long.word 0x0C 18.--31. 1. "INTERP_FID0_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x0C 2.--15. 1. "INTERP_FID0_C1,C1 coefficient for Interpolated Pixel" line.long 0x10 "VPE_REG3," hexmask.long.word 0x10 18.--31. 1. "INTERP_FID0_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x10 2.--15. 1. "INTERP_FID0_C3,C3 coefficient for Interpolated Pixel" line.long 0x14 "VPE_REG4," hexmask.long.word 0x14 18.--31. 1. "ANCHOR_FID1_C0,C0 coefficient for Anchor Pixel" hexmask.long.word 0x14 2.--15. 1. "ANCHOR_FID1_C1,C1 coefficient for Anchor Pixel" line.long 0x18 "VPE_REG5," hexmask.long.word 0x18 18.--31. 1. "ANCHOR_FID1_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x18 2.--15. 1. "ANCHOR_FID1_C3,C3 coefficient for Anchor Pixel" line.long 0x1C "VPE_REG6," hexmask.long.word 0x1C 18.--31. 1. "INTERP_FID1_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x1C 2.--15. 1. "INTERP_FID1_C1,C1 coefficient for Interpolated Pixel" line.long 0x20 "VPE_REG7," hexmask.long.word 0x20 18.--31. 1. "INTERP_FID1_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x20 2.--15. 1. "INTERP_FID1_C3,C3 coefficient for Interpolated Pixel" width 0x0B tree.end tree "VPE_CSC" base ad:0x489D5700 group.long 0x00++0x17 line.long 0x00 "VPE_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Its is represented as Q3.10 number" line.long 0x04 "VPE_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VPE_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VPE_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VPE_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VPE_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" width 0x0B tree.end tree "VPE_DEI" base ad:0x489D0600 group.long 0x00++0x0F line.long 0x00 "VPE_DEI_REG0," bitfld.long 0x00 31. "PROGRESSIVE_BYPASS,Progressive Mode" "PROGRESSIVE_BYPASS_0,PROGRESSIVE_BYPASS_1" bitfld.long 0x00 30. "FIELD_FLUSH,Field Flush Mode" "FIELD_FLUSH_0,FIELD_FLUSH_1" bitfld.long 0x00 29. "INTERLACE_BYPASS,Interlace Bypass Mode" "INTERLACE_BYPASS_0,INTERLACE_BYPASS_1" newline hexmask.long.word 0x00 16.--26. 1. "HEIGHT,Frame Height" hexmask.long.word 0x00 0.--10. 1. "WIDTH,Frame Width" line.long 0x04 "VPE_DEI_REG1," bitfld.long 0x04 1. "MDT_SPATMAX_BYPASS,Spatial Maximum Filtering Bypass for motion values used in EDI" "MDT_SPATMAX_BYPASS_0,MDT_SPATMAX_BYPASS_1" bitfld.long 0x04 0. "MDT_TEMPMAX_BYPASS,Spatio-temporal Maximum Filtering Bypass for motion valued used in EDI" "MDT_TEMPMAX_BYPASS_0,MDT_TEMPMAX_BYPASS_1" line.long 0x08 "VPE_DEI_REG2," bitfld.long 0x08 28.--31. "MDT_MVSTMAX_COR_THR,This is used for increasing noise robustness" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "MDT_MV_COR_THR,This threshold is for the coring for motion value mv" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. "MDT_SF_SC_THR3,Spatial frequency threshold 3" newline hexmask.long.byte 0x08 8.--15. 1. "MDT_SF_SC_THR2,Spatial frequency threshold 2" hexmask.long.byte 0x08 0.--7. 1. "MDT_SF_SC_THR1,Spatial frequency threshold It is used for adaptive scaling of motion values according to how busy the texture is" line.long 0x0C "VPE_DEI_REG3," hexmask.long.byte 0x0C 24.--31. 1. "EDI_COR_SCALE_FACTOR,Scaling factor for correlation along detected edge" hexmask.long.byte 0x0C 16.--23. 1. "EDI_DIR_COR_LOWER_THR,Lower threshold used for correlation along detected edge" hexmask.long.byte 0x0C 8.--15. 1. "EDI_CHROMA3D_COR_THR,Correlation threshold used in 3D processing for chroma" newline bitfld.long 0x0C 3. "EDI_CHROMA_3D_ENABLE,3D Chroma Enable" "EDI_CHROMA_3D_ENABLE_0,EDI_CHROMA_3D_ENABLE_1" bitfld.long 0x0C 2. "EDI_ENABLE_3D,3D Enable" "EDI_ENABLE_3D_0,EDI_ENABLE_3D_1" bitfld.long 0x0C 0.--1. "EDI_INP_MODE,Interpolation mode" "EDI_INP_MODE_0,EDI_INP_MODE_1,EDI_INP_MODE_2,EDI_INP_MODE_3" group.long 0x20++0x1B line.long 0x00 "VPE_DEI_REG8," bitfld.long 0x00 31. "FMD_WINDOW_ENABLE,Enable FMD operation window" "0,1" hexmask.long.word 0x00 16.--26. 1. "FMD_WINDOW_MAXX,Right boundary of FMD operation window Must be less than width" hexmask.long.word 0x00 0.--10. 1. "FMD_WINDOW_MINX,Left boundary of FMD operation window" line.long 0x04 "VPE_DEI_REG9," hexmask.long.word 0x04 16.--26. 1. "FMD_WINDOW_MAXY,Bottom boundary of FMD operation window Must be less than height/2" hexmask.long.word 0x04 0.--10. 1. "FMD_WINDOW_MINY,Top boundary of FMD operation window" line.long 0x08 "VPE_DEI_REG10," hexmask.long.byte 0x08 24.--31. 1. "FMD_CAF_LINE_THR,CAF threshold used for the pixels from two lines in one field This is the threshold used for combing artifacts detection" hexmask.long.byte 0x08 16.--23. 1. "FMD_CAF_FIELD_THR,CAF threshold used for the pixels from two fields This is the threshold used for combing artifacts detection" bitfld.long 0x08 3. "FMD_BED_ENABLE,Film Mode Bad Edit Detection" "FMD_BED_ENABLE_0,FMD_BED_ENABLE_1" newline bitfld.long 0x08 2. "FMD_JAM_DIR,Film Mode Field Jamming Direction" "FMD_JAM_DIR_0,FMD_JAM_DIR_1" bitfld.long 0x08 1. "FMD_LOCK,Film Mode Field Jamming Direction" "FMD_LOCK_0,FMD_LOCK_1" bitfld.long 0x08 0. "FMD_ENABLE,Enable film mode processing" "FMD_ENABLE_0,FMD_ENABLE_1" line.long 0x0C "VPE_DEI_REG11," hexmask.long.tbyte 0x0C 0.--19. 1. "FMD_CAF_THR,CAF threshold used for leaving film mode: If the combing artifacts is greater than this threshold CAF is detected and thus the state machine will be forced to leave the film mode" line.long 0x10 "VPE_DEI_REG12," bitfld.long 0x10 24. "FMD_RESET,When '1' the film mode detection module needs to be reset by the software" "0,1" hexmask.long.tbyte 0x10 0.--20. 1. "FMD_CAF,Detected combing artifacts" line.long 0x14 "VPE_DEI_REG13," hexmask.long 0x14 0.--27. 1. "FMD_FIELD_DIFF,Field difference (difference between two neighboring fields one top and one bottom)" line.long 0x18 "VPE_DEI_REG14," hexmask.long.tbyte 0x18 0.--19. 1. "FMD_FRAME_DIFF,Frame difference (difference between two top or two bottom fields)" repeat 4. (list 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x10)++0x03 line.long 0x00 "VPE_DEI_REG$1," bitfld.long 0x00 24.--28. "EDI_LUT3,EDI Lookup Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "EDI_LUT2,EDI Lookup Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "EDI_LUT1,EDI Lookup Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "EDI_LUT0,EDI Lookup Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end width 0x0B tree.end tree "VPE_SC" base ad:0x489D0700 group.long 0x00++0x1B line.long 0x00 "VPE_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "CFG_TRIM_0,CFG_TRIM_1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "CFG_Y_PK_EN_0,CFG_Y_PK_EN_1" newline bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by horizontal and vertical scaling" "CFG_INTERLACE_I_0,CFG_INTERLACE_I_1" bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "CFG_HP_BYPASS_0,CFG_HP_BYPASS_1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "CFG_DCM_4X_0,CFG_DCM_4X_1" newline bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "CFG_DCM_2X_0,CFG_DCM_2X_1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "CFG_AUTO_HS_0,CFG_AUTO_HS_1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "CFG_USE_RAV_0,CFG_USE_RAV_1" newline bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "CFG_INVT_FID_0,CFG_INVT_FID_1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is general purpose" "CFG_SC_BYPASS_0,CFG_SC_BYPASS_1" bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "CFG_LINEAR_0,CFG_LINEAR_1" newline bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "CFG_INTERLACE_O_0,CFG_INTERLACE_O_1" line.long 0x04 "VPE_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VPE_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VPE_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VPE_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VPE_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VPE_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VPE_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VPE_CFG_SC9," line.long 0x08 "VPE_CFG_SC10," line.long 0x0C "VPE_CFG_SC11," line.long 0x10 "VPE_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VPE_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VPE_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VPE_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VPE_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VPE_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VPE_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VPE_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VPE_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" width 0x0B tree.end tree "VPE_TOP_LEVEL" base ad:0x489D0000 rgroup.long 0x00++0x03 line.long 0x00 "VPE_CLKC_PID," group.long 0x10++0x03 line.long 0x00 "VPE_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "Force-standby mode,No-standby mode,Same behavior as bit-field value of 0x1,Reserved" newline bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" group.long 0x20++0x1F line.long 0x00 "VPE_INTC_INTR0_STATUS_RAW0," bitfld.long 0x00 18. "DEI_FMD_INT_RAW,DEI Film Mode Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x04 "VPE_INTC_INTR0_STATUS_RAW1," bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 16. "DEI_ERROR_INT_RAW,DEI Error Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x08 "VPE_INTC_INTR0_STATUS_ENA0," bitfld.long 0x08 18. "DEI_FMD_INT_ENA,DEI Film Mode Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x0C "VPE_INTC_INTR0_STATUS_ENA1," bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 16. "DEI_ERROR_INT_ENA,DEI Error Enabled Interrupt Status Read indicates enabled status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "inactive,active Writing 1 will.." line.long 0x10 "VPE_INTC_INTR0_ENA_SET0," bitfld.long 0x10 18. "DEI_FMD_INT_ENA_SET,DEI Film Mode Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x14 "VPE_INTC_INTR0_ENA_SET1," bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 16. "DEI_ERROR_INT_ENA_SET,DEI Error Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x18 "VPE_INTC_INTR0_ENA_CLR0," bitfld.long 0x18 18. "DEI_FMD_INT_ENA_CLR,DEI Film Mode Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." line.long 0x1C "VPE_INTC_INTR0_ENA_CLR1," bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 16. "DEI_ERROR_INT_ENA_CLR,DEI Error Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.." group.long 0xA0++0x03 line.long 0x00 "VPE_INTC_EOI,INTC EOI Register" group.long 0x100++0x07 line.long 0x00 "VPE_CLKC_CLKEN," bitfld.long 0x00 1. "PRIM_DP_EN,Primary Video Data Path Clock Enable" "PRIM_DP_EN_0,PRIM_DP_EN_1" newline bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable" "VPDMA_EN_0,VPDMA_EN_1" line.long 0x04 "VPE_CLKC_RST," bitfld.long 0x04 31. "MAIN_RST,Reset for entire data path in VPE0" "0,1" newline bitfld.long 0x04 1. "PRIM_DP_RST,Primary Video Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" group.long 0x10C++0x03 line.long 0x00 "VPE_CLKC_DPS," bitfld.long 0x00 18. "COLOR_SEPARATE_422,422 Color Separate Select" "COLOR_SEPARATE_422_0,COLOR_SEPARATE_422_1" newline bitfld.long 0x00 16. "CHR_DS_BYPASS,Chroma Downsampler Bypass" "CHR_DS_BYPASS_0,CHR_DS_BYPASS_1" newline bitfld.long 0x00 9.--11. "CHR_DS_SRC_SELECT,Chroma Downsampler Source Select" "CHR_DS_SRC_SELECT_0,CHR_DS_SRC_SELECT_1,?,?,?,?,?,?" newline bitfld.long 0x00 8. "RGB_OUT_SELECT,RGB Output Select" "RGB_OUT_SELECT_0,RGB_OUT_SELECT_1" newline bitfld.long 0x00 0.--2. "CSC_SRC_SELECT,CSC Source Select" "CSC_SRC_SELECT_0,CSC_SRC_SELECT_1,?,?,?,?,?,?" group.long 0x11C++0x03 line.long 0x00 "VPE_RANGE_MAP," bitfld.long 0x00 28. "RANGE_REDUCTION_PRIM_ON,Range Reduction ON for Primary input" "0,1" newline bitfld.long 0x00 6. "RANGE_MAP_PRIM_ON,Range Mapping ON for Primary input" "0,1" newline bitfld.long 0x00 3.--5. "RANGE_MAPUV_PRIM,Range Map UV for Primary input" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "RANGE_MAPY_PRIM,Range Map Y for Primary input" "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VPE_VPDMA" base ad:0x489DD000 rgroup.long 0x00++0x0F line.long 0x00 "VPE_VPDMA_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "FUNC,The funcition of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "VPDMA_LOAD_COMPLETE,This bit will be 1 when the VPDMA state machines image and data image have successfuly been fetched and loaded" "0,1" newline bitfld.long 0x00 6. "VPDMA_ACCESS_TYPE,After bootup this bit states how DMA transaction are setup by lists or through register access" "VPDMA_ACCESS_TYPE_0,VPDMA_ACCESS_TYPE_1" newline bitfld.long 0x00 0.--5. "MINOR,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VPE_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VPE_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located at LIST_ADDR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" newline rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVPE_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated" "LIST_TYPE_0,LIST_TYPE_1,LIST_TYPE_2,?,?,?,?,?" newline hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VPE_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" newline rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" newline rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" newline rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" newline rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" newline rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" newline bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" newline bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" newline bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" newline bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" newline bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VPE_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VPE_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x3F line.long 0x00 "VPE_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VPE_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" newline hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VPE_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" newline hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VPE_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" newline hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VPE_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_GRPX3,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 30. "INT_STAT_GRPX2,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 29. "INT_STAT_GRPX1,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 28. "INT_STAT_SCALER_OUT,The last write DMA transaction has completed for channel scaler_out" "0,1" newline bitfld.long 0x10 19. "INT_STAT_SCALER_CHROMA,The last write DMA transaction has completed for channel scaler_chroma" "0,1" newline bitfld.long 0x10 18. "INT_STAT_SCALER_LUMA,The last write DMA transaction has completed for channel scaler_luma" "0,1" newline bitfld.long 0x10 17. "INT_STAT_HQ_SCALER,The last write DMA transaction has completed for channel hq_scaler" "0,1" newline bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" newline bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" newline bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VPE_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_GRPX3,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 30. "INT_MASK_GRPX2,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_GRPX1,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_SCALER_OUT,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_SCALER_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 18. "INT_MASK_SCALER_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_HQ_SCALER,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VPE_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP1_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip1_mult_portb_src9" "0,1" newline bitfld.long 0x18 30. "INT_STAT_VIP1_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip1_mult_portb_src8" "0,1" newline bitfld.long 0x18 29. "INT_STAT_VIP1_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip1_mult_portb_src7" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP1_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip1_mult_portb_src6" "0,1" newline bitfld.long 0x18 27. "INT_STAT_VIP1_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip1_mult_portb_src5" "0,1" newline bitfld.long 0x18 26. "INT_STAT_VIP1_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip1_mult_portb_src4" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP1_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip1_mult_portb_src3" "0,1" newline bitfld.long 0x18 24. "INT_STAT_VIP1_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip1_mult_portb_src2" "0,1" newline bitfld.long 0x18 23. "INT_STAT_VIP1_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip1_mult_portb_src1" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP1_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip1_mult_portb_src0" "0,1" newline bitfld.long 0x18 21. "INT_STAT_VIP1_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip1_mult_porta_src15" "0,1" newline bitfld.long 0x18 20. "INT_STAT_VIP1_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip1_mult_porta_src14" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP1_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip1_mult_porta_src13" "0,1" newline bitfld.long 0x18 18. "INT_STAT_VIP1_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip1_mult_porta_src12" "0,1" newline bitfld.long 0x18 17. "INT_STAT_VIP1_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip1_mult_porta_src11" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP1_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip1_mult_porta_src10" "0,1" newline bitfld.long 0x18 15. "INT_STAT_VIP1_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip1_mult_porta_src9" "0,1" newline bitfld.long 0x18 14. "INT_STAT_VIP1_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip1_mult_porta_src8" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP1_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip1_mult_porta_src7" "0,1" newline bitfld.long 0x18 12. "INT_STAT_VIP1_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip1_mult_porta_src6" "0,1" newline bitfld.long 0x18 11. "INT_STAT_VIP1_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip1_mult_porta_src5" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip1_mult_porta_src4" "0,1" newline bitfld.long 0x18 9. "INT_STAT_VIP1_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip1_mult_porta_src3" "0,1" newline bitfld.long 0x18 8. "INT_STAT_VIP1_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip1_mult_porta_src2" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip1_mult_porta_src1" "0,1" newline bitfld.long 0x18 6. "INT_STAT_VIP1_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip1_mult_porta_src0" "0,1" line.long 0x1C "VPE_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP1_MULT_PORTB_SRC9,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 30. "INT_MASK_VIP1_MULT_PORTB_SRC8,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 29. "INT_MASK_VIP1_MULT_PORTB_SRC7,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP1_MULT_PORTB_SRC6,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 27. "INT_MASK_VIP1_MULT_PORTB_SRC5,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 26. "INT_MASK_VIP1_MULT_PORTB_SRC4,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP1_MULT_PORTB_SRC3,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 24. "INT_MASK_VIP1_MULT_PORTB_SRC2,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 23. "INT_MASK_VIP1_MULT_PORTB_SRC1,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP1_MULT_PORTB_SRC0,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 21. "INT_MASK_VIP1_MULT_PORTA_SRC15,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 20. "INT_MASK_VIP1_MULT_PORTA_SRC14,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP1_MULT_PORTA_SRC13,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 18. "INT_MASK_VIP1_MULT_PORTA_SRC12,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 17. "INT_MASK_VIP1_MULT_PORTA_SRC11,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP1_MULT_PORTA_SRC10,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 15. "INT_MASK_VIP1_MULT_PORTA_SRC9,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 14. "INT_MASK_VIP1_MULT_PORTA_SRC8,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP1_MULT_PORTA_SRC7,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 12. "INT_MASK_VIP1_MULT_PORTA_SRC6,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 11. "INT_MASK_VIP1_MULT_PORTA_SRC5,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_MULT_PORTA_SRC4,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 9. "INT_MASK_VIP1_MULT_PORTA_SRC3,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 8. "INT_MASK_VIP1_MULT_PORTA_SRC2,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_MULT_PORTA_SRC1,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 6. "INT_MASK_VIP1_MULT_PORTA_SRC0,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VPE_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" newline bitfld.long 0x20 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" newline bitfld.long 0x20 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" newline bitfld.long 0x20 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" newline bitfld.long 0x20 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" newline bitfld.long 0x20 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" newline bitfld.long 0x20 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" newline bitfld.long 0x20 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" newline bitfld.long 0x20 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" newline bitfld.long 0x20 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" newline bitfld.long 0x20 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" newline bitfld.long 0x20 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" newline bitfld.long 0x20 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" newline bitfld.long 0x20 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" newline bitfld.long 0x20 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" newline bitfld.long 0x20 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" newline bitfld.long 0x20 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" newline bitfld.long 0x20 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" newline bitfld.long 0x20 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" newline bitfld.long 0x20 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" newline bitfld.long 0x20 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" newline bitfld.long 0x20 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x24 "VPE_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VPE_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" newline bitfld.long 0x28 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" newline bitfld.long 0x28 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x28 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" newline bitfld.long 0x28 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" newline bitfld.long 0x28 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x28 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" newline bitfld.long 0x28 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" newline bitfld.long 0x28 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x28 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" newline bitfld.long 0x28 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" newline bitfld.long 0x28 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x28 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" newline bitfld.long 0x28 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" newline bitfld.long 0x28 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x28 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" newline bitfld.long 0x28 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x28 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" newline bitfld.long 0x28 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" newline bitfld.long 0x28 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x28 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" newline bitfld.long 0x28 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x28 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" newline bitfld.long 0x28 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" newline bitfld.long 0x28 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x28 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" newline bitfld.long 0x28 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x28 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" newline bitfld.long 0x28 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x2C "VPE_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VPE_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" newline bitfld.long 0x30 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" newline bitfld.long 0x30 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x30 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" newline bitfld.long 0x30 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" newline bitfld.long 0x30 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x30 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" newline bitfld.long 0x30 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" newline bitfld.long 0x30 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x30 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" newline bitfld.long 0x30 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" newline bitfld.long 0x30 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x30 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" newline bitfld.long 0x30 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" newline bitfld.long 0x30 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x30 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" newline bitfld.long 0x30 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" newline bitfld.long 0x30 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x30 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" newline bitfld.long 0x30 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" newline bitfld.long 0x30 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x30 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" newline bitfld.long 0x30 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" newline bitfld.long 0x30 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x30 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" newline bitfld.long 0x30 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" newline bitfld.long 0x30 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x30 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" newline bitfld.long 0x30 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" newline bitfld.long 0x30 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x30 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" newline bitfld.long 0x30 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x34 "VPE_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VPE_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x38 31. "INT_STAT_TRANSCODE2_CHROMA,The last write DMA transaction has completed for channel transcode2_chroma" "0,1" newline bitfld.long 0x38 30. "INT_STAT_TRANSCODE2_LUMA,The last write DMA transaction has completed for channel transcode2_luma" "0,1" newline bitfld.long 0x38 29. "INT_STAT_TRANSCODE1_CHROMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 28. "INT_STAT_TRANSCODE1_LUMA,The last write DMA transaction has completed for channel transcode1_luma" "0,1" newline bitfld.long 0x38 27. "INT_STAT_AUX_IN,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 26. "INT_STAT_PIP_FRAME,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 25. "INT_STAT_POST_COMP_WR,The last write DMA transaction has completed for channel post_comp_wr" "0,1" newline bitfld.long 0x38 24. "INT_STAT_VBI_SD_VENC,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x38 22. "INT_STAT_NF_LAST_CHROMA,The last write DMA transaction has completed for channel nf_last_chroma" "0,1" newline bitfld.long 0x38 21. "INT_STAT_NF_LAST_LUMA,The last write DMA transaction has completed for channel nf_last_luma" "0,1" newline bitfld.long 0x38 20. "INT_STAT_NF_WRITE_CHROMA,The last write DMA transaction has completed for channel nf_write_chroma" "0,1" newline bitfld.long 0x38 19. "INT_STAT_NF_WRITE_LUMA,The last write DMA transaction has completed for channel nf_write_luma" "0,1" newline bitfld.long 0x38 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" newline bitfld.long 0x38 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x38 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" newline bitfld.long 0x38 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x38 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" newline bitfld.long 0x38 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x38 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" newline bitfld.long 0x38 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x38 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" newline bitfld.long 0x38 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x38 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" newline bitfld.long 0x38 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x38 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x3C "VPE_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x3C 31. "INT_MASK_TRANSCODE2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 30. "INT_MASK_TRANSCODE2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_TRANSCODE1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_TRANSCODE1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_AUX_IN,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 26. "INT_MASK_PIP_FRAME,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_POST_COMP_WR,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 24. "INT_MASK_VBI_SD_VENC,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_NF_LAST_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_NF_LAST_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 20. "INT_MASK_NF_WRITE_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_NF_WRITE_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x3C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x78++0x17 line.long 0x00 "VPE_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x00 31. "INT_STAT_GRPX1_DATA,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 30. "INT_STAT_COMP_WRBK,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 29. "INT_STAT_SC_OUT,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 20. "INT_STAT_SC_IN_LUMA,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 19. "INT_STAT_SC_IN_CHROMA,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 18. "INT_STAT_PIP_WRBK,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 17. "INT_STAT_DEI_SC_OUT,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x00 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x04 "VPE_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x04 31. "INT_MASK_GRPX1_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 30. "INT_MASK_COMP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 29. "INT_MASK_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 20. "INT_MASK_SC_IN_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 19. "INT_MASK_SC_IN_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 18. "INT_MASK_PIP_WRBK,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 17. "INT_MASK_DEI_SC_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x04 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x08 "VPE_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x08 29. "INT_STAT_VIP2_ANC_B,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 28. "INT_STAT_VIP2_ANC_A,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 27. "INT_STAT_VIP1_ANC_B,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 26. "INT_STAT_VIP1_ANC_A,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 25. "INT_STAT_TRANS2_LUMA,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 24. "INT_STAT_TRANS2_CHROMA,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 23. "INT_STAT_TRANS1_LUMA,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 22. "INT_STAT_TRANS1_CHROMA,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 21. "INT_STAT_HDMI_WRBK_OUT,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 20. "INT_STAT_VPI_CTL,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 19. "INT_STAT_VBI_SDVENC,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 17. "INT_STAT_NF_420_UV_OUT,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 16. "INT_STAT_NF_420_Y_OUT,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 15. "INT_STAT_NF_420_UV_IN,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 14. "INT_STAT_NF_420_Y_IN,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 13. "INT_STAT_NF_422_IN,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 12. "INT_STAT_GRPX3_ST,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 11. "INT_STAT_GRPX2_ST,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 10. "INT_STAT_GRPX1_ST,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 9. "INT_STAT_VIP2_UP_UV,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 8. "INT_STAT_VIP2_UP_Y,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 7. "INT_STAT_VIP2_LO_UV,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 6. "INT_STAT_VIP2_LO_Y,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 5. "INT_STAT_VIP1_UP_UV,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 4. "INT_STAT_VIP1_UP_Y,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 3. "INT_STAT_VIP1_LO_UV,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 2. "INT_STAT_VIP1_LO_Y,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 1. "INT_STAT_GRPX3_DATA,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x08 0. "INT_STAT_GRPX2_DATA,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x0C "VPE_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x0C 29. "INT_MASK_VIP2_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 28. "INT_MASK_VIP2_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 27. "INT_MASK_VIP1_ANC_B,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 26. "INT_MASK_VIP1_ANC_A,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 25. "INT_MASK_TRANS2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 24. "INT_MASK_TRANS2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 23. "INT_MASK_TRANS1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 22. "INT_MASK_TRANS1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 21. "INT_MASK_HDMI_WRBK_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 20. "INT_MASK_VPI_CTL,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 19. "INT_MASK_VBI_SDVENC,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 17. "INT_MASK_NF_420_UV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 16. "INT_MASK_NF_420_Y_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 15. "INT_MASK_NF_420_UV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 14. "INT_MASK_NF_420_Y_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 13. "INT_MASK_NF_422_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 12. "INT_MASK_GRPX3_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 11. "INT_MASK_GRPX2_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 10. "INT_MASK_GRPX1_ST,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 9. "INT_MASK_VIP2_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 8. "INT_MASK_VIP2_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 7. "INT_MASK_VIP2_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 6. "INT_MASK_VIP2_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 5. "INT_MASK_VIP1_UP_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 4. "INT_MASK_VIP1_UP_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 3. "INT_MASK_VIP1_LO_UV,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 2. "INT_MASK_VIP1_LO_Y,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 1. "INT_MASK_GRPX3_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x0C 0. "INT_MASK_GRPX2_DATA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x10 "VPE_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" newline bitfld.long 0x10 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x10 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x10 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x10 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" newline bitfld.long 0x10 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x10 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" newline bitfld.long 0x10 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x10 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x10 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x10 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" newline bitfld.long 0x10 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x10 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" newline bitfld.long 0x10 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x10 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x10 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x10 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x10 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x10 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x14 "VPE_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" group.long 0x200++0xD3 line.long 0x00 "VPE_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VPE_PERF_MON1,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VPE_PERF_MON2,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VPE_PERF_MON3,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VPE_PERF_MON4,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VPE_PERF_MON5,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x14 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x18 "VPE_PERF_MON6,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x18 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x18 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x18 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x18 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x18 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x18 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x1C "VPE_PERF_MON7,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x1C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x1C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x1C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x1C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x1C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x1C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x20 "VPE_PERF_MON8,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x20 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x20 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x20 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x20 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x20 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x20 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x24 "VPE_PERF_MON9,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x24 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x24 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x24 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x24 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x24 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x24 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x28 "VPE_PERF_MON10,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x28 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x28 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x28 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x28 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x28 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x28 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x2C "VPE_PERF_MON11,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x2C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x2C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x2C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x2C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x2C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x2C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x30 "VPE_PERF_MON12,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x30 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x30 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x30 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x30 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x30 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x30 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x34 "VPE_PERF_MON13,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x34 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x34 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x34 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x34 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x34 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x34 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x38 "VPE_PERF_MON14,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x38 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x38 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x38 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x38 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x38 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x38 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x3C "VPE_PERF_MON15,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x3C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x3C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x3C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x3C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x3C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x3C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x40 "VPE_PERF_MON16,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x40 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x40 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x40 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x40 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x40 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x40 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x44 "VPE_PERF_MON17,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x44 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x44 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x44 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x44 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x44 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x44 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x48 "VPE_PERF_MON18,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x48 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x48 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x48 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x48 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x48 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x48 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x4C "VPE_PERF_MON19,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x4C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x4C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x4C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x4C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x4C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x4C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x50 "VPE_PERF_MON20,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x50 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x50 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x50 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x50 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x50 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x50 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x54 "VPE_PERF_MON21,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x54 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x54 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x54 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x54 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x54 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x54 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x58 "VPE_PERF_MON22,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x58 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x58 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x58 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x58 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x58 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x58 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x5C "VPE_PERF_MON23,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x5C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x5C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x5C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x5C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x5C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x5C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x60 "VPE_PERF_MON24,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x60 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x60 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x60 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x60 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x60 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x60 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x64 "VPE_PERF_MON25,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x64 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x64 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x64 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x64 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x64 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x64 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x68 "VPE_PERF_MON26,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x68 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x68 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x68 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x68 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x68 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x68 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x6C "VPE_PERF_MON27,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x6C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x6C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x6C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x6C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x6C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x6C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x70 "VPE_PERF_MON28,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x70 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x70 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x70 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x70 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x70 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x70 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x74 "VPE_PERF_MON29,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x74 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x74 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x74 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x74 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x74 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x74 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x78 "VPE_PERF_MON30,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x78 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x78 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x78 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x78 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x78 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x78 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x7C "VPE_PERF_MON31,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x7C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x7C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x7C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x7C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x7C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x7C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x80 "VPE_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x80 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x80 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x80 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x80 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x80 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x80 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x84 "VPE_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x84 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x84 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x84 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x84 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x84 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x84 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x88 "VPE_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x88 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x88 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x88 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x88 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x88 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x88 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x8C "VPE_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x8C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x8C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x8C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x8C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x8C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x8C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x90 "VPE_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x90 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x90 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x90 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x90 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x90 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x90 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x94 "VPE_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x94 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x94 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x94 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x94 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x94 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x94 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x98 "VPE_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x98 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x98 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x98 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x98 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x98 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x98 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x9C "VPE_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x9C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0x9C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x9C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x9C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x9C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x9C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xA0 "VPE_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xA0 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xA0 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA0 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xA0 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA0 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xA0 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xA4 "VPE_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xA4 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xA4 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA4 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xA4 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA4 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xA4 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xA8 "VPE_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xA8 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xA8 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA8 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xA8 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xA8 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xA8 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xAC "VPE_PERF_MON43,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xAC 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xAC 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xAC 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xAC 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xAC 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xAC 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xB0 "VPE_PERF_MON44,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xB0 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xB0 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB0 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xB0 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB0 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xB0 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xB4 "VPE_PERF_MON45,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xB4 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xB4 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB4 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xB4 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB4 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xB4 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xB8 "VPE_PERF_MON46,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xB8 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xB8 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB8 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xB8 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xB8 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xB8 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xBC "VPE_PERF_MON47,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xBC 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xBC 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xBC 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xBC 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xBC 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xBC 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xC0 "VPE_PERF_MON48,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xC0 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xC0 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xC0 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xC0 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xC0 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xC0 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xC4 "VPE_PERF_MON49,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xC4 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "Running Average,Minimum Value,Maximum Value,Last Value" newline bitfld.long 0xC4 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0xC4 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xC4 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0xC4 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xC4 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xC8 "VPE_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xC8 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0xC8 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0xC8 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xC8 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0xC8 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xC8 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xCC "VPE_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xCC 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0xCC 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0xCC 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xCC 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0xCC 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xCC 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0xD0 "VPE_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0xD0 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0xD0 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0xD0 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0xD0 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0xD0 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0xD0 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x300++0x17 line.long 0x00 "VPE_PRI_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" line.long 0x04 "VPE_PRI_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x08 "VPE_PRI_FLD1_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x0C "VPE_PRI_FLD1_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" newline hexmask.long.byte 0x0C 0.--7. 1. "3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines.," line.long 0x10 "VPE_PRI_FLD2_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x14 "VPE_PRI_FLD2_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x14 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" group.long 0x330++0x03 line.long 0x00 "VPE_PRI_MV0_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x33C++0x03 line.long 0x00 "VPE_PRI_MV_OUT_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x390++0x07 line.long 0x00 "VPE_VIP0_UP_Y_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x04 "VPE_VIP0_UP_UV_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x3D0++0x03 line.long 0x00 "VPE_VPI_CTL_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" width 0x0B tree.end tree.end tree "Watchdog_Timer" base ad:0x4AE14000 rgroup.long 0x00++0x03 line.long 0x00 "WIDR,IP revision identifier" group.long 0x10++0x27 line.long 0x00 "WDSC,This register controls the various parameters of the L4 interface" bitfld.long 0x00 5. "EMUFREE,Emulation mode - Disabled" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 3.--4. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_r" line.long 0x04 "WDST,This register provides status information about the module" bitfld.long 0x04 0. "RESETDONE,Internal module reset monitoring - Ongoing" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "WISR,This register shows which interrupt events are pending inside the module" bitfld.long 0x08 1. "DLY_IT_FLAG,Pending delay interrupt status" "DLY_IT_FLAG_0_w,DLY_IT_FLAG_1_r" bitfld.long 0x08 0. "OVF_IT_FLAG,Pending overflow interrupt status" "OVF_IT_FLAG_0_w,OVF_IT_FLAG_1_r" line.long 0x0C "WIER,This register controls (enable/disable) the interrupt events" bitfld.long 0x0C 1. "DLY_IT_ENA,Delay interrupt enable/disable - Disabled" "DLY_IT_ENA_0,DLY_IT_ENA_1" bitfld.long 0x0C 0. "OVF_IT_ENA,Overflow interrupt enable/disable - Disabled" "OVF_IT_ENA_0,OVF_IT_ENA_1" line.long 0x10 "WWER,This register controls (enable/disable) the wake-up events" bitfld.long 0x10 1. "DLY_WK_ENA,Delay wake-up enable - Disabled" "DLY_WK_ENA_0,DLY_WK_ENA_1" bitfld.long 0x10 0. "OVF_WK_ENA,Overflow wake-up enable - Disabled" "OVF_WK_ENA_0,OVF_WK_ENA_1" line.long 0x14 "WCLR,This register controls the prescaler stage of the counter" bitfld.long 0x14 5. "PRE,Prescaler enable/disable configuration - Disabled" "PRE_0,PRE_1" bitfld.long 0x14 2.--4. "PTV,Prescaler value The timer counter is prescaled with the value: 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" line.long 0x18 "WCRR,This register holds the value of the internal counter" line.long 0x1C "WLDR,This register holds the timer load value" line.long 0x20 "WTGR,Writing a different value than the one already written in this register does a watchdog counter reload" line.long 0x24 "WWPS,This register contains the write posting bits for all writeable functional registers" bitfld.long 0x24 5. "W_PEND_WDLY,Write pending for registerWDLY - Ready" "W_PEND_WDLY_0_r,W_PEND_WDLY_1_r" bitfld.long 0x24 4. "W_PEND_WSPR,Write pending for registerWSPR - Ready" "W_PEND_WSPR_0_r,W_PEND_WSPR_1_r" bitfld.long 0x24 3. "W_PEND_WTGR,Write pending for registerWTGR - Ready" "W_PEND_WTGR_0_r,W_PEND_WTGR_1_r" bitfld.long 0x24 2. "W_PEND_WLDR,Write pending for registerWLDR - Ready" "W_PEND_WLDR_0_r,W_PEND_WLDR_1_r" newline bitfld.long 0x24 1. "W_PEND_WCRR,Write pending for registerWCRR - Ready" "W_PEND_WCRR_0_r,W_PEND_WCRR_1_r" bitfld.long 0x24 0. "W_PEND_WCLR,Write pending for registerWCLR - Ready" "W_PEND_WCLR_0_r,W_PEND_WCLR_1_r" group.long 0x44++0x07 line.long 0x00 "WDLY,This register holds the delay value that controls the internal pre-overflow event detection" line.long 0x04 "WSPR,This register holds the start-stop value that controls the internal start-stop FSM" group.long 0x50++0x17 line.long 0x00 "WIRQEOI,Software End Of Interrupt" bitfld.long 0x00 0. "LINE_NUMBER,EOI for interrupt output line Reads always 0 (no EOI memory)" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "WIRQSTATRAW,IRQ unmasked status. status set per-event raw interrupt status vector. line 0" bitfld.long 0x04 1. "EVENT_DLY,Settable raw status for delay event - Read_0" "EVENT_DLY_0_w,EVENT_DLY_1_r" bitfld.long 0x04 0. "EVENT_OVF,Settable raw status for overflow event - Read_0" "EVENT_OVF_0_w,EVENT_OVF_1_r" line.long 0x08 "WIRQSTAT,IRQ masked status. status clear per-event enabled interrupt status vector. line 0" bitfld.long 0x08 1. "EVENT_DLY,Clearable enabled status for delay event - Read_0" "EVENT_DLY_0_w,EVENT_DLY_1_r" bitfld.long 0x08 0. "EVENT_OVF,Clearable enabled status for overflow event - Read_0" "EVENT_OVF_0_w,EVENT_OVF_1_r" line.long 0x0C "WIRQENSET,IRQ enable set per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 1. "ENABLE_DLY,Enable for delay event - Read_0" "ENABLE_DLY_0_w,ENABLE_DLY_1_r" bitfld.long 0x0C 0. "ENABLE_OVF,Enable for overflow event - Read_0" "ENABLE_OVF_0_w,ENABLE_OVF_1_r" line.long 0x10 "WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector. line 0" bitfld.long 0x10 1. "ENABLE_DLY,Enable for delay event - Read_0" "ENABLE_DLY_0_w,ENABLE_DLY_1_r" bitfld.long 0x10 0. "ENABLE_OVF,Enable for overflow event - Read_0" "ENABLE_OVF_0_w,ENABLE_OVF_1_r" line.long 0x14 "WIRQWAKEEN,This register controls (enable/disable) the wake-up events" bitfld.long 0x14 1. "DLY_WK_ENA,Enable delay wake-up - Disabled" "DLY_WK_ENA_0,DLY_WK_ENA_1" bitfld.long 0x14 0. "OVF_WK_ENA,Enable overflow wakeup - Disabled" "OVF_WK_ENA_0,OVF_WK_ENA_1" width 0x0B tree.end autoindent.off newline